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PowerPC problem building gold with clang
[thirdparty/binutils-gdb.git] / include / opcode / aarch64.h
CommitLineData
a06ea964
NC		 1/* AArch64 assembler/disassembler support.
2
b3adc24a 3 Copyright (C) 2009-2020 Free Software Foundation, Inc.
a06ea964
NC		 4 Contributed by ARM Ltd.
5
6 This file is part of GNU Binutils.
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the license, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING3. If not,
20 see <http://www.gnu.org/licenses/>. */
21
22#ifndef OPCODE_AARCH64_H
23#define OPCODE_AARCH64_H
24
25#include "bfd.h"
26#include "bfd_stdint.h"
27#include <assert.h>
28#include <stdlib.h>
29
d3e12b29
YQ		 30#ifdef __cplusplus
31extern "C" {
32#endif
33
a06ea964
NC		 34/* The offset for pc-relative addressing is currently defined to be 0. */
35#define AARCH64_PCREL_OFFSET 0
36
37typedef uint32_t aarch64_insn;
38
39/* The following bitmasks control CPU features. */
359157df
AC		 40#define AARCH64_FEATURE_V8 (1ULL << 0) /* All processors. */
41#define AARCH64_FEATURE_V8_6 (1ULL << 1) /* ARMv8.6 processors. */
42#define AARCH64_FEATURE_BFLOAT16 (1ULL << 2) /* Bfloat16 insns. */
95830c98 43#define AARCH64_FEATURE_V8_A (1ULL << 3) /* Armv8-A processors. */
359157df
AC		 44#define AARCH64_FEATURE_SVE2 (1ULL << 4) /* SVE2 instructions. */
45#define AARCH64_FEATURE_V8_2 (1ULL << 5) /* ARMv8.2 processors. */
46#define AARCH64_FEATURE_V8_3 (1ULL << 6) /* ARMv8.3 processors. */
47#define AARCH64_FEATURE_SVE2_AES (1ULL << 7)
48#define AARCH64_FEATURE_SVE2_BITPERM (1ULL << 8)
49#define AARCH64_FEATURE_SVE2_SM4 (1ULL << 9)
50#define AARCH64_FEATURE_SVE2_SHA3 (1ULL << 10)
51#define AARCH64_FEATURE_V8_4 (1ULL << 11) /* ARMv8.4 processors. */
95830c98 52#define AARCH64_FEATURE_V8_R (1ULL << 12) /* Armv8-R processors. */
8926e54e 53#define AARCH64_FEATURE_V8_7 (1ULL << 13) /* Armv8.7 processors. */
dd4a72c8 54#define AARCH64_FEATURE_CSRE (1ULL << 14) /* CSRE feature. */
359157df
AC		 55#define AARCH64_FEATURE_FP (1ULL << 17) /* FP instructions. */
56#define AARCH64_FEATURE_SIMD (1ULL << 18) /* SIMD instructions. */
57#define AARCH64_FEATURE_CRC (1ULL << 19) /* CRC instructions. */
58#define AARCH64_FEATURE_LSE (1ULL << 20) /* LSE instructions. */
59#define AARCH64_FEATURE_PAN (1ULL << 21) /* PAN instructions. */
60#define AARCH64_FEATURE_LOR (1ULL << 22) /* LOR instructions. */
61#define AARCH64_FEATURE_RDMA (1ULL << 23) /* v8.1 SIMD instructions. */
62#define AARCH64_FEATURE_V8_1 (1ULL << 24) /* v8.1 features. */
63#define AARCH64_FEATURE_F16 (1ULL << 25) /* v8.2 FP16 instructions. */
64#define AARCH64_FEATURE_RAS (1ULL << 26) /* RAS Extensions. */
65#define AARCH64_FEATURE_PROFILE (1ULL << 27) /* Statistical Profiling. */
66#define AARCH64_FEATURE_SVE (1ULL << 28) /* SVE instructions. */
67#define AARCH64_FEATURE_RCPC (1ULL << 29) /* RCPC instructions. */
68#define AARCH64_FEATURE_COMPNUM (1ULL << 30) /* Complex # instructions. */
69#define AARCH64_FEATURE_DOTPROD (1ULL << 31) /* Dot Product instructions. */
70#define AARCH64_FEATURE_SM4 (1ULL << 32) /* SM3 & SM4 instructions. */
71#define AARCH64_FEATURE_SHA2 (1ULL << 33) /* SHA2 instructions. */
72#define AARCH64_FEATURE_SHA3 (1ULL << 34) /* SHA3 instructions. */
73#define AARCH64_FEATURE_AES (1ULL << 35) /* AES instructions. */
74#define AARCH64_FEATURE_F16_FML (1ULL << 36) /* v8.2 FP16FML ins. */
75#define AARCH64_FEATURE_V8_5 (1ULL << 37) /* ARMv8.5 processors. */
76#define AARCH64_FEATURE_FLAGMANIP (1ULL << 38) /* Flag Manipulation insns. */
77#define AARCH64_FEATURE_FRINTTS (1ULL << 39) /* FRINT[32,64][Z,X] insns. */
78#define AARCH64_FEATURE_SB (1ULL << 40) /* SB instruction. */
79#define AARCH64_FEATURE_PREDRES (1ULL << 41) /* Execution and Data Prediction Restriction instructions. */
80#define AARCH64_FEATURE_CVADP (1ULL << 42) /* DC CVADP. */
81#define AARCH64_FEATURE_RNG (1ULL << 43) /* Random Number instructions. */
82#define AARCH64_FEATURE_BTI (1ULL << 44) /* BTI instructions. */
83#define AARCH64_FEATURE_SCXTNUM (1ULL << 45) /* SCXTNUM_ELx. */
84#define AARCH64_FEATURE_ID_PFR2 (1ULL << 46) /* ID_PFR2 instructions. */
85#define AARCH64_FEATURE_SSBS (1ULL << 47) /* SSBS mechanism enabled. */
86#define AARCH64_FEATURE_MEMTAG (1ULL << 48) /* Memory Tagging Extension. */
87#define AARCH64_FEATURE_TME (1ULL << 49) /* Transactional Memory Extension. */
88#define AARCH64_FEATURE_I8MM (1ULL << 52) /* Matrix Multiply instructions. */
89#define AARCH64_FEATURE_F32MM (1ULL << 53)
90#define AARCH64_FEATURE_F64MM (1ULL << 54)
7ce2460a 91
2dc4b12f
JB		 92/* Crypto instructions are the combination of AES and SHA2. */
93#define AARCH64_FEATURE_CRYPTO (AARCH64_FEATURE_SHA2 | AARCH64_FEATURE_AES)
94
a06ea964
NC		 95/* Architectures are the sum of the base and extensions. */
96#define AARCH64_ARCH_V8 AARCH64_FEATURE (AARCH64_FEATURE_V8, \
95830c98
AC		 97 AARCH64_FEATURE_V8_A \
98 | AARCH64_FEATURE_FP \
a06ea964 99 | AARCH64_FEATURE_SIMD)
1924ff75
SN		 100#define AARCH64_ARCH_V8_1 AARCH64_FEATURE (AARCH64_ARCH_V8, \
101 AARCH64_FEATURE_CRC \
250aafa4 102 | AARCH64_FEATURE_V8_1 \
88f0ea34
MW		 103 | AARCH64_FEATURE_LSE \
104 | AARCH64_FEATURE_PAN \
105 | AARCH64_FEATURE_LOR \
106 | AARCH64_FEATURE_RDMA)
1924ff75 107#define AARCH64_ARCH_V8_2 AARCH64_FEATURE (AARCH64_ARCH_V8_1, \
acb787b0 108 AARCH64_FEATURE_V8_2 \
1924ff75
SN		 109 | AARCH64_FEATURE_RAS)
110#define AARCH64_ARCH_V8_3 AARCH64_FEATURE (AARCH64_ARCH_V8_2, \
d74d4880 111 AARCH64_FEATURE_V8_3 \
f482d304
RS		 112 | AARCH64_FEATURE_RCPC \
113 | AARCH64_FEATURE_COMPNUM)
b6b9ca0c 114#define AARCH64_ARCH_V8_4 AARCH64_FEATURE (AARCH64_ARCH_V8_3, \
981b557a 115 AARCH64_FEATURE_V8_4 \
d0f7791c
TC		 116 | AARCH64_FEATURE_DOTPROD \
117 | AARCH64_FEATURE_F16_FML)
70d56181 118#define AARCH64_ARCH_V8_5 AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
13c60ad7
SD		 119 AARCH64_FEATURE_V8_5 \
120 | AARCH64_FEATURE_FLAGMANIP \
68dfbb92 121 | AARCH64_FEATURE_FRINTTS \
2ac435d4 122 | AARCH64_FEATURE_SB \
3fd229a4 123 | AARCH64_FEATURE_PREDRES \
ff605452 124 | AARCH64_FEATURE_CVADP \
a97330e7
SD		 125 | AARCH64_FEATURE_BTI \
126 | AARCH64_FEATURE_SCXTNUM \
104fefee
SD		 127 | AARCH64_FEATURE_ID_PFR2 \
128 | AARCH64_FEATURE_SSBS)
8ae2d3d9 129#define AARCH64_ARCH_V8_6 AARCH64_FEATURE (AARCH64_ARCH_V8_5, \
df678013 130 AARCH64_FEATURE_V8_6 \
8382113f
MM		 131 | AARCH64_FEATURE_BFLOAT16 \
132 | AARCH64_FEATURE_I8MM)
8926e54e
PW		 133#define AARCH64_ARCH_V8_7 AARCH64_FEATURE (AARCH64_ARCH_V8_6, \
134 AARCH64_FEATURE_V8_7)
95830c98
AC		 135#define AARCH64_ARCH_V8_R (AARCH64_FEATURE (AARCH64_ARCH_V8_4, \
136 AARCH64_FEATURE_V8_R) \
137 & ~(AARCH64_FEATURE_V8_A | AARCH64_FEATURE_LOR))
88f0ea34 138
a06ea964
NC		 139#define AARCH64_ARCH_NONE AARCH64_FEATURE (0, 0)
140#define AARCH64_ANY AARCH64_FEATURE (-1, 0) /* Any basic core. */
141
142/* CPU-specific features. */
21b81e67 143typedef unsigned long long aarch64_feature_set;
a06ea964 144
93d8990c
SN		 145#define AARCH64_CPU_HAS_ALL_FEATURES(CPU,FEAT) \
146 ((~(CPU) & (FEAT)) == 0)
147
148#define AARCH64_CPU_HAS_ANY_FEATURES(CPU,FEAT) \
a06ea964
NC		 149 (((CPU) & (FEAT)) != 0)
150
93d8990c
SN		 151#define AARCH64_CPU_HAS_FEATURE(CPU,FEAT) \
152 AARCH64_CPU_HAS_ALL_FEATURES (CPU,FEAT)
153
a06ea964
NC		 154#define AARCH64_MERGE_FEATURE_SETS(TARG,F1,F2) \
155 do \
156 { \
157 (TARG) = (F1) | (F2); \
158 } \
159 while (0)
160
161#define AARCH64_CLEAR_FEATURE(TARG,F1,F2) \
162 do \
163 { \
164 (TARG) = (F1) &~ (F2); \
165 } \
166 while (0)
167
168#define AARCH64_FEATURE(core,coproc) ((core) | (coproc))
169
a06ea964
NC		 170enum aarch64_operand_class
171{
172 AARCH64_OPND_CLASS_NIL,
173 AARCH64_OPND_CLASS_INT_REG,
174 AARCH64_OPND_CLASS_MODIFIED_REG,
175 AARCH64_OPND_CLASS_FP_REG,
176 AARCH64_OPND_CLASS_SIMD_REG,
177 AARCH64_OPND_CLASS_SIMD_ELEMENT,
178 AARCH64_OPND_CLASS_SISD_REG,
179 AARCH64_OPND_CLASS_SIMD_REGLIST,
f11ad6bc
RS		 180 AARCH64_OPND_CLASS_SVE_REG,
181 AARCH64_OPND_CLASS_PRED_REG,
a06ea964
NC		 182 AARCH64_OPND_CLASS_ADDRESS,
183 AARCH64_OPND_CLASS_IMMEDIATE,
184 AARCH64_OPND_CLASS_SYSTEM,
68a64283 185 AARCH64_OPND_CLASS_COND,
a06ea964
NC		 186};
187
188/* Operand code that helps both parsing and coding.
189 Keep AARCH64_OPERANDS synced. */
190
191enum aarch64_opnd
192{
193 AARCH64_OPND_NIL, /* no operand---MUST BE FIRST!*/
194
195 AARCH64_OPND_Rd, /* Integer register as destination. */
196 AARCH64_OPND_Rn, /* Integer register as source. */
197 AARCH64_OPND_Rm, /* Integer register as source. */
198 AARCH64_OPND_Rt, /* Integer register used in ld/st instructions. */
199 AARCH64_OPND_Rt2, /* Integer register used in ld/st pair instructions. */
bd7ceb8d 200 AARCH64_OPND_Rt_SP, /* Integer Rt or SP used in STG instructions. */
a06ea964
NC		 201 AARCH64_OPND_Rs, /* Integer register used in ld/st exclusive. */
202 AARCH64_OPND_Ra, /* Integer register used in ddp_3src instructions. */
203 AARCH64_OPND_Rt_SYS, /* Integer register used in system instructions. */
204
205 AARCH64_OPND_Rd_SP, /* Integer Rd or SP. */
206 AARCH64_OPND_Rn_SP, /* Integer Rn or SP. */
c84364ec 207 AARCH64_OPND_Rm_SP, /* Integer Rm or SP. */
ee804238 208 AARCH64_OPND_PAIRREG, /* Paired register operand. */
a06ea964
NC		 209 AARCH64_OPND_Rm_EXT, /* Integer Rm extended. */
210 AARCH64_OPND_Rm_SFT, /* Integer Rm shifted. */
211
212 AARCH64_OPND_Fd, /* Floating-point Fd. */
213 AARCH64_OPND_Fn, /* Floating-point Fn. */
214 AARCH64_OPND_Fm, /* Floating-point Fm. */
215 AARCH64_OPND_Fa, /* Floating-point Fa. */
216 AARCH64_OPND_Ft, /* Floating-point Ft. */
217 AARCH64_OPND_Ft2, /* Floating-point Ft2. */
218
219 AARCH64_OPND_Sd, /* AdvSIMD Scalar Sd. */
220 AARCH64_OPND_Sn, /* AdvSIMD Scalar Sn. */
221 AARCH64_OPND_Sm, /* AdvSIMD Scalar Sm. */
222
f42f1a1d 223 AARCH64_OPND_Va, /* AdvSIMD Vector Va. */
a06ea964
NC		 224 AARCH64_OPND_Vd, /* AdvSIMD Vector Vd. */
225 AARCH64_OPND_Vn, /* AdvSIMD Vector Vn. */
226 AARCH64_OPND_Vm, /* AdvSIMD Vector Vm. */
227 AARCH64_OPND_VdD1, /* AdvSIMD <Vd>.D[1]; for FMOV only. */
228 AARCH64_OPND_VnD1, /* AdvSIMD <Vn>.D[1]; for FMOV only. */
229 AARCH64_OPND_Ed, /* AdvSIMD Vector Element Vd. */
230 AARCH64_OPND_En, /* AdvSIMD Vector Element Vn. */
231 AARCH64_OPND_Em, /* AdvSIMD Vector Element Vm. */
369c9167
TC		 232 AARCH64_OPND_Em16, /* AdvSIMD Vector Element Vm restricted to V0 - V15 when
233 qualifier is S_H. */
a06ea964
NC		 234 AARCH64_OPND_LVn, /* AdvSIMD Vector register list used in e.g. TBL. */
235 AARCH64_OPND_LVt, /* AdvSIMD Vector register list used in ld/st. */
236 AARCH64_OPND_LVt_AL, /* AdvSIMD Vector register list for loading single
237 structure to all lanes. */
238 AARCH64_OPND_LEt, /* AdvSIMD Vector Element list. */
239
a6a51754
RL		 240 AARCH64_OPND_CRn, /* Co-processor register in CRn field. */
241 AARCH64_OPND_CRm, /* Co-processor register in CRm field. */
a06ea964
NC		 242
243 AARCH64_OPND_IDX, /* AdvSIMD EXT index operand. */
f42f1a1d 244 AARCH64_OPND_MASK, /* AdvSIMD EXT index operand. */
a06ea964
NC		 245 AARCH64_OPND_IMM_VLSL,/* Immediate for shifting vector registers left. */
246 AARCH64_OPND_IMM_VLSR,/* Immediate for shifting vector registers right. */
247 AARCH64_OPND_SIMD_IMM,/* AdvSIMD modified immediate without shift. */
248 AARCH64_OPND_SIMD_IMM_SFT, /* AdvSIMD modified immediate with shift. */
249 AARCH64_OPND_SIMD_FPIMM,/* AdvSIMD 8-bit fp immediate. */
250 AARCH64_OPND_SHLL_IMM,/* Immediate shift for AdvSIMD SHLL instruction
251 (no encoding). */
252 AARCH64_OPND_IMM0, /* Immediate for #0. */
253 AARCH64_OPND_FPIMM0, /* Immediate for #0.0. */
254 AARCH64_OPND_FPIMM, /* Floating-point Immediate. */
255 AARCH64_OPND_IMMR, /* Immediate #<immr> in e.g. BFM. */
256 AARCH64_OPND_IMMS, /* Immediate #<imms> in e.g. BFM. */
257 AARCH64_OPND_WIDTH, /* Immediate #<width> in e.g. BFI. */
258 AARCH64_OPND_IMM, /* Immediate. */
f42f1a1d 259 AARCH64_OPND_IMM_2, /* Immediate. */
a06ea964
NC		 260 AARCH64_OPND_UIMM3_OP1,/* Unsigned 3-bit immediate in the op1 field. */
261 AARCH64_OPND_UIMM3_OP2,/* Unsigned 3-bit immediate in the op2 field. */
262 AARCH64_OPND_UIMM4, /* Unsigned 4-bit immediate in the CRm field. */
193614f2 263 AARCH64_OPND_UIMM4_ADDG,/* Unsigned 4-bit immediate in addg/subg. */
a06ea964 264 AARCH64_OPND_UIMM7, /* Unsigned 7-bit immediate in the CRm:op2 fields. */
193614f2 265 AARCH64_OPND_UIMM10, /* Unsigned 10-bit immediate in addg/subg. */
a06ea964
NC		 266 AARCH64_OPND_BIT_NUM, /* Immediate. */
267 AARCH64_OPND_EXCEPTION,/* imm16 operand in exception instructions. */
09c1e68a 268 AARCH64_OPND_UNDEFINED,/* imm16 operand in undefined instruction. */
a06ea964 269 AARCH64_OPND_CCMP_IMM,/* Immediate in conditional compare instructions. */
e950b345 270 AARCH64_OPND_SIMM5, /* 5-bit signed immediate in the imm5 field. */
a06ea964
NC		 271 AARCH64_OPND_NZCV, /* Flag bit specifier giving an alternative value for
272 each condition flag. */
273
274 AARCH64_OPND_LIMM, /* Logical Immediate. */
275 AARCH64_OPND_AIMM, /* Arithmetic immediate. */
276 AARCH64_OPND_HALF, /* #<imm16>{, LSL #<shift>} operand in move wide. */
277 AARCH64_OPND_FBITS, /* FP #<fbits> operand in e.g. SCVTF */
278 AARCH64_OPND_IMM_MOV, /* Immediate operand for the MOV alias. */
c2c4ff8d
SN		 279 AARCH64_OPND_IMM_ROT1, /* Immediate rotate operand for FCMLA. */
280 AARCH64_OPND_IMM_ROT2, /* Immediate rotate operand for indexed FCMLA. */
281 AARCH64_OPND_IMM_ROT3, /* Immediate rotate operand for FCADD. */
a06ea964
NC		 282
283 AARCH64_OPND_COND, /* Standard condition as the last operand. */
68a64283 284 AARCH64_OPND_COND1, /* Same as the above, but excluding AL and NV. */
a06ea964
NC		 285
286 AARCH64_OPND_ADDR_ADRP, /* Memory address for ADRP */
287 AARCH64_OPND_ADDR_PCREL14, /* 14-bit PC-relative address for e.g. TBZ. */
288 AARCH64_OPND_ADDR_PCREL19, /* 19-bit PC-relative address for e.g. LDR. */
289 AARCH64_OPND_ADDR_PCREL21, /* 21-bit PC-relative address for e.g. ADR. */
290 AARCH64_OPND_ADDR_PCREL26, /* 26-bit PC-relative address for e.g. BL. */
291
292 AARCH64_OPND_ADDR_SIMPLE, /* Address of ld/st exclusive. */
293 AARCH64_OPND_ADDR_REGOFF, /* Address of register offset. */
294 AARCH64_OPND_ADDR_SIMM7, /* Address of signed 7-bit immediate. */
295 AARCH64_OPND_ADDR_SIMM9, /* Address of signed 9-bit immediate. */
296 AARCH64_OPND_ADDR_SIMM9_2, /* Same as the above, but the immediate is
297 negative or unaligned and there is
298 no writeback allowed. This operand code
299 is only used to support the programmer-
300 friendly feature of using LDR/STR as the
301 the mnemonic name for LDUR/STUR instructions
302 wherever there is no ambiguity. */
3f06e550 303 AARCH64_OPND_ADDR_SIMM10, /* Address of signed 10-bit immediate. */
fb3265b3
SD		 304 AARCH64_OPND_ADDR_SIMM11, /* Address with a signed 11-bit (multiple of
305 16) immediate. */
a06ea964 306 AARCH64_OPND_ADDR_UIMM12, /* Address of unsigned 12-bit immediate. */
fb3265b3
SD		 307 AARCH64_OPND_ADDR_SIMM13, /* Address with a signed 13-bit (multiple of
308 16) immediate. */
a06ea964 309 AARCH64_OPND_SIMD_ADDR_SIMPLE,/* Address of ld/st multiple structures. */
f42f1a1d 310 AARCH64_OPND_ADDR_OFFSET, /* Address with an optional 9-bit immediate. */
a06ea964
NC		 311 AARCH64_OPND_SIMD_ADDR_POST, /* Address of ld/st multiple post-indexed. */
312
313 AARCH64_OPND_SYSREG, /* System register operand. */
314 AARCH64_OPND_PSTATEFIELD, /* PSTATE field name operand. */
315 AARCH64_OPND_SYSREG_AT, /* System register <at_op> operand. */
316 AARCH64_OPND_SYSREG_DC, /* System register <dc_op> operand. */
317 AARCH64_OPND_SYSREG_IC, /* System register <ic_op> operand. */
318 AARCH64_OPND_SYSREG_TLBI, /* System register <tlbi_op> operand. */
2ac435d4 319 AARCH64_OPND_SYSREG_SR, /* System register RCTX operand. */
a06ea964 320 AARCH64_OPND_BARRIER, /* Barrier operand. */
fd195909 321 AARCH64_OPND_BARRIER_DSB_NXS, /* Barrier operand for DSB nXS variant. */
a06ea964
NC		 322 AARCH64_OPND_BARRIER_ISB, /* Barrier operand for ISB. */
323 AARCH64_OPND_PRFOP, /* Prefetch operation. */
1e6f4800 324 AARCH64_OPND_BARRIER_PSB, /* Barrier operand for PSB. */
ff605452 325 AARCH64_OPND_BTI_TARGET, /* BTI {<target>}. */
f11ad6bc 326
582e12bf 327 AARCH64_OPND_SVE_ADDR_RI_S4x16, /* SVE [<Xn|SP>, #<simm4>*16]. */
8382113f 328 AARCH64_OPND_SVE_ADDR_RI_S4x32, /* SVE [<Xn|SP>, #<simm4>*32]. */
98907a70
RS		 329 AARCH64_OPND_SVE_ADDR_RI_S4xVL, /* SVE [<Xn|SP>, #<simm4>, MUL VL]. */
330 AARCH64_OPND_SVE_ADDR_RI_S4x2xVL, /* SVE [<Xn|SP>, #<simm4>*2, MUL VL]. */
331 AARCH64_OPND_SVE_ADDR_RI_S4x3xVL, /* SVE [<Xn|SP>, #<simm4>*3, MUL VL]. */
332 AARCH64_OPND_SVE_ADDR_RI_S4x4xVL, /* SVE [<Xn|SP>, #<simm4>*4, MUL VL]. */
333 AARCH64_OPND_SVE_ADDR_RI_S6xVL, /* SVE [<Xn|SP>, #<simm6>, MUL VL]. */
334 AARCH64_OPND_SVE_ADDR_RI_S9xVL, /* SVE [<Xn|SP>, #<simm9>, MUL VL]. */
4df068de
RS		 335 AARCH64_OPND_SVE_ADDR_RI_U6, /* SVE [<Xn|SP>, #<uimm6>]. */
336 AARCH64_OPND_SVE_ADDR_RI_U6x2, /* SVE [<Xn|SP>, #<uimm6>*2]. */
337 AARCH64_OPND_SVE_ADDR_RI_U6x4, /* SVE [<Xn|SP>, #<uimm6>*4]. */
338 AARCH64_OPND_SVE_ADDR_RI_U6x8, /* SVE [<Xn|SP>, #<uimm6>*8]. */
c8d59609 339 AARCH64_OPND_SVE_ADDR_R, /* SVE [<Xn|SP>]. */
4df068de
RS		 340 AARCH64_OPND_SVE_ADDR_RR, /* SVE [<Xn|SP>, <Xm|XZR>]. */
341 AARCH64_OPND_SVE_ADDR_RR_LSL1, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #1]. */
342 AARCH64_OPND_SVE_ADDR_RR_LSL2, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #2]. */
343 AARCH64_OPND_SVE_ADDR_RR_LSL3, /* SVE [<Xn|SP>, <Xm|XZR>, LSL #3]. */
344 AARCH64_OPND_SVE_ADDR_RX, /* SVE [<Xn|SP>, <Xm>]. */
345 AARCH64_OPND_SVE_ADDR_RX_LSL1, /* SVE [<Xn|SP>, <Xm>, LSL #1]. */
346 AARCH64_OPND_SVE_ADDR_RX_LSL2, /* SVE [<Xn|SP>, <Xm>, LSL #2]. */
347 AARCH64_OPND_SVE_ADDR_RX_LSL3, /* SVE [<Xn|SP>, <Xm>, LSL #3]. */
c469c864 348 AARCH64_OPND_SVE_ADDR_ZX, /* SVE [Zn.<T>{, <Xm>}]. */
4df068de
RS		 349 AARCH64_OPND_SVE_ADDR_RZ, /* SVE [<Xn|SP>, Zm.D]. */
350 AARCH64_OPND_SVE_ADDR_RZ_LSL1, /* SVE [<Xn|SP>, Zm.D, LSL #1]. */
351 AARCH64_OPND_SVE_ADDR_RZ_LSL2, /* SVE [<Xn|SP>, Zm.D, LSL #2]. */
352 AARCH64_OPND_SVE_ADDR_RZ_LSL3, /* SVE [<Xn|SP>, Zm.D, LSL #3]. */
353 AARCH64_OPND_SVE_ADDR_RZ_XTW_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
354 Bit 14 controls S/U choice. */
355 AARCH64_OPND_SVE_ADDR_RZ_XTW_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW].
356 Bit 22 controls S/U choice. */
357 AARCH64_OPND_SVE_ADDR_RZ_XTW1_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
358 Bit 14 controls S/U choice. */
359 AARCH64_OPND_SVE_ADDR_RZ_XTW1_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #1].
360 Bit 22 controls S/U choice. */
361 AARCH64_OPND_SVE_ADDR_RZ_XTW2_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
362 Bit 14 controls S/U choice. */
363 AARCH64_OPND_SVE_ADDR_RZ_XTW2_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #2].
364 Bit 22 controls S/U choice. */
365 AARCH64_OPND_SVE_ADDR_RZ_XTW3_14, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
366 Bit 14 controls S/U choice. */
367 AARCH64_OPND_SVE_ADDR_RZ_XTW3_22, /* SVE [<Xn|SP>, Zm.<T>, (S|U)XTW #3].
368 Bit 22 controls S/U choice. */
369 AARCH64_OPND_SVE_ADDR_ZI_U5, /* SVE [Zn.<T>, #<uimm5>]. */
370 AARCH64_OPND_SVE_ADDR_ZI_U5x2, /* SVE [Zn.<T>, #<uimm5>*2]. */
371 AARCH64_OPND_SVE_ADDR_ZI_U5x4, /* SVE [Zn.<T>, #<uimm5>*4]. */
372 AARCH64_OPND_SVE_ADDR_ZI_U5x8, /* SVE [Zn.<T>, #<uimm5>*8]. */
373 AARCH64_OPND_SVE_ADDR_ZZ_LSL, /* SVE [Zn.<T>, Zm,<T>, LSL #<msz>]. */
374 AARCH64_OPND_SVE_ADDR_ZZ_SXTW, /* SVE [Zn.<T>, Zm,<T>, SXTW #<msz>]. */
375 AARCH64_OPND_SVE_ADDR_ZZ_UXTW, /* SVE [Zn.<T>, Zm,<T>, UXTW #<msz>]. */
e950b345
RS		 376 AARCH64_OPND_SVE_AIMM, /* SVE unsigned arithmetic immediate. */
377 AARCH64_OPND_SVE_ASIMM, /* SVE signed arithmetic immediate. */
165d4950
RS		 378 AARCH64_OPND_SVE_FPIMM8, /* SVE 8-bit floating-point immediate. */
379 AARCH64_OPND_SVE_I1_HALF_ONE, /* SVE choice between 0.5 and 1.0. */
380 AARCH64_OPND_SVE_I1_HALF_TWO, /* SVE choice between 0.5 and 2.0. */
381 AARCH64_OPND_SVE_I1_ZERO_ONE, /* SVE choice between 0.0 and 1.0. */
582e12bf
RS		 382 AARCH64_OPND_SVE_IMM_ROT1, /* SVE 1-bit rotate operand (90 or 270). */
383 AARCH64_OPND_SVE_IMM_ROT2, /* SVE 2-bit rotate operand (N*90). */
adccc507 384 AARCH64_OPND_SVE_IMM_ROT3, /* SVE cadd 1-bit rotate (90 or 270). */
e950b345
RS		 385 AARCH64_OPND_SVE_INV_LIMM, /* SVE inverted logical immediate. */
386 AARCH64_OPND_SVE_LIMM, /* SVE logical immediate. */
387 AARCH64_OPND_SVE_LIMM_MOV, /* SVE logical immediate for MOV. */
245d2e3f 388 AARCH64_OPND_SVE_PATTERN, /* SVE vector pattern enumeration. */
2442d846 389 AARCH64_OPND_SVE_PATTERN_SCALED, /* Likewise, with additional MUL factor. */
245d2e3f 390 AARCH64_OPND_SVE_PRFOP, /* SVE prefetch operation. */
f11ad6bc
RS		 391 AARCH64_OPND_SVE_Pd, /* SVE p0-p15 in Pd. */
392 AARCH64_OPND_SVE_Pg3, /* SVE p0-p7 in Pg. */
393 AARCH64_OPND_SVE_Pg4_5, /* SVE p0-p15 in Pg, bits [8,5]. */
394 AARCH64_OPND_SVE_Pg4_10, /* SVE p0-p15 in Pg, bits [13,10]. */
395 AARCH64_OPND_SVE_Pg4_16, /* SVE p0-p15 in Pg, bits [19,16]. */
396 AARCH64_OPND_SVE_Pm, /* SVE p0-p15 in Pm. */
397 AARCH64_OPND_SVE_Pn, /* SVE p0-p15 in Pn. */
398 AARCH64_OPND_SVE_Pt, /* SVE p0-p15 in Pt. */
047cd301
RS		 399 AARCH64_OPND_SVE_Rm, /* Integer Rm or ZR, alt. SVE position. */
400 AARCH64_OPND_SVE_Rn_SP, /* Integer Rn or SP, alt. SVE position. */
e950b345
RS		 401 AARCH64_OPND_SVE_SHLIMM_PRED, /* SVE shift left amount (predicated). */
402 AARCH64_OPND_SVE_SHLIMM_UNPRED, /* SVE shift left amount (unpredicated). */
28ed815a 403 AARCH64_OPND_SVE_SHLIMM_UNPRED_22, /* SVE 3 bit shift left unpred. */
e950b345
RS		 404 AARCH64_OPND_SVE_SHRIMM_PRED, /* SVE shift right amount (predicated). */
405 AARCH64_OPND_SVE_SHRIMM_UNPRED, /* SVE shift right amount (unpredicated). */
3c17238b 406 AARCH64_OPND_SVE_SHRIMM_UNPRED_22, /* SVE 3 bit shift right unpred. */
e950b345
RS		 407 AARCH64_OPND_SVE_SIMM5, /* SVE signed 5-bit immediate. */
408 AARCH64_OPND_SVE_SIMM5B, /* SVE secondary signed 5-bit immediate. */
409 AARCH64_OPND_SVE_SIMM6, /* SVE signed 6-bit immediate. */
410 AARCH64_OPND_SVE_SIMM8, /* SVE signed 8-bit immediate. */
411 AARCH64_OPND_SVE_UIMM3, /* SVE unsigned 3-bit immediate. */
412 AARCH64_OPND_SVE_UIMM7, /* SVE unsigned 7-bit immediate. */
413 AARCH64_OPND_SVE_UIMM8, /* SVE unsigned 8-bit immediate. */
414 AARCH64_OPND_SVE_UIMM8_53, /* SVE split unsigned 8-bit immediate. */
047cd301
RS		 415 AARCH64_OPND_SVE_VZn, /* Scalar SIMD&FP register in Zn field. */
416 AARCH64_OPND_SVE_Vd, /* Scalar SIMD&FP register in Vd. */
417 AARCH64_OPND_SVE_Vm, /* Scalar SIMD&FP register in Vm. */
418 AARCH64_OPND_SVE_Vn, /* Scalar SIMD&FP register in Vn. */
f11ad6bc
RS		 419 AARCH64_OPND_SVE_Za_5, /* SVE vector register in Za, bits [9,5]. */
420 AARCH64_OPND_SVE_Za_16, /* SVE vector register in Za, bits [20,16]. */
421 AARCH64_OPND_SVE_Zd, /* SVE vector register in Zd. */
422 AARCH64_OPND_SVE_Zm_5, /* SVE vector register in Zm, bits [9,5]. */
423 AARCH64_OPND_SVE_Zm_16, /* SVE vector register in Zm, bits [20,16]. */
582e12bf
RS		 424 AARCH64_OPND_SVE_Zm3_INDEX, /* z0-z7[0-3] in Zm, bits [20,16]. */
425 AARCH64_OPND_SVE_Zm3_22_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 22. */
116adc27 426 AARCH64_OPND_SVE_Zm3_11_INDEX, /* z0-z7[0-7] in Zm3_INDEX plus bit 11. */
31e36ab3 427 AARCH64_OPND_SVE_Zm4_11_INDEX, /* z0-z15[0-3] in Zm plus bit 11. */
582e12bf 428 AARCH64_OPND_SVE_Zm4_INDEX, /* z0-z15[0-1] in Zm, bits [20,16]. */
f11ad6bc
RS		 429 AARCH64_OPND_SVE_Zn, /* SVE vector register in Zn. */
430 AARCH64_OPND_SVE_Zn_INDEX, /* Indexed SVE vector register, for DUP. */
431 AARCH64_OPND_SVE_ZnxN, /* SVE vector register list in Zn. */
432 AARCH64_OPND_SVE_Zt, /* SVE vector register in Zt. */
433 AARCH64_OPND_SVE_ZtxN, /* SVE vector register list in Zt. */
b83b4b13 434 AARCH64_OPND_TME_UIMM16, /* TME unsigned 16-bit immediate. */
f42f1a1d 435 AARCH64_OPND_SM3_IMM2, /* SM3 encodes lane in bits [13, 14]. */
dd4a72c8 436 AARCH64_OPND_CSRE_CSR, /* CSRE CSR instruction Rt field. */
a06ea964
NC		 437};
438
439/* Qualifier constrains an operand. It either specifies a variant of an
440 operand type or limits values available to an operand type.
441
442 N.B. Order is important; keep aarch64_opnd_qualifiers synced. */
443
444enum aarch64_opnd_qualifier
445{
446 /* Indicating no further qualification on an operand. */
447 AARCH64_OPND_QLF_NIL,
448
449 /* Qualifying an operand which is a general purpose (integer) register;
450 indicating the operand data size or a specific register. */
451 AARCH64_OPND_QLF_W, /* Wn, WZR or WSP. */
452 AARCH64_OPND_QLF_X, /* Xn, XZR or XSP. */
453 AARCH64_OPND_QLF_WSP, /* WSP. */
454 AARCH64_OPND_QLF_SP, /* SP. */
455
456 /* Qualifying an operand which is a floating-point register, a SIMD
457 vector element or a SIMD vector element list; indicating operand data
458 size or the size of each SIMD vector element in the case of a SIMD
459 vector element list.
460 These qualifiers are also used to qualify an address operand to
461 indicate the size of data element a load/store instruction is
462 accessing.
463 They are also used for the immediate shift operand in e.g. SSHR. Such
464 a use is only for the ease of operand encoding/decoding and qualifier
465 sequence matching; such a use should not be applied widely; use the value
466 constraint qualifiers for immediate operands wherever possible. */
467 AARCH64_OPND_QLF_S_B,
468 AARCH64_OPND_QLF_S_H,
469 AARCH64_OPND_QLF_S_S,
470 AARCH64_OPND_QLF_S_D,
471 AARCH64_OPND_QLF_S_Q,
df678013
MM		 472 /* These type qualifiers have a special meaning in that they mean 4 x 1 byte
473 or 2 x 2 byte are selected by the instruction. Other than that they have
474 no difference with AARCH64_OPND_QLF_S_B in encoding. They are here purely
475 for syntactical reasons and is an exception from normal AArch64
476 disassembly scheme. */
00c2093f 477 AARCH64_OPND_QLF_S_4B,
df678013 478 AARCH64_OPND_QLF_S_2H,
a06ea964
NC		 479
480 /* Qualifying an operand which is a SIMD vector register or a SIMD vector
481 register list; indicating register shape.
482 They are also used for the immediate shift operand in e.g. SSHR. Such
483 a use is only for the ease of operand encoding/decoding and qualifier
484 sequence matching; such a use should not be applied widely; use the value
485 constraint qualifiers for immediate operands wherever possible. */
a3b3345a 486 AARCH64_OPND_QLF_V_4B,
a06ea964
NC		 487 AARCH64_OPND_QLF_V_8B,
488 AARCH64_OPND_QLF_V_16B,
3067d3b9 489 AARCH64_OPND_QLF_V_2H,
a06ea964
NC		 490 AARCH64_OPND_QLF_V_4H,
491 AARCH64_OPND_QLF_V_8H,
492 AARCH64_OPND_QLF_V_2S,
493 AARCH64_OPND_QLF_V_4S,
494 AARCH64_OPND_QLF_V_1D,
495 AARCH64_OPND_QLF_V_2D,
496 AARCH64_OPND_QLF_V_1Q,
497
d50c751e
RS		 498 AARCH64_OPND_QLF_P_Z,
499 AARCH64_OPND_QLF_P_M,
fb3265b3
SD		 500
501 /* Used in scaled signed immediate that are scaled by a Tag granule
502 like in stg, st2g, etc. */
503 AARCH64_OPND_QLF_imm_tag,
d50c751e 504
a06ea964 505 /* Constraint on value. */
a6a51754 506 AARCH64_OPND_QLF_CR, /* CRn, CRm. */
a06ea964
NC		 507 AARCH64_OPND_QLF_imm_0_7,
508 AARCH64_OPND_QLF_imm_0_15,
509 AARCH64_OPND_QLF_imm_0_31,
510 AARCH64_OPND_QLF_imm_0_63,
511 AARCH64_OPND_QLF_imm_1_32,
512 AARCH64_OPND_QLF_imm_1_64,
513
514 /* Indicate whether an AdvSIMD modified immediate operand is shift-zeros
515 or shift-ones. */
516 AARCH64_OPND_QLF_LSL,
517 AARCH64_OPND_QLF_MSL,
518
519 /* Special qualifier helping retrieve qualifier information during the
520 decoding time (currently not in use). */
521 AARCH64_OPND_QLF_RETRIEVE,
522};
523\f
524/* Instruction class. */
525
526enum aarch64_insn_class
527{
8382113f 528 aarch64_misc,
a06ea964
NC		 529 addsub_carry,
530 addsub_ext,
531 addsub_imm,
532 addsub_shift,
533 asimdall,
534 asimddiff,
535 asimdelem,
536 asimdext,
537 asimdimm,
538 asimdins,
539 asimdmisc,
540 asimdperm,
541 asimdsame,
542 asimdshf,
543 asimdtbl,
544 asisddiff,
545 asisdelem,
546 asisdlse,
547 asisdlsep,
548 asisdlso,
549 asisdlsop,
550 asisdmisc,
551 asisdone,
552 asisdpair,
553 asisdsame,
554 asisdshf,
555 bitfield,
556 branch_imm,
557 branch_reg,
558 compbranch,
559 condbranch,
560 condcmp_imm,
561 condcmp_reg,
562 condsel,
563 cryptoaes,
564 cryptosha2,
565 cryptosha3,
566 dp_1src,
567 dp_2src,
568 dp_3src,
569 exception,
570 extract,
571 float2fix,
572 float2int,
573 floatccmp,
574 floatcmp,
575 floatdp1,
576 floatdp2,
577 floatdp3,
578 floatimm,
579 floatsel,
580 ldst_immpost,
581 ldst_immpre,
582 ldst_imm9, /* immpost or immpre */
3f06e550 583 ldst_imm10, /* LDRAA/LDRAB */
a06ea964
NC		 584 ldst_pos,
585 ldst_regoff,
586 ldst_unpriv,
587 ldst_unscaled,
588 ldstexcl,
589 ldstnapair_offs,
590 ldstpair_off,
591 ldstpair_indexed,
592 loadlit,
593 log_imm,
594 log_shift,
ee804238 595 lse_atomic,
a06ea964
NC		 596 movewide,
597 pcreladdr,
598 ic_system,
116b6019
RS		 599 sve_cpy,
600 sve_index,
601 sve_limm,
602 sve_misc,
603 sve_movprfx,
604 sve_pred_zm,
605 sve_shift_pred,
606 sve_shift_unpred,
607 sve_size_bhs,
608 sve_size_bhsd,
609 sve_size_hsd,
3bd82c86 610 sve_size_hsd2,
116b6019 611 sve_size_sd,
3c705960 612 sve_size_bh,
0a57e14f 613 sve_size_sd2,
41be57ca 614 sve_size_13,
3c17238b 615 sve_shift_tsz_hsd,
1be5f94f 616 sve_shift_tsz_bhsd,
fd1dc4a0 617 sve_size_tsz_bhs,
a06ea964 618 testbranch,
f42f1a1d
TC		 619 cryptosm3,
620 cryptosm4,
65a55fbb 621 dotproduct,
df678013 622 bfloat16,
a06ea964
NC		 623};
624
625/* Opcode enumerators. */
626
627enum aarch64_op
628{
629 OP_NIL,
630 OP_STRB_POS,
631 OP_LDRB_POS,
632 OP_LDRSB_POS,
633 OP_STRH_POS,
634 OP_LDRH_POS,
635 OP_LDRSH_POS,
636 OP_STR_POS,
637 OP_LDR_POS,
638 OP_STRF_POS,
639 OP_LDRF_POS,
640 OP_LDRSW_POS,
641 OP_PRFM_POS,
642
643 OP_STURB,
644 OP_LDURB,
645 OP_LDURSB,
646 OP_STURH,
647 OP_LDURH,
648 OP_LDURSH,
649 OP_STUR,
650 OP_LDUR,
651 OP_STURV,
652 OP_LDURV,
653 OP_LDURSW,
654 OP_PRFUM,
655
656 OP_LDR_LIT,
657 OP_LDRV_LIT,
658 OP_LDRSW_LIT,
659 OP_PRFM_LIT,
660
661 OP_ADD,
662 OP_B,
663 OP_BL,
664
665 OP_MOVN,
666 OP_MOVZ,
667 OP_MOVK,
668
669 OP_MOV_IMM_LOG, /* MOV alias for moving bitmask immediate. */
670 OP_MOV_IMM_WIDE, /* MOV alias for moving wide immediate. */
671 OP_MOV_IMM_WIDEN, /* MOV alias for moving wide immediate (negated). */
672
673 OP_MOV_V, /* MOV alias for moving vector register. */
674
675 OP_ASR_IMM,
676 OP_LSR_IMM,
677 OP_LSL_IMM,
678
679 OP_BIC,
680
681 OP_UBFX,
682 OP_BFXIL,
683 OP_SBFX,
684 OP_SBFIZ,
685 OP_BFI,
d685192a 686 OP_BFC, /* ARMv8.2. */
a06ea964
NC		 687 OP_UBFIZ,
688 OP_UXTB,
689 OP_UXTH,
690 OP_UXTW,
691
a06ea964
NC		 692 OP_CINC,
693 OP_CINV,
694 OP_CNEG,
695 OP_CSET,
696 OP_CSETM,
697
698 OP_FCVT,
699 OP_FCVTN,
700 OP_FCVTN2,
701 OP_FCVTL,
702 OP_FCVTL2,
703 OP_FCVTXN_S, /* Scalar version. */
704
705 OP_ROR_IMM,
706
e30181a5
YZ		 707 OP_SXTL,
708 OP_SXTL2,
709 OP_UXTL,
710 OP_UXTL2,
711
c0890d26
RS		 712 OP_MOV_P_P,
713 OP_MOV_Z_P_Z,
714 OP_MOV_Z_V,
715 OP_MOV_Z_Z,
716 OP_MOV_Z_Zi,
717 OP_MOVM_P_P_P,
718 OP_MOVS_P_P,
719 OP_MOVZS_P_P_P,
720 OP_MOVZ_P_P_P,
721 OP_NOTS_P_P_P_Z,
722 OP_NOT_P_P_P_Z,
723
c2c4ff8d
SN		 724 OP_FCMLA_ELEM, /* ARMv8.3, indexed element version. */
725
a06ea964
NC		 726 OP_TOTAL_NUM, /* Pseudo. */
727};
728
1d482394
TC		 729/* Error types. */
730enum err_type
731{
732 ERR_OK,
733 ERR_UND,
734 ERR_UNP,
735 ERR_NYI,
a68f4cd2 736 ERR_VFI,
1d482394
TC		 737 ERR_NR_ENTRIES
738};
739
a06ea964
NC		 740/* Maximum number of operands an instruction can have. */
741#define AARCH64_MAX_OPND_NUM 6
742/* Maximum number of qualifier sequences an instruction can have. */
743#define AARCH64_MAX_QLF_SEQ_NUM 10
744/* Operand qualifier typedef; optimized for the size. */
745typedef unsigned char aarch64_opnd_qualifier_t;
746/* Operand qualifier sequence typedef. */
747typedef aarch64_opnd_qualifier_t \
748 aarch64_opnd_qualifier_seq_t [AARCH64_MAX_OPND_NUM];
749
750/* FIXME: improve the efficiency. */
751static inline bfd_boolean
752empty_qualifier_sequence_p (const aarch64_opnd_qualifier_t *qualifiers)
753{
754 int i;
755 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
756 if (qualifiers[i] != AARCH64_OPND_QLF_NIL)
757 return FALSE;
758 return TRUE;
759}
760
7e84b55d
TC		 761/* Forward declare error reporting type. */
762typedef struct aarch64_operand_error aarch64_operand_error;
763/* Forward declare instruction sequence type. */
764typedef struct aarch64_instr_sequence aarch64_instr_sequence;
765/* Forward declare instruction definition. */
766typedef struct aarch64_inst aarch64_inst;
767
a06ea964
NC		 768/* This structure holds information for a particular opcode. */
769
770struct aarch64_opcode
771{
772 /* The name of the mnemonic. */
773 const char *name;
774
775 /* The opcode itself. Those bits which will be filled in with
776 operands are zeroes. */
777 aarch64_insn opcode;
778
779 /* The opcode mask. This is used by the disassembler. This is a
780 mask containing ones indicating those bits which must match the
781 opcode field, and zeroes indicating those bits which need not
782 match (and are presumably filled in by operands). */
783 aarch64_insn mask;
784
785 /* Instruction class. */
786 enum aarch64_insn_class iclass;
787
788 /* Enumerator identifier. */
789 enum aarch64_op op;
790
791 /* Which architecture variant provides this instruction. */
792 const aarch64_feature_set *avariant;
793
794 /* An array of operand codes. Each code is an index into the
795 operand table. They appear in the order which the operands must
796 appear in assembly code, and are terminated by a zero. */
797 enum aarch64_opnd operands[AARCH64_MAX_OPND_NUM];
798
799 /* A list of operand qualifier code sequence. Each operand qualifier
800 code qualifies the corresponding operand code. Each operand
801 qualifier sequence specifies a valid opcode variant and related
802 constraint on operands. */
803 aarch64_opnd_qualifier_seq_t qualifiers_list[AARCH64_MAX_QLF_SEQ_NUM];
804
805 /* Flags providing information about this instruction */
eae424ae
TC		 806 uint64_t flags;
807
808 /* Extra constraints on the instruction that the verifier checks. */
809 uint32_t constraints;
4bd13cde 810
0c608d6b
RS		 811 /* If nonzero, this operand and operand 0 are both registers and
812 are required to have the same register number. */
813 unsigned char tied_operand;
814
4bd13cde 815 /* If non-NULL, a function to verify that a given instruction is valid. */
755b748f
TC		 816 enum err_type (* verifier) (const struct aarch64_inst *, const aarch64_insn,
817 bfd_vma, bfd_boolean, aarch64_operand_error *,
818 struct aarch64_instr_sequence *);
a06ea964
NC		 819};
820
821typedef struct aarch64_opcode aarch64_opcode;
822
823/* Table describing all the AArch64 opcodes. */
824extern aarch64_opcode aarch64_opcode_table[];
825
826/* Opcode flags. */
827#define F_ALIAS (1 << 0)
828#define F_HAS_ALIAS (1 << 1)
829/* Disassembly preference priority 1-3 (the larger the higher). If nothing
830 is specified, it is the priority 0 by default, i.e. the lowest priority. */
831#define F_P1 (1 << 2)
832#define F_P2 (2 << 2)
833#define F_P3 (3 << 2)
834/* Flag an instruction that is truly conditional executed, e.g. b.cond. */
835#define F_COND (1 << 4)
836/* Instruction has the field of 'sf'. */
837#define F_SF (1 << 5)
838/* Instruction has the field of 'size:Q'. */
839#define F_SIZEQ (1 << 6)
840/* Floating-point instruction has the field of 'type'. */
841#define F_FPTYPE (1 << 7)
842/* AdvSIMD scalar instruction has the field of 'size'. */
843#define F_SSIZE (1 << 8)
844/* AdvSIMD vector register arrangement specifier encoded in "imm5<3:0>:Q". */
845#define F_T (1 << 9)
846/* Size of GPR operand in AdvSIMD instructions encoded in Q. */
847#define F_GPRSIZE_IN_Q (1 << 10)
848/* Size of Rt load signed instruction encoded in opc[0], i.e. bit 22. */
849#define F_LDS_SIZE (1 << 11)
850/* Optional operand; assume maximum of 1 operand can be optional. */
851#define F_OPD0_OPT (1 << 12)
852#define F_OPD1_OPT (2 << 12)
853#define F_OPD2_OPT (3 << 12)
854#define F_OPD3_OPT (4 << 12)
855#define F_OPD4_OPT (5 << 12)
856/* Default value for the optional operand when omitted from the assembly. */
857#define F_DEFAULT(X) (((X) & 0x1f) << 15)
858/* Instruction that is an alias of another instruction needs to be
859 encoded/decoded by converting it to/from the real form, followed by
860 the encoding/decoding according to the rules of the real opcode.
861 This compares to the direct coding using the alias's information.
862 N.B. this flag requires F_ALIAS to be used together. */
863#define F_CONV (1 << 20)
864/* Use together with F_ALIAS to indicate an alias opcode is a programmer
865 friendly pseudo instruction available only in the assembly code (thus will
866 not show up in the disassembly). */
867#define F_PSEUDO (1 << 21)
868/* Instruction has miscellaneous encoding/decoding rules. */
869#define F_MISC (1 << 22)
870/* Instruction has the field of 'N'; used in conjunction with F_SF. */
871#define F_N (1 << 23)
872/* Opcode dependent field. */
873#define F_OD(X) (((X) & 0x7) << 24)
ee804238
JW		 874/* Instruction has the field of 'sz'. */
875#define F_LSE_SZ (1 << 27)
4989adac
RS		 876/* Require an exact qualifier match, even for NIL qualifiers. */
877#define F_STRICT (1ULL << 28)
f9830ec1
TC		 878/* This system instruction is used to read system registers. */
879#define F_SYS_READ (1ULL << 29)
880/* This system instruction is used to write system registers. */
881#define F_SYS_WRITE (1ULL << 30)
eae424ae
TC		 882/* This instruction has an extra constraint on it that imposes a requirement on
883 subsequent instructions. */
884#define F_SCAN (1ULL << 31)
885/* Next bit is 32. */
886
887/* Instruction constraints. */
888/* This instruction has a predication constraint on the instruction at PC+4. */
889#define C_SCAN_MOVPRFX (1U << 0)
890/* This instruction's operation width is determined by the operand with the
891 largest element size. */
892#define C_MAX_ELEM (1U << 1)
893/* Next bit is 2. */
a06ea964
NC		 894
895static inline bfd_boolean
896alias_opcode_p (const aarch64_opcode *opcode)
897{
898 return (opcode->flags & F_ALIAS) ? TRUE : FALSE;
899}
900
901static inline bfd_boolean
902opcode_has_alias (const aarch64_opcode *opcode)
903{
904 return (opcode->flags & F_HAS_ALIAS) ? TRUE : FALSE;
905}
906
907/* Priority for disassembling preference. */
908static inline int
909opcode_priority (const aarch64_opcode *opcode)
910{
911 return (opcode->flags >> 2) & 0x3;
912}
913
914static inline bfd_boolean
915pseudo_opcode_p (const aarch64_opcode *opcode)
916{
917 return (opcode->flags & F_PSEUDO) != 0lu ? TRUE : FALSE;
918}
919
920static inline bfd_boolean
921optional_operand_p (const aarch64_opcode *opcode, unsigned int idx)
922{
923 return (((opcode->flags >> 12) & 0x7) == idx + 1)
924 ? TRUE : FALSE;
925}
926
927static inline aarch64_insn
928get_optional_operand_default_value (const aarch64_opcode *opcode)
929{
930 return (opcode->flags >> 15) & 0x1f;
931}
932
933static inline unsigned int
934get_opcode_dependent_value (const aarch64_opcode *opcode)
935{
936 return (opcode->flags >> 24) & 0x7;
937}
938
939static inline bfd_boolean
940opcode_has_special_coder (const aarch64_opcode *opcode)
941{
ee804238 942 return (opcode->flags & (F_SF | F_LSE_SZ | F_SIZEQ | F_FPTYPE | F_SSIZE | F_T
a06ea964
NC		 943 | F_GPRSIZE_IN_Q | F_LDS_SIZE | F_MISC | F_N | F_COND)) ? TRUE
944 : FALSE;
945}
946\f
947struct aarch64_name_value_pair
948{
949 const char * name;
950 aarch64_insn value;
951};
952
953extern const struct aarch64_name_value_pair aarch64_operand_modifiers [];
a06ea964 954extern const struct aarch64_name_value_pair aarch64_barrier_options [16];
fd195909 955extern const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options [4];
a06ea964 956extern const struct aarch64_name_value_pair aarch64_prfops [32];
9ed608f9 957extern const struct aarch64_name_value_pair aarch64_hint_options [];
a06ea964 958
fa63795f
AC		 959#define AARCH64_MAX_SYSREG_NAME_LEN 32
960
49eec193
YZ		 961typedef struct
962{
963 const char * name;
964 aarch64_insn value;
965 uint32_t flags;
14962256
AC		 966
967 /* A set of features, all of which are required for this system register to be
968 available. */
969 aarch64_feature_set features;
49eec193
YZ		 970} aarch64_sys_reg;
971
972extern const aarch64_sys_reg aarch64_sys_regs [];
87b8eed7 973extern const aarch64_sys_reg aarch64_pstatefields [];
f7cb161e 974extern bfd_boolean aarch64_sys_reg_deprecated_p (const uint32_t);
f21cce2c
MW		 975extern bfd_boolean aarch64_pstatefield_supported_p (const aarch64_feature_set,
976 const aarch64_sys_reg *);
49eec193 977
a06ea964
NC		 978typedef struct
979{
875880c6 980 const char *name;
a06ea964 981 uint32_t value;
ea2deeec 982 uint32_t flags ;
a06ea964
NC		 983} aarch64_sys_ins_reg;
984
ea2deeec 985extern bfd_boolean aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *);
d6bf7ce6 986extern bfd_boolean
38cf07a6
AC		 987aarch64_sys_ins_reg_supported_p (const aarch64_feature_set,
988 const char *reg_name, aarch64_insn,
f7cb161e 989 uint32_t, aarch64_feature_set);
ea2deeec 990
a06ea964
NC		 991extern const aarch64_sys_ins_reg aarch64_sys_regs_ic [];
992extern const aarch64_sys_ins_reg aarch64_sys_regs_dc [];
993extern const aarch64_sys_ins_reg aarch64_sys_regs_at [];
994extern const aarch64_sys_ins_reg aarch64_sys_regs_tlbi [];
2ac435d4 995extern const aarch64_sys_ins_reg aarch64_sys_regs_sr [];
a06ea964
NC		 996
997/* Shift/extending operator kinds.
998 N.B. order is important; keep aarch64_operand_modifiers synced. */
999enum aarch64_modifier_kind
1000{
1001 AARCH64_MOD_NONE,
1002 AARCH64_MOD_MSL,
1003 AARCH64_MOD_ROR,
1004 AARCH64_MOD_ASR,
1005 AARCH64_MOD_LSR,
1006 AARCH64_MOD_LSL,
1007 AARCH64_MOD_UXTB,
1008 AARCH64_MOD_UXTH,
1009 AARCH64_MOD_UXTW,
1010 AARCH64_MOD_UXTX,
1011 AARCH64_MOD_SXTB,
1012 AARCH64_MOD_SXTH,
1013 AARCH64_MOD_SXTW,
1014 AARCH64_MOD_SXTX,
2442d846 1015 AARCH64_MOD_MUL,
98907a70 1016 AARCH64_MOD_MUL_VL,
a06ea964
NC		 1017};
1018
1019bfd_boolean
1020aarch64_extend_operator_p (enum aarch64_modifier_kind);
1021
1022enum aarch64_modifier_kind
1023aarch64_get_operand_modifier (const struct aarch64_name_value_pair *);
1024/* Condition. */
1025
1026typedef struct
1027{
1028 /* A list of names with the first one as the disassembly preference;
1029 terminated by NULL if fewer than 3. */
bb7eff52 1030 const char *names[4];
a06ea964
NC		 1031 aarch64_insn value;
1032} aarch64_cond;
1033
1034extern const aarch64_cond aarch64_conds[16];
1035
1036const aarch64_cond* get_cond_from_value (aarch64_insn value);
1037const aarch64_cond* get_inverted_cond (const aarch64_cond *cond);
1038\f
1039/* Structure representing an operand. */
1040
1041struct aarch64_opnd_info
1042{
1043 enum aarch64_opnd type;
1044 aarch64_opnd_qualifier_t qualifier;
1045 int idx;
1046
1047 union
1048 {
1049 struct
1050 {
1051 unsigned regno;
1052 } reg;
1053 struct
1054 {
dab26bf4
RS		 1055 unsigned int regno;
1056 int64_t index;
a06ea964
NC		 1057 } reglane;
1058 /* e.g. LVn. */
1059 struct
1060 {
1061 unsigned first_regno : 5;
1062 unsigned num_regs : 3;
1063 /* 1 if it is a list of reg element. */
1064 unsigned has_index : 1;
1065 /* Lane index; valid only when has_index is 1. */
dab26bf4 1066 int64_t index;
a06ea964
NC		 1067 } reglist;
1068 /* e.g. immediate or pc relative address offset. */
1069 struct
1070 {
1071 int64_t value;
1072 unsigned is_fp : 1;
1073 } imm;
1074 /* e.g. address in STR (register offset). */
1075 struct
1076 {
1077 unsigned base_regno;
1078 struct
1079 {
1080 union
1081 {
1082 int imm;
1083 unsigned regno;
1084 };
1085 unsigned is_reg;
1086 } offset;
1087 unsigned pcrel : 1; /* PC-relative. */
1088 unsigned writeback : 1;
1089 unsigned preind : 1; /* Pre-indexed. */
1090 unsigned postind : 1; /* Post-indexed. */
1091 } addr;
561a72d4
TC		 1092
1093 struct
1094 {
1095 /* The encoding of the system register. */
1096 aarch64_insn value;
1097
1098 /* The system register flags. */
1099 uint32_t flags;
1100 } sysreg;
1101
a06ea964 1102 const aarch64_cond *cond;
a06ea964
NC		 1103 /* The encoding of the PSTATE field. */
1104 aarch64_insn pstatefield;
1105 const aarch64_sys_ins_reg *sysins_op;
1106 const struct aarch64_name_value_pair *barrier;
9ed608f9 1107 const struct aarch64_name_value_pair *hint_option;
a06ea964
NC		 1108 const struct aarch64_name_value_pair *prfop;
1109 };
1110
1111 /* Operand shifter; in use when the operand is a register offset address,
1112 add/sub extended reg, etc. e.g. <R><m>{, <extend> {#<amount>}}. */
1113 struct
1114 {
1115 enum aarch64_modifier_kind kind;
a06ea964
NC		 1116 unsigned operator_present: 1; /* Only valid during encoding. */
1117 /* Value of the 'S' field in ld/st reg offset; used only in decoding. */
1118 unsigned amount_present: 1;
2442d846 1119 int64_t amount;
a06ea964
NC		 1120 } shifter;
1121
1122 unsigned skip:1; /* Operand is not completed if there is a fixup needed
1123 to be done on it. In some (but not all) of these
1124 cases, we need to tell libopcodes to skip the
1125 constraint checking and the encoding for this
1126 operand, so that the libopcodes can pick up the
1127 right opcode before the operand is fixed-up. This
1128 flag should only be used during the
1129 assembling/encoding. */
1130 unsigned present:1; /* Whether this operand is present in the assembly
1131 line; not used during the disassembly. */
1132};
1133
1134typedef struct aarch64_opnd_info aarch64_opnd_info;
1135
1136/* Structure representing an instruction.
1137
1138 It is used during both the assembling and disassembling. The assembler
1139 fills an aarch64_inst after a successful parsing and then passes it to the
1140 encoding routine to do the encoding. During the disassembling, the
1141 disassembler calls the decoding routine to decode a binary instruction; on a
1142 successful return, such a structure will be filled with information of the
1143 instruction; then the disassembler uses the information to print out the
1144 instruction. */
1145
1146struct aarch64_inst
1147{
1148 /* The value of the binary instruction. */
1149 aarch64_insn value;
1150
1151 /* Corresponding opcode entry. */
1152 const aarch64_opcode *opcode;
1153
1154 /* Condition for a truly conditional-executed instrutions, e.g. b.cond. */
1155 const aarch64_cond *cond;
1156
1157 /* Operands information. */
1158 aarch64_opnd_info operands[AARCH64_MAX_OPND_NUM];
1159};
1160
ff605452
SD		 1161/* Defining the HINT #imm values for the aarch64_hint_options. */
1162#define HINT_OPD_CSYNC 0x11
1163#define HINT_OPD_C 0x22
1164#define HINT_OPD_J 0x24
1165#define HINT_OPD_JC 0x26
1166#define HINT_OPD_NULL 0x00
1167
a06ea964
NC		 1168\f
1169/* Diagnosis related declaration and interface. */
1170
1171/* Operand error kind enumerators.
1172
1173 AARCH64_OPDE_RECOVERABLE
1174 Less severe error found during the parsing, very possibly because that
1175 GAS has picked up a wrong instruction template for the parsing.
1176
1177 AARCH64_OPDE_SYNTAX_ERROR
1178 General syntax error; it can be either a user error, or simply because
1179 that GAS is trying a wrong instruction template.
1180
1181 AARCH64_OPDE_FATAL_SYNTAX_ERROR
1182 Definitely a user syntax error.
1183
1184 AARCH64_OPDE_INVALID_VARIANT
1185 No syntax error, but the operands are not a valid combination, e.g.
1186 FMOV D0,S0
1187
0c608d6b
RS		 1188 AARCH64_OPDE_UNTIED_OPERAND
1189 The asm failed to use the same register for a destination operand
1190 and a tied source operand.
1191
a06ea964
NC		 1192 AARCH64_OPDE_OUT_OF_RANGE
1193 Error about some immediate value out of a valid range.
1194
1195 AARCH64_OPDE_UNALIGNED
1196 Error about some immediate value not properly aligned (i.e. not being a
1197 multiple times of a certain value).
1198
1199 AARCH64_OPDE_REG_LIST
1200 Error about the register list operand having unexpected number of
1201 registers.
1202
1203 AARCH64_OPDE_OTHER_ERROR
1204 Error of the highest severity and used for any severe issue that does not
1205 fall into any of the above categories.
1206
1207 The enumerators are only interesting to GAS. They are declared here (in
1208 libopcodes) because that some errors are detected (and then notified to GAS)
1209 by libopcodes (rather than by GAS solely).
1210
1211 The first three errors are only deteced by GAS while the
1212 AARCH64_OPDE_INVALID_VARIANT error can only be spotted by libopcodes as
1213 only libopcodes has the information about the valid variants of each
1214 instruction.
1215
1216 The enumerators have an increasing severity. This is helpful when there are
1217 multiple instruction templates available for a given mnemonic name (e.g.
1218 FMOV); this mechanism will help choose the most suitable template from which
1219 the generated diagnostics can most closely describe the issues, if any. */
1220
1221enum aarch64_operand_error_kind
1222{
1223 AARCH64_OPDE_NIL,
1224 AARCH64_OPDE_RECOVERABLE,
1225 AARCH64_OPDE_SYNTAX_ERROR,
1226 AARCH64_OPDE_FATAL_SYNTAX_ERROR,
1227 AARCH64_OPDE_INVALID_VARIANT,
0c608d6b 1228 AARCH64_OPDE_UNTIED_OPERAND,
a06ea964
NC		 1229 AARCH64_OPDE_OUT_OF_RANGE,
1230 AARCH64_OPDE_UNALIGNED,
1231 AARCH64_OPDE_REG_LIST,
1232 AARCH64_OPDE_OTHER_ERROR
1233};
1234
1235/* N.B. GAS assumes that this structure work well with shallow copy. */
1236struct aarch64_operand_error
1237{
1238 enum aarch64_operand_error_kind kind;
1239 int index;
1240 const char *error;
1241 int data[3]; /* Some data for extra information. */
7d02540a 1242 bfd_boolean non_fatal;
a06ea964
NC		 1243};
1244
7e84b55d
TC		 1245/* AArch64 sequence structure used to track instructions with F_SCAN
1246 dependencies for both assembler and disassembler. */
1247struct aarch64_instr_sequence
1248{
1249 /* The instruction that caused this sequence to be opened. */
1250 aarch64_inst *instr;
1251 /* The number of instructions the above instruction allows to be kept in the
1252 sequence before an automatic close is done. */
1253 int num_insns;
1254 /* The instructions currently added to the sequence. */
1255 aarch64_inst **current_insns;
1256 /* The number of instructions already in the sequence. */
1257 int next_insn;
1258};
a06ea964
NC		 1259
1260/* Encoding entrypoint. */
1261
1262extern int
1263aarch64_opcode_encode (const aarch64_opcode *, const aarch64_inst *,
1264 aarch64_insn *, aarch64_opnd_qualifier_t *,
7e84b55d 1265 aarch64_operand_error *, aarch64_instr_sequence *);
a06ea964
NC		 1266
1267extern const aarch64_opcode *
1268aarch64_replace_opcode (struct aarch64_inst *,
1269 const aarch64_opcode *);
1270
1271/* Given the opcode enumerator OP, return the pointer to the corresponding
1272 opcode entry. */
1273
1274extern const aarch64_opcode *
1275aarch64_get_opcode (enum aarch64_op);
1276
1277/* Generate the string representation of an operand. */
1278extern void
1279aarch64_print_operand (char *, size_t, bfd_vma, const aarch64_opcode *,
7d02540a 1280 const aarch64_opnd_info *, int, int *, bfd_vma *,
38cf07a6
AC		 1281 char **,
1282 aarch64_feature_set features);
a06ea964
NC		 1283
1284/* Miscellaneous interface. */
1285
1286extern int
1287aarch64_operand_index (const enum aarch64_opnd *, enum aarch64_opnd);
1288
1289extern aarch64_opnd_qualifier_t
1290aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *, int,
1291 const aarch64_opnd_qualifier_t, int);
1292
a68f4cd2
TC		 1293extern bfd_boolean
1294aarch64_is_destructive_by_operands (const aarch64_opcode *);
1295
a06ea964
NC		 1296extern int
1297aarch64_num_of_operands (const aarch64_opcode *);
1298
1299extern int
1300aarch64_stack_pointer_p (const aarch64_opnd_info *);
1301
e141d84e
YQ		 1302extern int
1303aarch64_zero_register_p (const aarch64_opnd_info *);
a06ea964 1304
1d482394 1305extern enum err_type
561a72d4 1306aarch64_decode_insn (aarch64_insn, aarch64_inst *, bfd_boolean,
a68f4cd2
TC		 1307 aarch64_operand_error *);
1308
1309extern void
1310init_insn_sequence (const struct aarch64_inst *, aarch64_instr_sequence *);
36f4aab1 1311
a06ea964
NC		 1312/* Given an operand qualifier, return the expected data element size
1313 of a qualified operand. */
1314extern unsigned char
1315aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t);
1316
1317extern enum aarch64_operand_class
1318aarch64_get_operand_class (enum aarch64_opnd);
1319
1320extern const char *
1321aarch64_get_operand_name (enum aarch64_opnd);
1322
1323extern const char *
1324aarch64_get_operand_desc (enum aarch64_opnd);
1325
e950b345
RS		 1326extern bfd_boolean
1327aarch64_sve_dupm_mov_immediate_p (uint64_t, int);
1328
a06ea964
NC		 1329#ifdef DEBUG_AARCH64
1330extern int debug_dump;
1331
1332extern void
1333aarch64_verbose (const char *, ...) __attribute__ ((format (printf, 1, 2)));
1334
1335#define DEBUG_TRACE(M, ...) \
1336 { \
1337 if (debug_dump) \
1338 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1339 }
1340
1341#define DEBUG_TRACE_IF(C, M, ...) \
1342 { \
1343 if (debug_dump && (C)) \
1344 aarch64_verbose ("%s: " M ".", __func__, ##__VA_ARGS__); \
1345 }
1346#else /* !DEBUG_AARCH64 */
1347#define DEBUG_TRACE(M, ...) ;
1348#define DEBUG_TRACE_IF(C, M, ...) ;
1349#endif /* DEBUG_AARCH64 */
1350
245d2e3f
RS		 1351extern const char *const aarch64_sve_pattern_array[32];
1352extern const char *const aarch64_sve_prfop_array[16];
1353
d3e12b29
YQ		 1354#ifdef __cplusplus
1355}
1356#endif
1357
a06ea964 1358#endif /* OPCODE_AARCH64_H */
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