[thirdparty/binutils-gdb.git] / include / opcode / arc.h

/* Opcode table for the ARC.
   Copyright (C) 1994-2016 Free Software Foundation, Inc.

   Contributed by Claudiu Zissulescu (claziss@synopsys.com)

   This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   the GNU Binutils.

   GAS/GDB is free software; you can redistribute it and/or modify
   it under the terms of the GNU General Public License as published by
   the Free Software Foundation; either version 3, or (at your option)
   any later version.

   GAS/GDB is distributed in the hope that it will be useful,
   but WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
   GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GAS or GDB; see the file COPYING3.  If not, write to
   the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

#ifndef OPCODE_ARC_H
#define OPCODE_ARC_H

#ifndef MAX_INSN_ARGS
#define MAX_INSN_ARGS	     6
#endif

#ifndef MAX_INSN_FLGS
#define MAX_INSN_FLGS	     3
#endif

/* Instruction Class.  */
typedef enum
  {
    ARITH,
    AUXREG,
    BRANCH,
    CONTROL,
    DSP,
    FLOAT,
    INVALID,
    JUMP,
    KERNEL,
    LOGICAL,
    MEMORY,
  } insn_class_t;

/* Instruction Subclass.  */
typedef enum
  {
    NONE,
    CVT,
    BTSCN,
    CD1,
    CD2,
    DIV,
    DP,
    MPY1E,
    MPY6E,
    MPY7E,
    MPY8E,
    MPY9E,
    SHFT1,
    SHFT2,
    SWAP,
    SP
  } insn_subclass_t;

/* Flags class.  */
typedef enum
  {
    FNONE,
    CND,  /* Conditional flags.  */
    WBM,  /* Write-back modes.  */
    FLG,  /* F Flag.  */
    SBP,  /* Static branch prediction.  */
    DLY,  /* Delay slot.  */
    DIF,  /* Bypass caches.  */
    SGX,  /* Sign extend modes.  */
    SZM   /* Data size modes.  */
  } flag_class_t;

/* The opcode table is an array of struct arc_opcode.  */
struct arc_opcode
{
  /* The opcode name.  */
  const char *name;

  /* The opcode itself.  Those bits which will be filled in with
     operands are zeroes.  */
  unsigned opcode;

  /* The opcode mask.  This is used by the disassembler.  This is a
     mask containing ones indicating those bits which must match the
     opcode field, and zeroes indicating those bits which need not
     match (and are presumably filled in by operands).  */
  unsigned mask;

  /* One bit flags for the opcode.  These are primarily used to
     indicate specific processors and environments support the
     instructions.  The defined values are listed below.  */
  unsigned cpu;

  /* The instruction class.  This is used by gdb.  */
  insn_class_t class;

  /* The instruction subclass.  */
  insn_subclass_t subclass;

  /* An array of operand codes.  Each code is an index into the
     operand table.  They appear in the order which the operands must
     appear in assembly code, and are terminated by a zero.  */
  unsigned char operands[MAX_INSN_ARGS + 1];

  /* An array of flag codes.  Each code is an index into the flag
     table.  They appear in the order which the flags must appear in
     assembly code, and are terminated by a zero.  */
  unsigned char flags[MAX_INSN_FLGS + 1];
};

/* The table itself is sorted by major opcode number, and is otherwise
   in the order in which the disassembler should consider
   instructions.  */
extern const struct arc_opcode arc_opcodes[];
extern const unsigned arc_num_opcodes;

/* CPU Availability.  */
#define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
#define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
#define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
#define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
#define ARC_OPCODE_NPS400   0x0010  /* NPS400 specific insns.  */

/* CPU extensions.  */
#define ARC_EA       0x0001
#define ARC_CD       0x0001    /* Mutual exclusive with EA.  */
#define ARC_LLOCK    0x0002
#define ARC_ATOMIC   0x0002    /* Mutual exclusive with LLOCK.  */
#define ARC_MPY      0x0004
#define ARC_MULT     0x0004

/* Floating point support.  */
#define ARC_DPFP     0x0010
#define ARC_SPFP     0x0020
#define ARC_FPU      0x0030

/* NORM & SWAP.  */
#define ARC_SWAP     0x0100
#define ARC_NORM     0x0200
#define ARC_BSCAN    0x0200

/* A7 specific.  */
#define ARC_UIX      0x1000
#define ARC_TSTAMP   0x1000

/* A6 specific.  */
#define ARC_VBFDW    0x1000
#define ARC_BARREL   0x1000
#define ARC_DSPA     0x1000

/* EM specific.  */
#define ARC_SHIFT    0x1000

/* V2 specific.  */
#define ARC_INTR     0x1000
#define ARC_DIV      0x1000

/* V1 specific.  */
#define ARC_XMAC     0x1000
#define ARC_CRC      0x1000

/* A macro to check for short instructions.  */
#define ARC_SHORT(mask)				\
  (((mask) & 0xFFFF0000) ? 0 : 1)

/* The operands table is an array of struct arc_operand.  */
struct arc_operand
{
  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* The default relocation type for this operand.  */
  signed int default_reloc;

  /* One bit syntax flags.  */
  unsigned int flags;

  /* Insertion function.  This is used by the assembler.  To insert an
     operand value into an instruction, check this field.

     If it is NULL, execute
	 i |= (op & ((1 << o->bits) - 1)) << o->shift;
     (i is the instruction which we are filling in, o is a pointer to
     this structure, and op is the opcode value; this assumes twos
     complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction and the operand value.	 It will return the new value
     of the instruction.  If the ERRMSG argument is not NULL, then if
     the operand value is illegal, *ERRMSG will be set to a warning
     string (the operand will be inserted in any case).	 If the
     operand value is legal, *ERRMSG will be unchanged (most operands
     can accept any value).  */
  unsigned (*insert) (unsigned instruction, int op, const char **errmsg);

  /* Extraction function.  This is used by the disassembler.  To
     extract this operand type from an instruction, check this field.

     If it is NULL, compute
	 op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	 if ((o->flags & ARC_OPERAND_SIGNED) != 0
	     && (op & (1 << (o->bits - 1))) != 0)
	   op -= 1 << o->bits;
     (i is the instruction, o is a pointer to this structure, and op
     is the result; this assumes twos complement arithmetic).

     If this field is not NULL, then simply call it with the
     instruction value.	 It will return the value of the operand.  If
     the INVALID argument is not NULL, *INVALID will be set to
     TRUE if this operand type can not actually be extracted from
     this operand (i.e., the instruction does not match).  If the
     operand is valid, *INVALID will not be changed.  */
  int (*extract) (unsigned instruction, bfd_boolean *invalid);
};

/* Elements in the table are retrieved by indexing with values from
   the operands field of the arc_opcodes table.  */
extern const struct arc_operand arc_operands[];
extern const unsigned arc_num_operands;
extern const unsigned arc_Toperand;
extern const unsigned arc_NToperand;

/* Values defined for the flags field of a struct arc_operand.  */

/* This operand does not actually exist in the assembler input.  This
   is used to support extended mnemonics, for which two operands fields
   are identical.  The assembler should call the insert function with
   any op value.  The disassembler should call the extract function,
   ignore the return value, and check the value placed in the invalid
   argument.  */
#define ARC_OPERAND_FAKE	0x0001

/* This operand names an integer register.  */
#define ARC_OPERAND_IR		0x0002

/* This operand takes signed values.  */
#define ARC_OPERAND_SIGNED	0x0004

/* This operand takes unsigned values.  This exists primarily so that
   a flags value of 0 can be treated as end-of-arguments.  */
#define ARC_OPERAND_UNSIGNED	0x0008

/* This operand takes long immediate values.  */
#define ARC_OPERAND_LIMM	0x0010

/* This operand is identical like the previous one.  */
#define ARC_OPERAND_DUPLICATE   0x0020

/* This operand is PC relative.  Used for internal relocs.  */
#define ARC_OPERAND_PCREL       0x0040

/* This operand is truncated.  The truncation is done accordingly to
   operand alignment attribute.  */
#define ARC_OPERAND_TRUNCATE    0x0080

/* This operand is 16bit aligned.  */
#define ARC_OPERAND_ALIGNED16   0x0100

/* This operand is 32bit aligned.  */
#define ARC_OPERAND_ALIGNED32   0x0200

/* This operand can be ignored by matching process if it is not
   present.  */
#define ARC_OPERAND_IGNORE      0x0400

/* Don't check the range when matching.	 */
#define ARC_OPERAND_NCHK	0x0800

/* Mark the braket possition.  */
#define ARC_OPERAND_BRAKET      0x1000

/* Mask for selecting the type for typecheck purposes.  */
#define ARC_OPERAND_TYPECHECK_MASK		\
  (ARC_OPERAND_IR |				\
   ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | 	\
   ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET)

/* The flags structure.  */
struct arc_flag_operand
{
  /* The flag name.  */
  const char *name;

  /* The flag code.  */
  unsigned code;

  /* The number of bits in the operand.  */
  unsigned int bits;

  /* How far the operand is left shifted in the instruction.  */
  unsigned int shift;

  /* Available for disassembler.  */
  unsigned char favail;
};

/* The flag operands table.  */
extern const struct arc_flag_operand arc_flag_operands[];
extern const unsigned arc_num_flag_operands;

/* The flag's class structure.  */
struct arc_flag_class
{
  /* Flag class.  */
  flag_class_t class;

  /* List of valid flags (codes).  */
  unsigned flags[256];
};

extern const struct arc_flag_class arc_flag_classes[];

/* Structure for special cases.  */
struct arc_flag_special
{
  /* Name of special case instruction.  */
  const char *name;

  /* List of flags applicable for special case instruction.  */
  unsigned flags[32];
};

extern const struct arc_flag_special arc_flag_special_cases[];
extern const unsigned arc_num_flag_special;

/* Relocation equivalence structure.  */
struct arc_reloc_equiv_tab
{
  const char * name;	   /* String to lookup.  */
  const char * mnemonic;   /* Extra matching condition.  */
  unsigned     flags[32];  /* Extra matching condition.  */
  signed int   oldreloc;   /* Old relocation.  */
  signed int   newreloc;   /* New relocation.  */
};

extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
extern const unsigned arc_num_equiv_tab;

/* Structure for operand operations for pseudo/alias instructions.  */
struct arc_operand_operation
{
  /* The index for operand from operand array.  */
  unsigned operand_idx;

  /* Defines if it needs the operand inserted by the assembler or
     whether this operand comes from the pseudo instruction's
     operands.  */
  unsigned char needs_insert;

  /* Count we have to add to the operand.  Use negative number to
     subtract from the operand.  Also use this number to add to 0 if
     the operand needs to be inserted (i.e. needs_insert == 1).  */
  int count;

  /* Index of the operand to swap with.  To be done AFTER applying
     inc_count.  */
  unsigned swap_operand_idx;
};

/* Structure for pseudo/alias instructions.  */
struct arc_pseudo_insn
{
  /* Mnemonic for pseudo/alias insn.  */
  const char *mnemonic_p;

  /* Mnemonic for real instruction.  */
  const char *mnemonic_r;

  /* Flag that will have to be added (if any).  */
  const char *flag_r;

  /* Amount of operands.  */
  unsigned operand_cnt;

  /* Array of operand operations.  */
  struct arc_operand_operation operand[6];
};

extern const struct arc_pseudo_insn arc_pseudo_insns[];
extern const unsigned arc_num_pseudo_insn;

/* Structure for AUXILIARY registers.  */
struct arc_aux_reg
{
  /* Register address.  */
  int address;

 /* Register name.  */
  const char *name;

  /* Size of the string.  */
  size_t length;
};

extern const struct arc_aux_reg arc_aux_regs[];
extern const unsigned arc_num_aux_regs;

extern const struct arc_opcode arc_relax_opcodes[];
extern const unsigned arc_num_relax_opcodes;

#endif /* OPCODE_ARC_H */
Commit	Line	Data
252b5132	1	/* Opcode table for the ARC.
6f2750fe	2	Copyright (C) 1994-2016 Free Software Foundation, Inc.
886a2506 NC	3
886a2506 NC	4	Contributed by Claudiu Zissulescu (claziss@synopsys.com)
252b5132	5
0d2bcfaf NC	6	This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
0d2bcfaf NC	7	the GNU Binutils.
252b5132	8
0d2bcfaf NC	9	GAS/GDB is free software; you can redistribute it and/or modify
0d2bcfaf NC	10	it under the terms of the GNU General Public License as published by
e4e42b45	11	the Free Software Foundation; either version 3, or (at your option)
0d2bcfaf	12	any later version.
252b5132	13
0d2bcfaf NC	14	GAS/GDB is distributed in the hope that it will be useful,
0d2bcfaf NC	15	but WITHOUT ANY WARRANTY; without even the implied warranty of
886a2506	16	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
0d2bcfaf NC	17	GNU General Public License for more details.
	18
	19	You should have received a copy of the GNU General Public License
e4e42b45	20	along with GAS or GDB; see the file COPYING3. If not, write to
e172dbf8 NC	21	the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
e172dbf8 NC	22	MA 02110-1301, USA. */
252b5132	23
886a2506 NC	24	#ifndef OPCODE_ARC_H
	25	#define OPCODE_ARC_H
	26
4670103e	27	#ifndef MAX_INSN_ARGS
886a2506	28	#define MAX_INSN_ARGS 6
4670103e CZ	29	#endif
	30
	31	#ifndef MAX_INSN_FLGS
886a2506	32	#define MAX_INSN_FLGS 3
4670103e	33	#endif
886a2506 NC	34
	35	/* Instruction Class. */
	36	typedef enum
	37	{
	38	ARITH,
	39	AUXREG,
	40	BRANCH,
	41	CONTROL,
	42	DSP,
	43	FLOAT,
	44	INVALID,
	45	JUMP,
	46	KERNEL,
	47	LOGICAL,
	48	MEMORY,
	49	} insn_class_t;
	50
	51	/* Instruction Subclass. */
	52	typedef enum
	53	{
	54	NONE,
	55	CVT,
	56	BTSCN,
	57	CD1,
	58	CD2,
	59	DIV,
	60	DP,
	61	MPY1E,
	62	MPY6E,
	63	MPY7E,
	64	MPY8E,
	65	MPY9E,
	66	SHFT1,
	67	SHFT2,
	68	SWAP,
	69	SP
	70	} insn_subclass_t;
	71
	72	/* Flags class. */
	73	typedef enum
	74	{
	75	FNONE,
	76	CND, /* Conditional flags. */
	77	WBM, /* Write-back modes. */
	78	FLG, /* F Flag. */
	79	SBP, /* Static branch prediction. */
	80	DLY, /* Delay slot. */
	81	DIF, /* Bypass caches. */
	82	SGX, /* Sign extend modes. */
	83	SZM /* Data size modes. */
	84	} flag_class_t;
	85
	86	/* The opcode table is an array of struct arc_opcode. */
	87	struct arc_opcode
	88	{
	89	/* The opcode name. */
	90	const char *name;
	91
	92	/* The opcode itself. Those bits which will be filled in with
	93	operands are zeroes. */
	94	unsigned opcode;
	95
	96	/* The opcode mask. This is used by the disassembler. This is a
	97	mask containing ones indicating those bits which must match the
98	opcode field, and zeroes indicating those bits which need not
99	match (and are presumably filled in by operands). */
100	unsigned mask;
101
102	/* One bit flags for the opcode. These are primarily used to
103	indicate specific processors and environments support the
104	instructions. The defined values are listed below. */
105	unsigned cpu;
106
107	/* The instruction class. This is used by gdb. */
108	insn_class_t class;
109
110	/* The instruction subclass. */
111	insn_subclass_t subclass;
112
113	/* An array of operand codes. Each code is an index into the
114	operand table. They appear in the order which the operands must
115	appear in assembly code, and are terminated by a zero. */
116	unsigned char operands[MAX_INSN_ARGS + 1];
117
118	/* An array of flag codes. Each code is an index into the flag
119	table. They appear in the order which the flags must appear in
120	assembly code, and are terminated by a zero. */
121	unsigned char flags[MAX_INSN_FLGS + 1];
122	};
252b5132	123
886a2506 NC	124	/* The table itself is sorted by major opcode number, and is otherwise
	125	in the order in which the disassembler should consider
	126	instructions. */
	127	extern const struct arc_opcode arc_opcodes[];
	128	extern const unsigned arc_num_opcodes;
	129
	130	/* CPU Availability. */
	131	#define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */
	132	#define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */
	133	#define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */
	134	#define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */
8699fc3e	135	#define ARC_OPCODE_NPS400 0x0010 /* NPS400 specific insns. */
886a2506 NC	136
	137	/* CPU extensions. */
	138	#define ARC_EA 0x0001
	139	#define ARC_CD 0x0001 /* Mutual exclusive with EA. */
	140	#define ARC_LLOCK 0x0002
	141	#define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */
	142	#define ARC_MPY 0x0004
	143	#define ARC_MULT 0x0004
	144
	145	/* Floating point support. */
	146	#define ARC_DPFP 0x0010
	147	#define ARC_SPFP 0x0020
	148	#define ARC_FPU 0x0030
	149
	150	/* NORM & SWAP. */
	151	#define ARC_SWAP 0x0100
	152	#define ARC_NORM 0x0200
	153	#define ARC_BSCAN 0x0200
	154
	155	/* A7 specific. */
	156	#define ARC_UIX 0x1000
	157	#define ARC_TSTAMP 0x1000
	158
	159	/* A6 specific. */
	160	#define ARC_VBFDW 0x1000
	161	#define ARC_BARREL 0x1000
	162	#define ARC_DSPA 0x1000
	163
	164	/* EM specific. */
	165	#define ARC_SHIFT 0x1000
	166
	167	/* V2 specific. */
	168	#define ARC_INTR 0x1000
	169	#define ARC_DIV 0x1000
	170
	171	/* V1 specific. */
	172	#define ARC_XMAC 0x1000
	173	#define ARC_CRC 0x1000
	174
886a2506 NC	175	/* A macro to check for short instructions. */
	176	#define ARC_SHORT(mask) \
	177	(((mask) & 0xFFFF0000) ? 0 : 1)
	178
	179	/* The operands table is an array of struct arc_operand. */
	180	struct arc_operand
	181	{
	182	/* The number of bits in the operand. */
	183	unsigned int bits;
	184
	185	/* How far the operand is left shifted in the instruction. */
	186	unsigned int shift;
	187
	188	/* The default relocation type for this operand. */
	189	signed int default_reloc;
	190
	191	/* One bit syntax flags. */
	192	unsigned int flags;
	193
	194	/* Insertion function. This is used by the assembler. To insert an
	195	operand value into an instruction, check this field.
	196
	197	If it is NULL, execute
	198	i \|= (op & ((1 << o->bits) - 1)) << o->shift;
	199	(i is the instruction which we are filling in, o is a pointer to
	200	this structure, and op is the opcode value; this assumes twos
	201	complement arithmetic).
	202
	203	If this field is not NULL, then simply call it with the
	204	instruction and the operand value. It will return the new value
	205	of the instruction. If the ERRMSG argument is not NULL, then if
	206	the operand value is illegal, *ERRMSG will be set to a warning
	207	string (the operand will be inserted in any case). If the
	208	operand value is legal, *ERRMSG will be unchanged (most operands
	209	can accept any value). */
	210	unsigned (insert) (unsigned instruction, int op, const char *errmsg);
	211
	212	/* Extraction function. This is used by the disassembler. To
	213	extract this operand type from an instruction, check this field.
	214
	215	If it is NULL, compute
	216	op = ((i) >> o->shift) & ((1 << o->bits) - 1);
	217	if ((o->flags & ARC_OPERAND_SIGNED) != 0
	218	&& (op & (1 << (o->bits - 1))) != 0)
	219	op -= 1 << o->bits;
	220	(i is the instruction, o is a pointer to this structure, and op
	221	is the result; this assumes twos complement arithmetic).
	222
	223	If this field is not NULL, then simply call it with the
	224	instruction value. It will return the value of the operand. If
	225	the INVALID argument is not NULL, *INVALID will be set to
	226	TRUE if this operand type can not actually be extracted from
	227	this operand (i.e., the instruction does not match). If the
	228	operand is valid, INVALID will not be changed. /
	229	int (extract) (unsigned instruction, bfd_boolean invalid);
	230	};
0d2bcfaf	231
886a2506 NC	232	/* Elements in the table are retrieved by indexing with values from
	233	the operands field of the arc_opcodes table. */
	234	extern const struct arc_operand arc_operands[];
	235	extern const unsigned arc_num_operands;
	236	extern const unsigned arc_Toperand;
	237	extern const unsigned arc_NToperand;
252b5132	238
886a2506	239	/* Values defined for the flags field of a struct arc_operand. */
0d2bcfaf	240
886a2506 NC	241	/* This operand does not actually exist in the assembler input. This
	242	is used to support extended mnemonics, for which two operands fields
	243	are identical. The assembler should call the insert function with
	244	any op value. The disassembler should call the extract function,
	245	ignore the return value, and check the value placed in the invalid
	246	argument. */
	247	#define ARC_OPERAND_FAKE 0x0001
252b5132	248
886a2506 NC	249	/* This operand names an integer register. */
886a2506 NC	250	#define ARC_OPERAND_IR 0x0002
0d2bcfaf	251
886a2506 NC	252	/* This operand takes signed values. */
886a2506 NC	253	#define ARC_OPERAND_SIGNED 0x0004
252b5132	254
886a2506 NC	255	/* This operand takes unsigned values. This exists primarily so that
	256	a flags value of 0 can be treated as end-of-arguments. */
	257	#define ARC_OPERAND_UNSIGNED 0x0008
252b5132	258
886a2506 NC	259	/* This operand takes long immediate values. */
886a2506 NC	260	#define ARC_OPERAND_LIMM 0x0010
252b5132	261
886a2506 NC	262	/* This operand is identical like the previous one. */
886a2506 NC	263	#define ARC_OPERAND_DUPLICATE 0x0020
0d2bcfaf	264
886a2506 NC	265	/* This operand is PC relative. Used for internal relocs. */
886a2506 NC	266	#define ARC_OPERAND_PCREL 0x0040
0d2bcfaf	267
886a2506 NC	268	/* This operand is truncated. The truncation is done accordingly to
	269	operand alignment attribute. */
	270	#define ARC_OPERAND_TRUNCATE 0x0080
0d2bcfaf	271
886a2506 NC	272	/* This operand is 16bit aligned. */
886a2506 NC	273	#define ARC_OPERAND_ALIGNED16 0x0100
0d2bcfaf	274
886a2506 NC	275	/* This operand is 32bit aligned. */
886a2506 NC	276	#define ARC_OPERAND_ALIGNED32 0x0200
0d2bcfaf	277
886a2506 NC	278	/* This operand can be ignored by matching process if it is not
	279	present. */
	280	#define ARC_OPERAND_IGNORE 0x0400
0d2bcfaf	281
886a2506 NC	282	/* Don't check the range when matching. */
886a2506 NC	283	#define ARC_OPERAND_NCHK 0x0800
0d2bcfaf	284
886a2506 NC	285	/* Mark the braket possition. */
886a2506 NC	286	#define ARC_OPERAND_BRAKET 0x1000
252b5132	287
886a2506 NC	288	/* Mask for selecting the type for typecheck purposes. */
	289	#define ARC_OPERAND_TYPECHECK_MASK \
	290	(ARC_OPERAND_IR \| \
	291	ARC_OPERAND_LIMM \| ARC_OPERAND_SIGNED \| \
	292	ARC_OPERAND_UNSIGNED \| ARC_OPERAND_BRAKET)
252b5132	293
886a2506 NC	294	/* The flags structure. */
	295	struct arc_flag_operand
	296	{
	297	/* The flag name. */
	298	const char *name;
0d2bcfaf	299
886a2506 NC	300	/* The flag code. */
886a2506 NC	301	unsigned code;
252b5132	302
886a2506 NC	303	/* The number of bits in the operand. */
886a2506 NC	304	unsigned int bits;
252b5132	305
886a2506 NC	306	/* How far the operand is left shifted in the instruction. */
886a2506 NC	307	unsigned int shift;
252b5132	308
886a2506 NC	309	/* Available for disassembler. */
886a2506 NC	310	unsigned char favail;
84037f8c KD	311	};
84037f8c KD	312
886a2506 NC	313	/* The flag operands table. */
	314	extern const struct arc_flag_operand arc_flag_operands[];
	315	extern const unsigned arc_num_flag_operands;
0d2bcfaf	316
886a2506 NC	317	/* The flag's class structure. */
	318	struct arc_flag_class
	319	{
	320	/* Flag class. */
	321	flag_class_t class;
252b5132	322
886a2506 NC	323	/* List of valid flags (codes). */
	324	unsigned flags[256];
	325	};
252b5132	326
886a2506	327	extern const struct arc_flag_class arc_flag_classes[];
252b5132	328
886a2506 NC	329	/* Structure for special cases. */
	330	struct arc_flag_special
	331	{
	332	/* Name of special case instruction. */
	333	const char *name;
252b5132	334
886a2506 NC	335	/* List of flags applicable for special case instruction. */
	336	unsigned flags[32];
	337	};
252b5132	338
886a2506 NC	339	extern const struct arc_flag_special arc_flag_special_cases[];
	340	extern const unsigned arc_num_flag_special;
	341
	342	/* Relocation equivalence structure. */
	343	struct arc_reloc_equiv_tab
	344	{
	345	const char * name; /* String to lookup. */
	346	const char * mnemonic; /* Extra matching condition. */
24b368f8	347	unsigned flags[32]; /* Extra matching condition. */
886a2506 NC	348	signed int oldreloc; /* Old relocation. */
	349	signed int newreloc; /* New relocation. */
	350	};
252b5132	351
886a2506 NC	352	extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
886a2506 NC	353	extern const unsigned arc_num_equiv_tab;
252b5132	354
886a2506 NC	355	/* Structure for operand operations for pseudo/alias instructions. */
	356	struct arc_operand_operation
	357	{
	358	/* The index for operand from operand array. */
	359	unsigned operand_idx;
252b5132	360
886a2506 NC	361	/* Defines if it needs the operand inserted by the assembler or
	362	whether this operand comes from the pseudo instruction's
	363	operands. */
	364	unsigned char needs_insert;
252b5132	365
886a2506 NC	366	/* Count we have to add to the operand. Use negative number to
	367	subtract from the operand. Also use this number to add to 0 if
	368	the operand needs to be inserted (i.e. needs_insert == 1). */
	369	int count;
252b5132	370
886a2506 NC	371	/* Index of the operand to swap with. To be done AFTER applying
	372	inc_count. */
	373	unsigned swap_operand_idx;
252b5132 RH	374	};
252b5132 RH	375
886a2506 NC	376	/* Structure for pseudo/alias instructions. */
	377	struct arc_pseudo_insn
	378	{
	379	/* Mnemonic for pseudo/alias insn. */
	380	const char *mnemonic_p;
252b5132	381
886a2506 NC	382	/* Mnemonic for real instruction. */
886a2506 NC	383	const char *mnemonic_r;
252b5132	384
886a2506 NC	385	/* Flag that will have to be added (if any). */
886a2506 NC	386	const char *flag_r;
252b5132	387
886a2506 NC	388	/* Amount of operands. */
886a2506 NC	389	unsigned operand_cnt;
252b5132	390
886a2506 NC	391	/* Array of operand operations. */
	392	struct arc_operand_operation operand[6];
	393	};
252b5132	394
886a2506 NC	395	extern const struct arc_pseudo_insn arc_pseudo_insns[];
886a2506 NC	396	extern const unsigned arc_num_pseudo_insn;
252b5132	397
886a2506 NC	398	/* Structure for AUXILIARY registers. */
	399	struct arc_aux_reg
	400	{
	401	/* Register address. */
	402	int address;
252b5132	403
886a2506 NC	404	/* Register name. */
	405	const char *name;
	406
	407	/* Size of the string. */
	408	size_t length;
	409	};
	410
	411	extern const struct arc_aux_reg arc_aux_regs[];
	412	extern const unsigned arc_num_aux_regs;
	413
4670103e CZ	414	extern const struct arc_opcode arc_relax_opcodes[];
	415	extern const unsigned arc_num_relax_opcodes;
	416
886a2506	417	#endif /* OPCODE_ARC_H */