[thirdparty/binutils-gdb.git] / include / opcode / arm.h

/* ARM assembler/disassembler support.
   Copyright 2004, 2010 Free Software Foundation, Inc.

   This file is part of GDB and GAS.

   GDB and GAS are free software; you can redistribute it and/or
   modify it under the terms of the GNU General Public License as
   published by the Free Software Foundation; either version 3, or (at
   your option) any later version.

   GDB and GAS are distributed in the hope that it will be useful, but
   WITHOUT ANY WARRANTY; without even the implied warranty of
   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
   General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with GDB or GAS; see the file COPYING3.  If not, write to the
   Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
   MA 02110-1301, USA.  */

/* The following bitmasks control CPU extensions:  */
#define ARM_EXT_V1	 0x00000001	/* All processors (core set).  */
#define ARM_EXT_V2	 0x00000002	/* Multiply instructions.  */
#define ARM_EXT_V2S	 0x00000004	/* SWP instructions.       */
#define ARM_EXT_V3	 0x00000008	/* MSR MRS.                */
#define ARM_EXT_V3M	 0x00000010	/* Allow long multiplies.  */
#define ARM_EXT_V4	 0x00000020	/* Allow half word loads.  */
#define ARM_EXT_V4T	 0x00000040	/* Thumb.                  */
#define ARM_EXT_V5	 0x00000080	/* Allow CLZ, etc.         */
#define ARM_EXT_V5T	 0x00000100	/* Improved interworking.  */
#define ARM_EXT_V5ExP	 0x00000200	/* DSP core set.           */
#define ARM_EXT_V5E	 0x00000400	/* DSP Double transfers.   */
#define ARM_EXT_V5J	 0x00000800	/* Jazelle extension.	   */
#define ARM_EXT_V6       0x00001000     /* ARM V6.                 */
#define ARM_EXT_V6K      0x00002000     /* ARM V6K.                */
/*			 0x00004000	   Was ARM V6Z.            */
#define ARM_EXT_V6T2	 0x00008000	/* Thumb-2.                */
#define ARM_EXT_DIV	 0x00010000	/* Integer division.       */
/* The 'M' in Arm V7M stands for Microcontroller.
   On earlier architecture variants it stands for Multiply.  */
#define ARM_EXT_V5E_NOTM 0x00020000	/* Arm V5E but not Arm V7M. */
#define ARM_EXT_V6_NOTM	 0x00040000	/* Arm V6 but not Arm V7M. */
#define ARM_EXT_V7	 0x00080000	/* Arm V7.                 */
#define ARM_EXT_V7A	 0x00100000	/* Arm V7A.                */
#define ARM_EXT_V7R	 0x00200000	/* Arm V7R.                */
#define ARM_EXT_V7M	 0x00400000	/* Arm V7M.                */
#define ARM_EXT_V6M	 0x00800000	/* ARM V6M.		    */
#define ARM_EXT_BARRIER	 0x01000000	/* DSB/DMB/ISB.		    */
#define ARM_EXT_THUMB_MSR 0x02000000	/* Thumb MSR/MRS.	    */
#define ARM_EXT_V6_DSP 0x04000000	/* ARM v6 (DSP-related),
					   not in v7-M.  */
#define ARM_EXT_MP       0x08000000     /* Multiprocessing Extensions.  */
#define ARM_EXT_SEC	 0x10000000	/* Security extensions.  */
#define ARM_EXT_OS	 0x20000000	/* OS Extensions.  */
#define ARM_EXT_ADIV	 0x40000000	/* Integer divide extensions in ARM 
					   state.  */

/* Co-processor space extensions.  */
#define ARM_CEXT_XSCALE   0x00000001	/* Allow MIA etc.          */
#define ARM_CEXT_MAVERICK 0x00000002	/* Use Cirrus/DSP coprocessor.  */
#define ARM_CEXT_IWMMXT   0x00000004    /* Intel Wireless MMX technology coprocessor.   */
#define ARM_CEXT_IWMMXT2  0x00000008    /* Intel Wireless MMX technology coprocessor version 2.   */

#define FPU_ENDIAN_PURE	 0x80000000	/* Pure-endian doubles.	      */
#define FPU_ENDIAN_BIG	 0		/* Double words-big-endian.   */
#define FPU_FPA_EXT_V1	 0x40000000	/* Base FPA instruction set.  */
#define FPU_FPA_EXT_V2	 0x20000000	/* LFM/SFM.		      */
#define FPU_MAVERICK	 0x10000000	/* Cirrus Maverick.	      */
#define FPU_VFP_EXT_V1xD 0x08000000	/* Base VFP instruction set.  */
#define FPU_VFP_EXT_V1	 0x04000000	/* Double-precision insns.    */
#define FPU_VFP_EXT_V2	 0x02000000	/* ARM10E VFPr1.	      */
#define FPU_VFP_EXT_V3xD 0x01000000	/* VFPv3 single-precision.    */
#define FPU_VFP_EXT_V3	 0x00800000	/* VFPv3 double-precision.    */
#define FPU_NEON_EXT_V1	 0x00400000	/* Neon (SIMD) insns.	      */
#define FPU_VFP_EXT_D32  0x00200000	/* Registers D16-D31.	      */
#define FPU_VFP_EXT_FP16 0x00100000	/* Half-precision extensions. */
#define FPU_NEON_EXT_FMA 0x00080000	/* Neon fused multiply-add    */
#define FPU_VFP_EXT_FMA	 0x00040000	/* VFP fused multiply-add     */

/* Architectures are the sum of the base and extensions.  The ARM ARM (rev E)
   defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
   ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE.  To these we add
   three more to cover cores prior to ARM6.  Finally, there are cores which
   implement further extensions in the co-processor space.  */
#define ARM_AEXT_V1			  ARM_EXT_V1
#define ARM_AEXT_V2	(ARM_AEXT_V1	| ARM_EXT_V2)
#define ARM_AEXT_V2S	(ARM_AEXT_V2	| ARM_EXT_V2S)
#define ARM_AEXT_V3	(ARM_AEXT_V2S	| ARM_EXT_V3)
#define ARM_AEXT_V3M	(ARM_AEXT_V3	| ARM_EXT_V3M)
#define ARM_AEXT_V4xM	(ARM_AEXT_V3	| ARM_EXT_V4)
#define ARM_AEXT_V4	(ARM_AEXT_V3M	| ARM_EXT_V4)
#define ARM_AEXT_V4TxM	(ARM_AEXT_V4xM	| ARM_EXT_V4T)
#define ARM_AEXT_V4T	(ARM_AEXT_V4	| ARM_EXT_V4T)
#define ARM_AEXT_V5xM	(ARM_AEXT_V4xM	| ARM_EXT_V5)
#define ARM_AEXT_V5	(ARM_AEXT_V4	| ARM_EXT_V5)
#define ARM_AEXT_V5TxM	(ARM_AEXT_V5xM	| ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5T	(ARM_AEXT_V5	| ARM_EXT_V4T | ARM_EXT_V5T)
#define ARM_AEXT_V5TExP	(ARM_AEXT_V5T	| ARM_EXT_V5ExP)
#define ARM_AEXT_V5TE	(ARM_AEXT_V5TExP | ARM_EXT_V5E)
#define ARM_AEXT_V5TEJ	(ARM_AEXT_V5TE	| ARM_EXT_V5J)
#define ARM_AEXT_V6     (ARM_AEXT_V5TEJ | ARM_EXT_V6)
#define ARM_AEXT_V6K    (ARM_AEXT_V6    | ARM_EXT_V6K)
#define ARM_AEXT_V6Z    (ARM_AEXT_V6K	| ARM_EXT_SEC)
#define ARM_AEXT_V6ZK   (ARM_AEXT_V6K	| ARM_EXT_SEC)
#define ARM_AEXT_V6T2   (ARM_AEXT_V6 \
    | ARM_EXT_V6T2 | ARM_EXT_V6_NOTM | ARM_EXT_THUMB_MSR \
    | ARM_EXT_V6_DSP )
#define ARM_AEXT_V6KT2  (ARM_AEXT_V6T2 | ARM_EXT_V6K)
#define ARM_AEXT_V6ZT2  (ARM_AEXT_V6T2 | ARM_EXT_SEC)
#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 | ARM_EXT_V6K | ARM_EXT_SEC)
#define ARM_AEXT_V7_ARM	(ARM_AEXT_V6KT2 | ARM_EXT_V7 | ARM_EXT_BARRIER)
#define ARM_AEXT_V7A	(ARM_AEXT_V7_ARM | ARM_EXT_V7A)
#define ARM_AEXT_V7R	(ARM_AEXT_V7_ARM | ARM_EXT_V7R | ARM_EXT_DIV)
#define ARM_AEXT_NOTM \
  (ARM_AEXT_V4 | ARM_EXT_V5ExP | ARM_EXT_V5J | ARM_EXT_V6_NOTM \
   | ARM_EXT_V6_DSP )
#define ARM_AEXT_V6M \
  ((ARM_AEXT_V6K | ARM_EXT_BARRIER | ARM_EXT_V6M | ARM_EXT_THUMB_MSR) \
   & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V6SM (ARM_AEXT_V6M | ARM_EXT_OS)
#define ARM_AEXT_V7M \
  ((ARM_AEXT_V7_ARM | ARM_EXT_V6M | ARM_EXT_V7M | ARM_EXT_DIV) \
   & ~(ARM_AEXT_NOTM))
#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
#define ARM_AEXT_V7EM \
  (ARM_AEXT_V7M | ARM_EXT_V5ExP | ARM_EXT_V6_DSP)

/* Processors with specific extensions in the co-processor space.  */
#define ARM_ARCH_XSCALE	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
#define ARM_ARCH_IWMMXT	\
 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT)
#define ARM_ARCH_IWMMXT2	\
 ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE | ARM_CEXT_IWMMXT | ARM_CEXT_IWMMXT2)

#define FPU_VFP_V1xD	(FPU_VFP_EXT_V1xD | FPU_ENDIAN_PURE)
#define FPU_VFP_V1	(FPU_VFP_V1xD | FPU_VFP_EXT_V1)
#define FPU_VFP_V2	(FPU_VFP_V1 | FPU_VFP_EXT_V2)
#define FPU_VFP_V3D16	(FPU_VFP_V2 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_V3)
#define FPU_VFP_V3	(FPU_VFP_V3D16 | FPU_VFP_EXT_D32)
#define FPU_VFP_V3xD	(FPU_VFP_V1xD | FPU_VFP_EXT_V2 | FPU_VFP_EXT_V3xD)
#define FPU_VFP_V4D16	(FPU_VFP_V3D16 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4	(FPU_VFP_V3 | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD | FPU_VFP_EXT_FP16 | FPU_VFP_EXT_FMA)
#define FPU_VFP_HARD	(FPU_VFP_EXT_V1xD | FPU_VFP_EXT_V1 | FPU_VFP_EXT_V2 \
			 | FPU_VFP_EXT_V3xD | FPU_VFP_EXT_FMA | FPU_NEON_EXT_FMA \
                         | FPU_VFP_EXT_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_D32)
#define FPU_FPA		(FPU_FPA_EXT_V1 | FPU_FPA_EXT_V2)

/* Deprecated */
#define FPU_ARCH_VFP	ARM_FEATURE (0, FPU_ENDIAN_PURE)

#define FPU_ARCH_FPE	ARM_FEATURE (0, FPU_FPA_EXT_V1)
#define FPU_ARCH_FPA	ARM_FEATURE (0, FPU_FPA)

#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
#define FPU_ARCH_VFP_V1	  ARM_FEATURE (0, FPU_VFP_V1)
#define FPU_ARCH_VFP_V2	  ARM_FEATURE (0, FPU_VFP_V2)
#define FPU_ARCH_VFP_V3D16	ARM_FEATURE (0, FPU_VFP_V3D16)
#define FPU_ARCH_VFP_V3D16_FP16 \
  ARM_FEATURE (0, FPU_VFP_V3D16 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3	  ARM_FEATURE (0, FPU_VFP_V3)
#define FPU_ARCH_VFP_V3_FP16	ARM_FEATURE (0, FPU_VFP_V3 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_V3xD	ARM_FEATURE (0, FPU_VFP_V3xD)
#define FPU_ARCH_VFP_V3xD_FP16	ARM_FEATURE (0, FPU_VFP_V3xD | FPU_VFP_EXT_FP16)
#define FPU_ARCH_NEON_V1  ARM_FEATURE (0, FPU_NEON_EXT_V1)
#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
  ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1)
#define FPU_ARCH_NEON_FP16 \
  ARM_FEATURE (0, FPU_VFP_V3 | FPU_NEON_EXT_V1 | FPU_VFP_EXT_FP16)
#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
#define FPU_ARCH_NEON_VFP_V4 \
  ARM_FEATURE(0, FPU_VFP_V4 | FPU_NEON_EXT_V1 | FPU_NEON_EXT_FMA)

#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)

#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)

#define ARM_ARCH_V1	ARM_FEATURE (ARM_AEXT_V1, 0)
#define ARM_ARCH_V2	ARM_FEATURE (ARM_AEXT_V2, 0)
#define ARM_ARCH_V2S	ARM_FEATURE (ARM_AEXT_V2S, 0)
#define ARM_ARCH_V3	ARM_FEATURE (ARM_AEXT_V3, 0)
#define ARM_ARCH_V3M	ARM_FEATURE (ARM_AEXT_V3M, 0)
#define ARM_ARCH_V4xM	ARM_FEATURE (ARM_AEXT_V4xM, 0)
#define ARM_ARCH_V4	ARM_FEATURE (ARM_AEXT_V4, 0)
#define ARM_ARCH_V4TxM	ARM_FEATURE (ARM_AEXT_V4TxM, 0)
#define ARM_ARCH_V4T	ARM_FEATURE (ARM_AEXT_V4T, 0)
#define ARM_ARCH_V5xM	ARM_FEATURE (ARM_AEXT_V5xM, 0)
#define ARM_ARCH_V5	ARM_FEATURE (ARM_AEXT_V5, 0)
#define ARM_ARCH_V5TxM	ARM_FEATURE (ARM_AEXT_V5TxM, 0)
#define ARM_ARCH_V5T	ARM_FEATURE (ARM_AEXT_V5T, 0)
#define ARM_ARCH_V5TExP	ARM_FEATURE (ARM_AEXT_V5TExP, 0)
#define ARM_ARCH_V5TE	ARM_FEATURE (ARM_AEXT_V5TE, 0)
#define ARM_ARCH_V5TEJ	ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
#define ARM_ARCH_V6	ARM_FEATURE (ARM_AEXT_V6, 0)
#define ARM_ARCH_V6K	ARM_FEATURE (ARM_AEXT_V6K, 0)
#define ARM_ARCH_V6Z	ARM_FEATURE (ARM_AEXT_V6Z, 0)
#define ARM_ARCH_V6ZK	ARM_FEATURE (ARM_AEXT_V6ZK, 0)
#define ARM_ARCH_V6T2	ARM_FEATURE (ARM_AEXT_V6T2, 0)
#define ARM_ARCH_V6KT2	ARM_FEATURE (ARM_AEXT_V6KT2, 0)
#define ARM_ARCH_V6ZT2	ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
#define ARM_ARCH_V6ZKT2	ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
#define ARM_ARCH_V6M	ARM_FEATURE (ARM_AEXT_V6M, 0)
#define ARM_ARCH_V6SM	ARM_FEATURE (ARM_AEXT_V6SM, 0)
#define ARM_ARCH_V7	ARM_FEATURE (ARM_AEXT_V7, 0)
#define ARM_ARCH_V7A	ARM_FEATURE (ARM_AEXT_V7A, 0)
#define ARM_ARCH_V7R	ARM_FEATURE (ARM_AEXT_V7R, 0)
#define ARM_ARCH_V7M	ARM_FEATURE (ARM_AEXT_V7M, 0)
#define ARM_ARCH_V7EM	ARM_FEATURE (ARM_AEXT_V7EM, 0)

/* Some useful combinations:  */
#define ARM_ARCH_NONE	ARM_FEATURE (0, 0)
#define FPU_NONE	ARM_FEATURE (0, 0)
#define ARM_ANY		ARM_FEATURE (-1, 0)	/* Any basic core.  */
#define FPU_ANY_HARD	ARM_FEATURE (0, FPU_FPA | FPU_VFP_HARD | FPU_MAVERICK)
#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 | ARM_EXT_V7 | ARM_EXT_V7A | ARM_EXT_V7R | ARM_EXT_V7M | ARM_EXT_DIV, 0)
/* v7-a+sec.  */
#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_SEC, 0)
/* v7-a+mp+sec.  */
#define ARM_ARCH_V7A_MP_SEC \
			ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC, \
				     0)
/* v7-a+idiv+mp+sec.  */
#define ARM_ARCH_V7A_IDIV_MP_SEC \
			ARM_FEATURE (ARM_AEXT_V7A | ARM_EXT_MP | ARM_EXT_SEC \
				     | ARM_EXT_DIV | ARM_EXT_ADIV, 0)

/* There are too many feature bits to fit in a single word, so use a
   structure.  For simplicity we put all core features in one word and
   everything else in the other.  */
typedef struct
{
  unsigned long core;
  unsigned long coproc;
} arm_feature_set;

#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
  (((CPU).core & (FEAT).core) != 0 || ((CPU).coproc & (FEAT).coproc) != 0)

#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2)	\
  do {						\
    (TARG).core = (F1).core | (F2).core;	\
    (TARG).coproc = (F1).coproc | (F2).coproc;	\
  } while (0)

#define ARM_CLEAR_FEATURE(TARG,F1,F2)		\
  do {						\
    (TARG).core = (F1).core &~ (F2).core;	\
    (TARG).coproc = (F1).coproc &~ (F2).coproc;	\
  } while (0)

#define ARM_FEATURE(core, coproc) {(core), (coproc)}
Commit	Line	Data
b781e558	1	/* ARM assembler/disassembler support.
e4e42b45	2	Copyright 2004, 2010 Free Software Foundation, Inc.
b781e558 RE	3
	4	This file is part of GDB and GAS.
	5
	6	GDB and GAS are free software; you can redistribute it and/or
	7	modify it under the terms of the GNU General Public License as
e4e42b45	8	published by the Free Software Foundation; either version 3, or (at
b781e558 RE	9	your option) any later version.
	10
	11	GDB and GAS are distributed in the hope that it will be useful, but
	12	WITHOUT ANY WARRANTY; without even the implied warranty of
	13	MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
	14	General Public License for more details.
	15
	16	You should have received a copy of the GNU General Public License
e4e42b45 NC	17	along with GDB or GAS; see the file COPYING3. If not, write to the
	18	Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
	19	MA 02110-1301, USA. */
b781e558 RE	20
	21	/* The following bitmasks control CPU extensions: */
	22	#define ARM_EXT_V1 0x00000001 /* All processors (core set). */
	23	#define ARM_EXT_V2 0x00000002 /* Multiply instructions. */
	24	#define ARM_EXT_V2S 0x00000004 /* SWP instructions. */
	25	#define ARM_EXT_V3 0x00000008 /* MSR MRS. */
	26	#define ARM_EXT_V3M 0x00000010 /* Allow long multiplies. */
	27	#define ARM_EXT_V4 0x00000020 /* Allow half word loads. */
0a003adc	28	#define ARM_EXT_V4T 0x00000040 /* Thumb. */
b781e558	29	#define ARM_EXT_V5 0x00000080 /* Allow CLZ, etc. */
0a003adc	30	#define ARM_EXT_V5T 0x00000100 /* Improved interworking. */
b781e558 RE	31	#define ARM_EXT_V5ExP 0x00000200 /* DSP core set. */
	32	#define ARM_EXT_V5E 0x00000400 /* DSP Double transfers. */
	33	#define ARM_EXT_V5J 0x00000800 /* Jazelle extension. */
	34	#define ARM_EXT_V6 0x00001000 /* ARM V6. */
0dd132b6	35	#define ARM_EXT_V6K 0x00002000 /* ARM V6K. */
f4c65163	36	/* 0x00004000 Was ARM V6Z. */
0a003adc	37	#define ARM_EXT_V6T2 0x00008000 /* Thumb-2. */
62b3e311 PB	38	#define ARM_EXT_DIV 0x00010000 /* Integer division. */
	39	/* The 'M' in Arm V7M stands for Microcontroller.
	40	On earlier architecture variants it stands for Multiply. */
	41	#define ARM_EXT_V5E_NOTM 0x00020000 /* Arm V5E but not Arm V7M. */
	42	#define ARM_EXT_V6_NOTM 0x00040000 /* Arm V6 but not Arm V7M. */
	43	#define ARM_EXT_V7 0x00080000 /* Arm V7. */
	44	#define ARM_EXT_V7A 0x00100000 /* Arm V7A. */
	45	#define ARM_EXT_V7R 0x00200000 /* Arm V7R. */
	46	#define ARM_EXT_V7M 0x00400000 /* Arm V7M. */
7e806470 PB	47	#define ARM_EXT_V6M 0x00800000 /* ARM V6M. */
	48	#define ARM_EXT_BARRIER 0x01000000 /* DSB/DMB/ISB. */
	49	#define ARM_EXT_THUMB_MSR 0x02000000 /* Thumb MSR/MRS. */
9e3c6df6 PB	50	#define ARM_EXT_V6_DSP 0x04000000 /* ARM v6 (DSP-related),
9e3c6df6 PB	51	not in v7-M. */
60e5ef9f	52	#define ARM_EXT_MP 0x08000000 /* Multiprocessing Extensions. */
f4c65163	53	#define ARM_EXT_SEC 0x10000000 /* Security extensions. */
b2a5fbdc	54	#define ARM_EXT_OS 0x20000000 /* OS Extensions. */
eea54501 MGD	55	#define ARM_EXT_ADIV 0x40000000 /* Integer divide extensions in ARM
eea54501 MGD	56	state. */
b781e558 RE	57
b781e558 RE	58	/* Co-processor space extensions. */
e74cfd16 PB	59	#define ARM_CEXT_XSCALE 0x00000001 /* Allow MIA etc. */
	60	#define ARM_CEXT_MAVERICK 0x00000002 /* Use Cirrus/DSP coprocessor. */
	61	#define ARM_CEXT_IWMMXT 0x00000004 /* Intel Wireless MMX technology coprocessor. */
2d447fca	62	#define ARM_CEXT_IWMMXT2 0x00000008 /* Intel Wireless MMX technology coprocessor version 2. */
e74cfd16 PB	63
	64	#define FPU_ENDIAN_PURE 0x80000000 /* Pure-endian doubles. */
	65	#define FPU_ENDIAN_BIG 0 /* Double words-big-endian. */
	66	#define FPU_FPA_EXT_V1 0x40000000 /* Base FPA instruction set. */
	67	#define FPU_FPA_EXT_V2 0x20000000 /* LFM/SFM. */
	68	#define FPU_MAVERICK 0x10000000 /* Cirrus Maverick. */
	69	#define FPU_VFP_EXT_V1xD 0x08000000 /* Base VFP instruction set. */
	70	#define FPU_VFP_EXT_V1 0x04000000 /* Double-precision insns. */
	71	#define FPU_VFP_EXT_V2 0x02000000 /* ARM10E VFPr1. */
62f3b8c8 PB	72	#define FPU_VFP_EXT_V3xD 0x01000000 /* VFPv3 single-precision. */
	73	#define FPU_VFP_EXT_V3 0x00800000 /* VFPv3 double-precision. */
	74	#define FPU_NEON_EXT_V1 0x00400000 /* Neon (SIMD) insns. */
	75	#define FPU_VFP_EXT_D32 0x00200000 /* Registers D16-D31. */
	76	#define FPU_VFP_EXT_FP16 0x00100000 /* Half-precision extensions. */
	77	#define FPU_NEON_EXT_FMA 0x00080000 /* Neon fused multiply-add */
	78	#define FPU_VFP_EXT_FMA 0x00040000 /* VFP fused multiply-add */
b781e558 RE	79
	80	/* Architectures are the sum of the base and extensions. The ARM ARM (rev E)
	81	defines the following: ARMv3, ARMv3M, ARMv4xM, ARMv4, ARMv4TxM, ARMv4T,
	82	ARMv5xM, ARMv5, ARMv5TxM, ARMv5T, ARMv5TExP, ARMv5TE. To these we add
	83	three more to cover cores prior to ARM6. Finally, there are cores which
	84	implement further extensions in the co-processor space. */
e74cfd16 PB	85	#define ARM_AEXT_V1 ARM_EXT_V1
	86	#define ARM_AEXT_V2 (ARM_AEXT_V1 \| ARM_EXT_V2)
	87	#define ARM_AEXT_V2S (ARM_AEXT_V2 \| ARM_EXT_V2S)
	88	#define ARM_AEXT_V3 (ARM_AEXT_V2S \| ARM_EXT_V3)
	89	#define ARM_AEXT_V3M (ARM_AEXT_V3 \| ARM_EXT_V3M)
	90	#define ARM_AEXT_V4xM (ARM_AEXT_V3 \| ARM_EXT_V4)
	91	#define ARM_AEXT_V4 (ARM_AEXT_V3M \| ARM_EXT_V4)
	92	#define ARM_AEXT_V4TxM (ARM_AEXT_V4xM \| ARM_EXT_V4T)
	93	#define ARM_AEXT_V4T (ARM_AEXT_V4 \| ARM_EXT_V4T)
	94	#define ARM_AEXT_V5xM (ARM_AEXT_V4xM \| ARM_EXT_V5)
	95	#define ARM_AEXT_V5 (ARM_AEXT_V4 \| ARM_EXT_V5)
	96	#define ARM_AEXT_V5TxM (ARM_AEXT_V5xM \| ARM_EXT_V4T \| ARM_EXT_V5T)
	97	#define ARM_AEXT_V5T (ARM_AEXT_V5 \| ARM_EXT_V4T \| ARM_EXT_V5T)
	98	#define ARM_AEXT_V5TExP (ARM_AEXT_V5T \| ARM_EXT_V5ExP)
	99	#define ARM_AEXT_V5TE (ARM_AEXT_V5TExP \| ARM_EXT_V5E)
	100	#define ARM_AEXT_V5TEJ (ARM_AEXT_V5TE \| ARM_EXT_V5J)
	101	#define ARM_AEXT_V6 (ARM_AEXT_V5TEJ \| ARM_EXT_V6)
	102	#define ARM_AEXT_V6K (ARM_AEXT_V6 \| ARM_EXT_V6K)
f4c65163 MGD	103	#define ARM_AEXT_V6Z (ARM_AEXT_V6K \| ARM_EXT_SEC)
f4c65163 MGD	104	#define ARM_AEXT_V6ZK (ARM_AEXT_V6K \| ARM_EXT_SEC)
7e806470	105	#define ARM_AEXT_V6T2 (ARM_AEXT_V6 \
9e3c6df6 PB	106	\| ARM_EXT_V6T2 \| ARM_EXT_V6_NOTM \| ARM_EXT_THUMB_MSR \
9e3c6df6 PB	107	\| ARM_EXT_V6_DSP )
62b3e311	108	#define ARM_AEXT_V6KT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K)
f4c65163 MGD	109	#define ARM_AEXT_V6ZT2 (ARM_AEXT_V6T2 \| ARM_EXT_SEC)
	110	#define ARM_AEXT_V6ZKT2 (ARM_AEXT_V6T2 \| ARM_EXT_V6K \| ARM_EXT_SEC)
	111	#define ARM_AEXT_V7_ARM (ARM_AEXT_V6KT2 \| ARM_EXT_V7 \| ARM_EXT_BARRIER)
62b3e311 PB	112	#define ARM_AEXT_V7A (ARM_AEXT_V7_ARM \| ARM_EXT_V7A)
	113	#define ARM_AEXT_V7R (ARM_AEXT_V7_ARM \| ARM_EXT_V7R \| ARM_EXT_DIV)
	114	#define ARM_AEXT_NOTM \
9e3c6df6 PB	115	(ARM_AEXT_V4 \| ARM_EXT_V5ExP \| ARM_EXT_V5J \| ARM_EXT_V6_NOTM \
9e3c6df6 PB	116	\| ARM_EXT_V6_DSP )
7e806470 PB	117	#define ARM_AEXT_V6M \
	118	((ARM_AEXT_V6K \| ARM_EXT_BARRIER \| ARM_EXT_V6M \| ARM_EXT_THUMB_MSR) \
	119	& ~(ARM_AEXT_NOTM))
b2a5fbdc	120	#define ARM_AEXT_V6SM (ARM_AEXT_V6M \| ARM_EXT_OS)
62b3e311	121	#define ARM_AEXT_V7M \
7e806470 PB	122	((ARM_AEXT_V7_ARM \| ARM_EXT_V6M \| ARM_EXT_V7M \| ARM_EXT_DIV) \
7e806470 PB	123	& ~(ARM_AEXT_NOTM))
62b3e311	124	#define ARM_AEXT_V7 (ARM_AEXT_V7A & ARM_AEXT_V7R & ARM_AEXT_V7M)
9e3c6df6 PB	125	#define ARM_AEXT_V7EM \
9e3c6df6 PB	126	(ARM_AEXT_V7M \| ARM_EXT_V5ExP \| ARM_EXT_V6_DSP)
b781e558 RE	127
b781e558 RE	128	/* Processors with specific extensions in the co-processor space. */
e74cfd16 PB	129	#define ARM_ARCH_XSCALE ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE)
	130	#define ARM_ARCH_IWMMXT \
	131	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE \| ARM_CEXT_IWMMXT)
2d447fca JM	132	#define ARM_ARCH_IWMMXT2 \
2d447fca JM	133	ARM_FEATURE (ARM_AEXT_V5TE, ARM_CEXT_XSCALE \| ARM_CEXT_IWMMXT \| ARM_CEXT_IWMMXT2)
e74cfd16 PB	134
	135	#define FPU_VFP_V1xD (FPU_VFP_EXT_V1xD \| FPU_ENDIAN_PURE)
	136	#define FPU_VFP_V1 (FPU_VFP_V1xD \| FPU_VFP_EXT_V1)
	137	#define FPU_VFP_V2 (FPU_VFP_V1 \| FPU_VFP_EXT_V2)
62f3b8c8	138	#define FPU_VFP_V3D16 (FPU_VFP_V2 \| FPU_VFP_EXT_V3xD \| FPU_VFP_EXT_V3)
b1cc4aeb	139	#define FPU_VFP_V3 (FPU_VFP_V3D16 \| FPU_VFP_EXT_D32)
62f3b8c8 PB	140	#define FPU_VFP_V3xD (FPU_VFP_V1xD \| FPU_VFP_EXT_V2 \| FPU_VFP_EXT_V3xD)
	141	#define FPU_VFP_V4D16 (FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
	142	#define FPU_VFP_V4 (FPU_VFP_V3 \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
ada65aa3	143	#define FPU_VFP_V4_SP_D16 (FPU_VFP_V3xD \| FPU_VFP_EXT_FP16 \| FPU_VFP_EXT_FMA)
9e498214	144	#define FPU_VFP_HARD (FPU_VFP_EXT_V1xD \| FPU_VFP_EXT_V1 \| FPU_VFP_EXT_V2 \
62f3b8c8	145	\| FPU_VFP_EXT_V3xD \| FPU_VFP_EXT_FMA \| FPU_NEON_EXT_FMA \
b1cc4aeb	146	\| FPU_VFP_EXT_V3 \| FPU_NEON_EXT_V1 \| FPU_VFP_EXT_D32)
e74cfd16 PB	147	#define FPU_FPA (FPU_FPA_EXT_V1 \| FPU_FPA_EXT_V2)
	148
	149	/* Deprecated */
	150	#define FPU_ARCH_VFP ARM_FEATURE (0, FPU_ENDIAN_PURE)
b781e558	151
e74cfd16 PB	152	#define FPU_ARCH_FPE ARM_FEATURE (0, FPU_FPA_EXT_V1)
e74cfd16 PB	153	#define FPU_ARCH_FPA ARM_FEATURE (0, FPU_FPA)
b781e558	154
e74cfd16 PB	155	#define FPU_ARCH_VFP_V1xD ARM_FEATURE (0, FPU_VFP_V1xD)
	156	#define FPU_ARCH_VFP_V1 ARM_FEATURE (0, FPU_VFP_V1)
	157	#define FPU_ARCH_VFP_V2 ARM_FEATURE (0, FPU_VFP_V2)
b1cc4aeb	158	#define FPU_ARCH_VFP_V3D16 ARM_FEATURE (0, FPU_VFP_V3D16)
62f3b8c8 PB	159	#define FPU_ARCH_VFP_V3D16_FP16 \
62f3b8c8 PB	160	ARM_FEATURE (0, FPU_VFP_V3D16 \| FPU_VFP_EXT_FP16)
9e498214	161	#define FPU_ARCH_VFP_V3 ARM_FEATURE (0, FPU_VFP_V3)
62f3b8c8 PB	162	#define FPU_ARCH_VFP_V3_FP16 ARM_FEATURE (0, FPU_VFP_V3 \| FPU_VFP_EXT_FP16)
	163	#define FPU_ARCH_VFP_V3xD ARM_FEATURE (0, FPU_VFP_V3xD)
	164	#define FPU_ARCH_VFP_V3xD_FP16 ARM_FEATURE (0, FPU_VFP_V3xD \| FPU_VFP_EXT_FP16)
9e498214 JB	165	#define FPU_ARCH_NEON_V1 ARM_FEATURE (0, FPU_NEON_EXT_V1)
	166	#define FPU_ARCH_VFP_V3_PLUS_NEON_V1 \
	167	ARM_FEATURE (0, FPU_VFP_V3 \| FPU_NEON_EXT_V1)
8e79c3df	168	#define FPU_ARCH_NEON_FP16 \
62f3b8c8	169	ARM_FEATURE (0, FPU_VFP_V3 \| FPU_NEON_EXT_V1 \| FPU_VFP_EXT_FP16)
e74cfd16	170	#define FPU_ARCH_VFP_HARD ARM_FEATURE (0, FPU_VFP_HARD)
62f3b8c8 PB	171	#define FPU_ARCH_VFP_V4 ARM_FEATURE(0, FPU_VFP_V4)
62f3b8c8 PB	172	#define FPU_ARCH_VFP_V4D16 ARM_FEATURE(0, FPU_VFP_V4D16)
ada65aa3	173	#define FPU_ARCH_VFP_V4_SP_D16 ARM_FEATURE(0, FPU_VFP_V4_SP_D16)
62f3b8c8 PB	174	#define FPU_ARCH_NEON_VFP_V4 \
62f3b8c8 PB	175	ARM_FEATURE(0, FPU_VFP_V4 \| FPU_NEON_EXT_V1 \| FPU_NEON_EXT_FMA)
b781e558	176
e74cfd16	177	#define FPU_ARCH_ENDIAN_PURE ARM_FEATURE (0, FPU_ENDIAN_PURE)
b781e558	178
e74cfd16 PB	179	#define FPU_ARCH_MAVERICK ARM_FEATURE (0, FPU_MAVERICK)
	180
	181	#define ARM_ARCH_V1 ARM_FEATURE (ARM_AEXT_V1, 0)
	182	#define ARM_ARCH_V2 ARM_FEATURE (ARM_AEXT_V2, 0)
	183	#define ARM_ARCH_V2S ARM_FEATURE (ARM_AEXT_V2S, 0)
	184	#define ARM_ARCH_V3 ARM_FEATURE (ARM_AEXT_V3, 0)
	185	#define ARM_ARCH_V3M ARM_FEATURE (ARM_AEXT_V3M, 0)
	186	#define ARM_ARCH_V4xM ARM_FEATURE (ARM_AEXT_V4xM, 0)
	187	#define ARM_ARCH_V4 ARM_FEATURE (ARM_AEXT_V4, 0)
	188	#define ARM_ARCH_V4TxM ARM_FEATURE (ARM_AEXT_V4TxM, 0)
	189	#define ARM_ARCH_V4T ARM_FEATURE (ARM_AEXT_V4T, 0)
	190	#define ARM_ARCH_V5xM ARM_FEATURE (ARM_AEXT_V5xM, 0)
	191	#define ARM_ARCH_V5 ARM_FEATURE (ARM_AEXT_V5, 0)
	192	#define ARM_ARCH_V5TxM ARM_FEATURE (ARM_AEXT_V5TxM, 0)
	193	#define ARM_ARCH_V5T ARM_FEATURE (ARM_AEXT_V5T, 0)
	194	#define ARM_ARCH_V5TExP ARM_FEATURE (ARM_AEXT_V5TExP, 0)
	195	#define ARM_ARCH_V5TE ARM_FEATURE (ARM_AEXT_V5TE, 0)
	196	#define ARM_ARCH_V5TEJ ARM_FEATURE (ARM_AEXT_V5TEJ, 0)
	197	#define ARM_ARCH_V6 ARM_FEATURE (ARM_AEXT_V6, 0)
	198	#define ARM_ARCH_V6K ARM_FEATURE (ARM_AEXT_V6K, 0)
	199	#define ARM_ARCH_V6Z ARM_FEATURE (ARM_AEXT_V6Z, 0)
	200	#define ARM_ARCH_V6ZK ARM_FEATURE (ARM_AEXT_V6ZK, 0)
	201	#define ARM_ARCH_V6T2 ARM_FEATURE (ARM_AEXT_V6T2, 0)
	202	#define ARM_ARCH_V6KT2 ARM_FEATURE (ARM_AEXT_V6KT2, 0)
	203	#define ARM_ARCH_V6ZT2 ARM_FEATURE (ARM_AEXT_V6ZT2, 0)
	204	#define ARM_ARCH_V6ZKT2 ARM_FEATURE (ARM_AEXT_V6ZKT2, 0)
7e806470	205	#define ARM_ARCH_V6M ARM_FEATURE (ARM_AEXT_V6M, 0)
b2a5fbdc	206	#define ARM_ARCH_V6SM ARM_FEATURE (ARM_AEXT_V6SM, 0)
62b3e311 PB	207	#define ARM_ARCH_V7 ARM_FEATURE (ARM_AEXT_V7, 0)
	208	#define ARM_ARCH_V7A ARM_FEATURE (ARM_AEXT_V7A, 0)
	209	#define ARM_ARCH_V7R ARM_FEATURE (ARM_AEXT_V7R, 0)
	210	#define ARM_ARCH_V7M ARM_FEATURE (ARM_AEXT_V7M, 0)
9e3c6df6	211	#define ARM_ARCH_V7EM ARM_FEATURE (ARM_AEXT_V7EM, 0)
b781e558 RE	212
b781e558 RE	213	/* Some useful combinations: */
e74cfd16 PB	214	#define ARM_ARCH_NONE ARM_FEATURE (0, 0)
	215	#define FPU_NONE ARM_FEATURE (0, 0)
	216	#define ARM_ANY ARM_FEATURE (-1, 0) /* Any basic core. */
	217	#define FPU_ANY_HARD ARM_FEATURE (0, FPU_FPA \| FPU_VFP_HARD \| FPU_MAVERICK)
62b3e311	218	#define ARM_ARCH_THUMB2 ARM_FEATURE (ARM_EXT_V6T2 \| ARM_EXT_V7 \| ARM_EXT_V7A \| ARM_EXT_V7R \| ARM_EXT_V7M \| ARM_EXT_DIV, 0)
f4c65163 MGD	219	/* v7-a+sec. */
	220	#define ARM_ARCH_V7A_SEC ARM_FEATURE (ARM_AEXT_V7A \| ARM_EXT_SEC, 0)
	221	/* v7-a+mp+sec. */
	222	#define ARM_ARCH_V7A_MP_SEC \
	223	ARM_FEATURE (ARM_AEXT_V7A \| ARM_EXT_MP \| ARM_EXT_SEC, \
	224	0)
eea54501 MGD	225	/* v7-a+idiv+mp+sec. */
	226	#define ARM_ARCH_V7A_IDIV_MP_SEC \
	227	ARM_FEATURE (ARM_AEXT_V7A \| ARM_EXT_MP \| ARM_EXT_SEC \
	228	\| ARM_EXT_DIV \| ARM_EXT_ADIV, 0)
e74cfd16 PB	229
	230	/* There are too many feature bits to fit in a single word, so use a
	231	structure. For simplicity we put all core features in one word and
	232	everything else in the other. */
	233	typedef struct
	234	{
	235	unsigned long core;
	236	unsigned long coproc;
	237	} arm_feature_set;
	238
	239	#define ARM_CPU_HAS_FEATURE(CPU,FEAT) \
	240	(((CPU).core & (FEAT).core) != 0 \|\| ((CPU).coproc & (FEAT).coproc) != 0)
	241
	242	#define ARM_MERGE_FEATURE_SETS(TARG,F1,F2) \
	243	do { \
	244	(TARG).core = (F1).core \| (F2).core; \
	245	(TARG).coproc = (F1).coproc \| (F2).coproc; \
	246	} while (0)
	247
	248	#define ARM_CLEAR_FEATURE(TARG,F1,F2) \
	249	do { \
	250	(TARG).core = (F1).core &~ (F2).core; \
	251	(TARG).coproc = (F1).coproc &~ (F2).coproc; \
	252	} while (0)
	253
	254	#define ARM_FEATURE(core, coproc) {(core), (coproc)}