[thirdparty/binutils-gdb.git] / include / opcode / riscv.h

/* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   Copyright (C) 2011-2021 Free Software Foundation, Inc.
   Contributed by Andrew Waterman

   This file is part of GDB, GAS, and the GNU binutils.

   GDB, GAS, and the GNU binutils are free software; you can redistribute
   them and/or modify them under the terms of the GNU General Public
   License as published by the Free Software Foundation; either version
   3, or (at your option) any later version.

   GDB, GAS, and the GNU binutils are distributed in the hope that they
   will be useful, but WITHOUT ANY WARRANTY; without even the implied
   warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
   the GNU General Public License for more details.

   You should have received a copy of the GNU General Public License
   along with this program; see the file COPYING3. If not,
   see <http://www.gnu.org/licenses/>.  */

#ifndef _RISCV_H_
#define _RISCV_H_

#include "riscv-opc.h"
#include <stdlib.h>
#include <stdint.h>

typedef uint64_t insn_t;

static inline unsigned int riscv_insn_length (insn_t insn)
{
  if ((insn & 0x3) != 0x3) /* RVC instructions.  */
    return 2;
  if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
    return 4;
  if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
    return 6;
  if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
    return 8;
  /* Longer instructions not supported at the moment.  */
  return 2;
}

static const char * const riscv_rm[8] =
{
  "rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
};

static const char * const riscv_pred_succ[16] =
{
  0,   "w",  "r",  "rw",  "o",  "ow",  "or",  "orw",
  "i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
};

#define RVC_JUMP_BITS 11
#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)

#define RVC_BRANCH_BITS 8
#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)

#define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))

#define EXTRACT_ITYPE_IMM(x) \
  (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
#define EXTRACT_STYPE_IMM(x) \
  (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
#define EXTRACT_BTYPE_IMM(x) \
  ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
#define EXTRACT_UTYPE_IMM(x) \
  ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
#define EXTRACT_JTYPE_IMM(x) \
  ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
#define EXTRACT_CITYPE_IMM(x) \
  (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
#define EXTRACT_CITYPE_LUI_IMM(x) \
  (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
  ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
#define EXTRACT_CITYPE_LWSP_IMM(x) \
  ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
#define EXTRACT_CITYPE_LDSP_IMM(x) \
  ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
#define EXTRACT_CSSTYPE_IMM(x) \
  (RV_X(x, 7, 6) << 0)
#define EXTRACT_CSSTYPE_SWSP_IMM(x) \
  ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
#define EXTRACT_CSSTYPE_SDSP_IMM(x) \
  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
#define EXTRACT_CIWTYPE_IMM(x) \
  (RV_X(x, 5, 8))
#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
#define EXTRACT_CLTYPE_IMM(x) \
  ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
#define EXTRACT_CLTYPE_LW_IMM(x) \
  ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
#define EXTRACT_CLTYPE_LD_IMM(x) \
  ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
#define EXTRACT_CBTYPE_IMM(x) \
  ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
#define EXTRACT_CJTYPE_IMM(x) \
  ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))

#define ENCODE_ITYPE_IMM(x) \
  (RV_X(x, 0, 12) << 20)
#define ENCODE_STYPE_IMM(x) \
  ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
#define ENCODE_BTYPE_IMM(x) \
  ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
#define ENCODE_UTYPE_IMM(x) \
  (RV_X(x, 12, 20) << 12)
#define ENCODE_JTYPE_IMM(x) \
  ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
#define ENCODE_CITYPE_IMM(x) \
  ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
#define ENCODE_CITYPE_LUI_IMM(x) \
  ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
#define ENCODE_CITYPE_ADDI16SP_IMM(x) \
  ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
#define ENCODE_CITYPE_LWSP_IMM(x) \
  ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
#define ENCODE_CITYPE_LDSP_IMM(x) \
  ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
#define ENCODE_CSSTYPE_IMM(x) \
  (RV_X(x, 0, 6) << 7)
#define ENCODE_CSSTYPE_SWSP_IMM(x) \
  ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
#define ENCODE_CSSTYPE_SDSP_IMM(x) \
  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
#define ENCODE_CIWTYPE_IMM(x) \
  (RV_X(x, 0, 8) << 5)
#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
#define ENCODE_CLTYPE_IMM(x) \
  ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
#define ENCODE_CLTYPE_LW_IMM(x) \
  ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
#define ENCODE_CLTYPE_LD_IMM(x) \
  ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
#define ENCODE_CBTYPE_IMM(x) \
  ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
#define ENCODE_CJTYPE_IMM(x) \
  ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))

#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
				 && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
				      && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))

#define RISCV_RTYPE(insn, rd, rs1, rs2) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
#define RISCV_ITYPE(insn, rd, rs1, imm) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
#define RISCV_STYPE(insn, rs1, rs2, imm) \
  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
#define RISCV_BTYPE(insn, rs1, rs2, target) \
  ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
#define RISCV_UTYPE(insn, rd, bigimm) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
#define RISCV_JTYPE(insn, rd, target) \
  ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))

#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
#define RVC_NOP MATCH_C_ADDI

#define RISCV_CONST_HIGH_PART(VALUE) \
  (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))

#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
#define RISCV_JUMP_ALIGN_BITS 1
#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)

#define RISCV_IMM_BITS 12
#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
#define RISCV_RVC_IMM_REACH (1LL << 6)
#define RISCV_BRANCH_BITS RISCV_IMM_BITS
#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)

/* RV fields.  */

#define OP_MASK_OP		0x7f
#define OP_SH_OP		0
#define OP_MASK_RS2		0x1f
#define OP_SH_RS2		20
#define OP_MASK_RS1		0x1f
#define OP_SH_RS1		15
#define OP_MASK_RS3		0x1fU
#define OP_SH_RS3		27
#define OP_MASK_RD		0x1f
#define OP_SH_RD		7
#define OP_MASK_SHAMT		0x3f
#define OP_SH_SHAMT		20
#define OP_MASK_SHAMTW		0x1f
#define OP_SH_SHAMTW		20
#define OP_MASK_RM		0x7
#define OP_SH_RM		12
#define OP_MASK_PRED		0xf
#define OP_SH_PRED		24
#define OP_MASK_SUCC		0xf
#define OP_SH_SUCC		20
#define OP_MASK_AQ		0x1
#define OP_SH_AQ		26
#define OP_MASK_RL		0x1
#define OP_SH_RL		25

#define OP_MASK_CSR		0xfffU
#define OP_SH_CSR		20

#define OP_MASK_FUNCT3		0x7
#define OP_SH_FUNCT3		12
#define OP_MASK_FUNCT7		0x7fU
#define OP_SH_FUNCT7		25
#define OP_MASK_FUNCT2		0x3
#define OP_SH_FUNCT2		25

/* RVC fields.  */

#define OP_MASK_OP2		0x3
#define OP_SH_OP2		0

#define OP_MASK_CRS2		0x1f
#define OP_SH_CRS2		2
#define OP_MASK_CRS1S		0x7
#define OP_SH_CRS1S		7
#define OP_MASK_CRS2S		0x7
#define OP_SH_CRS2S		2

#define OP_MASK_CFUNCT6		0x3f
#define OP_SH_CFUNCT6		10
#define OP_MASK_CFUNCT4		0xf
#define OP_SH_CFUNCT4		12
#define OP_MASK_CFUNCT3		0x7
#define OP_SH_CFUNCT3		13
#define OP_MASK_CFUNCT2		0x3
#define OP_SH_CFUNCT2		5

/* ABI names for selected x-registers.  */

#define X_RA 1
#define X_SP 2
#define X_GP 3
#define X_TP 4
#define X_T0 5
#define X_T1 6
#define X_T2 7
#define X_T3 28

#define NGPR 32
#define NFPR 32

/* These fake label defines are use by both the assembler, and
   libopcodes.  The assembler uses this when it needs to generate a fake
   label, and libopcodes uses it to hide the fake labels in its output.  */
#define RISCV_FAKE_LABEL_NAME ".L0 "
#define RISCV_FAKE_LABEL_CHAR ' '

/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
   VALUE << SHIFT.  VALUE is evaluated exactly once.  */
#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
  (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
	      | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))

/* Extract bits MASK << SHIFT from STRUCT and shift them right
   SHIFT places.  */
#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
  (((STRUCT) >> (SHIFT)) & (MASK))

/* Extract the operand given by FIELD from integer INSN.  */
#define EXTRACT_OPERAND(FIELD, INSN) \
  EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)

/* The maximal number of subset can be required.  */
#define MAX_SUBSET_NUM 4

/* All RISC-V instructions belong to at least one of these classes.  */
enum riscv_insn_class
{
  INSN_CLASS_NONE,

  INSN_CLASS_I,
  INSN_CLASS_C,
  INSN_CLASS_A,
  INSN_CLASS_M,
  INSN_CLASS_F,
  INSN_CLASS_D,
  INSN_CLASS_Q,
  INSN_CLASS_F_AND_C,
  INSN_CLASS_D_AND_C,
  INSN_CLASS_ZICSR,
  INSN_CLASS_ZIFENCEI,
  INSN_CLASS_ZIHINTPAUSE,
  INSN_CLASS_ZBA,
  INSN_CLASS_ZBB,
  INSN_CLASS_ZBC,
};

/* This structure holds information for a particular instruction.  */
struct riscv_opcode
{
  /* The name of the instruction.  */
  const char *name;

  /* The requirement of xlen for the instruction, 0 if no requirement.  */
  unsigned xlen_requirement;

  /* Class to which this instruction belongs.  Used to decide whether or
     not this instruction is legal in the current -march context.  */
  enum riscv_insn_class insn_class;

  /* A string describing the arguments for this instruction.  */
  const char *args;

  /* The basic opcode for the instruction.  When assembling, this
     opcode is modified by the arguments to produce the actual opcode
     that is used.  If pinfo is INSN_MACRO, then this is 0.  */
  insn_t match;

  /* If pinfo is not INSN_MACRO, then this is a bit mask for the
     relevant portions of the opcode when disassembling.  If the
     actual opcode anded with the match field equals the opcode field,
     then we have found the correct instruction.  If pinfo is
     INSN_MACRO, then this field is the macro identifier.  */
  insn_t mask;

  /* A function to determine if a word corresponds to this instruction.
     Usually, this computes ((word & mask) == match).  */
  int (*match_func) (const struct riscv_opcode *op, insn_t word);

  /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
     of bits describing the instruction, notably any relevant hazard
     information.  */
  unsigned long pinfo;
};

/* Instruction is a simple alias (e.g. "mv" for "addi").  */
#define	INSN_ALIAS		0x00000001

/* These are for setting insn_info fields.

   Nonbranch is the default.  Noninsn is used only if there is no match.
   There are no condjsr or dref2 instructions.  So that leaves condbranch,
   branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
#define INSN_TYPE		0x0000000e

/* Instruction is an unconditional branch.  */
#define INSN_BRANCH		0x00000002
/* Instruction is a conditional branch.  */
#define INSN_CONDBRANCH		0x00000004
/* Instruction is a jump to subroutine.  */
#define INSN_JSR		0x00000006
/* Instruction is a data reference.  */
#define INSN_DREF		0x00000008

/* We have 5 data reference sizes, which we can encode in 3 bits.  */
#define INSN_DATA_SIZE		0x00000070
#define INSN_DATA_SIZE_SHIFT	4
#define INSN_1_BYTE		0x00000010
#define INSN_2_BYTE		0x00000020
#define INSN_4_BYTE		0x00000030
#define INSN_8_BYTE		0x00000040
#define INSN_16_BYTE		0x00000050

/* Instruction is actually a macro.  It should be ignored by the
   disassembler, and requires special treatment by the assembler.  */
#define INSN_MACRO		0xffffffff

/* This is a list of macro expanded instructions.  */
enum
{
  M_LA,
  M_LLA,
  M_LA_TLS_GD,
  M_LA_TLS_IE,
  M_LB,
  M_LBU,
  M_LH,
  M_LHU,
  M_LW,
  M_LWU,
  M_LD,
  M_SB,
  M_SH,
  M_SW,
  M_SD,
  M_FLW,
  M_FLD,
  M_FLQ,
  M_FSW,
  M_FSD,
  M_FSQ,
  M_CALL,
  M_J,
  M_LI,
  M_ZEXTH,
  M_ZEXTW,
  M_SEXTB,
  M_SEXTH,
  M_NUM_MACROS
};


extern const char * const riscv_gpr_names_numeric[NGPR];
extern const char * const riscv_gpr_names_abi[NGPR];
extern const char * const riscv_fpr_names_numeric[NFPR];
extern const char * const riscv_fpr_names_abi[NFPR];

extern const struct riscv_opcode riscv_opcodes[];
extern const struct riscv_opcode riscv_insn_types[];

#endif /* _RISCV_H_ */
Commit	Line	Data
e23eba97	1	/* riscv.h. RISC-V opcode list for GDB, the GNU debugger.
250d07de	2	Copyright (C) 2011-2021 Free Software Foundation, Inc.
e23eba97 NC	3	Contributed by Andrew Waterman
	4
	5	This file is part of GDB, GAS, and the GNU binutils.
	6
	7	GDB, GAS, and the GNU binutils are free software; you can redistribute
	8	them and/or modify them under the terms of the GNU General Public
	9	License as published by the Free Software Foundation; either version
	10	3, or (at your option) any later version.
	11
	12	GDB, GAS, and the GNU binutils are distributed in the hope that they
	13	will be useful, but WITHOUT ANY WARRANTY; without even the implied
	14	warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
	15	the GNU General Public License for more details.
	16
	17	You should have received a copy of the GNU General Public License
	18	along with this program; see the file COPYING3. If not,
	19	see <http://www.gnu.org/licenses/>. */
	20
	21	#ifndef _RISCV_H_
	22	#define _RISCV_H_
	23
	24	#include "riscv-opc.h"
	25	#include <stdlib.h>
	26	#include <stdint.h>
	27
	28	typedef uint64_t insn_t;
	29
	30	static inline unsigned int riscv_insn_length (insn_t insn)
	31	{
dcd709e0	32	if ((insn & 0x3) != 0x3) /* RVC instructions. */
e23eba97	33	return 2;
dcd709e0	34	if ((insn & 0x1f) != 0x1f) /* 32-bit instructions. */
e23eba97	35	return 4;
dcd709e0	36	if ((insn & 0x3f) == 0x1f) /* 48-bit instructions. */
e23eba97	37	return 6;
dcd709e0	38	if ((insn & 0x7f) == 0x3f) /* 64-bit instructions. */
e23eba97 NC	39	return 8;
	40	/* Longer instructions not supported at the moment. */
	41	return 2;
	42	}
	43
	44	static const char * const riscv_rm[8] =
	45	{
	46	"rne", "rtz", "rdn", "rup", "rmm", 0, 0, "dyn"
	47	};
	48
	49	static const char * const riscv_pred_succ[16] =
	50	{
	51	0, "w", "r", "rw", "o", "ow", "or", "orw",
	52	"i", "iw", "ir", "irw", "io", "iow", "ior", "iorw"
	53	};
	54
	55	#define RVC_JUMP_BITS 11
	56	#define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
	57
	58	#define RVC_BRANCH_BITS 8
	59	#define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
	60
	61	#define RV_X(x, s, n) (((x) >> (s)) & ((1 << (n)) - 1))
	62	#define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
	63
	64	#define EXTRACT_ITYPE_IMM(x) \
	65	(RV_X(x, 20, 12) \| (RV_IMM_SIGN(x) << 12))
	66	#define EXTRACT_STYPE_IMM(x) \
	67	(RV_X(x, 7, 5) \| (RV_X(x, 25, 7) << 5) \| (RV_IMM_SIGN(x) << 12))
5a9f5403	68	#define EXTRACT_BTYPE_IMM(x) \
e23eba97 NC	69	((RV_X(x, 8, 4) << 1) \| (RV_X(x, 25, 6) << 5) \| (RV_X(x, 7, 1) << 11) \| (RV_IMM_SIGN(x) << 12))
	70	#define EXTRACT_UTYPE_IMM(x) \
	71	((RV_X(x, 12, 20) << 12) \| (RV_IMM_SIGN(x) << 32))
5a9f5403	72	#define EXTRACT_JTYPE_IMM(x) \
e23eba97	73	((RV_X(x, 21, 10) << 1) \| (RV_X(x, 20, 1) << 11) \| (RV_X(x, 12, 8) << 12) \| (RV_IMM_SIGN(x) << 20))
5a9f5403	74	#define EXTRACT_CITYPE_IMM(x) \
e23eba97	75	(RV_X(x, 2, 5) \| (-RV_X(x, 12, 1) << 5))
5a9f5403 NC	76	#define EXTRACT_CITYPE_LUI_IMM(x) \
	77	(EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
	78	#define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
e23eba97	79	((RV_X(x, 6, 1) << 4) \| (RV_X(x, 2, 1) << 5) \| (RV_X(x, 5, 1) << 6) \| (RV_X(x, 3, 2) << 7) \| (-RV_X(x, 12, 1) << 9))
5a9f5403	80	#define EXTRACT_CITYPE_LWSP_IMM(x) \
e23eba97	81	((RV_X(x, 4, 3) << 2) \| (RV_X(x, 12, 1) << 5) \| (RV_X(x, 2, 2) << 6))
5a9f5403	82	#define EXTRACT_CITYPE_LDSP_IMM(x) \
e23eba97	83	((RV_X(x, 5, 2) << 3) \| (RV_X(x, 12, 1) << 5) \| (RV_X(x, 2, 3) << 6))
5a9f5403 NC	84	#define EXTRACT_CSSTYPE_IMM(x) \
	85	(RV_X(x, 7, 6) << 0)
	86	#define EXTRACT_CSSTYPE_SWSP_IMM(x) \
e23eba97	87	((RV_X(x, 9, 4) << 2) \| (RV_X(x, 7, 2) << 6))
5a9f5403	88	#define EXTRACT_CSSTYPE_SDSP_IMM(x) \
e23eba97	89	((RV_X(x, 10, 3) << 3) \| (RV_X(x, 7, 3) << 6))
5a9f5403 NC	90	#define EXTRACT_CIWTYPE_IMM(x) \
	91	(RV_X(x, 5, 8))
	92	#define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
	93	((RV_X(x, 6, 1) << 2) \| (RV_X(x, 5, 1) << 3) \| (RV_X(x, 11, 2) << 4) \| (RV_X(x, 7, 4) << 6))
	94	#define EXTRACT_CLTYPE_IMM(x) \
	95	((RV_X(x, 5, 2) << 0) \| (RV_X(x, 10, 3) << 2))
	96	#define EXTRACT_CLTYPE_LW_IMM(x) \
	97	((RV_X(x, 6, 1) << 2) \| (RV_X(x, 10, 3) << 3) \| (RV_X(x, 5, 1) << 6))
	98	#define EXTRACT_CLTYPE_LD_IMM(x) \
	99	((RV_X(x, 10, 3) << 3) \| (RV_X(x, 5, 2) << 6))
	100	#define EXTRACT_CBTYPE_IMM(x) \
e23eba97	101	((RV_X(x, 3, 2) << 1) \| (RV_X(x, 10, 2) << 3) \| (RV_X(x, 2, 1) << 5) \| (RV_X(x, 5, 2) << 6) \| (-RV_X(x, 12, 1) << 8))
5a9f5403	102	#define EXTRACT_CJTYPE_IMM(x) \
e23eba97 NC	103	((RV_X(x, 3, 3) << 1) \| (RV_X(x, 11, 1) << 4) \| (RV_X(x, 2, 1) << 5) \| (RV_X(x, 7, 1) << 6) \| (RV_X(x, 6, 1) << 7) \| (RV_X(x, 9, 2) << 8) \| (RV_X(x, 8, 1) << 10) \| (-RV_X(x, 12, 1) << 11))
	104
	105	#define ENCODE_ITYPE_IMM(x) \
	106	(RV_X(x, 0, 12) << 20)
	107	#define ENCODE_STYPE_IMM(x) \
	108	((RV_X(x, 0, 5) << 7) \| (RV_X(x, 5, 7) << 25))
5a9f5403	109	#define ENCODE_BTYPE_IMM(x) \
e23eba97 NC	110	((RV_X(x, 1, 4) << 8) \| (RV_X(x, 5, 6) << 25) \| (RV_X(x, 11, 1) << 7) \| (RV_X(x, 12, 1) << 31))
	111	#define ENCODE_UTYPE_IMM(x) \
	112	(RV_X(x, 12, 20) << 12)
5a9f5403	113	#define ENCODE_JTYPE_IMM(x) \
e23eba97	114	((RV_X(x, 1, 10) << 21) \| (RV_X(x, 11, 1) << 20) \| (RV_X(x, 12, 8) << 12) \| (RV_X(x, 20, 1) << 31))
5a9f5403	115	#define ENCODE_CITYPE_IMM(x) \
e23eba97	116	((RV_X(x, 0, 5) << 2) \| (RV_X(x, 5, 1) << 12))
5a9f5403 NC	117	#define ENCODE_CITYPE_LUI_IMM(x) \
	118	ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
	119	#define ENCODE_CITYPE_ADDI16SP_IMM(x) \
e23eba97	120	((RV_X(x, 4, 1) << 6) \| (RV_X(x, 5, 1) << 2) \| (RV_X(x, 6, 1) << 5) \| (RV_X(x, 7, 2) << 3) \| (RV_X(x, 9, 1) << 12))
5a9f5403	121	#define ENCODE_CITYPE_LWSP_IMM(x) \
e23eba97	122	((RV_X(x, 2, 3) << 4) \| (RV_X(x, 5, 1) << 12) \| (RV_X(x, 6, 2) << 2))
5a9f5403	123	#define ENCODE_CITYPE_LDSP_IMM(x) \
e23eba97	124	((RV_X(x, 3, 2) << 5) \| (RV_X(x, 5, 1) << 12) \| (RV_X(x, 6, 3) << 2))
5a9f5403 NC	125	#define ENCODE_CSSTYPE_IMM(x) \
	126	(RV_X(x, 0, 6) << 7)
	127	#define ENCODE_CSSTYPE_SWSP_IMM(x) \
e23eba97	128	((RV_X(x, 2, 4) << 9) \| (RV_X(x, 6, 2) << 7))
5a9f5403	129	#define ENCODE_CSSTYPE_SDSP_IMM(x) \
e23eba97	130	((RV_X(x, 3, 3) << 10) \| (RV_X(x, 6, 3) << 7))
5a9f5403 NC	131	#define ENCODE_CIWTYPE_IMM(x) \
	132	(RV_X(x, 0, 8) << 5)
	133	#define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
	134	((RV_X(x, 2, 1) << 6) \| (RV_X(x, 3, 1) << 5) \| (RV_X(x, 4, 2) << 11) \| (RV_X(x, 6, 4) << 7))
	135	#define ENCODE_CLTYPE_IMM(x) \
	136	((RV_X(x, 0, 2) << 5) \| (RV_X(x, 2, 3) << 10))
	137	#define ENCODE_CLTYPE_LW_IMM(x) \
	138	((RV_X(x, 2, 1) << 6) \| (RV_X(x, 3, 3) << 10) \| (RV_X(x, 6, 1) << 5))
	139	#define ENCODE_CLTYPE_LD_IMM(x) \
	140	((RV_X(x, 3, 3) << 10) \| (RV_X(x, 6, 2) << 5))
	141	#define ENCODE_CBTYPE_IMM(x) \
e23eba97	142	((RV_X(x, 1, 2) << 3) \| (RV_X(x, 3, 2) << 10) \| (RV_X(x, 5, 1) << 2) \| (RV_X(x, 6, 2) << 5) \| (RV_X(x, 8, 1) << 12))
5a9f5403	143	#define ENCODE_CJTYPE_IMM(x) \
e23eba97 NC	144	((RV_X(x, 1, 3) << 3) \| (RV_X(x, 4, 1) << 11) \| (RV_X(x, 5, 1) << 2) \| (RV_X(x, 6, 1) << 7) \| (RV_X(x, 7, 1) << 6) \| (RV_X(x, 8, 2) << 9) \| (RV_X(x, 10, 1) << 8) \| (RV_X(x, 11, 1) << 12))
	145
	146	#define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
	147	#define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
5a9f5403	148	#define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
e23eba97	149	#define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
5a9f5403 NC	150	#define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
	151	#define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
	152	#define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
	153	&& EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
	154	#define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
	155	&& EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
	156	#define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
	157	#define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
	158	#define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
	159	#define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
	160	#define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
	161	#define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
	162	#define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
	163	#define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
	164	#define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
	165	#define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
	166	#define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
	167	#define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
e23eba97 NC	168
	169	#define RISCV_RTYPE(insn, rd, rs1, rs2) \
	170	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ((rs1) << OP_SH_RS1) \| ((rs2) << OP_SH_RS2))
	171	#define RISCV_ITYPE(insn, rd, rs1, imm) \
	172	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ((rs1) << OP_SH_RS1) \| ENCODE_ITYPE_IMM(imm))
	173	#define RISCV_STYPE(insn, rs1, rs2, imm) \
	174	((MATCH_ ## insn) \| ((rs1) << OP_SH_RS1) \| ((rs2) << OP_SH_RS2) \| ENCODE_STYPE_IMM(imm))
5a9f5403 NC	175	#define RISCV_BTYPE(insn, rs1, rs2, target) \
5a9f5403 NC	176	((MATCH_ ## insn) \| ((rs1) << OP_SH_RS1) \| ((rs2) << OP_SH_RS2) \| ENCODE_BTYPE_IMM(target))
e23eba97 NC	177	#define RISCV_UTYPE(insn, rd, bigimm) \
e23eba97 NC	178	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ENCODE_UTYPE_IMM(bigimm))
5a9f5403 NC	179	#define RISCV_JTYPE(insn, rd, target) \
5a9f5403 NC	180	((MATCH_ ## insn) \| ((rd) << OP_SH_RD) \| ENCODE_JTYPE_IMM(target))
e23eba97 NC	181
	182	#define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
	183	#define RVC_NOP MATCH_C_ADDI
	184
	185	#define RISCV_CONST_HIGH_PART(VALUE) \
	186	(((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
	187	#define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
	188	#define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
	189	#define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
	190
	191	#define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
	192	#define RISCV_JUMP_ALIGN_BITS 1
	193	#define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
	194	#define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
	195
	196	#define RISCV_IMM_BITS 12
	197	#define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
	198	#define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
	199	#define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
	200	#define RISCV_RVC_IMM_REACH (1LL << 6)
	201	#define RISCV_BRANCH_BITS RISCV_IMM_BITS
	202	#define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
	203	#define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
	204	#define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
	205
	206	/* RV fields. */
	207
	208	#define OP_MASK_OP 0x7f
	209	#define OP_SH_OP 0
	210	#define OP_MASK_RS2 0x1f
	211	#define OP_SH_RS2 20
	212	#define OP_MASK_RS1 0x1f
	213	#define OP_SH_RS1 15
1174d920	214	#define OP_MASK_RS3 0x1fU
e23eba97 NC	215	#define OP_SH_RS3 27
	216	#define OP_MASK_RD 0x1f
	217	#define OP_SH_RD 7
	218	#define OP_MASK_SHAMT 0x3f
	219	#define OP_SH_SHAMT 20
	220	#define OP_MASK_SHAMTW 0x1f
	221	#define OP_SH_SHAMTW 20
	222	#define OP_MASK_RM 0x7
	223	#define OP_SH_RM 12
	224	#define OP_MASK_PRED 0xf
	225	#define OP_SH_PRED 24
	226	#define OP_MASK_SUCC 0xf
	227	#define OP_SH_SUCC 20
	228	#define OP_MASK_AQ 0x1
	229	#define OP_SH_AQ 26
	230	#define OP_MASK_RL 0x1
	231	#define OP_SH_RL 25
	232
1174d920	233	#define OP_MASK_CSR 0xfffU
e23eba97 NC	234	#define OP_SH_CSR 20
e23eba97 NC	235
1942a048 NC	236	#define OP_MASK_FUNCT3 0x7
	237	#define OP_SH_FUNCT3 12
	238	#define OP_MASK_FUNCT7 0x7fU
	239	#define OP_SH_FUNCT7 25
	240	#define OP_MASK_FUNCT2 0x3
	241	#define OP_SH_FUNCT2 25
0e35537d	242
e23eba97 NC	243	/* RVC fields. */
e23eba97 NC	244
1942a048 NC	245	#define OP_MASK_OP2 0x3
	246	#define OP_SH_OP2 0
	247
	248	#define OP_MASK_CRS2 0x1f
	249	#define OP_SH_CRS2 2
	250	#define OP_MASK_CRS1S 0x7
	251	#define OP_SH_CRS1S 7
	252	#define OP_MASK_CRS2S 0x7
	253	#define OP_SH_CRS2S 2
	254
	255	#define OP_MASK_CFUNCT6 0x3f
	256	#define OP_SH_CFUNCT6 10
	257	#define OP_MASK_CFUNCT4 0xf
	258	#define OP_SH_CFUNCT4 12
	259	#define OP_MASK_CFUNCT3 0x7
	260	#define OP_SH_CFUNCT3 13
	261	#define OP_MASK_CFUNCT2 0x3
	262	#define OP_SH_CFUNCT2 5
0e35537d	263
e23eba97 NC	264	/* ABI names for selected x-registers. */
	265
	266	#define X_RA 1
	267	#define X_SP 2
	268	#define X_GP 3
	269	#define X_TP 4
	270	#define X_T0 5
	271	#define X_T1 6
	272	#define X_T2 7
	273	#define X_T3 28
	274
	275	#define NGPR 32
	276	#define NFPR 32
	277
884b49e3 AB	278	/* These fake label defines are use by both the assembler, and
	279	libopcodes. The assembler uses this when it needs to generate a fake
	280	label, and libopcodes uses it to hide the fake labels in its output. */
	281	#define RISCV_FAKE_LABEL_NAME ".L0 "
	282	#define RISCV_FAKE_LABEL_CHAR ' '
	283
e23eba97 NC	284	/* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
	285	VALUE << SHIFT. VALUE is evaluated exactly once. */
	286	#define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
	287	(STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
	288	\| ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
	289
	290	/* Extract bits MASK << SHIFT from STRUCT and shift them right
	291	SHIFT places. */
	292	#define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
	293	(((STRUCT) >> (SHIFT)) & (MASK))
	294
	295	/* Extract the operand given by FIELD from integer INSN. */
	296	#define EXTRACT_OPERAND(FIELD, INSN) \
	297	EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD)
	298
dcd709e0	299	/* The maximal number of subset can be required. */
43135d3b JW	300	#define MAX_SUBSET_NUM 4
43135d3b JW	301
7e9ad3a3	302	/* All RISC-V instructions belong to at least one of these classes. */
7e9ad3a3	303	enum riscv_insn_class
1942a048 NC	304	{
	305	INSN_CLASS_NONE,
	306
	307	INSN_CLASS_I,
	308	INSN_CLASS_C,
	309	INSN_CLASS_A,
	310	INSN_CLASS_M,
	311	INSN_CLASS_F,
	312	INSN_CLASS_D,
	313	INSN_CLASS_Q,
	314	INSN_CLASS_F_AND_C,
	315	INSN_CLASS_D_AND_C,
	316	INSN_CLASS_ZICSR,
	317	INSN_CLASS_ZIFENCEI,
	318	INSN_CLASS_ZIHINTPAUSE,
80d49d6a KLC	319	INSN_CLASS_ZBA,
	320	INSN_CLASS_ZBB,
	321	INSN_CLASS_ZBC,
1942a048	322	};
7e9ad3a3	323
e23eba97	324	/* This structure holds information for a particular instruction. */
e23eba97 NC	325	struct riscv_opcode
	326	{
	327	/* The name of the instruction. */
	328	const char *name;
1942a048	329
43135d3b	330	/* The requirement of xlen for the instruction, 0 if no requirement. */
1080bf78	331	unsigned xlen_requirement;
1942a048	332
7e9ad3a3 JW	333	/* Class to which this instruction belongs. Used to decide whether or
	334	not this instruction is legal in the current -march context. */
	335	enum riscv_insn_class insn_class;
1942a048	336
e23eba97 NC	337	/* A string describing the arguments for this instruction. */
e23eba97 NC	338	const char *args;
1942a048	339
e23eba97 NC	340	/* The basic opcode for the instruction. When assembling, this
	341	opcode is modified by the arguments to produce the actual opcode
	342	that is used. If pinfo is INSN_MACRO, then this is 0. */
	343	insn_t match;
1942a048	344
e23eba97 NC	345	/* If pinfo is not INSN_MACRO, then this is a bit mask for the
	346	relevant portions of the opcode when disassembling. If the
	347	actual opcode anded with the match field equals the opcode field,
	348	then we have found the correct instruction. If pinfo is
	349	INSN_MACRO, then this field is the macro identifier. */
	350	insn_t mask;
1942a048	351
e23eba97 NC	352	/* A function to determine if a word corresponds to this instruction.
	353	Usually, this computes ((word & mask) == match). */
	354	int (match_func) (const struct riscv_opcode op, insn_t word);
1942a048	355
e23eba97 NC	356	/* For a macro, this is INSN_MACRO. Otherwise, it is a collection
	357	of bits describing the instruction, notably any relevant hazard
	358	information. */
	359	unsigned long pinfo;
	360	};
	361
	362	/* Instruction is a simple alias (e.g. "mv" for "addi"). */
	363	#define INSN_ALIAS 0x00000001
eb41b248 JW	364
	365	/* These are for setting insn_info fields.
	366
	367	Nonbranch is the default. Noninsn is used only if there is no match.
	368	There are no condjsr or dref2 instructions. So that leaves condbranch,
	369	branch, jsr, and dref that we need to handle here, encoded in 3 bits. */
	370	#define INSN_TYPE 0x0000000e
	371
	372	/* Instruction is an unconditional branch. */
	373	#define INSN_BRANCH 0x00000002
	374	/* Instruction is a conditional branch. */
	375	#define INSN_CONDBRANCH 0x00000004
	376	/* Instruction is a jump to subroutine. */
	377	#define INSN_JSR 0x00000006
	378	/* Instruction is a data reference. */
	379	#define INSN_DREF 0x00000008
	380
	381	/* We have 5 data reference sizes, which we can encode in 3 bits. */
	382	#define INSN_DATA_SIZE 0x00000070
	383	#define INSN_DATA_SIZE_SHIFT 4
	384	#define INSN_1_BYTE 0x00000010
	385	#define INSN_2_BYTE 0x00000020
	386	#define INSN_4_BYTE 0x00000030
	387	#define INSN_8_BYTE 0x00000040
	388	#define INSN_16_BYTE 0x00000050
	389
e23eba97 NC	390	/* Instruction is actually a macro. It should be ignored by the
	391	disassembler, and requires special treatment by the assembler. */
	392	#define INSN_MACRO 0xffffffff
	393
dcd709e0	394	/* This is a list of macro expanded instructions. */
e23eba97 NC	395	enum
	396	{
	397	M_LA,
	398	M_LLA,
	399	M_LA_TLS_GD,
	400	M_LA_TLS_IE,
	401	M_LB,
	402	M_LBU,
	403	M_LH,
	404	M_LHU,
	405	M_LW,
	406	M_LWU,
	407	M_LD,
	408	M_SB,
	409	M_SH,
	410	M_SW,
	411	M_SD,
	412	M_FLW,
	413	M_FLD,
cc917fd9	414	M_FLQ,
e23eba97 NC	415	M_FSW,
e23eba97 NC	416	M_FSD,
cc917fd9	417	M_FSQ,
e23eba97 NC	418	M_CALL,
	419	M_J,
	420	M_LI,
c2137f55 NC	421	M_ZEXTH,
	422	M_ZEXTW,
	423	M_SEXTB,
	424	M_SEXTH,
e23eba97 NC	425	M_NUM_MACROS
	426	};
	427
	428
	429	extern const char * const riscv_gpr_names_numeric[NGPR];
	430	extern const char * const riscv_gpr_names_abi[NGPR];
	431	extern const char * const riscv_fpr_names_numeric[NFPR];
	432	extern const char * const riscv_fpr_names_abi[NFPR];
	433
	434	extern const struct riscv_opcode riscv_opcodes[];
0e35537d	435	extern const struct riscv_opcode riscv_insn_types[];
e23eba97 NC	436
e23eba97 NC	437	#endif /* _RISCV_H_ */