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[thirdparty/pciutils.git] / ls-ecaps.c
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c7a34993
MM		 1/*
2 * The PCI Utilities -- Show Extended Capabilities
3 *
2849db67 4 * Copyright (c) 1997--2022 Martin Mares <mj@ucw.cz>
c7a34993 5 *
61829219
MM		 6 * Can be freely distributed and used under the terms of the GNU GPL v2+.
7 *
8 * SPDX-License-Identifier: GPL-2.0-or-later
c7a34993
MM		 9 */
10
11#include <stdio.h>
12#include <string.h>
13
14#include "lspci.h"
15
67da1792
MM		 16static void
17cap_tph(struct device *d, int where)
18{
19 u32 tph_cap;
20 printf("Transaction Processing Hints\n");
21 if (verbose < 2)
22 return;
23
24 if (!config_fetch(d, where + PCI_TPH_CAPABILITIES, 4))
25 return;
26
27 tph_cap = get_conf_long(d, where + PCI_TPH_CAPABILITIES);
28
29 if (tph_cap & PCI_TPH_INTVEC_SUP)
30 printf("\t\tInterrupt vector mode supported\n");
31 if (tph_cap & PCI_TPH_DEV_SUP)
32 printf("\t\tDevice specific mode supported\n");
33 if (tph_cap & PCI_TPH_EXT_REQ_SUP)
34 printf("\t\tExtended requester support\n");
35
36 switch (tph_cap & PCI_TPH_ST_LOC_MASK) {
37 case PCI_TPH_ST_NONE:
38 printf("\t\tNo steering table available\n");
39 break;
40 case PCI_TPH_ST_CAP:
41 printf("\t\tSteering table in TPH capability structure\n");
42 break;
43 case PCI_TPH_ST_MSIX:
44 printf("\t\tSteering table in MSI-X table\n");
45 break;
46 default:
47 printf("\t\tReserved steering table location\n");
48 break;
49 }
50}
51
52static u32
53cap_ltr_scale(u8 scale)
54{
55 return 1 << (scale * 5);
56}
57
58static void
59cap_ltr(struct device *d, int where)
60{
61 u32 scale;
62 u16 snoop, nosnoop;
63 printf("Latency Tolerance Reporting\n");
64 if (verbose < 2)
65 return;
66
67 if (!config_fetch(d, where + PCI_LTR_MAX_SNOOP, 4))
68 return;
69
70 snoop = get_conf_word(d, where + PCI_LTR_MAX_SNOOP);
71 scale = cap_ltr_scale((snoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
c3d1d465 72 printf("\t\tMax snoop latency: %" PCI_U64_FMT_U "ns\n",
6811edb8 73 ((u64)snoop & PCI_LTR_VALUE_MASK) * scale);
67da1792
MM		 74
75 nosnoop = get_conf_word(d, where + PCI_LTR_MAX_NOSNOOP);
76 scale = cap_ltr_scale((nosnoop >> PCI_LTR_SCALE_SHIFT) & PCI_LTR_SCALE_MASK);
c3d1d465 77 printf("\t\tMax no snoop latency: %" PCI_U64_FMT_U "ns\n",
6811edb8 78 ((u64)nosnoop & PCI_LTR_VALUE_MASK) * scale);
67da1792
MM		 79}
80
21ff9851 81static void
9225e71d 82cap_sec(struct device *d, int where)
21ff9851
B		 83{
84 u32 ctrl3, lane_err_stat;
85 u8 lane;
86 printf("Secondary PCI Express\n");
9225e71d 87 if (verbose < 2)
21ff9851
B		 88 return;
89
90 if (!config_fetch(d, where + PCI_SEC_LNKCTL3, 12))
91 return;
92
93 ctrl3 = get_conf_word(d, where + PCI_SEC_LNKCTL3);
018f413c 94 printf("\t\tLnkCtl3: LnkEquIntrruptEn%c PerformEqu%c\n",
21ff9851
B		 95 FLAG(ctrl3, PCI_SEC_LNKCTL3_LNK_EQU_REQ_INTR_EN),
96 FLAG(ctrl3, PCI_SEC_LNKCTL3_PERFORM_LINK_EQU));
97
98 lane_err_stat = get_conf_word(d, where + PCI_SEC_LANE_ERR);
99 printf("\t\tLaneErrStat: ");
100 if (lane_err_stat)
101 {
9f7dc65c 102 printf("LaneErr at lane:");
21ff9851
B		 103 for (lane = 0; lane_err_stat; lane_err_stat >>= 1, lane += 1)
104 if (BITS(lane_err_stat, 0, 1))
105 printf(" %u", lane);
106 }
107 else
108 printf("0");
109 printf("\n");
110}
111
c7a34993
MM		 112static void
113cap_dsn(struct device *d, int where)
114{
115 u32 t1, t2;
116 if (!config_fetch(d, where + 4, 8))
117 return;
118 t1 = get_conf_long(d, where + 4);
119 t2 = get_conf_long(d, where + 8);
120 printf("Device Serial Number %02x-%02x-%02x-%02x-%02x-%02x-%02x-%02x\n",
6f9f8fd7
MW		 121 t2 >> 24, (t2 >> 16) & 0xff, (t2 >> 8) & 0xff, t2 & 0xff,
122 t1 >> 24, (t1 >> 16) & 0xff, (t1 >> 8) & 0xff, t1 & 0xff);
c7a34993
MM		 123}
124
125static void
a1492b88 126cap_aer(struct device *d, int where, int type)
c7a34993 127{
a6625432 128 u32 l, l0, l1, l2, l3;
a1492b88 129 u16 w;
c7a34993
MM		 130
131 printf("Advanced Error Reporting\n");
9a2e4b35
YZ		 132 if (verbose < 2)
133 return;
134
a6625432 135 if (!config_fetch(d, where + PCI_ERR_UNCOR_STATUS, 40))
c7a34993
MM		 136 return;
137
138 l = get_conf_long(d, where + PCI_ERR_UNCOR_STATUS);
139 printf("\t\tUESta:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
140 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
141 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
142 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
143 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
144 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
145 l = get_conf_long(d, where + PCI_ERR_UNCOR_MASK);
146 printf("\t\tUEMsk:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
147 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
148 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
149 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
150 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
151 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
152 l = get_conf_long(d, where + PCI_ERR_UNCOR_SEVER);
153 printf("\t\tUESvrt:\tDLP%c SDES%c TLP%c FCP%c CmpltTO%c CmpltAbrt%c UnxCmplt%c RxOF%c "
154 "MalfTLP%c ECRC%c UnsupReq%c ACSViol%c\n",
155 FLAG(l, PCI_ERR_UNC_DLP), FLAG(l, PCI_ERR_UNC_SDES), FLAG(l, PCI_ERR_UNC_POISON_TLP),
156 FLAG(l, PCI_ERR_UNC_FCP), FLAG(l, PCI_ERR_UNC_COMP_TIME), FLAG(l, PCI_ERR_UNC_COMP_ABORT),
157 FLAG(l, PCI_ERR_UNC_UNX_COMP), FLAG(l, PCI_ERR_UNC_RX_OVER), FLAG(l, PCI_ERR_UNC_MALF_TLP),
158 FLAG(l, PCI_ERR_UNC_ECRC), FLAG(l, PCI_ERR_UNC_UNSUP), FLAG(l, PCI_ERR_UNC_ACS_VIOL));
159 l = get_conf_long(d, where + PCI_ERR_COR_STATUS);
aca48104 160 printf("\t\tCESta:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
c7a34993
MM		 161 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
162 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
163 l = get_conf_long(d, where + PCI_ERR_COR_MASK);
aca48104 164 printf("\t\tCEMsk:\tRxErr%c BadTLP%c BadDLLP%c Rollover%c Timeout%c AdvNonFatalErr%c\n",
c7a34993
MM		 165 FLAG(l, PCI_ERR_COR_RCVR), FLAG(l, PCI_ERR_COR_BAD_TLP), FLAG(l, PCI_ERR_COR_BAD_DLLP),
166 FLAG(l, PCI_ERR_COR_REP_ROLL), FLAG(l, PCI_ERR_COR_REP_TIMER), FLAG(l, PCI_ERR_COR_REP_ANFE));
167 l = get_conf_long(d, where + PCI_ERR_CAP);
9a54979e 168 printf("\t\tAERCap:\tFirst Error Pointer: %02x, ECRCGenCap%c ECRCGenEn%c ECRCChkCap%c ECRCChkEn%c\n"
b33a4a2b 169 "\t\t\tMultHdrRecCap%c MultHdrRecEn%c TLPPfxPres%c HdrLogCap%c\n",
c7a34993 170 PCI_ERR_CAP_FEP(l), FLAG(l, PCI_ERR_CAP_ECRC_GENC), FLAG(l, PCI_ERR_CAP_ECRC_GENE),
b33a4a2b
BH		 171 FLAG(l, PCI_ERR_CAP_ECRC_CHKC), FLAG(l, PCI_ERR_CAP_ECRC_CHKE),
172 FLAG(l, PCI_ERR_CAP_MULT_HDRC), FLAG(l, PCI_ERR_CAP_MULT_HDRE),
173 FLAG(l, PCI_ERR_CAP_TLP_PFX), FLAG(l, PCI_ERR_CAP_HDR_LOG));
a6625432
BH		 174
175 l0 = get_conf_long(d, where + PCI_ERR_HEADER_LOG);
176 l1 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 4);
177 l2 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 8);
178 l3 = get_conf_long(d, where + PCI_ERR_HEADER_LOG + 12);
179 printf("\t\tHeaderLog: %08x %08x %08x %08x\n", l0, l1, l2, l3);
a1492b88
BH		 180
181 if (type == PCI_EXP_TYPE_ROOT_PORT || type == PCI_EXP_TYPE_ROOT_EC)
182 {
183 if (!config_fetch(d, where + PCI_ERR_ROOT_COMMAND, 12))
184 return;
185
186 l = get_conf_long(d, where + PCI_ERR_ROOT_COMMAND);
187 printf("\t\tRootCmd: CERptEn%c NFERptEn%c FERptEn%c\n",
188 FLAG(l, PCI_ERR_ROOT_CMD_COR_EN),
189 FLAG(l, PCI_ERR_ROOT_CMD_NONFATAL_EN),
190 FLAG(l, PCI_ERR_ROOT_CMD_FATAL_EN));
191
192 l = get_conf_long(d, where + PCI_ERR_ROOT_STATUS);
193 printf("\t\tRootSta: CERcvd%c MultCERcvd%c UERcvd%c MultUERcvd%c\n"
aeb74fe2 194 "\t\t\t FirstFatal%c NonFatalMsg%c FatalMsg%c IntMsgNum %d\n",
a1492b88
BH		 195 FLAG(l, PCI_ERR_ROOT_COR_RCV),
196 FLAG(l, PCI_ERR_ROOT_MULTI_COR_RCV),
197 FLAG(l, PCI_ERR_ROOT_UNCOR_RCV),
198 FLAG(l, PCI_ERR_ROOT_MULTI_UNCOR_RCV),
199 FLAG(l, PCI_ERR_ROOT_FIRST_FATAL),
200 FLAG(l, PCI_ERR_ROOT_NONFATAL_RCV),
201 FLAG(l, PCI_ERR_ROOT_FATAL_RCV),
202 PCI_ERR_MSG_NUM(l));
203
204 w = get_conf_word(d, where + PCI_ERR_ROOT_COR_SRC);
205 printf("\t\tErrorSrc: ERR_COR: %04x ", w);
206
207 w = get_conf_word(d, where + PCI_ERR_ROOT_SRC);
208 printf("ERR_FATAL/NONFATAL: %04x\n", w);
209 }
c7a34993
MM		 210}
211
de91b6f2
KB		 212static void cap_dpc(struct device *d, int where)
213{
214 u16 l;
215
216 printf("Downstream Port Containment\n");
217 if (verbose < 2)
218 return;
219
220 if (!config_fetch(d, where + PCI_DPC_CAP, 8))
221 return;
222
223 l = get_conf_word(d, where + PCI_DPC_CAP);
aeb74fe2 224 printf("\t\tDpcCap:\tIntMsgNum %d, RPExt%c PoisonedTLP%c SwTrigger%c RP PIO Log %d, DL_ActiveErr%c\n",
de91b6f2
KB		 225 PCI_DPC_CAP_INT_MSG(l), FLAG(l, PCI_DPC_CAP_RP_EXT), FLAG(l, PCI_DPC_CAP_TLP_BLOCK),
226 FLAG(l, PCI_DPC_CAP_SW_TRIGGER), PCI_DPC_CAP_RP_LOG(l), FLAG(l, PCI_DPC_CAP_DL_ACT_ERR));
227
228 l = get_conf_word(d, where + PCI_DPC_CTL);
229 printf("\t\tDpcCtl:\tTrigger:%x Cmpl%c INT%c ErrCor%c PoisonedTLP%c SwTrigger%c DL_ActiveErr%c\n",
230 PCI_DPC_CTL_TRIGGER(l), FLAG(l, PCI_DPC_CTL_CMPL), FLAG(l, PCI_DPC_CTL_INT),
231 FLAG(l, PCI_DPC_CTL_ERR_COR), FLAG(l, PCI_DPC_CTL_TLP), FLAG(l, PCI_DPC_CTL_SW_TRIGGER),
232 FLAG(l, PCI_DPC_CTL_DL_ACTIVE));
233
234 l = get_conf_word(d, where + PCI_DPC_STATUS);
235 printf("\t\tDpcSta:\tTrigger%c Reason:%02x INT%c RPBusy%c TriggerExt:%02x RP PIO ErrPtr:%02x\n",
236 FLAG(l, PCI_DPC_STS_TRIGGER), PCI_DPC_STS_REASON(l), FLAG(l, PCI_DPC_STS_INT),
237 FLAG(l, PCI_DPC_STS_RP_BUSY), PCI_DPC_STS_TRIGGER_EXT(l), PCI_DPC_STS_PIO_FEP(l));
238
239 l = get_conf_word(d, where + PCI_DPC_SOURCE);
240 printf("\t\tSource:\t%04x\n", l);
241}
242
c7a34993
MM		 243static void
244cap_acs(struct device *d, int where)
245{
246 u16 w;
247
248 printf("Access Control Services\n");
9a2e4b35
YZ		 249 if (verbose < 2)
250 return;
251
c7a34993
MM		 252 if (!config_fetch(d, where + PCI_ACS_CAP, 4))
253 return;
254
255 w = get_conf_word(d, where + PCI_ACS_CAP);
256 printf("\t\tACSCap:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
257 "DirectTrans%c\n",
258 FLAG(w, PCI_ACS_CAP_VALID), FLAG(w, PCI_ACS_CAP_BLOCK), FLAG(w, PCI_ACS_CAP_REQ_RED),
259 FLAG(w, PCI_ACS_CAP_CMPLT_RED), FLAG(w, PCI_ACS_CAP_FORWARD), FLAG(w, PCI_ACS_CAP_EGRESS),
260 FLAG(w, PCI_ACS_CAP_TRANS));
261 w = get_conf_word(d, where + PCI_ACS_CTRL);
262 printf("\t\tACSCtl:\tSrcValid%c TransBlk%c ReqRedir%c CmpltRedir%c UpstreamFwd%c EgressCtrl%c "
263 "DirectTrans%c\n",
264 FLAG(w, PCI_ACS_CTRL_VALID), FLAG(w, PCI_ACS_CTRL_BLOCK), FLAG(w, PCI_ACS_CTRL_REQ_RED),
265 FLAG(w, PCI_ACS_CTRL_CMPLT_RED), FLAG(w, PCI_ACS_CTRL_FORWARD), FLAG(w, PCI_ACS_CTRL_EGRESS),
266 FLAG(w, PCI_ACS_CTRL_TRANS));
267}
268
269static void
270cap_ari(struct device *d, int where)
271{
272 u16 w;
273
274 printf("Alternative Routing-ID Interpretation (ARI)\n");
9a2e4b35
YZ		 275 if (verbose < 2)
276 return;
277
c7a34993
MM		 278 if (!config_fetch(d, where + PCI_ARI_CAP, 4))
279 return;
280
281 w = get_conf_word(d, where + PCI_ARI_CAP);
282 printf("\t\tARICap:\tMFVC%c ACS%c, Next Function: %d\n",
283 FLAG(w, PCI_ARI_CAP_MFVC), FLAG(w, PCI_ARI_CAP_ACS),
284 PCI_ARI_CAP_NFN(w));
285 w = get_conf_word(d, where + PCI_ARI_CTRL);
286 printf("\t\tARICtl:\tMFVC%c ACS%c, Function Group: %d\n",
287 FLAG(w, PCI_ARI_CTRL_MFVC), FLAG(w, PCI_ARI_CTRL_ACS),
288 PCI_ARI_CTRL_FG(w));
289}
290
291static void
292cap_ats(struct device *d, int where)
293{
294 u16 w;
295
296 printf("Address Translation Service (ATS)\n");
9a2e4b35
YZ		 297 if (verbose < 2)
298 return;
299
c7a34993
MM		 300 if (!config_fetch(d, where + PCI_ATS_CAP, 4))
301 return;
302
303 w = get_conf_word(d, where + PCI_ATS_CAP);
304 printf("\t\tATSCap:\tInvalidate Queue Depth: %02x\n", PCI_ATS_CAP_IQD(w));
305 w = get_conf_word(d, where + PCI_ATS_CTRL);
306 printf("\t\tATSCtl:\tEnable%c, Smallest Translation Unit: %02x\n",
307 FLAG(w, PCI_ATS_CTRL_ENABLE), PCI_ATS_CTRL_STU(w));
308}
309
a858df0d
DW		 310static void
311cap_pri(struct device *d, int where)
312{
313 u16 w;
314 u32 l;
315
316 printf("Page Request Interface (PRI)\n");
317 if (verbose < 2)
318 return;
319
320 if (!config_fetch(d, where + PCI_PRI_CTRL, 0xc))
321 return;
322
323 w = get_conf_word(d, where + PCI_PRI_CTRL);
bfd8658f 324 printf("\t\tPRICtl: Enable%c Reset%c\n",
a858df0d
DW		 325 FLAG(w, PCI_PRI_CTRL_ENABLE), FLAG(w, PCI_PRI_CTRL_RESET));
326 w = get_conf_word(d, where + PCI_PRI_STATUS);
548a6e3b 327 printf("\t\tPRISta: RF%c UPRGI%c Stopped%c PASID%c\n",
a858df0d 328 FLAG(w, PCI_PRI_STATUS_RF), FLAG(w, PCI_PRI_STATUS_UPRGI),
548a6e3b 329 FLAG(w, PCI_PRI_STATUS_STOPPED), FLAG(w, PCI_PRI_STATUS_PASID));
a858df0d
DW		 330 l = get_conf_long(d, where + PCI_PRI_MAX_REQ);
331 printf("\t\tPage Request Capacity: %08x, ", l);
332 l = get_conf_long(d, where + PCI_PRI_ALLOC_REQ);
333 printf("Page Request Allocation: %08x\n", l);
334}
335
336static void
337cap_pasid(struct device *d, int where)
338{
339 u16 w;
340
341 printf("Process Address Space ID (PASID)\n");
342 if (verbose < 2)
343 return;
344
345 if (!config_fetch(d, where + PCI_PASID_CAP, 4))
346 return;
347
348 w = get_conf_word(d, where + PCI_PASID_CAP);
bfd8658f 349 printf("\t\tPASIDCap: Exec%c Priv%c, Max PASID Width: %02x\n",
a858df0d
DW		 350 FLAG(w, PCI_PASID_CAP_EXEC), FLAG(w, PCI_PASID_CAP_PRIV),
351 PCI_PASID_CAP_WIDTH(w));
352 w = get_conf_word(d, where + PCI_PASID_CTRL);
bfd8658f 353 printf("\t\tPASIDCtl: Enable%c Exec%c Priv%c\n",
a858df0d
DW		 354 FLAG(w, PCI_PASID_CTRL_ENABLE), FLAG(w, PCI_PASID_CTRL_EXEC),
355 FLAG(w, PCI_PASID_CTRL_PRIV));
356}
357
c7a34993
MM		 358static void
359cap_sriov(struct device *d, int where)
360{
361 u16 b;
362 u16 w;
363 u32 l;
67e78b32 364 int i;
c7a34993
MM		 365
366 printf("Single Root I/O Virtualization (SR-IOV)\n");
9a2e4b35
YZ		 367 if (verbose < 2)
368 return;
369
c7a34993
MM		 370 if (!config_fetch(d, where + PCI_IOV_CAP, 0x3c))
371 return;
372
373 l = get_conf_long(d, where + PCI_IOV_CAP);
aeb74fe2 374 printf("\t\tIOVCap:\tMigration%c 10BitTagReq%c IntMsgNum %d\n",
053d08d2 375 FLAG(l, PCI_IOV_CAP_VFM), FLAG(l, PCI_IOV_CAP_VF_10BIT_TAG_REQ), PCI_IOV_CAP_IMN(l));
c7a34993 376 w = get_conf_word(d, where + PCI_IOV_CTRL);
053d08d2 377 printf("\t\tIOVCtl:\tEnable%c Migration%c Interrupt%c MSE%c ARIHierarchy%c 10BitTagReq%c\n",
c7a34993
MM		 378 FLAG(w, PCI_IOV_CTRL_VFE), FLAG(w, PCI_IOV_CTRL_VFME),
379 FLAG(w, PCI_IOV_CTRL_VFMIE), FLAG(w, PCI_IOV_CTRL_MSE),
053d08d2 380 FLAG(w, PCI_IOV_CTRL_ARI), FLAG(w, PCI_IOV_CTRL_VF_10BIT_TAG_REQ_EN));
c7a34993
MM		 381 w = get_conf_word(d, where + PCI_IOV_STATUS);
382 printf("\t\tIOVSta:\tMigration%c\n", FLAG(w, PCI_IOV_STATUS_MS));
383 w = get_conf_word(d, where + PCI_IOV_INITIALVF);
384 printf("\t\tInitial VFs: %d, ", w);
385 w = get_conf_word(d, where + PCI_IOV_TOTALVF);
386 printf("Total VFs: %d, ", w);
387 w = get_conf_word(d, where + PCI_IOV_NUMVF);
388 printf("Number of VFs: %d, ", w);
389 b = get_conf_byte(d, where + PCI_IOV_FDL);
390 printf("Function Dependency Link: %02x\n", b);
391 w = get_conf_word(d, where + PCI_IOV_OFFSET);
392 printf("\t\tVF offset: %d, ", w);
393 w = get_conf_word(d, where + PCI_IOV_STRIDE);
394 printf("stride: %d, ", w);
395 w = get_conf_word(d, where + PCI_IOV_DID);
396 printf("Device ID: %04x\n", w);
397 l = get_conf_long(d, where + PCI_IOV_SUPPS);
398 printf("\t\tSupported Page Size: %08x, ", l);
399 l = get_conf_long(d, where + PCI_IOV_SYSPS);
400 printf("System Page Size: %08x\n", l);
b9e11c65
MM		 401
402 for (i=0; i < PCI_IOV_NUM_BAR; i++)
403 {
187bf2f5 404 u32 addr;
b9e11c65
MM		 405 int type;
406 u32 h;
407 l = get_conf_long(d, where + PCI_IOV_BAR_BASE + 4*i);
408 if (l == 0xffffffff)
409 l = 0;
410 if (!l)
411 continue;
412 printf("\t\tRegion %d: Memory at ", i);
413 addr = l & PCI_ADDR_MEM_MASK;
414 type = l & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
415 if (type == PCI_BASE_ADDRESS_MEM_TYPE_64)
416 {
417 i++;
418 h = get_conf_long(d, where + PCI_IOV_BAR_BASE + (i*4));
187bf2f5 419 printf("%08x", h);
b9e11c65 420 }
187bf2f5
MM		 421 printf("%08x (%s-bit, %sprefetchable)\n",
422 addr,
b9e11c65
MM		 423 (type == PCI_BASE_ADDRESS_MEM_TYPE_32) ? "32" : "64",
424 (l & PCI_BASE_ADDRESS_MEM_PREFETCH) ? "" : "non-");
67e78b32 425 }
b9e11c65 426
edca3520 427 l = get_conf_long(d, where + PCI_IOV_MSAO);
c7a34993
MM		 428 printf("\t\tVF Migration: offset: %08x, BIR: %x\n", PCI_IOV_MSA_OFFSET(l),
429 PCI_IOV_MSA_BIR(l));
430}
431
c0d9545c
BH		 432static void
433cap_multicast(struct device *d, int where, int type)
434{
435 u16 w;
436 u32 l;
437 u64 bar, rcv, block;
438
439 printf("Multicast\n");
440 if (verbose < 2)
441 return;
442
443 if (!config_fetch(d, where + PCI_MCAST_CAP, 0x30))
444 return;
445
446 w = get_conf_word(d, where + PCI_MCAST_CAP);
447 printf("\t\tMcastCap: MaxGroups %d", PCI_MCAST_CAP_MAX_GROUP(w) + 1);
448 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
449 printf(", WindowSz %d (%d bytes)",
450 PCI_MCAST_CAP_WIN_SIZE(w), 1 << PCI_MCAST_CAP_WIN_SIZE(w));
451 if (type == PCI_EXP_TYPE_ROOT_PORT ||
452 type == PCI_EXP_TYPE_UPSTREAM || type == PCI_EXP_TYPE_DOWNSTREAM)
453 printf(", ECRCRegen%c\n", FLAG(w, PCI_MCAST_CAP_ECRC));
454 w = get_conf_word(d, where + PCI_MCAST_CTRL);
455 printf("\t\tMcastCtl: NumGroups %d, Enable%c\n",
456 PCI_MCAST_CTRL_NUM_GROUP(w) + 1, FLAG(w, PCI_MCAST_CTRL_ENABLE));
457 bar = get_conf_long(d, where + PCI_MCAST_BAR);
458 l = get_conf_long(d, where + PCI_MCAST_BAR + 4);
459 bar |= (u64) l << 32;
460 printf("\t\tMcastBAR: IndexPos %d, BaseAddr %016" PCI_U64_FMT_X "\n",
461 PCI_MCAST_BAR_INDEX_POS(bar), bar & PCI_MCAST_BAR_MASK);
462 rcv = get_conf_long(d, where + PCI_MCAST_RCV);
463 l = get_conf_long(d, where + PCI_MCAST_RCV + 4);
464 rcv |= (u64) l << 32;
465 printf("\t\tMcastReceiveVec: %016" PCI_U64_FMT_X "\n", rcv);
466 block = get_conf_long(d, where + PCI_MCAST_BLOCK);
467 l = get_conf_long(d, where + PCI_MCAST_BLOCK + 4);
468 block |= (u64) l << 32;
469 printf("\t\tMcastBlockAllVec: %016" PCI_U64_FMT_X "\n", block);
470 block = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS);
471 l = get_conf_long(d, where + PCI_MCAST_BLOCK_UNTRANS + 4);
472 block |= (u64) l << 32;
473 printf("\t\tMcastBlockUntransVec: %016" PCI_U64_FMT_X "\n", block);
474
475 if (type == PCI_EXP_TYPE_ENDPOINT || type == PCI_EXP_TYPE_ROOT_INT_EP)
476 return;
477 bar = get_conf_long(d, where + PCI_MCAST_OVL_BAR);
478 l = get_conf_long(d, where + PCI_MCAST_OVL_BAR + 4);
479 bar |= (u64) l << 32;
480 printf("\t\tMcastOverlayBAR: OverlaySize %d ", PCI_MCAST_OVL_SIZE(bar));
481 if (PCI_MCAST_OVL_SIZE(bar) >= 6)
482 printf("(%d bytes)", 1 << PCI_MCAST_OVL_SIZE(bar));
483 else
484 printf("(disabled)");
485 printf(", BaseAddr %016" PCI_U64_FMT_X "\n", bar & PCI_MCAST_OVL_MASK);
486}
487
33088c24
MM		 488static void
489cap_vc(struct device *d, int where)
490{
491 u32 cr1, cr2;
492 u16 ctrl, status;
493 int evc_cnt;
494 int arb_table_pos;
495 int i, j;
3d8b5258 496 static const char ref_clocks[][6] = { "100ns" };
3edae14a
MM		 497 static const char arb_selects[8][7] = { "Fixed", "WRR32", "WRR64", "WRR128", "??4", "??5", "??6", "??7" };
498 static const char vc_arb_selects[8][8] = { "Fixed", "WRR32", "WRR64", "WRR128", "TWRR128", "WRR256", "??6", "??7" };
3d8b5258 499 char buf[8];
33088c24
MM		 500
501 printf("Virtual Channel\n");
502 if (verbose < 2)
503 return;
504
505 if (!config_fetch(d, where + 4, 0x1c - 4))
506 return;
507
508 cr1 = get_conf_long(d, where + PCI_VC_PORT_REG1);
509 cr2 = get_conf_long(d, where + PCI_VC_PORT_REG2);
510 ctrl = get_conf_word(d, where + PCI_VC_PORT_CTRL);
511 status = get_conf_word(d, where + PCI_VC_PORT_STATUS);
512
3d8b5258 513 evc_cnt = BITS(cr1, 0, 3);
d676f20d 514 printf("\t\tCaps:\tLPEVC=%d RefClk=%s PATEntryBits=%d\n",
3d8b5258
MM		 515 BITS(cr1, 4, 3),
516 TABLE(ref_clocks, BITS(cr1, 8, 2), buf),
d676f20d 517 1 << BITS(cr1, 10, 2));
33088c24 518
d676f20d 519 printf("\t\tArb:");
33088c24
MM		 520 for (i=0; i<8; i++)
521 if (arb_selects[i][0] != '?' || cr2 & (1 << i))
d676f20d 522 printf("%c%s%c", (i ? ' ' : '\t'), arb_selects[i], FLAG(cr2, 1 << i));
3d8b5258 523 arb_table_pos = BITS(cr2, 24, 8);
33088c24 524
d676f20d 525 printf("\n\t\tCtrl:\tArbSelect=%s\n", TABLE(arb_selects, BITS(ctrl, 1, 3), buf));
33088c24
MM		 526 printf("\t\tStatus:\tInProgress%c\n", FLAG(status, 1));
527
528 if (arb_table_pos)
d676f20d
MM		 529 {
530 arb_table_pos = where + 16*arb_table_pos;
531 printf("\t\tPort Arbitration Table [%x] <?>\n", arb_table_pos);
532 }
33088c24
MM		 533
534 for (i=0; i<=evc_cnt; i++)
535 {
536 int pos = where + PCI_VC_RES_CAP + 12*i;
537 u32 rcap, rctrl;
538 u16 rstatus;
539 int pat_pos;
540
5a9a932c 541 printf("\t\tVC%d:\t", i);
33088c24
MM		 542 if (!config_fetch(d, pos, 12))
543 {
5a9a932c 544 printf("<unreadable>\n");
33088c24
MM		 545 continue;
546 }
547 rcap = get_conf_long(d, pos);
548 rctrl = get_conf_long(d, pos+4);
7970509b 549 rstatus = get_conf_word(d, pos+10);
33088c24 550
3d8b5258 551 pat_pos = BITS(rcap, 24, 8);
5a9a932c 552 printf("Caps:\tPATOffset=%02x MaxTimeSlots=%d RejSnoopTrans%c\n",
33088c24 553 pat_pos,
3711e86f 554 BITS(rcap, 16, 7) + 1,
33088c24
MM		 555 FLAG(rcap, 1 << 15));
556
557 printf("\t\t\tArb:");
558 for (j=0; j<8; j++)
559 if (vc_arb_selects[j][0] != '?' || rcap & (1 << j))
560 printf("%c%s%c", (j ? ' ' : '\t'), vc_arb_selects[j], FLAG(rcap, 1 << j));
561
562 printf("\n\t\t\tCtrl:\tEnable%c ID=%d ArbSelect=%s TC/VC=%02x\n",
563 FLAG(rctrl, 1 << 31),
3d8b5258
MM		 564 BITS(rctrl, 24, 3),
565 TABLE(vc_arb_selects, BITS(rctrl, 17, 3), buf),
566 BITS(rctrl, 0, 8));
33088c24
MM		 567
568 printf("\t\t\tStatus:\tNegoPending%c InProgress%c\n",
569 FLAG(rstatus, 2),
570 FLAG(rstatus, 1));
571
572 if (pat_pos)
573 printf("\t\t\tPort Arbitration Table <?>\n");
574 }
575}
576
5a9a932c
MM		 577static void
578cap_rclink(struct device *d, int where)
579{
580 u32 esd;
581 int num_links;
582 int i;
583 static const char elt_types[][9] = { "Config", "Egress", "Internal" };
584 char buf[8];
585
586 printf("Root Complex Link\n");
587 if (verbose < 2)
588 return;
589
590 if (!config_fetch(d, where + 4, PCI_RCLINK_LINK1 - 4))
591 return;
592
593 esd = get_conf_long(d, where + PCI_RCLINK_ESD);
594 num_links = BITS(esd, 8, 8);
595 printf("\t\tDesc:\tPortNumber=%02x ComponentID=%02x EltType=%s\n",
596 BITS(esd, 24, 8),
597 BITS(esd, 16, 8),
598 TABLE(elt_types, BITS(esd, 0, 8), buf));
599
600 for (i=0; i<num_links; i++)
601 {
602 int pos = where + PCI_RCLINK_LINK1 + i*PCI_RCLINK_LINK_SIZE;
603 u32 desc;
604 u32 addr_lo, addr_hi;
605
606 printf("\t\tLink%d:\t", i);
607 if (!config_fetch(d, pos, PCI_RCLINK_LINK_SIZE))
608 {
609 printf("<unreadable>\n");
610 return;
611 }
612 desc = get_conf_long(d, pos + PCI_RCLINK_LINK_DESC);
613 addr_lo = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR);
614 addr_hi = get_conf_long(d, pos + PCI_RCLINK_LINK_ADDR + 4);
615
616 printf("Desc:\tTargetPort=%02x TargetComponent=%02x AssocRCRB%c LinkType=%s LinkValid%c\n",
617 BITS(desc, 24, 8),
618 BITS(desc, 16, 8),
619 FLAG(desc, 4),
620 ((desc & 2) ? "Config" : "MemMapped"),
621 FLAG(desc, 1));
622
623 if (desc & 2)
624 {
625 int n = addr_lo & 7;
626 if (!n)
627 n = 8;
628 printf("\t\t\tAddr:\t%02x:%02x.%d CfgSpace=%08x%08x\n",
629 BITS(addr_lo, 20, n),
630 BITS(addr_lo, 15, 5),
631 BITS(addr_lo, 12, 3),
632 addr_hi, addr_lo);
633 }
634 else
635 printf("\t\t\tAddr:\t%08x%08x\n", addr_hi, addr_lo);
636 }
637}
638
e12bd01e
SK		 639static void
640cap_rcec(struct device *d, int where)
641{
642 printf("Root Complex Event Collector Endpoint Association\n");
643 if (verbose < 2)
644 return;
645
646 if (!config_fetch(d, where, 12))
647 return;
648
649 u32 hdr = get_conf_long(d, where);
650 byte cap_ver = PCI_RCEC_EP_CAP_VER(hdr);
651 u32 bmap = get_conf_long(d, where + PCI_RCEC_RCIEP_BMAP);
652 printf("\t\tRCiEPBitmap: ");
653 if (bmap)
654 {
655 int prevmatched=0;
656 int adjcount=0;
657 int prevdev=0;
658 printf("RCiEP at Device(s):");
659 for (int dev=0; dev < 32; dev++)
660 {
661 if (BITS(bmap, dev, 1))
662 {
663 if (!adjcount)
664 printf("%s %u", (prevmatched) ? "," : "", dev);
665 adjcount++;
666 prevdev=dev;
667 prevmatched=1;
668 }
669 else
670 {
671 if (adjcount > 1)
672 printf("-%u", prevdev);
673 adjcount=0;
674 }
675 }
676 }
677 else
678 printf("%s", (verbose > 2) ? "00000000 [none]" : "[none]");
679 printf("\n");
680
681 if (cap_ver < PCI_RCEC_BUSN_REG_VER)
682 return;
683
684 u32 busn = get_conf_long(d, where + PCI_RCEC_BUSN_REG);
685 u8 lastbusn = BITS(busn, 16, 8);
686 u8 nextbusn = BITS(busn, 8, 8);
687
688 if ((lastbusn == 0x00) && (nextbusn == 0xff))
689 printf("\t\tAssociatedBusNumbers: %s\n", (verbose > 2) ? "ff-00 [none]" : "[none]");
690 else
691 printf("\t\tAssociatedBusNumbers: %02x-%02x\n", nextbusn, lastbusn );
692}
693
52097446
BW		 694static void
695cxl_range(u64 base, u64 size, int n)
696{
697 u32 interleave[] = { 0, 256, 4096, 512, 1024, 2048, 8192, 16384 };
698 const char *type[] = { "Volatile", "Non-volatile", "CDAT" };
699 const char *class[] = { "DRAM", "Storage", "CDAT" };
700 u16 w;
701
702 w = (u16) size;
703
704 size &= ~0x0fffffffULL;
705
c0ccce1b 706 printf("\t\tRange%d: %016"PCI_U64_FMT_X"-%016"PCI_U64_FMT_X" [size=0x%"PCI_U64_FMT_X"]\n", n, base, base + size - 1, size);
52097446
BW		 707 printf("\t\t\tValid%c Active%c Type=%s Class=%s interleave=%d timeout=%ds\n",
708 FLAG(w, PCI_CXL_RANGE_VALID), FLAG(w, PCI_CXL_RANGE_ACTIVE),
709 type[PCI_CXL_RANGE_TYPE(w)], class[PCI_CXL_RANGE_CLASS(w)],
710 interleave[PCI_CXL_RANGE_INTERLEAVE(w)],
711 1 << (PCI_CXL_RANGE_TIMEOUT(w) * 2));
712}
713
bd853ef8 714static void
2849db67 715dvsec_cxl_device(struct device *d, int rev, int where, int len)
bd853ef8 716{
2849db67 717 u32 cache_size, cache_unit_size;
52097446 718 u64 range_base, range_size;
ccf5ff41 719 u16 w;
bd853ef8 720
c0ccce1b 721 if (len < 0x38)
2849db67
MM		 722 return;
723
0d4491cb 724 /* Legacy 1.1 revs aren't handled */
c0ccce1b 725 if (rev == 0)
bd853ef8
SK		 726 return;
727
3d2d69cb
MM		 728 if (rev >= 1)
729 {
730 w = get_conf_word(d, where + PCI_CXL_DEV_CAP);
731 printf("\t\tCXLCap:\tCache%c IO%c Mem%c MemHWInit%c HDMCount %d Viral%c\n",
732 FLAG(w, PCI_CXL_DEV_CAP_CACHE), FLAG(w, PCI_CXL_DEV_CAP_IO), FLAG(w, PCI_CXL_DEV_CAP_MEM),
733 FLAG(w, PCI_CXL_DEV_CAP_MEM_HWINIT), PCI_CXL_DEV_CAP_HDM_CNT(w), FLAG(w, PCI_CXL_DEV_CAP_VIRAL));
734
735 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL);
736 printf("\t\tCXLCtl:\tCache%c IO%c Mem%c CacheSFCov %d CacheSFGran %d CacheClean%c Viral%c\n",
737 FLAG(w, PCI_CXL_DEV_CTRL_CACHE), FLAG(w, PCI_CXL_DEV_CTRL_IO), FLAG(w, PCI_CXL_DEV_CTRL_MEM),
738 PCI_CXL_DEV_CTRL_CACHE_SF_COV(w), PCI_CXL_DEV_CTRL_CACHE_SF_GRAN(w), FLAG(w, PCI_CXL_DEV_CTRL_CACHE_CLN),
739 FLAG(w, PCI_CXL_DEV_CTRL_VIRAL));
740
741 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS);
742 printf("\t\tCXLSta:\tViral%c\n", FLAG(w, PCI_CXL_DEV_STATUS_VIRAL));
743
744 w = get_conf_word(d, where + PCI_CXL_DEV_CTRL2);
745 printf("\t\tCXLCtl2:\tDisableCaching%c InitCacheWB&Inval%c InitRst%c RstMemClrEn%c",
746 FLAG(w, PCI_CXL_DEV_CTRL2_DISABLE_CACHING),
747 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_WB_INVAL),
748 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST),
749 FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_RST_CLR_EN));
750 if (rev >= 2)
751 printf(" DesiredVolatileHDMStateAfterHotReset%c", FLAG(w, PCI_CXL_DEV_CTRL2_INIT_CXL_HDM_STATE_HOTRST));
752 printf("\n");
753
754 w = get_conf_word(d, where + PCI_CXL_DEV_STATUS2);
755 printf("\t\tCXLSta2:\tResetComplete%c ResetError%c PMComplete%c\n",
756 FLAG(w, PCI_CXL_DEV_STATUS_RC), FLAG(w,PCI_CXL_DEV_STATUS_RE), FLAG(w, PCI_CXL_DEV_STATUS_PMC));
757
758 w = get_conf_word(d, where + PCI_CXL_DEV_CAP2);
759 printf("\t\tCXLCap2:\t");
760 cache_unit_size = BITS(w, 0, 4);
761 cache_size = BITS(w, 8, 8);
762 switch (cache_unit_size)
763 {
764 case PCI_CXL_DEV_CAP2_CACHE_1M:
765 printf("Cache Size: %08x\n", cache_size * (1<<20));
766 break;
767 case PCI_CXL_DEV_CAP2_CACHE_64K:
768 printf("Cache Size: %08x\n", cache_size * (64<<10));
769 break;
770 case PCI_CXL_DEV_CAP2_CACHE_UNK:
771 printf("Cache Size Not Reported\n");
772 break;
773 default:
774 printf("Cache Size: %d of unknown unit size (%d)\n", cache_size, cache_unit_size);
775 break;
776 }
777
778 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_HI) << 32;
779 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_SIZE_LO);
780 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_HI) << 32;
781 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE1_BASE_LO);
782 cxl_range(range_base, range_size, 1);
783
784 range_size = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_HI) << 32;
785 range_size |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_SIZE_LO);
786 range_base = (u64) get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_HI) << 32;
787 range_base |= get_conf_long(d, where + PCI_CXL_DEV_RANGE2_BASE_LO);
788 cxl_range(range_base, range_size, 2);
c0ccce1b 789 }
52097446 790
3d2d69cb
MM		 791 if (rev >= 2)
792 {
793 w = get_conf_word(d, where + PCI_CXL_DEV_CAP3);
794 printf("\t\tCXLCap3:\tDefaultVolatile HDM State After:\tColdReset%c WarmReset%c HotReset%c HotResetConfigurability%c\n",
795 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_COLD),
796 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_WARM),
797 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT),
798 FLAG(w, PCI_CXL_DEV_CAP3_HDM_STATE_RST_HOT_CFG));
799 }
52097446 800
c0ccce1b 801 // Unparsed data
3d2d69cb 802 if (len > PCI_CXL_DEV_LEN)
c0ccce1b 803 printf("\t\t<?>\n");
bd853ef8
SK		 804}
805
c8b83c6c 806static void
2849db67 807dvsec_cxl_port(struct device *d, int where, int len)
c8b83c6c
BW		 808{
809 u16 w, m1, m2;
810 u8 b1, b2;
811
2849db67
MM		 812 if (len < PCI_CXL_PORT_EXT_LEN)
813 return;
814
c8b83c6c
BW		 815 w = get_conf_word(d, where + PCI_CXL_PORT_EXT_STATUS);
816 printf("\t\tCXLPortSta:\tPMComplete%c\n", FLAG(w, PCI_CXL_PORT_EXT_STATUS));
817
818 w = get_conf_word(d, where + PCI_CXL_PORT_CTRL);
819 printf("\t\tCXLPortCtl:\tUnmaskSBR%c UnmaskLinkDisable%c AltMem%c AltBME%c ViralEnable%c\n",
820 FLAG(w, PCI_CXL_PORT_UNMASK_SBR), FLAG(w, PCI_CXL_PORT_UNMASK_LINK),
821 FLAG(w, PCI_CXL_PORT_ALT_MEMORY), FLAG(w, PCI_CXL_PORT_ALT_BME),
822 FLAG(w, PCI_CXL_PORT_VIRAL_EN));
823
824 b1 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_BASE);
825 b2 = get_conf_byte(d, where + PCI_CXL_PORT_ALT_BUS_LIMIT);
826 printf("\t\tAlternateBus:\t%02x-%02x\n", b1, b2);
827 m1 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_BASE);
828 m2 = get_conf_word(d, where + PCI_CXL_PORT_ALT_MEM_LIMIT);
829 printf("\t\tAlternateBus:\t%04x-%04x\n", m1, m2);
830}
831
2849db67
MM		 832static void
833dvsec_cxl_register_locator(struct device *d, int where, int len)
0dfa1050 834{
2849db67
MM		 835 static const char * const id_names[] = {
836 "empty",
837 "component registers",
838 "BAR virtualization",
839 "CXL device registers",
840 "CPMU registers",
841 };
842
843 for (int i=0; ; i++)
844 {
55704534
JH		 845 int pos = where + PCI_CXL_RL_BLOCK1_LO + 8*i;
846 if (pos + 7 >= where + len)
2849db67 847 break;
0dfa1050 848
2849db67
MM		 849 u32 lo = get_conf_long(d, pos);
850 u32 hi = get_conf_long(d, pos + 4);
0dfa1050 851
2849db67
MM		 852 unsigned int bir = BITS(lo, 0, 3);
853 unsigned int block_id = BITS(lo, 8, 8);
854 u64 base = (BITS(lo, 16, 16) << 16) | ((u64) hi << 32);
0dfa1050 855
2849db67
MM		 856 if (!block_id)
857 continue;
0dfa1050 858
2849db67
MM		 859 const char *id_name;
860 if (block_id < sizeof(id_names) / sizeof(*id_names))
861 id_name = id_names[block_id];
862 else if (block_id == 0xff)
863 id_name = "vendor-specific";
864 else
865 id_name = "<?>";
0dfa1050 866
55704534 867 printf("\t\tBlock%d: BIR: bar%d, ID: %s, offset: %016" PCI_U64_FMT_X "\n", i + 1, bir, id_name, base);
2849db67 868 }
0dfa1050
BW		 869}
870
d462e89c
JH		 871static void
872dvsec_cxl_gpf_device(struct device *d, int where)
873{
874 u32 l;
875 u16 w, duration;
876 u8 time_base, time_scale;
877
878 w = get_conf_word(d, where + PCI_CXL_GPF_DEV_PHASE2_DUR);
879 time_base = BITS(w, 0, 4);
880 time_scale = BITS(w, 8, 4);
881
882 switch (time_scale)
883 {
884 case PCI_CXL_GPF_DEV_100US:
885 case PCI_CXL_GPF_DEV_100MS:
886 duration = time_base * 100;
887 break;
888 case PCI_CXL_GPF_DEV_10US:
889 case PCI_CXL_GPF_DEV_10MS:
890 case PCI_CXL_GPF_DEV_10S:
891 duration = time_base * 10;
892 break;
893 case PCI_CXL_GPF_DEV_1US:
894 case PCI_CXL_GPF_DEV_1MS:
895 case PCI_CXL_GPF_DEV_1S:
896 duration = time_base;
897 break;
898 default:
899 /* Reserved */
900 printf("\t\tReserved time scale encoding %x\n", time_scale);
901 duration = time_base;
902 }
903
904 printf("\t\tGPF Phase 2 Duration: %u%s\n", duration,
905 (time_scale < PCI_CXL_GPF_DEV_1MS) ? "us":
906 (time_scale < PCI_CXL_GPF_DEV_1S) ? "ms" :
907 (time_scale == PCI_CXL_GPF_DEV_1S) ? "s" : "<?>");
908
909 l = get_conf_long(d, where + PCI_CXL_GPF_DEV_PHASE2_POW);
910 printf("\t\tGPF Phase 2 Power: %umW\n", (unsigned int)l);
911}
912
5c75f737
JH		 913static void
914dvsec_cxl_gpf_port(struct device *d, int where)
915{
916 u16 w, timeout;
917 u8 time_base, time_scale;
918
919 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE1_CTRL);
920 time_base = BITS(w, 0, 4);
921 time_scale = BITS(w, 8, 4);
922
923 switch (time_scale)
924 {
925 case PCI_CXL_GPF_PORT_100US:
926 case PCI_CXL_GPF_PORT_100MS:
927 timeout = time_base * 100;
928 break;
929 case PCI_CXL_GPF_PORT_10US:
930 case PCI_CXL_GPF_PORT_10MS:
931 case PCI_CXL_GPF_PORT_10S:
932 timeout = time_base * 10;
933 break;
934 case PCI_CXL_GPF_PORT_1US:
935 case PCI_CXL_GPF_PORT_1MS:
936 case PCI_CXL_GPF_PORT_1S:
937 timeout = time_base;
938 break;
939 default:
940 /* Reserved */
941 printf("\t\tReserved time scale encoding %x\n", time_scale);
942 timeout = time_base;
943 }
944
945 printf("\t\tGPF Phase 1 Timeout: %d%s\n", timeout,
946 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
947 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
948 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
949
950 w = get_conf_word(d, where + PCI_CXL_GPF_PORT_PHASE2_CTRL);
951 time_base = BITS(w, 0, 4);
952 time_scale = BITS(w, 8, 4);
953
954 switch (time_scale)
955 {
956 case PCI_CXL_GPF_PORT_100US:
957 case PCI_CXL_GPF_PORT_100MS:
958 timeout = time_base * 100;
959 break;
960 case PCI_CXL_GPF_PORT_10US:
961 case PCI_CXL_GPF_PORT_10MS:
962 case PCI_CXL_GPF_PORT_10S:
963 timeout = time_base * 10;
964 break;
965 case PCI_CXL_GPF_PORT_1US:
966 case PCI_CXL_GPF_PORT_1MS:
967 case PCI_CXL_GPF_PORT_1S:
968 timeout = time_base;
969 break;
970 default:
971 /* Reserved */
972 printf("\t\tReserved time scale encoding %x\n", time_scale);
973 timeout = time_base;
974 }
975
976 printf("\t\tGPF Phase 2 Timeout: %d%s\n", timeout,
977 (time_scale < PCI_CXL_GPF_PORT_1MS) ? "us":
978 (time_scale < PCI_CXL_GPF_PORT_1S) ? "ms" :
979 (time_scale == PCI_CXL_GPF_PORT_1S) ? "s" : "<?>");
980}
981
9e567a4e 982static void
23b1ee0c 983dvsec_cxl_flex_bus(struct device *d, int where, int rev, int len)
9e567a4e
JH		 984{
985 u16 w;
986 u32 l, data;
987
23b1ee0c
AG		 988 // Sanity check: Does the length correspond to its revision?
989 switch (rev) {
990 case 0:
3d2d69cb 991 if (len != PCI_CXL_FB_MOD_TS_DATA)
23b1ee0c 992 printf("\t\t<Wrong length for Revision %d>\n", rev);
23b1ee0c
AG		 993 break;
994 case 1:
3d2d69cb 995 if (len != PCI_CXL_FB_PORT_CAP2)
23b1ee0c 996 printf("\t\t<Wrong length for Revision %d>\n", rev);
23b1ee0c
AG		 997 break;
998 case 2:
3d2d69cb 999 if (len != PCI_CXL_FB_NEXT_UNSUPPORTED)
23b1ee0c 1000 printf("\t\t<Wrong length for Revision %d>\n", rev);
23b1ee0c
AG		 1001 break;
1002 default:
1003 break;
9e567a4e
JH		 1004 }
1005
23b1ee0c 1006 // From Rev 0
9e567a4e
JH		 1007 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CAP);
1008 printf("\t\tFBCap:\tCache%c IO%c Mem%c 68BFlit%c MltLogDev%c",
1009 FLAG(w, PCI_CXL_FB_CAP_CACHE), FLAG(w, PCI_CXL_FB_CAP_IO),
1010 FLAG(w, PCI_CXL_FB_CAP_MEM), FLAG(w, PCI_CXL_FB_CAP_68B_FLIT),
1011 FLAG(w, PCI_CXL_FB_CAP_MULT_LOG_DEV));
1012
1013 if (rev > 1)
1014 printf(" 256BFlit%c PBRFlit%c",
1015 FLAG(w, PCI_CXL_FB_CAP_256B_FLIT), FLAG(w, PCI_CXL_FB_CAP_PBR_FLIT));
1016
1017 w = get_conf_word(d, where + PCI_CXL_FB_PORT_CTRL);
1018 printf("\n\t\tFBCtl:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c RCD%c Retimer1%c Retimer2%c",
1019 FLAG(w, PCI_CXL_FB_CTRL_CACHE), FLAG(w, PCI_CXL_FB_CTRL_IO),
1020 FLAG(w, PCI_CXL_FB_CTRL_MEM), FLAG(w, PCI_CXL_FB_CTRL_SYNC_HDR_BYP),
1021 FLAG(w, PCI_CXL_FB_CTRL_DRFT_BUF), FLAG(w, PCI_CXL_FB_CTRL_68B_FLIT),
1022 FLAG(w, PCI_CXL_FB_CTRL_MULT_LOG_DEV), FLAG(w, PCI_CXL_FB_CTRL_RCD),
1023 FLAG(w, PCI_CXL_FB_CTRL_RETIMER1), FLAG(w, PCI_CXL_FB_CTRL_RETIMER2));
1024
1025 if (rev > 1)
1026 printf(" 256BFlit%c PBRFlit%c",
1027 FLAG(w, PCI_CXL_FB_CTRL_256B_FLIT), FLAG(w, PCI_CXL_FB_CTRL_PBR_FLIT));
1028
1029 w = get_conf_word(d, where + PCI_CXL_FB_PORT_STATUS);
1030 printf("\n\t\tFBSta:\tCache%c IO%c Mem%c SynHdrByp%c DrftBuf%c 68BFlit%c MltLogDev%c",
1031 FLAG(w, PCI_CXL_FB_STAT_CACHE), FLAG(w, PCI_CXL_FB_STAT_IO),
1032 FLAG(w, PCI_CXL_FB_STAT_MEM), FLAG(w, PCI_CXL_FB_STAT_SYNC_HDR_BYP),
1033 FLAG(w, PCI_CXL_FB_STAT_DRFT_BUF), FLAG(w, PCI_CXL_FB_STAT_68B_FLIT),
1034 FLAG(w, PCI_CXL_FB_STAT_MULT_LOG_DEV));
1035
1036 if (rev > 1)
1037 printf(" 256BFlit%c PBRFlit%c",
1038 FLAG(w, PCI_CXL_FB_STAT_256B_FLIT), FLAG(w, PCI_CXL_FB_STAT_PBR_FLIT));
23b1ee0c 1039 printf("\n");
9e567a4e 1040
23b1ee0c
AG		 1041 // From Rev 1
1042 if (rev >= 1)
3d2d69cb
MM		 1043 {
1044 l = get_conf_long(d, where + PCI_CXL_FB_MOD_TS_DATA);
1045 data = BITS(l, 0, 24);
1046 printf("\t\tFBModTS:\tReceived FB Data: %06x\n", (unsigned int)data);
1047 }
9e567a4e 1048
23b1ee0c
AG		 1049 // From Rev 2
1050 if (rev >= 2)
3d2d69cb
MM		 1051 {
1052 u8 nop;
9e567a4e 1053
3d2d69cb
MM		 1054 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CAP2);
1055 printf("\t\tFBCap2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CAP2_NOP_HINT));
9e567a4e 1056
3d2d69cb
MM		 1057 l = get_conf_long(d, where + PCI_CXL_FB_PORT_CTRL2);
1058 printf("\t\tFBCtl2:\tNOPHint%c\n", FLAG(l, PCI_CXL_FB_CTRL2_NOP_HINT));
9e567a4e 1059
3d2d69cb
MM		 1060 l = get_conf_long(d, where + PCI_CXL_FB_PORT_STATUS2);
1061 nop = BITS(l, 0, 2);
1062 printf("\t\tFBSta2:\tNOPHintInfo: %x\n", nop);
1063 }
23b1ee0c
AG		 1064
1065 // Unparsed data
3d2d69cb 1066 if (len > PCI_CXL_FB_LEN)
23b1ee0c 1067 printf("\t\t<?>\n");
9e567a4e
JH		 1068}
1069
45824262
JH		 1070static void
1071dvsec_cxl_mld(struct device *d, int where)
1072{
1073 u16 w;
1074
1075 w = get_conf_word(d, where + PCI_CXL_MLD_NUM_LD);
1076
1077 /* Encodings greater than 16 are reserved */
1078 if (w && w <= PCI_CXL_MLD_MAX_LD)
1079 printf("\t\tNumLogDevs: %d\n", w);
1080}
1081
ec4cd47b
JH		 1082static void
1083dvsec_cxl_function_map(struct device *d, int where)
1084{
1085
1086 printf("\t\tFuncMap 0: %08x\n",
1087 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_0)));
1088
1089 printf("\t\tFuncMap 1: %08x\n",
1090 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_1)));
1091
1092 printf("\t\tFuncMap 2: %08x\n",
1093 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_2)));
1094
1095 printf("\t\tFuncMap 3: %08x\n",
1096 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_3)));
1097
1098 printf("\t\tFuncMap 4: %08x\n",
1099 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_4)));
1100
1101 printf("\t\tFuncMap 5: %08x\n",
1102 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_5)));
1103
1104 printf("\t\tFuncMap 6: %08x\n",
1105 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_6)));
1106
1107 printf("\t\tFuncMap 7: %08x\n",
1108 (unsigned int)(get_conf_word(d, where + PCI_CXL_FUN_MAP_REG_7)));
1109}
1110
0d4491cb 1111static void
2849db67 1112cap_dvsec_cxl(struct device *d, int id, int rev, int where, int len)
0d4491cb 1113{
0d4491cb
BW		 1114 printf(": CXL\n");
1115 if (verbose < 2)
1116 return;
1117
2849db67
MM		 1118 if (!config_fetch(d, where, len))
1119 return;
0d4491cb 1120
2849db67
MM		 1121 switch (id)
1122 {
c8b83c6c 1123 case 0:
23b1ee0c 1124 printf("\t\tPCIe DVSEC for CXL Devices\n");
2849db67 1125 dvsec_cxl_device(d, rev, where, len);
0dfa1050 1126 break;
fe0df5d3 1127 case 2:
23b1ee0c 1128 printf("\t\tNon-CXL Function Map DVSEC\n");
ec4cd47b 1129 dvsec_cxl_function_map(d, where);
fe0df5d3 1130 break;
2849db67 1131 case 3:
23b1ee0c 1132 printf("\t\tCXL Extensions DVSEC for Ports\n");
2849db67
MM		 1133 dvsec_cxl_port(d, where, len);
1134 break;
fe0df5d3 1135 case 4:
23b1ee0c 1136 printf("\t\tGPF DVSEC for CXL Ports\n");
5c75f737 1137 dvsec_cxl_gpf_port(d, where);
fe0df5d3
BW		 1138 break;
1139 case 5:
23b1ee0c 1140 printf("\t\tGPF DVSEC for CXL Devices\n");
d462e89c 1141 dvsec_cxl_gpf_device(d, where);
fe0df5d3
BW		 1142 break;
1143 case 7:
23b1ee0c
AG		 1144 printf("\t\tPCIe DVSEC for Flex Bus Port\n");
1145 dvsec_cxl_flex_bus(d, where, rev, len);
fe0df5d3 1146 break;
2849db67 1147 case 8:
23b1ee0c 1148 printf("\t\tRegister Locator DVSEC\n");
2849db67
MM		 1149 dvsec_cxl_register_locator(d, where, len);
1150 break;
fe0df5d3 1151 case 9:
23b1ee0c 1152 printf("\t\tMLD DVSEC\n");
45824262 1153 dvsec_cxl_mld(d, where);
fe0df5d3 1154 break;
23b1ee0c
AG		 1155 case 0xa:
1156 printf("\t\tPCIe DVSEC for Test Capability <?>\n");
1157 break;
c8b83c6c 1158 default:
2849db67
MM		 1159 printf("\t\tUnknown ID %04x\n", id);
1160 }
0d4491cb
BW		 1161}
1162
5f1d1265
SK		 1163static void
1164cap_dvsec(struct device *d, int where)
1165{
71aeac63 1166 printf("Designated Vendor-Specific: ");
5f1d1265
SK		 1167 if (!config_fetch(d, where + PCI_DVSEC_HEADER1, 8))
1168 {
1169 printf("<unreadable>\n");
1170 return;
1171 }
1172
71aeac63
MM		 1173 u32 hdr = get_conf_long(d, where + PCI_DVSEC_HEADER1);
1174 u16 vendor = BITS(hdr, 0, 16);
1175 byte rev = BITS(hdr, 16, 4);
1176 u16 len = BITS(hdr, 20, 12);
5f1d1265 1177
71aeac63
MM		 1178 u16 id = get_conf_long(d, where + PCI_DVSEC_HEADER2);
1179
1180 printf("Vendor=%04x ID=%04x Rev=%d Len=%d", vendor, id, rev, len);
6c138204 1181 if (vendor == PCI_DVSEC_VENDOR_ID_CXL && len >= 16)
2849db67 1182 cap_dvsec_cxl(d, id, rev, where, len);
71aeac63
MM		 1183 else
1184 printf(" <?>\n");
5f1d1265
SK		 1185}
1186
78ca9582
MM		 1187static void
1188cap_evendor(struct device *d, int where)
1189{
1190 u32 hdr;
1191
1192 printf("Vendor Specific Information: ");
1193 if (!config_fetch(d, where + PCI_EVNDR_HEADER, 4))
1194 {
1195 printf("<unreadable>\n");
1196 return;
1197 }
1198
1199 hdr = get_conf_long(d, where + PCI_EVNDR_HEADER);
1200 printf("ID=%04x Rev=%d Len=%03x <?>\n",
1201 BITS(hdr, 0, 16),
1202 BITS(hdr, 16, 4),
1203 BITS(hdr, 20, 12));
1204}
1205
fb17077d 1206static int l1pm_calc_pwron(int scale, int value)
8efbe075
RJ		 1207{
1208 switch (scale)
1209 {
1210 case 0:
1211 return 2 * value;
1212 case 1:
1213 return 10 * value;
1214 case 2:
1215 return 100 * value;
1216 }
1217 return -1;
1218}
1219
214c9a95
DB		 1220static void
1221cap_l1pm(struct device *d, int where)
1222{
8efbe075
RJ		 1223 u32 l1_cap, val, scale;
1224 int time;
214c9a95
DB		 1225
1226 printf("L1 PM Substates\n");
1227
1228 if (verbose < 2)
1229 return;
1230
8efbe075 1231 if (!config_fetch(d, where + PCI_L1PM_SUBSTAT_CAP, 12))
214c9a95
DB		 1232 {
1233 printf("\t\t<unreadable>\n");
1234 return;
1235 }
1236
8efbe075 1237 l1_cap = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CAP);
214c9a95 1238 printf("\t\tL1SubCap: ");
e495466c 1239 printf("PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c L1_PM_Substates%c\n",
8efbe075
RJ		 1240 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L12),
1241 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_PM_L11),
1242 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L12),
1243 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_ASPM_L11),
1244 FLAG(l1_cap, PCI_L1PM_SUBSTAT_CAP_L1PM_SUPP));
1245
fb17077d 1246 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
214c9a95 1247 {
fb17077d 1248 printf("\t\t\t PortCommonModeRestoreTime=%dus ", BITS(l1_cap, 8, 8));
8efbe075
RJ		 1249 time = l1pm_calc_pwron(BITS(l1_cap, 16, 2), BITS(l1_cap, 19, 5));
1250 if (time != -1)
1251 printf("PortTPowerOnTime=%dus\n", time);
1252 else
1253 printf("PortTPowerOnTime=<error>\n");
1254 }
214c9a95 1255
8efbe075 1256 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL1);
fb17077d 1257 printf("\t\tL1SubCtl1: PCI-PM_L1.2%c PCI-PM_L1.1%c ASPM_L1.2%c ASPM_L1.1%c\n",
8efbe075
RJ		 1258 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L12),
1259 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_PM_L11),
1260 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L12),
1261 FLAG(val, PCI_L1PM_SUBSTAT_CTL1_ASPM_L11));
1262
fb17077d 1263 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
8efbe075 1264 {
6469d596
VL		 1265 printf("\t\t\t T_CommonMode=%dus", BITS(val, 8, 8));
1266
1267 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
1268 {
1269 scale = BITS(val, 29, 3);
1270 if (scale > 5)
1271 printf(" LTR1.2_Threshold=<error>");
1272 else
c3d1d465 1273 printf(" LTR1.2_Threshold=%" PCI_U64_FMT_U "ns", BITS(val, 16, 10) * (u64) cap_ltr_scale(scale));
6469d596
VL		 1274 }
1275 printf("\n");
8efbe075
RJ		 1276 }
1277
1278 val = get_conf_long(d, where + PCI_L1PM_SUBSTAT_CTL2);
fb17077d
MM		 1279 printf("\t\tL1SubCtl2:");
1280 if (l1_cap & PCI_L1PM_SUBSTAT_CAP_PM_L12 || l1_cap & PCI_L1PM_SUBSTAT_CAP_ASPM_L12)
8efbe075
RJ		 1281 {
1282 time = l1pm_calc_pwron(BITS(val, 0, 2), BITS(val, 3, 5));
1283 if (time != -1)
fb17077d 1284 printf(" T_PwrOn=%dus", time);
8efbe075 1285 else
fb17077d 1286 printf(" T_PwrOn=<error>");
214c9a95 1287 }
fb17077d 1288 printf("\n");
214c9a95
DB		 1289}
1290
415a9c18
YJ		 1291static void
1292cap_ptm(struct device *d, int where)
1293{
1294 u32 buff;
1295 u16 clock;
1296
1297 printf("Precision Time Measurement\n");
1298
1299 if (verbose < 2)
1300 return;
1301
1302 if (!config_fetch(d, where + 4, 8))
1303 {
1304 printf("\t\t<unreadable>\n");
1305 return;
1306 }
1307
1308 buff = get_conf_long(d, where + 4);
1309 printf("\t\tPTMCap: ");
b2caca01 1310 printf("Requester%c Responder%c Root%c\n",
415a9c18
YJ		 1311 FLAG(buff, 0x1),
1312 FLAG(buff, 0x2),
1313 FLAG(buff, 0x4));
1314
1315 clock = BITS(buff, 8, 8);
1316 printf("\t\tPTMClockGranularity: ");
1317 switch (clock)
1318 {
1319 case 0x00:
1320 printf("Unimplemented\n");
1321 break;
1322 case 0xff:
1323 printf("Greater than 254ns\n");
1324 break;
1325 default:
1326 printf("%huns\n", clock);
1327 }
1328
1329 buff = get_conf_long(d, where + 8);
1330 printf("\t\tPTMControl: ");
b2caca01 1331 printf("Enabled%c RootSelected%c\n",
415a9c18
YJ		 1332 FLAG(buff, 0x1),
1333 FLAG(buff, 0x2));
1334
1335 clock = BITS(buff, 8, 8);
1336 printf("\t\tPTMEffectiveGranularity: ");
1337 switch (clock)
1338 {
1339 case 0x00:
1340 printf("Unknown\n");
1341 break;
1342 case 0xff:
1343 printf("Greater than 254ns\n");
1344 break;
1345 default:
1346 printf("%huns\n", clock);
1347 }
1348}
1349
44c6c7fc
MM		 1350static void
1351print_rebar_range_size(int ld2_size)
1352{
1353 // This function prints the input as a power-of-2 size value
1354 // It is biased with 1MB = 0, ...
1355 // Maximum resizable BAR value supported is 2^63 bytes = 43
1356 // for the extended resizable BAR capability definition
1357 // (otherwise it would stop at 2^28)
1358
1359 if (ld2_size >= 0 && ld2_size < 10)
1360 printf(" %dMB", (1 << ld2_size));
1361 else if (ld2_size >= 10 && ld2_size < 20)
1362 printf(" %dGB", (1 << (ld2_size-10)));
1363 else if (ld2_size >= 20 && ld2_size < 30)
1364 printf(" %dTB", (1 << (ld2_size-20)));
1365 else if (ld2_size >= 30 && ld2_size < 40)
1366 printf(" %dPB", (1 << (ld2_size-30)));
1367 else if (ld2_size >= 40 && ld2_size < 44)
1368 printf(" %dEB", (1 << (ld2_size-40)));
1369 else
1370 printf(" <unknown>");
1371}
1372
1373static void
1374cap_rebar(struct device *d, int where, int virtual)
1375{
1376 u32 sizes_buffer, control_buffer, ext_sizes, current_size;
d10c2aa1
MM		 1377 u16 bar_index, barcount, i;
1378 // If the structure exists, at least one bar is defined
44c6c7fc
MM		 1379 u16 num_bars = 1;
1380
1381 printf("%s Resizable BAR\n", (virtual) ? "Virtual" : "Physical");
1382
d10c2aa1 1383 if (verbose < 2)
44c6c7fc
MM		 1384 return;
1385
1386 // Go through all defined BAR definitions of the caps, at minimum 1
1387 // (loop also terminates if num_bars read from caps is > 6)
1388 for (barcount = 0; barcount < num_bars; barcount++)
1389 {
1390 where += 4;
1391
1392 // Get the next BAR configuration
1393 if (!config_fetch(d, where, 8))
1394 {
1395 printf("\t\t<unreadable>\n");
1396 return;
1397 }
1398
1399 sizes_buffer = get_conf_long(d, where) >> 4;
44c6c7fc 1400 where += 4;
44c6c7fc
MM		 1401 control_buffer = get_conf_long(d, where);
1402
d10c2aa1
MM		 1403 bar_index = BITS(control_buffer, 0, 3);
1404 current_size = BITS(control_buffer, 8, 6);
1405 ext_sizes = BITS(control_buffer, 16, 16);
44c6c7fc
MM		 1406
1407 if (barcount == 0)
1408 {
1409 // Only index 0 controlreg has the num_bar count definition
d10c2aa1
MM		 1410 num_bars = BITS(control_buffer, 5, 3);
1411 if (num_bars < 1 || num_bars > 6)
1412 {
1413 printf("\t\t<error in resizable BAR: num_bars=%d is out of specification>\n", num_bars);
1414 break;
1415 }
44c6c7fc
MM		 1416 }
1417
1418 // Resizable BAR list entry have an arbitrary index and current size
d10c2aa1 1419 printf("\t\tBAR %d: current size:", bar_index);
44c6c7fc
MM		 1420 print_rebar_range_size(current_size);
1421
d10c2aa1
MM		 1422 if (sizes_buffer || ext_sizes)
1423 {
1424 printf(", supported:");
44c6c7fc 1425
d10c2aa1
MM		 1426 for (i=0; i<28; i++)
1427 if (sizes_buffer & (1U << i))
1428 print_rebar_range_size(i);
44c6c7fc 1429
d10c2aa1
MM		 1430 for (i=0; i<16; i++)
1431 if (ext_sizes & (1U << i))
1432 print_rebar_range_size(i + 28);
1433 }
44c6c7fc 1434
44c6c7fc
MM		 1435 printf("\n");
1436 }
1437}
1438
60be9345
JC		 1439static void
1440cap_doe(struct device *d, int where)
1441{
1442 u32 l;
1443
1444 printf("Data Object Exchange\n");
1445
1446 if (verbose < 2)
1447 return;
1448
1449 if (!config_fetch(d, where + PCI_DOE_CAP, 0x14))
1450 {
1451 printf("\t\t<unreadable>\n");
1452 return;
1453 }
1454
1455 l = get_conf_long(d, where + PCI_DOE_CAP);
1456 printf("\t\tDOECap: IntSup%c\n",
1457 FLAG(l, PCI_DOE_CAP_INT_SUPP));
1458 if (l & PCI_DOE_CAP_INT_SUPP)
aeb74fe2 1459 printf("\t\t\tIntMsgNum %d\n",
60be9345
JC		 1460 PCI_DOE_CAP_INT_MSG(l));
1461
1462 l = get_conf_long(d, where + PCI_DOE_CTL);
1463 printf("\t\tDOECtl: IntEn%c\n",
1464 FLAG(l, PCI_DOE_CTL_INT));
1465
1466 l = get_conf_long(d, where + PCI_DOE_STS);
1467 printf("\t\tDOESta: Busy%c IntSta%c Error%c ObjectReady%c\n",
1468 FLAG(l, PCI_DOE_STS_BUSY),
1469 FLAG(l, PCI_DOE_STS_INT),
1470 FLAG(l, PCI_DOE_STS_ERROR),
1471 FLAG(l, PCI_DOE_STS_OBJECT_READY));
1472}
1473
c7a34993 1474void
a1492b88 1475show_ext_caps(struct device *d, int type)
c7a34993
MM		 1476{
1477 int where = 0x100;
1478 char been_there[0x1000];
1479 memset(been_there, 0, 0x1000);
1480 do
1481 {
1482 u32 header;
33088c24 1483 int id, version;
c7a34993
MM		 1484
1485 if (!config_fetch(d, where, 4))
1486 break;
1487 header = get_conf_long(d, where);
861063f3 1488 if (!header || header == 0xffffffff)
c7a34993
MM		 1489 break;
1490 id = header & 0xffff;
33088c24
MM		 1491 version = (header >> 16) & 0xf;
1492 printf("\tCapabilities: [%03x", where);
1493 if (verbose > 1)
1494 printf(" v%d", version);
1495 printf("] ");
c7a34993
MM		 1496 if (been_there[where]++)
1497 {
1498 printf("<chain looped>\n");
1499 break;
1500 }
1501 switch (id)
1502 {
c508d1c9
BH		 1503 case PCI_EXT_CAP_ID_NULL:
1504 printf("Null\n");
1505 break;
c7a34993 1506 case PCI_EXT_CAP_ID_AER:
a1492b88 1507 cap_aer(d, where, type);
c7a34993 1508 break;
de91b6f2
KB		 1509 case PCI_EXT_CAP_ID_DPC:
1510 cap_dpc(d, where);
1511 break;
c7a34993 1512 case PCI_EXT_CAP_ID_VC:
33088c24
MM		 1513 case PCI_EXT_CAP_ID_VC2:
1514 cap_vc(d, where);
c7a34993
MM		 1515 break;
1516 case PCI_EXT_CAP_ID_DSN:
1517 cap_dsn(d, where);
1518 break;
1519 case PCI_EXT_CAP_ID_PB:
1520 printf("Power Budgeting <?>\n");
1521 break;
1522 case PCI_EXT_CAP_ID_RCLINK:
5a9a932c 1523 cap_rclink(d, where);
c7a34993
MM		 1524 break;
1525 case PCI_EXT_CAP_ID_RCILINK:
1526 printf("Root Complex Internal Link <?>\n");
1527 break;
e12bd01e
SK		 1528 case PCI_EXT_CAP_ID_RCEC:
1529 cap_rcec(d, where);
c7a34993
MM		 1530 break;
1531 case PCI_EXT_CAP_ID_MFVC:
1532 printf("Multi-Function Virtual Channel <?>\n");
1533 break;
eff08b33
BH		 1534 case PCI_EXT_CAP_ID_RCRB:
1535 printf("Root Complex Register Block <?>\n");
c7a34993
MM		 1536 break;
1537 case PCI_EXT_CAP_ID_VNDR:
78ca9582 1538 cap_evendor(d, where);
c7a34993
MM		 1539 break;
1540 case PCI_EXT_CAP_ID_ACS:
1541 cap_acs(d, where);
1542 break;
1543 case PCI_EXT_CAP_ID_ARI:
1544 cap_ari(d, where);
1545 break;
1546 case PCI_EXT_CAP_ID_ATS:
1547 cap_ats(d, where);
1548 break;
1549 case PCI_EXT_CAP_ID_SRIOV:
1550 cap_sriov(d, where);
1551 break;
b8f7cd64
BH		 1552 case PCI_EXT_CAP_ID_MRIOV:
1553 printf("Multi-Root I/O Virtualization <?>\n");
1554 break;
c0d9545c
BH		 1555 case PCI_EXT_CAP_ID_MCAST:
1556 cap_multicast(d, where, type);
1557 break;
a858df0d
DW		 1558 case PCI_EXT_CAP_ID_PRI:
1559 cap_pri(d, where);
1560 break;
b8f7cd64 1561 case PCI_EXT_CAP_ID_REBAR:
44c6c7fc 1562 cap_rebar(d, where, 0);
b8f7cd64
BH		 1563 break;
1564 case PCI_EXT_CAP_ID_DPA:
1565 printf("Dynamic Power Allocation <?>\n");
1566 break;
67da1792
MM		 1567 case PCI_EXT_CAP_ID_TPH:
1568 cap_tph(d, where);
1569 break;
1570 case PCI_EXT_CAP_ID_LTR:
1571 cap_ltr(d, where);
1572 break;
b8f7cd64 1573 case PCI_EXT_CAP_ID_SECPCI:
9225e71d 1574 cap_sec(d, where);
b8f7cd64
BH		 1575 break;
1576 case PCI_EXT_CAP_ID_PMUX:
1577 printf("Protocol Multiplexing <?>\n");
1578 break;
a858df0d
DW		 1579 case PCI_EXT_CAP_ID_PASID:
1580 cap_pasid(d, where);
1581 break;
b8f7cd64
BH		 1582 case PCI_EXT_CAP_ID_LNR:
1583 printf("LN Requester <?>\n");
1584 break;
214c9a95
DB		 1585 case PCI_EXT_CAP_ID_L1PM:
1586 cap_l1pm(d, where);
1587 break;
415a9c18
YJ		 1588 case PCI_EXT_CAP_ID_PTM:
1589 cap_ptm(d, where);
1590 break;
b8f7cd64
BH		 1591 case PCI_EXT_CAP_ID_M_PCIE:
1592 printf("PCI Express over M_PHY <?>\n");
1593 break;
1594 case PCI_EXT_CAP_ID_FRS:
1595 printf("FRS Queueing <?>\n");
1596 break;
1597 case PCI_EXT_CAP_ID_RTR:
1598 printf("Readiness Time Reporting <?>\n");
1599 break;
1600 case PCI_EXT_CAP_ID_DVSEC:
71aeac63 1601 cap_dvsec(d, where);
b8f7cd64
BH		 1602 break;
1603 case PCI_EXT_CAP_ID_VF_REBAR:
44c6c7fc 1604 cap_rebar(d, where, 1);
b8f7cd64
BH		 1605 break;
1606 case PCI_EXT_CAP_ID_DLNK:
1607 printf("Data Link Feature <?>\n");
1608 break;
1609 case PCI_EXT_CAP_ID_16GT:
1610 printf("Physical Layer 16.0 GT/s <?>\n");
1611 break;
1612 case PCI_EXT_CAP_ID_LMR:
1613 printf("Lane Margining at the Receiver <?>\n");
1614 break;
1615 case PCI_EXT_CAP_ID_HIER_ID:
1616 printf("Hierarchy ID <?>\n");
1617 break;
1618 case PCI_EXT_CAP_ID_NPEM:
1619 printf("Native PCIe Enclosure Management <?>\n");
1620 break;
db43fb5e
MN		 1621 case PCI_EXT_CAP_ID_32GT:
1622 printf("Physical Layer 32.0 GT/s <?>\n");
1623 break;
60be9345
JC		 1624 case PCI_EXT_CAP_ID_DOE:
1625 cap_doe(d, where);
1626 break;
c7a34993 1627 default:
60a45a7e 1628 printf("Extended Capability ID %#02x\n", id);
c7a34993
MM		 1629 break;
1630 }
d61c4772 1631 where = (header >> 20) & ~3;
c7a34993
MM		 1632 } while (where);
1633}
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