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Explicitly specify common tdesc.h for use with aarch64.h
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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12018-02-27 H.J. Lu <hongjiu.lu@intel.com>
2
3 PR gas/22871
4 * i386-gen.c (opcode_modifiers): Add Optimize.
5 * i386-opc.h (Optimize): New enum.
6 (i386_opcode_modifier): Add optimize.
7 * i386-opc.tbl: Add "Optimize" to "mov $imm, reg",
8 "sub reg, reg/mem", "test $imm, acc", "test $imm, reg/mem",
9 "and $imm, acc", "and $imm, reg/mem", "xor reg, reg/mem",
10 "movq $imm, reg" and AVX256 and AVX512 versions of vandnps,
11 vandnpd, vpandn, vpandnd, vpandnq, vxorps, vxorpd, vpxor,
12 vpxord and vpxorq.
13 * i386-tbl.h: Regenerated.
14
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152018-02-26 Alan Modra <amodra@gmail.com>
16
17 * crx-dis.c (getregliststring): Allocate a large enough buffer
18 to silence false positive gcc8 warning.
19
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202018-02-22 Shea Levy <shea@shealevy.com>
21
22 * disassemble.c (ARCH_riscv): Define if ARCH_all.
23
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242018-02-22 H.J. Lu <hongjiu.lu@intel.com>
25
26 * i386-opc.tbl: Add {rex},
27 * i386-tbl.h: Regenerated.
28
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292018-02-20 Maciej W. Rozycki <macro@mips.com>
30
31 * mips16-opc.c (decode_mips16_operand) <'M'>: Remove case.
32 (mips16_opcodes): Replace `M' with `m' for "restore".
33
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342018-02-19 Thomas Preud'homme <thomas.preudhomme@arm.com>
35
36 * arm-dis.c (thumb_opcodes): Fix BXNS mask.
37
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382018-02-13 Maciej W. Rozycki <macro@mips.com>
39
40 * wasm32-dis.c (print_insn_wasm32): Rename `index' local
41 variable to `function_index'.
42
68d20676
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432018-02-13 Nick Clifton <nickc@redhat.com>
44
45 PR 22823
46 * metag-dis.c (print_fmmov): Double buffer size to avoid warning
47 about truncation of printing.
48
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492018-02-12 Henry Wong <henry@stuffedcow.net>
50
51 * mips-opc.c (mips_builtin_opcodes): Correct "sigrie" encoding.
52
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532018-02-05 Nick Clifton <nickc@redhat.com>
54
55 * po/pt_BR.po: Updated Brazilian Portuguese translation.
56
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572018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
58
59 * i386-dis.c (enum): Add pconfig.
60 * i386-gen.c (cpu_flag_init): Add CPU_PCONFIG_FLAGS.
61 (cpu_flags): Add CpuPCONFIG.
62 * i386-opc.h (enum): Add CpuPCONFIG.
63 (i386_cpu_flags): Add cpupconfig.
64 * i386-opc.tbl: Add PCONFIG instruction.
65 * i386-init.h: Regenerate.
66 * i386-tbl.h: Likewise.
67
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682018-01-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
69
70 * i386-dis.c (enum): Add PREFIX_0F09.
71 * i386-gen.c (cpu_flag_init): Add CPU_WBNOINVD_FLAGS.
72 (cpu_flags): Add CpuWBNOINVD.
73 * i386-opc.h (enum): Add CpuWBNOINVD.
74 (i386_cpu_flags): Add cpuwbnoinvd.
75 * i386-opc.tbl: Add WBNOINVD instruction.
76 * i386-init.h: Regenerate.
77 * i386-tbl.h: Likewise.
78
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792018-01-17 Jim Wilson <jimw@sifive.com>
80
81 * riscv-opc.c (riscv_opcodes) <addi>: Use z instead of 0.
82
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832018-01-17 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
84
85 * i386-gen.c (cpu_flag_init): Delete CPU_CET_FLAGS, CpuCET.
86 Add CPU_IBT_FLAGS, CPU_SHSTK_FLAGS, CPY_ANY_IBT_FLAGS,
87 CPU_ANY_SHSTK_FLAGS, CpuIBT, CpuSHSTK.
88 (cpu_flags): Add CpuIBT, CpuSHSTK.
89 * i386-opc.h (enum): Add CpuIBT, CpuSHSTK.
90 (i386_cpu_flags): Add cpuibt, cpushstk.
91 * i386-opc.tbl: Change CpuCET to CpuSHSTK and CpuIBT.
92 * i386-init.h: Regenerate.
93 * i386-tbl.h: Likewise.
94
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952018-01-16 Nick Clifton <nickc@redhat.com>
96
97 * po/pt_BR.po: Updated Brazilian Portugese translation.
98 * po/de.po: Updated German translation.
99
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1002018-01-15 Jim Wilson <jimw@sifive.com>
101
102 * riscv-opc.c (match_c_nop): New.
103 (riscv_opcodes) <addi>: Handle an addi that compresses to c.nop.
104
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1052018-01-15 Nick Clifton <nickc@redhat.com>
106
107 * po/uk.po: Updated Ukranian translation.
108
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1092018-01-13 Nick Clifton <nickc@redhat.com>
110
111 * po/opcodes.pot: Regenerated.
112
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1132018-01-13 Nick Clifton <nickc@redhat.com>
114
115 * configure: Regenerate.
116
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1172018-01-13 Nick Clifton <nickc@redhat.com>
118
119 2.30 branch created.
120
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1212018-01-11 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
122
123 * i386-opc.tbl: Remove VL variants for 4FMAPS and 4VNNIW insns.
124 * i386-tbl.h: Regenerate.
125
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1262018-01-10 Jan Beulich <jbeulich@suse.com>
127
128 * i386-opc.tbl (v4fmaddss, v4fnmaddss): Adjust Disp8MemShift.
129 * i386-tbl.h: Re-generate.
130
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1312018-01-10 Jan Beulich <jbeulich@suse.com>
132
133 * i386-opc.tbl (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb,
134 vpcmpnleb, vpcmpnltb, vpcmpequb, vpcmpleub, vpcmpltub,
135 vpcmpnequb, vpcmpnleub, vpcmpnltub, vpcmpeqw, vpcmplew,
136 vpcmpltw, vpcmpneqw, vpcmpnlew, vpcmpnltw, vpcmpequw, vpcmpleuw,
137 vpcmpltuw, vpcmpnequw, vpcmpnleuw, vpcmpnltuw): Adjust
138 Disp8MemShift of AVX512VL forms.
139 * i386-tbl.h: Re-generate.
140
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1412018-01-09 Jim Wilson <jimw@sifive.com>
142
143 * riscv-dis.c (maybe_print_address): If base_reg is zero,
144 then the hi_addr value is zero.
145
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1462018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
147
148 * arm-dis.c (arm_opcodes): Add csdb.
149 (thumb32_opcodes): Add csdb.
150
be2e7d95
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1512018-01-09 James Greenhalgh <james.greenhalgh@arm.com>
152
153 * aarch64-tbl.h (aarch64_opcode_table): Add "csdb".
154 * aarch64-asm-2.c: Regenerate.
155 * aarch64-dis-2.c: Regenerate.
156 * aarch64-opc-2.c: Regenerate.
157
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1582018-01-08 H.J. Lu <hongjiu.lu@intel.com>
159
160 PR gas/22681
161 * i386-opc.tbl: Properly encode vmovd with Qword memeory operand.
162 Remove AVX512 vmovd with 64-bit operands.
163 * i386-tbl.h: Regenerated.
164
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1652018-01-05 Jim Wilson <jimw@sifive.com>
166
167 * riscv-dis.c (print_insn_args) <'s'>: Call maybe_print_address for a
168 jalr.
169
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1702018-01-03 Alan Modra <amodra@gmail.com>
171
172 Update year range in copyright notice of all files.
173
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1742018-01-02 Jan Beulich <jbeulich@suse.com>
175
176 * i386-gen.c (operand_type_init): Restore OPERAND_TYPE_REGYMM
177 and OPERAND_TYPE_REGZMM entries.
178
1e563868 179For older changes see ChangeLog-2017
3499769a 180\f
1e563868 181Copyright (C) 2018 Free Software Foundation, Inc.
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182
183Copying and distribution of this file, with or without modification,
184are permitted in any medium without royalty provided the copyright
185notice and this notice are preserved.
186
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188mode: change-log
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