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Commit | Line | Data |
---|---|---|
9ed608f9 MW |
1 | 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> |
2 | ||
3 | * aarch64-asm.c (aarch64_ins_hint): New. | |
4 | * aarch64-asm.h (aarch64_ins_hint): Declare. | |
5 | * aarch64-dis.c (aarch64_ext_hint): New. | |
6 | * aarch64-dis.h (aarch64_ext_hint): Declare. | |
7 | * aarch64-opc-2.c: Regenerate. | |
8 | * aarch64-opc.c (aarch64_hint_options): New. | |
9 | * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos. | |
10 | ||
a0f7013a MW |
11 | 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> |
12 | ||
13 | * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16. | |
14 | ||
55c144e6 MW |
15 | 2015-12-11 Matthew Wahab <matthew.wahab@arm.com> |
16 | ||
17 | * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1, | |
18 | pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1, | |
19 | pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and | |
20 | pmscr_el2. | |
21 | (aarch64_sys_reg_supported_p): Add architecture feature tests for | |
22 | the new registers. | |
23 | ||
22a5455c MW |
24 | 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> |
25 | ||
26 | * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp". | |
27 | (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register | |
28 | feature test for "s1e1rp" and "s1e1wp". | |
29 | ||
d6bf7ce6 MW |
30 | 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> |
31 | ||
32 | * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap". | |
33 | (aarch64_sys_ins_reg_supported_p): New. | |
34 | ||
ea2deeec MW |
35 | 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> |
36 | ||
37 | * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt | |
38 | with aarch64_sys_ins_reg_has_xt. | |
39 | (aarch64_ext_sysins_op): Likewise. | |
40 | * aarch64-opc.c (operand_general_constraint_met_p): Likewise. | |
41 | (F_HASXT): New. | |
42 | (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg. | |
43 | (aarch64_sys_regs_dc): Likewise. | |
44 | (aarch64_sys_regs_at): Likewise. | |
45 | (aarch64_sys_regs_tlbi): Likewise. | |
46 | (aarch64_sys_ins_reg_has_xt): New. | |
47 | ||
6479e48e MW |
48 | 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> |
49 | ||
50 | * aarch64-opc.c (aarch64_sys_regs): Add "uao". | |
51 | (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao". | |
52 | (aarch64_pstatefields): Add "uao". | |
53 | (aarch64_pstatefield_supported_p): Add checks for "uao". | |
54 | ||
47f81142 MW |
55 | 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> |
56 | ||
57 | * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1", | |
58 | "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1", | |
59 | "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2". | |
60 | (aarch64_sys_reg_supported_p): Add architecture feature tests for | |
61 | new registers. | |
62 | ||
c8a6db6f MW |
63 | 2015-12-10 Matthew Wahab <matthew.wahab@arm.com> |
64 | ||
65 | * aarch64-asm-2.c: Regenerate. | |
66 | * aarch64-dis-2.c: Regenerate. | |
67 | * aarch64-tbl.h (aarch64_feature_ras): New. | |
68 | (RAS): New. | |
69 | (aarch64_opcode_table): Add "esb". | |
70 | ||
8eab4136 L |
71 | 2015-12-09 H.J. Lu <hongjiu.lu@intel.com> |
72 | ||
73 | * i386-dis.c (MOD_0F01_REG_5): New. | |
74 | (RM_0F01_REG_5): Likewise. | |
75 | (reg_table): Use MOD_0F01_REG_5. | |
76 | (mod_table): Add MOD_0F01_REG_5. | |
77 | (rm_table): Add RM_0F01_REG_5. | |
78 | * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS. | |
79 | (cpu_flags): Add CpuOSPKE. | |
80 | * i386-opc.h (CpuOSPKE): New. | |
81 | (i386_cpu_flags): Add cpuospke. | |
82 | * i386-opc.tbl: Add rdpkru and wrpkru instructions. | |
83 | * i386-init.h: Regenerated. | |
84 | * i386-tbl.h: Likewise. | |
85 | ||
1eac08cc DD |
86 | 2015-12-07 DJ Delorie <dj@redhat.com> |
87 | ||
88 | * rl78-decode.opc: Enable MULU for all ISAs. | |
89 | * rl78-decode.c: Regenerate. | |
90 | ||
dd2887fc AM |
91 | 2015-12-07 Alan Modra <amodra@gmail.com> |
92 | ||
93 | * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by | |
94 | major opcode/xop. | |
95 | ||
24b368f8 CZ |
96 | 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com> |
97 | ||
98 | * arc-dis.c (special_flag_p): Match full mnemonic. | |
99 | * arc-opc.c (print_insn_arc): Check section size to read | |
100 | appropriate number of bytes. Fix printing. | |
101 | * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without | |
102 | arguments. | |
103 | ||
3395762e AV |
104 | 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> |
105 | ||
106 | * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo... | |
107 | <ldah>: ... to this. | |
108 | ||
622b9eb1 MW |
109 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
110 | ||
111 | * aarch64-asm-2.c: Regenerate. | |
112 | * aarch64-dis-2.c: Regenerate. | |
113 | * aarch64-opc-2.c: Regenerate. | |
114 | * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. | |
115 | (QL_INT2FP_H, QL_FP2INT_H): New. | |
116 | (QL_FP2_H, QL_FP3_H, QL_FP4_H): New | |
117 | (QL_DST_H): New. | |
118 | (QL_FCCMP_H): New. | |
119 | (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, | |
120 | fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, | |
121 | fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, | |
122 | fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, | |
123 | frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, | |
124 | fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and | |
125 | fcsel. | |
126 | ||
cf86120b MW |
127 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
128 | ||
129 | * aarch64-opc.c (half_conv_t): New. | |
130 | (expand_fp_imm): Replace is_dp flag with the parameter size to | |
131 | specify the number of bytes for the required expansion. Treat | |
132 | a 16-bit expansion like a 32-bit expansion. Add check for an | |
133 | unsupported size request. Update comment. | |
134 | (aarch64_print_operand): Update to support 16-bit floating point | |
135 | values. Update for changes to expand_fp_imm. | |
136 | ||
3bd894a7 MW |
137 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
138 | ||
139 | * aarch64-tbl.h (aarch64_feature_fp_f16): New. | |
140 | (FP_F16): New. | |
141 | ||
64357d2e MW |
142 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
143 | ||
144 | * aarch64-asm-2.c: Regenerate. | |
145 | * aarch64-dis-2.c: Regenerate. | |
146 | * aarch64-opc-2.c: Regenerate. | |
147 | * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add | |
148 | "rev64". | |
149 | ||
d685192a MW |
150 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
151 | ||
152 | * aarch64-asm-2.c: Regenerate. | |
153 | * aarch64-asm.c (convert_bfc_to_bfm): New. | |
154 | (convert_to_real): Add case for OP_BFC. | |
155 | * aarch64-dis-2.c: Regenerate. | |
156 | * aarch64-dis.c: (convert_bfm_to_bfc): New. | |
157 | (convert_to_alias): Add case for OP_BFC. | |
158 | * aarch64-opc-2.c: Regenerate. | |
159 | * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert | |
160 | to allow width operand in three-operand instructions. | |
161 | * aarch64-tbl.h (QL_BF1): New. | |
162 | (aarch64_feature_v8_2): New. | |
163 | (ARMV8_2): New. | |
164 | (aarch64_opcode_table): Add "bfc". | |
165 | ||
35822b38 MW |
166 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
167 | ||
168 | * aarch64-asm-2.c: Regenerate. | |
169 | * aarch64-dis-2.c: Regenerate. | |
170 | * aarch64-dis.c: Weaken assert. | |
171 | * aarch64-gen.c: Include the instruction in the list of its | |
172 | possible aliases. | |
173 | ||
1a04d1a7 MW |
174 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
175 | ||
176 | * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1". | |
177 | (aarch64_sys_reg_supported_p): Add ARMv8.2 system register | |
178 | feature test. | |
179 | ||
e49d43ff TG |
180 | 2015-11-23 Tristan Gingold <gingold@adacore.com> |
181 | ||
182 | * arm-dis.c (print_insn): Also set is_thumb for Mach-O. | |
183 | ||
250aafa4 MW |
184 | 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> |
185 | ||
186 | * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, | |
187 | sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, | |
188 | tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, | |
189 | amair_el12, vbar_el12, contextidr_el2, contextidr_el12, | |
190 | cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, | |
191 | cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, | |
192 | cnthv_ctl_el2, cnthv_cval_el2. | |
193 | (aarch64_sys_reg_supported_p): Update for the new system | |
194 | registers. | |
195 | ||
a915c10f NC |
196 | 2015-11-20 Nick Clifton <nickc@redhat.com> |
197 | ||
198 | PR binutils/19224 | |
199 | * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause. | |
200 | ||
f8c2a965 NC |
201 | 2015-11-20 Nick Clifton <nickc@redhat.com> |
202 | ||
203 | * po/zh_CN.po: Updated simplified Chinese translation. | |
204 | ||
c2825638 MW |
205 | 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> |
206 | ||
207 | * aarch64-opc.c (operand_general_constraint_met_p): Check validity | |
208 | of MSR PAN immediate operand. | |
209 | ||
e7286c56 NC |
210 | 2015-11-16 Nick Clifton <nickc@redhat.com> |
211 | ||
212 | * rx-dis.c (condition_names): Replace always and never with | |
213 | invalid, since the always/never conditions can never be legal. | |
214 | ||
d8bd95ef TG |
215 | 2015-11-13 Tristan Gingold <gingold@adacore.com> |
216 | ||
217 | * configure: Regenerate. | |
218 | ||
a680de9a PB |
219 | 2015-11-11 Alan Modra <amodra@gmail.com> |
220 | Peter Bergner <bergner@vnet.ibm.com> | |
221 | ||
222 | * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. | |
223 | Add PPC_OPCODE_VSX3 to the vsx entry. | |
224 | (powerpc_init_dialect): Set default dialect to power9. | |
225 | * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, | |
226 | insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, | |
227 | extract_l1 insert_xtq6, extract_xtq6): New static functions. | |
228 | (insert_esync): Test for illegal L operand value. | |
229 | (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, | |
230 | XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, | |
231 | XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, | |
232 | XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, | |
233 | PPCVSX3): New defines. | |
234 | (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, | |
235 | fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. | |
236 | <mcrxr>: Use XBFRARB_MASK. | |
237 | <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., | |
238 | bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., | |
239 | cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, | |
240 | cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, | |
241 | lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, | |
242 | lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, | |
243 | modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, | |
244 | rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, | |
245 | stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, | |
246 | subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, | |
247 | vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., | |
248 | vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, | |
249 | vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, | |
250 | vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, | |
251 | vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, | |
252 | vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, | |
253 | vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, | |
254 | xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, | |
255 | xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, | |
256 | xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, | |
257 | xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, | |
258 | xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, | |
259 | xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, | |
260 | xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, | |
261 | xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, | |
262 | xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, | |
263 | xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, | |
264 | xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, | |
265 | xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, | |
266 | xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. | |
267 | <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. | |
268 | <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. | |
269 | ||
854eb72b NC |
270 | 2015-11-02 Nick Clifton <nickc@redhat.com> |
271 | ||
272 | * rx-decode.opc (rx_decode_opcode): Decode extra NOP | |
273 | instructions. | |
274 | * rx-decode.c: Regenerate. | |
275 | ||
e292aa7a NC |
276 | 2015-11-02 Nick Clifton <nickc@redhat.com> |
277 | ||
278 | * rx-decode.opc (rx_disp): If the displacement is zero, set the | |
279 | type to RX_Operand_Zero_Indirect. | |
280 | * rx-decode.c: Regenerate. | |
281 | * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. | |
282 | ||
43cdf5ae YQ |
283 | 2015-10-28 Yao Qi <yao.qi@linaro.org> |
284 | ||
285 | * aarch64-dis.c (aarch64_decode_insn): Add one argument | |
286 | noaliases_p. Update comments. Pass noaliases_p rather than | |
287 | no_aliases to aarch64_opcode_decode. | |
288 | (print_insn_aarch64_word): Pass no_aliases to | |
289 | aarch64_decode_insn. | |
290 | ||
c2f28758 VK |
291 | 2015-10-27 Vinay <Vinay.G@kpit.com> |
292 | ||
293 | PR binutils/19159 | |
294 | * rl78-decode.opc (MOV): Added offset to DE register in index | |
295 | addressing mode. | |
296 | * rl78-decode.c: Regenerate. | |
297 | ||
46662804 VK |
298 | 2015-10-27 Vinay Kumar <vinay.g@kpit.com> |
299 | ||
300 | PR binutils/19158 | |
301 | * rl78-decode.opc: Add 's' print operator to instructions that | |
302 | access system registers. | |
303 | * rl78-decode.c: Regenerate. | |
304 | * rl78-dis.c (print_insn_rl78_common): Decode all system | |
305 | registers. | |
306 | ||
02f12cd4 VK |
307 | 2015-10-27 Vinay Kumar <vinay.g@kpit.com> |
308 | ||
309 | PR binutils/19157 | |
310 | * rl78-decode.opc: Add 'a' print operator to mov instructions | |
311 | using stack pointer plus index addressing. | |
312 | * rl78-decode.c: Regenerate. | |
313 | ||
485f23cf AK |
314 | 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
315 | ||
316 | * s390-opc.c: Fix comment. | |
317 | * s390-opc.txt: Change instruction type for troo, trot, trto, and | |
318 | trtt to RRF_U0RER since the second parameter does not need to be a | |
319 | register pair. | |
320 | ||
3f94e60d NC |
321 | 2015-10-08 Nick Clifton <nickc@redhat.com> |
322 | ||
323 | * arc-dis.c (print_insn_arc): Initiallise insn array. | |
324 | ||
875880c6 YQ |
325 | 2015-10-07 Yao Qi <yao.qi@linaro.org> |
326 | ||
327 | * aarch64-dis.c (aarch64_ext_sysins_op): Access field | |
328 | 'name' rather than 'template'. | |
329 | * aarch64-opc.c (aarch64_print_operand): Likewise. | |
330 | ||
886a2506 NC |
331 | 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> |
332 | ||
333 | * arc-dis.c: Revamped file for ARC support | |
334 | * arc-dis.h: Likewise. | |
335 | * arc-ext.c: Likewise. | |
336 | * arc-ext.h: Likewise. | |
337 | * arc-opc.c: Likewise. | |
338 | * arc-fxi.h: New file. | |
339 | * arc-regs.h: Likewise. | |
340 | * arc-tbl.h: Likewise. | |
341 | ||
36f4aab1 YQ |
342 | 2015-10-02 Yao Qi <yao.qi@linaro.org> |
343 | ||
344 | * aarch64-dis.c (disas_aarch64_insn): Remove static. Change | |
345 | argument insn type to aarch64_insn. Rename to ... | |
346 | (aarch64_decode_insn): ... it. | |
347 | (print_insn_aarch64_word): Caller updated. | |
348 | ||
7232d389 YQ |
349 | 2015-10-02 Yao Qi <yao.qi@linaro.org> |
350 | ||
351 | * aarch64-dis.c (disas_aarch64_insn): Remove argument PC. | |
352 | (print_insn_aarch64_word): Caller updated. | |
353 | ||
7ecc513a DV |
354 | 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> |
355 | ||
356 | * s390-mkopc.c (main): Parse htm and vx flag. | |
357 | * s390-opc.txt: Mark instructions from the hardware transactional | |
358 | memory and vector facilities with the "htm"/"vx" flag. | |
359 | ||
b08b78e7 NC |
360 | 2015-09-28 Nick Clifton <nickc@redhat.com> |
361 | ||
362 | * po/de.po: Updated German translation. | |
363 | ||
36f7a941 TR |
364 | 2015-09-28 Tom Rix <tom@bumblecow.com> |
365 | ||
366 | * ppc-opc.c (PPC500): Mark some opcodes as invalid | |
367 | ||
b6518b38 NC |
368 | 2015-09-23 Nick Clifton <nickc@redhat.com> |
369 | ||
370 | * bfin-dis.c (fmtconst): Remove unnecessary call to the abs | |
371 | function. | |
372 | * tic30-dis.c (print_branch): Likewise. | |
373 | * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed | |
374 | value before left shifting. | |
375 | * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. | |
376 | * hppa-dis.c (print_insn_hppa): Likewise. | |
377 | * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static | |
378 | array. | |
379 | * msp430-dis.c (msp430_singleoperand): Likewise. | |
380 | (msp430_doubleoperand): Likewise. | |
381 | (print_insn_msp430): Likewise. | |
382 | * nds32-asm.c (parse_operand): Likewise. | |
383 | * sh-opc.h (MASK): Likewise. | |
384 | * v850-dis.c (get_operand_value): Likewise. | |
385 | ||
f04265ec NC |
386 | 2015-09-22 Nick Clifton <nickc@redhat.com> |
387 | ||
388 | * rx-decode.opc (bwl): Use RX_Bad_Size. | |
389 | (sbwl): Likewise. | |
390 | (ubwl): Likewise. Rename to ubw. | |
391 | (uBWL): Rename to uBW. | |
392 | Replace all references to uBWL with uBW. | |
393 | * rx-decode.c: Regenerate. | |
394 | * rx-dis.c (size_names): Add entry for RX_Bad_Size. | |
395 | (opsize_names): Likewise. | |
396 | (print_insn_rx): Detect and report RX_Bad_Size. | |
397 | ||
6dca4fd1 AB |
398 | 2015-09-22 Anton Blanchard <anton@samba.org> |
399 | ||
400 | * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl. | |
401 | ||
38074311 JM |
402 | 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> |
403 | ||
404 | * sparc-dis.c (print_insn_sparc): Handle the privileged register | |
405 | %pmcdper. | |
406 | ||
5f40e14d JS |
407 | 2015-08-24 Jan Stancek <jstancek@redhat.com> |
408 | ||
409 | * i386-dis.c (print_insn): Fix decoding of three byte operands. | |
410 | ||
ab4e4ed5 AF |
411 | 2015-08-21 Alexander Fomin <alexander.fomin@intel.com> |
412 | ||
413 | PR binutils/18257 | |
414 | * i386-dis.c: Use MOD_TABLE for most of mask instructions. | |
415 | (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, | |
416 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
417 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
418 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
419 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
420 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
421 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
422 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
423 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
424 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
425 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
426 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
427 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
428 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
429 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
430 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
431 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
432 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
433 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
434 | MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, | |
435 | MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, | |
436 | MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, | |
437 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
438 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
439 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
440 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
441 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
442 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
443 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
444 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. | |
445 | (vex_w_table): Replace terminals with MOD_TABLE entries for | |
446 | most of mask instructions. | |
447 | ||
919b75f7 AM |
448 | 2015-08-17 Alan Modra <amodra@gmail.com> |
449 | ||
450 | * cgen.sh: Trim trailing space from cgen output. | |
451 | * ia64-gen.c (print_dependency_table): Don't generate trailing space. | |
452 | (print_dis_table): Likewise. | |
453 | * opc2c.c (dump_lines): Likewise. | |
454 | (orig_filename): Warning fix. | |
455 | * ia64-asmtab.c: Regenerate. | |
456 | ||
4ab90a7a AV |
457 | 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com> |
458 | ||
459 | * arm-dis.c (print_insn_arm): Disassembling for all targets V6 | |
460 | and higher with ARM instruction set will now mark the 26-bit | |
461 | versions of teq,tst,cmn and cmp as UNPREDICTABLE. | |
462 | (arm_opcodes): Fix for unpredictable nop being recognized as a | |
463 | teq. | |
464 | ||
40fc1451 SD |
465 | 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> |
466 | ||
467 | * micromips-opc.c (micromips_opcodes): Re-order table so that move | |
468 | based on 'or' is first. | |
469 | * mips-opc.c (mips_builtin_opcodes): Ditto. | |
470 | ||
922c5db5 NC |
471 | 2015-08-11 Nick Clifton <nickc@redhat.com> |
472 | ||
473 | PR 18800 | |
474 | * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT | |
475 | instruction. | |
476 | ||
75fb7498 RS |
477 | 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> |
478 | ||
479 | * mips-opc.c (mips_builtin_opcodes): Add "sigrie". | |
480 | ||
36aed29d AP |
481 | 2015-08-07 Amit Pawar <Amit.Pawar@amd.com> |
482 | ||
483 | * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. | |
484 | * i386-init.h: Regenerated. | |
485 | ||
a8484f96 L |
486 | 2015-07-30 H.J. Lu <hongjiu.lu@intel.com> |
487 | ||
488 | PR binutils/13571 | |
489 | * i386-dis.c (MOD_0FC3): New. | |
490 | (PREFIX_0FC3): Renamed to ... | |
491 | (PREFIX_MOD_0_0FC3): This. | |
492 | (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. | |
493 | (prefix_table): Replace Ma with Ev on movntiS. | |
494 | (mod_table): Add MOD_0FC3. | |
495 | ||
37a42ee9 L |
496 | 2015-07-27 H.J. Lu <hongjiu.lu@intel.com> |
497 | ||
498 | * configure: Regenerated. | |
499 | ||
070fe95d AM |
500 | 2015-07-23 Alan Modra <amodra@gmail.com> |
501 | ||
502 | PR 18708 | |
503 | * i386-dis.c (get64): Avoid signed integer overflow. | |
504 | ||
20c2a615 L |
505 | 2015-07-22 Alexander Fomin <alexander.fomin@intel.com> |
506 | ||
507 | PR binutils/18631 | |
508 | * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with | |
509 | "EXEvexHalfBcstXmmq" for the second operand. | |
510 | (EVEX_W_0F79_P_2): Likewise. | |
511 | (EVEX_W_0F7A_P_2): Likewise. | |
512 | (EVEX_W_0F7B_P_2): Likewise. | |
513 | ||
6f1c2142 AM |
514 | 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com> |
515 | ||
516 | * arm-dis.c (print_insn_coprocessor): Added support for quarter | |
517 | float bitfield format. | |
518 | (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new | |
519 | quarter float bitfield format. | |
520 | ||
8a643cc3 L |
521 | 2015-07-14 H.J. Lu <hongjiu.lu@intel.com> |
522 | ||
523 | * configure: Regenerated. | |
524 | ||
ef5a96d5 AM |
525 | 2015-07-03 Alan Modra <amodra@gmail.com> |
526 | ||
527 | * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. | |
528 | * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add | |
529 | PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. | |
530 | ||
c8c8175b SL |
531 | 2015-07-01 Sandra Loosemore <sandra@codesourcery.com> |
532 | Cesar Philippidis <cesar@codesourcery.com> | |
533 | ||
534 | * nios2-dis.c (nios2_extract_opcode): New. | |
535 | (nios2_disassembler_state): New. | |
536 | (nios2_find_opcode_hash): Use mach parameter to select correct | |
537 | disassembler state. | |
538 | (nios2_print_insn_arg): Extend to support new R2 argument letters | |
539 | and formats. | |
540 | (print_insn_nios2): Check for 16-bit instruction at end of memory. | |
541 | * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. | |
542 | (NIOS2_NUM_OPCODES): Rename to... | |
543 | (NIOS2_NUM_R1_OPCODES): This. | |
544 | (nios2_r2_opcodes): New. | |
545 | (NIOS2_NUM_R2_OPCODES): New. | |
546 | (nios2_num_r2_opcodes): New. | |
547 | (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. | |
548 | (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. | |
549 | (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. | |
550 | (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. | |
551 | (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. | |
552 | ||
9916071f AP |
553 | 2015-06-30 Amit Pawar <Amit.Pawar@amd.com> |
554 | ||
555 | * i386-dis.c (OP_Mwaitx): New. | |
556 | (rm_table): Add monitorx/mwaitx. | |
557 | * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS | |
558 | and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. | |
559 | (operand_type_init): Add CpuMWAITX. | |
560 | * i386-opc.h (CpuMWAITX): New. | |
561 | (i386_cpu_flags): Add cpumwaitx. | |
562 | * i386-opc.tbl: Add monitorx and mwaitx. | |
563 | * i386-init.h: Regenerated. | |
564 | * i386-tbl.h: Likewise. | |
565 | ||
7b934113 PB |
566 | 2015-06-22 Peter Bergner <bergner@vnet.ibm.com> |
567 | ||
568 | * ppc-opc.c (insert_ls): Test for invalid LS operands. | |
569 | (insert_esync): New function. | |
570 | (LS, WC): Use insert_ls. | |
571 | (ESYNC): Use insert_esync. | |
572 | ||
bdc4de1b NC |
573 | 2015-06-22 Nick Clifton <nickc@redhat.com> |
574 | ||
575 | * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the | |
576 | requested region lies beyond it. | |
577 | * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when | |
578 | looking for 32-bit insns. | |
579 | * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading | |
580 | data. | |
581 | * sh-dis.c (print_insn_sh): Likewise. | |
582 | * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading | |
583 | blocks of instructions. | |
584 | * vax-dis.c (print_insn_vax): Check that the requested address | |
585 | does not clash with the stop_vma. | |
586 | ||
11a0cf2e PB |
587 | 2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
588 | ||
070fe95d | 589 | * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. |
11a0cf2e PB |
590 | * ppc-opc.c (FXM4): Add non-zero optional value. |
591 | (TBR): Likewise. | |
592 | (SXL): Likewise. | |
593 | (insert_fxm): Handle new default operand value. | |
594 | (extract_fxm): Likewise. | |
595 | (insert_tbr): Likewise. | |
596 | (extract_tbr): Likewise. | |
597 | ||
bdfa8b95 MW |
598 | 2015-06-16 Matthew Wahab <matthew.wahab@arm.com> |
599 | ||
600 | * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". | |
601 | ||
24b4cf66 SN |
602 | 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> |
603 | ||
604 | * arm-dis.c (print_insn_coprocessor): Avoid negative shift. | |
605 | ||
99a2c561 PB |
606 | 2015-06-12 Peter Bergner <bergner@vnet.ibm.com> |
607 | ||
608 | * ppc-opc.c: Add comment accidentally removed by old commit. | |
609 | (MTMSRD_L): Delete. | |
610 | ||
40f77f82 AM |
611 | 2015-06-04 Peter Bergner <bergner@vnet.ibm.com> |
612 | ||
613 | * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. | |
614 | ||
13be46a2 NC |
615 | 2015-06-04 Nick Clifton <nickc@redhat.com> |
616 | ||
617 | PR 18474 | |
618 | * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. | |
619 | ||
ddfded2f MW |
620 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
621 | ||
622 | * arm-dis.c (arm_opcodes): Add "setpan". | |
623 | (thumb_opcodes): Add "setpan". | |
624 | ||
1af1dd51 MW |
625 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
626 | ||
627 | * arm-dis.c (select_arm_features): Rework to avoid used of redefined | |
628 | macros. | |
629 | ||
9e1f0fa7 MW |
630 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
631 | ||
632 | * aarch64-tbl.h (aarch64_feature_rdma): New. | |
633 | (RDMA): New. | |
634 | (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. | |
635 | * aarch64-asm-2.c: Regenerate. | |
636 | * aarch64-dis-2.c: Regenerate. | |
637 | * aarch64-opc-2.c: Regenerate. | |
638 | ||
290806fd MW |
639 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
640 | ||
641 | * aarch64-tbl.h (aarch64_feature_lor): New. | |
642 | (LOR): New. | |
643 | (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", | |
644 | "stllrb", "stllrh". | |
645 | * aarch64-asm-2.c: Regenerate. | |
646 | * aarch64-dis-2.c: Regenerate. | |
647 | * aarch64-opc-2.c: Regenerate. | |
648 | ||
f21cce2c MW |
649 | 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> |
650 | ||
651 | * aarch64-opc.c (F_ARCHEXT): New. | |
652 | (aarch64_sys_regs): Add "pan". | |
653 | (aarch64_sys_reg_supported_p): New. | |
654 | (aarch64_pstatefields): Add "pan". | |
655 | (aarch64_pstatefield_supported_p): New. | |
656 | ||
d194d186 JB |
657 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
658 | ||
659 | * i386-tbl.h: Regenerate. | |
660 | ||
3a8547d2 JB |
661 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
662 | ||
663 | * i386-dis.c (print_insn): Swap rounding mode specifier and | |
664 | general purpose register in Intel mode. | |
665 | ||
015c54d5 JB |
666 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
667 | ||
668 | * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. | |
669 | * i386-tbl.h: Regenerate. | |
670 | ||
071f0063 L |
671 | 2015-05-18 H.J. Lu <hongjiu.lu@intel.com> |
672 | ||
673 | * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. | |
674 | * i386-init.h: Regenerated. | |
675 | ||
5db04b09 L |
676 | 2015-05-15 H.J. Lu <hongjiu.lu@intel.com> |
677 | ||
678 | PR binutis/18386 | |
679 | * i386-dis.c: Add comments for '@'. | |
680 | (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. | |
681 | (enum x86_64_isa): New. | |
682 | (isa64): Likewise. | |
683 | (print_i386_disassembler_options): Add amd64 and intel64. | |
684 | (print_insn): Handle amd64 and intel64. | |
685 | (putop): Handle '@'. | |
686 | (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. | |
687 | * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. | |
688 | * i386-opc.h (AMD64): New. | |
689 | (CpuIntel64): Likewise. | |
690 | (i386_cpu_flags): Add cpuamd64 and cpuintel64. | |
691 | * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. | |
692 | Mark direct call/jmp without Disp16|Disp32 as Intel64. | |
693 | * i386-init.h: Regenerated. | |
694 | * i386-tbl.h: Likewise. | |
695 | ||
4bc0608a PB |
696 | 2015-05-14 Peter Bergner <bergner@vnet.ibm.com> |
697 | ||
698 | * ppc-opc.c (IH) New define. | |
699 | (powerpc_opcodes) <wait>: Do not enable for POWER7. | |
700 | <tlbie>: Add RS operand for POWER7. | |
701 | <slbia>: Add IH operand for POWER6. | |
702 | ||
70cead07 L |
703 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
704 | ||
705 | * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit | |
706 | direct branch. | |
707 | (jmp): Likewise. | |
708 | * i386-tbl.h: Regenerated. | |
709 | ||
7b6d09fb L |
710 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
711 | ||
712 | * configure.ac: Support bfd_iamcu_arch. | |
713 | * disassemble.c (disassembler): Support bfd_iamcu_arch. | |
714 | * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and | |
715 | CPU_IAMCU_COMPAT_FLAGS. | |
716 | (cpu_flags): Add CpuIAMCU. | |
717 | * i386-opc.h (CpuIAMCU): New. | |
718 | (i386_cpu_flags): Add cpuiamcu. | |
719 | * configure: Regenerated. | |
720 | * i386-init.h: Likewise. | |
721 | * i386-tbl.h: Likewise. | |
722 | ||
31955f99 L |
723 | 2015-05-08 H.J. Lu <hongjiu.lu@intel.com> |
724 | ||
725 | PR binutis/18386 | |
726 | * i386-dis.c (X86_64_E8): New. | |
727 | (X86_64_E9): Likewise. | |
728 | Update comments on 'T', 'U', 'V'. Add comments for '^'. | |
729 | (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. | |
730 | (x86_64_table): Add X86_64_E8 and X86_64_E9. | |
731 | (mod_table): Replace {T|} with ^ on Jcall/Jmp. | |
732 | (putop): Handle '^'. | |
733 | (OP_J): Ignore the operand size prefix in 64-bit. Don't check | |
734 | REX_W. | |
735 | ||
0952813b DD |
736 | 2015-04-30 DJ Delorie <dj@redhat.com> |
737 | ||
738 | * disassemble.c (disassembler): Choose suitable disassembler based | |
739 | on E_ABI. | |
740 | * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use | |
741 | it to decode mul/div insns. | |
742 | * rl78-decode.c: Regenerate. | |
743 | * rl78-dis.c (print_insn_rl78): Rename to... | |
744 | (print_insn_rl78_common): ...this, take ISA parameter. | |
745 | (print_insn_rl78): New. | |
746 | (print_insn_rl78_g10): New. | |
747 | (print_insn_rl78_g13): New. | |
748 | (print_insn_rl78_g14): New. | |
749 | (rl78_get_disassembler): New. | |
750 | ||
f9d3ecaa NC |
751 | 2015-04-29 Nick Clifton <nickc@redhat.com> |
752 | ||
753 | * po/fr.po: Updated French translation. | |
754 | ||
4fff86c5 PB |
755 | 2015-04-27 Peter Bergner <bergner@vnet.ibm.com> |
756 | ||
757 | * ppc-opc.c (DCBT_EO): New define. | |
758 | (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. | |
759 | <lharx>: Likewise. | |
760 | <stbcx.>: Likewise. | |
761 | <sthcx.>: Likewise. | |
762 | <waitrsv>: Do not enable for POWER7 and later. | |
763 | <waitimpl>: Likewise. | |
764 | <dcbt>: Default to the two operand form of the instruction for all | |
765 | "old" cpus. For "new" cpus, use the operand ordering that matches | |
766 | whether the cpu is server or embedded. | |
767 | <dcbtst>: Likewise. | |
768 | ||
3b78cfe1 AK |
769 | 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
770 | ||
771 | * s390-opc.c: New instruction type VV0UU2. | |
772 | * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, | |
773 | and WFC. | |
774 | ||
04d824a4 JB |
775 | 2015-04-23 Jan Beulich <jbeulich@suse.com> |
776 | ||
777 | * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". | |
778 | * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, | |
779 | vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. | |
780 | (vfpclasspd, vfpclassps): Add %XZ. | |
781 | ||
09708981 L |
782 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
783 | ||
784 | * i386-dis.c (PREFIX_UD_SHIFT): Removed. | |
785 | (PREFIX_UD_REPZ): Likewise. | |
786 | (PREFIX_UD_REPNZ): Likewise. | |
787 | (PREFIX_UD_DATA): Likewise. | |
788 | (PREFIX_UD_ADDR): Likewise. | |
789 | (PREFIX_UD_LOCK): Likewise. | |
790 | ||
3888916d L |
791 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
792 | ||
793 | * i386-dis.c (prefix_requirement): Removed. | |
794 | (print_insn): Don't set prefix_requirement. Check | |
795 | dp->prefix_requirement instead of prefix_requirement. | |
796 | ||
f24bcbaa L |
797 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
798 | ||
799 | PR binutils/17898 | |
800 | * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... | |
801 | (PREFIX_MOD_0_0FC7_REG_6): This. | |
802 | (PREFIX_MOD_3_0FC7_REG_6): New. | |
803 | (PREFIX_MOD_3_0FC7_REG_7): Likewise. | |
804 | (prefix_table): Replace PREFIX_0FC7_REG_6 with | |
805 | PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and | |
806 | PREFIX_MOD_3_0FC7_REG_7. | |
807 | (mod_table): Replace PREFIX_0FC7_REG_6 with | |
808 | PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and | |
809 | PREFIX_MOD_3_0FC7_REG_7. | |
810 | ||
507bd325 L |
811 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
812 | ||
813 | * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. | |
814 | (PREFIX_MANDATORY_REPNZ): Likewise. | |
815 | (PREFIX_MANDATORY_DATA): Likewise. | |
816 | (PREFIX_MANDATORY_ADDR): Likewise. | |
817 | (PREFIX_MANDATORY_LOCK): Likewise. | |
818 | (PREFIX_MANDATORY): Likewise. | |
819 | (PREFIX_UD_SHIFT): Set to 8 | |
820 | (PREFIX_UD_REPZ): Updated. | |
821 | (PREFIX_UD_REPNZ): Likewise. | |
822 | (PREFIX_UD_DATA): Likewise. | |
823 | (PREFIX_UD_ADDR): Likewise. | |
824 | (PREFIX_UD_LOCK): Likewise. | |
825 | (PREFIX_IGNORED_SHIFT): New. | |
826 | (PREFIX_IGNORED_REPZ): Likewise. | |
827 | (PREFIX_IGNORED_REPNZ): Likewise. | |
828 | (PREFIX_IGNORED_DATA): Likewise. | |
829 | (PREFIX_IGNORED_ADDR): Likewise. | |
830 | (PREFIX_IGNORED_LOCK): Likewise. | |
831 | (PREFIX_OPCODE): Likewise. | |
832 | (PREFIX_IGNORED): Likewise. | |
833 | (Bad_Opcode): Replace PREFIX_MANDATORY with 0. | |
834 | (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
835 | (three_byte_table): Likewise. | |
836 | (mod_table): Likewise. | |
837 | (mandatory_prefix): Renamed to ... | |
838 | (prefix_requirement): This. | |
839 | (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
840 | Update PREFIX_90 entry. | |
841 | (get_valid_dis386): Check prefix_requirement to see if a prefix | |
842 | should be ignored. | |
843 | (print_insn): Replace mandatory_prefix with prefix_requirement. | |
844 | ||
f0fba320 RL |
845 | 2015-04-15 Renlin Li <renlin.li@arm.com> |
846 | ||
847 | * arm-dis.c (thumb32_opcodes): Define 'D' format control code, | |
848 | use it for ssat and ssat16. | |
849 | (print_insn_thumb32): Add handle case for 'D' control code. | |
850 | ||
bf890a93 IT |
851 | 2015-04-06 Ilya Tocar <ilya.tocar@intel.com> |
852 | H.J. Lu <hongjiu.lu@intel.com> | |
853 | ||
854 | * i386-dis-evex.h (evex_table): Fill prefix_requirement field. | |
855 | * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, | |
856 | PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, | |
857 | PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, | |
858 | PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. | |
859 | (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): | |
860 | Fill prefix_requirement field. | |
861 | (struct dis386): Add prefix_requirement field. | |
862 | (dis386): Fill prefix_requirement field. | |
863 | (dis386_twobyte): Ditto. | |
864 | (twobyte_has_mandatory_prefix_: Remove. | |
865 | (reg_table): Fill prefix_requirement field. | |
866 | (prefix_table): Ditto. | |
867 | (x86_64_table): Ditto. | |
868 | (three_byte_table): Ditto. | |
869 | (xop_table): Ditto. | |
870 | (vex_table): Ditto. | |
871 | (vex_len_table): Ditto. | |
872 | (vex_w_table): Ditto. | |
873 | (mod_table): Ditto. | |
874 | (bad_opcode): Ditto. | |
875 | (print_insn): Use prefix_requirement. | |
876 | (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, | |
877 | FGRPde_3, FGRPdf_4): Fill prefix_requirement field. | |
878 | (float_reg): Ditto. | |
879 | ||
2f783c1f MF |
880 | 2015-03-30 Mike Frysinger <vapier@gentoo.org> |
881 | ||
882 | * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. | |
883 | ||
b9d94d62 L |
884 | 2015-03-29 H.J. Lu <hongjiu.lu@intel.com> |
885 | ||
886 | * Makefile.in: Regenerated. | |
887 | ||
27c49e9a AB |
888 | 2015-03-25 Anton Blanchard <anton@samba.org> |
889 | ||
890 | * ppc-dis.c (disassemble_init_powerpc): Only initialise | |
891 | powerpc_opcd_indices and vle_opcd_indices once. | |
892 | ||
c4e676f1 AB |
893 | 2015-03-25 Anton Blanchard <anton@samba.org> |
894 | ||
895 | * ppc-opc.c (powerpc_opcodes): Add slbfee. | |
896 | ||
823d2571 TG |
897 | 2015-03-24 Terry Guo <terry.guo@arm.com> |
898 | ||
899 | * arm-dis.c (opcode32): Updated to use new arm feature struct. | |
900 | (opcode16): Likewise. | |
901 | (coprocessor_opcodes): Replace bit with feature struct. | |
902 | (neon_opcodes): Likewise. | |
903 | (arm_opcodes): Likewise. | |
904 | (thumb_opcodes): Likewise. | |
905 | (thumb32_opcodes): Likewise. | |
906 | (print_insn_coprocessor): Likewise. | |
907 | (print_insn_arm): Likewise. | |
908 | (select_arm_features): Follow new feature struct. | |
909 | ||
029f3522 GG |
910 | 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> |
911 | ||
912 | * i386-dis.c (rm_table): Add clzero. | |
913 | * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. | |
914 | Add CPU_CLZERO_FLAGS. | |
915 | (cpu_flags): Add CpuCLZERO. | |
916 | * i386-opc.h: Add CpuCLZERO. | |
917 | * i386-opc.tbl: Add clzero. | |
918 | * i386-init.h: Re-generated. | |
919 | * i386-tbl.h: Re-generated. | |
920 | ||
6914869a AB |
921 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
922 | ||
923 | * mips-opc.c (decode_mips_operand): Fix constraint issues | |
924 | with u and y operands. | |
925 | ||
21e20815 AB |
926 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
927 | ||
928 | * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. | |
929 | ||
6b1d7593 AK |
930 | 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
931 | ||
932 | * s390-opc.c: Add new IBM z13 instructions. | |
933 | * s390-opc.txt: Likewise. | |
934 | ||
c8f89a34 JW |
935 | 2015-03-10 Renlin Li <renlin.li@arm.com> |
936 | ||
937 | * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, | |
938 | stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and | |
939 | related alias. | |
940 | * aarch64-asm-2.c: Regenerate. | |
941 | * aarch64-dis-2.c: Likewise. | |
942 | * aarch64-opc-2.c: Likewise. | |
943 | ||
d8282f0e JW |
944 | 2015-03-03 Jiong Wang <jiong.wang@arm.com> |
945 | ||
946 | * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. | |
947 | ||
ac994365 OE |
948 | 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org> |
949 | ||
950 | * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of | |
951 | arch_sh_up. | |
952 | (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of | |
953 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. | |
954 | ||
fd63f640 V |
955 | 2015-02-23 Vinay <Vinay.G@kpit.com> |
956 | ||
957 | * rl78-decode.opc (MOV): Added space between two operands for | |
958 | 'mov' instruction in index addressing mode. | |
959 | * rl78-decode.c: Regenerate. | |
960 | ||
f63c1776 PA |
961 | 2015-02-19 Pedro Alves <palves@redhat.com> |
962 | ||
963 | * microblaze-dis.h [__cplusplus]: Wrap in extern "C". | |
964 | ||
07774fcc PA |
965 | 2015-02-10 Pedro Alves <palves@redhat.com> |
966 | Tom Tromey <tromey@redhat.com> | |
967 | ||
968 | * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, | |
969 | microblaze_and, microblaze_xor. | |
970 | * microblaze-opc.h (opcodes): Adjust. | |
971 | ||
3f8107ab AM |
972 | 2015-01-28 James Bowman <james.bowman@ftdichip.com> |
973 | ||
974 | * Makefile.am: Add FT32 files. | |
975 | * configure.ac: Handle FT32. | |
976 | * disassemble.c (disassembler): Call print_insn_ft32. | |
977 | * ft32-dis.c: New file. | |
978 | * ft32-opc.c: New file. | |
979 | * Makefile.in: Regenerate. | |
980 | * configure: Regenerate. | |
981 | * po/POTFILES.in: Regenerate. | |
982 | ||
e5fe4957 KLC |
983 | 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
984 | ||
985 | * nds32-asm.c (keyword_sr): Add new system registers. | |
986 | ||
1e2e8c52 AK |
987 | 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
988 | ||
989 | * s390-dis.c (s390_extract_operand): Support vector register | |
990 | operands. | |
991 | (s390_print_insn_with_opcode): Support new operands types and add | |
992 | new handling of optional operands. | |
993 | * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove | |
994 | and include opcode/s390.h instead. | |
995 | (struct op_struct): New field `flags'. | |
996 | (insertOpcode, insertExpandedMnemonic): New parameter `flags'. | |
997 | (dumpTable): Dump flags. | |
998 | (main): Parse flags from the s390-opc.txt file. Add z13 as cpu | |
999 | string. | |
1000 | * s390-opc.c: Add new operands types, instruction formats, and | |
1001 | instruction masks. | |
1002 | (s390_opformats): Add new formats for .insn. | |
1003 | * s390-opc.txt: Add new instructions. | |
1004 | ||
b90efa5b | 1005 | 2015-01-01 Alan Modra <amodra@gmail.com> |
bffb6004 | 1006 | |
b90efa5b | 1007 | Update year range in copyright notice of all files. |
bffb6004 | 1008 | |
b90efa5b | 1009 | For older changes see ChangeLog-2014 |
252b5132 | 1010 | \f |
b90efa5b | 1011 | Copyright (C) 2015 Free Software Foundation, Inc. |
752937aa NC |
1012 | |
1013 | Copying and distribution of this file, with or without modification, | |
1014 | are permitted in any medium without royalty provided the copyright | |
1015 | notice and this notice are preserved. | |
1016 | ||
252b5132 | 1017 | Local Variables: |
2f6d2f85 NC |
1018 | mode: change-log |
1019 | left-margin: 8 | |
1020 | fill-column: 74 | |
252b5132 RH |
1021 | version-control: never |
1022 | End: |