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Synchronize libiberty sources (and include/demangle.h) with GCC master version
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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62194b63
AM		 12021-07-02 Alan Modra <amodra@gmail.com>
2
3 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
4 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
5 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
6 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
7 (nds32_keyword_gpr): Move declarations to..
8 * nds32-asm.h: ..here, constifying to match definitions.
9
2fe36d31
MF		 102021-07-01 Mike Frysinger <vapier@gentoo.org>
11
12 * Makefile.am (GUILE): New variable.
13 (CGEN): Use $(GUILE).
14 * Makefile.in: Regenerate.
15
f375d32b
MF		 162021-07-01 Mike Frysinger <vapier@gentoo.org>
17
18 * mep-asm.c (macros): Mark static & const.
19 (lookup_macro): Change return & m to const.
20 (expand_macro): Change mac to const.
21 (expand_string): Change pmacro to const.
22
9b2beaf7
MF		 232021-07-01 Mike Frysinger <vapier@gentoo.org>
24
25 * nds32-asm.c (operand_fields): Rename to ...
26 (nds32_operand_fields): ... this.
27 (keyword_gpr): Rename to ...
28 (nds32_keyword_gpr): ... this.
29 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
30 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
31 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
32 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
33 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
34 Mark static.
35 (keywords): Rename to ...
36 (nds32_keywords): ... this.
37 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
38 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
39
ac8ef696
MF		 402021-07-01 Mike Frysinger <vapier@gentoo.org>
41
42 * z80-dis.c (opc_ed): Make const.
43 (pref_ed): Make p const.
44
52b83874
MF		 452021-07-01 Mike Frysinger <vapier@gentoo.org>
46
47 * microblaze-dis.c (get_field_special): Make op const.
48 (read_insn_microblaze): Make opr & op const. Rename opcodes to
49 microblaze_opcodes.
50 (print_insn_microblaze): Make op & pop const.
51 (get_insn_microblaze): Make op const. Rename opcodes to
52 microblaze_opcodes.
53 (microblaze_get_target_address): Likewise.
54 * microblaze-opc.h (struct op_code_struct): Make const.
55 Rename opcodes to microblaze_opcodes.
56
6c2ede01
MF		 572021-07-01 Mike Frysinger <vapier@gentoo.org>
58
59 * aarch64-gen.c (aarch64_opcode_table): Add const.
60 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
61
46b8b3d6
AB		 622021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
63
64 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
65 available.
66
ded5cb94
AM		 672021-06-22 Alan Modra <amodra@gmail.com>
68
69 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
70 print separator for pcrel insns.
71
47399e9c
AM		 722021-06-19 Alan Modra <amodra@gmail.com>
73
74 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
75
d984392e
AM		 762021-06-19 Alan Modra <amodra@gmail.com>
77
78 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
79 entire buffer.
80
7993124e
AM		 812021-06-17 Alan Modra <amodra@gmail.com>
82
83 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
84 in table.
85
a38d1396
AM		 862021-06-03 Alan Modra <amodra@gmail.com>
87
88 PR 1202
89 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
90 Use unsigned int for inst.
91
8f467114
SV		 922021-06-02 Shahab Vahedi <shahab@synopsys.com>
93
94 * arc-dis.c (arc_option_arg_t): New enumeration.
95 (arc_options): New variable.
96 (disassembler_options_arc): New function.
97 (print_arc_disassembler_options): Reimplement in terms of
98 "disassembler_options_arc".
99
1ff6a3b8
AM		 1002021-05-29 Alan Modra <amodra@gmail.com>
101
102 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
103 Don't special case PPC_OPCODE_RAW.
104 (lookup_prefix): Likewise.
105 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
106 (print_insn_powerpc): ..update caller.
107 * ppc-opc.c (EXT): Define.
108 (powerpc_opcodes): Mark extended mnemonics with EXT.
109 (prefix_opcodes, vle_opcodes): Likewise.
110 (XISEL, XISEL_MASK): Add cr field and simplify.
111 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
112 all isel variants to where the base mnemonic belongs. Sort dstt,
113 dststt and dssall.
114
49149d59
MR		 1152021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
116
117 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
118 COP3 opcode instructions.
119
9573a461
MR		 1202021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
121
122 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
123 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
124 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
125 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
126 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
127 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
128 "cop2", and "cop3" entries.
129
fa495743
MR		 1302021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
131
132 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
133 entries and associated comments.
134
b930964c
MR		 1352021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
136
137 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
138 of "c0".
139
dd844468
MR		 1402021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
141
142 * mips-dis.c (mips_cp1_names_mips): New variable.
143 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
144 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
145 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
146 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
147 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
148 "loongson2f".
149
9204ccd4
MR		 1502021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
151
152 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
153 handling code over to...
154 <OP_REG_CONTROL>: ... this new case.
155 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
156 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
157 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
158 replacing the `G' operand code with `g'. Update "cftc1" and
159 "cftc2" entries replacing the `E' operand code with `y'.
160 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
161 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
162 entries replacing the `G' operand code with `g'.
163
a3fb396f
MR		 1642021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
165
166 * mips-dis.c (mips_cp0_names_r3900): New variable.
167 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
168 for "r3900".
169
cccc84fa
MR		 1702021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
171
172 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
173 and "mtthc2" to using the `G' rather than `g' operand code for
174 the coprocessor control register referred.
175
c9de3168
MR		 1762021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
177
178 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
179 entries with each other.
180
ebcab741
PB		 1812021-05-27 Peter Bergner <bergner@linux.ibm.com>
182
183 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
184
bc30a119
AM		 1852021-05-25 Alan Modra <amodra@gmail.com>
186
187 * cris-desc.c: Regenerate.
188 * cris-desc.h: Regenerate.
189 * cris-opc.h: Regenerate.
190 * po/POTFILES.in: Regenerate.
191
54711280
MF		 1922021-05-24 Mike Frysinger <vapier@gentoo.org>
193
194 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
195 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
196 (CGEN_CPUS): Add cris.
197 (CRIS_DEPS): Define.
198 (stamp-cris): New rule.
199 * cgen.sh: Handle desc action.
200 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
201 * Makefile.in, configure: Regenerate.
202
113bb761
JN		 2032021-05-18 Job Noorman <mtvec@pm.me>
204
205 PR 27814
206 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
207 the elf objects.
208
e683cb41
AC		 2092021-05-17 Alex Coplan <alex.coplan@arm.com>
210
211 * arm-dis.c (mve_opcodes): Fix disassembly of
212 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
213 (is_mve_encoding_conflict): MVE vector loads should not match
214 when P = W = 0.
215 (is_mve_unpredictable): It's not unpredictable to use the same
216 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
217
a680affc
NC		 2182021-05-11 Nick Clifton <nickc@redhat.com>
219
220 PR 27840
221 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
222 the end of the code buffer.
223
0b3e14c9
SH		 2242021-05-06 Stafford Horne <shorne@gmail.com>
225
226 PR 21464
227 * or1k-asm.c: Regenerate.
228
6aee2cb2
MF		 2292021-05-01 Max Filippov <jcmvbkbc@gmail.com>
230
231 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
232 info->insn_info_valid.
233
fe134c65
JB		 2342021-04-26 Jan Beulich <jbeulich@suse.com>
235
236 * i386-opc.tbl (lea): Add Optimize.
237 * opcodes/i386-tbl.h: Re-generate.
238
b3ea7639
MF		 2392020-04-23 Max Filippov <jcmvbkbc@gmail.com>
240
241 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
242 of l32r fetch and display referenced literal value.
243
c1cbb7d8
MF		 2442021-04-23 Max Filippov <jcmvbkbc@gmail.com>
245
246 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
247 to 4 for literal disassembly.
248
02202574
PW		 2492021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
250
251 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
252 for TLBI instruction.
253
cd6608e4
PW		 2542021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
255
256 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
257 DC instruction.
258
fe1640ff
JB		 2592021-04-19 Jan Beulich <jbeulich@suse.com>
260
261 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
262 "qualifier".
263 (convert_mov_to_movewide): Add initializer for "value".
264
100e914d
PW		 2652021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
266
267 * aarch64-opc.c: Add RME system registers.
268
a21b96dd
NC		 2692021-04-16 Lifang Xia <lifang_xia@c-sky.com>
270
271 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
272 "addi d,CV,z" to "c.mv d,CV".
273
43e05cd4
AM		 2742021-04-12 Alan Modra <amodra@gmail.com>
275
276 * configure.ac (--enable-checking): Add support.
277 * config.in: Regenerate.
278 * configure: Regenerate.
279
52efda82
TB		 2802021-04-09 Tejas Belagod <tejas.belagod@arm.com>
281
282 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
283 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
284
c3f72de4
AM		 2852021-04-09 Alan Modra <amodra@gmail.com>
286
287 * ppc-dis.c (struct dis_private): Add "special".
288 (POWERPC_DIALECT): Delete. Replace uses with..
289 (private_data): ..this. New inline function.
290 (disassemble_init_powerpc): Init "special" names.
291 (skip_optional_operands): Add is_pcrel arg, set when detecting R
292 field of prefix instructions.
293 (bsearch_reloc, print_got_plt): New functions.
294 (print_insn_powerpc): For pcrel instructions, print target address
295 and symbol if known, and decode plt and got loads too.
296
ce7d813a
AM		 2972021-04-08 Alan Modra <amodra@gmail.com>
298
299 PR 27684
300 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
301
97bf40d8
AM		 3022021-04-08 Alan Modra <amodra@gmail.com>
303
304 PR 27676
305 * ppc-opc.c (DCBT_EO): Move earlier.
306 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
307 (powerpc_operands): Add THCT and THDS entries.
308 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
309
a2e66773
AM		 3102021-04-06 Alan Modra <amodra@gmail.com>
311
312 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
313 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
314 symbol_at_address_func.
315
ab2af25e
AM		 3162021-04-05 Alan Modra <amodra@gmail.com>
317
318 * configure.ac: Don't check for limits.h, string.h, strings.h or
319 stdlib.h.
320 (AC_ISC_POSIX): Don't invoke.
321 * sysdep.h: Include stdlib.h and string.h unconditionally.
322 * i386-opc.h: Include limits.h unconditionally.
323 * wasm32-dis.c: Likewise.
324 * cgen-opc.c: Don't include alloca-conf.h.
325 * config.in: Regenerate.
326 * configure: Regenerate.
327
e9b095a5
ML		 3282021-04-01 Martin Liska <mliska@suse.cz>
329
330 * arm-dis.c (strneq): Remove strneq and use startswith.
331 * cr16-dis.c (print_insn_cr16): Likewise.
332 * score-dis.c (streq): Likewise.
333 (strneq): Likewise.
334 * score7-dis.c (strneq): Likewise.
335
1cb108e4
AM		 3362021-04-01 Alan Modra <amodra@gmail.com>
337
338 PR 27675
339 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
340
78933a4a
AM		 3412021-03-31 Alan Modra <amodra@gmail.com>
342
343 * sysdep.h (POISON_BFD_BOOLEAN): Define.
344 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
345 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
346 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
347 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
348 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
349 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
350 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
351 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
352 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
353 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
354 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
355 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
356 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
357 and TRUE with true throughout.
358
3dfb1b6d
AM		 3592021-03-31 Alan Modra <amodra@gmail.com>
360
361 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
362 * aarch64-dis.h: Likewise.
363 * aarch64-opc.c: Likewise.
364 * avr-dis.c: Likewise.
365 * csky-dis.c: Likewise.
366 * nds32-asm.c: Likewise.
367 * nds32-dis.c: Likewise.
368 * nfp-dis.c: Likewise.
369 * riscv-dis.c: Likewise.
370 * s12z-dis.c: Likewise.
371 * wasm32-dis.c: Likewise.
372
5e042380
JB		 3732021-03-30 Jan Beulich <jbeulich@suse.com>
374
375 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
376 (i386_seg_prefixes): New.
377 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
378 (i386_seg_prefixes): Declare.
379
34684862
JB		 3802021-03-30 Jan Beulich <jbeulich@suse.com>
381
382 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
383
6288d05f
JB		 3842021-03-30 Jan Beulich <jbeulich@suse.com>
385
386 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
387 * i386-reg.tbl (st): Move down.
388 (st(0)): Delete. Extend comment.
389 * i386-tbl.h: Re-generate.
390
bbe1eca6
JB		 3912021-03-29 Jan Beulich <jbeulich@suse.com>
392
393 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
394 (cmpsd): Move next to cmps.
395 (movsd): Move next to movs.
396 (cmpxchg16b): Move to separate section.
397 (fisttp, fisttpll): Likewise.
398 (monitor, mwait): Likewise.
399 * i386-tbl.h: Re-generate.
400
c8cad9d3
JB		 4012021-03-29 Jan Beulich <jbeulich@suse.com>
402
403 * i386-opc.tbl (psadbw): Add <sse2:comm>.
404 (vpsadbw): Add C.
405 * i386-tbl.h: Re-generate.
406
5cdaf100
JB		 4072021-03-29 Jan Beulich <jbeulich@suse.com>
408
409 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
410 pclmul, gfni): New templates. Use them wherever possible. Move
411 SSE4.1 pextrw into respective section.
412 * i386-tbl.h: Re-generate.
413
73e45eb2
JB		 4142021-03-29 Jan Beulich <jbeulich@suse.com>
415
416 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
417 strtoull(). Bump upper loop bound. Widen masks. Sanity check
418 "length".
419 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
420 Convert all of their uses to representation in opcode.
421
9df6f676
JB		 4222021-03-29 Jan Beulich <jbeulich@suse.com>
423
424 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
425 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
426 value of None. Shrink operands to 3 bits.
427
389d00a5
JB		 4282021-03-29 Jan Beulich <jbeulich@suse.com>
429
430 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 431 "space".
389d00a5
JB		 432 (output_i386_opcode): New local variable "space". Adjust
433 process_i386_opcode_modifier() invocation.
434 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
435 invocation.
436 * i386-tbl.h: Re-generate.
437
63b4cc53
AM		 4382021-03-29 Alan Modra <amodra@gmail.com>
439
440 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
441 (fp_qualifier_p, get_data_pattern): Likewise.
442 (aarch64_get_operand_modifier_from_value): Likewise.
443 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
444 (operand_variant_qualifier_p): Likewise.
445 (qualifier_value_in_range_constraint_p): Likewise.
446 (aarch64_get_qualifier_esize): Likewise.
447 (aarch64_get_qualifier_nelem): Likewise.
448 (aarch64_get_qualifier_standard_value): Likewise.
449 (get_lower_bound, get_upper_bound): Likewise.
450 (aarch64_find_best_match, match_operands_qualifier): Likewise.
451 (aarch64_print_operand): Likewise.
452 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
453 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
454 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
455 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
456 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
457 (print_insn_tic6x): Likewise.
458
3d7d6c1b
AM		 4592021-03-29 Alan Modra <amodra@gmail.com>
460
461 * arc-dis.c (extract_operand_value): Correct NULL cast.
462 * frv-opc.h: Regenerate.
463
c3344b62
JB		 4642021-03-26 Jan Beulich <jbeulich@suse.com>
465
466 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
467 MMX form.
468 * i386-tbl.h: Re-generate.
469
efa30ac3
HAQ		 4702021-03-25 Abid Qadeer <abidh@codesourcery.com>
471
472 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
473 immediate in br.n instruction.
474
596a02ff
JB		 4752021-03-25 Jan Beulich <jbeulich@suse.com>
476
477 * i386-dis.c (XMGatherD, VexGatherD): New.
478 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
479 (print_insn): Check masking for S/G insns.
480 (OP_E_memory): New local variable check_gather. Extend mandatory
481 SIB check. Check register conflicts for (EVEX-encoded) gathers.
482 Extend check for disallowed 16-bit addressing.
483 (OP_VEX): New local variables modrm_reg and sib_index. Convert
484 if()s to switch(). Check register conflicts for (VEX-encoded)
485 gathers. Drop no longer reachable cases.
486 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
487 vgatherdp*.
488
53642852
JB		 4892021-03-25 Jan Beulich <jbeulich@suse.com>
490
491 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
492 zeroing-masking without masking.
493
c0e54661
JB		 4942021-03-25 Jan Beulich <jbeulich@suse.com>
495
496 * i386-opc.tbl (invlpgb): Fix multi-operand form.
497 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
498 single-operand forms as deprecated.
499 * i386-tbl.h: Re-generate.
500
5a403766
AM		 5012021-03-25 Alan Modra <amodra@gmail.com>
502
503 PR 27647
504 * ppc-opc.c (XLOCB_MASK): Delete.
505 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
506 XLBH_MASK.
507 (powerpc_opcodes): Accept a BH field on all extended forms of
508 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
509
9a182d04
JB		 5102021-03-24 Jan Beulich <jbeulich@suse.com>
511
512 * i386-gen.c (output_i386_opcode): Drop processing of
513 opcode_length. Calculate length from base_opcode. Adjust prefix
514 encoding determination.
515 (process_i386_opcodes): Drop output of fake opcode_length.
516 * i386-opc.h (struct insn_template): Drop opcode_length field.
517 * i386-opc.tbl: Drop opcode length field from all templates.
518 * i386-tbl.h: Re-generate.
519
35648716
JB		 5202021-03-24 Jan Beulich <jbeulich@suse.com>
521
522 * i386-gen.c (process_i386_opcode_modifier): Return void. New
523 parameter "prefix". Drop local variable "regular_encoding".
524 Record prefix setting / check for consistency.
525 (output_i386_opcode): Parse opcode_length and base_opcode
526 earlier. Derive prefix encoding. Drop no longer applicable
527 consistency checking. Adjust process_i386_opcode_modifier()
528 invocation.
529 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
530 invocation.
531 * i386-tbl.h: Re-generate.
532
31184569
JB		 5332021-03-24 Jan Beulich <jbeulich@suse.com>
534
535 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
536 check.
537 * i386-opc.h (Prefix_*): Move #define-s.
538 * i386-opc.tbl: Move pseudo prefix enumerator values to
539 extension opcode field. Introduce pseudopfx template.
540 * i386-tbl.h: Re-generate.
541
b933fa4b
JB		 5422021-03-23 Jan Beulich <jbeulich@suse.com>
543
544 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
545 comment.
546 * i386-tbl.h: Re-generate.
547
dac10fb0
JB		 5482021-03-23 Jan Beulich <jbeulich@suse.com>
549
550 * i386-opc.h (struct insn_template): Move cpu_flags field past
551 opcode_modifier one.
552 * i386-tbl.h: Re-generate.
553
441f6aca
JB		 5542021-03-23 Jan Beulich <jbeulich@suse.com>
555
556 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
557 * i386-opc.h (OpcodeSpace): New enumerator.
558 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
559 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
560 SPACE_XOP09, SPACE_XOP0A): ... respectively.
561 (struct i386_opcode_modifier): New field opcodespace. Shrink
562 opcodeprefix field.
563 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
564 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
565 OpcodePrefix uses.
566 * i386-tbl.h: Re-generate.
567
08dedd66
ML		 5682021-03-22 Martin Liska <mliska@suse.cz>
569
570 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
571 * arc-dis.c (parse_option): Likewise.
572 * arm-dis.c (parse_arm_disassembler_options): Likewise.
573 * cris-dis.c (print_with_operands): Likewise.
574 * h8300-dis.c (bfd_h8_disassemble): Likewise.
575 * i386-dis.c (print_insn): Likewise.
576 * ia64-gen.c (fetch_insn_class): Likewise.
577 (parse_resource_users): Likewise.
578 (in_iclass): Likewise.
579 (lookup_specifier): Likewise.
580 (insert_opcode_dependencies): Likewise.
581 * mips-dis.c (parse_mips_ase_option): Likewise.
582 (parse_mips_dis_option): Likewise.
583 * s390-dis.c (disassemble_init_s390): Likewise.
584 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
585
80d49d6a
KLC		 5862021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
587
588 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
589
7fce7ea9
PW		 5902021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
591
592 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
593 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
594
78c84bf9
AM		 5952021-03-12 Alan Modra <amodra@gmail.com>
596
597 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
598
fd1fd061
JB		 5992021-03-11 Jan Beulich <jbeulich@suse.com>
600
601 * i386-dis.c (OP_XMM): Re-order checks.
602
ac7a2311
JB		 6032021-03-11 Jan Beulich <jbeulich@suse.com>
604
605 * i386-dis.c (putop): Drop need_vex check when also checking
606 vex.evex.
607 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
608 checking vex.b.
609
da944c8a
JB		 6102021-03-11 Jan Beulich <jbeulich@suse.com>
611
612 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
613 checks. Move case label past broadcast check.
614
b763d508
JB		 6152021-03-10 Jan Beulich <jbeulich@suse.com>
616
617 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
618 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
619 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
620 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
621 EVEX_W_0F38C7_M_0_L_2): Delete.
622 (REG_EVEX_0F38C7_M_0_L_2): New.
623 (intel_operand_size): Handle VEX and EVEX the same for
624 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
625 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
626 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
627 vex_vsib_q_w_d_mode uses.
628 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
629 0F38A1, and 0F38A3 entries.
630 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
631 entry.
632 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
633 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
634 0F38A3 entries.
635
32e31ad7
JB		 6362021-03-10 Jan Beulich <jbeulich@suse.com>
637
638 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
639 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
640 MOD_VEX_0FXOP_09_12): Rename to ...
641 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
642 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
643 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
644 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
645 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
646 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
647 (reg_table): Adjust comments.
648 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
649 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
650 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
651 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
652 (vex_len_table): Adjust opcode 0A_12 entry.
653 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
654 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
655 (rm_table): Move hreset entry.
656
85ba7507
JB		 6572021-03-10 Jan Beulich <jbeulich@suse.com>
658
659 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
660 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
661 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
662 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
663 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
664 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
665 (get_valid_dis386): Also handle 512-bit vector length when
666 vectoring into vex_len_table[].
667 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
668 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
669 entries.
670 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
671 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
672 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
673 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
674 entries.
675
066f82b9
JB		 6762021-03-10 Jan Beulich <jbeulich@suse.com>
677
678 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
679 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
680 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
681 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
682 entries.
683 * i386-dis-evex-len.h (evex_len_table): Likewise.
684 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
685
fc681dd6
JB		 6862021-03-10 Jan Beulich <jbeulich@suse.com>
687
688 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
689 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
690 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
691 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
692 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
693 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
694 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
695 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
696 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
697 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
698 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
699 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
700 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
701 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
702 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
703 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
704 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
705 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
706 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
707 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
708 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
709 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
710 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
711 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
712 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
713 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
714 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
715 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
716 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
717 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
718 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
719 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
720 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
721 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
722 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
723 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
724 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
725 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
726 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
727 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
728 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
729 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
730 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
731 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
732 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
733 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
734 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
735 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
736 EVEX_W_0F3A43_L_n): New.
737 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
738 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
739 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
740 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
741 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
742 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
743 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
744 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
745 0F385B, 0F38C6, and 0F38C7 entries.
746 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
747 0F38C6 and 0F38C7.
748 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
749 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
750 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
751 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
752
13954a31
JB		 7532021-03-10 Jan Beulich <jbeulich@suse.com>
754
755 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
756 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
757 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
758 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
759 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
760 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
761 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
762 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
763 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
764 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
765 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
766 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
767 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
768 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
769 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
770 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
771 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
772 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
773 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
774 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
775 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
776 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
777 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
778 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
779 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
780 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
781 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
782 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
783 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
784 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
785 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
786 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
787 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
788 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
789 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
790 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
791 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
792 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
793 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
794 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
795 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
796 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
797 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
798 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
799 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
800 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
801 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
802 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
803 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
804 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
805 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
806 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
807 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
808 VEX_W_0F99_P_2_LEN_0): Delete.
809 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
810 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
811 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
812 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
813 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
814 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
815 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
816 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
817 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
818 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
819 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
820 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
821 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
822 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
823 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
824 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
825 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
826 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
827 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
828 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
829 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
830 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
831 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
832 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
833 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
834 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
835 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
836 (prefix_table): No longer link to vex_len_table[] for opcodes
837 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
838 0F92, 0F93, 0F98, and 0F99.
839 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
840 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
841 0F98, and 0F99.
842 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
843 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
844 0F98, and 0F99.
845 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
846 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
847 0F98, and 0F99.
848 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
849 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
850 0F98, and 0F99.
851
14d10c6c
JB		 8522021-03-10 Jan Beulich <jbeulich@suse.com>
853
854 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
855 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
856 REG_VEX_0F73_M_0 respectively.
857 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
858 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
859 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
860 MOD_VEX_0F73_REG_7): Delete.
861 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
862 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
863 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
864 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
865 PREFIX_VEX_0F3AF0_L_0 respectively.
866 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
867 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
868 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
869 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
870 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
871 VEX_LEN_0F38F7): New.
872 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
873 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
874 0F72, and 0F73. No longer link to vex_len_table[] for opcode
875 0F38F3.
876 (prefix_table): No longer link to vex_len_table[] for opcodes
877 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
878 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
879 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
880 0F38F6, 0F38F7, and 0F3AF0.
881 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
882 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
883 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
884 0F73.
885
00ec1875
JB		 8862021-03-10 Jan Beulich <jbeulich@suse.com>
887
888 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
889 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
890 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
891 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
892 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
893 (MOD_0F71, MOD_0F72, MOD_0F73): New.
894 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
895 73.
896 (reg_table): No longer link to mod_table[] for opcodes 0F71,
897 0F72, and 0F73.
898 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
899 0F73.
900
31941983
JB		 9012021-03-10 Jan Beulich <jbeulich@suse.com>
902
903 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
904 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
905 (reg_table): Don't link to mod_table[] where not needed. Add
906 PREFIX_IGNORED to nop entries.
907 (prefix_table): Replace PREFIX_OPCODE in nop entries.
908 (mod_table): Add nop entries next to prefetch ones. Drop
909 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
910 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
911 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
912 PREFIX_OPCODE from endbr* entries.
913 (get_valid_dis386): Also consider entry's name when zapping
914 vindex.
915 (print_insn): Handle PREFIX_IGNORED.
916
742732c7
JB		 9172021-03-09 Jan Beulich <jbeulich@suse.com>
918
919 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
920 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
921 element.
922 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
923 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
924 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
925 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
926 (struct i386_opcode_modifier): Delete notrackprefixok,
927 islockable, hleprefixok, and repprefixok fields. Add prefixok
928 field.
929 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
930 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
931 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
932 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
933 Replace HLEPrefixOk.
934 * opcodes/i386-tbl.h: Re-generate.
935
e93a3b27
JB		 9362021-03-09 Jan Beulich <jbeulich@suse.com>
937
938 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
939 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
940 64-bit form.
941 * opcodes/i386-tbl.h: Re-generate.
942
75363b6d
JB		 9432021-03-03 Jan Beulich <jbeulich@suse.com>
944
945 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
946 for {} instead of {0}. Don't look for '0'.
947 * i386-opc.tbl: Drop operand count field. Drop redundant operand
948 size specifiers.
949
5a9f5403
NC		 9502021-02-19 Nelson Chu <nelson.chu@sifive.com>
951
952 PR 27158
953 * riscv-dis.c (print_insn_args): Updated encoding macros.
954 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
955 (match_c_addi16sp): Updated encoding macros.
956 (match_c_lui): Likewise.
957 (match_c_lui_with_hint): Likewise.
958 (match_c_addi4spn): Likewise.
959 (match_c_slli): Likewise.
960 (match_slli_as_c_slli): Likewise.
961 (match_c_slli64): Likewise.
962 (match_srxi_as_c_srxi): Likewise.
963 (riscv_insn_types): Added .insn css/cl/cs.
964
3d73d29e
NC		 9652021-02-18 Nelson Chu <nelson.chu@sifive.com>
966
967 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
968 (default_priv_spec): Updated type to riscv_spec_class.
969 (parse_riscv_dis_option): Updated.
970 * riscv-opc.c: Moved stuff and make the file tidy.
971
b9b204b3
AM		 9722021-02-17 Alan Modra <amodra@gmail.com>
973
974 * wasm32-dis.c: Include limits.h.
975 (CHAR_BIT): Provide backup define.
976 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
977 Correct signed overflow checking.
978
394ae71f
JB		 9792021-02-16 Jan Beulich <jbeulich@suse.com>
980
981 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
982 * i386-tbl.h: Re-generate.
983
b818b220
JB		 9842021-02-16 Jan Beulich <jbeulich@suse.com>
985
986 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
987 Oword.
988 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
989
ba2b480f
AK		 9902021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
991
992 * s390-mkopc.c (main): Accept arch14 as cpu string.
993 * s390-opc.txt: Add new arch14 instructions.
994
95148614
NA		 9952021-02-04 Nick Alcock <nick.alcock@oracle.com>
996
997 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
998 favour of LIBINTL.
999 * configure: Regenerated.
1000
bfd428bc
MF		 10012021-02-08 Mike Frysinger <vapier@gentoo.org>
1002
1003 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1004 * tic54x-opc.c (regs): Rename to ...
1005 (tic54x_regs): ... this.
1006 (mmregs): Rename to ...
1007 (tic54x_mmregs): ... this.
1008 (condition_codes): Rename to ...
1009 (tic54x_condition_codes): ... this.
1010 (cc2_codes): Rename to ...
1011 (tic54x_cc2_codes): ... this.
1012 (cc3_codes): Rename to ...
1013 (tic54x_cc3_codes): ... this.
1014 (status_bits): Rename to ...
1015 (tic54x_status_bits): ... this.
1016 (misc_symbols): Rename to ...
1017 (tic54x_misc_symbols): ... this.
1018
24075dcc
NC		 10192021-02-04 Nelson Chu <nelson.chu@sifive.com>
1020
1021 * riscv-opc.c (MASK_RVB_IMM): Removed.
1022 (riscv_opcodes): Removed zb* instructions.
1023 (riscv_ext_version_table): Removed versions for zb*.
1024
c3ffb8f3
AM		 10252021-01-26 Alan Modra <amodra@gmail.com>
1026
1027 * i386-gen.c (parse_template): Ensure entire template_instance
1028 is initialised.
1029
1942a048
NC		 10302021-01-15 Nelson Chu <nelson.chu@sifive.com>
1031
1032 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1033 (riscv_fpr_names_abi): Likewise.
1034 (riscv_opcodes): Likewise.
1035 (riscv_insn_types): Likewise.
1036
b800637e
NC		 10372021-01-15 Nelson Chu <nelson.chu@sifive.com>
1038
1039 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1040
dcd709e0
NC		 10412021-01-15 Nelson Chu <nelson.chu@sifive.com>
1042
1043 * riscv-dis.c: Comments tidy and improvement.
1044 * riscv-opc.c: Likewise.
1045
5347ed60
AM		 10462021-01-13 Alan Modra <amodra@gmail.com>
1047
1048 * Makefile.in: Regenerate.
1049
d546b610
L		 10502021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1051
1052 PR binutils/26792
1053 * configure.ac: Use GNU_MAKE_JOBSERVER.
1054 * aclocal.m4: Regenerated.
1055 * configure: Likewise.
1056
6d104cac
NC		 10572021-01-12 Nick Clifton <nickc@redhat.com>
1058
1059 * po/sr.po: Updated Serbian translation.
1060
83b33c6c
L		 10612021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1062
1063 PR ld/27173
1064 * configure: Regenerated.
1065
82c70b08
KT		 10662021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1067
1068 * aarch64-asm-2.c: Regenerate.
1069 * aarch64-dis-2.c: Likewise.
1070 * aarch64-opc-2.c: Likewise.
1071 * aarch64-opc.c (aarch64_print_operand):
1072 Delete handling of AARCH64_OPND_CSRE_CSR.
1073 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1074 (CSRE): Likewise.
1075 (_CSRE_INSN): Likewise.
1076 (aarch64_opcode_table): Delete csr.
1077
a8aa72b9
NC		 10782021-01-11 Nick Clifton <nickc@redhat.com>
1079
1080 * po/de.po: Updated German translation.
1081 * po/fr.po: Updated French translation.
1082 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1083 * po/sv.po: Updated Swedish translation.
1084 * po/uk.po: Updated Ukranian translation.
1085
a4966cd9
L		 10862021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1087
1088 * configure: Regenerated.
1089
573fe3fb
NC		 10902021-01-09 Nick Clifton <nickc@redhat.com>
1091
1092 * configure: Regenerate.
1093 * po/opcodes.pot: Regenerate.
1094
055bc77a
NC		 10952021-01-09 Nick Clifton <nickc@redhat.com>
1096
1097 * 2.36 release branch crated.
1098
aae7fcb8
PB		 10992021-01-08 Peter Bergner <bergner@linux.ibm.com>
1100
1101 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1102 (DW, (XRC_MASK): Define.
1103 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1104
64307045
AM		 11052021-01-09 Alan Modra <amodra@gmail.com>
1106
1107 * configure: Regenerate.
1108
ed205222
NC		 11092021-01-08 Nick Clifton <nickc@redhat.com>
1110
1111 * po/sv.po: Updated Swedish translation.
1112
fb932b57
NC		 11132021-01-08 Nick Clifton <nickc@redhat.com>
1114
e84c8716
NC		 1115 PR 27129
1116 * aarch64-dis.c (determine_disassembling_preference): Move call to
1117 aarch64_match_operands_constraint outside of the assertion.
1118 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1119 Replace with a return of FALSE.
1120
fb932b57
NC		 1121 PR 27139
1122 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1123 core system register.
1124
f4782128
ST		 11252021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1126
1127 * configure: Regenerate.
1128
1b0927db
NC		 11292021-01-07 Nick Clifton <nickc@redhat.com>
1130
1131 * po/fr.po: Updated French translation.
1132
3b288c8e
FN		 11332021-01-07 Fredrik Noring <noring@nocrew.org>
1134
1135 * m68k-opc.c (chkl): Change minimum architecture requirement to
1136 m68020.
1137
aa881ecd
PT		 11382021-01-07 Philipp Tomsich <prt@gnu.org>
1139
1140 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1141
2652cfad
CXW		 11422021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1143 Jim Wilson <jimw@sifive.com>
1144 Andrew Waterman <andrew@sifive.com>
1145 Maxim Blinov <maxim.blinov@embecosm.com>
1146 Kito Cheng <kito.cheng@sifive.com>
1147 Nelson Chu <nelson.chu@sifive.com>
1148
1149 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1150 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1151
250d07de
AM		 11522021-01-01 Alan Modra <amodra@gmail.com>
1153
1154 Update year range in copyright notice of all files.
1155
c2795844 1156For older changes see ChangeLog-2020
3499769a 1157\f
c2795844 1158Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1159
1160Copying and distribution of this file, with or without modification,
1161are permitted in any medium without royalty provided the copyright
1162notice and this notice are preserved.
1163
1164Local Variables:
1165mode: change-log
1166left-margin: 8
1167fill-column: 74
1168version-control: never
1169End:
A mirror of the official binutils-gdb repository