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Commit | Line | Data |
---|---|---|
ddfded2f MW |
1 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
2 | ||
3 | * arm-dis.c (arm_opcodes): Add "setpan". | |
4 | (thumb_opcodes): Add "setpan". | |
5 | ||
1af1dd51 MW |
6 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
7 | ||
8 | * arm-dis.c (select_arm_features): Rework to avoid used of redefined | |
9 | macros. | |
10 | ||
9e1f0fa7 MW |
11 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
12 | ||
13 | * aarch64-tbl.h (aarch64_feature_rdma): New. | |
14 | (RDMA): New. | |
15 | (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. | |
16 | * aarch64-asm-2.c: Regenerate. | |
17 | * aarch64-dis-2.c: Regenerate. | |
18 | * aarch64-opc-2.c: Regenerate. | |
19 | ||
290806fd MW |
20 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
21 | ||
22 | * aarch64-tbl.h (aarch64_feature_lor): New. | |
23 | (LOR): New. | |
24 | (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", | |
25 | "stllrb", "stllrh". | |
26 | * aarch64-asm-2.c: Regenerate. | |
27 | * aarch64-dis-2.c: Regenerate. | |
28 | * aarch64-opc-2.c: Regenerate. | |
29 | ||
f21cce2c MW |
30 | 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> |
31 | ||
32 | * aarch64-opc.c (F_ARCHEXT): New. | |
33 | (aarch64_sys_regs): Add "pan". | |
34 | (aarch64_sys_reg_supported_p): New. | |
35 | (aarch64_pstatefields): Add "pan". | |
36 | (aarch64_pstatefield_supported_p): New. | |
37 | ||
d194d186 JB |
38 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
39 | ||
40 | * i386-tbl.h: Regenerate. | |
41 | ||
3a8547d2 JB |
42 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
43 | ||
44 | * i386-dis.c (print_insn): Swap rounding mode specifier and | |
45 | general purpose register in Intel mode. | |
46 | ||
015c54d5 JB |
47 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
48 | ||
49 | * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. | |
50 | * i386-tbl.h: Regenerate. | |
51 | ||
071f0063 L |
52 | 2015-05-18 H.J. Lu <hongjiu.lu@intel.com> |
53 | ||
54 | * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. | |
55 | * i386-init.h: Regenerated. | |
56 | ||
5db04b09 L |
57 | 2015-05-15 H.J. Lu <hongjiu.lu@intel.com> |
58 | ||
59 | PR binutis/18386 | |
60 | * i386-dis.c: Add comments for '@'. | |
61 | (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. | |
62 | (enum x86_64_isa): New. | |
63 | (isa64): Likewise. | |
64 | (print_i386_disassembler_options): Add amd64 and intel64. | |
65 | (print_insn): Handle amd64 and intel64. | |
66 | (putop): Handle '@'. | |
67 | (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. | |
68 | * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. | |
69 | * i386-opc.h (AMD64): New. | |
70 | (CpuIntel64): Likewise. | |
71 | (i386_cpu_flags): Add cpuamd64 and cpuintel64. | |
72 | * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. | |
73 | Mark direct call/jmp without Disp16|Disp32 as Intel64. | |
74 | * i386-init.h: Regenerated. | |
75 | * i386-tbl.h: Likewise. | |
76 | ||
4bc0608a PB |
77 | 2015-05-14 Peter Bergner <bergner@vnet.ibm.com> |
78 | ||
79 | * ppc-opc.c (IH) New define. | |
80 | (powerpc_opcodes) <wait>: Do not enable for POWER7. | |
81 | <tlbie>: Add RS operand for POWER7. | |
82 | <slbia>: Add IH operand for POWER6. | |
83 | ||
70cead07 L |
84 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
85 | ||
86 | * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit | |
87 | direct branch. | |
88 | (jmp): Likewise. | |
89 | * i386-tbl.h: Regenerated. | |
90 | ||
7b6d09fb L |
91 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
92 | ||
93 | * configure.ac: Support bfd_iamcu_arch. | |
94 | * disassemble.c (disassembler): Support bfd_iamcu_arch. | |
95 | * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and | |
96 | CPU_IAMCU_COMPAT_FLAGS. | |
97 | (cpu_flags): Add CpuIAMCU. | |
98 | * i386-opc.h (CpuIAMCU): New. | |
99 | (i386_cpu_flags): Add cpuiamcu. | |
100 | * configure: Regenerated. | |
101 | * i386-init.h: Likewise. | |
102 | * i386-tbl.h: Likewise. | |
103 | ||
31955f99 L |
104 | 2015-05-08 H.J. Lu <hongjiu.lu@intel.com> |
105 | ||
106 | PR binutis/18386 | |
107 | * i386-dis.c (X86_64_E8): New. | |
108 | (X86_64_E9): Likewise. | |
109 | Update comments on 'T', 'U', 'V'. Add comments for '^'. | |
110 | (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. | |
111 | (x86_64_table): Add X86_64_E8 and X86_64_E9. | |
112 | (mod_table): Replace {T|} with ^ on Jcall/Jmp. | |
113 | (putop): Handle '^'. | |
114 | (OP_J): Ignore the operand size prefix in 64-bit. Don't check | |
115 | REX_W. | |
116 | ||
0952813b DD |
117 | 2015-04-30 DJ Delorie <dj@redhat.com> |
118 | ||
119 | * disassemble.c (disassembler): Choose suitable disassembler based | |
120 | on E_ABI. | |
121 | * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use | |
122 | it to decode mul/div insns. | |
123 | * rl78-decode.c: Regenerate. | |
124 | * rl78-dis.c (print_insn_rl78): Rename to... | |
125 | (print_insn_rl78_common): ...this, take ISA parameter. | |
126 | (print_insn_rl78): New. | |
127 | (print_insn_rl78_g10): New. | |
128 | (print_insn_rl78_g13): New. | |
129 | (print_insn_rl78_g14): New. | |
130 | (rl78_get_disassembler): New. | |
131 | ||
f9d3ecaa NC |
132 | 2015-04-29 Nick Clifton <nickc@redhat.com> |
133 | ||
134 | * po/fr.po: Updated French translation. | |
135 | ||
4fff86c5 PB |
136 | 2015-04-27 Peter Bergner <bergner@vnet.ibm.com> |
137 | ||
138 | * ppc-opc.c (DCBT_EO): New define. | |
139 | (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. | |
140 | <lharx>: Likewise. | |
141 | <stbcx.>: Likewise. | |
142 | <sthcx.>: Likewise. | |
143 | <waitrsv>: Do not enable for POWER7 and later. | |
144 | <waitimpl>: Likewise. | |
145 | <dcbt>: Default to the two operand form of the instruction for all | |
146 | "old" cpus. For "new" cpus, use the operand ordering that matches | |
147 | whether the cpu is server or embedded. | |
148 | <dcbtst>: Likewise. | |
149 | ||
3b78cfe1 AK |
150 | 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
151 | ||
152 | * s390-opc.c: New instruction type VV0UU2. | |
153 | * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, | |
154 | and WFC. | |
155 | ||
04d824a4 JB |
156 | 2015-04-23 Jan Beulich <jbeulich@suse.com> |
157 | ||
158 | * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". | |
159 | * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, | |
160 | vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. | |
161 | (vfpclasspd, vfpclassps): Add %XZ. | |
162 | ||
09708981 L |
163 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
164 | ||
165 | * i386-dis.c (PREFIX_UD_SHIFT): Removed. | |
166 | (PREFIX_UD_REPZ): Likewise. | |
167 | (PREFIX_UD_REPNZ): Likewise. | |
168 | (PREFIX_UD_DATA): Likewise. | |
169 | (PREFIX_UD_ADDR): Likewise. | |
170 | (PREFIX_UD_LOCK): Likewise. | |
171 | ||
3888916d L |
172 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
173 | ||
174 | * i386-dis.c (prefix_requirement): Removed. | |
175 | (print_insn): Don't set prefix_requirement. Check | |
176 | dp->prefix_requirement instead of prefix_requirement. | |
177 | ||
f24bcbaa L |
178 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
179 | ||
180 | PR binutils/17898 | |
181 | * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... | |
182 | (PREFIX_MOD_0_0FC7_REG_6): This. | |
183 | (PREFIX_MOD_3_0FC7_REG_6): New. | |
184 | (PREFIX_MOD_3_0FC7_REG_7): Likewise. | |
185 | (prefix_table): Replace PREFIX_0FC7_REG_6 with | |
186 | PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and | |
187 | PREFIX_MOD_3_0FC7_REG_7. | |
188 | (mod_table): Replace PREFIX_0FC7_REG_6 with | |
189 | PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and | |
190 | PREFIX_MOD_3_0FC7_REG_7. | |
191 | ||
507bd325 L |
192 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
193 | ||
194 | * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. | |
195 | (PREFIX_MANDATORY_REPNZ): Likewise. | |
196 | (PREFIX_MANDATORY_DATA): Likewise. | |
197 | (PREFIX_MANDATORY_ADDR): Likewise. | |
198 | (PREFIX_MANDATORY_LOCK): Likewise. | |
199 | (PREFIX_MANDATORY): Likewise. | |
200 | (PREFIX_UD_SHIFT): Set to 8 | |
201 | (PREFIX_UD_REPZ): Updated. | |
202 | (PREFIX_UD_REPNZ): Likewise. | |
203 | (PREFIX_UD_DATA): Likewise. | |
204 | (PREFIX_UD_ADDR): Likewise. | |
205 | (PREFIX_UD_LOCK): Likewise. | |
206 | (PREFIX_IGNORED_SHIFT): New. | |
207 | (PREFIX_IGNORED_REPZ): Likewise. | |
208 | (PREFIX_IGNORED_REPNZ): Likewise. | |
209 | (PREFIX_IGNORED_DATA): Likewise. | |
210 | (PREFIX_IGNORED_ADDR): Likewise. | |
211 | (PREFIX_IGNORED_LOCK): Likewise. | |
212 | (PREFIX_OPCODE): Likewise. | |
213 | (PREFIX_IGNORED): Likewise. | |
214 | (Bad_Opcode): Replace PREFIX_MANDATORY with 0. | |
215 | (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
216 | (three_byte_table): Likewise. | |
217 | (mod_table): Likewise. | |
218 | (mandatory_prefix): Renamed to ... | |
219 | (prefix_requirement): This. | |
220 | (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
221 | Update PREFIX_90 entry. | |
222 | (get_valid_dis386): Check prefix_requirement to see if a prefix | |
223 | should be ignored. | |
224 | (print_insn): Replace mandatory_prefix with prefix_requirement. | |
225 | ||
f0fba320 RL |
226 | 2015-04-15 Renlin Li <renlin.li@arm.com> |
227 | ||
228 | * arm-dis.c (thumb32_opcodes): Define 'D' format control code, | |
229 | use it for ssat and ssat16. | |
230 | (print_insn_thumb32): Add handle case for 'D' control code. | |
231 | ||
bf890a93 IT |
232 | 2015-04-06 Ilya Tocar <ilya.tocar@intel.com> |
233 | H.J. Lu <hongjiu.lu@intel.com> | |
234 | ||
235 | * i386-dis-evex.h (evex_table): Fill prefix_requirement field. | |
236 | * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, | |
237 | PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, | |
238 | PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, | |
239 | PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. | |
240 | (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): | |
241 | Fill prefix_requirement field. | |
242 | (struct dis386): Add prefix_requirement field. | |
243 | (dis386): Fill prefix_requirement field. | |
244 | (dis386_twobyte): Ditto. | |
245 | (twobyte_has_mandatory_prefix_: Remove. | |
246 | (reg_table): Fill prefix_requirement field. | |
247 | (prefix_table): Ditto. | |
248 | (x86_64_table): Ditto. | |
249 | (three_byte_table): Ditto. | |
250 | (xop_table): Ditto. | |
251 | (vex_table): Ditto. | |
252 | (vex_len_table): Ditto. | |
253 | (vex_w_table): Ditto. | |
254 | (mod_table): Ditto. | |
255 | (bad_opcode): Ditto. | |
256 | (print_insn): Use prefix_requirement. | |
257 | (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, | |
258 | FGRPde_3, FGRPdf_4): Fill prefix_requirement field. | |
259 | (float_reg): Ditto. | |
260 | ||
2f783c1f MF |
261 | 2015-03-30 Mike Frysinger <vapier@gentoo.org> |
262 | ||
263 | * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. | |
264 | ||
b9d94d62 L |
265 | 2015-03-29 H.J. Lu <hongjiu.lu@intel.com> |
266 | ||
267 | * Makefile.in: Regenerated. | |
268 | ||
27c49e9a AB |
269 | 2015-03-25 Anton Blanchard <anton@samba.org> |
270 | ||
271 | * ppc-dis.c (disassemble_init_powerpc): Only initialise | |
272 | powerpc_opcd_indices and vle_opcd_indices once. | |
273 | ||
c4e676f1 AB |
274 | 2015-03-25 Anton Blanchard <anton@samba.org> |
275 | ||
276 | * ppc-opc.c (powerpc_opcodes): Add slbfee. | |
277 | ||
823d2571 TG |
278 | 2015-03-24 Terry Guo <terry.guo@arm.com> |
279 | ||
280 | * arm-dis.c (opcode32): Updated to use new arm feature struct. | |
281 | (opcode16): Likewise. | |
282 | (coprocessor_opcodes): Replace bit with feature struct. | |
283 | (neon_opcodes): Likewise. | |
284 | (arm_opcodes): Likewise. | |
285 | (thumb_opcodes): Likewise. | |
286 | (thumb32_opcodes): Likewise. | |
287 | (print_insn_coprocessor): Likewise. | |
288 | (print_insn_arm): Likewise. | |
289 | (select_arm_features): Follow new feature struct. | |
290 | ||
029f3522 GG |
291 | 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> |
292 | ||
293 | * i386-dis.c (rm_table): Add clzero. | |
294 | * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. | |
295 | Add CPU_CLZERO_FLAGS. | |
296 | (cpu_flags): Add CpuCLZERO. | |
297 | * i386-opc.h: Add CpuCLZERO. | |
298 | * i386-opc.tbl: Add clzero. | |
299 | * i386-init.h: Re-generated. | |
300 | * i386-tbl.h: Re-generated. | |
301 | ||
6914869a AB |
302 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
303 | ||
304 | * mips-opc.c (decode_mips_operand): Fix constraint issues | |
305 | with u and y operands. | |
306 | ||
21e20815 AB |
307 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
308 | ||
309 | * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. | |
310 | ||
6b1d7593 AK |
311 | 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
312 | ||
313 | * s390-opc.c: Add new IBM z13 instructions. | |
314 | * s390-opc.txt: Likewise. | |
315 | ||
c8f89a34 JW |
316 | 2015-03-10 Renlin Li <renlin.li@arm.com> |
317 | ||
318 | * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, | |
319 | stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and | |
320 | related alias. | |
321 | * aarch64-asm-2.c: Regenerate. | |
322 | * aarch64-dis-2.c: Likewise. | |
323 | * aarch64-opc-2.c: Likewise. | |
324 | ||
d8282f0e JW |
325 | 2015-03-03 Jiong Wang <jiong.wang@arm.com> |
326 | ||
327 | * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. | |
328 | ||
ac994365 OE |
329 | 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org> |
330 | ||
331 | * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of | |
332 | arch_sh_up. | |
333 | (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of | |
334 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. | |
335 | ||
fd63f640 V |
336 | 2015-02-23 Vinay <Vinay.G@kpit.com> |
337 | ||
338 | * rl78-decode.opc (MOV): Added space between two operands for | |
339 | 'mov' instruction in index addressing mode. | |
340 | * rl78-decode.c: Regenerate. | |
341 | ||
f63c1776 PA |
342 | 2015-02-19 Pedro Alves <palves@redhat.com> |
343 | ||
344 | * microblaze-dis.h [__cplusplus]: Wrap in extern "C". | |
345 | ||
07774fcc PA |
346 | 2015-02-10 Pedro Alves <palves@redhat.com> |
347 | Tom Tromey <tromey@redhat.com> | |
348 | ||
349 | * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, | |
350 | microblaze_and, microblaze_xor. | |
351 | * microblaze-opc.h (opcodes): Adjust. | |
352 | ||
3f8107ab AM |
353 | 2015-01-28 James Bowman <james.bowman@ftdichip.com> |
354 | ||
355 | * Makefile.am: Add FT32 files. | |
356 | * configure.ac: Handle FT32. | |
357 | * disassemble.c (disassembler): Call print_insn_ft32. | |
358 | * ft32-dis.c: New file. | |
359 | * ft32-opc.c: New file. | |
360 | * Makefile.in: Regenerate. | |
361 | * configure: Regenerate. | |
362 | * po/POTFILES.in: Regenerate. | |
363 | ||
e5fe4957 KLC |
364 | 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
365 | ||
366 | * nds32-asm.c (keyword_sr): Add new system registers. | |
367 | ||
1e2e8c52 AK |
368 | 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
369 | ||
370 | * s390-dis.c (s390_extract_operand): Support vector register | |
371 | operands. | |
372 | (s390_print_insn_with_opcode): Support new operands types and add | |
373 | new handling of optional operands. | |
374 | * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove | |
375 | and include opcode/s390.h instead. | |
376 | (struct op_struct): New field `flags'. | |
377 | (insertOpcode, insertExpandedMnemonic): New parameter `flags'. | |
378 | (dumpTable): Dump flags. | |
379 | (main): Parse flags from the s390-opc.txt file. Add z13 as cpu | |
380 | string. | |
381 | * s390-opc.c: Add new operands types, instruction formats, and | |
382 | instruction masks. | |
383 | (s390_opformats): Add new formats for .insn. | |
384 | * s390-opc.txt: Add new instructions. | |
385 | ||
b90efa5b | 386 | 2015-01-01 Alan Modra <amodra@gmail.com> |
bffb6004 | 387 | |
b90efa5b | 388 | Update year range in copyright notice of all files. |
bffb6004 | 389 | |
b90efa5b | 390 | For older changes see ChangeLog-2014 |
252b5132 | 391 | \f |
b90efa5b | 392 | Copyright (C) 2015 Free Software Foundation, Inc. |
752937aa NC |
393 | |
394 | Copying and distribution of this file, with or without modification, | |
395 | are permitted in any medium without royalty provided the copyright | |
396 | notice and this notice are preserved. | |
397 | ||
252b5132 | 398 | Local Variables: |
2f6d2f85 NC |
399 | mode: change-log |
400 | left-margin: 8 | |
401 | fill-column: 74 | |
252b5132 RH |
402 | version-control: never |
403 | End: |