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Commit | Line | Data |
---|---|---|
24b368f8 CZ |
1 | 2015-12-04 Claudiu Zissulescu <claziss@synopsys.com> |
2 | ||
3 | * arc-dis.c (special_flag_p): Match full mnemonic. | |
4 | * arc-opc.c (print_insn_arc): Check section size to read | |
5 | appropriate number of bytes. Fix printing. | |
6 | * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without | |
7 | arguments. | |
8 | ||
3395762e AV |
9 | 2015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com> |
10 | ||
11 | * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo... | |
12 | <ldah>: ... to this. | |
13 | ||
622b9eb1 MW |
14 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
15 | ||
16 | * aarch64-asm-2.c: Regenerate. | |
17 | * aarch64-dis-2.c: Regenerate. | |
18 | * aarch64-opc-2.c: Regenerate. | |
19 | * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New. | |
20 | (QL_INT2FP_H, QL_FP2INT_H): New. | |
21 | (QL_FP2_H, QL_FP3_H, QL_FP4_H): New | |
22 | (QL_DST_H): New. | |
23 | (QL_FCCMP_H): New. | |
24 | (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf, | |
25 | fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau, | |
26 | fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp, | |
27 | fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm, | |
28 | frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax, | |
29 | fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and | |
30 | fcsel. | |
31 | ||
cf86120b MW |
32 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
33 | ||
34 | * aarch64-opc.c (half_conv_t): New. | |
35 | (expand_fp_imm): Replace is_dp flag with the parameter size to | |
36 | specify the number of bytes for the required expansion. Treat | |
37 | a 16-bit expansion like a 32-bit expansion. Add check for an | |
38 | unsupported size request. Update comment. | |
39 | (aarch64_print_operand): Update to support 16-bit floating point | |
40 | values. Update for changes to expand_fp_imm. | |
41 | ||
3bd894a7 MW |
42 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
43 | ||
44 | * aarch64-tbl.h (aarch64_feature_fp_f16): New. | |
45 | (FP_F16): New. | |
46 | ||
64357d2e MW |
47 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
48 | ||
49 | * aarch64-asm-2.c: Regenerate. | |
50 | * aarch64-dis-2.c: Regenerate. | |
51 | * aarch64-opc-2.c: Regenerate. | |
52 | * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add | |
53 | "rev64". | |
54 | ||
d685192a MW |
55 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
56 | ||
57 | * aarch64-asm-2.c: Regenerate. | |
58 | * aarch64-asm.c (convert_bfc_to_bfm): New. | |
59 | (convert_to_real): Add case for OP_BFC. | |
60 | * aarch64-dis-2.c: Regenerate. | |
61 | * aarch64-dis.c: (convert_bfm_to_bfc): New. | |
62 | (convert_to_alias): Add case for OP_BFC. | |
63 | * aarch64-opc-2.c: Regenerate. | |
64 | * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert | |
65 | to allow width operand in three-operand instructions. | |
66 | * aarch64-tbl.h (QL_BF1): New. | |
67 | (aarch64_feature_v8_2): New. | |
68 | (ARMV8_2): New. | |
69 | (aarch64_opcode_table): Add "bfc". | |
70 | ||
35822b38 MW |
71 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
72 | ||
73 | * aarch64-asm-2.c: Regenerate. | |
74 | * aarch64-dis-2.c: Regenerate. | |
75 | * aarch64-dis.c: Weaken assert. | |
76 | * aarch64-gen.c: Include the instruction in the list of its | |
77 | possible aliases. | |
78 | ||
1a04d1a7 MW |
79 | 2015-11-27 Matthew Wahab <matthew.wahab@arm.com> |
80 | ||
81 | * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1". | |
82 | (aarch64_sys_reg_supported_p): Add ARMv8.2 system register | |
83 | feature test. | |
84 | ||
e49d43ff TG |
85 | 2015-11-23 Tristan Gingold <gingold@adacore.com> |
86 | ||
87 | * arm-dis.c (print_insn): Also set is_thumb for Mach-O. | |
88 | ||
250aafa4 MW |
89 | 2015-11-20 Matthew Wahab <matthew.wahab@arm.com> |
90 | ||
91 | * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12, | |
92 | sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12, | |
93 | tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12, | |
94 | amair_el12, vbar_el12, contextidr_el2, contextidr_el12, | |
95 | cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02, | |
96 | cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2, | |
97 | cnthv_ctl_el2, cnthv_cval_el2. | |
98 | (aarch64_sys_reg_supported_p): Update for the new system | |
99 | registers. | |
100 | ||
a915c10f NC |
101 | 2015-11-20 Nick Clifton <nickc@redhat.com> |
102 | ||
103 | PR binutils/19224 | |
104 | * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause. | |
105 | ||
f8c2a965 NC |
106 | 2015-11-20 Nick Clifton <nickc@redhat.com> |
107 | ||
108 | * po/zh_CN.po: Updated simplified Chinese translation. | |
109 | ||
c2825638 MW |
110 | 2015-11-19 Matthew Wahab <matthew.wahab@arm.com> |
111 | ||
112 | * aarch64-opc.c (operand_general_constraint_met_p): Check validity | |
113 | of MSR PAN immediate operand. | |
114 | ||
e7286c56 NC |
115 | 2015-11-16 Nick Clifton <nickc@redhat.com> |
116 | ||
117 | * rx-dis.c (condition_names): Replace always and never with | |
118 | invalid, since the always/never conditions can never be legal. | |
119 | ||
d8bd95ef TG |
120 | 2015-11-13 Tristan Gingold <gingold@adacore.com> |
121 | ||
122 | * configure: Regenerate. | |
123 | ||
a680de9a PB |
124 | 2015-11-11 Alan Modra <amodra@gmail.com> |
125 | Peter Bergner <bergner@vnet.ibm.com> | |
126 | ||
127 | * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries. | |
128 | Add PPC_OPCODE_VSX3 to the vsx entry. | |
129 | (powerpc_init_dialect): Set default dialect to power9. | |
130 | * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd, | |
131 | insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1, | |
132 | extract_l1 insert_xtq6, extract_xtq6): New static functions. | |
133 | (insert_esync): Test for illegal L operand value. | |
134 | (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6, | |
135 | XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA, | |
136 | XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK, | |
137 | XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3, | |
138 | PPCVSX3): New defines. | |
139 | (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu, | |
140 | fcmpo, ftdiv, ftsqrt>: Use XBF_MASK. | |
141 | <mcrxr>: Use XBFRARB_MASK. | |
142 | <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq., | |
143 | bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc., | |
144 | cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first, | |
145 | cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx, | |
146 | lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll, | |
147 | lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw, | |
148 | modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last, | |
149 | rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx, | |
150 | stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx, | |
151 | subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh, | |
152 | vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh., | |
153 | vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd, | |
154 | vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d, | |
155 | vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx, | |
156 | vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq, | |
157 | vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd, | |
158 | vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait, | |
159 | xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp, | |
160 | xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp, | |
161 | xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz, | |
162 | xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp, | |
163 | xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp, | |
164 | xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo, | |
165 | xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo, | |
166 | xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo, | |
167 | xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp, | |
168 | xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp, | |
169 | xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp, | |
170 | xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw, | |
171 | xxinsertw, xxperm, xxpermr, xxspltib>: New instructions. | |
172 | <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9. | |
173 | <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands. | |
174 | ||
854eb72b NC |
175 | 2015-11-02 Nick Clifton <nickc@redhat.com> |
176 | ||
177 | * rx-decode.opc (rx_decode_opcode): Decode extra NOP | |
178 | instructions. | |
179 | * rx-decode.c: Regenerate. | |
180 | ||
e292aa7a NC |
181 | 2015-11-02 Nick Clifton <nickc@redhat.com> |
182 | ||
183 | * rx-decode.opc (rx_disp): If the displacement is zero, set the | |
184 | type to RX_Operand_Zero_Indirect. | |
185 | * rx-decode.c: Regenerate. | |
186 | * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect. | |
187 | ||
43cdf5ae YQ |
188 | 2015-10-28 Yao Qi <yao.qi@linaro.org> |
189 | ||
190 | * aarch64-dis.c (aarch64_decode_insn): Add one argument | |
191 | noaliases_p. Update comments. Pass noaliases_p rather than | |
192 | no_aliases to aarch64_opcode_decode. | |
193 | (print_insn_aarch64_word): Pass no_aliases to | |
194 | aarch64_decode_insn. | |
195 | ||
c2f28758 VK |
196 | 2015-10-27 Vinay <Vinay.G@kpit.com> |
197 | ||
198 | PR binutils/19159 | |
199 | * rl78-decode.opc (MOV): Added offset to DE register in index | |
200 | addressing mode. | |
201 | * rl78-decode.c: Regenerate. | |
202 | ||
46662804 VK |
203 | 2015-10-27 Vinay Kumar <vinay.g@kpit.com> |
204 | ||
205 | PR binutils/19158 | |
206 | * rl78-decode.opc: Add 's' print operator to instructions that | |
207 | access system registers. | |
208 | * rl78-decode.c: Regenerate. | |
209 | * rl78-dis.c (print_insn_rl78_common): Decode all system | |
210 | registers. | |
211 | ||
02f12cd4 VK |
212 | 2015-10-27 Vinay Kumar <vinay.g@kpit.com> |
213 | ||
214 | PR binutils/19157 | |
215 | * rl78-decode.opc: Add 'a' print operator to mov instructions | |
216 | using stack pointer plus index addressing. | |
217 | * rl78-decode.c: Regenerate. | |
218 | ||
485f23cf AK |
219 | 2015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
220 | ||
221 | * s390-opc.c: Fix comment. | |
222 | * s390-opc.txt: Change instruction type for troo, trot, trto, and | |
223 | trtt to RRF_U0RER since the second parameter does not need to be a | |
224 | register pair. | |
225 | ||
3f94e60d NC |
226 | 2015-10-08 Nick Clifton <nickc@redhat.com> |
227 | ||
228 | * arc-dis.c (print_insn_arc): Initiallise insn array. | |
229 | ||
875880c6 YQ |
230 | 2015-10-07 Yao Qi <yao.qi@linaro.org> |
231 | ||
232 | * aarch64-dis.c (aarch64_ext_sysins_op): Access field | |
233 | 'name' rather than 'template'. | |
234 | * aarch64-opc.c (aarch64_print_operand): Likewise. | |
235 | ||
886a2506 NC |
236 | 2015-10-07 Claudiu Zissulescu <claziss@synopsys.com> |
237 | ||
238 | * arc-dis.c: Revamped file for ARC support | |
239 | * arc-dis.h: Likewise. | |
240 | * arc-ext.c: Likewise. | |
241 | * arc-ext.h: Likewise. | |
242 | * arc-opc.c: Likewise. | |
243 | * arc-fxi.h: New file. | |
244 | * arc-regs.h: Likewise. | |
245 | * arc-tbl.h: Likewise. | |
246 | ||
36f4aab1 YQ |
247 | 2015-10-02 Yao Qi <yao.qi@linaro.org> |
248 | ||
249 | * aarch64-dis.c (disas_aarch64_insn): Remove static. Change | |
250 | argument insn type to aarch64_insn. Rename to ... | |
251 | (aarch64_decode_insn): ... it. | |
252 | (print_insn_aarch64_word): Caller updated. | |
253 | ||
7232d389 YQ |
254 | 2015-10-02 Yao Qi <yao.qi@linaro.org> |
255 | ||
256 | * aarch64-dis.c (disas_aarch64_insn): Remove argument PC. | |
257 | (print_insn_aarch64_word): Caller updated. | |
258 | ||
7ecc513a DV |
259 | 2015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com> |
260 | ||
261 | * s390-mkopc.c (main): Parse htm and vx flag. | |
262 | * s390-opc.txt: Mark instructions from the hardware transactional | |
263 | memory and vector facilities with the "htm"/"vx" flag. | |
264 | ||
b08b78e7 NC |
265 | 2015-09-28 Nick Clifton <nickc@redhat.com> |
266 | ||
267 | * po/de.po: Updated German translation. | |
268 | ||
36f7a941 TR |
269 | 2015-09-28 Tom Rix <tom@bumblecow.com> |
270 | ||
271 | * ppc-opc.c (PPC500): Mark some opcodes as invalid | |
272 | ||
b6518b38 NC |
273 | 2015-09-23 Nick Clifton <nickc@redhat.com> |
274 | ||
275 | * bfin-dis.c (fmtconst): Remove unnecessary call to the abs | |
276 | function. | |
277 | * tic30-dis.c (print_branch): Likewise. | |
278 | * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed | |
279 | value before left shifting. | |
280 | * fr30-ibld.c (fr30_cgen_extract_operand): Likewise. | |
281 | * hppa-dis.c (print_insn_hppa): Likewise. | |
282 | * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static | |
283 | array. | |
284 | * msp430-dis.c (msp430_singleoperand): Likewise. | |
285 | (msp430_doubleoperand): Likewise. | |
286 | (print_insn_msp430): Likewise. | |
287 | * nds32-asm.c (parse_operand): Likewise. | |
288 | * sh-opc.h (MASK): Likewise. | |
289 | * v850-dis.c (get_operand_value): Likewise. | |
290 | ||
f04265ec NC |
291 | 2015-09-22 Nick Clifton <nickc@redhat.com> |
292 | ||
293 | * rx-decode.opc (bwl): Use RX_Bad_Size. | |
294 | (sbwl): Likewise. | |
295 | (ubwl): Likewise. Rename to ubw. | |
296 | (uBWL): Rename to uBW. | |
297 | Replace all references to uBWL with uBW. | |
298 | * rx-decode.c: Regenerate. | |
299 | * rx-dis.c (size_names): Add entry for RX_Bad_Size. | |
300 | (opsize_names): Likewise. | |
301 | (print_insn_rx): Detect and report RX_Bad_Size. | |
302 | ||
6dca4fd1 AB |
303 | 2015-09-22 Anton Blanchard <anton@samba.org> |
304 | ||
305 | * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl. | |
306 | ||
38074311 JM |
307 | 2015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com> |
308 | ||
309 | * sparc-dis.c (print_insn_sparc): Handle the privileged register | |
310 | %pmcdper. | |
311 | ||
5f40e14d JS |
312 | 2015-08-24 Jan Stancek <jstancek@redhat.com> |
313 | ||
314 | * i386-dis.c (print_insn): Fix decoding of three byte operands. | |
315 | ||
ab4e4ed5 AF |
316 | 2015-08-21 Alexander Fomin <alexander.fomin@intel.com> |
317 | ||
318 | PR binutils/18257 | |
319 | * i386-dis.c: Use MOD_TABLE for most of mask instructions. | |
320 | (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1, | |
321 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
322 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
323 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
324 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
325 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
326 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
327 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
328 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
329 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
330 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
331 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
332 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
333 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
334 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
335 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
336 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
337 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
338 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
339 | MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0, | |
340 | MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0, | |
341 | MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0, | |
342 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
343 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
344 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
345 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
346 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
347 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
348 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
349 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0. | |
350 | (vex_w_table): Replace terminals with MOD_TABLE entries for | |
351 | most of mask instructions. | |
352 | ||
919b75f7 AM |
353 | 2015-08-17 Alan Modra <amodra@gmail.com> |
354 | ||
355 | * cgen.sh: Trim trailing space from cgen output. | |
356 | * ia64-gen.c (print_dependency_table): Don't generate trailing space. | |
357 | (print_dis_table): Likewise. | |
358 | * opc2c.c (dump_lines): Likewise. | |
359 | (orig_filename): Warning fix. | |
360 | * ia64-asmtab.c: Regenerate. | |
361 | ||
4ab90a7a AV |
362 | 2015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com> |
363 | ||
364 | * arm-dis.c (print_insn_arm): Disassembling for all targets V6 | |
365 | and higher with ARM instruction set will now mark the 26-bit | |
366 | versions of teq,tst,cmn and cmp as UNPREDICTABLE. | |
367 | (arm_opcodes): Fix for unpredictable nop being recognized as a | |
368 | teq. | |
369 | ||
40fc1451 SD |
370 | 2015-08-12 Simon Dardis <simon.dardis@imgtec.com> |
371 | ||
372 | * micromips-opc.c (micromips_opcodes): Re-order table so that move | |
373 | based on 'or' is first. | |
374 | * mips-opc.c (mips_builtin_opcodes): Ditto. | |
375 | ||
922c5db5 NC |
376 | 2015-08-11 Nick Clifton <nickc@redhat.com> |
377 | ||
378 | PR 18800 | |
379 | * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT | |
380 | instruction. | |
381 | ||
75fb7498 RS |
382 | 2015-08-10 Robert Suchanek <robert.suchanek@imgtec.com> |
383 | ||
384 | * mips-opc.c (mips_builtin_opcodes): Add "sigrie". | |
385 | ||
36aed29d AP |
386 | 2015-08-07 Amit Pawar <Amit.Pawar@amd.com> |
387 | ||
388 | * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS. | |
389 | * i386-init.h: Regenerated. | |
390 | ||
a8484f96 L |
391 | 2015-07-30 H.J. Lu <hongjiu.lu@intel.com> |
392 | ||
393 | PR binutils/13571 | |
394 | * i386-dis.c (MOD_0FC3): New. | |
395 | (PREFIX_0FC3): Renamed to ... | |
396 | (PREFIX_MOD_0_0FC3): This. | |
397 | (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3. | |
398 | (prefix_table): Replace Ma with Ev on movntiS. | |
399 | (mod_table): Add MOD_0FC3. | |
400 | ||
37a42ee9 L |
401 | 2015-07-27 H.J. Lu <hongjiu.lu@intel.com> |
402 | ||
403 | * configure: Regenerated. | |
404 | ||
070fe95d AM |
405 | 2015-07-23 Alan Modra <amodra@gmail.com> |
406 | ||
407 | PR 18708 | |
408 | * i386-dis.c (get64): Avoid signed integer overflow. | |
409 | ||
20c2a615 L |
410 | 2015-07-22 Alexander Fomin <alexander.fomin@intel.com> |
411 | ||
412 | PR binutils/18631 | |
413 | * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with | |
414 | "EXEvexHalfBcstXmmq" for the second operand. | |
415 | (EVEX_W_0F79_P_2): Likewise. | |
416 | (EVEX_W_0F7A_P_2): Likewise. | |
417 | (EVEX_W_0F7B_P_2): Likewise. | |
418 | ||
6f1c2142 AM |
419 | 2015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com> |
420 | ||
421 | * arm-dis.c (print_insn_coprocessor): Added support for quarter | |
422 | float bitfield format. | |
423 | (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new | |
424 | quarter float bitfield format. | |
425 | ||
8a643cc3 L |
426 | 2015-07-14 H.J. Lu <hongjiu.lu@intel.com> |
427 | ||
428 | * configure: Regenerated. | |
429 | ||
ef5a96d5 AM |
430 | 2015-07-03 Alan Modra <amodra@gmail.com> |
431 | ||
432 | * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*. | |
433 | * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add | |
434 | PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry. | |
435 | ||
c8c8175b SL |
436 | 2015-07-01 Sandra Loosemore <sandra@codesourcery.com> |
437 | Cesar Philippidis <cesar@codesourcery.com> | |
438 | ||
439 | * nios2-dis.c (nios2_extract_opcode): New. | |
440 | (nios2_disassembler_state): New. | |
441 | (nios2_find_opcode_hash): Use mach parameter to select correct | |
442 | disassembler state. | |
443 | (nios2_print_insn_arg): Extend to support new R2 argument letters | |
444 | and formats. | |
445 | (print_insn_nios2): Check for 16-bit instruction at end of memory. | |
446 | * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes. | |
447 | (NIOS2_NUM_OPCODES): Rename to... | |
448 | (NIOS2_NUM_R1_OPCODES): This. | |
449 | (nios2_r2_opcodes): New. | |
450 | (NIOS2_NUM_R2_OPCODES): New. | |
451 | (nios2_num_r2_opcodes): New. | |
452 | (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New. | |
453 | (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New. | |
454 | (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New. | |
455 | (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New. | |
456 | (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New. | |
457 | ||
9916071f AP |
458 | 2015-06-30 Amit Pawar <Amit.Pawar@amd.com> |
459 | ||
460 | * i386-dis.c (OP_Mwaitx): New. | |
461 | (rm_table): Add monitorx/mwaitx. | |
462 | * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS | |
463 | and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS. | |
464 | (operand_type_init): Add CpuMWAITX. | |
465 | * i386-opc.h (CpuMWAITX): New. | |
466 | (i386_cpu_flags): Add cpumwaitx. | |
467 | * i386-opc.tbl: Add monitorx and mwaitx. | |
468 | * i386-init.h: Regenerated. | |
469 | * i386-tbl.h: Likewise. | |
470 | ||
7b934113 PB |
471 | 2015-06-22 Peter Bergner <bergner@vnet.ibm.com> |
472 | ||
473 | * ppc-opc.c (insert_ls): Test for invalid LS operands. | |
474 | (insert_esync): New function. | |
475 | (LS, WC): Use insert_ls. | |
476 | (ESYNC): Use insert_esync. | |
477 | ||
bdc4de1b NC |
478 | 2015-06-22 Nick Clifton <nickc@redhat.com> |
479 | ||
480 | * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the | |
481 | requested region lies beyond it. | |
482 | * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when | |
483 | looking for 32-bit insns. | |
484 | * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading | |
485 | data. | |
486 | * sh-dis.c (print_insn_sh): Likewise. | |
487 | * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading | |
488 | blocks of instructions. | |
489 | * vax-dis.c (print_insn_vax): Check that the requested address | |
490 | does not clash with the stop_vma. | |
491 | ||
11a0cf2e PB |
492 | 2015-06-19 Peter Bergner <bergner@vnet.ibm.com> |
493 | ||
070fe95d | 494 | * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value. |
11a0cf2e PB |
495 | * ppc-opc.c (FXM4): Add non-zero optional value. |
496 | (TBR): Likewise. | |
497 | (SXL): Likewise. | |
498 | (insert_fxm): Handle new default operand value. | |
499 | (extract_fxm): Likewise. | |
500 | (insert_tbr): Likewise. | |
501 | (extract_tbr): Likewise. | |
502 | ||
bdfa8b95 MW |
503 | 2015-06-16 Matthew Wahab <matthew.wahab@arm.com> |
504 | ||
505 | * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1". | |
506 | ||
24b4cf66 SN |
507 | 2015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com> |
508 | ||
509 | * arm-dis.c (print_insn_coprocessor): Avoid negative shift. | |
510 | ||
99a2c561 PB |
511 | 2015-06-12 Peter Bergner <bergner@vnet.ibm.com> |
512 | ||
513 | * ppc-opc.c: Add comment accidentally removed by old commit. | |
514 | (MTMSRD_L): Delete. | |
515 | ||
40f77f82 AM |
516 | 2015-06-04 Peter Bergner <bergner@vnet.ibm.com> |
517 | ||
518 | * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic. | |
519 | ||
13be46a2 NC |
520 | 2015-06-04 Nick Clifton <nickc@redhat.com> |
521 | ||
522 | PR 18474 | |
523 | * msp430-dis.c (msp430_nooperands): Fix check for emulated insns. | |
524 | ||
ddfded2f MW |
525 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
526 | ||
527 | * arm-dis.c (arm_opcodes): Add "setpan". | |
528 | (thumb_opcodes): Add "setpan". | |
529 | ||
1af1dd51 MW |
530 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
531 | ||
532 | * arm-dis.c (select_arm_features): Rework to avoid used of redefined | |
533 | macros. | |
534 | ||
9e1f0fa7 MW |
535 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
536 | ||
537 | * aarch64-tbl.h (aarch64_feature_rdma): New. | |
538 | (RDMA): New. | |
539 | (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions. | |
540 | * aarch64-asm-2.c: Regenerate. | |
541 | * aarch64-dis-2.c: Regenerate. | |
542 | * aarch64-opc-2.c: Regenerate. | |
543 | ||
290806fd MW |
544 | 2015-06-02 Matthew Wahab <matthew.wahab@arm.com> |
545 | ||
546 | * aarch64-tbl.h (aarch64_feature_lor): New. | |
547 | (LOR): New. | |
548 | (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr", | |
549 | "stllrb", "stllrh". | |
550 | * aarch64-asm-2.c: Regenerate. | |
551 | * aarch64-dis-2.c: Regenerate. | |
552 | * aarch64-opc-2.c: Regenerate. | |
553 | ||
f21cce2c MW |
554 | 2015-06-01 Matthew Wahab <matthew.wahab@arm.com> |
555 | ||
556 | * aarch64-opc.c (F_ARCHEXT): New. | |
557 | (aarch64_sys_regs): Add "pan". | |
558 | (aarch64_sys_reg_supported_p): New. | |
559 | (aarch64_pstatefields): Add "pan". | |
560 | (aarch64_pstatefield_supported_p): New. | |
561 | ||
d194d186 JB |
562 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
563 | ||
564 | * i386-tbl.h: Regenerate. | |
565 | ||
3a8547d2 JB |
566 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
567 | ||
568 | * i386-dis.c (print_insn): Swap rounding mode specifier and | |
569 | general purpose register in Intel mode. | |
570 | ||
015c54d5 JB |
571 | 2015-06-01 Jan Beulich <jbeulich@suse.com> |
572 | ||
573 | * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}. | |
574 | * i386-tbl.h: Regenerate. | |
575 | ||
071f0063 L |
576 | 2015-05-18 H.J. Lu <hongjiu.lu@intel.com> |
577 | ||
578 | * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp. | |
579 | * i386-init.h: Regenerated. | |
580 | ||
5db04b09 L |
581 | 2015-05-15 H.J. Lu <hongjiu.lu@intel.com> |
582 | ||
583 | PR binutis/18386 | |
584 | * i386-dis.c: Add comments for '@'. | |
585 | (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9. | |
586 | (enum x86_64_isa): New. | |
587 | (isa64): Likewise. | |
588 | (print_i386_disassembler_options): Add amd64 and intel64. | |
589 | (print_insn): Handle amd64 and intel64. | |
590 | (putop): Handle '@'. | |
591 | (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit. | |
592 | * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64. | |
593 | * i386-opc.h (AMD64): New. | |
594 | (CpuIntel64): Likewise. | |
595 | (i386_cpu_flags): Add cpuamd64 and cpuintel64. | |
596 | * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64. | |
597 | Mark direct call/jmp without Disp16|Disp32 as Intel64. | |
598 | * i386-init.h: Regenerated. | |
599 | * i386-tbl.h: Likewise. | |
600 | ||
4bc0608a PB |
601 | 2015-05-14 Peter Bergner <bergner@vnet.ibm.com> |
602 | ||
603 | * ppc-opc.c (IH) New define. | |
604 | (powerpc_opcodes) <wait>: Do not enable for POWER7. | |
605 | <tlbie>: Add RS operand for POWER7. | |
606 | <slbia>: Add IH operand for POWER6. | |
607 | ||
70cead07 L |
608 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
609 | ||
610 | * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit | |
611 | direct branch. | |
612 | (jmp): Likewise. | |
613 | * i386-tbl.h: Regenerated. | |
614 | ||
7b6d09fb L |
615 | 2015-05-11 H.J. Lu <hongjiu.lu@intel.com> |
616 | ||
617 | * configure.ac: Support bfd_iamcu_arch. | |
618 | * disassemble.c (disassembler): Support bfd_iamcu_arch. | |
619 | * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and | |
620 | CPU_IAMCU_COMPAT_FLAGS. | |
621 | (cpu_flags): Add CpuIAMCU. | |
622 | * i386-opc.h (CpuIAMCU): New. | |
623 | (i386_cpu_flags): Add cpuiamcu. | |
624 | * configure: Regenerated. | |
625 | * i386-init.h: Likewise. | |
626 | * i386-tbl.h: Likewise. | |
627 | ||
31955f99 L |
628 | 2015-05-08 H.J. Lu <hongjiu.lu@intel.com> |
629 | ||
630 | PR binutis/18386 | |
631 | * i386-dis.c (X86_64_E8): New. | |
632 | (X86_64_E9): Likewise. | |
633 | Update comments on 'T', 'U', 'V'. Add comments for '^'. | |
634 | (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9. | |
635 | (x86_64_table): Add X86_64_E8 and X86_64_E9. | |
636 | (mod_table): Replace {T|} with ^ on Jcall/Jmp. | |
637 | (putop): Handle '^'. | |
638 | (OP_J): Ignore the operand size prefix in 64-bit. Don't check | |
639 | REX_W. | |
640 | ||
0952813b DD |
641 | 2015-04-30 DJ Delorie <dj@redhat.com> |
642 | ||
643 | * disassemble.c (disassembler): Choose suitable disassembler based | |
644 | on E_ABI. | |
645 | * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use | |
646 | it to decode mul/div insns. | |
647 | * rl78-decode.c: Regenerate. | |
648 | * rl78-dis.c (print_insn_rl78): Rename to... | |
649 | (print_insn_rl78_common): ...this, take ISA parameter. | |
650 | (print_insn_rl78): New. | |
651 | (print_insn_rl78_g10): New. | |
652 | (print_insn_rl78_g13): New. | |
653 | (print_insn_rl78_g14): New. | |
654 | (rl78_get_disassembler): New. | |
655 | ||
f9d3ecaa NC |
656 | 2015-04-29 Nick Clifton <nickc@redhat.com> |
657 | ||
658 | * po/fr.po: Updated French translation. | |
659 | ||
4fff86c5 PB |
660 | 2015-04-27 Peter Bergner <bergner@vnet.ibm.com> |
661 | ||
662 | * ppc-opc.c (DCBT_EO): New define. | |
663 | (powerpc_opcodes) <lbarx>: Enable for POWER8 and later. | |
664 | <lharx>: Likewise. | |
665 | <stbcx.>: Likewise. | |
666 | <sthcx.>: Likewise. | |
667 | <waitrsv>: Do not enable for POWER7 and later. | |
668 | <waitimpl>: Likewise. | |
669 | <dcbt>: Default to the two operand form of the instruction for all | |
670 | "old" cpus. For "new" cpus, use the operand ordering that matches | |
671 | whether the cpu is server or embedded. | |
672 | <dcbtst>: Likewise. | |
673 | ||
3b78cfe1 AK |
674 | 2015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
675 | ||
676 | * s390-opc.c: New instruction type VV0UU2. | |
677 | * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK, | |
678 | and WFC. | |
679 | ||
04d824a4 JB |
680 | 2015-04-23 Jan Beulich <jbeulich@suse.com> |
681 | ||
682 | * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ". | |
683 | * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq, | |
684 | vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY. | |
685 | (vfpclasspd, vfpclassps): Add %XZ. | |
686 | ||
09708981 L |
687 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
688 | ||
689 | * i386-dis.c (PREFIX_UD_SHIFT): Removed. | |
690 | (PREFIX_UD_REPZ): Likewise. | |
691 | (PREFIX_UD_REPNZ): Likewise. | |
692 | (PREFIX_UD_DATA): Likewise. | |
693 | (PREFIX_UD_ADDR): Likewise. | |
694 | (PREFIX_UD_LOCK): Likewise. | |
695 | ||
3888916d L |
696 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
697 | ||
698 | * i386-dis.c (prefix_requirement): Removed. | |
699 | (print_insn): Don't set prefix_requirement. Check | |
700 | dp->prefix_requirement instead of prefix_requirement. | |
701 | ||
f24bcbaa L |
702 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
703 | ||
704 | PR binutils/17898 | |
705 | * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ... | |
706 | (PREFIX_MOD_0_0FC7_REG_6): This. | |
707 | (PREFIX_MOD_3_0FC7_REG_6): New. | |
708 | (PREFIX_MOD_3_0FC7_REG_7): Likewise. | |
709 | (prefix_table): Replace PREFIX_0FC7_REG_6 with | |
710 | PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and | |
711 | PREFIX_MOD_3_0FC7_REG_7. | |
712 | (mod_table): Replace PREFIX_0FC7_REG_6 with | |
713 | PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and | |
714 | PREFIX_MOD_3_0FC7_REG_7. | |
715 | ||
507bd325 L |
716 | 2015-04-15 H.J. Lu <hongjiu.lu@intel.com> |
717 | ||
718 | * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed. | |
719 | (PREFIX_MANDATORY_REPNZ): Likewise. | |
720 | (PREFIX_MANDATORY_DATA): Likewise. | |
721 | (PREFIX_MANDATORY_ADDR): Likewise. | |
722 | (PREFIX_MANDATORY_LOCK): Likewise. | |
723 | (PREFIX_MANDATORY): Likewise. | |
724 | (PREFIX_UD_SHIFT): Set to 8 | |
725 | (PREFIX_UD_REPZ): Updated. | |
726 | (PREFIX_UD_REPNZ): Likewise. | |
727 | (PREFIX_UD_DATA): Likewise. | |
728 | (PREFIX_UD_ADDR): Likewise. | |
729 | (PREFIX_UD_LOCK): Likewise. | |
730 | (PREFIX_IGNORED_SHIFT): New. | |
731 | (PREFIX_IGNORED_REPZ): Likewise. | |
732 | (PREFIX_IGNORED_REPNZ): Likewise. | |
733 | (PREFIX_IGNORED_DATA): Likewise. | |
734 | (PREFIX_IGNORED_ADDR): Likewise. | |
735 | (PREFIX_IGNORED_LOCK): Likewise. | |
736 | (PREFIX_OPCODE): Likewise. | |
737 | (PREFIX_IGNORED): Likewise. | |
738 | (Bad_Opcode): Replace PREFIX_MANDATORY with 0. | |
739 | (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
740 | (three_byte_table): Likewise. | |
741 | (mod_table): Likewise. | |
742 | (mandatory_prefix): Renamed to ... | |
743 | (prefix_requirement): This. | |
744 | (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE. | |
745 | Update PREFIX_90 entry. | |
746 | (get_valid_dis386): Check prefix_requirement to see if a prefix | |
747 | should be ignored. | |
748 | (print_insn): Replace mandatory_prefix with prefix_requirement. | |
749 | ||
f0fba320 RL |
750 | 2015-04-15 Renlin Li <renlin.li@arm.com> |
751 | ||
752 | * arm-dis.c (thumb32_opcodes): Define 'D' format control code, | |
753 | use it for ssat and ssat16. | |
754 | (print_insn_thumb32): Add handle case for 'D' control code. | |
755 | ||
bf890a93 IT |
756 | 2015-04-06 Ilya Tocar <ilya.tocar@intel.com> |
757 | H.J. Lu <hongjiu.lu@intel.com> | |
758 | ||
759 | * i386-dis-evex.h (evex_table): Fill prefix_requirement field. | |
760 | * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ, | |
761 | PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK, | |
762 | PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA, | |
763 | PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define. | |
764 | (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX): | |
765 | Fill prefix_requirement field. | |
766 | (struct dis386): Add prefix_requirement field. | |
767 | (dis386): Fill prefix_requirement field. | |
768 | (dis386_twobyte): Ditto. | |
769 | (twobyte_has_mandatory_prefix_: Remove. | |
770 | (reg_table): Fill prefix_requirement field. | |
771 | (prefix_table): Ditto. | |
772 | (x86_64_table): Ditto. | |
773 | (three_byte_table): Ditto. | |
774 | (xop_table): Ditto. | |
775 | (vex_table): Ditto. | |
776 | (vex_len_table): Ditto. | |
777 | (vex_w_table): Ditto. | |
778 | (mod_table): Ditto. | |
779 | (bad_opcode): Ditto. | |
780 | (print_insn): Use prefix_requirement. | |
781 | (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4, | |
782 | FGRPde_3, FGRPdf_4): Fill prefix_requirement field. | |
783 | (float_reg): Ditto. | |
784 | ||
2f783c1f MF |
785 | 2015-03-30 Mike Frysinger <vapier@gentoo.org> |
786 | ||
787 | * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype. | |
788 | ||
b9d94d62 L |
789 | 2015-03-29 H.J. Lu <hongjiu.lu@intel.com> |
790 | ||
791 | * Makefile.in: Regenerated. | |
792 | ||
27c49e9a AB |
793 | 2015-03-25 Anton Blanchard <anton@samba.org> |
794 | ||
795 | * ppc-dis.c (disassemble_init_powerpc): Only initialise | |
796 | powerpc_opcd_indices and vle_opcd_indices once. | |
797 | ||
c4e676f1 AB |
798 | 2015-03-25 Anton Blanchard <anton@samba.org> |
799 | ||
800 | * ppc-opc.c (powerpc_opcodes): Add slbfee. | |
801 | ||
823d2571 TG |
802 | 2015-03-24 Terry Guo <terry.guo@arm.com> |
803 | ||
804 | * arm-dis.c (opcode32): Updated to use new arm feature struct. | |
805 | (opcode16): Likewise. | |
806 | (coprocessor_opcodes): Replace bit with feature struct. | |
807 | (neon_opcodes): Likewise. | |
808 | (arm_opcodes): Likewise. | |
809 | (thumb_opcodes): Likewise. | |
810 | (thumb32_opcodes): Likewise. | |
811 | (print_insn_coprocessor): Likewise. | |
812 | (print_insn_arm): Likewise. | |
813 | (select_arm_features): Follow new feature struct. | |
814 | ||
029f3522 GG |
815 | 2015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com> |
816 | ||
817 | * i386-dis.c (rm_table): Add clzero. | |
818 | * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS. | |
819 | Add CPU_CLZERO_FLAGS. | |
820 | (cpu_flags): Add CpuCLZERO. | |
821 | * i386-opc.h: Add CpuCLZERO. | |
822 | * i386-opc.tbl: Add clzero. | |
823 | * i386-init.h: Re-generated. | |
824 | * i386-tbl.h: Re-generated. | |
825 | ||
6914869a AB |
826 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
827 | ||
828 | * mips-opc.c (decode_mips_operand): Fix constraint issues | |
829 | with u and y operands. | |
830 | ||
21e20815 AB |
831 | 2015-03-13 Andrew Bennett <andrew.bennett@imgtec.com> |
832 | ||
833 | * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions. | |
834 | ||
6b1d7593 AK |
835 | 2015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
836 | ||
837 | * s390-opc.c: Add new IBM z13 instructions. | |
838 | * s390-opc.txt: Likewise. | |
839 | ||
c8f89a34 JW |
840 | 2015-03-10 Renlin Li <renlin.li@arm.com> |
841 | ||
842 | * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb, | |
843 | stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and | |
844 | related alias. | |
845 | * aarch64-asm-2.c: Regenerate. | |
846 | * aarch64-dis-2.c: Likewise. | |
847 | * aarch64-opc-2.c: Likewise. | |
848 | ||
d8282f0e JW |
849 | 2015-03-03 Jiong Wang <jiong.wang@arm.com> |
850 | ||
851 | * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols. | |
852 | ||
ac994365 OE |
853 | 2015-02-25 Oleg Endo <olegendo@gcc.gnu.org> |
854 | ||
855 | * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of | |
856 | arch_sh_up. | |
857 | (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of | |
858 | arch_sh2a_nofpu_or_sh4_nommu_nofpu_up. | |
859 | ||
fd63f640 V |
860 | 2015-02-23 Vinay <Vinay.G@kpit.com> |
861 | ||
862 | * rl78-decode.opc (MOV): Added space between two operands for | |
863 | 'mov' instruction in index addressing mode. | |
864 | * rl78-decode.c: Regenerate. | |
865 | ||
f63c1776 PA |
866 | 2015-02-19 Pedro Alves <palves@redhat.com> |
867 | ||
868 | * microblaze-dis.h [__cplusplus]: Wrap in extern "C". | |
869 | ||
07774fcc PA |
870 | 2015-02-10 Pedro Alves <palves@redhat.com> |
871 | Tom Tromey <tromey@redhat.com> | |
872 | ||
873 | * microblaze-opcm.h (or, and, xor): Rename to microblaze_or, | |
874 | microblaze_and, microblaze_xor. | |
875 | * microblaze-opc.h (opcodes): Adjust. | |
876 | ||
3f8107ab AM |
877 | 2015-01-28 James Bowman <james.bowman@ftdichip.com> |
878 | ||
879 | * Makefile.am: Add FT32 files. | |
880 | * configure.ac: Handle FT32. | |
881 | * disassemble.c (disassembler): Call print_insn_ft32. | |
882 | * ft32-dis.c: New file. | |
883 | * ft32-opc.c: New file. | |
884 | * Makefile.in: Regenerate. | |
885 | * configure: Regenerate. | |
886 | * po/POTFILES.in: Regenerate. | |
887 | ||
e5fe4957 KLC |
888 | 2015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
889 | ||
890 | * nds32-asm.c (keyword_sr): Add new system registers. | |
891 | ||
1e2e8c52 AK |
892 | 2015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com> |
893 | ||
894 | * s390-dis.c (s390_extract_operand): Support vector register | |
895 | operands. | |
896 | (s390_print_insn_with_opcode): Support new operands types and add | |
897 | new handling of optional operands. | |
898 | * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove | |
899 | and include opcode/s390.h instead. | |
900 | (struct op_struct): New field `flags'. | |
901 | (insertOpcode, insertExpandedMnemonic): New parameter `flags'. | |
902 | (dumpTable): Dump flags. | |
903 | (main): Parse flags from the s390-opc.txt file. Add z13 as cpu | |
904 | string. | |
905 | * s390-opc.c: Add new operands types, instruction formats, and | |
906 | instruction masks. | |
907 | (s390_opformats): Add new formats for .insn. | |
908 | * s390-opc.txt: Add new instructions. | |
909 | ||
b90efa5b | 910 | 2015-01-01 Alan Modra <amodra@gmail.com> |
bffb6004 | 911 | |
b90efa5b | 912 | Update year range in copyright notice of all files. |
bffb6004 | 913 | |
b90efa5b | 914 | For older changes see ChangeLog-2014 |
252b5132 | 915 | \f |
b90efa5b | 916 | Copyright (C) 2015 Free Software Foundation, Inc. |
752937aa NC |
917 | |
918 | Copying and distribution of this file, with or without modification, | |
919 | are permitted in any medium without royalty provided the copyright | |
920 | notice and this notice are preserved. | |
921 | ||
252b5132 | 922 | Local Variables: |
2f6d2f85 NC |
923 | mode: change-log |
924 | left-margin: 8 | |
925 | fill-column: 74 | |
252b5132 RH |
926 | version-control: never |
927 | End: |