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opcodes: blackfin: fix decoding of all register move insns
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
35fc57f3
MF		 12010-09-22 Mike Frysinger <vapier@gentoo.org>
2
3 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
4
219b747a
MF		 52010-09-22 Robin Getz <robin.getz@analog.com>
6
7 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
8 Reject P6/P7 to TESTSET.
9 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
10 SP onto the stack.
11 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
12 P/D fields match all the time.
13 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
14 are 0 for accumulator compares.
15 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
16 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
17 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
18 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
19 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
20 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
21 insns.
22 (decode_dagMODim_0): Verify br field for IREG ops.
23 (decode_LDST_0): Reject preg load into same preg.
24 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
25 (print_insn_bfin): Likewise.
26
775f1cf0
MF		 272010-09-22 Mike Frysinger <vapier@gentoo.org>
28
29 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
30
0b7691fd
MF		 312010-09-22 Robin Getz <robin.getz@analog.com>
32
33 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
34
b2459327
MF		 352010-09-22 Mike Frysinger <vapier@gentoo.org>
36
37 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
38
50e2162a
MF		 392010-09-22 Robin Getz <robin.getz@analog.com>
40
41 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
42 register values greater than 8.
43 (IS_RESERVEDREG, allreg, mostreg): New helpers.
44 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
45 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
46 (decode_CC2dreg_0): Check valid CC register number.
47
a01eda85
MF		 482010-09-22 Robin Getz <robin.getz@analog.com>
49
50 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
51
22215ae0
MF		 522010-09-22 Robin Getz <robin.getz@analog.com>
53
54 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
55 (reg_names): Likewise.
56 (decode_statbits): Likewise; while reformatting to make manageable.
57
73a63ccf
MF		 582010-09-22 Mike Frysinger <vapier@gentoo.org>
59
60 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
61 (decode_pseudoOChar_0): New function.
62 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
63
59a82d23
MF		 642010-09-22 Robin Getz <robin.getz@analog.com>
65
66 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
67 LSHIFT instead of SHIFT.
68
528c6277
MF		 692010-09-22 Mike Frysinger <vapier@gentoo.org>
70
71 * bfin-dis.c (constant_formats): Constify the whole structure.
72 (fmtconst): Add const to return value.
73 (reg_names): Mark const.
74 (decode_multfunc): Mark s0/s1 as const.
75 (decode_macfunc): Mark a/sop as const.
76
db472d6f
MGD		 772010-09-17 Tejas Belagod <tejas.belagod@arm.com>
78
79 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
80
f6690563
MR		 812010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
82
83 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
84 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
85
8901a3cd
PM		 862010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
87
88 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
89 dlx_insn_type array.
90
d9e3625e
L		 912010-08-31 H.J. Lu <hongjiu.lu@intel.com>
92
93 PR binutils/11960
94 * i386-dis.c (sIv): New.
95 (dis386): Replace Iq with sIv on "pushT".
96 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
97 (x86_64_table): Replace {T|}/{P|} with P.
98 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
99 (OP_sI): Update v_mode. Remove w_mode.
100
f383de66
NF		 1012010-08-27 Nathan Froyd <froydnj@codesourcery.com>
102
103 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
104 on E500 and E500MC.
105
1ab03f4b
L		 1062010-08-17 H.J. Lu <hongjiu.lu@intel.com>
107
108 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
109 prefetchw.
110
22109423
L		 1112010-08-06 Quentin Neill <quentin.neill@amd.com>
112
113 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
114 to processor flags for PENTIUMPRO processors and later.
115 * i386-opc.h (enum): Add CpuNop.
116 (i386_cpu_flags): Add cpunop bit.
117 * i386-opc.tbl: Change nop cpu_flags.
118 * i386-init.h: Regenerated.
119 * i386-tbl.h: Likewise.
120
b49dfb4a
L		 1212010-08-06 Quentin Neill <quentin.neill@amd.com>
122
123 * i386-opc.h (enum): Fix typos in comments.
124
6ca4eb77
AM		 1252010-08-06 Alan Modra <amodra@gmail.com>
126
127 * disassemble.c: Formatting.
128 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
129
92d4d42e
L		 1302010-08-05 H.J. Lu <hongjiu.lu@intel.com>
131
132 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
133 * i386-tbl.h: Regenerated.
134
b414985b
L		 1352010-08-05 H.J. Lu <hongjiu.lu@intel.com>
136
137 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
138
139 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
140 * i386-tbl.h: Regenerated.
141
f9c7014e
DD		 1422010-07-29 DJ Delorie <dj@redhat.com>
143
144 * rx-decode.opc (SRR): New.
145 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
146 r0,r0) and NOP3 (max r0,r0) special cases.
147 * rx-decode.c: Regenerate.
6ca4eb77 148
592a252b
L		 1492010-07-28 H.J. Lu <hongjiu.lu@intel.com>
150
151 * i386-dis.c: Add 0F to VEX opcode enums.
152
3cf79a01
DD		 1532010-07-27 DJ Delorie <dj@redhat.com>
154
155 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
156 (rx_decode_opcode): Likewise.
157 * rx-decode.c: Regenerate.
158
1cd986c5
NC		 1592010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
160 Ina Pandit <ina.pandit@kpitcummins.com>
161
162 * v850-dis.c (v850_sreg_names): Updated structure for system
163 registers.
164 (float_cc_names): new structure for condition codes.
165 (print_value): Update the function that prints value.
166 (get_operand_value): New function to get the operand value.
167 (disassemble): Updated to handle the disassembly of instructions.
168 (print_insn_v850): Updated function to print instruction for different
169 families.
170 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
171 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
172 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
173 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
174 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
175 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
176 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
177 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
178 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
179 (v850_operands): Update with the relocation name. Also update
180 the instructions with specific set of processors.
181
52e7f43d
RE		 1822010-07-08 Tejas Belagod <tejas.belagod@arm.com>
183
184 * arm-dis.c (print_insn_arm): Add cases for printing more
185 symbolic operands.
186 (print_insn_thumb32): Likewise.
187
c680e7f6
MR		 1882010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
189
190 * mips-dis.c (print_insn_mips): Correct branch instruction type
191 determination.
192
9a2c7088
MR		 1932010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
194
195 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
196 type and delay slot determination.
197 (print_insn_mips16): Extend branch instruction type and delay
198 slot determination to cover all instructions.
199 * mips16-opc.c (BR): Remove macro.
200 (UBR, CBR): New macros.
201 (mips16_opcodes): Update branch annotation for "b", "beqz",
202 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
203 and "jrc".
204
d7d9a9f8
L		 2052010-07-05 H.J. Lu <hongjiu.lu@intel.com>
206
207 AVX Programming Reference (June, 2010)
208 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
209 * i386-opc.tbl: Likewise.
210 * i386-tbl.h: Regenerated.
211
77321f53
L		 2122010-07-05 H.J. Lu <hongjiu.lu@intel.com>
213
214 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
215
7102e95e
AS		 2162010-07-03 Andreas Schwab <schwab@linux-m68k.org>
217
218 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
219 ppc_cpu_t before inverting.
3a5530ea
AS		 220 (ppc_parse_cpu): Likewise.
221 (print_insn_powerpc): Likewise.
7102e95e 222
bdc70b4a
AM		 2232010-07-03 Alan Modra <amodra@gmail.com>
224
225 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
226 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
227 (PPC64, MFDEC2): Update.
228 (NON32, NO371): Define.
229 (powerpc_opcode): Update to not use old opcode flags, and avoid
230 -m601 duplicates.
231
21375995
DD		 2322010-07-03 DJ Delorie <dj@delorie.com>
233
234 * m32c-ibld.c: Regenerate.
235
81a0b7e2
AM		 2362010-07-03 Alan Modra <amodra@gmail.com>
237
238 * ppc-opc.c (PWR2COM): Define.
239 (PPCPWR2): Add PPC_OPCODE_COMMON.
240 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
241 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
242 "rac" from -mcom.
243
c7b8aa3a
L		 2442010-07-01 H.J. Lu <hongjiu.lu@intel.com>
245
246 AVX Programming Reference (June, 2010)
247 * i386-dis.c (PREFIX_0FAE_REG_0): New.
248 (PREFIX_0FAE_REG_1): Likewise.
249 (PREFIX_0FAE_REG_2): Likewise.
250 (PREFIX_0FAE_REG_3): Likewise.
251 (PREFIX_VEX_3813): Likewise.
252 (PREFIX_VEX_3A1D): Likewise.
253 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
254 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
255 PREFIX_VEX_3A1D.
256 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
257 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
258 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
259
260 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
261 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
262 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
263
264 * i386-opc.h (CpuXsaveopt): New.
77321f53 265 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 266 (CpuRdRnd): Likewise.
267 (CpuF16C): Likewise.
268 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
269 cpuf16c.
270
271 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
272 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 273 * i386-init.h: Regenerated.
274 * i386-tbl.h: Likewise.
c7b8aa3a 275
09a8ad8d
AM		 2762010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
277
278 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
279 and mtocrf on EFS.
280
360cfc9c
AM		 2812010-06-29 Alan Modra <amodra@gmail.com>
282
283 * maxq-dis.c: Delete file.
284 * Makefile.am: Remove references to maxq.
285 * configure.in: Likewise.
286 * disassemble.c: Likewise.
287 * Makefile.in: Regenerate.
288 * configure: Regenerate.
289 * po/POTFILES.in: Regenerate.
290
dc898d5e
AM		 2912010-06-29 Alan Modra <amodra@gmail.com>
292
293 * mep-dis.c: Regenerate.
294
8e560766
MGD		 2952010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
296
297 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
298
c7e2358a
AM		 2992010-06-27 Alan Modra <amodra@gmail.com>
300
301 * arc-dis.c (arc_sprintf): Delete set but unused variables.
302 (decodeInstr): Likewise.
303 * dlx-dis.c (print_insn_dlx): Likewise.
304 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
305 * maxq-dis.c (check_move, print_insn): Likewise.
306 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
307 * msp430-dis.c (msp430_branchinstr): Likewise.
308 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
309 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
310 * sparc-dis.c (print_insn_sparc): Likewise.
311 * fr30-asm.c: Regenerate.
312 * frv-asm.c: Regenerate.
313 * ip2k-asm.c: Regenerate.
314 * iq2000-asm.c: Regenerate.
315 * lm32-asm.c: Regenerate.
316 * m32c-asm.c: Regenerate.
317 * m32r-asm.c: Regenerate.
318 * mep-asm.c: Regenerate.
319 * mt-asm.c: Regenerate.
320 * openrisc-asm.c: Regenerate.
321 * xc16x-asm.c: Regenerate.
322 * xstormy16-asm.c: Regenerate.
323
6ffe3d99
NC		 3242010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
325
326 PR gas/11673
327 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
328
09ec0d17
NC		 3292010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
330
331 PR binutils/11676
332 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
333
e01d869a
AM		 3342010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
335
336 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
337 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
338 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
339 touch floating point regs and are enabled by COM, PPC or PPCCOM.
340 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
341 Treat lwsync as msync on e500.
342
1f4e4950
MGD		 3432010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
344
345 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
346
9d82ec38
MGD		 3472010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
348
e01d869a 349 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 350 constants is the same on 32-bit and 64-bit hosts.
351
c3a6ea62 3522010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 353
354 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
355 .short directives so that they can be reassembled.
356
9db8dccb
CM		 3572010-05-26 Catherine Moore <clm@codesourcery.com>
358 David Ung <davidu@mips.com>
359
360 * mips-opc.c: Change membership to I1 for instructions ssnop and
361 ehb.
362
dfc8cf43
L		 3632010-05-26 H.J. Lu <hongjiu.lu@intel.com>
364
365 * i386-dis.c (sib): New.
366 (get_sib): Likewise.
367 (print_insn): Call get_sib.
368 OP_E_memory): Use sib.
369
f79e2745
CM		 3702010-05-26 Catherine Moore <clm@codesoourcery.com>
371
372 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
373 * mips-opc.c (I16): Remove.
374 (mips_builtin_op): Reclassify jalx.
375
51b5d4a8
AM		 3762010-05-19 Alan Modra <amodra@gmail.com>
377
378 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
379 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
380
85d4ac0b
AM		 3812010-05-13 Alan Modra <amodra@gmail.com>
382
383 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
384
4547cb56
NC		 3852010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
386
387 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
388 format.
389 (print_insn_thumb16): Add support for new %W format.
390
6540b386
TG		 3912010-05-07 Tristan Gingold <gingold@adacore.com>
392
393 * Makefile.in: Regenerate with automake 1.11.1.
394 * aclocal.m4: Ditto.
395
3e01a7fd
NC		 3962010-05-05 Nick Clifton <nickc@redhat.com>
397
398 * po/es.po: Updated Spanish translation.
399
9c9c98a5
NC		 4002010-04-22 Nick Clifton <nickc@redhat.com>
401
402 * po/opcodes.pot: Updated by the Translation project.
403 * po/vi.po: Updated Vietnamese translation.
404
f07af43e
L		 4052010-04-16 H.J. Lu <hongjiu.lu@intel.com>
406
407 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
408 bits in opcode.
409
3d540e93
NC		 4102010-04-09 Nick Clifton <nickc@redhat.com>
411
412 * i386-dis.c (print_insn): Remove unused variable op.
413 (OP_sI): Remove unused variable mask.
414
397841b5
AM		 4152010-04-07 Alan Modra <amodra@gmail.com>
416
417 * configure: Regenerate.
418
cee62821
PB		 4192010-04-06 Peter Bergner <bergner@vnet.ibm.com>
420
421 * ppc-opc.c (RBOPT): New define.
422 ("dccci"): Enable for PPCA2. Make operands optional.
423 ("iccci"): Likewise. Do not deprecate for PPC476.
424
accf4463
NC		 4252010-04-02 Masaki Muranaka <monaka@monami-software.com>
426
427 * cr16-opc.c (cr16_instruction): Fix typo in comment.
428
40b36596
JM		 4292010-03-25 Joseph Myers <joseph@codesourcery.com>
430
431 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
432 * Makefile.in: Regenerate.
433 * configure.in (bfd_tic6x_arch): New.
434 * configure: Regenerate.
435 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
436 (disassembler): Handle TI C6X.
437 * tic6x-dis.c: New.
438
1985c81c
MF		 4392010-03-24 Mike Frysinger <vapier@gentoo.org>
440
441 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
442
f66187fd
JM		 4432010-03-23 Joseph Myers <joseph@codesourcery.com>
444
445 * dis-buf.c (buffer_read_memory): Give error for reading just
446 before the start of memory.
447
ce7d077e
SP		 4482010-03-22 Sebastian Pop <sebastian.pop@amd.com>
449 Quentin Neill <quentin.neill@amd.com>
450
451 * i386-dis.c (OP_LWP_I): Removed.
452 (reg_table): Do not use OP_LWP_I, use Iq.
453 (OP_LWPCB_E): Remove use of names16.
454 (OP_LWP_E): Same.
455 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
456 should not set the Vex.length bit.
457 * i386-tbl.h: Regenerated.
458
63d0fa4e
AM		 4592010-02-25 Edmar Wienskoski <edmar@freescale.com>
460
461 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
462
c060226a
NC		 4632010-02-24 Nick Clifton <nickc@redhat.com>
464
465 PR binutils/6773
466 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
467 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
468 (thumb32_opcodes): Likewise.
469
ab7875de
NC		 4702010-02-15 Nick Clifton <nickc@redhat.com>
471
472 * po/vi.po: Updated Vietnamese translation.
473
fee1d3e8
DE		 4742010-02-12 Doug Evans <dje@sebabeach.org>
475
476 * lm32-opinst.c: Regenerate.
477
37ec9240
DE		 4782010-02-11 Doug Evans <dje@sebabeach.org>
479
9468ae89
DE		 480 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
481 (print_address): Delete CGEN_PRINT_ADDRESS.
482 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
483 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
484 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
485 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
486
37ec9240
DE		 487 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
488 * frv-desc.c, * frv-desc.h, * frv-opc.c,
489 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
490 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
491 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
492 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
493 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
494 * mep-desc.c, * mep-desc.h, * mep-opc.c,
495 * mt-desc.c, * mt-desc.h, * mt-opc.c,
496 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
497 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
498 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
499
c75ef631
L		 5002010-02-11 H.J. Lu <hongjiu.lu@intel.com>
501
502 * i386-dis.c: Update copyright.
503 * i386-gen.c: Likewise.
504 * i386-opc.h: Likewise.
505 * i386-opc.tbl: Likewise.
506
a683cc34
SP		 5072010-02-10 Quentin Neill <quentin.neill@amd.com>
508 Sebastian Pop <sebastian.pop@amd.com>
509
510 * i386-dis.c (OP_EX_VexImmW): Reintroduced
511 function to handle 5th imm8 operand.
512 (PREFIX_VEX_3A48): Added.
513 (PREFIX_VEX_3A49): Added.
514 (VEX_W_3A48_P_2): Added.
515 (VEX_W_3A49_P_2): Added.
516 (prefix table): Added entries for PREFIX_VEX_3A48
517 and PREFIX_VEX_3A49.
518 (vex table): Added entries for VEX_W_3A48_P_2 and
519 and VEX_W_3A49_P_2.
520 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
521 for Vec_Imm4 operands.
522 * i386-opc.h (enum): Added Vec_Imm4.
523 (i386_operand_type): Added vec_imm4.
524 * i386-opc.tbl: Add entries for vpermilp[ds].
525 * i386-init.h: Regenerated.
526 * i386-tbl.h: Regenerated.
527
cdc51b07
RS		 5282010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
529
530 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
531 and "pwr7". Move "a2" into alphabetical order.
532
ce3d2015
AM		 5332010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
534
535 * ppc-dis.c (ppc_opts): Add titan entry.
536 * ppc-opc.c (TITAN, MULHW): Define.
537 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
538
68339fdf
SP		 5392010-02-03 Quentin Neill <quentin.neill@amd.com>
540
541 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
542 to CPU_BDVER1_FLAGS
543 * i386-init.h: Regenerated.
544
f3d55a94
AG		 5452010-02-03 Anthony Green <green@moxielogic.com>
546
547 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
548 0x0f, and make 0x00 an illegal instruction.
549
b0e28b39
DJ		 5502010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
551
552 * opcodes/arm-dis.c (struct arm_private_data): New.
553 (print_insn_coprocessor, print_insn_arm): Update to use struct
554 arm_private_data.
555 (is_mapping_symbol, get_map_sym_type): New functions.
556 (get_sym_code_type): Check the symbol's section. Do not check
557 mapping symbols.
558 (print_insn): Default to disassembling ARM mode code. Check
559 for mapping symbols separately from other symbols. Use
560 struct arm_private_data.
561
1c480963
L		 5622010-01-28 H.J. Lu <hongjiu.lu@intel.com>
563
564 * i386-dis.c (EXVexWdqScalar): New.
565 (vex_scalar_w_dq_mode): Likewise.
566 (prefix_table): Update entries for PREFIX_VEX_3899,
567 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
568 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
569 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
570 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
571 (intel_operand_size): Handle vex_scalar_w_dq_mode.
572 (OP_EX): Likewise.
573
539f890d
L		 5742010-01-27 H.J. Lu <hongjiu.lu@intel.com>
575
576 * i386-dis.c (XMScalar): New.
577 (EXdScalar): Likewise.
578 (EXqScalar): Likewise.
579 (EXqScalarS): Likewise.
580 (VexScalar): Likewise.
581 (EXdVexScalarS): Likewise.
582 (EXqVexScalarS): Likewise.
583 (XMVexScalar): Likewise.
584 (scalar_mode): Likewise.
585 (d_scalar_mode): Likewise.
586 (d_scalar_swap_mode): Likewise.
587 (q_scalar_mode): Likewise.
588 (q_scalar_swap_mode): Likewise.
589 (vex_scalar_mode): Likewise.
590 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
591 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
592 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
593 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
594 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
595 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
596 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
597 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
598 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
599 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
600 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
601 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
602 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
603 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
604 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
605 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
606 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
607 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
608 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
609 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
610 q_scalar_mode, q_scalar_swap_mode.
611 (OP_XMM): Handle scalar_mode.
612 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
613 and q_scalar_swap_mode.
614 (OP_VEX): Handle vex_scalar_mode.
615
208b4d78
L		 6162010-01-24 H.J. Lu <hongjiu.lu@intel.com>
617
618 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
619
448b213a
L		 6202010-01-24 H.J. Lu <hongjiu.lu@intel.com>
621
622 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
623
47cf8fa0
L		 6242010-01-24 H.J. Lu <hongjiu.lu@intel.com>
625
626 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
627
592d1631
L		 6282010-01-24 H.J. Lu <hongjiu.lu@intel.com>
629
630 * i386-dis.c (Bad_Opcode): New.
631 (bad_opcode): Likewise.
632 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
633 (dis386_twobyte): Likewise.
634 (reg_table): Likewise.
635 (prefix_table): Likewise.
636 (x86_64_table): Likewise.
637 (vex_len_table): Likewise.
638 (vex_w_table): Likewise.
639 (mod_table): Likewise.
640 (rm_table): Likewise.
641 (float_reg): Likewise.
642 (reg_table): Remove trailing "(bad)" entries.
643 (prefix_table): Likewise.
644 (x86_64_table): Likewise.
645 (vex_len_table): Likewise.
646 (vex_w_table): Likewise.
647 (mod_table): Likewise.
648 (rm_table): Likewise.
649 (get_valid_dis386): Handle bytemode 0.
650
712366da
L		 6512010-01-23 H.J. Lu <hongjiu.lu@intel.com>
652
653 * i386-opc.h (VEXScalar): New.
654
655 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
656 instructions.
657 * i386-tbl.h: Regenerated.
658
706e8205 6592010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 660
661 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
662
663 * i386-opc.tbl: Add xsave64 and xrstor64.
664 * i386-tbl.h: Regenerated.
665
99ea83aa
NC		 6662010-01-20 Nick Clifton <nickc@redhat.com>
667
668 PR 11170
669 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
670 based post-indexed addressing.
671
a6461c02
SP		 6722010-01-15 Sebastian Pop <sebastian.pop@amd.com>
673
674 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
675 * i386-tbl.h: Regenerated.
676
a2a7d12c
L		 6772010-01-14 H.J. Lu <hongjiu.lu@intel.com>
678
679 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
680 comments.
681
b9733481
L		 6822010-01-14 H.J. Lu <hongjiu.lu@intel.com>
683
684 * i386-dis.c (names_mm): New.
685 (intel_names_mm): Likewise.
686 (att_names_mm): Likewise.
687 (names_xmm): Likewise.
688 (intel_names_xmm): Likewise.
689 (att_names_xmm): Likewise.
690 (names_ymm): Likewise.
691 (intel_names_ymm): Likewise.
692 (att_names_ymm): Likewise.
693 (print_insn): Set names_mm, names_xmm and names_ymm.
694 (OP_MMX): Use names_mm, names_xmm and names_ymm.
695 (OP_XMM): Likewise.
696 (OP_EM): Likewise.
697 (OP_EMC): Likewise.
698 (OP_MXC): Likewise.
699 (OP_EX): Likewise.
700 (XMM_Fixup): Likewise.
701 (OP_VEX): Likewise.
702 (OP_EX_VexReg): Likewise.
703 (OP_Vex_2src): Likewise.
704 (OP_Vex_2src_1): Likewise.
705 (OP_Vex_2src_2): Likewise.
706 (OP_REG_VexI4): Likewise.
707
5e6718e4
L		 7082010-01-13 H.J. Lu <hongjiu.lu@intel.com>
709
710 * i386-dis.c (print_insn): Update comments.
711
d869730d
L		 7122010-01-12 H.J. Lu <hongjiu.lu@intel.com>
713
714 * i386-dis.c (rex_original): Removed.
715 (ckprefix): Remove rex_original.
716 (print_insn): Update comments.
717
3725885a
RW		 7182010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
719
720 * Makefile.in: Regenerate.
721 * configure: Regenerate.
722
b7cd1872
DE		 7232010-01-07 Doug Evans <dje@sebabeach.org>
724
725 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
726 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
727 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
728 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
729 * xstormy16-ibld.c: Regenerate.
730
69dd9865
SP		 7312010-01-06 Quentin Neill <quentin.neill@amd.com>
732
733 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
734 * i386-init.h: Regenerated.
735
e3e535bc
NC		 7362010-01-06 Daniel Gutson <dgutson@codesourcery.com>
737
738 * arm-dis.c (print_insn): Fixed search for next symbol and data
739 dumping condition, and the initial mapping symbol state.
740
fe8afbc4
DE		 7412010-01-05 Doug Evans <dje@sebabeach.org>
742
743 * cgen-ibld.in: #include "cgen/basic-modes.h".
744 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
745 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
746 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
747 * xstormy16-ibld.c: Regenerate.
748
2edcd244
NC		 7492010-01-04 Nick Clifton <nickc@redhat.com>
750
751 PR 11123
752 * arm-dis.c (print_insn_coprocessor): Initialise value.
753
0dc93057
AM		 7542010-01-04 Edmar Wienskoski <edmar@freescale.com>
755
756 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
757
05994f45
DE		 7582010-01-02 Doug Evans <dje@sebabeach.org>
759
760 * cgen-asm.in: Update copyright year.
761 * cgen-dis.in: Update copyright year.
762 * cgen-ibld.in: Update copyright year.
763 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
764 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
765 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
766 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
767 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
768 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
769 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
770 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
771 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
772 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
773 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
774 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
775 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
776 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
777 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
778 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
779 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
780 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
781 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
782 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
783 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 784
43ecc30f 785For older changes see ChangeLog-2009
252b5132
RH		 786\f
787Local Variables:
2f6d2f85
NC		 788mode: change-log
789left-margin: 8
790fill-column: 74
252b5132
RH		 791version-control: never
792End:
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