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[binutils][aarch64] New SVE_SHRIMM_UNPRED_22 operand.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3c17238b
MM		 12019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
2
3 * aarch64-asm-2.c: Regenerated.
4 * aarch64-dis-2.c: Regenerated.
5 * aarch64-opc-2.c: Regenerated.
6 * aarch64-asm.c (aarch64_ins_sve_shrimm):
7 (aarch64_encode_variant_using_iclass): Handle
8 sve_shift_tsz_hsd iclass encode.
9 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
10 sve_shift_tsz_hsd iclass decode.
11 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
12 for SVE_SHRIMM_UNPRED_22.
13 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
14 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
15 operand.
16
cd50a87a
MM		 172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
18
19 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
20 sve_size_013 iclass encode.
21 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
22 sve_size_013 iclass decode.
23
3c705960
MM		 242019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
25
26 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
27 sve_size_bh iclass encode.
28 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
29 sve_size_bh iclass decode.
30
0a57e14f
MM		 312019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
32
33 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
34 sve_size_sd2 iclass encode.
35 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
36 sve_size_sd2 iclass decode.
37 * aarch64-opc.c (fields): Handle SVE_sz2 field.
38 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
39
c469c864
MM		 402019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
41
42 * aarch64-asm-2.c: Regenerated.
43 * aarch64-dis-2.c: Regenerated.
44 * aarch64-opc-2.c: Regenerated.
45 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
46 for SVE_ADDR_ZX.
47 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
48 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
49
116adc27
MM		 502019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
51
52 * aarch64-asm-2.c: Regenerated.
53 * aarch64-dis-2.c: Regenerated.
54 * aarch64-opc-2.c: Regenerated.
55 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
56 for SVE_Zm3_11_INDEX.
57 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
58 (fields): Handle SVE_i3l and SVE_i3h2 fields.
59 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
60 fields.
61 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
62
3bd82c86
MM		 632019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
64
65 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
66 sve_size_hsd2 iclass encode.
67 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
68 sve_size_hsd2 iclass decode.
69 * aarch64-opc.c (fields): Handle SVE_size field.
70 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
71
adccc507
MM		 722019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
73
74 * aarch64-asm-2.c: Regenerated.
75 * aarch64-dis-2.c: Regenerated.
76 * aarch64-opc-2.c: Regenerated.
77 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
78 for SVE_IMM_ROT3.
79 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
80 (fields): Handle SVE_rot3 field.
81 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
82 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
83
5cd99750
MM		 842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
85
86 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
87 instructions.
88
7ce2460a
MM		 892019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
90
91 * aarch64-tbl.h
92 (aarch64_feature_sve2, aarch64_feature_sve2aes,
93 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
94 aarch64_feature_sve2bitperm): New feature sets.
95 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
96 for feature set addresses.
97 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
98 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
99
41cee089
FS		 1002019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
101 Faraz Shahbazker <fshahbazker@wavecomp.com>
102
103 * mips-dis.c (mips_calculate_combination_ases): Add ISA
104 argument and set ASE_EVA_R6 appropriately.
105 (set_default_mips_dis_options): Pass ISA to above.
106 (parse_mips_dis_option): Likewise.
107 * mips-opc.c (EVAR6): New macro.
108 (mips_builtin_opcodes): Add llwpe, scwpe.
109
b83b4b13
SD		 1102019-05-01 Sudakshina Das <sudi.das@arm.com>
111
112 * aarch64-asm-2.c: Regenerated.
113 * aarch64-dis-2.c: Regenerated.
114 * aarch64-opc-2.c: Regenerated.
115 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
116 AARCH64_OPND_TME_UIMM16.
117 (aarch64_print_operand): Likewise.
118 * aarch64-tbl.h (QL_IMM_NIL): New.
119 (TME): New.
120 (_TME_INSN): New.
121 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
122
4a90ce95
JD		 1232019-04-29 John Darrington <john@darrington.wattle.id.au>
124
125 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
126
a45328b9
AB		 1272019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
128 Faraz Shahbazker <fshahbazker@wavecomp.com>
129
130 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
131
d10be0cb
JD		 1322019-04-24 John Darrington <john@darrington.wattle.id.au>
133
134 * s12z-opc.h: Add extern "C" bracketing to help
135 users who wish to use this interface in c++ code.
136
a679f24e
JD		 1372019-04-24 John Darrington <john@darrington.wattle.id.au>
138
139 * s12z-opc.c (bm_decode): Handle bit map operations with the
140 "reserved0" mode.
141
32c36c3c
AV		 1422019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
143
144 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
145 specifier. Add entries for VLDR and VSTR of system registers.
146 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
147 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
148 of %J and %K format specifier.
149
efd6b359
AV		 1502019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
151
152 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
153 Add new entries for VSCCLRM instruction.
154 (print_insn_coprocessor): Handle new %C format control code.
155
6b0dd094
AV		 1562019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
157
158 * arm-dis.c (enum isa): New enum.
159 (struct sopcode32): New structure.
160 (coprocessor_opcodes): change type of entries to struct sopcode32 and
161 set isa field of all current entries to ANY.
162 (print_insn_coprocessor): Change type of insn to struct sopcode32.
163 Only match an entry if its isa field allows the current mode.
164
4b5a202f
AV		 1652019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
166
167 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
168 CLRM.
169 (print_insn_thumb32): Add logic to print %n CLRM register list.
170
60f993ce
AV		 1712019-04-15 Sudakshina Das <sudi.das@arm.com>
172
173 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
174 and %Q patterns.
175
f6b2b12d
AV		 1762019-04-15 Sudakshina Das <sudi.das@arm.com>
177
178 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
179 (print_insn_thumb32): Edit the switch case for %Z.
180
1889da70
AV		 1812019-04-15 Sudakshina Das <sudi.das@arm.com>
182
183 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
184
65d1bc05
AV		 1852019-04-15 Sudakshina Das <sudi.das@arm.com>
186
187 * arm-dis.c (thumb32_opcodes): New instruction bfl.
188
1caf72a5
AV		 1892019-04-15 Sudakshina Das <sudi.das@arm.com>
190
191 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
192
f1c7f421
AV		 1932019-04-15 Sudakshina Das <sudi.das@arm.com>
194
195 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
196 Arm register with r13 and r15 unpredictable.
197 (thumb32_opcodes): New instructions for bfx and bflx.
198
4389b29a
AV		 1992019-04-15 Sudakshina Das <sudi.das@arm.com>
200
201 * arm-dis.c (thumb32_opcodes): New instructions for bf.
202
e5d6e09e
AV		 2032019-04-15 Sudakshina Das <sudi.das@arm.com>
204
205 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
206
e12437dc
AV		 2072019-04-15 Sudakshina Das <sudi.das@arm.com>
208
209 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
210
031254f2
AV		 2112019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
212
213 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
214
e5a557ac
JD		 2152019-04-12 John Darrington <john@darrington.wattle.id.au>
216
217 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
218 "optr". ("operator" is a reserved word in c++).
219
bd7ceb8d
SD		 2202019-04-11 Sudakshina Das <sudi.das@arm.com>
221
222 * aarch64-opc.c (aarch64_print_operand): Add case for
223 AARCH64_OPND_Rt_SP.
224 (verify_constraints): Likewise.
225 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
226 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
227 to accept Rt|SP as first operand.
228 (AARCH64_OPERANDS): Add new Rt_SP.
229 * aarch64-asm-2.c: Regenerated.
230 * aarch64-dis-2.c: Regenerated.
231 * aarch64-opc-2.c: Regenerated.
232
e54010f1
SD		 2332019-04-11 Sudakshina Das <sudi.das@arm.com>
234
235 * aarch64-asm-2.c: Regenerated.
236 * aarch64-dis-2.c: Likewise.
237 * aarch64-opc-2.c: Likewise.
238 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
239
7e96e219
RS		 2402019-04-09 Robert Suchanek <robert.suchanek@mips.com>
241
242 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
243
6f2791d5
L		 2442019-04-08 H.J. Lu <hongjiu.lu@intel.com>
245
246 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
247 * i386-init.h: Regenerated.
248
e392bad3
AM		 2492019-04-07 Alan Modra <amodra@gmail.com>
250
251 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
252 op_separator to control printing of spaces, comma and parens
253 rather than need_comma, need_paren and spaces vars.
254
dffaa15c
AM		 2552019-04-07 Alan Modra <amodra@gmail.com>
256
257 PR 24421
258 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
259 (print_insn_neon, print_insn_arm): Likewise.
260
d6aab7a1
XG		 2612019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
262
263 * i386-dis-evex.h (evex_table): Updated to support BF16
264 instructions.
265 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
266 and EVEX_W_0F3872_P_3.
267 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
268 (cpu_flags): Add bitfield for CpuAVX512_BF16.
269 * i386-opc.h (enum): Add CpuAVX512_BF16.
270 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
271 * i386-opc.tbl: Add AVX512 BF16 instructions.
272 * i386-init.h: Regenerated.
273 * i386-tbl.h: Likewise.
274
66e85460
AM		 2752019-04-05 Alan Modra <amodra@gmail.com>
276
277 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
278 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
279 to favour printing of "-" branch hint when using the "y" bit.
280 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
281
c2b1c275
AM		 2822019-04-05 Alan Modra <amodra@gmail.com>
283
284 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
285 opcode until first operand is output.
286
aae9718e
PB		 2872019-04-04 Peter Bergner <bergner@linux.ibm.com>
288
289 PR gas/24349
290 * ppc-opc.c (valid_bo_pre_v2): Add comments.
291 (valid_bo_post_v2): Add support for 'at' branch hints.
292 (insert_bo): Only error on branch on ctr.
293 (get_bo_hint_mask): New function.
294 (insert_boe): Add new 'branch_taken' formal argument. Add support
295 for inserting 'at' branch hints.
296 (extract_boe): Add new 'branch_taken' formal argument. Add support
297 for extracting 'at' branch hints.
298 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
299 (BOE): Delete operand.
300 (BOM, BOP): New operands.
301 (RM): Update value.
302 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
303 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
304 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
305 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
306 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
307 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
308 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
309 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
310 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
311 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
312 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
313 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
314 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
315 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
316 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
317 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
318 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
319 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
320 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
321 bttarl+>: New extended mnemonics.
322
96a86c01
AM		 3232019-03-28 Alan Modra <amodra@gmail.com>
324
325 PR 24390
326 * ppc-opc.c (BTF): Define.
327 (powerpc_opcodes): Use for mtfsb*.
328 * ppc-dis.c (print_insn_powerpc): Print fields with both
329 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
330
796d6298
TC		 3312019-03-25 Tamar Christina <tamar.christina@arm.com>
332
333 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
334 (mapping_symbol_for_insn): Implement new algorithm.
335 (print_insn): Remove duplicate code.
336
60df3720
TC		 3372019-03-25 Tamar Christina <tamar.christina@arm.com>
338
339 * aarch64-dis.c (print_insn_aarch64):
340 Implement override.
341
51457761
TC		 3422019-03-25 Tamar Christina <tamar.christina@arm.com>
343
344 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
345 order.
346
53b2f36b
TC		 3472019-03-25 Tamar Christina <tamar.christina@arm.com>
348
349 * aarch64-dis.c (last_stop_offset): New.
350 (print_insn_aarch64): Use stop_offset.
351
89199bb5
L		 3522019-03-19 H.J. Lu <hongjiu.lu@intel.com>
353
354 PR gas/24359
355 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
356 CPU_ANY_AVX2_FLAGS.
357 * i386-init.h: Regenerated.
358
97ed31ae
L		 3592019-03-18 H.J. Lu <hongjiu.lu@intel.com>
360
361 PR gas/24348
362 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
363 vmovdqu16, vmovdqu32 and vmovdqu64.
364 * i386-tbl.h: Regenerated.
365
0919bfe9
AK		 3662019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
367
368 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
369 from vstrszb, vstrszh, and vstrszf.
370
3712019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
372
373 * s390-opc.txt: Add instruction descriptions.
374
21820ebe
JW		 3752019-02-08 Jim Wilson <jimw@sifive.com>
376
377 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
378 <bne>: Likewise.
379
f7dd2fb2
TC		 3802019-02-07 Tamar Christina <tamar.christina@arm.com>
381
382 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
383
6456d318
TC		 3842019-02-07 Tamar Christina <tamar.christina@arm.com>
385
386 PR binutils/23212
387 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
388 * aarch64-opc.c (verify_elem_sd): New.
389 (fields): Add FLD_sz entr.
390 * aarch64-tbl.h (_SIMD_INSN): New.
391 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
392 fmulx scalar and vector by element isns.
393
4a83b610
NC		 3942019-02-07 Nick Clifton <nickc@redhat.com>
395
396 * po/sv.po: Updated Swedish translation.
397
fc60b8c8
AK		 3982019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
399
400 * s390-mkopc.c (main): Accept arch13 as cpu string.
401 * s390-opc.c: Add new instruction formats and instruction opcode
402 masks.
403 * s390-opc.txt: Add new arch13 instructions.
404
e10620d3
TC		 4052019-01-25 Sudakshina Das <sudi.das@arm.com>
406
407 * aarch64-tbl.h (QL_LDST_AT): Update macro.
408 (aarch64_opcode): Change encoding for stg, stzg
409 st2g and st2zg.
410 * aarch64-asm-2.c: Regenerated.
411 * aarch64-dis-2.c: Regenerated.
412 * aarch64-opc-2.c: Regenerated.
413
20a4ca55
SD		 4142019-01-25 Sudakshina Das <sudi.das@arm.com>
415
416 * aarch64-asm-2.c: Regenerated.
417 * aarch64-dis-2.c: Likewise.
418 * aarch64-opc-2.c: Likewise.
419 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
420
550fd7bf
SD		 4212019-01-25 Sudakshina Das <sudi.das@arm.com>
422 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
423
424 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
425 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
426 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
427 * aarch64-dis.h (ext_addr_simple_2): Likewise.
428 * aarch64-opc.c (operand_general_constraint_met_p): Remove
429 case for ldstgv_indexed.
430 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
431 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
432 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
433 * aarch64-asm-2.c: Regenerated.
434 * aarch64-dis-2.c: Regenerated.
435 * aarch64-opc-2.c: Regenerated.
436
d9938630
NC		 4372019-01-23 Nick Clifton <nickc@redhat.com>
438
439 * po/pt_BR.po: Updated Brazilian Portuguese translation.
440
375cd423
NC		 4412019-01-21 Nick Clifton <nickc@redhat.com>
442
443 * po/de.po: Updated German translation.
444 * po/uk.po: Updated Ukranian translation.
445
57299f48
CX		 4462019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
447 * mips-dis.c (mips_arch_choices): Fix typo in
448 gs464, gs464e and gs264e descriptors.
449
f48dfe41
NC		 4502019-01-19 Nick Clifton <nickc@redhat.com>
451
452 * configure: Regenerate.
453 * po/opcodes.pot: Regenerate.
454
f974f26c
NC		 4552018-06-24 Nick Clifton <nickc@redhat.com>
456
457 2.32 branch created.
458
39f286cd
JD		 4592019-01-09 John Darrington <john@darrington.wattle.id.au>
460
448b8ca8
JD		 461 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
462 if it is null.
463 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 464 zero.
465
3107326d
AP		 4662019-01-09 Andrew Paprocki <andrew@ishiboo.com>
467
468 * configure: Regenerate.
469
7e9ca91e
AM		 4702019-01-07 Alan Modra <amodra@gmail.com>
471
472 * configure: Regenerate.
473 * po/POTFILES.in: Regenerate.
474
ef1ad42b
JD		 4752019-01-03 John Darrington <john@darrington.wattle.id.au>
476
477 * s12z-opc.c: New file.
478 * s12z-opc.h: New file.
479 * s12z-dis.c: Removed all code not directly related to display
480 of instructions. Used the interface provided by the new files
481 instead.
482 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 483 * Makefile.in: Regenerate.
ef1ad42b 484 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 485 * configure: Regenerate.
ef1ad42b 486
82704155
AM		 4872019-01-01 Alan Modra <amodra@gmail.com>
488
489 Update year range in copyright notice of all files.
490
d5c04e1b 491For older changes see ChangeLog-2018
3499769a 492\f
d5c04e1b 493Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 494
495Copying and distribution of this file, with or without modification,
496are permitted in any medium without royalty provided the copyright
497notice and this notice are preserved.
498
499Local Variables:
500mode: change-log
501left-margin: 8
502fill-column: 74
503version-control: never
504End:
A mirror of the official binutils-gdb repository