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429d795d
AM		 12017-07-12 Alan Modra <amodra@gmail.com>
2
3 * po/da.po: Update from translationproject.org/latest/opcodes/.
4 * po/de.po: Likewise.
5 * po/es.po: Likewise.
6 * po/fi.po: Likewise.
7 * po/fr.po: Likewise.
8 * po/id.po: Likewise.
9 * po/it.po: Likewise.
10 * po/nl.po: Likewise.
11 * po/pt_BR.po: Likewise.
12 * po/ro.po: Likewise.
13 * po/sv.po: Likewise.
14 * po/tr.po: Likewise.
15 * po/uk.po: Likewise.
16 * po/vi.po: Likewise.
17 * po/zh_CN.po: Likewise.
18
4162bb66
AM		 192017-07-11 Yao Qi <yao.qi@linaro.org>
20 Alan Modra <amodra@gmail.com>
21
22 * cgen.sh: Mark generated files read-only.
23 * epiphany-asm.c: Regenerate.
24 * epiphany-desc.c: Regenerate.
25 * epiphany-desc.h: Regenerate.
26 * epiphany-dis.c: Regenerate.
27 * epiphany-ibld.c: Regenerate.
28 * epiphany-opc.c: Regenerate.
29 * epiphany-opc.h: Regenerate.
30 * fr30-asm.c: Regenerate.
31 * fr30-desc.c: Regenerate.
32 * fr30-desc.h: Regenerate.
33 * fr30-dis.c: Regenerate.
34 * fr30-ibld.c: Regenerate.
35 * fr30-opc.c: Regenerate.
36 * fr30-opc.h: Regenerate.
37 * frv-asm.c: Regenerate.
38 * frv-desc.c: Regenerate.
39 * frv-desc.h: Regenerate.
40 * frv-dis.c: Regenerate.
41 * frv-ibld.c: Regenerate.
42 * frv-opc.c: Regenerate.
43 * frv-opc.h: Regenerate.
44 * ip2k-asm.c: Regenerate.
45 * ip2k-desc.c: Regenerate.
46 * ip2k-desc.h: Regenerate.
47 * ip2k-dis.c: Regenerate.
48 * ip2k-ibld.c: Regenerate.
49 * ip2k-opc.c: Regenerate.
50 * ip2k-opc.h: Regenerate.
51 * iq2000-asm.c: Regenerate.
52 * iq2000-desc.c: Regenerate.
53 * iq2000-desc.h: Regenerate.
54 * iq2000-dis.c: Regenerate.
55 * iq2000-ibld.c: Regenerate.
56 * iq2000-opc.c: Regenerate.
57 * iq2000-opc.h: Regenerate.
58 * lm32-asm.c: Regenerate.
59 * lm32-desc.c: Regenerate.
60 * lm32-desc.h: Regenerate.
61 * lm32-dis.c: Regenerate.
62 * lm32-ibld.c: Regenerate.
63 * lm32-opc.c: Regenerate.
64 * lm32-opc.h: Regenerate.
65 * lm32-opinst.c: Regenerate.
66 * m32c-asm.c: Regenerate.
67 * m32c-desc.c: Regenerate.
68 * m32c-desc.h: Regenerate.
69 * m32c-dis.c: Regenerate.
70 * m32c-ibld.c: Regenerate.
71 * m32c-opc.c: Regenerate.
72 * m32c-opc.h: Regenerate.
73 * m32r-asm.c: Regenerate.
74 * m32r-desc.c: Regenerate.
75 * m32r-desc.h: Regenerate.
76 * m32r-dis.c: Regenerate.
77 * m32r-ibld.c: Regenerate.
78 * m32r-opc.c: Regenerate.
79 * m32r-opc.h: Regenerate.
80 * m32r-opinst.c: Regenerate.
81 * mep-asm.c: Regenerate.
82 * mep-desc.c: Regenerate.
83 * mep-desc.h: Regenerate.
84 * mep-dis.c: Regenerate.
85 * mep-ibld.c: Regenerate.
86 * mep-opc.c: Regenerate.
87 * mep-opc.h: Regenerate.
88 * mt-asm.c: Regenerate.
89 * mt-desc.c: Regenerate.
90 * mt-desc.h: Regenerate.
91 * mt-dis.c: Regenerate.
92 * mt-ibld.c: Regenerate.
93 * mt-opc.c: Regenerate.
94 * mt-opc.h: Regenerate.
95 * or1k-asm.c: Regenerate.
96 * or1k-desc.c: Regenerate.
97 * or1k-desc.h: Regenerate.
98 * or1k-dis.c: Regenerate.
99 * or1k-ibld.c: Regenerate.
100 * or1k-opc.c: Regenerate.
101 * or1k-opc.h: Regenerate.
102 * or1k-opinst.c: Regenerate.
103 * xc16x-asm.c: Regenerate.
104 * xc16x-desc.c: Regenerate.
105 * xc16x-desc.h: Regenerate.
106 * xc16x-dis.c: Regenerate.
107 * xc16x-ibld.c: Regenerate.
108 * xc16x-opc.c: Regenerate.
109 * xc16x-opc.h: Regenerate.
110 * xstormy16-asm.c: Regenerate.
111 * xstormy16-desc.c: Regenerate.
112 * xstormy16-desc.h: Regenerate.
113 * xstormy16-dis.c: Regenerate.
114 * xstormy16-ibld.c: Regenerate.
115 * xstormy16-opc.c: Regenerate.
116 * xstormy16-opc.h: Regenerate.
117
7639175c
AM		 1182017-07-07 Alan Modra <amodra@gmail.com>
119
120 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
121 * m32c-dis.c: Regenerate.
122 * mep-dis.c: Regenerate.
123
e4bdd679
BP		 1242017-07-05 Borislav Petkov <bp@suse.de>
125
126 * i386-dis.c: Enable ModRM.reg /6 aliases.
127
60c96dbf
RR		 1282017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
129
130 * opcodes/arm-dis.c: Support MVFR2 in disassembly
131 with vmrs and vmsr.
132
0d702cfe
TG		 1332017-07-04 Tristan Gingold <gingold@adacore.com>
134
135 * configure: Regenerate.
136
15e6ed8c
TG		 1372017-07-03 Tristan Gingold <gingold@adacore.com>
138
139 * po/opcodes.pot: Regenerate.
140
b1d3c886
MR		 1412017-06-30 Maciej W. Rozycki <macro@imgtec.com>
142
143 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
144 entries to the MSA ASE instruction block.
145
909b4e3d
MR		 1462017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
147 Maciej W. Rozycki <macro@imgtec.com>
148
149 * micromips-opc.c (XPA, XPAVZ): New macros.
150 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
151 "mthgc0".
152
f5b2fd52
MR		 1532017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
154 Maciej W. Rozycki <macro@imgtec.com>
155
156 * micromips-opc.c (I36): New macro.
157 (micromips_opcodes): Add "eretnc".
158
9785fc2a
MR		 1592017-06-30 Maciej W. Rozycki <macro@imgtec.com>
160 Andrew Bennett <andrew.bennett@imgtec.com>
161
162 * mips-dis.c (mips_calculate_combination_ases): Handle the
163 ASE_XPA_VIRT flag.
164 (parse_mips_ase_option): New function.
165 (parse_mips_dis_option): Factor out ASE option handling to the
166 new function. Call `mips_calculate_combination_ases'.
167 * mips-opc.c (XPAVZ): New macro.
168 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
169 "mfhgc0", "mthc0" and "mthgc0".
170
60804c53
MR		 1712017-06-29 Maciej W. Rozycki <macro@imgtec.com>
172
173 * mips-dis.c (mips_calculate_combination_ases): New function.
174 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
175 calculation to the new function.
176 (set_default_mips_dis_options): Call the new function.
177
2e74f9dd
AK		 1782017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
179
180 * arc-dis.c (parse_disassembler_options): Use
181 FOR_EACH_DISASSEMBLER_OPTION.
182
e1e94c49
AK		 1832017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
184
185 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
186 disassembler option strings.
187 (parse_cpu_option): Likewise.
188
65a55fbb
TC		 1892017-06-28 Tamar Christina <tamar.christina@arm.com>
190
191 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
192 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
193 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
194 (aarch64_feature_dotprod, DOT_INSN): New.
195 (udot, sdot): New.
196 * aarch64-dis-2.c: Regenerated.
197
c604a79a
JW		 1982017-06-28 Jiong Wang <jiong.wang@arm.com>
199
200 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
201
38bf472a
MR		 2022017-06-28 Maciej W. Rozycki <macro@imgtec.com>
203 Matthew Fortune <matthew.fortune@imgtec.com>
4151f684 204 Andrew Bennett <andrew.bennett@imgtec.com>
38bf472a
MR		 205
206 * mips-formats.h (INT_BIAS): New macro.
207 (INT_ADJ): Redefine in INT_BIAS terms.
208 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
209 (mips_print_save_restore): New function.
210 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
211 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
212 call.
213 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
214 (print_mips16_insn_arg): Call `mips_print_save_restore' for
215 OP_SAVE_RESTORE_LIST handling, factored out from here.
216 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
217 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
218 (mips_builtin_opcodes): Add "restore" and "save" entries.
219 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
220 (IAMR2): New macro.
221 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
222
9bdfdbf9
AW		 2232017-06-23 Andrew Waterman <andrew@sifive.com>
224
225 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
226 alias; do not mark SLTI instruction as an alias.
227
2234eee6
L		 2282017-06-21 H.J. Lu <hongjiu.lu@intel.com>
229
230 * i386-dis.c (RM_0FAE_REG_5): Removed.
231 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
232 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
233 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
234 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
235 PREFIX_MOD_3_0F01_REG_5_RM_0.
236 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
237 PREFIX_MOD_3_0FAE_REG_5.
238 (mod_table): Update MOD_0FAE_REG_5.
239 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
240 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
241 * i386-tbl.h: Regenerated.
242
c2f76402
L		 2432017-06-21 H.J. Lu <hongjiu.lu@intel.com>
244
245 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
246 * i386-opc.tbl: Likewise.
247 * i386-tbl.h: Regenerated.
248
9fef80d6
L		 2492017-06-21 H.J. Lu <hongjiu.lu@intel.com>
250
251 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
252 and "jmp{&|}".
253 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
254 prefix.
255
0f6d864d
NC		 2562017-06-19 Nick Clifton <nickc@redhat.com>
257
258 PR binutils/21614
259 * score-dis.c (score_opcodes): Add sentinel.
260
e197589b
AM		 2612017-06-16 Alan Modra <amodra@gmail.com>
262
263 * rx-decode.c: Regenerate.
264
0d96e4df
L		 2652017-06-15 H.J. Lu <hongjiu.lu@intel.com>
266
267 PR binutils/21594
268 * i386-dis.c (OP_E_register): Check valid bnd register.
269 (OP_G): Likewise.
270
cd3ea7c6
NC		 2712017-06-15 Nick Clifton <nickc@redhat.com>
272
273 PR binutils/21595
274 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
275 range value.
276
63323b5b
NC		 2772017-06-15 Nick Clifton <nickc@redhat.com>
278
279 PR binutils/21588
280 * rl78-decode.opc (OP_BUF_LEN): Define.
281 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
282 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
283 array.
284 * rl78-decode.c: Regenerate.
285
08c7881b
NC		 2862017-06-15 Nick Clifton <nickc@redhat.com>
287
288 PR binutils/21586
289 * bfin-dis.c (gregs): Clip index to prevent overflow.
290 (regs): Likewise.
291 (regs_lo): Likewise.
292 (regs_hi): Likewise.
293
e64519d1
NC		 2942017-06-14 Nick Clifton <nickc@redhat.com>
295
296 PR binutils/21576
297 * score7-dis.c (score_opcodes): Add sentinel.
298
6394c606
YQ		 2992017-06-14 Yao Qi <yao.qi@linaro.org>
300
301 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
302 * arm-dis.c: Likewise.
303 * ia64-dis.c: Likewise.
304 * mips-dis.c: Likewise.
305 * spu-dis.c: Likewise.
306 * disassemble.h (print_insn_aarch64): New declaration, moved from
307 include/dis-asm.h.
308 (print_insn_big_arm, print_insn_big_mips): Likewise.
309 (print_insn_i386, print_insn_ia64): Likewise.
310 (print_insn_little_arm, print_insn_little_mips): Likewise.
311
db5fa770
NC		 3122017-06-14 Nick Clifton <nickc@redhat.com>
313
314 PR binutils/21587
315 * rx-decode.opc: Include libiberty.h
316 (GET_SCALE): New macro - validates access to SCALE array.
317 (GET_PSCALE): New macro - validates access to PSCALE array.
318 (DIs, SIs, S2Is, rx_disp): Use new macros.
319 * rx-decode.c: Regenerate.
320
05c966f3
AV		 3212017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
322
323 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
324
10045478
AK		 3252017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
326
327 * arc-dis.c (enforced_isa_mask): Declare.
328 (cpu_types): Likewise.
329 (parse_cpu_option): New function.
330 (parse_disassembler_options): Use it.
331 (print_insn_arc): Use enforced_isa_mask.
332 (print_arc_disassembler_options): Document new options.
333
88c1242d
YQ		 3342017-05-24 Yao Qi <yao.qi@linaro.org>
335
336 * alpha-dis.c: Include disassemble.h, don't include
337 dis-asm.h.
338 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
339 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
340 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
341 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
342 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
343 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
344 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
345 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
346 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
347 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
348 * moxie-dis.c, msp430-dis.c, mt-dis.c:
349 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
350 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
351 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
352 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
353 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
354 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
355 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
356 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
357 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
358 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
359 * z80-dis.c, z8k-dis.c: Likewise.
360 * disassemble.h: New file.
361
ab20fa4a
YQ		 3622017-05-24 Yao Qi <yao.qi@linaro.org>
363
364 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
365 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
366
003ca0fd
YQ		 3672017-05-24 Yao Qi <yao.qi@linaro.org>
368
369 * disassemble.c (disassembler): Add arguments a, big and mach.
370 Use them.
371
04ef582a
L		 3722017-05-22 H.J. Lu <hongjiu.lu@intel.com>
373
374 * i386-dis.c (NOTRACK_Fixup): New.
375 (NOTRACK): Likewise.
376 (NOTRACK_PREFIX): Likewise.
377 (last_active_prefix): Likewise.
378 (reg_table): Use NOTRACK on indirect call and jmp.
379 (ckprefix): Set last_active_prefix.
380 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
381 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
382 * i386-opc.h (NoTrackPrefixOk): New.
383 (i386_opcode_modifier): Add notrackprefixok.
384 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
385 Add notrack.
386 * i386-tbl.h: Regenerated.
387
64517994
JM		 3882017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
389
390 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
391 (X_IMM2): Define.
392 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
393 bfd_mach_sparc_v9m8.
394 (print_insn_sparc): Handle new operand types.
395 * sparc-opc.c (MASK_M8): Define.
396 (v6): Add MASK_M8.
397 (v6notlet): Likewise.
398 (v7): Likewise.
399 (v8): Likewise.
400 (v9): Likewise.
401 (v9a): Likewise.
402 (v9b): Likewise.
403 (v9c): Likewise.
404 (v9d): Likewise.
405 (v9e): Likewise.
406 (v9v): Likewise.
407 (v9m): Likewise.
408 (v9andleon): Likewise.
409 (m8): Define.
410 (HWS_VM8): Define.
411 (HWS2_VM8): Likewise.
412 (sparc_opcode_archs): Add entry for "m8".
413 (sparc_opcodes): Add OSA2017 and M8 instructions
414 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
415 fpx{ll,ra,rl}64x,
416 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
417 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
418 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
419 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
420 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
421 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
422 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
423 ASI_CORE_SELECT_COMMIT_NHT.
424
535b785f
AM		 4252017-05-18 Alan Modra <amodra@gmail.com>
426
427 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
428 * aarch64-dis.c: Likewise.
429 * aarch64-gen.c: Likewise.
430 * aarch64-opc.c: Likewise.
431
25499ac7
MR		 4322017-05-15 Maciej W. Rozycki <macro@imgtec.com>
433 Matthew Fortune <matthew.fortune@imgtec.com>
434
435 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
436 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
437 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
438 (print_insn_arg) <OP_REG28>: Add handler.
439 (validate_insn_args) <OP_REG28>: Handle.
440 (print_mips16_insn_arg): Handle MIPS16 instructions that require
441 32-bit encoding and 9-bit immediates.
442 (print_insn_mips16): Handle MIPS16 instructions that require
443 32-bit encoding and MFC0/MTC0 operand decoding.
444 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
445 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
446 (RD_C0, WR_C0, E2, E2MT): New macros.
447 (mips16_opcodes): Add entries for MIPS16e2 instructions:
448 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
449 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
450 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
451 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
452 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
453 instructions, "swl", "swr", "sync" and its "sync_acquire",
454 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
455 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
456 regular/extended entries for original MIPS16 ISA revision
457 instructions whose extended forms are subdecoded in the MIPS16e2
458 ISA revision: "li", "sll" and "srl".
459
fdfb4752
MR		 4602017-05-15 Maciej W. Rozycki <macro@imgtec.com>
461
462 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
463 reference in CP0 move operand decoding.
464
a4f89915
MR		 4652017-05-12 Maciej W. Rozycki <macro@imgtec.com>
466
467 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
468 type to hexadecimal.
469 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
470
99e2d67a
MR		 4712017-05-11 Maciej W. Rozycki <macro@imgtec.com>
472
473 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
474 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
475 "sync_rmb" and "sync_wmb" as aliases.
476 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
477 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
478
53a346d8
CZ		 4792017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
480
481 * arc-dis.c (parse_option): Update quarkse_em option..
482 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
483 QUARKSE1.
484 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
485
f91d48de
KC		 4862017-05-03 Kito Cheng <kito.cheng@gmail.com>
487
488 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
489
43e379d7
MC		 4902017-05-01 Michael Clark <michaeljclark@mac.com>
491
492 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
493 register.
494
a4ddc54e
MR		 4952017-05-02 Maciej W. Rozycki <macro@imgtec.com>
496
497 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
498 and branches and not synthetic data instructions.
499
fe50e98c
BE		 5002017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
501
502 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
503
126124cc
CZ		 5042017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
505
506 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
507 * arc-opc.c (insert_r13el): New function.
508 (R13_EL): Define.
509 * arc-tbl.h: Add new enter/leave variants.
510
be6a24d8
CZ		 5112017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
512
513 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
514
0348fd79
MR		 5152017-04-25 Maciej W. Rozycki <macro@imgtec.com>
516
517 * mips-dis.c (print_mips_disassembler_options): Add
518 `no-aliases'.
519
6e3d1f07
MR		 5202017-04-25 Maciej W. Rozycki <macro@imgtec.com>
521
522 * mips16-opc.c (AL): New macro.
523 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
524 of "ld" and "lw" as aliases.
525
957f6b39
TC		 5262017-04-24 Tamar Christina <tamar.christina@arm.com>
527
528 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
529 arguments.
530
a8cc8a54
AM		 5312017-04-22 Alexander Fedotov <alfedotov@gmail.com>
532 Alan Modra <amodra@gmail.com>
533
534 * ppc-opc.c (ELEV): Define.
535 (vle_opcodes): Add se_rfgi and e_sc.
536 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
537 for E200Z4.
538
3ab87b68
JM		 5392017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
540
541 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
542
792f174f
NC		 5432017-04-21 Nick Clifton <nickc@redhat.com>
544
545 PR binutils/21380
546 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
547 LD3R and LD4R.
548
42742084
AM		 5492017-04-13 Alan Modra <amodra@gmail.com>
550
551 * epiphany-desc.c: Regenerate.
552 * fr30-desc.c: Regenerate.
553 * frv-desc.c: Regenerate.
554 * ip2k-desc.c: Regenerate.
555 * iq2000-desc.c: Regenerate.
556 * lm32-desc.c: Regenerate.
557 * m32c-desc.c: Regenerate.
558 * m32r-desc.c: Regenerate.
559 * mep-desc.c: Regenerate.
560 * mt-desc.c: Regenerate.
561 * or1k-desc.c: Regenerate.
562 * xc16x-desc.c: Regenerate.
563 * xstormy16-desc.c: Regenerate.
564
9a85b496
AM		 5652017-04-11 Alan Modra <amodra@gmail.com>
566
ef85eab0 567 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
c03dc33b
AM		 568 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
569 PPC_OPCODE_TMR for e6500.
9a85b496
AM		 570 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
571 (PPCVEC3): Define as PPC_OPCODE_POWER9.
9570835e
AM		 572 (PPCVSX2): Define as PPC_OPCODE_POWER8.
573 (PPCVSX3): Define as PPC_OPCODE_POWER9.
ef85eab0 574 (PPCHTM): Define as PPC_OPCODE_POWER8.
c03dc33b 575 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
9a85b496 576
62adc510
AM		 5772017-04-10 Alan Modra <amodra@gmail.com>
578
579 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
580 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
581 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
582 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
583
aa808707
PC		 5842017-04-09 Pip Cet <pipcet@gmail.com>
585
586 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
587 appropriate floating-point precision directly.
588
ac8f0f72
AM		 5892017-04-07 Alan Modra <amodra@gmail.com>
590
591 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
592 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
593 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
594 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
595 vector instructions with E6500 not PPCVEC2.
596
62ecb94c
PC		 5972017-04-06 Pip Cet <pipcet@gmail.com>
598
599 * Makefile.am: Add wasm32-dis.c.
600 * configure.ac: Add wasm32-dis.c to wasm32 target.
601 * disassemble.c: Add wasm32 disassembler code.
602 * wasm32-dis.c: New file.
603 * Makefile.in: Regenerate.
604 * configure: Regenerate.
605 * po/POTFILES.in: Regenerate.
606 * po/opcodes.pot: Regenerate.
607
f995bbe8
PA		 6082017-04-05 Pedro Alves <palves@redhat.com>
609
610 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
611 * arm-dis.c (parse_arm_disassembler_options): Constify.
612 * ppc-dis.c (powerpc_init_dialect): Constify local.
613 * vax-dis.c (parse_disassembler_options): Constify.
614
b5292032
PD		 6152017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
616
617 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
618 RISCV_GP_SYMBOL.
619
f96bd6c2
PC		 6202017-03-30 Pip Cet <pipcet@gmail.com>
621
622 * configure.ac: Add (empty) bfd_wasm32_arch target.
623 * configure: Regenerate
624 * po/opcodes.pot: Regenerate.
625
f7c514a3
JM		 6262017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
627
628 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
629 OSA2015.
630 * opcodes/sparc-opc.c (asi_table): New ASIs.
631
52be03fd
AM		 6322017-03-29 Alan Modra <amodra@gmail.com>
633
634 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
635 "raw" option.
636 (lookup_powerpc): Don't special case -1 dialect. Handle
637 PPC_OPCODE_RAW.
638 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
639 lookup_powerpc call, pass it on second.
640
9b753937
AM		 6412017-03-27 Alan Modra <amodra@gmail.com>
642
643 PR 21303
644 * ppc-dis.c (struct ppc_mopt): Comment.
645 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
646
c0c31e91
RZ		 6472017-03-27 Rinat Zelig <rinat@mellanox.com>
648
649 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
650 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
651 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
652 (insert_nps_misc_imm_offset): New function.
653 (extract_nps_misc imm_offset): New function.
654 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
655 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
656
2253c8f0
AK		 6572017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
658
659 * s390-mkopc.c (main): Remove vx2 check.
660 * s390-opc.txt: Remove vx2 instruction flags.
661
645d3342
RZ		 6622017-03-21 Rinat Zelig <rinat@mellanox.com>
663
664 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
665 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
666 (insert_nps_imm_offset): New function.
667 (extract_nps_imm_offset): New function.
668 (insert_nps_imm_entry): New function.
669 (extract_nps_imm_entry): New function.
670
4b94dd2d
AM		 6712017-03-17 Alan Modra <amodra@gmail.com>
672
673 PR 21248
674 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
675 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
676 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
677
b416fe87
KC		 6782017-03-14 Kito Cheng <kito.cheng@gmail.com>
679
680 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
681 <c.andi>: Likewise.
682 <c.addiw> Likewise.
683
03b039a5
KC		 6842017-03-14 Kito Cheng <kito.cheng@gmail.com>
685
686 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
687
2c232b83
AW		 6882017-03-13 Andrew Waterman <andrew@sifive.com>
689
690 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
691 <srl> Likewise.
692 <srai> Likewise.
693 <sra> Likewise.
694
86fa6981
L		 6952017-03-09 H.J. Lu <hongjiu.lu@intel.com>
696
697 * i386-gen.c (opcode_modifiers): Replace S with Load.
698 * i386-opc.h (S): Removed.
699 (Load): New.
700 (i386_opcode_modifier): Replace s with load.
701 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
702 and {evex}. Replace S with Load.
703 * i386-tbl.h: Regenerated.
704
c1fe188b
L		 7052017-03-09 H.J. Lu <hongjiu.lu@intel.com>
706
707 * i386-opc.tbl: Use CpuCET on rdsspq.
708 * i386-tbl.h: Regenerated.
709
4b8b687e
PB		 7102017-03-08 Peter Bergner <bergner@vnet.ibm.com>
711
712 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
713 <vsx>: Do not use PPC_OPCODE_VSX3;
714
1437d063
PB		 7152017-03-08 Peter Bergner <bergner@vnet.ibm.com>
716
717 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
718
603555e5
L		 7192017-03-06 H.J. Lu <hongjiu.lu@intel.com>
720
721 * i386-dis.c (REG_0F1E_MOD_3): New enum.
722 (MOD_0F1E_PREFIX_1): Likewise.
723 (MOD_0F38F5_PREFIX_2): Likewise.
724 (MOD_0F38F6_PREFIX_0): Likewise.
725 (RM_0F1E_MOD_3_REG_7): Likewise.
726 (PREFIX_MOD_0_0F01_REG_5): Likewise.
727 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
728 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
729 (PREFIX_0F1E): Likewise.
730 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
731 (PREFIX_0F38F5): Likewise.
732 (dis386_twobyte): Use PREFIX_0F1E.
733 (reg_table): Add REG_0F1E_MOD_3.
734 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
735 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
736 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
737 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
738 (three_byte_table): Use PREFIX_0F38F5.
739 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
740 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
741 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
742 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
743 PREFIX_MOD_3_0F01_REG_5_RM_2.
744 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
745 (cpu_flags): Add CpuCET.
746 * i386-opc.h (CpuCET): New enum.
747 (CpuUnused): Commented out.
748 (i386_cpu_flags): Add cpucet.
749 * i386-opc.tbl: Add Intel CET instructions.
750 * i386-init.h: Regenerated.
751 * i386-tbl.h: Likewise.
752
73f07bff
AM		 7532017-03-06 Alan Modra <amodra@gmail.com>
754
755 PR 21124
756 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
757 (extract_raq, extract_ras, extract_rbx): New functions.
758 (powerpc_operands): Use opposite corresponding insert function.
759 (Q_MASK): Define.
760 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
761 register restriction.
762
65b48a81
PB		 7632017-02-28 Peter Bergner <bergner@vnet.ibm.com>
764
765 * disassemble.c Include "safe-ctype.h".
766 (disassemble_init_for_target): Handle s390 init.
767 (remove_whitespace_and_extra_commas): New function.
768 (disassembler_options_cmp): Likewise.
769 * arm-dis.c: Include "libiberty.h".
770 (NUM_ELEM): Delete.
771 (regnames): Use long disassembler style names.
772 Add force-thumb and no-force-thumb options.
773 (NUM_ARM_REGNAMES): Rename from this...
774 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
775 (get_arm_regname_num_options): Delete.
776 (set_arm_regname_option): Likewise.
777 (get_arm_regnames): Likewise.
778 (parse_disassembler_options): Likewise.
779 (parse_arm_disassembler_option): Rename from this...
780 (parse_arm_disassembler_options): ...to this. Make static.
781 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
782 (print_insn): Use parse_arm_disassembler_options.
783 (disassembler_options_arm): New function.
784 (print_arm_disassembler_options): Handle updated regnames.
785 * ppc-dis.c: Include "libiberty.h".
786 (ppc_opts): Add "32" and "64" entries.
787 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
788 (powerpc_init_dialect): Add break to switch statement.
789 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
790 (disassembler_options_powerpc): New function.
791 (print_ppc_disassembler_options): Use ARRAY_SIZE.
792 Remove printing of "32" and "64".
793 * s390-dis.c: Include "libiberty.h".
794 (init_flag): Remove unneeded variable.
795 (struct s390_options_t): New structure type.
796 (options): New structure.
797 (init_disasm): Rename from this...
798 (disassemble_init_s390): ...to this. Add initializations for
799 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
800 (print_insn_s390): Delete call to init_disasm.
801 (disassembler_options_s390): New function.
802 (print_s390_disassembler_options): Print using information from
803 struct 'options'.
804 * po/opcodes.pot: Regenerate.
805
15c7c1d8
JB		 8062017-02-28 Jan Beulich <jbeulich@suse.com>
807
808 * i386-dis.c (PCMPESTR_Fixup): New.
809 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
810 (prefix_table): Use PCMPESTR_Fixup.
811 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
812 PCMPESTR_Fixup.
813 (vex_w_table): Delete VPCMPESTR{I,M} entries.
814 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
815 Split 64-bit and non-64-bit variants.
816 * opcodes/i386-tbl.h: Re-generate.
817
582e12bf
RS		 8182017-02-24 Richard Sandiford <richard.sandiford@arm.com>
819
820 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
821 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
822 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
823 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
824 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
825 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
826 (OP_SVE_V_HSD): New macros.
827 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
828 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
829 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
830 (aarch64_opcode_table): Add new SVE instructions.
831 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
832 for rotation operands. Add new SVE operands.
833 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
834 (ins_sve_quad_index): Likewise.
835 (ins_imm_rotate): Split into...
836 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
837 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
838 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
839 functions.
840 (aarch64_ins_sve_addr_ri_s4): New function.
841 (aarch64_ins_sve_quad_index): Likewise.
842 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
843 * aarch64-asm-2.c: Regenerate.
844 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
845 (ext_sve_quad_index): Likewise.
846 (ext_imm_rotate): Split into...
847 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
848 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
849 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
850 functions.
851 (aarch64_ext_sve_addr_ri_s4): New function.
852 (aarch64_ext_sve_quad_index): Likewise.
853 (aarch64_ext_sve_index): Allow quad indices.
854 (do_misc_decoding): Likewise.
855 * aarch64-dis-2.c: Regenerate.
856 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
857 aarch64_field_kinds.
858 (OPD_F_OD_MASK): Widen by one bit.
859 (OPD_F_NO_ZR): Bump accordingly.
860 (get_operand_field_width): New function.
861 * aarch64-opc.c (fields): Add new SVE fields.
862 (operand_general_constraint_met_p): Handle new SVE operands.
863 (aarch64_print_operand): Likewise.
864 * aarch64-opc-2.c: Regenerate.
865
f482d304
RS		 8662017-02-24 Richard Sandiford <richard.sandiford@arm.com>
867
868 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
869 (aarch64_feature_compnum): ...this.
870 (SIMD_V8_3): Replace with...
871 (COMPNUM): ...this.
872 (CNUM_INSN): New macro.
873 (aarch64_opcode_table): Use it for the complex number instructions.
874
7db2c588
JB		 8752017-02-24 Jan Beulich <jbeulich@suse.com>
876
877 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
878
1e9d41d4
SL		 8792017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
880
881 Add support for associating SPARC ASIs with an architecture level.
882 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
883 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
884 decoding of SPARC ASIs.
885
53c4d625
JB		 8862017-02-23 Jan Beulich <jbeulich@suse.com>
887
888 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
889 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
890
11648de5
JB		 8912017-02-21 Jan Beulich <jbeulich@suse.com>
892
893 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
894 1 (instead of to itself). Correct typo.
895
f98d33be
AW		 8962017-02-14 Andrew Waterman <andrew@sifive.com>
897
898 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
899 pseudoinstructions.
900
773fb663
RS		 9012017-02-15 Richard Sandiford <richard.sandiford@arm.com>
902
903 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
904 (aarch64_sys_reg_supported_p): Handle them.
905
cc07cda6
CZ		 9062017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
907
908 * arc-opc.c (UIMM6_20R): Define.
909 (SIMM12_20): Use above.
910 (SIMM12_20R): Define.
911 (SIMM3_5_S): Use above.
912 (UIMM7_A32_11R_S): Define.
913 (UIMM7_9_S): Use above.
914 (UIMM3_13R_S): Define.
915 (SIMM11_A32_7_S): Use above.
916 (SIMM9_8R): Define.
917 (UIMM10_A32_8_S): Use above.
918 (UIMM8_8R_S): Define.
919 (W6): Use above.
920 (arc_relax_opcodes): Use all above defines.
921
66a5a740
VG		 9222017-02-15 Vineet Gupta <vgupta@synopsys.com>
923
924 * arc-regs.h: Distinguish some of the registers different on
925 ARC700 and HS38 cpus.
926
7e0de605
AM		 9272017-02-14 Alan Modra <amodra@gmail.com>
928
929 PR 21118
930 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
931 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
932
54064fdb
AM		 9332017-02-11 Stafford Horne <shorne@gmail.com>
934 Alan Modra <amodra@gmail.com>
935
936 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
937 Use insn_bytes_value and insn_int_value directly instead. Don't
938 free allocated memory until function exit.
939
dce75bf9
NP		 9402017-02-10 Nicholas Piggin <npiggin@gmail.com>
941
942 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
943
1b7e3d2f
NC		 9442017-02-03 Nick Clifton <nickc@redhat.com>
945
946 PR 21096
947 * aarch64-opc.c (print_register_list): Ensure that the register
948 list index will fir into the tb buffer.
949 (print_register_offset_address): Likewise.
950 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
951
8ec5cf65
AD		 9522017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
953
954 PR 21056
955 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
956 instructions when the previous fetch packet ends with a 32-bit
957 instruction.
958
a1aa5e81
DD		 9592017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
960
961 * pru-opc.c: Remove vague reference to a future GDB port.
962
add3afb2
NC		 9632017-01-20 Nick Clifton <nickc@redhat.com>
964
965 * po/ga.po: Updated Irish translation.
966
c13a63b0
SN		 9672017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
968
969 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
970
9608051a
YQ		 9712017-01-13 Yao Qi <yao.qi@linaro.org>
972
973 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
974 if FETCH_DATA returns 0.
975 (m68k_scan_mask): Likewise.
976 (print_insn_m68k): Update code to handle -1 return value.
977
f622ea96
YQ		 9782017-01-13 Yao Qi <yao.qi@linaro.org>
979
980 * m68k-dis.c (enum print_insn_arg_error): New.
981 (NEXTBYTE): Replace -3 with
982 PRINT_INSN_ARG_MEMORY_ERROR.
983 (NEXTULONG): Likewise.
984 (NEXTSINGLE): Likewise.
985 (NEXTDOUBLE): Likewise.
986 (NEXTDOUBLE): Likewise.
987 (NEXTPACKED): Likewise.
988 (FETCH_ARG): Likewise.
989 (FETCH_DATA): Update comments.
990 (print_insn_arg): Update comments. Replace magic numbers with
991 enum.
992 (match_insn_m68k): Likewise.
993
620214f7
IT		 9942017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
995
996 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
997 * i386-dis-evex.h (evex_table): Updated.
998 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
999 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1000 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1001 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1002 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1003 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1004 * i386-init.h: Regenerate.
1005 * i386-tbl.h: Ditto.
1006
d95014a2
YQ		 10072017-01-12 Yao Qi <yao.qi@linaro.org>
1008
1009 * msp430-dis.c (msp430_singleoperand): Return -1 if
1010 msp430dis_opcode_signed returns false.
1011 (msp430_doubleoperand): Likewise.
1012 (msp430_branchinstr): Return -1 if
1013 msp430dis_opcode_unsigned returns false.
1014 (msp430x_calla_instr): Likewise.
1015 (print_insn_msp430): Likewise.
1016
0ae60c3e
NC		 10172017-01-05 Nick Clifton <nickc@redhat.com>
1018
1019 PR 20946
1020 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1021 could not be matched.
1022 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1023 NULL.
1024
d74d4880
SN		 10252017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1026
1027 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1028 (aarch64_opcode_table): Use RCPC_INSN.
1029
cc917fd9
KC		 10302017-01-03 Kito Cheng <kito.cheng@gmail.com>
1031
1032 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1033 extension.
1034 * riscv-opcodes/all-opcodes: Likewise.
1035
b52d3cfc
DP		 10362017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1037
1038 * riscv-dis.c (print_insn_args): Add fall through comment.
1039
f90c58d5
NC		 10402017-01-03 Nick Clifton <nickc@redhat.com>
1041
1042 * po/sr.po: New Serbian translation.
1043 * configure.ac (ALL_LINGUAS): Add sr.
1044 * configure: Regenerate.
1045
f47b0d4a
AM		 10462017-01-02 Alan Modra <amodra@gmail.com>
1047
1048 * epiphany-desc.h: Regenerate.
1049 * epiphany-opc.h: Regenerate.
1050 * fr30-desc.h: Regenerate.
1051 * fr30-opc.h: Regenerate.
1052 * frv-desc.h: Regenerate.
1053 * frv-opc.h: Regenerate.
1054 * ip2k-desc.h: Regenerate.
1055 * ip2k-opc.h: Regenerate.
1056 * iq2000-desc.h: Regenerate.
1057 * iq2000-opc.h: Regenerate.
1058 * lm32-desc.h: Regenerate.
1059 * lm32-opc.h: Regenerate.
1060 * m32c-desc.h: Regenerate.
1061 * m32c-opc.h: Regenerate.
1062 * m32r-desc.h: Regenerate.
1063 * m32r-opc.h: Regenerate.
1064 * mep-desc.h: Regenerate.
1065 * mep-opc.h: Regenerate.
1066 * mt-desc.h: Regenerate.
1067 * mt-opc.h: Regenerate.
1068 * or1k-desc.h: Regenerate.
1069 * or1k-opc.h: Regenerate.
1070 * xc16x-desc.h: Regenerate.
1071 * xc16x-opc.h: Regenerate.
1072 * xstormy16-desc.h: Regenerate.
1073 * xstormy16-opc.h: Regenerate.
1074
2571583a
AM		 10752017-01-02 Alan Modra <amodra@gmail.com>
1076
1077 Update year range in copyright notice of all files.
1078
5c1ad6b5 1079For older changes see ChangeLog-2016
3499769a 1080\f
5c1ad6b5 1081Copyright (C) 2017 Free Software Foundation, Inc.
3499769a
AM		 1082
1083Copying and distribution of this file, with or without modification,
1084are permitted in any medium without royalty provided the copyright
1085notice and this notice are preserved.
1086
1087Local Variables:
1088mode: change-log
1089left-margin: 8
1090fill-column: 74
1091version-control: never
1092End:
A mirror of the official binutils-gdb repository