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gdb/fortran: test case modified to suit the clang behavior.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
a680affc
NC		 12021-05-11 Nick Clifton <nickc@redhat.com>
2
3 PR 27840
4 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
5 the end of the code buffer.
6
0b3e14c9
SH		 72021-05-06 Stafford Horne <shorne@gmail.com>
8
9 PR 21464
10 * or1k-asm.c: Regenerate.
11
6aee2cb2
MF		 122021-05-01 Max Filippov <jcmvbkbc@gmail.com>
13
14 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
15 info->insn_info_valid.
16
fe134c65
JB		 172021-04-26 Jan Beulich <jbeulich@suse.com>
18
19 * i386-opc.tbl (lea): Add Optimize.
20 * opcodes/i386-tbl.h: Re-generate.
21
b3ea7639
MF		 222020-04-23 Max Filippov <jcmvbkbc@gmail.com>
23
24 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
25 of l32r fetch and display referenced literal value.
26
c1cbb7d8
MF		 272021-04-23 Max Filippov <jcmvbkbc@gmail.com>
28
29 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
30 to 4 for literal disassembly.
31
02202574
PW		 322021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
33
34 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
35 for TLBI instruction.
36
cd6608e4
PW		 372021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
38
39 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
40 DC instruction.
41
fe1640ff
JB		 422021-04-19 Jan Beulich <jbeulich@suse.com>
43
44 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
45 "qualifier".
46 (convert_mov_to_movewide): Add initializer for "value".
47
100e914d
PW		 482021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
49
50 * aarch64-opc.c: Add RME system registers.
51
a21b96dd
NC		 522021-04-16 Lifang Xia <lifang_xia@c-sky.com>
53
54 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
55 "addi d,CV,z" to "c.mv d,CV".
56
43e05cd4
AM		 572021-04-12 Alan Modra <amodra@gmail.com>
58
59 * configure.ac (--enable-checking): Add support.
60 * config.in: Regenerate.
61 * configure: Regenerate.
62
52efda82
TB		 632021-04-09 Tejas Belagod <tejas.belagod@arm.com>
64
65 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
66 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
67
c3f72de4
AM		 682021-04-09 Alan Modra <amodra@gmail.com>
69
70 * ppc-dis.c (struct dis_private): Add "special".
71 (POWERPC_DIALECT): Delete. Replace uses with..
72 (private_data): ..this. New inline function.
73 (disassemble_init_powerpc): Init "special" names.
74 (skip_optional_operands): Add is_pcrel arg, set when detecting R
75 field of prefix instructions.
76 (bsearch_reloc, print_got_plt): New functions.
77 (print_insn_powerpc): For pcrel instructions, print target address
78 and symbol if known, and decode plt and got loads too.
79
ce7d813a
AM		 802021-04-08 Alan Modra <amodra@gmail.com>
81
82 PR 27684
83 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
84
97bf40d8
AM		 852021-04-08 Alan Modra <amodra@gmail.com>
86
87 PR 27676
88 * ppc-opc.c (DCBT_EO): Move earlier.
89 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
90 (powerpc_operands): Add THCT and THDS entries.
91 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
92
a2e66773
AM		 932021-04-06 Alan Modra <amodra@gmail.com>
94
95 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
96 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
97 symbol_at_address_func.
98
ab2af25e
AM		 992021-04-05 Alan Modra <amodra@gmail.com>
100
101 * configure.ac: Don't check for limits.h, string.h, strings.h or
102 stdlib.h.
103 (AC_ISC_POSIX): Don't invoke.
104 * sysdep.h: Include stdlib.h and string.h unconditionally.
105 * i386-opc.h: Include limits.h unconditionally.
106 * wasm32-dis.c: Likewise.
107 * cgen-opc.c: Don't include alloca-conf.h.
108 * config.in: Regenerate.
109 * configure: Regenerate.
110
e9b095a5
ML		 1112021-04-01 Martin Liska <mliska@suse.cz>
112
113 * arm-dis.c (strneq): Remove strneq and use startswith.
114 * cr16-dis.c (print_insn_cr16): Likewise.
115 * score-dis.c (streq): Likewise.
116 (strneq): Likewise.
117 * score7-dis.c (strneq): Likewise.
118
1cb108e4
AM		 1192021-04-01 Alan Modra <amodra@gmail.com>
120
121 PR 27675
122 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
123
78933a4a
AM		 1242021-03-31 Alan Modra <amodra@gmail.com>
125
126 * sysdep.h (POISON_BFD_BOOLEAN): Define.
127 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
128 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
129 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
130 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
131 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
132 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
133 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
134 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
135 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
136 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
137 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
138 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
139 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
140 and TRUE with true throughout.
141
3dfb1b6d
AM		 1422021-03-31 Alan Modra <amodra@gmail.com>
143
144 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
145 * aarch64-dis.h: Likewise.
146 * aarch64-opc.c: Likewise.
147 * avr-dis.c: Likewise.
148 * csky-dis.c: Likewise.
149 * nds32-asm.c: Likewise.
150 * nds32-dis.c: Likewise.
151 * nfp-dis.c: Likewise.
152 * riscv-dis.c: Likewise.
153 * s12z-dis.c: Likewise.
154 * wasm32-dis.c: Likewise.
155
5e042380
JB		 1562021-03-30 Jan Beulich <jbeulich@suse.com>
157
158 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
159 (i386_seg_prefixes): New.
160 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
161 (i386_seg_prefixes): Declare.
162
34684862
JB		 1632021-03-30 Jan Beulich <jbeulich@suse.com>
164
165 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
166
6288d05f
JB		 1672021-03-30 Jan Beulich <jbeulich@suse.com>
168
169 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
170 * i386-reg.tbl (st): Move down.
171 (st(0)): Delete. Extend comment.
172 * i386-tbl.h: Re-generate.
173
bbe1eca6
JB		 1742021-03-29 Jan Beulich <jbeulich@suse.com>
175
176 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
177 (cmpsd): Move next to cmps.
178 (movsd): Move next to movs.
179 (cmpxchg16b): Move to separate section.
180 (fisttp, fisttpll): Likewise.
181 (monitor, mwait): Likewise.
182 * i386-tbl.h: Re-generate.
183
c8cad9d3
JB		 1842021-03-29 Jan Beulich <jbeulich@suse.com>
185
186 * i386-opc.tbl (psadbw): Add <sse2:comm>.
187 (vpsadbw): Add C.
188 * i386-tbl.h: Re-generate.
189
5cdaf100
JB		 1902021-03-29 Jan Beulich <jbeulich@suse.com>
191
192 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
193 pclmul, gfni): New templates. Use them wherever possible. Move
194 SSE4.1 pextrw into respective section.
195 * i386-tbl.h: Re-generate.
196
73e45eb2
JB		 1972021-03-29 Jan Beulich <jbeulich@suse.com>
198
199 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
200 strtoull(). Bump upper loop bound. Widen masks. Sanity check
201 "length".
202 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
203 Convert all of their uses to representation in opcode.
204
9df6f676
JB		 2052021-03-29 Jan Beulich <jbeulich@suse.com>
206
207 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
208 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
209 value of None. Shrink operands to 3 bits.
210
389d00a5
JB		 2112021-03-29 Jan Beulich <jbeulich@suse.com>
212
213 * i386-gen.c (process_i386_opcode_modifier): New parameter
214 "space".
215 (output_i386_opcode): New local variable "space". Adjust
216 process_i386_opcode_modifier() invocation.
217 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
218 invocation.
219 * i386-tbl.h: Re-generate.
220
63b4cc53
AM		 2212021-03-29 Alan Modra <amodra@gmail.com>
222
223 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
224 (fp_qualifier_p, get_data_pattern): Likewise.
225 (aarch64_get_operand_modifier_from_value): Likewise.
226 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
227 (operand_variant_qualifier_p): Likewise.
228 (qualifier_value_in_range_constraint_p): Likewise.
229 (aarch64_get_qualifier_esize): Likewise.
230 (aarch64_get_qualifier_nelem): Likewise.
231 (aarch64_get_qualifier_standard_value): Likewise.
232 (get_lower_bound, get_upper_bound): Likewise.
233 (aarch64_find_best_match, match_operands_qualifier): Likewise.
234 (aarch64_print_operand): Likewise.
235 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
236 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
237 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
238 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
239 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
240 (print_insn_tic6x): Likewise.
241
3d7d6c1b
AM		 2422021-03-29 Alan Modra <amodra@gmail.com>
243
244 * arc-dis.c (extract_operand_value): Correct NULL cast.
245 * frv-opc.h: Regenerate.
246
c3344b62
JB		 2472021-03-26 Jan Beulich <jbeulich@suse.com>
248
249 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
250 MMX form.
251 * i386-tbl.h: Re-generate.
252
efa30ac3
HAQ		 2532021-03-25 Abid Qadeer <abidh@codesourcery.com>
254
255 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
256 immediate in br.n instruction.
257
596a02ff
JB		 2582021-03-25 Jan Beulich <jbeulich@suse.com>
259
260 * i386-dis.c (XMGatherD, VexGatherD): New.
261 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
262 (print_insn): Check masking for S/G insns.
263 (OP_E_memory): New local variable check_gather. Extend mandatory
264 SIB check. Check register conflicts for (EVEX-encoded) gathers.
265 Extend check for disallowed 16-bit addressing.
266 (OP_VEX): New local variables modrm_reg and sib_index. Convert
267 if()s to switch(). Check register conflicts for (VEX-encoded)
268 gathers. Drop no longer reachable cases.
269 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
270 vgatherdp*.
271
53642852
JB		 2722021-03-25 Jan Beulich <jbeulich@suse.com>
273
274 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
275 zeroing-masking without masking.
276
c0e54661
JB		 2772021-03-25 Jan Beulich <jbeulich@suse.com>
278
279 * i386-opc.tbl (invlpgb): Fix multi-operand form.
280 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
281 single-operand forms as deprecated.
282 * i386-tbl.h: Re-generate.
283
5a403766
AM		 2842021-03-25 Alan Modra <amodra@gmail.com>
285
286 PR 27647
287 * ppc-opc.c (XLOCB_MASK): Delete.
288 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
289 XLBH_MASK.
290 (powerpc_opcodes): Accept a BH field on all extended forms of
291 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
292
9a182d04
JB		 2932021-03-24 Jan Beulich <jbeulich@suse.com>
294
295 * i386-gen.c (output_i386_opcode): Drop processing of
296 opcode_length. Calculate length from base_opcode. Adjust prefix
297 encoding determination.
298 (process_i386_opcodes): Drop output of fake opcode_length.
299 * i386-opc.h (struct insn_template): Drop opcode_length field.
300 * i386-opc.tbl: Drop opcode length field from all templates.
301 * i386-tbl.h: Re-generate.
302
35648716
JB		 3032021-03-24 Jan Beulich <jbeulich@suse.com>
304
305 * i386-gen.c (process_i386_opcode_modifier): Return void. New
306 parameter "prefix". Drop local variable "regular_encoding".
307 Record prefix setting / check for consistency.
308 (output_i386_opcode): Parse opcode_length and base_opcode
309 earlier. Derive prefix encoding. Drop no longer applicable
310 consistency checking. Adjust process_i386_opcode_modifier()
311 invocation.
312 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
313 invocation.
314 * i386-tbl.h: Re-generate.
315
31184569
JB		 3162021-03-24 Jan Beulich <jbeulich@suse.com>
317
318 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
319 check.
320 * i386-opc.h (Prefix_*): Move #define-s.
321 * i386-opc.tbl: Move pseudo prefix enumerator values to
322 extension opcode field. Introduce pseudopfx template.
323 * i386-tbl.h: Re-generate.
324
b933fa4b
JB		 3252021-03-23 Jan Beulich <jbeulich@suse.com>
326
327 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
328 comment.
329 * i386-tbl.h: Re-generate.
330
dac10fb0
JB		 3312021-03-23 Jan Beulich <jbeulich@suse.com>
332
333 * i386-opc.h (struct insn_template): Move cpu_flags field past
334 opcode_modifier one.
335 * i386-tbl.h: Re-generate.
336
441f6aca
JB		 3372021-03-23 Jan Beulich <jbeulich@suse.com>
338
339 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
340 * i386-opc.h (OpcodeSpace): New enumerator.
341 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
342 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
343 SPACE_XOP09, SPACE_XOP0A): ... respectively.
344 (struct i386_opcode_modifier): New field opcodespace. Shrink
345 opcodeprefix field.
346 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
347 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
348 OpcodePrefix uses.
349 * i386-tbl.h: Re-generate.
350
08dedd66
ML		 3512021-03-22 Martin Liska <mliska@suse.cz>
352
353 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
354 * arc-dis.c (parse_option): Likewise.
355 * arm-dis.c (parse_arm_disassembler_options): Likewise.
356 * cris-dis.c (print_with_operands): Likewise.
357 * h8300-dis.c (bfd_h8_disassemble): Likewise.
358 * i386-dis.c (print_insn): Likewise.
359 * ia64-gen.c (fetch_insn_class): Likewise.
360 (parse_resource_users): Likewise.
361 (in_iclass): Likewise.
362 (lookup_specifier): Likewise.
363 (insert_opcode_dependencies): Likewise.
364 * mips-dis.c (parse_mips_ase_option): Likewise.
365 (parse_mips_dis_option): Likewise.
366 * s390-dis.c (disassemble_init_s390): Likewise.
367 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
368
80d49d6a
KLC		 3692021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
370
371 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
372
7fce7ea9
PW		 3732021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
374
375 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
376 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
377
78c84bf9
AM		 3782021-03-12 Alan Modra <amodra@gmail.com>
379
380 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
381
fd1fd061
JB		 3822021-03-11 Jan Beulich <jbeulich@suse.com>
383
384 * i386-dis.c (OP_XMM): Re-order checks.
385
ac7a2311
JB		 3862021-03-11 Jan Beulich <jbeulich@suse.com>
387
388 * i386-dis.c (putop): Drop need_vex check when also checking
389 vex.evex.
390 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
391 checking vex.b.
392
da944c8a
JB		 3932021-03-11 Jan Beulich <jbeulich@suse.com>
394
395 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
396 checks. Move case label past broadcast check.
397
b763d508
JB		 3982021-03-10 Jan Beulich <jbeulich@suse.com>
399
400 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
401 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
402 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
403 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
404 EVEX_W_0F38C7_M_0_L_2): Delete.
405 (REG_EVEX_0F38C7_M_0_L_2): New.
406 (intel_operand_size): Handle VEX and EVEX the same for
407 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
408 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
409 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
410 vex_vsib_q_w_d_mode uses.
411 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
412 0F38A1, and 0F38A3 entries.
413 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
414 entry.
415 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
416 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
417 0F38A3 entries.
418
32e31ad7
JB		 4192021-03-10 Jan Beulich <jbeulich@suse.com>
420
421 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
422 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
423 MOD_VEX_0FXOP_09_12): Rename to ...
424 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
425 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
426 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
427 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
428 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
429 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
430 (reg_table): Adjust comments.
431 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
432 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
433 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
434 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
435 (vex_len_table): Adjust opcode 0A_12 entry.
436 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
437 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
438 (rm_table): Move hreset entry.
439
85ba7507
JB		 4402021-03-10 Jan Beulich <jbeulich@suse.com>
441
442 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
443 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
444 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
445 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
446 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
447 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
448 (get_valid_dis386): Also handle 512-bit vector length when
449 vectoring into vex_len_table[].
450 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
451 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
452 entries.
453 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
454 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
455 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
456 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
457 entries.
458
066f82b9
JB		 4592021-03-10 Jan Beulich <jbeulich@suse.com>
460
461 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
462 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
463 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
464 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
465 entries.
466 * i386-dis-evex-len.h (evex_len_table): Likewise.
467 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
468
fc681dd6
JB		 4692021-03-10 Jan Beulich <jbeulich@suse.com>
470
471 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
472 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
473 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
474 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
475 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
476 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
477 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
478 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
479 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
480 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
481 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
482 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
483 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
484 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
485 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
486 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
487 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
488 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
489 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
490 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
491 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
492 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
493 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
494 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
495 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
496 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
497 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
498 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
499 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
500 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
501 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
502 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
503 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
504 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
505 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
506 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
507 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
508 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
509 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
510 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
511 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
512 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
513 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
514 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
515 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
516 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
517 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
518 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
519 EVEX_W_0F3A43_L_n): New.
520 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
521 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
522 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
523 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
524 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
525 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
526 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
527 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
528 0F385B, 0F38C6, and 0F38C7 entries.
529 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
530 0F38C6 and 0F38C7.
531 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
532 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
533 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
534 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
535
13954a31
JB		 5362021-03-10 Jan Beulich <jbeulich@suse.com>
537
538 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
539 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
540 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
541 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
542 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
543 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
544 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
545 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
546 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
547 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
548 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
549 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
550 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
551 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
552 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
553 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
554 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
555 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
556 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
557 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
558 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
559 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
560 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
561 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
562 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
563 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
564 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
565 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
566 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
567 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
568 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
569 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
570 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
571 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
572 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
573 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
574 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
575 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
576 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
577 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
578 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
579 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
580 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
581 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
582 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
583 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
584 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
585 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
586 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
587 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
588 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
589 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
590 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
591 VEX_W_0F99_P_2_LEN_0): Delete.
592 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
593 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
594 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
595 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
596 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
597 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
598 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
599 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
600 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
601 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
602 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
603 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
604 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
605 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
606 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
607 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
608 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
609 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
610 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
611 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
612 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
613 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
614 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
615 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
616 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
617 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
618 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
619 (prefix_table): No longer link to vex_len_table[] for opcodes
620 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
621 0F92, 0F93, 0F98, and 0F99.
622 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
623 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
624 0F98, and 0F99.
625 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
626 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
627 0F98, and 0F99.
628 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
629 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
630 0F98, and 0F99.
631 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
632 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
633 0F98, and 0F99.
634
14d10c6c
JB		 6352021-03-10 Jan Beulich <jbeulich@suse.com>
636
637 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
638 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
639 REG_VEX_0F73_M_0 respectively.
640 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
641 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
642 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
643 MOD_VEX_0F73_REG_7): Delete.
644 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
645 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
646 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
647 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
648 PREFIX_VEX_0F3AF0_L_0 respectively.
649 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
650 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
651 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
652 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
653 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
654 VEX_LEN_0F38F7): New.
655 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
656 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
657 0F72, and 0F73. No longer link to vex_len_table[] for opcode
658 0F38F3.
659 (prefix_table): No longer link to vex_len_table[] for opcodes
660 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
661 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
662 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
663 0F38F6, 0F38F7, and 0F3AF0.
664 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
665 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
666 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
667 0F73.
668
00ec1875
JB		 6692021-03-10 Jan Beulich <jbeulich@suse.com>
670
671 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
672 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
673 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
674 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
675 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
676 (MOD_0F71, MOD_0F72, MOD_0F73): New.
677 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
678 73.
679 (reg_table): No longer link to mod_table[] for opcodes 0F71,
680 0F72, and 0F73.
681 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
682 0F73.
683
31941983
JB		 6842021-03-10 Jan Beulich <jbeulich@suse.com>
685
686 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
687 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
688 (reg_table): Don't link to mod_table[] where not needed. Add
689 PREFIX_IGNORED to nop entries.
690 (prefix_table): Replace PREFIX_OPCODE in nop entries.
691 (mod_table): Add nop entries next to prefetch ones. Drop
692 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
693 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
694 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
695 PREFIX_OPCODE from endbr* entries.
696 (get_valid_dis386): Also consider entry's name when zapping
697 vindex.
698 (print_insn): Handle PREFIX_IGNORED.
699
742732c7
JB		 7002021-03-09 Jan Beulich <jbeulich@suse.com>
701
702 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
703 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
704 element.
705 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
706 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
707 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
708 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
709 (struct i386_opcode_modifier): Delete notrackprefixok,
710 islockable, hleprefixok, and repprefixok fields. Add prefixok
711 field.
712 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
713 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
714 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
715 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
716 Replace HLEPrefixOk.
717 * opcodes/i386-tbl.h: Re-generate.
718
e93a3b27
JB		 7192021-03-09 Jan Beulich <jbeulich@suse.com>
720
721 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
722 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
723 64-bit form.
724 * opcodes/i386-tbl.h: Re-generate.
725
75363b6d
JB		 7262021-03-03 Jan Beulich <jbeulich@suse.com>
727
728 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
729 for {} instead of {0}. Don't look for '0'.
730 * i386-opc.tbl: Drop operand count field. Drop redundant operand
731 size specifiers.
732
5a9f5403
NC		 7332021-02-19 Nelson Chu <nelson.chu@sifive.com>
734
735 PR 27158
736 * riscv-dis.c (print_insn_args): Updated encoding macros.
737 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
738 (match_c_addi16sp): Updated encoding macros.
739 (match_c_lui): Likewise.
740 (match_c_lui_with_hint): Likewise.
741 (match_c_addi4spn): Likewise.
742 (match_c_slli): Likewise.
743 (match_slli_as_c_slli): Likewise.
744 (match_c_slli64): Likewise.
745 (match_srxi_as_c_srxi): Likewise.
746 (riscv_insn_types): Added .insn css/cl/cs.
747
3d73d29e
NC		 7482021-02-18 Nelson Chu <nelson.chu@sifive.com>
749
750 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
751 (default_priv_spec): Updated type to riscv_spec_class.
752 (parse_riscv_dis_option): Updated.
753 * riscv-opc.c: Moved stuff and make the file tidy.
754
b9b204b3
AM		 7552021-02-17 Alan Modra <amodra@gmail.com>
756
757 * wasm32-dis.c: Include limits.h.
758 (CHAR_BIT): Provide backup define.
759 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
760 Correct signed overflow checking.
761
394ae71f
JB		 7622021-02-16 Jan Beulich <jbeulich@suse.com>
763
764 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
765 * i386-tbl.h: Re-generate.
766
b818b220
JB		 7672021-02-16 Jan Beulich <jbeulich@suse.com>
768
769 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
770 Oword.
771 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
772
ba2b480f
AK		 7732021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
774
775 * s390-mkopc.c (main): Accept arch14 as cpu string.
776 * s390-opc.txt: Add new arch14 instructions.
777
95148614
NA		 7782021-02-04 Nick Alcock <nick.alcock@oracle.com>
779
780 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
781 favour of LIBINTL.
782 * configure: Regenerated.
783
bfd428bc
MF		 7842021-02-08 Mike Frysinger <vapier@gentoo.org>
785
786 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
787 * tic54x-opc.c (regs): Rename to ...
788 (tic54x_regs): ... this.
789 (mmregs): Rename to ...
790 (tic54x_mmregs): ... this.
791 (condition_codes): Rename to ...
792 (tic54x_condition_codes): ... this.
793 (cc2_codes): Rename to ...
794 (tic54x_cc2_codes): ... this.
795 (cc3_codes): Rename to ...
796 (tic54x_cc3_codes): ... this.
797 (status_bits): Rename to ...
798 (tic54x_status_bits): ... this.
799 (misc_symbols): Rename to ...
800 (tic54x_misc_symbols): ... this.
801
24075dcc
NC		 8022021-02-04 Nelson Chu <nelson.chu@sifive.com>
803
804 * riscv-opc.c (MASK_RVB_IMM): Removed.
805 (riscv_opcodes): Removed zb* instructions.
806 (riscv_ext_version_table): Removed versions for zb*.
807
c3ffb8f3
AM		 8082021-01-26 Alan Modra <amodra@gmail.com>
809
810 * i386-gen.c (parse_template): Ensure entire template_instance
811 is initialised.
812
1942a048
NC		 8132021-01-15 Nelson Chu <nelson.chu@sifive.com>
814
815 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
816 (riscv_fpr_names_abi): Likewise.
817 (riscv_opcodes): Likewise.
818 (riscv_insn_types): Likewise.
819
b800637e
NC		 8202021-01-15 Nelson Chu <nelson.chu@sifive.com>
821
822 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
823
dcd709e0
NC		 8242021-01-15 Nelson Chu <nelson.chu@sifive.com>
825
826 * riscv-dis.c: Comments tidy and improvement.
827 * riscv-opc.c: Likewise.
828
5347ed60
AM		 8292021-01-13 Alan Modra <amodra@gmail.com>
830
831 * Makefile.in: Regenerate.
832
d546b610
L		 8332021-01-12 H.J. Lu <hongjiu.lu@intel.com>
834
835 PR binutils/26792
836 * configure.ac: Use GNU_MAKE_JOBSERVER.
837 * aclocal.m4: Regenerated.
838 * configure: Likewise.
839
6d104cac
NC		 8402021-01-12 Nick Clifton <nickc@redhat.com>
841
842 * po/sr.po: Updated Serbian translation.
843
83b33c6c
L		 8442021-01-11 H.J. Lu <hongjiu.lu@intel.com>
845
846 PR ld/27173
847 * configure: Regenerated.
848
82c70b08
KT		 8492021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
850
851 * aarch64-asm-2.c: Regenerate.
852 * aarch64-dis-2.c: Likewise.
853 * aarch64-opc-2.c: Likewise.
854 * aarch64-opc.c (aarch64_print_operand):
855 Delete handling of AARCH64_OPND_CSRE_CSR.
856 * aarch64-tbl.h (aarch64_feature_csre): Delete.
857 (CSRE): Likewise.
858 (_CSRE_INSN): Likewise.
859 (aarch64_opcode_table): Delete csr.
860
a8aa72b9
NC		 8612021-01-11 Nick Clifton <nickc@redhat.com>
862
863 * po/de.po: Updated German translation.
864 * po/fr.po: Updated French translation.
865 * po/pt_BR.po: Updated Brazilian Portuguese translation.
866 * po/sv.po: Updated Swedish translation.
867 * po/uk.po: Updated Ukranian translation.
868
a4966cd9
L		 8692021-01-09 H.J. Lu <hongjiu.lu@intel.com>
870
871 * configure: Regenerated.
872
573fe3fb
NC		 8732021-01-09 Nick Clifton <nickc@redhat.com>
874
875 * configure: Regenerate.
876 * po/opcodes.pot: Regenerate.
877
055bc77a
NC		 8782021-01-09 Nick Clifton <nickc@redhat.com>
879
880 * 2.36 release branch crated.
881
aae7fcb8
PB		 8822021-01-08 Peter Bergner <bergner@linux.ibm.com>
883
884 * ppc-opc.c (insert_dw, (extract_dw): New functions.
885 (DW, (XRC_MASK): Define.
886 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
887
64307045
AM		 8882021-01-09 Alan Modra <amodra@gmail.com>
889
890 * configure: Regenerate.
891
ed205222
NC		 8922021-01-08 Nick Clifton <nickc@redhat.com>
893
894 * po/sv.po: Updated Swedish translation.
895
fb932b57
NC		 8962021-01-08 Nick Clifton <nickc@redhat.com>
897
e84c8716
NC		 898 PR 27129
899 * aarch64-dis.c (determine_disassembling_preference): Move call to
900 aarch64_match_operands_constraint outside of the assertion.
901 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
902 Replace with a return of FALSE.
903
fb932b57
NC		 904 PR 27139
905 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
906 core system register.
907
f4782128
ST		 9082021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
909
910 * configure: Regenerate.
911
1b0927db
NC		 9122021-01-07 Nick Clifton <nickc@redhat.com>
913
914 * po/fr.po: Updated French translation.
915
3b288c8e
FN		 9162021-01-07 Fredrik Noring <noring@nocrew.org>
917
918 * m68k-opc.c (chkl): Change minimum architecture requirement to
919 m68020.
920
aa881ecd
PT		 9212021-01-07 Philipp Tomsich <prt@gnu.org>
922
923 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
924
2652cfad
CXW		 9252021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
926 Jim Wilson <jimw@sifive.com>
927 Andrew Waterman <andrew@sifive.com>
928 Maxim Blinov <maxim.blinov@embecosm.com>
929 Kito Cheng <kito.cheng@sifive.com>
930 Nelson Chu <nelson.chu@sifive.com>
931
932 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
933 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
934
250d07de
AM		 9352021-01-01 Alan Modra <amodra@gmail.com>
936
937 Update year range in copyright notice of all files.
938
c2795844 939For older changes see ChangeLog-2020
3499769a 940\f
c2795844 941Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 942
943Copying and distribution of this file, with or without modification,
944are permitted in any medium without royalty provided the copyright
945notice and this notice are preserved.
946
947Local Variables:
948mode: change-log
949left-margin: 8
950fill-column: 74
951version-control: never
952End:
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