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[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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7060c28e
NC		 12021-11-25 Nick Clifton <nickc@redhat.com>
2
3 PR 28614
4 * aarch64-asm.c: Replace assert(0) with real code.
5 * aarch64-dis.c: Likewise.
6 * aarch64-opc.c: Likewise.
7
79abb939
NC		 82021-11-25 Nick Clifton <nickc@redhat.com>
9
10 * po/fr.po; Updated French translation.
11
2b677209
MR		 122021-10-27 Maciej W. Rozycki <macro@embecosm.com>
13
14 * Makefile.am: Remove obsolete comment.
15 * configure.ac: Refer `libbfd.la' to link shared BFD library
16 except for Cygwin.
17 * Makefile.in: Regenerate.
18 * configure: Regenerate.
19
b9004024
NA		 202021-09-27 Nick Alcock <nick.alcock@oracle.com>
21
22 * configure: Regenerate.
23
4d5d5d46
PB		 242021-09-25 Peter Bergner <bergner@linux.ibm.com>
25
26 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
27 on POWER5 and later.
28
6a7f5766
AB		 292021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
30
31 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
32 before an unknown instruction, '%d' is replaced with the
33 instruction length.
34
718aefcf
NC		 352021-09-02 Nick Clifton <nickc@redhat.com>
36
37 PR 28292
38 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
39 of BFD_RELOC_16.
40
5d9cff51
SV		 412021-08-17 Shahab Vahedi <shahab@synopsys.com>
42
43 * arc-regs.h (DEF): Fix the register numbers.
44
3ee0cd9e
NC		 452021-08-10 Nick Clifton <nickc@redhat.com>
46
47 * po/sr.po: Updated Serbian translation.
48
8d56b9fc
CX		 492021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
50
51 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
52
b180e829
AK		 532021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
54
55 * s390-opc.txt: Add qpaci.
56
346d80ef
NC		 572021-07-03 Nick Clifton <nickc@redhat.com>
58
59 * configure: Regenerate.
60 * po/opcodes.pot: Regenerate.
61
51419248
NC		 622021-07-03 Nick Clifton <nickc@redhat.com>
63
64 * 2.37 release branch created.
65
62194b63
AM		 662021-07-02 Alan Modra <amodra@gmail.com>
67
68 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
69 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
70 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
71 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
72 (nds32_keyword_gpr): Move declarations to..
73 * nds32-asm.h: ..here, constifying to match definitions.
74
2fe36d31
MF		 752021-07-01 Mike Frysinger <vapier@gentoo.org>
76
77 * Makefile.am (GUILE): New variable.
78 (CGEN): Use $(GUILE).
79 * Makefile.in: Regenerate.
80
f375d32b
MF		 812021-07-01 Mike Frysinger <vapier@gentoo.org>
82
83 * mep-asm.c (macros): Mark static & const.
84 (lookup_macro): Change return & m to const.
85 (expand_macro): Change mac to const.
86 (expand_string): Change pmacro to const.
87
9b2beaf7
MF		 882021-07-01 Mike Frysinger <vapier@gentoo.org>
89
90 * nds32-asm.c (operand_fields): Rename to ...
91 (nds32_operand_fields): ... this.
92 (keyword_gpr): Rename to ...
93 (nds32_keyword_gpr): ... this.
94 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
95 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
96 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
97 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
98 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
99 Mark static.
100 (keywords): Rename to ...
101 (nds32_keywords): ... this.
102 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
103 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
104
ac8ef696
MF		 1052021-07-01 Mike Frysinger <vapier@gentoo.org>
106
107 * z80-dis.c (opc_ed): Make const.
108 (pref_ed): Make p const.
109
52b83874
MF		 1102021-07-01 Mike Frysinger <vapier@gentoo.org>
111
112 * microblaze-dis.c (get_field_special): Make op const.
113 (read_insn_microblaze): Make opr & op const. Rename opcodes to
114 microblaze_opcodes.
115 (print_insn_microblaze): Make op & pop const.
116 (get_insn_microblaze): Make op const. Rename opcodes to
117 microblaze_opcodes.
118 (microblaze_get_target_address): Likewise.
119 * microblaze-opc.h (struct op_code_struct): Make const.
120 Rename opcodes to microblaze_opcodes.
121
6c2ede01
MF		 1222021-07-01 Mike Frysinger <vapier@gentoo.org>
123
124 * aarch64-gen.c (aarch64_opcode_table): Add const.
125 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
126
46b8b3d6
AB		 1272021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
128
129 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
130 available.
131
ded5cb94
AM		 1322021-06-22 Alan Modra <amodra@gmail.com>
133
134 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
135 print separator for pcrel insns.
136
47399e9c
AM		 1372021-06-19 Alan Modra <amodra@gmail.com>
138
139 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
140
d984392e
AM		 1412021-06-19 Alan Modra <amodra@gmail.com>
142
143 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
144 entire buffer.
145
7993124e
AM		 1462021-06-17 Alan Modra <amodra@gmail.com>
147
148 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
149 in table.
150
a38d1396
AM		 1512021-06-03 Alan Modra <amodra@gmail.com>
152
153 PR 1202
154 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
155 Use unsigned int for inst.
156
8f467114
SV		 1572021-06-02 Shahab Vahedi <shahab@synopsys.com>
158
159 * arc-dis.c (arc_option_arg_t): New enumeration.
160 (arc_options): New variable.
161 (disassembler_options_arc): New function.
162 (print_arc_disassembler_options): Reimplement in terms of
163 "disassembler_options_arc".
164
1ff6a3b8
AM		 1652021-05-29 Alan Modra <amodra@gmail.com>
166
167 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
168 Don't special case PPC_OPCODE_RAW.
169 (lookup_prefix): Likewise.
170 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
171 (print_insn_powerpc): ..update caller.
172 * ppc-opc.c (EXT): Define.
173 (powerpc_opcodes): Mark extended mnemonics with EXT.
174 (prefix_opcodes, vle_opcodes): Likewise.
175 (XISEL, XISEL_MASK): Add cr field and simplify.
176 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
177 all isel variants to where the base mnemonic belongs. Sort dstt,
178 dststt and dssall.
179
49149d59
MR		 1802021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
181
182 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
183 COP3 opcode instructions.
184
9573a461
MR		 1852021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
186
187 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
188 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
189 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
190 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
191 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
192 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
193 "cop2", and "cop3" entries.
194
fa495743
MR		 1952021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
196
197 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
198 entries and associated comments.
199
b930964c
MR		 2002021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
201
202 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
203 of "c0".
204
dd844468
MR		 2052021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
206
207 * mips-dis.c (mips_cp1_names_mips): New variable.
208 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
209 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
210 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
211 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
212 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
213 "loongson2f".
214
9204ccd4
MR		 2152021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
216
217 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
218 handling code over to...
219 <OP_REG_CONTROL>: ... this new case.
220 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
221 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
222 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
223 replacing the `G' operand code with `g'. Update "cftc1" and
224 "cftc2" entries replacing the `E' operand code with `y'.
225 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
226 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
227 entries replacing the `G' operand code with `g'.
228
a3fb396f
MR		 2292021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
230
231 * mips-dis.c (mips_cp0_names_r3900): New variable.
232 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
233 for "r3900".
234
cccc84fa
MR		 2352021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
236
237 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
238 and "mtthc2" to using the `G' rather than `g' operand code for
239 the coprocessor control register referred.
240
c9de3168
MR		 2412021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
242
243 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
244 entries with each other.
245
ebcab741
PB		 2462021-05-27 Peter Bergner <bergner@linux.ibm.com>
247
248 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
249
bc30a119
AM		 2502021-05-25 Alan Modra <amodra@gmail.com>
251
252 * cris-desc.c: Regenerate.
253 * cris-desc.h: Regenerate.
254 * cris-opc.h: Regenerate.
255 * po/POTFILES.in: Regenerate.
256
54711280
MF		 2572021-05-24 Mike Frysinger <vapier@gentoo.org>
258
259 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
260 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
261 (CGEN_CPUS): Add cris.
262 (CRIS_DEPS): Define.
263 (stamp-cris): New rule.
264 * cgen.sh: Handle desc action.
265 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
266 * Makefile.in, configure: Regenerate.
267
113bb761
JN		 2682021-05-18 Job Noorman <mtvec@pm.me>
269
270 PR 27814
271 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
272 the elf objects.
273
e683cb41
AC		 2742021-05-17 Alex Coplan <alex.coplan@arm.com>
275
276 * arm-dis.c (mve_opcodes): Fix disassembly of
277 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
278 (is_mve_encoding_conflict): MVE vector loads should not match
279 when P = W = 0.
280 (is_mve_unpredictable): It's not unpredictable to use the same
281 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
282
a680affc
NC		 2832021-05-11 Nick Clifton <nickc@redhat.com>
284
285 PR 27840
286 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
287 the end of the code buffer.
288
0b3e14c9
SH		 2892021-05-06 Stafford Horne <shorne@gmail.com>
290
291 PR 21464
292 * or1k-asm.c: Regenerate.
293
6aee2cb2
MF		 2942021-05-01 Max Filippov <jcmvbkbc@gmail.com>
295
296 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
297 info->insn_info_valid.
298
fe134c65
JB		 2992021-04-26 Jan Beulich <jbeulich@suse.com>
300
301 * i386-opc.tbl (lea): Add Optimize.
302 * opcodes/i386-tbl.h: Re-generate.
303
b3ea7639
MF		 3042020-04-23 Max Filippov <jcmvbkbc@gmail.com>
305
306 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
307 of l32r fetch and display referenced literal value.
308
c1cbb7d8
MF		 3092021-04-23 Max Filippov <jcmvbkbc@gmail.com>
310
311 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
312 to 4 for literal disassembly.
313
02202574
PW		 3142021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
315
316 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
317 for TLBI instruction.
318
cd6608e4
PW		 3192021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
320
321 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
322 DC instruction.
323
fe1640ff
JB		 3242021-04-19 Jan Beulich <jbeulich@suse.com>
325
326 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
327 "qualifier".
328 (convert_mov_to_movewide): Add initializer for "value".
329
100e914d
PW		 3302021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
331
332 * aarch64-opc.c: Add RME system registers.
333
a21b96dd
NC		 3342021-04-16 Lifang Xia <lifang_xia@c-sky.com>
335
336 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
337 "addi d,CV,z" to "c.mv d,CV".
338
43e05cd4
AM		 3392021-04-12 Alan Modra <amodra@gmail.com>
340
341 * configure.ac (--enable-checking): Add support.
342 * config.in: Regenerate.
343 * configure: Regenerate.
344
52efda82
TB		 3452021-04-09 Tejas Belagod <tejas.belagod@arm.com>
346
347 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
348 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
349
c3f72de4
AM		 3502021-04-09 Alan Modra <amodra@gmail.com>
351
352 * ppc-dis.c (struct dis_private): Add "special".
353 (POWERPC_DIALECT): Delete. Replace uses with..
354 (private_data): ..this. New inline function.
355 (disassemble_init_powerpc): Init "special" names.
356 (skip_optional_operands): Add is_pcrel arg, set when detecting R
357 field of prefix instructions.
358 (bsearch_reloc, print_got_plt): New functions.
359 (print_insn_powerpc): For pcrel instructions, print target address
360 and symbol if known, and decode plt and got loads too.
361
ce7d813a
AM		 3622021-04-08 Alan Modra <amodra@gmail.com>
363
364 PR 27684
365 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
366
97bf40d8
AM		 3672021-04-08 Alan Modra <amodra@gmail.com>
368
369 PR 27676
370 * ppc-opc.c (DCBT_EO): Move earlier.
371 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
372 (powerpc_operands): Add THCT and THDS entries.
373 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
374
a2e66773
AM		 3752021-04-06 Alan Modra <amodra@gmail.com>
376
377 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
378 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
379 symbol_at_address_func.
380
ab2af25e
AM		 3812021-04-05 Alan Modra <amodra@gmail.com>
382
383 * configure.ac: Don't check for limits.h, string.h, strings.h or
384 stdlib.h.
385 (AC_ISC_POSIX): Don't invoke.
386 * sysdep.h: Include stdlib.h and string.h unconditionally.
387 * i386-opc.h: Include limits.h unconditionally.
388 * wasm32-dis.c: Likewise.
389 * cgen-opc.c: Don't include alloca-conf.h.
390 * config.in: Regenerate.
391 * configure: Regenerate.
392
e9b095a5
ML		 3932021-04-01 Martin Liska <mliska@suse.cz>
394
395 * arm-dis.c (strneq): Remove strneq and use startswith.
396 * cr16-dis.c (print_insn_cr16): Likewise.
397 * score-dis.c (streq): Likewise.
398 (strneq): Likewise.
399 * score7-dis.c (strneq): Likewise.
400
1cb108e4
AM		 4012021-04-01 Alan Modra <amodra@gmail.com>
402
403 PR 27675
404 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
405
78933a4a
AM		 4062021-03-31 Alan Modra <amodra@gmail.com>
407
408 * sysdep.h (POISON_BFD_BOOLEAN): Define.
409 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
410 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
411 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
412 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
413 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
414 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
415 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
416 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
417 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
418 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
419 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
420 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
421 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
422 and TRUE with true throughout.
423
3dfb1b6d
AM		 4242021-03-31 Alan Modra <amodra@gmail.com>
425
426 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
427 * aarch64-dis.h: Likewise.
428 * aarch64-opc.c: Likewise.
429 * avr-dis.c: Likewise.
430 * csky-dis.c: Likewise.
431 * nds32-asm.c: Likewise.
432 * nds32-dis.c: Likewise.
433 * nfp-dis.c: Likewise.
434 * riscv-dis.c: Likewise.
435 * s12z-dis.c: Likewise.
436 * wasm32-dis.c: Likewise.
437
5e042380
JB		 4382021-03-30 Jan Beulich <jbeulich@suse.com>
439
440 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
441 (i386_seg_prefixes): New.
442 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
443 (i386_seg_prefixes): Declare.
444
34684862
JB		 4452021-03-30 Jan Beulich <jbeulich@suse.com>
446
447 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
448
6288d05f
JB		 4492021-03-30 Jan Beulich <jbeulich@suse.com>
450
451 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
452 * i386-reg.tbl (st): Move down.
453 (st(0)): Delete. Extend comment.
454 * i386-tbl.h: Re-generate.
455
bbe1eca6
JB		 4562021-03-29 Jan Beulich <jbeulich@suse.com>
457
458 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
459 (cmpsd): Move next to cmps.
460 (movsd): Move next to movs.
461 (cmpxchg16b): Move to separate section.
462 (fisttp, fisttpll): Likewise.
463 (monitor, mwait): Likewise.
464 * i386-tbl.h: Re-generate.
465
c8cad9d3
JB		 4662021-03-29 Jan Beulich <jbeulich@suse.com>
467
468 * i386-opc.tbl (psadbw): Add <sse2:comm>.
469 (vpsadbw): Add C.
470 * i386-tbl.h: Re-generate.
471
5cdaf100
JB		 4722021-03-29 Jan Beulich <jbeulich@suse.com>
473
474 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
475 pclmul, gfni): New templates. Use them wherever possible. Move
476 SSE4.1 pextrw into respective section.
477 * i386-tbl.h: Re-generate.
478
73e45eb2
JB		 4792021-03-29 Jan Beulich <jbeulich@suse.com>
480
481 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
482 strtoull(). Bump upper loop bound. Widen masks. Sanity check
483 "length".
484 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
485 Convert all of their uses to representation in opcode.
486
9df6f676
JB		 4872021-03-29 Jan Beulich <jbeulich@suse.com>
488
489 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
490 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
491 value of None. Shrink operands to 3 bits.
492
389d00a5
JB		 4932021-03-29 Jan Beulich <jbeulich@suse.com>
494
495 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 496 "space".
389d00a5
JB		 497 (output_i386_opcode): New local variable "space". Adjust
498 process_i386_opcode_modifier() invocation.
499 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
500 invocation.
501 * i386-tbl.h: Re-generate.
502
63b4cc53
AM		 5032021-03-29 Alan Modra <amodra@gmail.com>
504
505 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
506 (fp_qualifier_p, get_data_pattern): Likewise.
507 (aarch64_get_operand_modifier_from_value): Likewise.
508 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
509 (operand_variant_qualifier_p): Likewise.
510 (qualifier_value_in_range_constraint_p): Likewise.
511 (aarch64_get_qualifier_esize): Likewise.
512 (aarch64_get_qualifier_nelem): Likewise.
513 (aarch64_get_qualifier_standard_value): Likewise.
514 (get_lower_bound, get_upper_bound): Likewise.
515 (aarch64_find_best_match, match_operands_qualifier): Likewise.
516 (aarch64_print_operand): Likewise.
517 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
518 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
519 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
520 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
521 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
522 (print_insn_tic6x): Likewise.
523
3d7d6c1b
AM		 5242021-03-29 Alan Modra <amodra@gmail.com>
525
526 * arc-dis.c (extract_operand_value): Correct NULL cast.
527 * frv-opc.h: Regenerate.
528
c3344b62
JB		 5292021-03-26 Jan Beulich <jbeulich@suse.com>
530
531 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
532 MMX form.
533 * i386-tbl.h: Re-generate.
534
efa30ac3
HAQ		 5352021-03-25 Abid Qadeer <abidh@codesourcery.com>
536
537 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
538 immediate in br.n instruction.
539
596a02ff
JB		 5402021-03-25 Jan Beulich <jbeulich@suse.com>
541
542 * i386-dis.c (XMGatherD, VexGatherD): New.
543 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
544 (print_insn): Check masking for S/G insns.
545 (OP_E_memory): New local variable check_gather. Extend mandatory
546 SIB check. Check register conflicts for (EVEX-encoded) gathers.
547 Extend check for disallowed 16-bit addressing.
548 (OP_VEX): New local variables modrm_reg and sib_index. Convert
549 if()s to switch(). Check register conflicts for (VEX-encoded)
550 gathers. Drop no longer reachable cases.
551 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
552 vgatherdp*.
553
53642852
JB		 5542021-03-25 Jan Beulich <jbeulich@suse.com>
555
556 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
557 zeroing-masking without masking.
558
c0e54661
JB		 5592021-03-25 Jan Beulich <jbeulich@suse.com>
560
561 * i386-opc.tbl (invlpgb): Fix multi-operand form.
562 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
563 single-operand forms as deprecated.
564 * i386-tbl.h: Re-generate.
565
5a403766
AM		 5662021-03-25 Alan Modra <amodra@gmail.com>
567
568 PR 27647
569 * ppc-opc.c (XLOCB_MASK): Delete.
570 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
571 XLBH_MASK.
572 (powerpc_opcodes): Accept a BH field on all extended forms of
573 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
574
9a182d04
JB		 5752021-03-24 Jan Beulich <jbeulich@suse.com>
576
577 * i386-gen.c (output_i386_opcode): Drop processing of
578 opcode_length. Calculate length from base_opcode. Adjust prefix
579 encoding determination.
580 (process_i386_opcodes): Drop output of fake opcode_length.
581 * i386-opc.h (struct insn_template): Drop opcode_length field.
582 * i386-opc.tbl: Drop opcode length field from all templates.
583 * i386-tbl.h: Re-generate.
584
35648716
JB		 5852021-03-24 Jan Beulich <jbeulich@suse.com>
586
587 * i386-gen.c (process_i386_opcode_modifier): Return void. New
588 parameter "prefix". Drop local variable "regular_encoding".
589 Record prefix setting / check for consistency.
590 (output_i386_opcode): Parse opcode_length and base_opcode
591 earlier. Derive prefix encoding. Drop no longer applicable
592 consistency checking. Adjust process_i386_opcode_modifier()
593 invocation.
594 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
595 invocation.
596 * i386-tbl.h: Re-generate.
597
31184569
JB		 5982021-03-24 Jan Beulich <jbeulich@suse.com>
599
600 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
601 check.
602 * i386-opc.h (Prefix_*): Move #define-s.
603 * i386-opc.tbl: Move pseudo prefix enumerator values to
604 extension opcode field. Introduce pseudopfx template.
605 * i386-tbl.h: Re-generate.
606
b933fa4b
JB		 6072021-03-23 Jan Beulich <jbeulich@suse.com>
608
609 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
610 comment.
611 * i386-tbl.h: Re-generate.
612
dac10fb0
JB		 6132021-03-23 Jan Beulich <jbeulich@suse.com>
614
615 * i386-opc.h (struct insn_template): Move cpu_flags field past
616 opcode_modifier one.
617 * i386-tbl.h: Re-generate.
618
441f6aca
JB		 6192021-03-23 Jan Beulich <jbeulich@suse.com>
620
621 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
622 * i386-opc.h (OpcodeSpace): New enumerator.
623 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
624 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
625 SPACE_XOP09, SPACE_XOP0A): ... respectively.
626 (struct i386_opcode_modifier): New field opcodespace. Shrink
627 opcodeprefix field.
628 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
629 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
630 OpcodePrefix uses.
631 * i386-tbl.h: Re-generate.
632
08dedd66
ML		 6332021-03-22 Martin Liska <mliska@suse.cz>
634
635 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
636 * arc-dis.c (parse_option): Likewise.
637 * arm-dis.c (parse_arm_disassembler_options): Likewise.
638 * cris-dis.c (print_with_operands): Likewise.
639 * h8300-dis.c (bfd_h8_disassemble): Likewise.
640 * i386-dis.c (print_insn): Likewise.
641 * ia64-gen.c (fetch_insn_class): Likewise.
642 (parse_resource_users): Likewise.
643 (in_iclass): Likewise.
644 (lookup_specifier): Likewise.
645 (insert_opcode_dependencies): Likewise.
646 * mips-dis.c (parse_mips_ase_option): Likewise.
647 (parse_mips_dis_option): Likewise.
648 * s390-dis.c (disassemble_init_s390): Likewise.
649 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
650
80d49d6a
KLC		 6512021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
652
653 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
654
7fce7ea9
PW		 6552021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
656
657 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
658 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
659
78c84bf9
AM		 6602021-03-12 Alan Modra <amodra@gmail.com>
661
662 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
663
fd1fd061
JB		 6642021-03-11 Jan Beulich <jbeulich@suse.com>
665
666 * i386-dis.c (OP_XMM): Re-order checks.
667
ac7a2311
JB		 6682021-03-11 Jan Beulich <jbeulich@suse.com>
669
670 * i386-dis.c (putop): Drop need_vex check when also checking
671 vex.evex.
672 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
673 checking vex.b.
674
da944c8a
JB		 6752021-03-11 Jan Beulich <jbeulich@suse.com>
676
677 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
678 checks. Move case label past broadcast check.
679
b763d508
JB		 6802021-03-10 Jan Beulich <jbeulich@suse.com>
681
682 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
683 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
684 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
685 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
686 EVEX_W_0F38C7_M_0_L_2): Delete.
687 (REG_EVEX_0F38C7_M_0_L_2): New.
688 (intel_operand_size): Handle VEX and EVEX the same for
689 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
690 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
691 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
692 vex_vsib_q_w_d_mode uses.
693 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
694 0F38A1, and 0F38A3 entries.
695 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
696 entry.
697 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
698 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
699 0F38A3 entries.
700
32e31ad7
JB		 7012021-03-10 Jan Beulich <jbeulich@suse.com>
702
703 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
704 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
705 MOD_VEX_0FXOP_09_12): Rename to ...
706 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
707 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
708 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
709 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
710 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
711 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
712 (reg_table): Adjust comments.
713 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
714 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
715 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
716 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
717 (vex_len_table): Adjust opcode 0A_12 entry.
718 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
719 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
720 (rm_table): Move hreset entry.
721
85ba7507
JB		 7222021-03-10 Jan Beulich <jbeulich@suse.com>
723
724 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
725 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
726 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
727 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
728 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
729 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
730 (get_valid_dis386): Also handle 512-bit vector length when
731 vectoring into vex_len_table[].
732 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
733 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
734 entries.
735 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
736 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
737 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
738 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
739 entries.
740
066f82b9
JB		 7412021-03-10 Jan Beulich <jbeulich@suse.com>
742
743 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
744 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
745 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
746 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
747 entries.
748 * i386-dis-evex-len.h (evex_len_table): Likewise.
749 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
750
fc681dd6
JB		 7512021-03-10 Jan Beulich <jbeulich@suse.com>
752
753 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
754 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
755 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
756 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
757 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
758 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
759 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
760 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
761 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
762 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
763 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
764 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
765 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
766 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
767 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
768 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
769 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
770 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
771 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
772 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
773 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
774 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
775 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
776 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
777 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
778 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
779 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
780 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
781 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
782 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
783 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
784 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
785 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
786 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
787 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
788 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
789 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
790 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
791 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
792 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
793 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
794 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
795 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
796 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
797 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
798 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
799 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
800 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
801 EVEX_W_0F3A43_L_n): New.
802 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
803 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
804 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
805 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
806 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
807 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
808 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
809 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
810 0F385B, 0F38C6, and 0F38C7 entries.
811 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
812 0F38C6 and 0F38C7.
813 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
814 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
815 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
816 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
817
13954a31
JB		 8182021-03-10 Jan Beulich <jbeulich@suse.com>
819
820 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
821 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
822 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
823 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
824 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
825 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
826 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
827 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
828 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
829 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
830 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
831 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
832 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
833 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
834 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
835 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
836 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
837 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
838 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
839 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
840 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
841 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
842 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
843 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
844 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
845 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
846 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
847 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
848 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
849 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
850 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
851 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
852 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
853 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
854 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
855 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
856 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
857 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
858 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
859 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
860 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
861 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
862 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
863 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
864 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
865 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
866 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
867 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
868 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
869 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
870 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
871 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
872 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
873 VEX_W_0F99_P_2_LEN_0): Delete.
874 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
875 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
876 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
877 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
878 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
879 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
880 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
881 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
882 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
883 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
884 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
885 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
886 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
887 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
888 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
889 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
890 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
891 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
892 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
893 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
894 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
895 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
896 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
897 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
898 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
899 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
900 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
901 (prefix_table): No longer link to vex_len_table[] for opcodes
902 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
903 0F92, 0F93, 0F98, and 0F99.
904 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
905 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
906 0F98, and 0F99.
907 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
908 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
909 0F98, and 0F99.
910 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
911 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
912 0F98, and 0F99.
913 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
914 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
915 0F98, and 0F99.
916
14d10c6c
JB		 9172021-03-10 Jan Beulich <jbeulich@suse.com>
918
919 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
920 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
921 REG_VEX_0F73_M_0 respectively.
922 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
923 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
924 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
925 MOD_VEX_0F73_REG_7): Delete.
926 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
927 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
928 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
929 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
930 PREFIX_VEX_0F3AF0_L_0 respectively.
931 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
932 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
933 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
934 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
935 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
936 VEX_LEN_0F38F7): New.
937 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
938 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
939 0F72, and 0F73. No longer link to vex_len_table[] for opcode
940 0F38F3.
941 (prefix_table): No longer link to vex_len_table[] for opcodes
942 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
943 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
944 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
945 0F38F6, 0F38F7, and 0F3AF0.
946 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
947 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
948 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
949 0F73.
950
00ec1875
JB		 9512021-03-10 Jan Beulich <jbeulich@suse.com>
952
953 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
954 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
955 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
956 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
957 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
958 (MOD_0F71, MOD_0F72, MOD_0F73): New.
959 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
960 73.
961 (reg_table): No longer link to mod_table[] for opcodes 0F71,
962 0F72, and 0F73.
963 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
964 0F73.
965
31941983
JB		 9662021-03-10 Jan Beulich <jbeulich@suse.com>
967
968 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
969 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
970 (reg_table): Don't link to mod_table[] where not needed. Add
971 PREFIX_IGNORED to nop entries.
972 (prefix_table): Replace PREFIX_OPCODE in nop entries.
973 (mod_table): Add nop entries next to prefetch ones. Drop
974 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
975 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
976 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
977 PREFIX_OPCODE from endbr* entries.
978 (get_valid_dis386): Also consider entry's name when zapping
979 vindex.
980 (print_insn): Handle PREFIX_IGNORED.
981
742732c7
JB		 9822021-03-09 Jan Beulich <jbeulich@suse.com>
983
984 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
985 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
986 element.
987 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
988 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
989 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
990 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
991 (struct i386_opcode_modifier): Delete notrackprefixok,
992 islockable, hleprefixok, and repprefixok fields. Add prefixok
993 field.
994 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
995 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
996 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
997 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
998 Replace HLEPrefixOk.
999 * opcodes/i386-tbl.h: Re-generate.
1000
e93a3b27
JB		 10012021-03-09 Jan Beulich <jbeulich@suse.com>
1002
1003 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1004 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1005 64-bit form.
1006 * opcodes/i386-tbl.h: Re-generate.
1007
75363b6d
JB		 10082021-03-03 Jan Beulich <jbeulich@suse.com>
1009
1010 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1011 for {} instead of {0}. Don't look for '0'.
1012 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1013 size specifiers.
1014
5a9f5403
NC		 10152021-02-19 Nelson Chu <nelson.chu@sifive.com>
1016
1017 PR 27158
1018 * riscv-dis.c (print_insn_args): Updated encoding macros.
1019 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1020 (match_c_addi16sp): Updated encoding macros.
1021 (match_c_lui): Likewise.
1022 (match_c_lui_with_hint): Likewise.
1023 (match_c_addi4spn): Likewise.
1024 (match_c_slli): Likewise.
1025 (match_slli_as_c_slli): Likewise.
1026 (match_c_slli64): Likewise.
1027 (match_srxi_as_c_srxi): Likewise.
1028 (riscv_insn_types): Added .insn css/cl/cs.
1029
3d73d29e
NC		 10302021-02-18 Nelson Chu <nelson.chu@sifive.com>
1031
1032 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1033 (default_priv_spec): Updated type to riscv_spec_class.
1034 (parse_riscv_dis_option): Updated.
1035 * riscv-opc.c: Moved stuff and make the file tidy.
1036
b9b204b3
AM		 10372021-02-17 Alan Modra <amodra@gmail.com>
1038
1039 * wasm32-dis.c: Include limits.h.
1040 (CHAR_BIT): Provide backup define.
1041 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1042 Correct signed overflow checking.
1043
394ae71f
JB		 10442021-02-16 Jan Beulich <jbeulich@suse.com>
1045
1046 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1047 * i386-tbl.h: Re-generate.
1048
b818b220
JB		 10492021-02-16 Jan Beulich <jbeulich@suse.com>
1050
1051 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1052 Oword.
1053 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1054
ba2b480f
AK		 10552021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1056
1057 * s390-mkopc.c (main): Accept arch14 as cpu string.
1058 * s390-opc.txt: Add new arch14 instructions.
1059
95148614
NA		 10602021-02-04 Nick Alcock <nick.alcock@oracle.com>
1061
1062 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1063 favour of LIBINTL.
1064 * configure: Regenerated.
1065
bfd428bc
MF		 10662021-02-08 Mike Frysinger <vapier@gentoo.org>
1067
1068 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1069 * tic54x-opc.c (regs): Rename to ...
1070 (tic54x_regs): ... this.
1071 (mmregs): Rename to ...
1072 (tic54x_mmregs): ... this.
1073 (condition_codes): Rename to ...
1074 (tic54x_condition_codes): ... this.
1075 (cc2_codes): Rename to ...
1076 (tic54x_cc2_codes): ... this.
1077 (cc3_codes): Rename to ...
1078 (tic54x_cc3_codes): ... this.
1079 (status_bits): Rename to ...
1080 (tic54x_status_bits): ... this.
1081 (misc_symbols): Rename to ...
1082 (tic54x_misc_symbols): ... this.
1083
24075dcc
NC		 10842021-02-04 Nelson Chu <nelson.chu@sifive.com>
1085
1086 * riscv-opc.c (MASK_RVB_IMM): Removed.
1087 (riscv_opcodes): Removed zb* instructions.
1088 (riscv_ext_version_table): Removed versions for zb*.
1089
c3ffb8f3
AM		 10902021-01-26 Alan Modra <amodra@gmail.com>
1091
1092 * i386-gen.c (parse_template): Ensure entire template_instance
1093 is initialised.
1094
1942a048
NC		 10952021-01-15 Nelson Chu <nelson.chu@sifive.com>
1096
1097 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1098 (riscv_fpr_names_abi): Likewise.
1099 (riscv_opcodes): Likewise.
1100 (riscv_insn_types): Likewise.
1101
b800637e
NC		 11022021-01-15 Nelson Chu <nelson.chu@sifive.com>
1103
1104 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1105
dcd709e0
NC		 11062021-01-15 Nelson Chu <nelson.chu@sifive.com>
1107
1108 * riscv-dis.c: Comments tidy and improvement.
1109 * riscv-opc.c: Likewise.
1110
5347ed60
AM		 11112021-01-13 Alan Modra <amodra@gmail.com>
1112
1113 * Makefile.in: Regenerate.
1114
d546b610
L		 11152021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1116
1117 PR binutils/26792
1118 * configure.ac: Use GNU_MAKE_JOBSERVER.
1119 * aclocal.m4: Regenerated.
1120 * configure: Likewise.
1121
6d104cac
NC		 11222021-01-12 Nick Clifton <nickc@redhat.com>
1123
1124 * po/sr.po: Updated Serbian translation.
1125
83b33c6c
L		 11262021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1127
1128 PR ld/27173
1129 * configure: Regenerated.
1130
82c70b08
KT		 11312021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1132
1133 * aarch64-asm-2.c: Regenerate.
1134 * aarch64-dis-2.c: Likewise.
1135 * aarch64-opc-2.c: Likewise.
1136 * aarch64-opc.c (aarch64_print_operand):
1137 Delete handling of AARCH64_OPND_CSRE_CSR.
1138 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1139 (CSRE): Likewise.
1140 (_CSRE_INSN): Likewise.
1141 (aarch64_opcode_table): Delete csr.
1142
a8aa72b9
NC		 11432021-01-11 Nick Clifton <nickc@redhat.com>
1144
1145 * po/de.po: Updated German translation.
1146 * po/fr.po: Updated French translation.
1147 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1148 * po/sv.po: Updated Swedish translation.
1149 * po/uk.po: Updated Ukranian translation.
1150
a4966cd9
L		 11512021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1152
1153 * configure: Regenerated.
1154
573fe3fb
NC		 11552021-01-09 Nick Clifton <nickc@redhat.com>
1156
1157 * configure: Regenerate.
1158 * po/opcodes.pot: Regenerate.
1159
055bc77a
NC		 11602021-01-09 Nick Clifton <nickc@redhat.com>
1161
1162 * 2.36 release branch crated.
1163
aae7fcb8
PB		 11642021-01-08 Peter Bergner <bergner@linux.ibm.com>
1165
1166 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1167 (DW, (XRC_MASK): Define.
1168 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1169
64307045
AM		 11702021-01-09 Alan Modra <amodra@gmail.com>
1171
1172 * configure: Regenerate.
1173
ed205222
NC		 11742021-01-08 Nick Clifton <nickc@redhat.com>
1175
1176 * po/sv.po: Updated Swedish translation.
1177
fb932b57
NC		 11782021-01-08 Nick Clifton <nickc@redhat.com>
1179
e84c8716
NC		 1180 PR 27129
1181 * aarch64-dis.c (determine_disassembling_preference): Move call to
1182 aarch64_match_operands_constraint outside of the assertion.
1183 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1184 Replace with a return of FALSE.
1185
fb932b57
NC		 1186 PR 27139
1187 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1188 core system register.
1189
f4782128
ST		 11902021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1191
1192 * configure: Regenerate.
1193
1b0927db
NC		 11942021-01-07 Nick Clifton <nickc@redhat.com>
1195
1196 * po/fr.po: Updated French translation.
1197
3b288c8e
FN		 11982021-01-07 Fredrik Noring <noring@nocrew.org>
1199
1200 * m68k-opc.c (chkl): Change minimum architecture requirement to
1201 m68020.
1202
aa881ecd
PT		 12032021-01-07 Philipp Tomsich <prt@gnu.org>
1204
1205 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1206
2652cfad
CXW		 12072021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1208 Jim Wilson <jimw@sifive.com>
1209 Andrew Waterman <andrew@sifive.com>
1210 Maxim Blinov <maxim.blinov@embecosm.com>
1211 Kito Cheng <kito.cheng@sifive.com>
1212 Nelson Chu <nelson.chu@sifive.com>
1213
1214 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1215 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1216
250d07de
AM		 12172021-01-01 Alan Modra <amodra@gmail.com>
1218
1219 Update year range in copyright notice of all files.
1220
c2795844 1221For older changes see ChangeLog-2020
3499769a 1222\f
c2795844 1223Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1224
1225Copying and distribution of this file, with or without modification,
1226are permitted in any medium without royalty provided the copyright
1227notice and this notice are preserved.
1228
1229Local Variables:
1230mode: change-log
1231left-margin: 8
1232fill-column: 74
1233version-control: never
1234End:
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