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Z8k: fix sout/soudb opcodes with direct address
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
563a3225
CG		 12020-08-04 Christian Groessler <chris@groessler.org>
2 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
3
4 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
5 opcodes (special "out" to absolute address).
6 * z8k-opc.h: Regenerate.
7
41eb8e88
L		 82020-07-30 H.J. Lu <hongjiu.lu@intel.com>
9
10 PR gas/26305
11 * i386-opc.h (Prefix_Disp8): New.
12 (Prefix_Disp16): Likewise.
13 (Prefix_Disp32): Likewise.
14 (Prefix_Load): Likewise.
15 (Prefix_Store): Likewise.
16 (Prefix_VEX): Likewise.
17 (Prefix_VEX3): Likewise.
18 (Prefix_EVEX): Likewise.
19 (Prefix_REX): Likewise.
20 (Prefix_NoOptimize): Likewise.
21 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
22 * i386-tbl.h: Regenerated.
23
98116973
AA		 242020-07-29 Andreas Arnez <arnez@linux.ibm.com>
25
26 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
27 default case with abort() instead of printing an error message and
28 continuing, to avoid a maybe-uninitialized warning.
29
2dddfa20
NC		 302020-07-24 Nick Clifton <nickc@redhat.com>
31
32 * po/de.po: Updated German translation.
33
bf4ba07c
JB		 342020-07-21 Jan Beulich <jbeulich@suse.com>
35
36 * i386-dis.c (OP_E_memory): Revert previous change.
37
04c662e2
L		 382020-07-15 H.J. Lu <hongjiu.lu@intel.com>
39
40 PR gas/26237
41 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
42 without base nor index registers.
43
f0e8d0ba
JB		 442020-07-15 Jan Beulich <jbeulich@suse.com>
45
46 * i386-dis.c (putop): Move 'V' and 'W' handling.
47
c3f5525f
JB		 482020-07-15 Jan Beulich <jbeulich@suse.com>
49
50 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
51 construct for push/pop of register.
52 (putop): Honor cond when handling 'P'. Drop handling of plain
53 'V'.
54
36938cab
JB		 552020-07-15 Jan Beulich <jbeulich@suse.com>
56
57 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
58 description. Drop '&' description. Use P for push of immediate,
59 pushf/popf, enter, and leave. Use %LP for lret/retf.
60 (dis386_twobyte): Use P for push/pop of fs/gs.
61 (reg_table): Use P for push/pop. Use @ for near call/jmp.
62 (x86_64_table): Use P for far call/jmp.
63 (putop): Drop handling of 'U' and '&'. Move and adjust handling
64 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
65 labels.
66 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
67 and dqw_mode (unconditional).
68
8e58ef80
L		 692020-07-14 H.J. Lu <hongjiu.lu@intel.com>
70
71 PR gas/26237
72 * i386-dis.c (OP_E_memory): Without base nor index registers,
73 32-bit displacement to 64 bits.
74
570b0ed6
CZ		 752020-07-14 Claudiu Zissulescu <claziss@gmail.com>
76
77 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
78 faulty double register pair is detected.
79
bfbd9438
JB		 802020-07-14 Jan Beulich <jbeulich@suse.com>
81
82 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
83
78467458
JB		 842020-07-14 Jan Beulich <jbeulich@suse.com>
85
86 * i386-dis.c (OP_R, Rm): Delete.
87 (MOD_0F24, MOD_0F26): Rename to ...
88 (X86_64_0F24, X86_64_0F26): ... respectively.
89 (dis386): Update 'L' and 'Z' comments.
90 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
91 table references.
92 (mod_table): Move opcode 0F24 and 0F26 entries ...
93 (x86_64_table): ... here.
94 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
95 'Z' case block.
96
464d2b65
JB		 972020-07-14 Jan Beulich <jbeulich@suse.com>
98
99 * i386-dis.c (Rd, Rdq, MaskR): Delete.
100 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
101 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
102 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
103 MOD_EVEX_0F387C): New enumerators.
104 (reg_table): Use Edq for rdssp.
105 (prefix_table): Use Edq for incssp.
106 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
107 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
108 ktest*, and kshift*. Use Edq / MaskE for kmov*.
109 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
110 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
111 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
112 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
113 0F3828_P_1 and 0F3838_P_1.
114 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
115 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
116
035e7389
JB		 1172020-07-14 Jan Beulich <jbeulich@suse.com>
118
119 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
120 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
121 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
122 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
123 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
124 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
125 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
126 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
127 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
128 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
129 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
130 (reg_table, prefix_table, three_byte_table, vex_table,
131 vex_len_table, mod_table, rm_table): Replace / remove respective
132 entries.
133 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
134 of PREFIX_DATA in used_prefixes.
135
bb5b3501
JB		 1362020-07-14 Jan Beulich <jbeulich@suse.com>
137
138 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
139 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
140 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
141 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
142 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
143 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
144 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
145 VEX_W_0F3A33_L_0): Delete.
146 (dis386): Adjust "BW" description.
147 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
148 0F3A31, 0F3A32, and 0F3A33.
149 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
150 entries.
151 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
152 entries.
153
7531c613
JB		 1542020-07-14 Jan Beulich <jbeulich@suse.com>
155
156 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
157 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
158 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
159 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
160 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
161 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
162 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
163 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
164 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
165 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
166 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
167 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
168 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
169 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
170 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
171 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
172 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
173 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
174 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
175 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
176 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
177 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
178 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
179 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
180 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
181 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
182 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
183 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
184 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
185 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
186 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
187 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
188 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
189 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
190 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
191 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
192 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
193 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
194 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
195 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
196 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
197 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
198 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
199 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
200 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
201 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
202 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
203 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
204 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
205 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
206 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
207 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
208 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
209 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
210 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
211 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
212 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
213 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
214 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
215 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
216 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
217 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
218 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
219 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
220 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
221 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
222 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
223 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
224 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
225 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
226 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
227 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
228 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
229 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
230 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
231 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
232 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
233 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
234 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
235 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
236 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
237 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
238 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
239 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
240 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
241 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
242 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
243 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
244 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
245 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
246 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
247 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
248 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
249 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
250 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
251 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
252 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
253 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
254 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
255 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
256 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
257 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
258 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
259 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
260 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
261 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
262 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
263 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
264 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
265 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
266 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
267 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
268 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
269 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
270 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
271 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
272 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
273 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
274 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
275 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
276 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
277 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
278 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
279 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
280 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
281 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
282 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
283 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
284 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
285 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
286 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
287 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
288 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
289 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
290 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
291 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
292 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
293 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
294 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
295 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
296 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
297 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
298 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
299 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
300 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
301 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
302 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
303 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
304 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
305 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
306 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
307 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
308 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
309 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
310 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
311 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
312 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
313 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
314 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
315 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
316 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
317 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
318 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
319 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
320 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
321 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
322 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
323 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
324 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
325 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
326 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
327 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
328 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
329 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
330 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
331 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
332 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
333 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
334 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
335 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
336 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
337 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
338 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
339 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
340 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
341 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
342 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
343 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
344 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
345 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
346 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
347 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
348 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
349 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
350 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
351 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
352 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
353 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
354 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
355 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
356 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
357 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
358 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
359 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
360 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
361 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
362 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
363 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
364 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
365 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
366 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
367 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
368 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
369 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
370 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
371 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
372 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
373 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
374 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
375 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
376 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
377 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
378 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
379 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
380 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
381 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
382 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
383 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
384 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
385 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
386 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
387 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
388 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
389 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
390 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
391 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
392 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
393 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
394 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
395 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
396 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
397 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
398 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
399 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
400 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
401 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
402 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
403 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
404 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
405 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
406 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
407 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
408 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
409 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
410 EVEX_W_0F3A72_P_2): Rename to ...
411 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
412 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
413 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
414 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
415 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
416 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
417 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
418 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
419 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
420 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
421 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
422 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
423 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
424 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
425 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
426 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
427 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
428 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
429 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
430 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
431 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
432 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
433 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
434 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
435 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
436 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
437 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
438 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
439 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
440 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
441 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
442 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
443 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
444 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
445 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
446 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
447 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
448 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
449 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
450 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
451 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
452 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
453 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
454 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
455 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
456 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
457 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
458 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
459 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
460 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
461 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
462 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
463 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
464 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
465 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
466 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
467 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
468 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
469 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
470 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
471 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
472 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
473 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
474 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
475 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
476 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
477 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
478 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
479 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
480 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
481 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
482 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
483 respectively.
484 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
485 vex_w_table, mod_table): Replace / remove respective entries.
486 (print_insn): Move up dp->prefix_requirement handling. Handle
487 PREFIX_DATA.
488 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
489 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
490 Replace / remove respective entries.
491
17d3c7ec
JB		 4922020-07-14 Jan Beulich <jbeulich@suse.com>
493
494 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
495 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
496 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
497 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
498 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
499 the latter two.
500 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
501 0F2C, 0F2D, 0F2E, and 0F2F.
502 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
503 0F2F table entries.
504
41f5efc6
JB		 5052020-07-14 Jan Beulich <jbeulich@suse.com>
506
507 * i386-dis.c (OP_VexR, VexScalarR): New.
508 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
509 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
510 need_vex_reg): Delete.
511 (prefix_table): Replace VexScalar by VexScalarR and
512 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
513 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
514 (vex_len_table): Replace EXqVexScalarS by EXqS.
515 (get_valid_dis386): Don't set need_vex_reg.
516 (print_insn): Don't initialize need_vex_reg.
517 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
518 q_scalar_swap_mode cases.
519 (OP_EX): Don't check for d_scalar_swap_mode and
520 q_scalar_swap_mode.
521 (OP_VEX): Done check need_vex_reg.
522 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
523 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
524 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
525
89e65d17
JB		 5262020-07-14 Jan Beulich <jbeulich@suse.com>
527
528 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
529 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
530 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
531 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
532 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
533 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
534 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
535 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
536 (vex_table): Replace Vex128 by Vex.
537 (vex_len_table): Likewise. Adjust referenced enum names.
538 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
539 referenced enum names.
540 (OP_VEX): Drop vex128_mode and vex256_mode cases.
541 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
542
492a76aa
JB		 5432020-07-14 Jan Beulich <jbeulich@suse.com>
544
545 * i386-dis.c (dis386): "LW" description now applies to "DQ".
546 (putop): Handle "DQ". Don't handle "LW" anymore.
547 (prefix_table, mod_table): Replace %LW by %DQ.
548 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
549
059edf8b
JB		 5502020-07-14 Jan Beulich <jbeulich@suse.com>
551
552 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
553 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
554 d_scalar_swap_mode case handling. Move shift adjsutment into
555 the case its applicable to.
556
4726e9a4
JB		 5572020-07-14 Jan Beulich <jbeulich@suse.com>
558
559 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
560 (EXbScalar, EXwScalar): Fold to ...
561 (EXbwUnit): ... this.
562 (b_scalar_mode, w_scalar_mode): Fold to ...
563 (bw_unit_mode): ... this.
564 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
565 w_scalar_mode handling by bw_unit_mode one.
566 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
567 ...
568 * i386-dis-evex-prefix.h: ... here.
569
b24d668c
JB		 5702020-07-14 Jan Beulich <jbeulich@suse.com>
571
572 * i386-dis.c (PCMPESTR_Fixup): Delete.
573 (dis386): Adjust "LQ" description.
574 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
575 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
576 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
577 vpcmpestrm, and vpcmpestri.
578 (putop): Honor "cond" when handling LQ.
579 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
580 vcvtsi2ss and vcvtusi2ss.
581 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
582 vcvtsi2sd and vcvtusi2sd.
583
c4de7606
JB		 5842020-07-14 Jan Beulich <jbeulich@suse.com>
585
586 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
587 (simd_cmp_op): Add const.
588 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
589 (CMP_Fixup): Handle VEX case.
590 (prefix_table): Replace VCMP by CMP.
591 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
592
9ab00b61
JB		 5932020-07-14 Jan Beulich <jbeulich@suse.com>
594
595 * i386-dis.c (MOVBE_Fixup): Delete.
596 (Mv): Define.
597 (prefix_table): Use Mv for movbe entries.
598
2875b28a
JB		 5992020-07-14 Jan Beulich <jbeulich@suse.com>
600
601 * i386-dis.c (CRC32_Fixup): Delete.
602 (prefix_table): Use Eb/Ev for crc32 entries.
603
e184e611
JB		 6042020-07-14 Jan Beulich <jbeulich@suse.com>
605
606 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
607 Conditionalize invocations of "USED_REX (0)".
608
e8b5d5f9
JB		 6092020-07-14 Jan Beulich <jbeulich@suse.com>
610
611 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
612 CH, DH, BH, AX, DX): Delete.
613 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
614 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
615 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
616
260cd341
LC		 6172020-07-10 Lili Cui <lili.cui@intel.com>
618
619 * i386-dis.c (TMM): New.
620 (EXtmm): Likewise.
621 (VexTmm): Likewise.
622 (MVexSIBMEM): Likewise.
623 (tmm_mode): Likewise.
624 (vex_sibmem_mode): Likewise.
625 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
626 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
627 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
628 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
629 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
630 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
631 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
632 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
633 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
634 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
635 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
636 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
637 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
638 (PREFIX_VEX_0F3849_X86_64): Likewise.
639 (PREFIX_VEX_0F384B_X86_64): Likewise.
640 (PREFIX_VEX_0F385C_X86_64): Likewise.
641 (PREFIX_VEX_0F385E_X86_64): Likewise.
642 (X86_64_VEX_0F3849): Likewise.
643 (X86_64_VEX_0F384B): Likewise.
644 (X86_64_VEX_0F385C): Likewise.
645 (X86_64_VEX_0F385E): Likewise.
646 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
647 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
648 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
649 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
650 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
651 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
652 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
653 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
654 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
655 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
656 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
657 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
658 (VEX_W_0F3849_X86_64_P_0): Likewise.
659 (VEX_W_0F3849_X86_64_P_2): Likewise.
660 (VEX_W_0F3849_X86_64_P_3): Likewise.
661 (VEX_W_0F384B_X86_64_P_1): Likewise.
662 (VEX_W_0F384B_X86_64_P_2): Likewise.
663 (VEX_W_0F384B_X86_64_P_3): Likewise.
664 (VEX_W_0F385C_X86_64_P_1): Likewise.
665 (VEX_W_0F385E_X86_64_P_0): Likewise.
666 (VEX_W_0F385E_X86_64_P_1): Likewise.
667 (VEX_W_0F385E_X86_64_P_2): Likewise.
668 (VEX_W_0F385E_X86_64_P_3): Likewise.
669 (names_tmm): Likewise.
670 (att_names_tmm): Likewise.
671 (intel_operand_size): Handle void_mode.
672 (OP_XMM): Handle tmm_mode.
673 (OP_EX): Likewise.
674 (OP_VEX): Likewise.
675 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
676 CpuAMX_BF16 and CpuAMX_TILE.
677 (operand_type_shorthands): Add RegTMM.
678 (operand_type_init): Likewise.
679 (operand_types): Add Tmmword.
680 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
681 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
682 * i386-opc.h (CpuAMX_INT8): New.
683 (CpuAMX_BF16): Likewise.
684 (CpuAMX_TILE): Likewise.
685 (SIBMEM): Likewise.
686 (Tmmword): Likewise.
687 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
688 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
689 (i386_operand_type): Add tmmword.
690 * i386-opc.tbl: Add AMX instructions.
691 * i386-reg.tbl: Add AMX registers.
692 * i386-init.h: Regenerated.
693 * i386-tbl.h: Likewise.
694
467bbef0
JB		 6952020-07-08 Jan Beulich <jbeulich@suse.com>
696
697 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
698 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
699 Rename to ...
700 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
701 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
702 respectively.
703 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
704 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
705 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
706 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
707 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
708 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
709 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
710 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
711 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
712 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
713 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
714 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
715 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
716 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
717 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
718 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
719 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
720 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
721 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
722 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
723 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
724 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
725 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
726 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
727 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
728 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
729 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
730 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
731 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
732 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
733 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
734 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
735 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
736 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
737 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
738 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
739 (reg_table): Re-order XOP entries. Adjust their operands.
740 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
741 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
742 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
743 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
744 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
745 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
746 entries by references ...
747 (vex_len_table): ... to resepctive new entries here. For several
748 new and existing entries reference ...
749 (vex_w_table): ... new entries here.
750 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
751
6384fd9e
JB		 7522020-07-08 Jan Beulich <jbeulich@suse.com>
753
754 * i386-dis.c (XMVexScalarI4): Define.
755 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
756 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
757 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
758 (vex_len_table): Move scalar FMA4 entries ...
759 (prefix_table): ... here.
760 (OP_REG_VexI4): Handle scalar_mode.
761 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
762 * i386-tbl.h: Re-generate.
763
e6123d0c
JB		 7642020-07-08 Jan Beulich <jbeulich@suse.com>
765
766 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
767 Vex_2src_2): Delete.
768 (OP_VexW, VexW): New.
769 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
770 for shifts and rotates by register.
771
93abb146
JB		 7722020-07-08 Jan Beulich <jbeulich@suse.com>
773
774 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
775 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
776 OP_EX_VexReg): Delete.
777 (OP_VexI4, VexI4): New.
778 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
779 (prefix_table): ... here.
780 (print_insn): Drop setting of vex_w_done.
781
b13b1bc0
JB		 7822020-07-08 Jan Beulich <jbeulich@suse.com>
783
784 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
785 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
786 (xop_table): Replace operands of 4-operand insns.
787 (OP_REG_VexI4): Move VEX.W based operand swaping here.
788
f337259f
CZ		 7892020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
790
791 * arc-opc.c (insert_rbd): New function.
792 (RBD): Define.
793 (RBDdup): Likewise.
794 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
795 instructions.
796
931452b6
JB		 7972020-07-07 Jan Beulich <jbeulich@suse.com>
798
799 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
800 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
801 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
802 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
803 Delete.
804 (putop): Handle "BW".
805 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
806 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
807 and 0F3A3F ...
808 * i386-dis-evex-prefix.h: ... here.
809
b5b098c2
JB		 8102020-07-06 Jan Beulich <jbeulich@suse.com>
811
812 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
813 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
814 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
815 VEX_W_0FXOP_09_83): New enumerators.
816 (xop_table): Reference the above.
817 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
818 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
819 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
820 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
821
21a3faeb
JB		 8222020-07-06 Jan Beulich <jbeulich@suse.com>
823
824 * i386-dis.c (EVEX_W_0F3838_P_1,
825 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
826 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
827 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
828 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
829 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
830 (putop): Centralize management of last[]. Delete SAVE_LAST.
831 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
832 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
833 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
834 * i386-dis-evex-prefix.h: here.
835
bc152a17
JB		 8362020-07-06 Jan Beulich <jbeulich@suse.com>
837
838 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
839 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
840 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
841 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
842 enumerators.
843 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
844 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
845 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
846 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
847 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
848 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
849 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
850 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
851 these, respectively.
852 * i386-dis-evex-len.h: Adjust comments.
853 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
854 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
855 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
856 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
857 MOD_EVEX_0F385B_P_2_W_1 table entries.
858 * i386-dis-evex-w.h: Reference mod_table[] for
859 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
860 EVEX_W_0F385B_P_2.
861
c82a99a0
JB		 8622020-07-06 Jan Beulich <jbeulich@suse.com>
863
864 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
865 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
866 EXymm.
867 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
868 Likewise. Mark 256-bit entries invalid.
869
fedfb81e
JB		 8702020-07-06 Jan Beulich <jbeulich@suse.com>
871
872 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
873 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
874 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
875 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
876 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
877 PREFIX_EVEX_0F382B): Delete.
878 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
879 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
880 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
881 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
882 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
883 to ...
884 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
885 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
886 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
887 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
888 respectively.
889 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
890 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
891 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
892 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
893 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
894 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
895 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
896 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
897 PREFIX_EVEX_0F382B): Remove table entries.
898 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
899 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
900 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
901
3a57774c
JB		 9022020-07-06 Jan Beulich <jbeulich@suse.com>
903
904 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
905 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
906 enumerators.
907 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
908 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
909 EVEX_LEN_0F3A01_P_2_W_1 table entries.
910 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
911 entries.
912
e74d9fa9
JB		 9132020-07-06 Jan Beulich <jbeulich@suse.com>
914
915 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
916 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
917 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
918 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
919 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
920 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
921 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
922 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
923 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
924 entries.
925
6431c801
JB		 9262020-07-06 Jan Beulich <jbeulich@suse.com>
927
928 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
929 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
930 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
931 respectively.
932 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
933 entries.
934 * i386-dis-evex.h (evex_table): Reference VEX table entry for
935 opcode 0F3A1D.
936 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
937 entry.
938 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
939
6df22cf6
JB		 9402020-07-06 Jan Beulich <jbeulich@suse.com>
941
942 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
943 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
944 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
945 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
946 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
947 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
948 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
949 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
950 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
951 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
952 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
953 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
954 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
955 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
956 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
957 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
958 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
959 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
960 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
961 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
962 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
963 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
964 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
965 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
966 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
967 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
968 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
969 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
970 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
971 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
972 (prefix_table): Add EXxEVexR to FMA table entries.
973 (OP_Rounding): Move abort() invocation.
974 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
975 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
976 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
977 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
978 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
979 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
980 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
981 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
982 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
983 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
984 0F3ACE, 0F3ACF.
985 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
986 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
987 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
988 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
989 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
990 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
991 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
992 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
993 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
994 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
995 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
996 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
997 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
998 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
999 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1000 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1001 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1002 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1003 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1004 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1005 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1006 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1007 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1008 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1009 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1010 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1011 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1012 Delete table entries.
1013 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1014 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1015 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1016 Likewise.
1017
39e0f456
JB		 10182020-07-06 Jan Beulich <jbeulich@suse.com>
1019
1020 * i386-dis.c (EXqScalarS): Delete.
1021 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1022 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1023
5b872f7d
JB		 10242020-07-06 Jan Beulich <jbeulich@suse.com>
1025
1026 * i386-dis.c (safe-ctype.h): Include.
1027 (EXdScalar, EXqScalar): Delete.
1028 (d_scalar_mode, q_scalar_mode): Delete.
1029 (prefix_table, vex_len_table): Use EXxmm_md in place of
1030 EXdScalar and EXxmm_mq in place of EXqScalar.
1031 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1032 d_scalar_mode and q_scalar_mode.
1033 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1034 (vmovsd): Use EXxmm_mq.
1035
ddc73fa9
NC		 10362020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1037
1038 PR 26204
1039 * arc-dis.c: Fix spelling mistake.
1040 * po/opcodes.pot: Regenerate.
1041
17550be7
NC		 10422020-07-06 Nick Clifton <nickc@redhat.com>
1043
1044 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1045 * po/uk.po: Updated Ukranian translation.
1046
b19d852d
NC		 10472020-07-04 Nick Clifton <nickc@redhat.com>
1048
1049 * configure: Regenerate.
1050 * po/opcodes.pot: Regenerate.
1051
b115b9fd
NC		 10522020-07-04 Nick Clifton <nickc@redhat.com>
1053
1054 Binutils 2.35 branch created.
1055
c2ecccb3
L		 10562020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1057
1058 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1059 * i386-opc.h (VexSwapSources): New.
1060 (i386_opcode_modifier): Add vexswapsources.
1061 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1062 with two source operands swapped.
1063 * i386-tbl.h: Regenerated.
1064
08ccfccf
NC		 10652020-06-30 Nelson Chu <nelson.chu@sifive.com>
1066
1067 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1068 unprivileged CSR can also be initialized.
1069
279edac5
AM		 10702020-06-29 Alan Modra <amodra@gmail.com>
1071
1072 * arm-dis.c: Use C style comments.
1073 * cr16-opc.c: Likewise.
1074 * ft32-dis.c: Likewise.
1075 * moxie-opc.c: Likewise.
1076 * tic54x-dis.c: Likewise.
1077 * s12z-opc.c: Remove useless comment.
1078 * xgate-dis.c: Likewise.
1079
e978ad62
L		 10802020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1081
1082 * i386-opc.tbl: Add a blank line.
1083
63112cd6
L		 10842020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1085
1086 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1087 (VecSIB128): Renamed to ...
1088 (VECSIB128): This.
1089 (VecSIB256): Renamed to ...
1090 (VECSIB256): This.
1091 (VecSIB512): Renamed to ...
1092 (VECSIB512): This.
1093 (VecSIB): Renamed to ...
1094 (SIB): This.
1095 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1096 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1097 (VecSIB256): Likewise.
1098 (VecSIB512): Likewise.
79b32e73 1099 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1100 and VecSIB512, respectively.
1101
d1c36125
JB		 11022020-06-26 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-dis.c: Adjust description of I macro.
1105 (x86_64_table): Drop use of I.
1106 (float_mem): Replace use of I.
1107 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1108
2a1bb84c
JB		 11092020-06-26 Jan Beulich <jbeulich@suse.com>
1110
1111 * i386-dis.c: (print_insn): Avoid straight assignment to
1112 priv.orig_sizeflag when processing -M sub-options.
1113
8f570d62
JB		 11142020-06-25 Jan Beulich <jbeulich@suse.com>
1115
1116 * i386-dis.c: Adjust description of J macro.
1117 (dis386, x86_64_table, mod_table): Replace J.
1118 (putop): Remove handling of J.
1119
464dc4af
JB		 11202020-06-25 Jan Beulich <jbeulich@suse.com>
1121
1122 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1123
589958d6
JB		 11242020-06-25 Jan Beulich <jbeulich@suse.com>
1125
1126 * i386-dis.c: Adjust description of "LQ" macro.
1127 (dis386_twobyte): Use LQ for sysret.
1128 (putop): Adjust handling of LQ.
1129
39ff0b81
NC		 11302020-06-22 Nelson Chu <nelson.chu@sifive.com>
1131
1132 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1133 * riscv-dis.c: Include elfxx-riscv.h.
1134
d27c357a
JB		 11352020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1136
1137 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1138
6fde587f
CL		 11392020-06-17 Lili Cui <lili.cui@intel.com>
1140
1141 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1142
efe30057
L		 11432020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1144
1145 PR gas/26115
1146 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1147 * i386-opc.tbl: Likewise.
1148 * i386-tbl.h: Regenerated.
1149
d8af286f
NC		 11502020-06-12 Nelson Chu <nelson.chu@sifive.com>
1151
1152 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1153
14962256
AC		 11542020-06-11 Alex Coplan <alex.coplan@arm.com>
1155
1156 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1157 (SR_CORE): Likewise.
1158 (SR_FEAT): Likewise.
1159 (SR_RNG): Likewise.
1160 (SR_V8_1): Likewise.
1161 (SR_V8_2): Likewise.
1162 (SR_V8_3): Likewise.
1163 (SR_V8_4): Likewise.
1164 (SR_PAN): Likewise.
1165 (SR_RAS): Likewise.
1166 (SR_SSBS): Likewise.
1167 (SR_SVE): Likewise.
1168 (SR_ID_PFR2): Likewise.
1169 (SR_PROFILE): Likewise.
1170 (SR_MEMTAG): Likewise.
1171 (SR_SCXTNUM): Likewise.
1172 (aarch64_sys_regs): Refactor to store feature information in the table.
1173 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1174 that now describe their own features.
1175 (aarch64_pstatefield_supported_p): Likewise.
1176
f9630fa6
L		 11772020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1178
1179 * i386-dis.c (prefix_table): Fix a typo in comments.
1180
73239888
JB		 11812020-06-09 Jan Beulich <jbeulich@suse.com>
1182
1183 * i386-dis.c (rex_ignored): Delete.
1184 (ckprefix): Drop rex_ignored initialization.
1185 (get_valid_dis386): Drop setting of rex_ignored.
1186 (print_insn): Drop checking of rex_ignored. Don't record data
1187 size prefix as used with VEX-and-alike encodings.
1188
18897deb
JB		 11892020-06-09 Jan Beulich <jbeulich@suse.com>
1190
1191 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1192 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1193 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1194 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1195 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1196 VEX_0F12, and VEX_0F16.
1197 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1198 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1199 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1200 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1201 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1202 MOD_VEX_0F16_PREFIX_2 entries.
1203
97e6786a
JB		 12042020-06-09 Jan Beulich <jbeulich@suse.com>
1205
1206 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1207 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1208 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1209 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1210 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1211 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1212 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1213 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1214 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1215 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1216 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1217 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1218 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1219 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1220 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1221 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1222 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1223 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1224 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1225 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1226 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1227 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1228 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1229 EVEX_W_0FC6_P_2): Delete.
1230 (print_insn): Add EVEX.W vs embedded prefix consistency check
1231 to prefix validation.
1232 * i386-dis-evex.h (evex_table): Don't further descend for
1233 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1234 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1235 and 0F2B.
1236 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1237 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1238 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1239 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1240 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1241 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1242 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1243 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1244 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1245 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1246 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1247 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1248 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1249 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1250 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1251 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1252 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1253 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1254 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1255 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1256 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1257 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1258 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1259 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1260 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1261 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1262 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1263
bf926894
JB		 12642020-06-09 Jan Beulich <jbeulich@suse.com>
1265
1266 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1267 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1268 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1269 vmovmskpX.
1270 (print_insn): Drop pointless check against bad_opcode. Split
1271 prefix validation into legacy and VEX-and-alike parts.
1272 (putop): Re-work 'X' macro handling.
1273
a5aaedb9
JB		 12742020-06-09 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-dis.c (MOD_0F51): Rename to ...
1277 (MOD_0F50): ... this.
1278
26417f19
AC		 12792020-06-08 Alex Coplan <alex.coplan@arm.com>
1280
1281 * arm-dis.c (arm_opcodes): Add dfb.
1282 (thumb32_opcodes): Add dfb.
1283
8a6fb3f9
JB		 12842020-06-08 Jan Beulich <jbeulich@suse.com>
1285
1286 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1287
1424c35d
AM		 12882020-06-06 Alan Modra <amodra@gmail.com>
1289
1290 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1291
d3d1cc7b
AM		 12922020-06-05 Alan Modra <amodra@gmail.com>
1293
1294 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1295 size is large enough.
1296
d8740be1
JM		 12972020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1298
1299 * disassemble.c (disassemble_init_for_target): Set endian_code for
1300 bpf targets.
1301 * bpf-desc.c: Regenerate.
1302 * bpf-opc.c: Likewise.
1303 * bpf-dis.c: Likewise.
1304
e9bffec9
JM		 13052020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1306
1307 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1308 (cgen_put_insn_value): Likewise.
1309 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1310 * cgen-dis.in (print_insn): Likewise.
1311 * cgen-ibld.in (insert_1): Likewise.
1312 (insert_1): Likewise.
1313 (insert_insn_normal): Likewise.
1314 (extract_1): Likewise.
1315 * bpf-dis.c: Regenerate.
1316 * bpf-ibld.c: Likewise.
1317 * bpf-ibld.c: Likewise.
1318 * cgen-dis.in: Likewise.
1319 * cgen-ibld.in: Likewise.
1320 * cgen-opc.c: Likewise.
1321 * epiphany-dis.c: Likewise.
1322 * epiphany-ibld.c: Likewise.
1323 * fr30-dis.c: Likewise.
1324 * fr30-ibld.c: Likewise.
1325 * frv-dis.c: Likewise.
1326 * frv-ibld.c: Likewise.
1327 * ip2k-dis.c: Likewise.
1328 * ip2k-ibld.c: Likewise.
1329 * iq2000-dis.c: Likewise.
1330 * iq2000-ibld.c: Likewise.
1331 * lm32-dis.c: Likewise.
1332 * lm32-ibld.c: Likewise.
1333 * m32c-dis.c: Likewise.
1334 * m32c-ibld.c: Likewise.
1335 * m32r-dis.c: Likewise.
1336 * m32r-ibld.c: Likewise.
1337 * mep-dis.c: Likewise.
1338 * mep-ibld.c: Likewise.
1339 * mt-dis.c: Likewise.
1340 * mt-ibld.c: Likewise.
1341 * or1k-dis.c: Likewise.
1342 * or1k-ibld.c: Likewise.
1343 * xc16x-dis.c: Likewise.
1344 * xc16x-ibld.c: Likewise.
1345 * xstormy16-dis.c: Likewise.
1346 * xstormy16-ibld.c: Likewise.
1347
b3db6d07
JM		 13482020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1349
1350 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1351 (print_insn_): Handle instruction endian.
1352 * bpf-dis.c: Regenerate.
1353 * bpf-desc.c: Regenerate.
1354 * epiphany-dis.c: Likewise.
1355 * epiphany-desc.c: Likewise.
1356 * fr30-dis.c: Likewise.
1357 * fr30-desc.c: Likewise.
1358 * frv-dis.c: Likewise.
1359 * frv-desc.c: Likewise.
1360 * ip2k-dis.c: Likewise.
1361 * ip2k-desc.c: Likewise.
1362 * iq2000-dis.c: Likewise.
1363 * iq2000-desc.c: Likewise.
1364 * lm32-dis.c: Likewise.
1365 * lm32-desc.c: Likewise.
1366 * m32c-dis.c: Likewise.
1367 * m32c-desc.c: Likewise.
1368 * m32r-dis.c: Likewise.
1369 * m32r-desc.c: Likewise.
1370 * mep-dis.c: Likewise.
1371 * mep-desc.c: Likewise.
1372 * mt-dis.c: Likewise.
1373 * mt-desc.c: Likewise.
1374 * or1k-dis.c: Likewise.
1375 * or1k-desc.c: Likewise.
1376 * xc16x-dis.c: Likewise.
1377 * xc16x-desc.c: Likewise.
1378 * xstormy16-dis.c: Likewise.
1379 * xstormy16-desc.c: Likewise.
1380
4ee4189f
NC		 13812020-06-03 Nick Clifton <nickc@redhat.com>
1382
1383 * po/sr.po: Updated Serbian translation.
1384
44730156
NC		 13852020-06-03 Nelson Chu <nelson.chu@sifive.com>
1386
1387 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1388 (riscv_get_priv_spec_class): Likewise.
1389
3c3d0376
AM		 13902020-06-01 Alan Modra <amodra@gmail.com>
1391
1392 * bpf-desc.c: Regenerate.
1393
78c1c354
JM		 13942020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1395 David Faust <david.faust@oracle.com>
1396
1397 * bpf-desc.c: Regenerate.
1398 * bpf-opc.h: Likewise.
1399 * bpf-opc.c: Likewise.
1400 * bpf-dis.c: Likewise.
1401
efcf5fb5
AM		 14022020-05-28 Alan Modra <amodra@gmail.com>
1403
1404 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1405 values.
1406
ab382d64
AM		 14072020-05-28 Alan Modra <amodra@gmail.com>
1408
1409 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1410 immediates.
1411 (print_insn_ns32k): Revert last change.
1412
151f5de4
NC		 14132020-05-28 Nick Clifton <nickc@redhat.com>
1414
1415 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1416 static.
1417
25e1eca8
SL		 14182020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1419
1420 Fix extraction of signed constants in nios2 disassembler (again).
1421
1422 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1423 extractions of signed fields.
1424
57b17940
SSF		 14252020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1426
1427 * s390-opc.txt: Relocate vector load/store instructions with
1428 additional alignment parameter and change architecture level
1429 constraint from z14 to z13.
1430
d96bf37b
AM		 14312020-05-21 Alan Modra <amodra@gmail.com>
1432
1433 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1434 * sparc-dis.c: Likewise.
1435 * tic4x-dis.c: Likewise.
1436 * xtensa-dis.c: Likewise.
1437 * bpf-desc.c: Regenerate.
1438 * epiphany-desc.c: Regenerate.
1439 * fr30-desc.c: Regenerate.
1440 * frv-desc.c: Regenerate.
1441 * ip2k-desc.c: Regenerate.
1442 * iq2000-desc.c: Regenerate.
1443 * lm32-desc.c: Regenerate.
1444 * m32c-desc.c: Regenerate.
1445 * m32r-desc.c: Regenerate.
1446 * mep-asm.c: Regenerate.
1447 * mep-desc.c: Regenerate.
1448 * mt-desc.c: Regenerate.
1449 * or1k-desc.c: Regenerate.
1450 * xc16x-desc.c: Regenerate.
1451 * xstormy16-desc.c: Regenerate.
1452
8f595e9b
NC		 14532020-05-20 Nelson Chu <nelson.chu@sifive.com>
1454
1455 * riscv-opc.c (riscv_ext_version_table): The table used to store
1456 all information about the supported spec and the corresponding ISA
1457 versions. Currently, only Zicsr is supported to verify the
1458 correctness of Z sub extension settings. Others will be supported
1459 in the future patches.
1460 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1461 classes and the corresponding strings.
1462 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1463 spec class by giving a ISA spec string.
1464 * riscv-opc.c (struct priv_spec_t): New structure.
1465 (struct priv_spec_t priv_specs): List for all supported privilege spec
1466 classes and the corresponding strings.
1467 (riscv_get_priv_spec_class): New function. Get the corresponding
1468 privilege spec class by giving a spec string.
1469 (riscv_get_priv_spec_name): New function. Get the corresponding
1470 privilege spec string by giving a CSR version class.
1471 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1472 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1473 according to the chosen version. Build a hash table riscv_csr_hash to
1474 store the valid CSR for the chosen pirv verison. Dump the direct
1475 CSR address rather than it's name if it is invalid.
1476 (parse_riscv_dis_option_without_args): New function. Parse the options
1477 without arguments.
1478 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1479 parse the options without arguments first, and then handle the options
1480 with arguments. Add the new option -Mpriv-spec, which has argument.
1481 * riscv-dis.c (print_riscv_disassembler_options): Add description
1482 about the new OBJDUMP option.
1483
3d205eb4
PB		 14842020-05-19 Peter Bergner <bergner@linux.ibm.com>
1485
1486 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1487 WC values on POWER10 sync, dcbf and wait instructions.
1488 (insert_pl, extract_pl): New functions.
1489 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1490 (LS3): New , 3-bit L for sync.
1491 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1492 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1493 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1494 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1495 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1496 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1497 <wait>: Enable PL operand on POWER10.
1498 <dcbf>: Enable L3OPT operand on POWER10.
1499 <sync>: Enable SC2 operand on POWER10.
1500
a501eb44
SH		 15012020-05-19 Stafford Horne <shorne@gmail.com>
1502
1503 PR 25184
1504 * or1k-asm.c: Regenerate.
1505 * or1k-desc.c: Regenerate.
1506 * or1k-desc.h: Regenerate.
1507 * or1k-dis.c: Regenerate.
1508 * or1k-ibld.c: Regenerate.
1509 * or1k-opc.c: Regenerate.
1510 * or1k-opc.h: Regenerate.
1511 * or1k-opinst.c: Regenerate.
1512
3b646889
AM		 15132020-05-11 Alan Modra <amodra@gmail.com>
1514
1515 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1516 xsmaxcqp, xsmincqp.
1517
9cc4ce88
AM		 15182020-05-11 Alan Modra <amodra@gmail.com>
1519
1520 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1521 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1522
5d57bc3f
AM		 15232020-05-11 Alan Modra <amodra@gmail.com>
1524
1525 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1526
66ef5847
AM		 15272020-05-11 Alan Modra <amodra@gmail.com>
1528
1529 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1530 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1531
4f3e9537
PB		 15322020-05-11 Peter Bergner <bergner@linux.ibm.com>
1533
1534 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1535 mnemonics.
1536
ec40e91c
AM		 15372020-05-11 Alan Modra <amodra@gmail.com>
1538
1539 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1540 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1541 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1542 (prefix_opcodes): Add xxeval.
1543
d7e97a76
AM		 15442020-05-11 Alan Modra <amodra@gmail.com>
1545
1546 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1547 xxgenpcvwm, xxgenpcvdm.
1548
fdefed7c
AM		 15492020-05-11 Alan Modra <amodra@gmail.com>
1550
1551 * ppc-opc.c (MP, VXVAM_MASK): Define.
1552 (VXVAPS_MASK): Use VXVA_MASK.
1553 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1554 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1555 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1556 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1557
aa3c112f
AM		 15582020-05-11 Alan Modra <amodra@gmail.com>
1559 Peter Bergner <bergner@linux.ibm.com>
1560
1561 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1562 New functions.
1563 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1564 YMSK2, XA6a, XA6ap, XB6a entries.
1565 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1566 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1567 (PPCVSX4): Define.
1568 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1569 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1570 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1571 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1572 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1573 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1574 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1575 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1576 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1577 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1578 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1579 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1580 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1581 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1582
6edbfd3b
AM		 15832020-05-11 Alan Modra <amodra@gmail.com>
1584
1585 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1586 (insert_xts, extract_xts): New functions.
1587 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1588 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1589 (VXRC_MASK, VXSH_MASK): Define.
1590 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1591 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1592 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1593 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1594 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1595 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1596 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1597
c7d7aea2
AM		 15982020-05-11 Alan Modra <amodra@gmail.com>
1599
1600 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1601 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1602 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1603 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1604 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1605
94ba9882
AM		 16062020-05-11 Alan Modra <amodra@gmail.com>
1607
1608 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1609 (XTP, DQXP, DQXP_MASK): Define.
1610 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1611 (prefix_opcodes): Add plxvp and pstxvp.
1612
f4791f1a
AM		 16132020-05-11 Alan Modra <amodra@gmail.com>
1614
1615 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1616 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1617 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1618
3ff0a5ba
PB		 16192020-05-11 Peter Bergner <bergner@linux.ibm.com>
1620
1621 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1622
afef4fe9
PB		 16232020-05-11 Peter Bergner <bergner@linux.ibm.com>
1624
1625 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1626 (L1OPT): Define.
1627 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1628
1224c05d
PB		 16292020-05-11 Peter Bergner <bergner@linux.ibm.com>
1630
1631 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1632
6bbb0c05
AM		 16332020-05-11 Alan Modra <amodra@gmail.com>
1634
1635 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1636
7c1f4227
AM		 16372020-05-11 Alan Modra <amodra@gmail.com>
1638
1639 * ppc-dis.c (ppc_opts): Add "power10" entry.
1640 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1641 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1642
73199c2b
NC		 16432020-05-11 Nick Clifton <nickc@redhat.com>
1644
1645 * po/fr.po: Updated French translation.
1646
09c1e68a
AC		 16472020-04-30 Alex Coplan <alex.coplan@arm.com>
1648
1649 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1650 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1651 (operand_general_constraint_met_p): validate
1652 AARCH64_OPND_UNDEFINED.
1653 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1654 for FLD_imm16_2.
1655 * aarch64-asm-2.c: Regenerated.
1656 * aarch64-dis-2.c: Regenerated.
1657 * aarch64-opc-2.c: Regenerated.
1658
9654d51a
NC		 16592020-04-29 Nick Clifton <nickc@redhat.com>
1660
1661 PR 22699
1662 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1663 and SETRC insns.
1664
c2e71e57
NC		 16652020-04-29 Nick Clifton <nickc@redhat.com>
1666
1667 * po/sv.po: Updated Swedish translation.
1668
5c936ef5
NC		 16692020-04-29 Nick Clifton <nickc@redhat.com>
1670
1671 PR 22699
1672 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1673 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1674 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1675 IMM0_8U case.
1676
bb2a1453
AS		 16772020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1678
1679 PR 25848
1680 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1681 cmpi only on m68020up and cpu32.
1682
c2e5c986
SD		 16832020-04-20 Sudakshina Das <sudi.das@arm.com>
1684
1685 * aarch64-asm.c (aarch64_ins_none): New.
1686 * aarch64-asm.h (ins_none): New declaration.
1687 * aarch64-dis.c (aarch64_ext_none): New.
1688 * aarch64-dis.h (ext_none): New declaration.
1689 * aarch64-opc.c (aarch64_print_operand): Update case for
1690 AARCH64_OPND_BARRIER_PSB.
1691 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1692 (AARCH64_OPERANDS): Update inserter/extracter for
1693 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1694 * aarch64-asm-2.c: Regenerated.
1695 * aarch64-dis-2.c: Regenerated.
1696 * aarch64-opc-2.c: Regenerated.
1697
8a6e1d1d
SD		 16982020-04-20 Sudakshina Das <sudi.das@arm.com>
1699
1700 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1701 (aarch64_feature_ras, RAS): Likewise.
1702 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1703 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1704 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1705 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1706 * aarch64-asm-2.c: Regenerated.
1707 * aarch64-dis-2.c: Regenerated.
1708 * aarch64-opc-2.c: Regenerated.
1709
e409955d
FS		 17102020-04-17 Fredrik Strupe <fredrik@strupe.net>
1711
1712 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1713 (print_insn_neon): Support disassembly of conditional
1714 instructions.
1715
c54a9b56
DF		 17162020-02-16 David Faust <david.faust@oracle.com>
1717
1718 * bpf-desc.c: Regenerate.
1719 * bpf-desc.h: Likewise.
1720 * bpf-opc.c: Regenerate.
1721 * bpf-opc.h: Likewise.
1722
bb651e8b
CL		 17232020-04-07 Lili Cui <lili.cui@intel.com>
1724
1725 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1726 (prefix_table): New instructions (see prefixes above).
1727 (rm_table): Likewise
1728 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1729 CPU_ANY_TSXLDTRK_FLAGS.
1730 (cpu_flags): Add CpuTSXLDTRK.
1731 * i386-opc.h (enum): Add CpuTSXLDTRK.
1732 (i386_cpu_flags): Add cputsxldtrk.
1733 * i386-opc.tbl: Add XSUSPLDTRK insns.
1734 * i386-init.h: Regenerate.
1735 * i386-tbl.h: Likewise.
1736
4b27d27c
L		 17372020-04-02 Lili Cui <lili.cui@intel.com>
1738
1739 * i386-dis.c (prefix_table): New instructions serialize.
1740 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1741 CPU_ANY_SERIALIZE_FLAGS.
1742 (cpu_flags): Add CpuSERIALIZE.
1743 * i386-opc.h (enum): Add CpuSERIALIZE.
1744 (i386_cpu_flags): Add cpuserialize.
1745 * i386-opc.tbl: Add SERIALIZE insns.
1746 * i386-init.h: Regenerate.
1747 * i386-tbl.h: Likewise.
1748
832a5807
AM		 17492020-03-26 Alan Modra <amodra@gmail.com>
1750
1751 * disassemble.h (opcodes_assert): Declare.
1752 (OPCODES_ASSERT): Define.
1753 * disassemble.c: Don't include assert.h. Include opintl.h.
1754 (opcodes_assert): New function.
1755 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1756 (bfd_h8_disassemble): Reduce size of data array. Correctly
1757 calculate maxlen. Omit insn decoding when insn length exceeds
1758 maxlen. Exit from nibble loop when looking for E, before
1759 accessing next data byte. Move processing of E outside loop.
1760 Replace tests of maxlen in loop with assertions.
1761
4c4addbe
AM		 17622020-03-26 Alan Modra <amodra@gmail.com>
1763
1764 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1765
a18cd0ca
AM		 17662020-03-25 Alan Modra <amodra@gmail.com>
1767
1768 * z80-dis.c (suffix): Init mybuf.
1769
57cb32b3
AM		 17702020-03-22 Alan Modra <amodra@gmail.com>
1771
1772 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1773 successflly read from section.
1774
beea5cc1
AM		 17752020-03-22 Alan Modra <amodra@gmail.com>
1776
1777 * arc-dis.c (find_format): Use ISO C string concatenation rather
1778 than line continuation within a string. Don't access needs_limm
1779 before testing opcode != NULL.
1780
03704c77
AM		 17812020-03-22 Alan Modra <amodra@gmail.com>
1782
1783 * ns32k-dis.c (print_insn_arg): Update comment.
1784 (print_insn_ns32k): Reduce size of index_offset array, and
1785 initialize, passing -1 to print_insn_arg for args that are not
1786 an index. Don't exit arg loop early. Abort on bad arg number.
1787
d1023b5d
AM		 17882020-03-22 Alan Modra <amodra@gmail.com>
1789
1790 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1791 * s12z-opc.c: Formatting.
1792 (operands_f): Return an int.
1793 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1794 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1795 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1796 (exg_sex_discrim): Likewise.
1797 (create_immediate_operand, create_bitfield_operand),
1798 (create_register_operand_with_size, create_register_all_operand),
1799 (create_register_all16_operand, create_simple_memory_operand),
1800 (create_memory_operand, create_memory_auto_operand): Don't
1801 segfault on malloc failure.
1802 (z_ext24_decode): Return an int status, negative on fail, zero
1803 on success.
1804 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1805 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1806 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1807 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1808 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1809 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1810 (loop_primitive_decode, shift_decode, psh_pul_decode),
1811 (bit_field_decode): Similarly.
1812 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1813 to return value, update callers.
1814 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1815 Don't segfault on NULL operand.
1816 (decode_operation): Return OP_INVALID on first fail.
1817 (decode_s12z): Check all reads, returning -1 on fail.
1818
340f3ac8
AM		 18192020-03-20 Alan Modra <amodra@gmail.com>
1820
1821 * metag-dis.c (print_insn_metag): Don't ignore status from
1822 read_memory_func.
1823
fe90ae8a
AM		 18242020-03-20 Alan Modra <amodra@gmail.com>
1825
1826 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1827 Initialize parts of buffer not written when handling a possible
1828 2-byte insn at end of section. Don't attempt decoding of such
1829 an insn by the 4-byte machinery.
1830
833d919c
AM		 18312020-03-20 Alan Modra <amodra@gmail.com>
1832
1833 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1834 partially filled buffer. Prevent lookup of 4-byte insns when
1835 only VLE 2-byte insns are possible due to section size. Print
1836 ".word" rather than ".long" for 2-byte leftovers.
1837
327ef784
NC		 18382020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1839
1840 PR 25641
1841 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1842
1673df32
JB		 18432020-03-13 Jan Beulich <jbeulich@suse.com>
1844
1845 * i386-dis.c (X86_64_0D): Rename to ...
1846 (X86_64_0E): ... this.
1847
384f3689
L		 18482020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1849
1850 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1851 * Makefile.in: Regenerated.
1852
865e2027
JB		 18532020-03-09 Jan Beulich <jbeulich@suse.com>
1854
1855 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1856 3-operand pseudos.
1857 * i386-tbl.h: Re-generate.
1858
2f13234b
JB		 18592020-03-09 Jan Beulich <jbeulich@suse.com>
1860
1861 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1862 vprot*, vpsha*, and vpshl*.
1863 * i386-tbl.h: Re-generate.
1864
3fabc179
JB		 18652020-03-09 Jan Beulich <jbeulich@suse.com>
1866
1867 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1868 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1869 * i386-tbl.h: Re-generate.
1870
3677e4c1
JB		 18712020-03-09 Jan Beulich <jbeulich@suse.com>
1872
1873 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1874 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1875 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1876 * i386-tbl.h: Re-generate.
1877
4c4898e8
JB		 18782020-03-09 Jan Beulich <jbeulich@suse.com>
1879
1880 * i386-gen.c (struct template_arg, struct template_instance,
1881 struct template_param, struct template, templates,
1882 parse_template, expand_templates): New.
1883 (process_i386_opcodes): Various local variables moved to
1884 expand_templates. Call parse_template and expand_templates.
1885 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1886 * i386-tbl.h: Re-generate.
1887
bc49bfd8
JB		 18882020-03-06 Jan Beulich <jbeulich@suse.com>
1889
1890 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1891 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1892 register and memory source templates. Replace VexW= by VexW*
1893 where applicable.
1894 * i386-tbl.h: Re-generate.
1895
4873e243
JB		 18962020-03-06 Jan Beulich <jbeulich@suse.com>
1897
1898 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1899 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1900 * i386-tbl.h: Re-generate.
1901
672a349b
JB		 19022020-03-06 Jan Beulich <jbeulich@suse.com>
1903
1904 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1905 * i386-tbl.h: Re-generate.
1906
4ed21b58
JB		 19072020-03-06 Jan Beulich <jbeulich@suse.com>
1908
1909 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1910 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1911 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1912 VexW0 on SSE2AVX variants.
1913 (vmovq): Drop NoRex64 from XMM/XMM variants.
1914 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1915 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1916 applicable use VexW0.
1917 * i386-tbl.h: Re-generate.
1918
643bb870
JB		 19192020-03-06 Jan Beulich <jbeulich@suse.com>
1920
1921 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1922 * i386-opc.h (Rex64): Delete.
1923 (struct i386_opcode_modifier): Remove rex64 field.
1924 * i386-opc.tbl (crc32): Drop Rex64.
1925 Replace Rex64 with Size64 everywhere else.
1926 * i386-tbl.h: Re-generate.
1927
a23b33b3
JB		 19282020-03-06 Jan Beulich <jbeulich@suse.com>
1929
1930 * i386-dis.c (OP_E_memory): Exclude recording of used address
1931 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1932 addressed memory operands for MPX insns.
1933
a0497384
JB		 19342020-03-06 Jan Beulich <jbeulich@suse.com>
1935
1936 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1937 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1938 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1939 (ptwrite): Split into non-64-bit and 64-bit forms.
1940 * i386-tbl.h: Re-generate.
1941
b630c145
JB		 19422020-03-06 Jan Beulich <jbeulich@suse.com>
1943
1944 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1945 template.
1946 * i386-tbl.h: Re-generate.
1947
a847e322
JB		 19482020-03-04 Jan Beulich <jbeulich@suse.com>
1949
1950 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1951 (prefix_table): Move vmmcall here. Add vmgexit.
1952 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1953 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1954 (cpu_flags): Add CpuSEV_ES entry.
1955 * i386-opc.h (CpuSEV_ES): New.
1956 (union i386_cpu_flags): Add cpusev_es field.
1957 * i386-opc.tbl (vmgexit): New.
1958 * i386-init.h, i386-tbl.h: Re-generate.
1959
3cd7f3e3
L		 19602020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1961
1962 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1963 with MnemonicSize.
1964 * i386-opc.h (IGNORESIZE): New.
1965 (DEFAULTSIZE): Likewise.
1966 (IgnoreSize): Removed.
1967 (DefaultSize): Likewise.
1968 (MnemonicSize): New.
1969 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1970 mnemonicsize.
1971 * i386-opc.tbl (IgnoreSize): New.
1972 (DefaultSize): Likewise.
1973 * i386-tbl.h: Regenerated.
1974
b8ba1385
SB		 19752020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1976
1977 PR 25627
1978 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1979 instructions.
1980
10d97a0f
L		 19812020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1982
1983 PR gas/25622
1984 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1985 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1986 * i386-tbl.h: Regenerated.
1987
dc1e8a47
AM		 19882020-02-26 Alan Modra <amodra@gmail.com>
1989
1990 * aarch64-asm.c: Indent labels correctly.
1991 * aarch64-dis.c: Likewise.
1992 * aarch64-gen.c: Likewise.
1993 * aarch64-opc.c: Likewise.
1994 * alpha-dis.c: Likewise.
1995 * i386-dis.c: Likewise.
1996 * nds32-asm.c: Likewise.
1997 * nfp-dis.c: Likewise.
1998 * visium-dis.c: Likewise.
1999
265b4673
CZ		 20002020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2001
2002 * arc-regs.h (int_vector_base): Make it available for all ARC
2003 CPUs.
2004
bd0cf5a6
NC		 20052020-02-20 Nelson Chu <nelson.chu@sifive.com>
2006
2007 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2008 changed.
2009
fa164239
JW		 20102020-02-19 Nelson Chu <nelson.chu@sifive.com>
2011
2012 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2013 c.mv/c.li if rs1 is zero.
2014
272a84b1
L		 20152020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2016
2017 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2018 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2019 CPU_POPCNT_FLAGS.
2020 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2021 * i386-opc.h (CpuABM): Removed.
2022 (CpuPOPCNT): New.
2023 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2024 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2025 popcnt. Remove CpuABM from lzcnt.
2026 * i386-init.h: Regenerated.
2027 * i386-tbl.h: Likewise.
2028
1f730c46
JB		 20292020-02-17 Jan Beulich <jbeulich@suse.com>
2030
2031 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2032 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2033 VexW1 instead of open-coding them.
2034 * i386-tbl.h: Re-generate.
2035
c8f8eebc
JB		 20362020-02-17 Jan Beulich <jbeulich@suse.com>
2037
2038 * i386-opc.tbl (AddrPrefixOpReg): Define.
2039 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2040 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2041 templates. Drop NoRex64.
2042 * i386-tbl.h: Re-generate.
2043
b9915cbc
JB		 20442020-02-17 Jan Beulich <jbeulich@suse.com>
2045
2046 PR gas/6518
2047 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2048 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2049 into Intel syntax instance (with Unpsecified) and AT&T one
2050 (without).
2051 (vcvtneps2bf16): Likewise, along with folding the two so far
2052 separate ones.
2053 * i386-tbl.h: Re-generate.
2054
ce504911
L		 20552020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2056
2057 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2058 CPU_ANY_SSE4A_FLAGS.
2059
dabec65d
AM		 20602020-02-17 Alan Modra <amodra@gmail.com>
2061
2062 * i386-gen.c (cpu_flag_init): Correct last change.
2063
af5c13b0
L		 20642020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2065
2066 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2067 CPU_ANY_SSE4_FLAGS.
2068
6867aac0
L		 20692020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2070
2071 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2072 (movzx): Likewise.
2073
65fca059
JB		 20742020-02-14 Jan Beulich <jbeulich@suse.com>
2075
2076 PR gas/25438
2077 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2078 destination for Cpu64-only variant.
2079 (movzx): Fold patterns.
2080 * i386-tbl.h: Re-generate.
2081
7deea9aa
JB		 20822020-02-13 Jan Beulich <jbeulich@suse.com>
2083
2084 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2085 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2086 CPU_ANY_SSE4_FLAGS entry.
2087 * i386-init.h: Re-generate.
2088
6c0946d0
JB		 20892020-02-12 Jan Beulich <jbeulich@suse.com>
2090
2091 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2092 with Unspecified, making the present one AT&T syntax only.
2093 * i386-tbl.h: Re-generate.
2094
ddb56fe6
JB		 20952020-02-12 Jan Beulich <jbeulich@suse.com>
2096
2097 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2098 * i386-tbl.h: Re-generate.
2099
5990e377
JB		 21002020-02-12 Jan Beulich <jbeulich@suse.com>
2101
2102 PR gas/24546
2103 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2104 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2105 Amd64 and Intel64 templates.
2106 (call, jmp): Likewise for far indirect variants. Dro
2107 Unspecified.
2108 * i386-tbl.h: Re-generate.
2109
50128d0c
JB		 21102020-02-11 Jan Beulich <jbeulich@suse.com>
2111
2112 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2113 * i386-opc.h (ShortForm): Delete.
2114 (struct i386_opcode_modifier): Remove shortform field.
2115 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2116 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2117 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2118 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2119 Drop ShortForm.
2120 * i386-tbl.h: Re-generate.
2121
1e05b5c4
JB		 21222020-02-11 Jan Beulich <jbeulich@suse.com>
2123
2124 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2125 fucompi): Drop ShortForm from operand-less templates.
2126 * i386-tbl.h: Re-generate.
2127
2f5dd314
AM		 21282020-02-11 Alan Modra <amodra@gmail.com>
2129
2130 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2131 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2132 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2133 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2134 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2135
5aae9ae9
MM		 21362020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2137
2138 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2139 (cde_opcodes): Add VCX* instructions.
2140
4934a27c
MM		 21412020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2142 Matthew Malcomson <matthew.malcomson@arm.com>
2143
2144 * arm-dis.c (struct cdeopcode32): New.
2145 (CDE_OPCODE): New macro.
2146 (cde_opcodes): New disassembly table.
2147 (regnames): New option to table.
2148 (cde_coprocs): New global variable.
2149 (print_insn_cde): New
2150 (print_insn_thumb32): Use print_insn_cde.
2151 (parse_arm_disassembler_options): Parse coprocN args.
2152
4b5aaf5f
L		 21532020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2154
2155 PR gas/25516
2156 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2157 with ISA64.
2158 * i386-opc.h (AMD64): Removed.
2159 (Intel64): Likewose.
2160 (AMD64): New.
2161 (INTEL64): Likewise.
2162 (INTEL64ONLY): Likewise.
2163 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2164 * i386-opc.tbl (Amd64): New.
2165 (Intel64): Likewise.
2166 (Intel64Only): Likewise.
2167 Replace AMD64 with Amd64. Update sysenter/sysenter with
2168 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2169 * i386-tbl.h: Regenerated.
2170
9fc0b501
SB		 21712020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2172
2173 PR 25469
2174 * z80-dis.c: Add support for GBZ80 opcodes.
2175
c5d7be0c
AM		 21762020-02-04 Alan Modra <amodra@gmail.com>
2177
2178 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2179
44e4546f
AM		 21802020-02-03 Alan Modra <amodra@gmail.com>
2181
2182 * m32c-ibld.c: Regenerate.
2183
b2b1453a
AM		 21842020-02-01 Alan Modra <amodra@gmail.com>
2185
2186 * frv-ibld.c: Regenerate.
2187
4102be5c
JB		 21882020-01-31 Jan Beulich <jbeulich@suse.com>
2189
2190 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2191 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2192 (OP_E_memory): Replace xmm_mdq_mode case label by
2193 vex_scalar_w_dq_mode one.
2194 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2195
825bd36c
JB		 21962020-01-31 Jan Beulich <jbeulich@suse.com>
2197
2198 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2199 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2200 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2201 (intel_operand_size): Drop vex_w_dq_mode case label.
2202
c3036ed0
RS		 22032020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2204
2205 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2206 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2207
0c115f84
AM		 22082020-01-30 Alan Modra <amodra@gmail.com>
2209
2210 * m32c-ibld.c: Regenerate.
2211
bd434cc4
JM		 22122020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2213
2214 * bpf-opc.c: Regenerate.
2215
aeab2b26
JB		 22162020-01-30 Jan Beulich <jbeulich@suse.com>
2217
2218 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2219 (dis386): Use them to replace C2/C3 table entries.
2220 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2221 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2222 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2223 * i386-tbl.h: Re-generate.
2224
62b3f548
JB		 22252020-01-30 Jan Beulich <jbeulich@suse.com>
2226
2227 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2228 forms.
2229 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2230 DefaultSize.
2231 * i386-tbl.h: Re-generate.
2232
1bd8ae10
AM		 22332020-01-30 Alan Modra <amodra@gmail.com>
2234
2235 * tic4x-dis.c (tic4x_dp): Make unsigned.
2236
bc31405e
L		 22372020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2238 Jan Beulich <jbeulich@suse.com>
2239
2240 PR binutils/25445
2241 * i386-dis.c (MOVSXD_Fixup): New function.
2242 (movsxd_mode): New enum.
2243 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2244 (intel_operand_size): Handle movsxd_mode.
2245 (OP_E_register): Likewise.
2246 (OP_G): Likewise.
2247 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2248 register on movsxd. Add movsxd with 16-bit destination register
2249 for AMD64 and Intel64 ISAs.
2250 * i386-tbl.h: Regenerated.
2251
7568c93b
TC		 22522020-01-27 Tamar Christina <tamar.christina@arm.com>
2253
2254 PR 25403
2255 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2256 * aarch64-asm-2.c: Regenerate
2257 * aarch64-dis-2.c: Likewise.
2258 * aarch64-opc-2.c: Likewise.
2259
c006a730
JB		 22602020-01-21 Jan Beulich <jbeulich@suse.com>
2261
2262 * i386-opc.tbl (sysret): Drop DefaultSize.
2263 * i386-tbl.h: Re-generate.
2264
c906a69a
JB		 22652020-01-21 Jan Beulich <jbeulich@suse.com>
2266
2267 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2268 Dword.
2269 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2270 * i386-tbl.h: Re-generate.
2271
26916852
NC		 22722020-01-20 Nick Clifton <nickc@redhat.com>
2273
2274 * po/de.po: Updated German translation.
2275 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2276 * po/uk.po: Updated Ukranian translation.
2277
4d6cbb64
AM		 22782020-01-20 Alan Modra <amodra@gmail.com>
2279
2280 * hppa-dis.c (fput_const): Remove useless cast.
2281
2bddb71a
AM		 22822020-01-20 Alan Modra <amodra@gmail.com>
2283
2284 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2285
1b1bb2c6
NC		 22862020-01-18 Nick Clifton <nickc@redhat.com>
2287
2288 * configure: Regenerate.
2289 * po/opcodes.pot: Regenerate.
2290
ae774686
NC		 22912020-01-18 Nick Clifton <nickc@redhat.com>
2292
2293 Binutils 2.34 branch created.
2294
07f1f3aa
CB		 22952020-01-17 Christian Biesinger <cbiesinger@google.com>
2296
2297 * opintl.h: Fix spelling error (seperate).
2298
42e04b36
L		 22992020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2300
2301 * i386-opc.tbl: Add {vex} pseudo prefix.
2302 * i386-tbl.h: Regenerated.
2303
2da2eaf4
AV		 23042020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2305
2306 PR 25376
2307 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2308 (neon_opcodes): Likewise.
2309 (select_arm_features): Make sure we enable MVE bits when selecting
2310 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2311 any architecture.
2312
d0849eed
JB		 23132020-01-16 Jan Beulich <jbeulich@suse.com>
2314
2315 * i386-opc.tbl: Drop stale comment from XOP section.
2316
9cf70a44
JB		 23172020-01-16 Jan Beulich <jbeulich@suse.com>
2318
2319 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2320 (extractps): Add VexWIG to SSE2AVX forms.
2321 * i386-tbl.h: Re-generate.
2322
4814632e
JB		 23232020-01-16 Jan Beulich <jbeulich@suse.com>
2324
2325 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2326 Size64 from and use VexW1 on SSE2AVX forms.
2327 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2328 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2329 * i386-tbl.h: Re-generate.
2330
aad09917
AM		 23312020-01-15 Alan Modra <amodra@gmail.com>
2332
2333 * tic4x-dis.c (tic4x_version): Make unsigned long.
2334 (optab, optab_special, registernames): New file scope vars.
2335 (tic4x_print_register): Set up registernames rather than
2336 malloc'd registertable.
2337 (tic4x_disassemble): Delete optable and optable_special. Use
2338 optab and optab_special instead. Throw away old optab,
2339 optab_special and registernames when info->mach changes.
2340
7a6bf3be
SB		 23412020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2342
2343 PR 25377
2344 * z80-dis.c (suffix): Use .db instruction to generate double
2345 prefix.
2346
ca1eaac0
AM		 23472020-01-14 Alan Modra <amodra@gmail.com>
2348
2349 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2350 values to unsigned before shifting.
2351
1d67fe3b
TT		 23522020-01-13 Thomas Troeger <tstroege@gmx.de>
2353
2354 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2355 flow instructions.
2356 (print_insn_thumb16, print_insn_thumb32): Likewise.
2357 (print_insn): Initialize the insn info.
2358 * i386-dis.c (print_insn): Initialize the insn info fields, and
2359 detect jumps.
2360
5e4f7e05
CZ		 23612012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2362
2363 * arc-opc.c (C_NE): Make it required.
2364
b9fe6b8a
CZ		 23652012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2366
2367 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2368 reserved register name.
2369
90dee485
AM		 23702020-01-13 Alan Modra <amodra@gmail.com>
2371
2372 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2373 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2374
febda64f
AM		 23752020-01-13 Alan Modra <amodra@gmail.com>
2376
2377 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2378 result of wasm_read_leb128 in a uint64_t and check that bits
2379 are not lost when copying to other locals. Use uint32_t for
2380 most locals. Use PRId64 when printing int64_t.
2381
df08b588
AM		 23822020-01-13 Alan Modra <amodra@gmail.com>
2383
2384 * score-dis.c: Formatting.
2385 * score7-dis.c: Formatting.
2386
b2c759ce
AM		 23872020-01-13 Alan Modra <amodra@gmail.com>
2388
2389 * score-dis.c (print_insn_score48): Use unsigned variables for
2390 unsigned values. Don't left shift negative values.
2391 (print_insn_score32): Likewise.
2392 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2393
5496abe1
AM		 23942020-01-13 Alan Modra <amodra@gmail.com>
2395
2396 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2397
202e762b
AM		 23982020-01-13 Alan Modra <amodra@gmail.com>
2399
2400 * fr30-ibld.c: Regenerate.
2401
7ef412cf
AM		 24022020-01-13 Alan Modra <amodra@gmail.com>
2403
2404 * xgate-dis.c (print_insn): Don't left shift signed value.
2405 (ripBits): Formatting, use 1u.
2406
7f578b95
AM		 24072020-01-10 Alan Modra <amodra@gmail.com>
2408
2409 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2410 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2411
441af85b
AM		 24122020-01-10 Alan Modra <amodra@gmail.com>
2413
2414 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2415 and XRREG value earlier to avoid a shift with negative exponent.
2416 * m10200-dis.c (disassemble): Similarly.
2417
bce58db4
NC		 24182020-01-09 Nick Clifton <nickc@redhat.com>
2419
2420 PR 25224
2421 * z80-dis.c (ld_ii_ii): Use correct cast.
2422
40c75bc8
SB		 24232020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2424
2425 PR 25224
2426 * z80-dis.c (ld_ii_ii): Use character constant when checking
2427 opcode byte value.
2428
d835a58b
JB		 24292020-01-09 Jan Beulich <jbeulich@suse.com>
2430
2431 * i386-dis.c (SEP_Fixup): New.
2432 (SEP): Define.
2433 (dis386_twobyte): Use it for sysenter/sysexit.
2434 (enum x86_64_isa): Change amd64 enumerator to value 1.
2435 (OP_J): Compare isa64 against intel64 instead of amd64.
2436 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2437 forms.
2438 * i386-tbl.h: Re-generate.
2439
030a2e78
AM		 24402020-01-08 Alan Modra <amodra@gmail.com>
2441
2442 * z8k-dis.c: Include libiberty.h
2443 (instr_data_s): Make max_fetched unsigned.
2444 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2445 Don't exceed byte_info bounds.
2446 (output_instr): Make num_bytes unsigned.
2447 (unpack_instr): Likewise for nibl_count and loop.
2448 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2449 idx unsigned.
2450 * z8k-opc.h: Regenerate.
2451
bb82aefe
SV		 24522020-01-07 Shahab Vahedi <shahab@synopsys.com>
2453
2454 * arc-tbl.h (llock): Use 'LLOCK' as class.
2455 (llockd): Likewise.
2456 (scond): Use 'SCOND' as class.
2457 (scondd): Likewise.
2458 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2459 (scondd): Likewise.
2460
cc6aa1a6
AM		 24612020-01-06 Alan Modra <amodra@gmail.com>
2462
2463 * m32c-ibld.c: Regenerate.
2464
660e62b1
AM		 24652020-01-06 Alan Modra <amodra@gmail.com>
2466
2467 PR 25344
2468 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2469 Peek at next byte to prevent recursion on repeated prefix bytes.
2470 Ensure uninitialised "mybuf" is not accessed.
2471 (print_insn_z80): Don't zero n_fetch and n_used here,..
2472 (print_insn_z80_buf): ..do it here instead.
2473
c9ae58fe
AM		 24742020-01-04 Alan Modra <amodra@gmail.com>
2475
2476 * m32r-ibld.c: Regenerate.
2477
5f57d4ec
AM		 24782020-01-04 Alan Modra <amodra@gmail.com>
2479
2480 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2481
2c5c1196
AM		 24822020-01-04 Alan Modra <amodra@gmail.com>
2483
2484 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2485
2e98c6c5
AM		 24862020-01-04 Alan Modra <amodra@gmail.com>
2487
2488 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2489
567dfba2
JB		 24902020-01-03 Jan Beulich <jbeulich@suse.com>
2491
5437a02a
JB		 2492 * aarch64-tbl.h (aarch64_opcode_table): Use
2493 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2494
24952020-01-03 Jan Beulich <jbeulich@suse.com>
2496
2497 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2498 forms of SUDOT and USDOT.
2499
8c45011a
JB		 25002020-01-03 Jan Beulich <jbeulich@suse.com>
2501
5437a02a 2502 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2503 uzip{1,2}.
2504 * opcodes/aarch64-dis-2.c: Re-generate.
2505
f4950f76
JB		 25062020-01-03 Jan Beulich <jbeulich@suse.com>
2507
5437a02a 2508 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2509 FMMLA encoding.
2510 * opcodes/aarch64-dis-2.c: Re-generate.
2511
6655dba2
SB		 25122020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2513
2514 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2515
b14ce8bf
AM		 25162020-01-01 Alan Modra <amodra@gmail.com>
2517
2518 Update year range in copyright notice of all files.
2519
0b114740 2520For older changes see ChangeLog-2019
3499769a 2521\f
0b114740 2522Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2523
2524Copying and distribution of this file, with or without modification,
2525are permitted in any medium without royalty provided the copyright
2526notice and this notice are preserved.
2527
2528Local Variables:
2529mode: change-log
2530left-margin: 8
2531fill-column: 74
2532version-control: never
2533End:
A mirror of the official binutils-gdb repository