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x86: flag bad S/G insn operand combinations
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
596a02ff
JB		 12021-03-25 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (XMGatherD, VexGatherD): New.
4 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
5 (print_insn): Check masking for S/G insns.
6 (OP_E_memory): New local variable check_gather. Extend mandatory
7 SIB check. Check register conflicts for (EVEX-encoded) gathers.
8 Extend check for disallowed 16-bit addressing.
9 (OP_VEX): New local variables modrm_reg and sib_index. Convert
10 if()s to switch(). Check register conflicts for (VEX-encoded)
11 gathers. Drop no longer reachable cases.
12 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
13 vgatherdp*.
14
53642852
JB		 152021-03-25 Jan Beulich <jbeulich@suse.com>
16
17 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
18 zeroing-masking without masking.
19
c0e54661
JB		 202021-03-25 Jan Beulich <jbeulich@suse.com>
21
22 * i386-opc.tbl (invlpgb): Fix multi-operand form.
23 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
24 single-operand forms as deprecated.
25 * i386-tbl.h: Re-generate.
26
5a403766
AM		 272021-03-25 Alan Modra <amodra@gmail.com>
28
29 PR 27647
30 * ppc-opc.c (XLOCB_MASK): Delete.
31 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
32 XLBH_MASK.
33 (powerpc_opcodes): Accept a BH field on all extended forms of
34 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
35
9a182d04
JB		 362021-03-24 Jan Beulich <jbeulich@suse.com>
37
38 * i386-gen.c (output_i386_opcode): Drop processing of
39 opcode_length. Calculate length from base_opcode. Adjust prefix
40 encoding determination.
41 (process_i386_opcodes): Drop output of fake opcode_length.
42 * i386-opc.h (struct insn_template): Drop opcode_length field.
43 * i386-opc.tbl: Drop opcode length field from all templates.
44 * i386-tbl.h: Re-generate.
45
35648716
JB		 462021-03-24 Jan Beulich <jbeulich@suse.com>
47
48 * i386-gen.c (process_i386_opcode_modifier): Return void. New
49 parameter "prefix". Drop local variable "regular_encoding".
50 Record prefix setting / check for consistency.
51 (output_i386_opcode): Parse opcode_length and base_opcode
52 earlier. Derive prefix encoding. Drop no longer applicable
53 consistency checking. Adjust process_i386_opcode_modifier()
54 invocation.
55 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
56 invocation.
57 * i386-tbl.h: Re-generate.
58
31184569
JB		 592021-03-24 Jan Beulich <jbeulich@suse.com>
60
61 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
62 check.
63 * i386-opc.h (Prefix_*): Move #define-s.
64 * i386-opc.tbl: Move pseudo prefix enumerator values to
65 extension opcode field. Introduce pseudopfx template.
66 * i386-tbl.h: Re-generate.
67
b933fa4b
JB		 682021-03-23 Jan Beulich <jbeulich@suse.com>
69
70 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
71 comment.
72 * i386-tbl.h: Re-generate.
73
dac10fb0
JB		 742021-03-23 Jan Beulich <jbeulich@suse.com>
75
76 * i386-opc.h (struct insn_template): Move cpu_flags field past
77 opcode_modifier one.
78 * i386-tbl.h: Re-generate.
79
441f6aca
JB		 802021-03-23 Jan Beulich <jbeulich@suse.com>
81
82 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
83 * i386-opc.h (OpcodeSpace): New enumerator.
84 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
85 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
86 SPACE_XOP09, SPACE_XOP0A): ... respectively.
87 (struct i386_opcode_modifier): New field opcodespace. Shrink
88 opcodeprefix field.
89 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
90 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
91 OpcodePrefix uses.
92 * i386-tbl.h: Re-generate.
93
08dedd66
ML		 942021-03-22 Martin Liska <mliska@suse.cz>
95
96 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
97 * arc-dis.c (parse_option): Likewise.
98 * arm-dis.c (parse_arm_disassembler_options): Likewise.
99 * cris-dis.c (print_with_operands): Likewise.
100 * h8300-dis.c (bfd_h8_disassemble): Likewise.
101 * i386-dis.c (print_insn): Likewise.
102 * ia64-gen.c (fetch_insn_class): Likewise.
103 (parse_resource_users): Likewise.
104 (in_iclass): Likewise.
105 (lookup_specifier): Likewise.
106 (insert_opcode_dependencies): Likewise.
107 * mips-dis.c (parse_mips_ase_option): Likewise.
108 (parse_mips_dis_option): Likewise.
109 * s390-dis.c (disassemble_init_s390): Likewise.
110 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
111
80d49d6a
KLC		 1122021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
113
114 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
115
7fce7ea9
PW		 1162021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
117
118 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
119 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
120
78c84bf9
AM		 1212021-03-12 Alan Modra <amodra@gmail.com>
122
123 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
124
fd1fd061
JB		 1252021-03-11 Jan Beulich <jbeulich@suse.com>
126
127 * i386-dis.c (OP_XMM): Re-order checks.
128
ac7a2311
JB		 1292021-03-11 Jan Beulich <jbeulich@suse.com>
130
131 * i386-dis.c (putop): Drop need_vex check when also checking
132 vex.evex.
133 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
134 checking vex.b.
135
da944c8a
JB		 1362021-03-11 Jan Beulich <jbeulich@suse.com>
137
138 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
139 checks. Move case label past broadcast check.
140
b763d508
JB		 1412021-03-10 Jan Beulich <jbeulich@suse.com>
142
143 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
144 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
145 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
146 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
147 EVEX_W_0F38C7_M_0_L_2): Delete.
148 (REG_EVEX_0F38C7_M_0_L_2): New.
149 (intel_operand_size): Handle VEX and EVEX the same for
150 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
151 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
152 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
153 vex_vsib_q_w_d_mode uses.
154 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
155 0F38A1, and 0F38A3 entries.
156 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
157 entry.
158 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
159 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
160 0F38A3 entries.
161
32e31ad7
JB		 1622021-03-10 Jan Beulich <jbeulich@suse.com>
163
164 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
165 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
166 MOD_VEX_0FXOP_09_12): Rename to ...
167 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
168 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
169 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
170 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
171 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
172 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
173 (reg_table): Adjust comments.
174 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
175 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
176 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
177 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
178 (vex_len_table): Adjust opcode 0A_12 entry.
179 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
180 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
181 (rm_table): Move hreset entry.
182
85ba7507
JB		 1832021-03-10 Jan Beulich <jbeulich@suse.com>
184
185 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
186 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
187 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
188 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
189 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
190 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
191 (get_valid_dis386): Also handle 512-bit vector length when
192 vectoring into vex_len_table[].
193 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
194 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
195 entries.
196 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
197 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
198 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
199 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
200 entries.
201
066f82b9
JB		 2022021-03-10 Jan Beulich <jbeulich@suse.com>
203
204 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
205 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
206 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
207 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
208 entries.
209 * i386-dis-evex-len.h (evex_len_table): Likewise.
210 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
211
fc681dd6
JB		 2122021-03-10 Jan Beulich <jbeulich@suse.com>
213
214 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
215 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
216 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
217 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
218 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
219 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
220 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
221 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
222 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
223 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
224 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
225 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
226 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
227 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
228 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
229 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
230 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
231 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
232 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
233 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
234 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
235 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
236 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
237 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
238 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
239 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
240 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
241 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
242 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
243 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
244 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
245 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
246 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
247 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
248 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
249 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
250 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
251 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
252 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
253 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
254 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
255 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
256 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
257 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
258 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
259 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
260 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
261 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
262 EVEX_W_0F3A43_L_n): New.
263 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
264 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
265 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
266 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
267 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
268 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
269 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
270 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
271 0F385B, 0F38C6, and 0F38C7 entries.
272 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
273 0F38C6 and 0F38C7.
274 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
275 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
276 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
277 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
278
13954a31
JB		 2792021-03-10 Jan Beulich <jbeulich@suse.com>
280
281 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
282 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
283 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
284 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
285 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
286 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
287 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
288 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
289 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
290 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
291 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
292 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
293 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
294 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
295 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
296 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
297 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
298 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
299 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
300 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
301 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
302 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
303 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
304 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
305 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
306 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
307 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
308 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
309 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
310 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
311 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
312 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
313 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
314 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
315 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
316 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
317 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
318 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
319 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
320 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
321 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
322 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
323 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
324 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
325 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
326 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
327 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
328 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
329 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
330 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
331 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
332 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
333 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
334 VEX_W_0F99_P_2_LEN_0): Delete.
335 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
336 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
337 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
338 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
339 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
340 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
341 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
342 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
343 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
344 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
345 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
346 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
347 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
348 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
349 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
350 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
351 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
352 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
353 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
354 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
355 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
356 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
357 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
358 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
359 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
360 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
361 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
362 (prefix_table): No longer link to vex_len_table[] for opcodes
363 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
364 0F92, 0F93, 0F98, and 0F99.
365 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
366 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
367 0F98, and 0F99.
368 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
369 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
370 0F98, and 0F99.
371 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
372 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
373 0F98, and 0F99.
374 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
375 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
376 0F98, and 0F99.
377
14d10c6c
JB		 3782021-03-10 Jan Beulich <jbeulich@suse.com>
379
380 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
381 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
382 REG_VEX_0F73_M_0 respectively.
383 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
384 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
385 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
386 MOD_VEX_0F73_REG_7): Delete.
387 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
388 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
389 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
390 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
391 PREFIX_VEX_0F3AF0_L_0 respectively.
392 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
393 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
394 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
395 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
396 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
397 VEX_LEN_0F38F7): New.
398 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
399 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
400 0F72, and 0F73. No longer link to vex_len_table[] for opcode
401 0F38F3.
402 (prefix_table): No longer link to vex_len_table[] for opcodes
403 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
404 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
405 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
406 0F38F6, 0F38F7, and 0F3AF0.
407 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
408 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
409 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
410 0F73.
411
00ec1875
JB		 4122021-03-10 Jan Beulich <jbeulich@suse.com>
413
414 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
415 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
416 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
417 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
418 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
419 (MOD_0F71, MOD_0F72, MOD_0F73): New.
420 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
421 73.
422 (reg_table): No longer link to mod_table[] for opcodes 0F71,
423 0F72, and 0F73.
424 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
425 0F73.
426
31941983
JB		 4272021-03-10 Jan Beulich <jbeulich@suse.com>
428
429 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
430 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
431 (reg_table): Don't link to mod_table[] where not needed. Add
432 PREFIX_IGNORED to nop entries.
433 (prefix_table): Replace PREFIX_OPCODE in nop entries.
434 (mod_table): Add nop entries next to prefetch ones. Drop
435 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
436 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
437 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
438 PREFIX_OPCODE from endbr* entries.
439 (get_valid_dis386): Also consider entry's name when zapping
440 vindex.
441 (print_insn): Handle PREFIX_IGNORED.
442
742732c7
JB		 4432021-03-09 Jan Beulich <jbeulich@suse.com>
444
445 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
446 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
447 element.
448 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
449 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
450 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
451 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
452 (struct i386_opcode_modifier): Delete notrackprefixok,
453 islockable, hleprefixok, and repprefixok fields. Add prefixok
454 field.
455 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
456 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
457 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
458 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
459 Replace HLEPrefixOk.
460 * opcodes/i386-tbl.h: Re-generate.
461
e93a3b27
JB		 4622021-03-09 Jan Beulich <jbeulich@suse.com>
463
464 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
465 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
466 64-bit form.
467 * opcodes/i386-tbl.h: Re-generate.
468
75363b6d
JB		 4692021-03-03 Jan Beulich <jbeulich@suse.com>
470
471 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
472 for {} instead of {0}. Don't look for '0'.
473 * i386-opc.tbl: Drop operand count field. Drop redundant operand
474 size specifiers.
475
5a9f5403
NC		 4762021-02-19 Nelson Chu <nelson.chu@sifive.com>
477
478 PR 27158
479 * riscv-dis.c (print_insn_args): Updated encoding macros.
480 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
481 (match_c_addi16sp): Updated encoding macros.
482 (match_c_lui): Likewise.
483 (match_c_lui_with_hint): Likewise.
484 (match_c_addi4spn): Likewise.
485 (match_c_slli): Likewise.
486 (match_slli_as_c_slli): Likewise.
487 (match_c_slli64): Likewise.
488 (match_srxi_as_c_srxi): Likewise.
489 (riscv_insn_types): Added .insn css/cl/cs.
490
3d73d29e
NC		 4912021-02-18 Nelson Chu <nelson.chu@sifive.com>
492
493 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
494 (default_priv_spec): Updated type to riscv_spec_class.
495 (parse_riscv_dis_option): Updated.
496 * riscv-opc.c: Moved stuff and make the file tidy.
497
b9b204b3
AM		 4982021-02-17 Alan Modra <amodra@gmail.com>
499
500 * wasm32-dis.c: Include limits.h.
501 (CHAR_BIT): Provide backup define.
502 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
503 Correct signed overflow checking.
504
394ae71f
JB		 5052021-02-16 Jan Beulich <jbeulich@suse.com>
506
507 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
508 * i386-tbl.h: Re-generate.
509
b818b220
JB		 5102021-02-16 Jan Beulich <jbeulich@suse.com>
511
512 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
513 Oword.
514 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
515
ba2b480f
AK		 5162021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
517
518 * s390-mkopc.c (main): Accept arch14 as cpu string.
519 * s390-opc.txt: Add new arch14 instructions.
520
95148614
NA		 5212021-02-04 Nick Alcock <nick.alcock@oracle.com>
522
523 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
524 favour of LIBINTL.
525 * configure: Regenerated.
526
bfd428bc
MF		 5272021-02-08 Mike Frysinger <vapier@gentoo.org>
528
529 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
530 * tic54x-opc.c (regs): Rename to ...
531 (tic54x_regs): ... this.
532 (mmregs): Rename to ...
533 (tic54x_mmregs): ... this.
534 (condition_codes): Rename to ...
535 (tic54x_condition_codes): ... this.
536 (cc2_codes): Rename to ...
537 (tic54x_cc2_codes): ... this.
538 (cc3_codes): Rename to ...
539 (tic54x_cc3_codes): ... this.
540 (status_bits): Rename to ...
541 (tic54x_status_bits): ... this.
542 (misc_symbols): Rename to ...
543 (tic54x_misc_symbols): ... this.
544
24075dcc
NC		 5452021-02-04 Nelson Chu <nelson.chu@sifive.com>
546
547 * riscv-opc.c (MASK_RVB_IMM): Removed.
548 (riscv_opcodes): Removed zb* instructions.
549 (riscv_ext_version_table): Removed versions for zb*.
550
c3ffb8f3
AM		 5512021-01-26 Alan Modra <amodra@gmail.com>
552
553 * i386-gen.c (parse_template): Ensure entire template_instance
554 is initialised.
555
1942a048
NC		 5562021-01-15 Nelson Chu <nelson.chu@sifive.com>
557
558 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
559 (riscv_fpr_names_abi): Likewise.
560 (riscv_opcodes): Likewise.
561 (riscv_insn_types): Likewise.
562
b800637e
NC		 5632021-01-15 Nelson Chu <nelson.chu@sifive.com>
564
565 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
566
dcd709e0
NC		 5672021-01-15 Nelson Chu <nelson.chu@sifive.com>
568
569 * riscv-dis.c: Comments tidy and improvement.
570 * riscv-opc.c: Likewise.
571
5347ed60
AM		 5722021-01-13 Alan Modra <amodra@gmail.com>
573
574 * Makefile.in: Regenerate.
575
d546b610
L		 5762021-01-12 H.J. Lu <hongjiu.lu@intel.com>
577
578 PR binutils/26792
579 * configure.ac: Use GNU_MAKE_JOBSERVER.
580 * aclocal.m4: Regenerated.
581 * configure: Likewise.
582
6d104cac
NC		 5832021-01-12 Nick Clifton <nickc@redhat.com>
584
585 * po/sr.po: Updated Serbian translation.
586
83b33c6c
L		 5872021-01-11 H.J. Lu <hongjiu.lu@intel.com>
588
589 PR ld/27173
590 * configure: Regenerated.
591
82c70b08
KT		 5922021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
593
594 * aarch64-asm-2.c: Regenerate.
595 * aarch64-dis-2.c: Likewise.
596 * aarch64-opc-2.c: Likewise.
597 * aarch64-opc.c (aarch64_print_operand):
598 Delete handling of AARCH64_OPND_CSRE_CSR.
599 * aarch64-tbl.h (aarch64_feature_csre): Delete.
600 (CSRE): Likewise.
601 (_CSRE_INSN): Likewise.
602 (aarch64_opcode_table): Delete csr.
603
a8aa72b9
NC		 6042021-01-11 Nick Clifton <nickc@redhat.com>
605
606 * po/de.po: Updated German translation.
607 * po/fr.po: Updated French translation.
608 * po/pt_BR.po: Updated Brazilian Portuguese translation.
609 * po/sv.po: Updated Swedish translation.
610 * po/uk.po: Updated Ukranian translation.
611
a4966cd9
L		 6122021-01-09 H.J. Lu <hongjiu.lu@intel.com>
613
614 * configure: Regenerated.
615
573fe3fb
NC		 6162021-01-09 Nick Clifton <nickc@redhat.com>
617
618 * configure: Regenerate.
619 * po/opcodes.pot: Regenerate.
620
055bc77a
NC		 6212021-01-09 Nick Clifton <nickc@redhat.com>
622
623 * 2.36 release branch crated.
624
aae7fcb8
PB		 6252021-01-08 Peter Bergner <bergner@linux.ibm.com>
626
627 * ppc-opc.c (insert_dw, (extract_dw): New functions.
628 (DW, (XRC_MASK): Define.
629 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
630
64307045
AM		 6312021-01-09 Alan Modra <amodra@gmail.com>
632
633 * configure: Regenerate.
634
ed205222
NC		 6352021-01-08 Nick Clifton <nickc@redhat.com>
636
637 * po/sv.po: Updated Swedish translation.
638
fb932b57
NC		 6392021-01-08 Nick Clifton <nickc@redhat.com>
640
e84c8716
NC		 641 PR 27129
642 * aarch64-dis.c (determine_disassembling_preference): Move call to
643 aarch64_match_operands_constraint outside of the assertion.
644 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
645 Replace with a return of FALSE.
646
fb932b57
NC		 647 PR 27139
648 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
649 core system register.
650
f4782128
ST		 6512021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
652
653 * configure: Regenerate.
654
1b0927db
NC		 6552021-01-07 Nick Clifton <nickc@redhat.com>
656
657 * po/fr.po: Updated French translation.
658
3b288c8e
FN		 6592021-01-07 Fredrik Noring <noring@nocrew.org>
660
661 * m68k-opc.c (chkl): Change minimum architecture requirement to
662 m68020.
663
aa881ecd
PT		 6642021-01-07 Philipp Tomsich <prt@gnu.org>
665
666 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
667
2652cfad
CXW		 6682021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
669 Jim Wilson <jimw@sifive.com>
670 Andrew Waterman <andrew@sifive.com>
671 Maxim Blinov <maxim.blinov@embecosm.com>
672 Kito Cheng <kito.cheng@sifive.com>
673 Nelson Chu <nelson.chu@sifive.com>
674
675 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
676 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
677
250d07de
AM		 6782021-01-01 Alan Modra <amodra@gmail.com>
679
680 Update year range in copyright notice of all files.
681
c2795844 682For older changes see ChangeLog-2020
3499769a 683\f
c2795844 684Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 685
686Copying and distribution of this file, with or without modification,
687are permitted in any medium without royalty provided the copyright
688notice and this notice are preserved.
689
690Local Variables:
691mode: change-log
692left-margin: 8
693fill-column: 74
694version-control: never
695End:
A mirror of the official binutils-gdb repository