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arc: Implement NPS-400 dcmac instruction
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
5a736821
GM		 12016-11-03 Graham Markall <graham.markall@embecosm.com>
2
3 * arc-dis.c (arc_insn_length): Return length 8 for instructions with
4 major opcode 0xa.
5 * arc-nps-400-tbl.h: Add dcmac instruction.
6 * arc-opc.c (arc_operands): Added operands for dcmac instruction.
7 (insert_nps_rbdouble_64): Added.
8 (extract_nps_rbdouble_64): Added.
9 (insert_nps_proto_size): Added.
10 (extract_nps_proto_size): Added.
11
bdfe53e3
AB		 122016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
13
14 * arc-dis.c (struct arc_operand_iterator): Remove all fields
15 relating to long instruction processing, add new limm field.
16 (OPCODE): Rename to...
17 (OPCODE_32BIT_INSN): ...this.
18 (OPCODE_AC): Delete.
19 (skip_this_opcode): Handle different instruction lengths, update
20 macro name.
21 (special_flag_p): Update parameter type.
22 (find_format_from_table): Update for more instruction lengths.
23 (find_format_long_instructions): Delete.
24 (find_format): Update for more instruction lengths.
25 (arc_insn_length): Likewise.
26 (extract_operand_value): Update for more instruction lengths.
27 (operand_iterator_next): Remove code relating to long
28 instructions.
29 (arc_opcode_to_insn_type): New function.
30 (print_insn_arc):Update for more instructions lengths.
31 * arc-ext.c (extInstruction_t): Change argument type.
32 * arc-ext.h (extInstruction_t): Change argument type.
33 * arc-fxi.h: Change type unsigned to unsigned long long
34 extensively throughout.
35 * arc-nps400-tbl.h: Add long instructions taken from
36 arc_long_opcodes table in arc-opc.c.
37 * arc-opc.c: Update parameter types on insert/extract handlers.
38 (arc_long_opcodes): Delete.
39 (arc_num_long_opcodes): Delete.
40 (arc_opcode_len): Update for more instruction lengths.
41
90f61cce
GM		 422016-11-03 Graham Markall <graham.markall@embecosm.com>
43
44 * arc-dis.c (print_insn_arc): Swap highbyte and lowbyte.
45
06fe285f
GM		 462016-11-03 Graham Markall <graham.markall@embecosm.com>
47
48 * arc-dis.c (find_format_from_table): Replace use of ARC_SHORT
49 with arc_opcode_len.
50 (find_format_long_instructions): Likewise.
51 * arc-opc.c (arc_opcode_len): New function.
52
ecf64ec6
AB		 532016-11-03 Andrew Burgess <andrew.burgess@embecosm.com>
54
55 * arc-nps400-tbl.h: Fix some instruction masks.
56
d039fef3
L		 572016-11-03 H.J. Lu <hongjiu.lu@intel.com>
58
59 * i386-dis.c (REG_82): Removed.
60 (X86_64_82_REG_0): Likewise.
61 (X86_64_82_REG_1): Likewise.
62 (X86_64_82_REG_2): Likewise.
63 (X86_64_82_REG_3): Likewise.
64 (X86_64_82_REG_4): Likewise.
65 (X86_64_82_REG_5): Likewise.
66 (X86_64_82_REG_6): Likewise.
67 (X86_64_82_REG_7): Likewise.
68 (X86_64_82): New.
69 (dis386): Use X86_64_82 instead of REG_82.
70 (reg_table): Remove REG_82.
71 (x86_64_table): Add X86_64_82. Remove X86_64_82_REG_0,
72 X86_64_82_REG_1, X86_64_82_REG_2, X86_64_82_REG_3,
73 X86_64_82_REG_4, X86_64_82_REG_5, X86_64_82_REG_6 and
74 X86_64_82_REG_7.
75
8b89fe14
L		 762016-11-03 H.J. Lu <hongjiu.lu@intel.com>
77
78 PR binutils/20754
79 * i386-dis.c (REG_82): New.
80 (X86_64_82_REG_0): Likewise.
81 (X86_64_82_REG_1): Likewise.
82 (X86_64_82_REG_2): Likewise.
83 (X86_64_82_REG_3): Likewise.
84 (X86_64_82_REG_4): Likewise.
85 (X86_64_82_REG_5): Likewise.
86 (X86_64_82_REG_6): Likewise.
87 (X86_64_82_REG_7): Likewise.
88 (dis386): Use REG_82.
89 (reg_table): Add REG_82.
90 (x86_64_table): Add X86_64_82_REG_0, X86_64_82_REG_1,
91 X86_64_82_REG_2, X86_64_82_REG_3, X86_64_82_REG_4,
92 X86_64_82_REG_5, X86_64_82_REG_6 and X86_64_82_REG_7.
93
7148c369
L		 942016-11-03 H.J. Lu <hongjiu.lu@intel.com>
95
96 * i386-dis.c (REG_82): Renamed to ...
97 (REG_83): This.
98 (dis386): Updated.
99 (reg_table): Likewise.
100
47acf0bd
IT		 1012016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
102
103 * i386-dis.c (enum): Add PREFIX_EVEX_0F3852, PREFIX_EVEX_0F3853.
104 * i386-dis-evex.h (evex_table): Updated.
105 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4VNNIW_FLAGS,
106 CPU_ANY_AVX512_4VNNIW_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
107 (cpu_flags): Add CpuAVX512_4VNNIW.
108 * i386-opc.h (enum): (AVX512_4VNNIW): New.
109 (i386_cpu_flags): Add cpuavx512_4vnniw.
110 * i386-opc.tbl: Add Intel AVX512_4VNNIW instructions.
111 * i386-init.h: Regenerate.
112 * i386-tbl.h: Ditto.
113
920d2ddc
IT		 1142016-11-02 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
115
116 * i386-dis.c. (enum): Add PREFIX_EVEX_0F389A,
117 PREFIX_EVEX_0F389B, PREFIX_EVEX_0F38AA, PREFIX_EVEX_0F38AB.
118 * i386-dis-evex.h (evex_table): Updated.
119 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_4FMAPS_FLAGS,
120 CPU_ANY_AVX512_4FMAPS_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
121 (cpu_flags): Add CpuAVX512_4FMAPS.
122 (opcode_modifiers): Add ImplicitQuadGroup modifier.
123 * i386-opc.h (AVX512_4FMAP): New.
124 (i386_cpu_flags): Add cpuavx512_4fmaps.
125 (ImplicitQuadGroup): New.
126 (i386_opcode_modifier): Add implicitquadgroup.
127 * i386-opc.tbl: Add Intel AVX512_4FMAPS instructions.
128 * i386-init.h: Regenerate.
129 * i386-tbl.h: Ditto.
130
e23eba97
NC		 1312016-11-01 Palmer Dabbelt <palmer@dabbelt.com>
132 Andrew Waterman <andrew@sifive.com>
133
134 Add support for RISC-V architecture.
135 * configure.ac: Add entry for bfd_riscv_arch.
136 * configure: Regenerate.
137 * disassemble.c (disassembler): Add support for riscv.
138 (disassembler_usage): Likewise.
139 * riscv-dis.c: New file.
140 * riscv-opc.c: New file.
141
b5cefcca
L		 1422016-10-21 H.J. Lu <hongjiu.lu@intel.com>
143
144 * i386-dis.c (PREFIX_RM_0_0FAE_REG_7): Removed.
145 (prefix_table): Remove the PREFIX_RM_0_0FAE_REG_7 entry.
146 (rm_table): Update the RM_0FAE_REG_7 entry.
147 * i386-gen.c (cpu_flag_init): Remove CPU_PCOMMIT_FLAGS.
148 (cpu_flags): Remove CpuPCOMMIT.
149 * i386-opc.h (CpuPCOMMIT): Removed.
150 (i386_cpu_flags): Remove cpupcommit.
151 * i386-opc.tbl: Remove pcommit.
152 * i386-init.h: Regenerated.
153 * i386-tbl.h: Likewise.
154
9889cbb1
L		 1552016-10-20 H.J. Lu <hongjiu.lu@intel.com>
156
157 PR binutis/20705
158 * i386-dis.c (get_valid_dis386): Ignore the REX_B bit and
159 the highest bit in VEX.vvvv for the 3-byte VEX prefix in
160 32-bit mode. Don't check vex.register_specifier in 32-bit
161 mode.
162 (OP_VEX): Check for invalid mask registers.
163
28596323
L		 1642016-10-18 H.J. Lu <hongjiu.lu@intel.com>
165
166 PR binutis/20699
167 * i386-dis.c (OP_E_memory): Check addr32flag in stead of
168 sizeflag.
169
da8d7d66
L		 1702016-10-18 H.J. Lu <hongjiu.lu@intel.com>
171
172 PR binutis/20704
173 * i386-dis.c (three_byte_table): Remove the remaining SSE5 support.
174
eaf02703
MR		 1752016-10-18 Maciej W. Rozycki <macro@imgtec.com>
176
177 * aarch64-dis.c (aarch64_ext_sve_addr_rr_lsl): Rename `index'
178 local variable to `index_regno'.
179
decf5bd1
CM		 1802016-10-17 Cupertino Miranda <cmiranda@synopsys.com>
181
182 * arc-tbl.h: Removed any "inv.+" instructions from the table.
183
e5b06ef0
CZ		 1842016-10-14 Claudiu Zissulescu <claziss@synopsys.com>
185
186 * arc-dis.c (find_format_from_table): Discriminate LIMM indicator
187 usage on ISA basis.
188
93562a34
JW		 1892016-10-11 Jiong Wang <jiong.wang@arm.com>
190
191 PR target/20666
192 * aarch64-asm.c (convert_bfc_to_bfm): Fix dest index.
193
362c0c4d
JW		 1942016-10-07 Jiong Wang <jiong.wang@arm.com>
195
196 PR target/20667
197 * aarch64-opc.c (aarch64_print_operand): Always print operand if it's
198 available.
199
1047201f
AM		 2002016-10-07 Alan Modra <amodra@gmail.com>
201
202 * sh-opc.h (sh_merge_bfd_arch): Delete prototype.
203
1a0670f3
AM		 2042016-10-06 Alan Modra <amodra@gmail.com>
205
206 * aarch64-opc.c: Spell fall through comments consistently.
207 * i386-dis.c: Likewise.
208 * aarch64-dis.c: Add missing fall through comments.
209 * aarch64-opc.c: Likewise.
210 * arc-dis.c: Likewise.
211 * arm-dis.c: Likewise.
212 * i386-dis.c: Likewise.
213 * m68k-dis.c: Likewise.
214 * mep-asm.c: Likewise.
215 * ns32k-dis.c: Likewise.
216 * sh-dis.c: Likewise.
217 * tic4x-dis.c: Likewise.
218 * tic6x-dis.c: Likewise.
219 * vax-dis.c: Likewise.
220
2b804145
AM		 2212016-10-06 Alan Modra <amodra@gmail.com>
222
223 * arc-ext.c (create_map): Add missing break.
224 * msp430-decode.opc (encode_as): Likewise.
225 * msp430-decode.c: Regenerate.
226
616ec358
AM		 2272016-10-06 Alan Modra <amodra@gmail.com>
228
229 * cr16-dis.c (print_insn_cr16): Don't use boolean OR in arithmetic.
230 * crx-dis.c (print_insn_crx): Likewise.
231
72da393d
L		 2322016-09-30 H.J. Lu <hongjiu.lu@intel.com>
233
234 PR binutils/20657
235 * i386-dis.c (putop): Don't assign alt twice.
236
744ce302
JW		 2372016-09-29 Jiong Wang <jiong.wang@arm.com>
238
239 PR target/20553
240 * aarch64-tbl.h (fmla, fmls, fmul, fmulx): Fix opcode mask field.
241
a5721ba2
AM		 2422016-09-29 Alan Modra <amodra@gmail.com>
243
244 * ppc-opc.c (L): Make compulsory.
245 (LOPT): New, optional form of L.
246 (HTM_R): Define as LOPT.
247 (L0, L1): Delete.
248 (L32OPT): New, optional for 32-bit L.
249 (L2OPT): New, 2-bit L for dcbf.
250 (SVC_LEC): Update.
251 (L2): Define.
252 (insert_l0, extract_l0, insert_l1, extract_l2): Delete.
253 (powerpc_opcodes <cmpli, cmpi, cmpl, cmp>): Use L32OPT.
254 <dcbf>: Use L2OPT.
255 <tlbiel, tlbie>: Use LOPT.
256 <wclr, wclrall>: Use L2.
257
c5da1932
VZ		 2582016-09-26 Vlad Zakharov <vzakhar@synopsys.com>
259
260 * Makefile.in: Regenerate.
261 * configure: Likewise.
262
2b848ebd
CZ		 2632016-09-26 Claudiu Zissulescu <claziss@synopsys.com>
264
265 * arc-ext-tbl.h (EXTINSN2OPF): Define.
266 (EXTINSN2OP): Use EXTINSN2OPF.
267 (bspeekm, bspop, modapp): New extension instructions.
268 * arc-opc.c (F_DNZ_ND): Define.
269 (F_DNZ_D): Likewise.
270 (F_SIZEB1): Changed.
271 (C_DNZ_D): Define.
272 (C_HARD): Changed.
273 * arc-tbl.h (dbnz): New instruction.
274 (prealloc): Allow it for ARC EM.
275 (xbfu): Likewise.
276
ad43e107
RS		 2772016-09-21 Richard Sandiford <richard.sandiford@arm.com>
278
279 * aarch64-opc.c (print_immediate_offset_address): Print spaces
280 after commas in addresses.
281 (aarch64_print_operand): Likewise.
282
ab3b8fcf
RS		 2832016-09-21 Richard Sandiford <richard.sandiford@arm.com>
284
285 * aarch64-opc.c (operand_general_constraint_met_p): Use "must be"
286 rather than "should be" or "expected to be" in error messages.
287
bb7eff52
RS		 2882016-09-21 Richard Sandiford <richard.sandiford@arm.com>
289
290 * aarch64-dis.c (remove_dot_suffix): New function, split out from...
291 (print_mnemonic_name): ...here.
292 (print_comment): New function.
293 (print_aarch64_insn): Call it.
294 * aarch64-opc.c (aarch64_conds): Add SVE names.
295 (aarch64_print_operand): Print alternative condition names in
296 a comment.
297
c0890d26
RS		 2982016-09-21 Richard Sandiford <richard.sandiford@arm.com>
299
300 * aarch64-tbl.h (OP_SVE_B, OP_SVE_BB, OP_SVE_BBBU, OP_SVE_BMB)
301 (OP_SVE_BPB, OP_SVE_BUB, OP_SVE_BUBB, OP_SVE_BUU, OP_SVE_BZ)
302 (OP_SVE_BZB, OP_SVE_BZBB, OP_SVE_BZU, OP_SVE_DD, OP_SVE_DDD)
303 (OP_SVE_DMD, OP_SVE_DMH, OP_SVE_DMS, OP_SVE_DU, OP_SVE_DUD, OP_SVE_DUU)
304 (OP_SVE_DUV_BHS, OP_SVE_DUV_BHSD, OP_SVE_DZD, OP_SVE_DZU, OP_SVE_HB)
305 (OP_SVE_HMD, OP_SVE_HMS, OP_SVE_HU, OP_SVE_HUU, OP_SVE_HZU, OP_SVE_RR)
306 (OP_SVE_RURV_BHSD, OP_SVE_RUV_BHSD, OP_SVE_SMD, OP_SVE_SMH, OP_SVE_SMS)
307 (OP_SVE_SU, OP_SVE_SUS, OP_SVE_SUU, OP_SVE_SZS, OP_SVE_SZU, OP_SVE_UB)
308 (OP_SVE_UUD, OP_SVE_UUS, OP_SVE_VMR_BHSD, OP_SVE_VMU_SD)
309 (OP_SVE_VMVD_BHS, OP_SVE_VMVU_BHSD, OP_SVE_VMVU_SD, OP_SVE_VMVV_BHSD)
310 (OP_SVE_VMVV_SD, OP_SVE_VMV_BHSD, OP_SVE_VMV_HSD, OP_SVE_VMV_SD)
311 (OP_SVE_VM_SD, OP_SVE_VPU_BHSD, OP_SVE_VPV_BHSD, OP_SVE_VRR_BHSD)
312 (OP_SVE_VRU_BHSD, OP_SVE_VR_BHSD, OP_SVE_VUR_BHSD, OP_SVE_VUU_BHSD)
313 (OP_SVE_VUVV_BHSD, OP_SVE_VUVV_SD, OP_SVE_VUV_BHSD, OP_SVE_VUV_SD)
314 (OP_SVE_VU_BHSD, OP_SVE_VU_HSD, OP_SVE_VU_SD, OP_SVE_VVD_BHS)
315 (OP_SVE_VVU_BHSD, OP_SVE_VVVU_SD, OP_SVE_VVV_BHSD, OP_SVE_VVV_SD)
316 (OP_SVE_VV_BHSD, OP_SVE_VV_HSD_BHS, OP_SVE_VV_SD, OP_SVE_VWW_BHSD)
317 (OP_SVE_VXX_BHSD, OP_SVE_VZVD_BHS, OP_SVE_VZVU_BHSD, OP_SVE_VZVV_BHSD)
318 (OP_SVE_VZVV_SD, OP_SVE_VZV_SD, OP_SVE_V_SD, OP_SVE_WU, OP_SVE_WV_BHSD)
319 (OP_SVE_XU, OP_SVE_XUV_BHSD, OP_SVE_XVW_BHSD, OP_SVE_XV_BHSD)
320 (OP_SVE_XWU, OP_SVE_XXU): New macros.
321 (aarch64_feature_sve): New variable.
322 (SVE): New macro.
323 (_SVE_INSN): Likewise.
324 (aarch64_opcode_table): Add SVE instructions.
325 * aarch64-opc.h (extract_fields): Declare.
326 * aarch64-opc-2.c: Regenerate.
327 * aarch64-asm.c (do_misc_encoding): Handle the new SVE aarch64_ops.
328 * aarch64-asm-2.c: Regenerate.
329 * aarch64-dis.c (extract_fields): Make global.
330 (do_misc_decoding): Handle the new SVE aarch64_ops.
331 * aarch64-dis-2.c: Regenerate.
332
116b6019
RS		 3332016-09-21 Richard Sandiford <richard.sandiford@arm.com>
334
335 * aarch64-opc.h (FLD_SVE_M_4, FLD_SVE_M_14, FLD_SVE_M_16)
336 (FLD_SVE_sz, FLD_SVE_tsz, FLD_SVE_tszl_8, FLD_SVE_tszl_19): New
337 aarch64_field_kinds.
338 * aarch64-opc.c (fields): Add corresponding entries.
339 * aarch64-asm.c (aarch64_get_variant): New function.
340 (aarch64_encode_variant_using_iclass): Likewise.
341 (aarch64_opcode_encode): Call it.
342 * aarch64-dis.c (aarch64_decode_variant_using_iclass): New function.
343 (aarch64_opcode_decode): Call it.
344
047cd301
RS		 3452016-09-21 Richard Sandiford <richard.sandiford@arm.com>
346
347 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE core
348 and FP register operands.
349 * aarch64-opc.h (FLD_SVE_Rm, FLD_SVE_Rn, FLD_SVE_Vd, FLD_SVE_Vm)
350 (FLD_SVE_Vn): New aarch64_field_kinds.
351 * aarch64-opc.c (fields): Add corresponding entries.
352 (aarch64_print_operand): Handle the new SVE core and FP register
353 operands.
354 * aarch64-opc-2.c: Regenerate.
355 * aarch64-asm-2.c: Likewise.
356 * aarch64-dis-2.c: Likewise.
357
165d4950
RS		 3582016-09-21 Richard Sandiford <richard.sandiford@arm.com>
359
360 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE FP
361 immediate operands.
362 * aarch64-opc.h (FLD_SVE_i1): New aarch64_field_kind.
363 * aarch64-opc.c (fields): Add corresponding entry.
364 (operand_general_constraint_met_p): Handle the new SVE FP immediate
365 operands.
366 (aarch64_print_operand): Likewise.
367 * aarch64-opc-2.c: Regenerate.
368 * aarch64-asm.h (ins_sve_float_half_one, ins_sve_float_half_two)
369 (ins_sve_float_zero_one): New inserters.
370 * aarch64-asm.c (aarch64_ins_sve_float_half_one): New function.
371 (aarch64_ins_sve_float_half_two): Likewise.
372 (aarch64_ins_sve_float_zero_one): Likewise.
373 * aarch64-asm-2.c: Regenerate.
374 * aarch64-dis.h (ext_sve_float_half_one, ext_sve_float_half_two)
375 (ext_sve_float_zero_one): New extractors.
376 * aarch64-dis.c (aarch64_ext_sve_float_half_one): New function.
377 (aarch64_ext_sve_float_half_two): Likewise.
378 (aarch64_ext_sve_float_zero_one): Likewise.
379 * aarch64-dis-2.c: Regenerate.
380
e950b345
RS		 3812016-09-21 Richard Sandiford <richard.sandiford@arm.com>
382
383 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
384 integer immediate operands.
385 * aarch64-opc.h (FLD_SVE_immN, FLD_SVE_imm3, FLD_SVE_imm5)
386 (FLD_SVE_imm5b, FLD_SVE_imm7, FLD_SVE_imm8, FLD_SVE_imm9)
387 (FLD_SVE_immr, FLD_SVE_imms, FLD_SVE_tszh): New aarch64_field_kinds.
388 * aarch64-opc.c (fields): Add corresponding entries.
389 (operand_general_constraint_met_p): Handle the new SVE integer
390 immediate operands.
391 (aarch64_print_operand): Likewise.
392 (aarch64_sve_dupm_mov_immediate_p): New function.
393 * aarch64-opc-2.c: Regenerate.
394 * aarch64-asm.h (ins_inv_limm, ins_sve_aimm, ins_sve_asimm)
395 (ins_sve_limm_mov, ins_sve_shlimm, ins_sve_shrimm): New inserters.
396 * aarch64-asm.c (aarch64_ins_limm_1): New function, split out from...
397 (aarch64_ins_limm): ...here.
398 (aarch64_ins_inv_limm): New function.
399 (aarch64_ins_sve_aimm): Likewise.
400 (aarch64_ins_sve_asimm): Likewise.
401 (aarch64_ins_sve_limm_mov): Likewise.
402 (aarch64_ins_sve_shlimm): Likewise.
403 (aarch64_ins_sve_shrimm): Likewise.
404 * aarch64-asm-2.c: Regenerate.
405 * aarch64-dis.h (ext_inv_limm, ext_sve_aimm, ext_sve_asimm)
406 (ext_sve_limm_mov, ext_sve_shlimm, ext_sve_shrimm): New extractors.
407 * aarch64-dis.c (decode_limm): New function, split out from...
408 (aarch64_ext_limm): ...here.
409 (aarch64_ext_inv_limm): New function.
410 (decode_sve_aimm): Likewise.
411 (aarch64_ext_sve_aimm): Likewise.
412 (aarch64_ext_sve_asimm): Likewise.
413 (aarch64_ext_sve_limm_mov): Likewise.
414 (aarch64_top_bit): Likewise.
415 (aarch64_ext_sve_shlimm): Likewise.
416 (aarch64_ext_sve_shrimm): Likewise.
417 * aarch64-dis-2.c: Regenerate.
418
98907a70
RS		 4192016-09-21 Richard Sandiford <richard.sandiford@arm.com>
420
421 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new MUL VL
422 operands.
423 * aarch64-opc.c (aarch64_operand_modifiers): Initialize
424 the AARCH64_MOD_MUL_VL entry.
425 (value_aligned_p): Cope with non-power-of-two alignments.
426 (operand_general_constraint_met_p): Handle the new MUL VL addresses.
427 (print_immediate_offset_address): Likewise.
428 (aarch64_print_operand): Likewise.
429 * aarch64-opc-2.c: Regenerate.
430 * aarch64-asm.h (ins_sve_addr_ri_s4xvl, ins_sve_addr_ri_s6xvl)
431 (ins_sve_addr_ri_s9xvl): New inserters.
432 * aarch64-asm.c (aarch64_ins_sve_addr_ri_s4xvl): New function.
433 (aarch64_ins_sve_addr_ri_s6xvl): Likewise.
434 (aarch64_ins_sve_addr_ri_s9xvl): Likewise.
435 * aarch64-asm-2.c: Regenerate.
436 * aarch64-dis.h (ext_sve_addr_ri_s4xvl, ext_sve_addr_ri_s6xvl)
437 (ext_sve_addr_ri_s9xvl): New extractors.
438 * aarch64-dis.c (aarch64_ext_sve_addr_reg_mul_vl): New function.
439 (aarch64_ext_sve_addr_ri_s4xvl): Likewise.
440 (aarch64_ext_sve_addr_ri_s6xvl): Likewise.
441 (aarch64_ext_sve_addr_ri_s9xvl): Likewise.
442 * aarch64-dis-2.c: Regenerate.
443
4df068de
RS		 4442016-09-21 Richard Sandiford <richard.sandiford@arm.com>
445
446 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for the new SVE
447 address operands.
448 * aarch64-opc.h (FLD_SVE_imm6, FLD_SVE_msz, FLD_SVE_xs_14)
449 (FLD_SVE_xs_22): New aarch64_field_kinds.
450 (OPD_F_OD_MASK, OPD_F_OD_LSB, OPD_F_NO_ZR): New flags.
451 (get_operand_specific_data): New function.
452 * aarch64-opc.c (fields): Add entries for FLD_SVE_imm6, FLD_SVE_msz,
453 FLD_SVE_xs_14 and FLD_SVE_xs_22.
454 (operand_general_constraint_met_p): Handle the new SVE address
455 operands.
456 (sve_reg): New array.
457 (get_addr_sve_reg_name): New function.
458 (aarch64_print_operand): Handle the new SVE address operands.
459 * aarch64-opc-2.c: Regenerate.
460 * aarch64-asm.h (ins_sve_addr_ri_u6, ins_sve_addr_rr_lsl)
461 (ins_sve_addr_rz_xtw, ins_sve_addr_zi_u5, ins_sve_addr_zz_lsl)
462 (ins_sve_addr_zz_sxtw, ins_sve_addr_zz_uxtw): New inserters.
463 * aarch64-asm.c (aarch64_ins_sve_addr_ri_u6): New function.
464 (aarch64_ins_sve_addr_rr_lsl): Likewise.
465 (aarch64_ins_sve_addr_rz_xtw): Likewise.
466 (aarch64_ins_sve_addr_zi_u5): Likewise.
467 (aarch64_ins_sve_addr_zz): Likewise.
468 (aarch64_ins_sve_addr_zz_lsl): Likewise.
469 (aarch64_ins_sve_addr_zz_sxtw): Likewise.
470 (aarch64_ins_sve_addr_zz_uxtw): Likewise.
471 * aarch64-asm-2.c: Regenerate.
472 * aarch64-dis.h (ext_sve_addr_ri_u6, ext_sve_addr_rr_lsl)
473 (ext_sve_addr_rz_xtw, ext_sve_addr_zi_u5, ext_sve_addr_zz_lsl)
474 (ext_sve_addr_zz_sxtw, ext_sve_addr_zz_uxtw): New extractors.
475 * aarch64-dis.c (aarch64_ext_sve_add_reg_imm): New function.
476 (aarch64_ext_sve_addr_ri_u6): Likewise.
477 (aarch64_ext_sve_addr_rr_lsl): Likewise.
478 (aarch64_ext_sve_addr_rz_xtw): Likewise.
479 (aarch64_ext_sve_addr_zi_u5): Likewise.
480 (aarch64_ext_sve_addr_zz): Likewise.
481 (aarch64_ext_sve_addr_zz_lsl): Likewise.
482 (aarch64_ext_sve_addr_zz_sxtw): Likewise.
483 (aarch64_ext_sve_addr_zz_uxtw): Likewise.
484 * aarch64-dis-2.c: Regenerate.
485
2442d846
RS		 4862016-09-21 Richard Sandiford <richard.sandiford@arm.com>
487
488 * aarch64-tbl.h (AARCH64_OPERANDS): Add an entry for
489 AARCH64_OPND_SVE_PATTERN_SCALED.
490 * aarch64-opc.h (FLD_SVE_imm4): New aarch64_field_kind.
491 * aarch64-opc.c (fields): Add a corresponding entry.
492 (set_multiplier_out_of_range_error): New function.
493 (aarch64_operand_modifiers): Add entry for AARCH64_MOD_MUL.
494 (operand_general_constraint_met_p): Handle
495 AARCH64_OPND_SVE_PATTERN_SCALED.
496 (print_register_offset_address): Use PRIi64 to print the
497 shift amount.
498 (aarch64_print_operand): Likewise. Handle
499 AARCH64_OPND_SVE_PATTERN_SCALED.
500 * aarch64-opc-2.c: Regenerate.
501 * aarch64-asm.h (ins_sve_scale): New inserter.
502 * aarch64-asm.c (aarch64_ins_sve_scale): New function.
503 * aarch64-asm-2.c: Regenerate.
504 * aarch64-dis.h (ext_sve_scale): New inserter.
505 * aarch64-dis.c (aarch64_ext_sve_scale): New function.
506 * aarch64-dis-2.c: Regenerate.
507
245d2e3f
RS		 5082016-09-21 Richard Sandiford <richard.sandiford@arm.com>
509
510 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for
511 AARCH64_OPND_SVE_PATTERN and AARCH64_OPND_SVE_PRFOP.
512 * aarch64-opc.h (FLD_SVE_pattern): New aarch64_field_kind.
513 (FLD_SVE_prfop): Likewise.
514 * aarch64-opc.c: Include libiberty.h.
515 (aarch64_sve_pattern_array): New variable.
516 (aarch64_sve_prfop_array): Likewise.
517 (fields): Add entries for FLD_SVE_pattern and FLD_SVE_prfop.
518 (aarch64_print_operand): Handle AARCH64_OPND_SVE_PATTERN and
519 AARCH64_OPND_SVE_PRFOP.
520 * aarch64-asm-2.c: Regenerate.
521 * aarch64-dis-2.c: Likewise.
522 * aarch64-opc-2.c: Likewise.
523
d50c751e
RS		 5242016-09-21 Richard Sandiford <richard.sandiford@arm.com>
525
526 * aarch64-opc.c (aarch64_opnd_qualifiers): Add entries for
527 AARCH64_OPND_QLF_P_[ZM].
528 (aarch64_print_operand): Print /z and /m where appropriate.
529
f11ad6bc
RS		 5302016-09-21 Richard Sandiford <richard.sandiford@arm.com>
531
532 * aarch64-tbl.h (AARCH64_OPERANDS): Add entries for new SVE operands.
533 * aarch64-opc.h (FLD_SVE_Pd, FLD_SVE_Pg3, FLD_SVE_Pg4_5)
534 (FLD_SVE_Pg4_10, FLD_SVE_Pg4_16, FLD_SVE_Pm, FLD_SVE_Pn, FLD_SVE_Pt)
535 (FLD_SVE_Za_5, FLD_SVE_Za_16, FLD_SVE_Zd, FLD_SVE_Zm_5, FLD_SVE_Zm_16)
536 (FLD_SVE_Zn, FLD_SVE_Zt, FLD_SVE_tzsh): New aarch64_field_kinds.
537 * aarch64-opc.c (fields): Add corresponding entries here.
538 (operand_general_constraint_met_p): Check that SVE register lists
539 have the correct length. Check the ranges of SVE index registers.
540 Check for cases where p8-p15 are used in 3-bit predicate fields.
541 (aarch64_print_operand): Handle the new SVE operands.
542 * aarch64-opc-2.c: Regenerate.
543 * aarch64-asm.h (ins_sve_index, ins_sve_reglist): New inserters.
544 * aarch64-asm.c (aarch64_ins_sve_index): New function.
545 (aarch64_ins_sve_reglist): Likewise.
546 * aarch64-asm-2.c: Regenerate.
547 * aarch64-dis.h (ext_sve_index, ext_sve_reglist): New extractors.
548 * aarch64-dis.c (aarch64_ext_sve_index): New function.
549 (aarch64_ext_sve_reglist): Likewise.
550 * aarch64-dis-2.c: Regenerate.
551
0c608d6b
RS		 5522016-09-21 Richard Sandiford <richard.sandiford@arm.com>
553
554 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN, CRYP_INSN)
555 (_CRC_INSN, _LSE_INSN, _LOR_INSN, RDMA_INSN, FP16_INSN, SF16_INSN)
556 (V8_2_INSN, aarch64_opcode_table): Initialize tied_operand field.
557 * aarch64-opc.c (aarch64_match_operands_constraint): Check for
558 tied operands.
559
01dbfe4c
RS		 5602016-09-21 Richard Sandiford <richard.sandiford@arm.com>
561
562 * aarch64-opc.c (get_offset_int_reg_name): New function.
563 (print_immediate_offset_address): Likewise.
564 (print_register_offset_address): Take the base and offset
565 registers as parameters.
566 (aarch64_print_operand): Update caller accordingly. Use
567 print_immediate_offset_address.
568
72e9f319
RS		 5692016-09-21 Richard Sandiford <richard.sandiford@arm.com>
570
571 * aarch64-opc.c (BANK): New macro.
572 (R32, R64): Take a register number as argument
573 (int_reg): Use BANK.
574
8a7f0c1b
RS		 5752016-09-21 Richard Sandiford <richard.sandiford@arm.com>
576
577 * aarch64-opc.c (print_register_list): Add a prefix parameter.
578 (aarch64_print_operand): Update accordingly.
579
aa2aa4c6
RS		 5802016-09-21 Richard Sandiford <richard.sandiford@arm.com>
581
582 * aarch64-tbl.h (AARCH64_OPERNADS): Use fpimm rather than imm
583 for FPIMM.
584 * aarch64-asm.h (ins_fpimm): New inserter.
585 * aarch64-asm.c (aarch64_ins_fpimm): New function.
586 * aarch64-asm-2.c: Regenerate.
587 * aarch64-dis.h (ext_fpimm): New extractor.
588 * aarch64-dis.c (aarch64_ext_imm): Remove fpimm test.
589 (aarch64_ext_fpimm): New function.
590 * aarch64-dis-2.c: Regenerate.
591
b5464a68
RS		 5922016-09-21 Richard Sandiford <richard.sandiford@arm.com>
593
594 * aarch64-asm.c: Include libiberty.h.
595 (insert_fields): New function.
596 (aarch64_ins_imm): Use it.
597 * aarch64-dis.c (extract_fields): New function.
598 (aarch64_ext_imm): Use it.
599
42408347
RS		 6002016-09-21 Richard Sandiford <richard.sandiford@arm.com>
601
602 * aarch64-opc.c (aarch64_logical_immediate_p): Replace is32
603 with an esize parameter.
604 (operand_general_constraint_met_p): Update accordingly.
605 Fix misindented code.
606 * aarch64-asm.c (aarch64_ins_limm): Update call to
607 aarch64_logical_immediate_p.
608
4989adac
RS		 6092016-09-21 Richard Sandiford <richard.sandiford@arm.com>
610
611 * aarch64-opc.c (match_operands_qualifier): Handle F_STRICT.
612
bd11d5d8
RS		 6132016-09-21 Richard Sandiford <richard.sandiford@arm.com>
614
615 * aarch64-gen.c (indented_print): Avoid hard-coded indentation limit.
616
f807f43d
CZ		 6172016-09-15 Claudiu Zissulescu <claziss@synopsys.com>
618
619 * arc-dis.c (find_format): Walk the linked list pointed by einsn.
620
fd486b63
PB		 6212016-09-14 Peter Bergner <bergner@vnet.ibm.com>
622
623 * ppc-opc.c (powerpc_opcodes) <slbiag>: New mnemonic.
624 <addex., brd, brh, brw, lwzmx, nandxor, rldixor, setbool,
625 xor3>: Delete mnemonics.
626 <cp_abort>: Rename mnemonic from ...
627 <cpabort>: ...to this.
628 <setb>: Change to a X form instruction.
629 <sync>: Change to 1 operand form.
630 <copy>: Delete mnemonic.
631 <copy_first>: Rename mnemonic from ...
632 <copy>: ...to this.
633 <paste, paste.>: Delete mnemonics.
634 <paste_last>: Rename mnemonic from ...
635 <paste.>: ...to this.
636
dce08442
AK		 6372016-09-14 Anton Kolesov <Anton.Kolesov@synopsys.com>
638
639 * arc-dis.c (arc_get_disassembler): Accept a null bfd gracefully.
640
952c3f51
AK		 6412016-09-12 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
642
643 * s390-mkopc.c (main): Support alternate arch strings.
644
8b71537b
PS		 6452016-09-12 Patrick Steuer <steuer@linux.vnet.ibm.com>
646
647 * s390-opc.txt: Fix kmctr instruction type.
648
5b64d091
L		 6492016-09-07 H.J. Lu <hongjiu.lu@intel.com>
650
651 * i386-gen.c (cpu_flag_init): Remove CPU_IAMCU_COMPAT_FLAGS.
652 * i386-init.h: Regenerated.
653
7763838e
CM		 6542016-08-30 Cupertino Miranda <cmiranda@synopsys.com>
655
656 * opcodes/arc-dis.c (print_insn_arc): Changed.
657
1b8b6532
JM		 6582016-08-26 Jose E. Marchesi <jose.marchesi@oracle.com>
659
660 * sparc-opc.c (sparc_opcodes): Fix typo in opcode, camellia_fi ->
661 camellia_fl.
662
1a336194
TP		 6632016-08-26 Thomas Preud'homme <thomas.preudhomme@arm.com>
664
665 * arm-dis.c (psr_name): Use hex as case labels. Add detection for
666 MSPLIM, PSPLIM, MSPLIM_NS, PSPLIM_NS, PRIMASK_NS, BASEPRI_NS,
667 FAULTMASK_NS, CONTROL_NS and SP_NS special registers.
668
6b40c462
L		 6692016-08-24 H.J. Lu <hongjiu.lu@intel.com>
670
671 * i386-dis.c (PREFIX_MOD_0_0FAE_REG_4): New.
672 (PREFIX_MOD_3_0FAE_REG_4): Likewise.
673 (prefix_table): Add PREFIX_MOD_0_0FAE_REG_4 and
674 PREFIX_MOD_3_0FAE_REG_4.
675 (mod_table): Use PREFIX_MOD_0_0FAE_REG_4 and
676 PREFIX_MOD_3_0FAE_REG_4.
677 * i386-gen.c (cpu_flag_init): Add CPU_PTWRITE_FLAGS.
678 (cpu_flags): Add CpuPTWRITE.
679 * i386-opc.h (CpuPTWRITE): New.
680 (i386_cpu_flags): Add cpuptwrite.
681 * i386-opc.tbl: Add ptwrite instruction.
682 * i386-init.h: Regenerated.
683 * i386-tbl.h: Likewise.
684
ab548d2d
AK		 6852016-08-24 Anton Kolesov <Anton.Kolesov@synopsys.com>
686
687 * arc-dis.h: Wrap around in extern "C".
688
344bde0a
RS		 6892016-08-23 Richard Sandiford <richard.sandiford@arm.com>
690
691 * aarch64-tbl.h (V8_2_INSN): New macro.
692 (aarch64_opcode_table): Use it.
693
5ce912d8
RS		 6942016-08-23 Richard Sandiford <richard.sandiford@arm.com>
695
696 * aarch64-tbl.h (aarch64_opcode_table): Make more use of
697 CORE_INSN, __FP_INSN and SIMD_INSN.
698
9d30b0bd
RS		 6992016-08-23 Richard Sandiford <richard.sandiford@arm.com>
700
701 * aarch64-tbl.h (CORE_INSN, __FP_INSN, SIMD_INSN): Add OP parameter.
702 (aarch64_opcode_table): Update uses accordingly.
703
dfdaec14
AJ		 7042016-07-25 Andrew Jenner <andrew@codesourcery.com>
705 Kwok Cheung Yeung <kcy@codesourcery.com>
706
707 opcodes/
708 * ppc-opc.c (vle_opcodes): Alias 'e_cmpwi' to 'e_cmpi' and
709 'e_cmplwi' to 'e_cmpli' instead.
710 (OPVUPRT, OPVUPRT_MASK): Define.
711 (powerpc_opcodes): Add E200Z4 insns.
712 (vle_opcodes): Add context save/restore insns.
713
7bd374a4
MR		 7142016-07-27 Maciej W. Rozycki <macro@imgtec.com>
715
716 * micromips-opc.c (micromips_opcodes): Reorder "bc" next to "b",
717 "beqzc" next to "beq", "bnezc" next to "bne" and "jrc" next to
718 "j".
719
db18dbab
GM		 7202016-07-27 Graham Markall <graham.markall@embecosm.com>
721
722 * arc-nps400-tbl.h: Change block comments to GNU format.
723 * arc-dis.c: Add new globals addrtypenames,
724 addrtypenames_max, and addtypeunknown.
725 (get_addrtype): New function.
726 (print_insn_arc): Print colons and address types when
727 required.
728 * arc-opc.c: Add MAKE_INSERT_NPS_ADDRTYPE macro and use to
729 define insert and extract functions for all address types.
730 (arc_operands): Add operands for colon and all address
731 types.
732 * arc-nps-400-tbl.h: Add NPS-400 BMU instructions to opcode table.
733 * arc-opc.c: Add NPS_BD_TYPE and NPS_BMU_NUM operands,
734 insert_nps_bd_num_buff and extract_nps_bd_num_buff functions.
735 * arc-nps-400-tbl.h: Add NPS-400 PMU instructions to opcode table.
736 * arc-opc.c: Add NPS_PMU_NXT_DST and NPS_PMU_NUM_JOB operands,
737 insert_nps_pmu_num_job and extract_nps_pmu_num_job functions.
738
fecd57f9
L		 7392016-07-21 H.J. Lu <hongjiu.lu@intel.com>
740
741 * configure: Regenerated.
742
37fd5ef3
CZ		 7432016-07-20 Claudiu Zissulescu <claziss@synopsys.com>
744
745 * arc-dis.c (skipclass): New structure.
746 (decodelist): New variable.
747 (is_compatible_p): New function.
748 (new_element): Likewise.
749 (skip_class_p): Likewise.
750 (find_format_from_table): Use skip_class_p function.
751 (find_format): Decode first the extension instructions.
752 (print_insn_arc): Select either ARCEM or ARCHS based on elf
753 e_flags.
754 (parse_option): New function.
755 (parse_disassembler_options): Likewise.
756 (print_arc_disassembler_options): Likewise.
757 (print_insn_arc): Use parse_disassembler_options function. Proper
758 select ARCv2 cpu variant.
759 * disassemble.c (disassembler_usage): Add ARC disassembler
760 options.
761
92281a5b
MR		 7622016-07-13 Maciej W. Rozycki <macro@imgtec.com>
763
764 * mips-opc.c (mips_builtin_opcodes): Remove the INSN2_ALIAS
765 annotation from the "nal" entry and reorder it beyond "bltzal".
766
6e7ced37
JM		 7672016-07-12 Jose E. Marchesi <jose.marchesi@oracle.com>
768
769 * sparc-opc.c (ldtxa): New macro.
770 (sparc_opcodes): Use the macro defined above to add entries for
771 the LDTXA instructions.
772 (asi_table): Add the ASI_TWINX_* asis used in the LDTXA
773 instruction.
774
2f831b9a 7752016-07-07 James Bowman <james.bowman@ftdichip.com>
776
777 * ft32-opc.c (ft32_opc_info): Correct mask for "callc"
778 and "jmpc".
779
c07315e0
JB		 7802016-07-01 Jan Beulich <jbeulich@suse.com>
781
782 * i386-opc.tbl (movzbl, movzbw, movzbq, movzwl, movzwq): Remove.
783 (movzb): Adjust to cover all permitted suffixes.
784 (movzw): New.
785 * i386-tbl.h: Re-generate.
786
9243100a
JB		 7872016-07-01 Jan Beulich <jbeulich@suse.com>
788
789 * i386-opc.tbl (jmp): Remove Disp32S from non-64-bit variant.
790 (lgdt): Remove Tbyte from non-64-bit variant.
791 (fxsave64, fxrstor64, xsave64, xrstor64, xsaveopt64, xrstors64,
792 xsaves64, xsavec64): Remove Disp16.
793 (cvtsi2ss, cvtsi2sd, invept, invvpid, invpcid, vcvtsi2sd):
794 Remove Disp32S from non-64-bit variants. Remove Disp16 from
795 64-bit variants.
796 (vcvtsi2ss, vcvtsd2si, vcvtsd2usi, vcvtsi2sd, vcvtusi2sd,
797 vcvtusi2ss, vcvtss2si, vcvtss2usi, vcvttsd2si, vcvttsd2usi,
798 vcvttss2si, vcvttss2usi, vmovd, vmovq): Remove Disp16 from
799 64-bit variants.
800 * i386-tbl.h: Re-generate.
801
8325cc63
JB		 8022016-07-01 Jan Beulich <jbeulich@suse.com>
803
804 * i386-opc.tbl (xlat): Remove RepPrefixOk.
805 * i386-tbl.h: Re-generate.
806
838441e4
YQ		 8072016-06-30 Yao Qi <yao.qi@linaro.org>
808
809 * arm-dis.c (print_insn): Fix typo in comment.
810
dab26bf4
RS		 8112016-06-28 Richard Sandiford <richard.sandiford@arm.com>
812
813 * aarch64-opc.c (operand_general_constraint_met_p): Check the
814 range of ldst_elemlist operands.
815 (print_register_list): Use PRIi64 to print the index.
816 (aarch64_print_operand): Likewise.
817
5703197e
TS		 8182016-06-25 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
819
820 * mcore-opc.h: Remove sentinal.
821 * mcore-dis.c (print_insn_mcore): Adjust.
822
ce440d63
GM		 8232016-06-23 Graham Markall <graham.markall@embecosm.com>
824
825 * arc-opc.c: Correct description of availability of NPS400
826 features.
827
6fd3a02d
PB		 8282016-06-22 Peter Bergner <bergner@vnet.ibm.com>
829
830 * ppc-opc.c (RM, DRM, VXASH, VXASH_MASK, XMMF, XMMF_MASK): New defines.
831 (powerpc_opcodes) <brd, brh, brw, mffsce, mffscdrn, mffscdrni,
832 mffscrn, mffscrni, mffsl, nandxor, rldixor, setbool,
833 xor3>: New mnemonics.
834 <setb>: Change to a VX form instruction.
835 (insert_sh6): Add support for rldixor.
836 (extract_sh6): Likewise.
837
6b477896
TS		 8382016-06-22 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
839
840 * arc-ext.h: Wrap in extern C.
841
bdd582db
GM		 8422016-06-21 Graham Markall <graham.markall@embecosm.com>
843
844 * arc-dis.c (arc_insn_length): Add comment on instruction length.
845 Use same method for determining instruction length on ARC700 and
846 NPS-400.
847 (arc_insn_length, print_insn_arc): Remove bfd_mach_arc_nps400.
848 * arc-nps400-tbl.h: Make all nps400 instructions ARC700 instructions
849 with the NPS400 subclass.
850 * arc-opc.c: Likewise.
851
96074adc
JM		 8522016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
853
854 * sparc-opc.c (rdasr): New macro.
855 (wrasr): Likewise.
856 (rdpr): Likewise.
857 (wrpr): Likewise.
858 (rdhpr): Likewise.
859 (wrhpr): Likewise.
860 (sparc_opcodes): Use the macros above to fix and expand the
861 definition of read/write instructions from/to
862 asr/privileged/hyperprivileged instructions.
863 * sparc-dis.c (v9_hpriv_reg_names): Add %hmcdper, %hmcddfr and
864 %hva_mask_nz. Prefer softint_set and softint_clear over
865 set_softint and clear_softint.
866 (print_insn_sparc): Support %ver in Rd.
867
7a10c22f
JM		 8682016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
869
870 * sparc-opc.c (sparc_opcodes): Adjust instructions opcode
871 architecture according to the hardware capabilities they require.
872
4f26fb3a
JM		 8732016-06-17 Jose E. Marchesi <jose.marchesi@oracle.com>
874
875 * sparc-dis.c (MASK_V9): Add SPARC_OPCODE_ARCH_V9{C,D,E,V,M}.
876 (compute_arch_mask): Handle bfd_mach_sparc_v8plus{c,d,e,v,m} and
877 bfd_mach_sparc_v9{c,d,e,v,m}.
878 * sparc-opc.c (MASK_V9C): Define.
879 (MASK_V9D): Likewise.
880 (MASK_V9E): Likewise.
881 (MASK_V9V): Likewise.
882 (MASK_V9M): Likewise.
883 (v6): Add MASK_V9{C,D,E,V,M}.
884 (v6notlet): Likewise.
885 (v7): Likewise.
886 (v8): Likewise.
887 (v9): Likewise.
888 (v9andleon): Likewise.
889 (v9a): Likewise.
890 (v9b): Likewise.
891 (v9c): Define.
892 (v9d): Likewise.
893 (v9e): Likewise.
894 (v9v): Likewise.
895 (v9m): Likewise.
896 (sparc_opcode_archs): Add entry for v9{c,d,e,v,m}.
897
3ee6e4fb
NC		 8982016-06-15 Nick Clifton <nickc@redhat.com>
899
900 * nds32-dis.c (nds32_parse_audio_ext): Change printing of integer
901 constants to match expected behaviour.
902 (nds32_parse_opcode): Likewise. Also for whitespace.
903
02f3be19
AB		 9042016-06-15 Andrew Burgess <andrew.burgess@embecosm.com>
905
906 * arc-opc.c (extract_rhv1): Extract value from insn.
907
6f9f37ed 9082016-06-14 Graham Markall <graham.markall@embecosm.com>
28215275
GM		 909
910 * arc-nps400-tbl.h: Add ldbit instruction.
911 * arc-opc.c: Add flag classes required for ldbit.
912
6f9f37ed 9132016-06-14 Graham Markall <graham.markall@embecosm.com>
9ba75c88
GM		 914
915 * arc-nps400-tbl.h: Add hash, hash.p[0-3], tr, utf8, e4by, and addf
916 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
917 support the above instructions.
918
6f9f37ed 9192016-06-14 Graham Markall <graham.markall@embecosm.com>
14053c19
GM		 920
921 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey, calcxkey, mxb,
922 imxb, addl, subl, andl, orl, xorl, andab, orab, lbdsize, bdlen, csms,
923 csma, cbba, zncv, and hofs.
924 * arc-opc.c: Add flag classes, insert/extract functions, and operands to
925 support the above instructions.
926
9272016-06-06 Graham Markall <graham.markall@embecosm.com>
928
929 * arc-nps400-tbl.h: Add andab and orab instructions.
930
9312016-06-06 Graham Markall <graham.markall@embecosm.com>
932
933 * arc-nps400-tbl.h: Add addl-like instructions.
934
9352016-06-06 Graham Markall <graham.markall@embecosm.com>
936
937 * arc-nps400-tbl.h: Add mxb and imxb instructions.
938
9392016-06-06 Graham Markall <graham.markall@embecosm.com>
940
941 * arc-nps400-tbl.h: Add calcbsd, calcbxd, calckey and calcxkey
942 instructions.
943
b2cc3f6f
AK		 9442016-06-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
945
946 * s390-dis.c (option_use_insn_len_bits_p): New file scope
947 variable.
948 (init_disasm): Handle new command line option "insnlength".
949 (print_s390_disassembler_options): Mention new option in help
950 output.
951 (print_insn_s390): Use the encoded insn length when dumping
952 unknown instructions.
953
1857fe72
DC		 9542016-06-03 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
955
956 * avr-dis.c (avr_operand): Add default data address space origin (0x800000)
957 to the address and set as symbol address for LDS/ STS immediate operands.
958
14b57c7c
AM		 9592016-06-07 Alan Modra <amodra@gmail.com>
960
961 * ppc-dis.c (ppc_opts): Delete extraneous parentheses. Default
962 cpu for "vle" to e500.
963 * ppc-opc.c (ALLOW8_SPRG): Remove PPC_OPCODE_VLE.
964 (NO371, PPCSPE, PPCISEL, PPCEFS, MULHW, DCBT_EO): Likewise.
965 (PPCNONE): Delete, substitute throughout.
966 (powerpc_opcodes): Remove PPCVLE from "flags". Add to "deprecated"
967 except for major opcode 4 and 31.
968 (vle_opcodes <se_rfmci>): Add PPCRFMCI to flags.
969
4d1464f2
MW		 9702016-06-07 Matthew Wahab <matthew.wahab@arm.com>
971
972 * arm-dis.c (arm_opcodes): Replace ARM_EXT_V8_2A with
973 ARM_EXT_RAS in relevant entries.
974
026122a6
PB		 9752016-06-03 Peter Bergner <bergner@vnet.ibm.com>
976
977 PR binutils/20196
978 * ppc-opc.c (powerpc_opcodes <lbarx, lharx, stbcx., sthcx.>): Enable
979 opcodes for E6500.
980
07f5af7d
L		 9812016-06-03 H.J. Lu <hongjiu.lu@intel.com>
982
983 PR binutis/18386
984 * i386-dis.c (indirEv): Replace stack_v_mode with indir_v_mode.
985 (indir_v_mode): New.
986 Add comments for '&'.
987 (reg_table): Replace "{T|}" with "{&|}" on call and jmp.
988 (putop): Handle '&'.
989 (intel_operand_size): Handle indir_v_mode.
990 (OP_E_register): Likewise.
991 * i386-opc.tbl: Mark 64-bit indirect call/jmp as AMD64. Add
992 64-bit indirect call/jmp for AMD64.
993 * i386-tbl.h: Regenerated
994
4eb6f892
AB		 9952016-06-02 Andrew Burgess <andrew.burgess@embecosm.com>
996
997 * arc-dis.c (struct arc_operand_iterator): New structure.
998 (find_format_from_table): All the old content from find_format,
999 with some minor adjustments, and parameter renaming.
1000 (find_format_long_instructions): New function.
1001 (find_format): Rewritten.
1002 (arc_insn_length): Add LSB parameter.
1003 (extract_operand_value): New function.
1004 (operand_iterator_next): New function.
1005 (print_insn_arc): Use new functions to find opcode, and iterator
1006 over operands.
1007 * arc-opc.c (insert_nps_3bit_dst_short): New function.
1008 (extract_nps_3bit_dst_short): New function.
1009 (insert_nps_3bit_src2_short): New function.
1010 (extract_nps_3bit_src2_short): New function.
1011 (insert_nps_bitop1_size): New function.
1012 (extract_nps_bitop1_size): New function.
1013 (insert_nps_bitop2_size): New function.
1014 (extract_nps_bitop2_size): New function.
1015 (insert_nps_bitop_mod4_msb): New function.
1016 (extract_nps_bitop_mod4_msb): New function.
1017 (insert_nps_bitop_mod4_lsb): New function.
1018 (extract_nps_bitop_mod4_lsb): New function.
1019 (insert_nps_bitop_dst_pos3_pos4): New function.
1020 (extract_nps_bitop_dst_pos3_pos4): New function.
1021 (insert_nps_bitop_ins_ext): New function.
1022 (extract_nps_bitop_ins_ext): New function.
1023 (arc_operands): Add new operands.
1024 (arc_long_opcodes): New global array.
1025 (arc_num_long_opcodes): New global.
1026 * arc-nps400-tbl.h: Add comments referencing arc_long_opcodes.
1027
1fe0971e
TS		 10282016-06-01 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1029
1030 * nds32-asm.h: Add extern "C".
1031 * sh-opc.h: Likewise.
1032
315f180f
GM		 10332016-06-01 Graham Markall <graham.markall@embecosm.com>
1034
1035 * arc-nps400-tbl.h: Add operands a,b,u6, 0,b,u6, and
1036 0,b,limm to the rflt instruction.
1037
a2b5fccc
TS		 10382016-05-31 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1039
1040 * sh-opc.h (ARCH_SH_HAS_DSP): Make the shifted value an unsigned
1041 constant.
1042
0cbd0046
L		 10432016-05-29 H.J. Lu <hongjiu.lu@intel.com>
1044
1045 PR gas/20145
1046 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS,
1047 CPU_ANY_AVX512CD_FLAGS, CPU_ANY_AVX512ER_FLAGS,
1048 CPU_ANY_AVX512PF_FLAGS, CPU_ANY_AVX512DQ_FLAGS,
1049 CPU_ANY_AVX512BW_FLAGS, CPU_ANY_AVX512VL_FLAGS,
1050 CPU_ANY_AVX512IFMA_FLAGS and CPU_ANY_AVX512VBMI_FLAGS.
1051 * i386-init.h: Regenerated.
1052
1848e567
L		 10532016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1054
1055 PR gas/20145
1056 * i386-gen.c (cpu_flag_init): Update CPU_XXX_FLAGS. Remove
1057 CpuMMX from CPU_SSE_FLAGS. Remove AVX and AVX512 bits from
1058 CPU_ANY_SSE_FLAGS. Remove AVX512 bits from CPU_ANY_AVX_FLAGS.
1059 Add CPU_XSAVE_FLAGS to CPU_XSAVEOPT_FLAGS, CPU_XSAVE_FLAGS and
1060 CpuXSAVEC. Add CPU_AVX_FLAGS to CpuF16C. Remove CpuMMX from
1061 CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS,
1062 CPU_AVX512PF_FLAGS, CPU_AVX512DQ_FLAGS and CPU_AVX512BW_FLAGS.
1063 Add CPU_SSE2_FLAGS to CPU_SHA_FLAGS. Add CPU_ANY_287_FLAGS,
1064 CPU_ANY_387_FLAGS, CPU_ANY_687_FLAGS, CPU_ANY_SSE2_FLAGS,
1065 CPU_ANY_SSE3_FLAGS, CPU_ANY_SSSE3_FLAGS, CPU_ANY_SSE4_1_FLAGS,
1066 CPU_ANY_SSE4_2_FLAGS and CPU_ANY_AVX2_FLAGS. Enable CpuRegMMX
1067 for MMX. Enable CpuRegXMM for SSE, AVX and AVX512. Enable
1068 CpuRegYMM for AVX and AVX512VL, Enable CpuRegZMM and
1069 CpuRegMask for AVX512.
1070 (cpu_flags): Add CpuRegMMX, CpuRegXMM, CpuRegYMM, CpuRegZMM
1071 and CpuRegMask.
1072 (set_bitfield_from_cpu_flag_init): New function.
1073 (set_bitfield): Remove const on f. Call
1074 set_bitfield_from_cpu_flag_init to handle CPU_XXX_FLAGS.
1075 * i386-opc.h (CpuRegMMX): New.
1076 (CpuRegXMM): Likewise.
1077 (CpuRegYMM): Likewise.
1078 (CpuRegZMM): Likewise.
1079 (CpuRegMask): Likewise.
1080 (i386_cpu_flags): Add cpuregmmx, cpuregxmm, cpuregymm, cpuregzmm
1081 and cpuregmask.
1082 * i386-init.h: Regenerated.
1083 * i386-tbl.h: Likewise.
1084
e92bae62
L		 10852016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1086
1087 PR gas/20154
1088 * i386-gen.c (cpu_flags): Remove CpuAMD64 and CpuIntel64.
1089 (opcode_modifiers): Add AMD64 and Intel64.
1090 (main): Properly verify CpuMax.
1091 * i386-opc.h (CpuAMD64): Removed.
1092 (CpuIntel64): Likewise.
1093 (CpuMax): Set to CpuNo64.
1094 (i386_cpu_flags): Remove cpuamd64 and cpuintel64.
1095 (AMD64): New.
1096 (Intel64): Likewise.
1097 (i386_opcode_modifier): Add amd64 and intel64.
1098 (i386-opc.tbl): Replace CpuAMD64/CpuIntel64 with AMD64/Intel64
1099 on call and jmp.
1100 * i386-init.h: Regenerated.
1101 * i386-tbl.h: Likewise.
1102
e89c5eaa
L		 11032016-05-27 H.J. Lu <hongjiu.lu@intel.com>
1104
1105 PR gas/20154
1106 * i386-gen.c (main): Fail if CpuMax is incorrect.
1107 * i386-opc.h (CpuMax): Set to CpuIntel64.
1108 * i386-tbl.h: Regenerated.
1109
77d66e7b
NC		 11102016-05-27 Nick Clifton <nickc@redhat.com>
1111
1112 PR target/20150
1113 * msp430-dis.c (msp430dis_read_two_bytes): New function.
1114 (msp430dis_opcode_unsigned): New function.
1115 (msp430dis_opcode_signed): New function.
1116 (msp430_singleoperand): Use the new opcode reading functions.
1117 Only disassenmble bytes if they were successfully read.
1118 (msp430_doubleoperand): Likewise.
1119 (msp430_branchinstr): Likewise.
1120 (msp430x_callx_instr): Likewise.
1121 (print_insn_msp430): Check that it is safe to read bytes before
1122 attempting disassembly. Use the new opcode reading functions.
1123
19dfcc89
PB		 11242016-05-26 Peter Bergner <bergner@vnet.ibm.com>
1125
1126 * ppc-opc.c (CY): New define. Document it.
1127 (powerpc_opcodes) <addex[.], lwzmx, vmsumudm>: New mnemonics.
1128
f3ad7637
L		 11292016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1130
1131 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512DQ_FLAGS,
1132 CPU_AVX512BW_FLAGS, CPU_AVX512VL_FLAGS, CPU_AVX512IFMA_FLAGS
1133 and CPU_AVX512VBMI_FLAGS. Add CpuAVX512DQ, CpuAVX512BW,
1134 CpuAVX512VL, CpuAVX512IFMA and CpuAVX512VBMI to
1135 CPU_ANY_AVX_FLAGS.
1136 * i386-init.h: Regenerated.
1137
f1360d58
L		 11382016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1139
1140 PR gas/20141
1141 * i386-gen.c (cpu_flag_init): Add CpuVREX to CPU_AVX512F_FLAGS,
1142 CPU_AVX512CD_FLAGS, CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
1143 * i386-init.h: Regenerated.
1144
293f5f65
L		 11452016-05-25 H.J. Lu <hongjiu.lu@intel.com>
1146
1147 * i386-gen.c (cpu_flag_init): Rename CPU_ANY87_FLAGS to
1148 CPU_ANY_X87_FLAGS. Add CPU_ANY_MMX_FLAGS.
1149 * i386-init.h: Regenerated.
1150
d9eca1df
CZ		 11512016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1152
1153 * arc-dis.c (print_flags): Set branch_delay_insns, and insn_type
1154 information.
1155 (print_insn_arc): Set insn_type information.
1156 * arc-opc.c (C_CC): Add F_CLASS_COND.
1157 * arc-tbl.h (bbit0, bbit1): Update subclass to COND.
1158 (beq_s, bge_s, bgt_s, bhi_s, bhs_s): Likewise.
1159 (ble_s, blo_s, bls_s, blt_s, bne_s): Likewise.
1160 (breq, breq_s, brge, brhs, brlo, brlt): Likewise.
1161 (brne, brne_s, jeq_s, jne_s): Likewise.
1162
87789e08
CZ		 11632016-05-23 Claudiu Zissulescu <claziss@synopsys.com>
1164
1165 * arc-tbl.h (neg): New instruction variant.
1166
c810e0b8
CZ		 11672016-05-23 Cupertino Miranda <cmiranda@synopsys.com>
1168
1169 * arc-dis.c (find_format, find_format, get_auxreg)
1170 (print_insn_arc): Changed.
1171 * arc-ext.h (INSERT_XOP): Likewise.
1172
3d207518
TS		 11732016-05-23 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1174
1175 * tic54x-dis.c (sprint_mmr): Adjust.
1176 * tic54x-opc.c: Likewise.
1177
514e58b7
AM		 11782016-05-19 Alan Modra <amodra@gmail.com>
1179
1180 * ppc-opc.c (NSISIGNOPT): Use insert_nsi and extract_nsi.
1181
e43de63c
AM		 11822016-05-19 Alan Modra <amodra@gmail.com>
1183
1184 * ppc-opc.c: Formatting.
1185 (NSISIGNOPT): Define.
1186 (powerpc_opcodes <subis>): Use NSISIGNOPT.
1187
1401d2fe
MR		 11882016-05-18 Maciej W. Rozycki <macro@imgtec.com>
1189
1190 * mips-dis.c (is_compressed_mode_p): Add `micromips_p' operand,
1191 replacing references to `micromips_ase' throughout.
1192 (_print_insn_mips): Don't use file-level microMIPS annotation to
1193 determine the disassembly mode with the symbol table.
1194
1178da44
PB		 11952016-05-13 Peter Bergner <bergner@vnet.ibm.com>
1196
1197 * ppc-opc.c (IMM8): Use PPC_OPERAND_SIGNOPT.
1198
8f4f9071
MF		 11992016-05-11 Andrew Bennett <andrew.bennett@imgtec.com>
1200
1201 * mips-dis.c (mips_arch_choices): Add ASE_DSPR3 to mips32r6 and
1202 mips64r6.
1203 * mips-opc.c (D34): New macro.
1204 (mips_builtin_opcodes): Define bposge32c for DSPr3.
1205
8bc52696
AF		 12062016-05-10 Alexander Fomin <alexander.fomin@intel.com>
1207
1208 * i386-dis.c (prefix_table): Add RDPID instruction.
1209 * i386-gen.c (cpu_flag_init): Add RDPID flag.
1210 (cpu_flags): Add RDPID bitfield.
1211 * i386-opc.h (enum): Add RDPID element.
1212 (i386_cpu_flags): Add RDPID field.
1213 * i386-opc.tbl: Add RDPID instruction.
1214 * i386-init.h: Regenerate.
1215 * i386-tbl.h: Regenerate.
1216
39d911fc
TP		 12172016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1218
1219 * arm-dis.c (get_sym_code_type): Use ARM_GET_SYM_BRANCH_TYPE to get
1220 branch type of a symbol.
1221 (print_insn): Likewise.
1222
16a1fa25
TP		 12232016-05-10 Thomas Preud'homme <thomas.preudhomme@arm.com>
1224
1225 * arm-dis.c (coprocessor_opcodes): Add entries for VFP ARMv8-M
1226 Mainline Security Extensions instructions.
1227 (thumb_opcodes): Add entries for narrow ARMv8-M Security
1228 Extensions instructions.
1229 (thumb32_opcodes): Add entries for wide ARMv8-M Security Extensions
1230 instructions.
1231 (psr_name): Add new MSP_NS and PSP_NS ARMv8-M Security Extensions
1232 special registers.
1233
d751b79e
JM		 12342016-05-09 Jose E. Marchesi <jose.marchesi@oracle.com>
1235
1236 * sparc-opc.c (sparc_opcodes): Fix mnemonic of faligndatai.
1237
945e0f82
CZ		 12382016-05-03 Claudiu Zissulescu <claziss@synopsys.com>
1239
1240 * arc-ext.c (dump_ARC_extmap): Handle SYNATX_NOP and SYNTAX_1OP.
1241 (arcExtMap_genOpcode): Likewise.
1242 * arc-opc.c (arg_32bit_rc): Define new variable.
1243 (arg_32bit_u6): Likewise.
1244 (arg_32bit_limm): Likewise.
1245
20f55f38
SN		 12462016-05-03 Szabolcs Nagy <szabolcs.nagy@arm.com>
1247
1248 * aarch64-gen.c (VERIFIER): Define.
1249 * aarch64-opc.c (VERIFIER): Define.
1250 (verify_ldpsw): Use static linkage.
1251 * aarch64-opc.h (verify_ldpsw): Remove.
1252 * aarch64-tbl.h: Use VERIFIER for verifiers.
1253
4bd13cde
NC		 12542016-04-28 Nick Clifton <nickc@redhat.com>
1255
1256 PR target/19722
1257 * aarch64-dis.c (aarch64_opcode_decode): Run verifier if present.
1258 * aarch64-opc.c (verify_ldpsw): New function.
1259 * aarch64-opc.h (verify_ldpsw): New prototype.
1260 * aarch64-tbl.h: Add initialiser for verifier field.
1261 (LDPSW): Set verifier to verify_ldpsw.
1262
c0f92bf9
L		 12632016-04-23 H.J. Lu <hongjiu.lu@intel.com>
1264
1265 PR binutils/19983
1266 PR binutils/19984
1267 * i386-dis.c (print_insn): Return -1 if size of bfd_vma is
1268 smaller than address size.
1269
e6c7cdec
TS		 12702016-04-20 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1271
1272 * alpha-dis.c: Regenerate.
1273 * crx-dis.c: Likewise.
1274 * disassemble.c: Likewise.
1275 * epiphany-opc.c: Likewise.
1276 * fr30-opc.c: Likewise.
1277 * frv-opc.c: Likewise.
1278 * ip2k-opc.c: Likewise.
1279 * iq2000-opc.c: Likewise.
1280 * lm32-opc.c: Likewise.
1281 * lm32-opinst.c: Likewise.
1282 * m32c-opc.c: Likewise.
1283 * m32r-opc.c: Likewise.
1284 * m32r-opinst.c: Likewise.
1285 * mep-opc.c: Likewise.
1286 * mt-opc.c: Likewise.
1287 * or1k-opc.c: Likewise.
1288 * or1k-opinst.c: Likewise.
1289 * tic80-opc.c: Likewise.
1290 * xc16x-opc.c: Likewise.
1291 * xstormy16-opc.c: Likewise.
1292
537aefaf
AB		 12932016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1294
1295 * arc-nps400-tbl.h: Add addb, subb, adcb, sbcb, andb, xorb, orb,
1296 fxorb, wxorb, shlb, shrb, notb, cntbb, div, mod, divm, qcmp,
1297 calcsd, and calcxd instructions.
1298 * arc-opc.c (insert_nps_bitop_size): Delete.
1299 (extract_nps_bitop_size): Delete.
1300 (MAKE_SRC_POS_INSERT_EXTRACT_FUNCS): Define, and use.
1301 (extract_nps_qcmp_m3): Define.
1302 (extract_nps_qcmp_m2): Define.
1303 (extract_nps_qcmp_m1): Define.
1304 (arc_flag_operands): Add F_NPS_SX, F_NPS_AR, F_NPS_AL.
1305 (arc_flag_classes): Add C_NPS_SX, C_NPS_AR_AL
1306 (arc_operands): Add NPS_SRC2_POS, NPS_SRC1_POS, NPS_ADDB_SIZE,
1307 NPS_ANDB_SIZE, NPS_FXORB_SIZ, NPS_WXORB_SIZ, NPS_R_XLDST,
1308 NPS_DIV_UIMM4, NPS_QCMP_SIZE, NPS_QCMP_M1, NPS_QCMP_M2, and
1309 NPS_QCMP_M3.
1310
c8f785f2
AB		 13112016-04-19 Andrew Burgess <andrew.burgess@embecosm.com>
1312
1313 * arc-nps400-tbl.h: Add dctcp, dcip, dcet, and dcacl instructions.
1314
6fd8e7c2
L		 13152016-04-15 H.J. Lu <hongjiu.lu@intel.com>
1316
1317 * Makefile.in: Regenerated with automake 1.11.6.
1318 * aclocal.m4: Likewise.
1319
4b0c052e
AB		 13202016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1321
1322 * arc-nps400-tbl.h: Add xldb, xldw, xld, xstb, xstw, and xst
1323 instructions.
1324 * arc-opc.c (insert_nps_cmem_uimm16): New function.
1325 (extract_nps_cmem_uimm16): New function.
1326 (arc_operands): Add NPS_XLDST_UIMM16 operand.
1327
cb040366
AB		 13282016-04-14 Andrew Burgess <andrew.burgess@embecosm.com>
1329
1330 * arc-dis.c (arc_insn_length): New function.
1331 (print_insn_arc): Use arc_insn_length, change insnLen to unsigned.
1332 (find_format): Change insnLen parameter to unsigned.
1333
accc0180
NC		 13342016-04-13 Nick Clifton <nickc@redhat.com>
1335
1336 PR target/19937
1337 * v850-opc.c (v850_opcodes): Correct masks for long versions of
1338 the LD.B and LD.BU instructions.
1339
f36e33da
CZ		 13402016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1341
1342 * arc-dis.c (find_format): Check for extension flags.
1343 (print_flags): New function.
1344 (print_insn_arc): Update for .extCondCode, .extCoreRegister and
1345 .extAuxRegister.
1346 * arc-ext.c (arcExtMap_coreRegName): Use
1347 LAST_EXTENSION_CORE_REGISTER.
1348 (arcExtMap_coreReadWrite): Likewise.
1349 (dump_ARC_extmap): Update printing.
1350 * arc-opc.c (arc_flag_classes): Add F_CLASS_EXTEND flag.
1351 (arc_aux_regs): Add cpu field.
1352 * arc-regs.h: Add cpu field, lower case name aux registers.
1353
1c2e355e
CZ		 13542016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1355
1356 * arc-tbl.h: Add rtsc, sleep with no arguments.
1357
b99747ae
CZ		 13582016-04-12 Claudiu Zissulescu <claziss@synopsys.com>
1359
1360 * arc-opc.c (flags_none, flags_f, flags_cc, flags_ccf):
1361 Initialize.
1362 (arg_none, arg_32bit_rarbrc, arg_32bit_zarbrc, arg_32bit_rbrbrc)
1363 (arg_32bit_rarbu6, arg_32bit_zarbu6, arg_32bit_rbrbu6)
1364 (arg_32bit_rbrbs12, arg_32bit_ralimmrc, arg_32bit_rarblimm)
1365 (arg_32bit_zalimmrc, arg_32bit_zarblimm, arg_32bit_rbrblimm)
1366 (arg_32bit_ralimmu6, arg_32bit_zalimmu6, arg_32bit_zalimms12)
1367 (arg_32bit_ralimmlimm, arg_32bit_zalimmlimm, arg_32bit_rbrc)
1368 (arg_32bit_zarc, arg_32bit_rbu6, arg_32bit_zau6, arg_32bit_rblimm)
1369 (arg_32bit_zalimm, arg_32bit_limmrc, arg_32bit_limmu6)
1370 (arg_32bit_limms12, arg_32bit_limmlimm): Likewise.
1371 (arc_opcode arc_opcodes): Null terminate the array.
1372 (arc_num_opcodes): Remove.
1373 * arc-ext.h (INSERT_XOP): Define.
1374 (extInstruction_t): Likewise.
1375 (arcExtMap_instName): Delete.
1376 (arcExtMap_insn): New function.
1377 (arcExtMap_genOpcode): Likewise.
1378 * arc-ext.c (ExtInstruction): Remove.
1379 (create_map): Zero initialize instruction fields.
1380 (arcExtMap_instName): Remove.
1381 (arcExtMap_insn): New function.
1382 (dump_ARC_extmap): More info while debuging.
1383 (arcExtMap_genOpcode): New function.
1384 * arc-dis.c (find_format): New function.
1385 (print_insn_arc): Use find_format.
1386 (arc_get_disassembler): Enable dump_ARC_extmap only when
1387 debugging.
1388
92708cec
MR		 13892016-04-11 Maciej W. Rozycki <macro@imgtec.com>
1390
1391 * mips-dis.c (print_mips16_insn_arg): Mask unused extended
1392 instruction bits out.
1393
a42a4f84
AB		 13942016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1395
1396 * arc-nps400-tbl.h: Add schd, sync, and hwschd instructions.
1397 * arc-opc.c (arc_flag_operands): Add new flags.
1398 (arc_flag_classes): Add new classes.
1399
1328504b
AB		 14002016-04-07 Andrew Burgess <andrew.burgess@embecosm.com>
1401
1402 * arc-opc.c (arc_opcodes): Extend comment to discus table layout.
1403
820f03ff
AB		 14042016-04-05 Andrew Burgess <andrew.burgess@embecosm.com>
1405
1406 * arc-nps400-tbl.h: Add movbi, decode1, fbset, fbclear, encode0,
1407 encode1, rflt, crc16, and crc32 instructions.
1408 * arc-opc.c (arc_flag_operands): Add F_NPS_R.
1409 (arc_flag_classes): Add C_NPS_R.
1410 (insert_nps_bitop_size_2b): New function.
1411 (extract_nps_bitop_size_2b): Likewise.
1412 (insert_nps_bitop_uimm8): Likewise.
1413 (extract_nps_bitop_uimm8): Likewise.
1414 (arc_operands): Add new operand entries.
1415
8ddf6b2a
CZ		 14162016-04-05 Claudiu Zissulescu <claziss@synopsys.com>
1417
b99747ae
CZ		 1418 * arc-regs.h: Add a new subclass field. Add double assist
1419 accumulator register values.
1420 * arc-tbl.h: Use DPA subclass to mark the double assist
1421 instructions. Use DPX/SPX subclas to mark the FPX instructions.
1422 * arc-opc.c (RSP): Define instead of SP.
1423 (arc_aux_regs): Add the subclass field.
8ddf6b2a 1424
589a7d88
JW		 14252016-04-05 Jiong Wang <jiong.wang@arm.com>
1426
1427 * arm-dis.c: Support FP16 vmul, vmla, vmls (by scalar).
1428
0a191de9 14292016-03-31 Andrew Burgess <andrew.burgess@embecosm.com>
2cce10e7
AB		 1430
1431 * arc-opc.c (arc_operands): Fix operand flags for NPS_R_DST, and
1432 NPS_R_SRC1.
1433
0a106562
AB		 14342016-03-30 Andrew Burgess <andrew.burgess@embecosm.com>
1435
1436 * arc-nps400-tbl.h: Add a header comment, and fix some whitespace
1437 issues. No functional changes.
1438
bd05ac5f
CZ		 14392016-03-30 Claudiu Zissulescu <claziss@synopsys.com>
1440
b99747ae
CZ		 1441 * arc-regs.h (IC_RAM_ADDRESS, IC_TAG, IC_WP, IC_DATA, CONTROL0)
1442 (AX2, AY2, MX2, MY2, AY0, AY1, DC_RAM_ADDR, DC_TAG, CONTROL1)
1443 (RTT): Remove duplicate.
1444 (LCDINSTR, LCDDATA, LCDSTAT, CC_*, PCT_COUNT*, PCT_SNAP*)
1445 (PCT_CONFIG*): Remove.
1446 (D1L, D1H, D2H, D2L): Define.
bd05ac5f 1447
9885948f
CZ		 14482016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1449
b99747ae 1450 * arc-ext-tbl.h (dsp_fp_i2flt): Fix typo.
9885948f 1451
f2dd8838
CZ		 14522016-03-29 Claudiu Zissulescu <claziss@synopsys.com>
1453
b99747ae
CZ		 1454 * arc-tbl.h (invld07): Remove.
1455 * arc-ext-tbl.h: New file.
1456 * arc-dis.c (FIELDA, FIELDB, FIELDC): Remove.
1457 * arc-opc.c (arc_opcodes): Add ext-tbl include.
f2dd8838 1458
0d2f91fe
JK		 14592016-03-24 Jan Kratochvil <jan.kratochvil@redhat.com>
1460
1461 Fix -Wstack-usage warnings.
1462 * aarch64-dis.c (print_operands): Substitute size.
1463 * aarch64-opc.c (print_register_offset_address): Substitute tblen.
1464
a6b71f42
JM		 14652016-03-22 Jose E. Marchesi <jose.marchesi@oracle.com>
1466
1467 * sparc-opc.c (sparc_opcodes): Reorder entries for `rd' in order
1468 to get a proper diagnostic when an invalid ASR register is used.
1469
9780e045
NC		 14702016-03-22 Nick Clifton <nickc@redhat.com>
1471
1472 * configure: Regenerate.
1473
e23e8ebe
AB		 14742016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1475
1476 * arc-nps400-tbl.h: New file.
1477 * arc-opc.c: Add top level comment.
1478 (insert_nps_3bit_dst): New function.
1479 (extract_nps_3bit_dst): New function.
1480 (insert_nps_3bit_src2): New function.
1481 (extract_nps_3bit_src2): New function.
1482 (insert_nps_bitop_size): New function.
1483 (extract_nps_bitop_size): New function.
1484 (arc_flag_operands): Add nps400 entries.
1485 (arc_flag_classes): Add nps400 entries.
1486 (arc_operands): Add nps400 entries.
1487 (arc_opcodes): Add nps400 include.
1488
1ae8ab47
AB		 14892016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1490
1491 * arc-opc.c (arc_flag_classes): Convert all flag classes to use
1492 the new class enum values.
1493
8699fc3e
AB		 14942016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1495
1496 * arc-dis.c (print_insn_arc): Handle nps400.
1497
24740d83
AB		 14982016-03-21 Andrew Burgess <andrew.burgess@embecosm.com>
1499
1500 * arc-opc.c (BASE): Delete.
1501
8678914f
NC		 15022016-03-18 Nick Clifton <nickc@redhat.com>
1503
1504 PR target/19721
1505 * aarch64-tbl.h (aarch64_opcode_table): Fix type of second operand
1506 of MOV insn that aliases an ORR insn.
1507
cc933301
JW		 15082016-03-16 Jiong Wang <jiong.wang@arm.com>
1509
1510 * arm-dis.c (neon_opcodes): Support new FP16 instructions.
1511
f86f5863
TS		 15122016-03-07 Trevor Saunders <tbsaunde+binutils@tbsaunde.org>
1513
1514 * mcore-opc.h: Add const qualifiers.
1515 * microblaze-opc.h (struct op_code_struct): Likewise.
1516 * sh-opc.h: Likewise.
1517 * tic4x-dis.c (tic4x_print_indirect): Likewise.
1518 (tic4x_print_op): Likewise.
1519
62de1c63
AM		 15202016-03-02 Alan Modra <amodra@gmail.com>
1521
d11698cd 1522 * or1k-desc.h: Regenerate.
62de1c63 1523 * fr30-ibld.c: Regenerate.
c697cf0b 1524 * rl78-decode.c: Regenerate.
62de1c63 1525
020efce5
NC		 15262016-03-01 Nick Clifton <nickc@redhat.com>
1527
1528 PR target/19747
1529 * rl78-dis.c (print_insn_rl78_common): Fix typo.
1530
b0c11777
RL		 15312016-02-24 Renlin Li <renlin.li@arm.com>
1532
1533 * arm-dis.c (coprocessor_opcodes): Add fp16 instruction entries.
1534 (print_insn_coprocessor): Support fp16 instructions.
1535
3e309328
RL		 15362016-02-24 Renlin Li <renlin.li@arm.com>
1537
1538 * arm-dis.c (print_insn_coprocessor): Fix mask for vsel, vmaxnm,
1539 vminnm, vrint(mpna).
1540
8afc7bea
RL		 15412016-02-24 Renlin Li <renlin.li@arm.com>
1542
1543 * arm-dis.c (print_insn_coprocessor): Check co-processor number for
1544 cpd/cpd2, mcr/mcr2, mrc/mrc2, ldc/ldc2, stc/stc2.
1545
4fd7268a
L		 15462016-02-15 H.J. Lu <hongjiu.lu@intel.com>
1547
1548 * i386-dis.c (print_insn): Parenthesize expression to prevent
1549 truncated addresses.
1550 (OP_J): Likewise.
1551
4670103e
CZ		 15522016-02-10 Claudiu Zissulescu <claziss@synopsys.com>
1553 Janek van Oirschot <jvanoirs@synopsys.com>
1554
b99747ae
CZ		 1555 * arc-opc.c (arc_relax_opcodes, arc_num_relax_opcodes): New
1556 variable.
4670103e 1557
c1d9289f
NC		 15582016-02-04 Nick Clifton <nickc@redhat.com>
1559
1560 PR target/19561
1561 * msp430-dis.c (print_insn_msp430): Add a special case for
1562 decoding an RRC instruction with the ZC bit set in the extension
1563 word.
1564
a143b004
AB		 15652016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1566
1567 * cgen-ibld.in (insert_normal): Rework calculation of shift.
1568 * epiphany-ibld.c: Regenerate.
1569 * fr30-ibld.c: Regenerate.
1570 * frv-ibld.c: Regenerate.
1571 * ip2k-ibld.c: Regenerate.
1572 * iq2000-ibld.c: Regenerate.
1573 * lm32-ibld.c: Regenerate.
1574 * m32c-ibld.c: Regenerate.
1575 * m32r-ibld.c: Regenerate.
1576 * mep-ibld.c: Regenerate.
1577 * mt-ibld.c: Regenerate.
1578 * or1k-ibld.c: Regenerate.
1579 * xc16x-ibld.c: Regenerate.
1580 * xstormy16-ibld.c: Regenerate.
1581
b89807c6
AB		 15822016-02-02 Andrew Burgess <andrew.burgess@embecosm.com>
1583
1584 * epiphany-dis.c: Regenerated from latest cpu files.
1585
d8c823c8
MM		 15862016-02-01 Michael McConville <mmcco@mykolab.com>
1587
1588 * cgen-dis.c (count_decodable_bits): Use unsigned value for mask
1589 test bit.
1590
5bc5ae88
RL		 15912016-01-25 Renlin Li <renlin.li@arm.com>
1592
1593 * arm-dis.c (mapping_symbol_for_insn): New function.
1594 (find_ifthen_state): Call mapping_symbol_for_insn().
1595
0bff6e2d
MW		 15962016-01-20 Matthew Wahab <matthew.wahab@arm.com>
1597
1598 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
1599 of MSR UAO immediate operand.
1600
100b4f2e
MR		 16012016-01-18 Maciej W. Rozycki <macro@imgtec.com>
1602
1603 * mips-dis.c (print_insn_micromips): Remove 48-bit microMIPS
1604 instruction support.
1605
5c14705f
AM		 16062016-01-17 Alan Modra <amodra@gmail.com>
1607
1608 * configure: Regenerate.
1609
4d82fe66
NC		 16102016-01-14 Nick Clifton <nickc@redhat.com>
1611
1612 * rl78-decode.opc (rl78_decode_opcode): Add 's' operand to movw
1613 instructions that can support stack pointer operations.
1614 * rl78-decode.c: Regenerate.
1615 * rl78-dis.c: Fix display of stack pointer in MOVW based
1616 instructions.
1617
651657fa
MW		 16182016-01-14 Matthew Wahab <matthew.wahab@arm.com>
1619
1620 * aarch64-opc.c (aarch64_sys_reg_supported_p): Merge conditionals
1621 testing for RAS support. Add checks for erxfr_el1, erxctlr_el1,
1622 erxtatus_el1 and erxaddr_el1.
1623
105bde57
MW		 16242016-01-12 Matthew Wahab <matthew.wahab@arm.com>
1625
1626 * arm-dis.c (arm_opcodes): Add "esb".
1627 (thumb_opcodes): Likewise.
1628
afa8d405
PB		 16292016-01-11 Peter Bergner <bergner@vnet.ibm.com>
1630
1631 * ppc-opc.c <xscmpnedp>: Delete.
1632 <xvcmpnedp>: Likewise.
1633 <xvcmpnedp.>: Likewise.
1634 <xvcmpnesp>: Likewise.
1635 <xvcmpnesp.>: Likewise.
1636
83c3256e
AS		 16372016-01-08 Andreas Schwab <schwab@linux-m68k.org>
1638
1639 PR gas/13050
1640 * m68k-opc.c (moveb, movew): For ISA_B/C only allow #,d(An) in
1641 addition to ISA_A.
1642
6f2750fe
AM		 16432016-01-01 Alan Modra <amodra@gmail.com>
1644
1645 Update year range in copyright notice of all files.
1646
3499769a
AM		 1647For older changes see ChangeLog-2015
1648\f
1649Copyright (C) 2016 Free Software Foundation, Inc.
1650
1651Copying and distribution of this file, with or without modification,
1652are permitted in any medium without royalty provided the copyright
1653notice and this notice are preserved.
1654
1655Local Variables:
1656mode: change-log
1657left-margin: 8
1658fill-column: 74
1659version-control: never
1660End:
A mirror of the official binutils-gdb repository