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gdb: fix powerpc disassembly tests
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CommitLineData
44e4546f
AM
12020-02-03 Alan Modra <amodra@gmail.com>
2
3 * m32c-ibld.c: Regenerate.
4
b2b1453a
AM
52020-02-01 Alan Modra <amodra@gmail.com>
6
7 * frv-ibld.c: Regenerate.
8
4102be5c
JB
92020-01-31 Jan Beulich <jbeulich@suse.com>
10
11 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
12 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
13 (OP_E_memory): Replace xmm_mdq_mode case label by
14 vex_scalar_w_dq_mode one.
15 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
16
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JB
172020-01-31 Jan Beulich <jbeulich@suse.com>
18
19 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
20 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
21 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
22 (intel_operand_size): Drop vex_w_dq_mode case label.
23
c3036ed0
RS
242020-01-31 Richard Sandiford <richard.sandiford@arm.com>
25
26 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
27 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
28
0c115f84
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292020-01-30 Alan Modra <amodra@gmail.com>
30
31 * m32c-ibld.c: Regenerate.
32
bd434cc4
JM
332020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
34
35 * bpf-opc.c: Regenerate.
36
aeab2b26
JB
372020-01-30 Jan Beulich <jbeulich@suse.com>
38
39 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
40 (dis386): Use them to replace C2/C3 table entries.
41 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
42 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
43 ones. Use Size64 instead of DefaultSize on Intel64 ones.
44 * i386-tbl.h: Re-generate.
45
62b3f548
JB
462020-01-30 Jan Beulich <jbeulich@suse.com>
47
48 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
49 forms.
50 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
51 DefaultSize.
52 * i386-tbl.h: Re-generate.
53
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542020-01-30 Alan Modra <amodra@gmail.com>
55
56 * tic4x-dis.c (tic4x_dp): Make unsigned.
57
bc31405e
L
582020-01-27 H.J. Lu <hongjiu.lu@intel.com>
59 Jan Beulich <jbeulich@suse.com>
60
61 PR binutils/25445
62 * i386-dis.c (MOVSXD_Fixup): New function.
63 (movsxd_mode): New enum.
64 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
65 (intel_operand_size): Handle movsxd_mode.
66 (OP_E_register): Likewise.
67 (OP_G): Likewise.
68 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
69 register on movsxd. Add movsxd with 16-bit destination register
70 for AMD64 and Intel64 ISAs.
71 * i386-tbl.h: Regenerated.
72
7568c93b
TC
732020-01-27 Tamar Christina <tamar.christina@arm.com>
74
75 PR 25403
76 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
77 * aarch64-asm-2.c: Regenerate
78 * aarch64-dis-2.c: Likewise.
79 * aarch64-opc-2.c: Likewise.
80
c006a730
JB
812020-01-21 Jan Beulich <jbeulich@suse.com>
82
83 * i386-opc.tbl (sysret): Drop DefaultSize.
84 * i386-tbl.h: Re-generate.
85
c906a69a
JB
862020-01-21 Jan Beulich <jbeulich@suse.com>
87
88 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
89 Dword.
90 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
91 * i386-tbl.h: Re-generate.
92
26916852
NC
932020-01-20 Nick Clifton <nickc@redhat.com>
94
95 * po/de.po: Updated German translation.
96 * po/pt_BR.po: Updated Brazilian Portuguese translation.
97 * po/uk.po: Updated Ukranian translation.
98
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992020-01-20 Alan Modra <amodra@gmail.com>
100
101 * hppa-dis.c (fput_const): Remove useless cast.
102
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1032020-01-20 Alan Modra <amodra@gmail.com>
104
105 * arm-dis.c (print_insn_arm): Wrap 'T' value.
106
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NC
1072020-01-18 Nick Clifton <nickc@redhat.com>
108
109 * configure: Regenerate.
110 * po/opcodes.pot: Regenerate.
111
ae774686
NC
1122020-01-18 Nick Clifton <nickc@redhat.com>
113
114 Binutils 2.34 branch created.
115
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CB
1162020-01-17 Christian Biesinger <cbiesinger@google.com>
117
118 * opintl.h: Fix spelling error (seperate).
119
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L
1202020-01-17 H.J. Lu <hongjiu.lu@intel.com>
121
122 * i386-opc.tbl: Add {vex} pseudo prefix.
123 * i386-tbl.h: Regenerated.
124
2da2eaf4
AV
1252020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
126
127 PR 25376
128 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
129 (neon_opcodes): Likewise.
130 (select_arm_features): Make sure we enable MVE bits when selecting
131 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
132 any architecture.
133
d0849eed
JB
1342020-01-16 Jan Beulich <jbeulich@suse.com>
135
136 * i386-opc.tbl: Drop stale comment from XOP section.
137
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JB
1382020-01-16 Jan Beulich <jbeulich@suse.com>
139
140 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
141 (extractps): Add VexWIG to SSE2AVX forms.
142 * i386-tbl.h: Re-generate.
143
4814632e
JB
1442020-01-16 Jan Beulich <jbeulich@suse.com>
145
146 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
147 Size64 from and use VexW1 on SSE2AVX forms.
148 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
149 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
150 * i386-tbl.h: Re-generate.
151
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1522020-01-15 Alan Modra <amodra@gmail.com>
153
154 * tic4x-dis.c (tic4x_version): Make unsigned long.
155 (optab, optab_special, registernames): New file scope vars.
156 (tic4x_print_register): Set up registernames rather than
157 malloc'd registertable.
158 (tic4x_disassemble): Delete optable and optable_special. Use
159 optab and optab_special instead. Throw away old optab,
160 optab_special and registernames when info->mach changes.
161
7a6bf3be
SB
1622020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
163
164 PR 25377
165 * z80-dis.c (suffix): Use .db instruction to generate double
166 prefix.
167
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1682020-01-14 Alan Modra <amodra@gmail.com>
169
170 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
171 values to unsigned before shifting.
172
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TT
1732020-01-13 Thomas Troeger <tstroege@gmx.de>
174
175 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
176 flow instructions.
177 (print_insn_thumb16, print_insn_thumb32): Likewise.
178 (print_insn): Initialize the insn info.
179 * i386-dis.c (print_insn): Initialize the insn info fields, and
180 detect jumps.
181
5e4f7e05
CZ
1822012-01-13 Claudiu Zissulescu <claziss@gmail.com>
183
184 * arc-opc.c (C_NE): Make it required.
185
b9fe6b8a
CZ
1862012-01-13 Claudiu Zissulescu <claziss@gmail.com>
187
188 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
189 reserved register name.
190
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1912020-01-13 Alan Modra <amodra@gmail.com>
192
193 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
194 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
195
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1962020-01-13 Alan Modra <amodra@gmail.com>
197
198 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
199 result of wasm_read_leb128 in a uint64_t and check that bits
200 are not lost when copying to other locals. Use uint32_t for
201 most locals. Use PRId64 when printing int64_t.
202
df08b588
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2032020-01-13 Alan Modra <amodra@gmail.com>
204
205 * score-dis.c: Formatting.
206 * score7-dis.c: Formatting.
207
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2082020-01-13 Alan Modra <amodra@gmail.com>
209
210 * score-dis.c (print_insn_score48): Use unsigned variables for
211 unsigned values. Don't left shift negative values.
212 (print_insn_score32): Likewise.
213 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
214
5496abe1
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2152020-01-13 Alan Modra <amodra@gmail.com>
216
217 * tic4x-dis.c (tic4x_print_register): Remove dead code.
218
202e762b
AM
2192020-01-13 Alan Modra <amodra@gmail.com>
220
221 * fr30-ibld.c: Regenerate.
222
7ef412cf
AM
2232020-01-13 Alan Modra <amodra@gmail.com>
224
225 * xgate-dis.c (print_insn): Don't left shift signed value.
226 (ripBits): Formatting, use 1u.
227
7f578b95
AM
2282020-01-10 Alan Modra <amodra@gmail.com>
229
230 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
231 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
232
441af85b
AM
2332020-01-10 Alan Modra <amodra@gmail.com>
234
235 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
236 and XRREG value earlier to avoid a shift with negative exponent.
237 * m10200-dis.c (disassemble): Similarly.
238
bce58db4
NC
2392020-01-09 Nick Clifton <nickc@redhat.com>
240
241 PR 25224
242 * z80-dis.c (ld_ii_ii): Use correct cast.
243
40c75bc8
SB
2442020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
245
246 PR 25224
247 * z80-dis.c (ld_ii_ii): Use character constant when checking
248 opcode byte value.
249
d835a58b
JB
2502020-01-09 Jan Beulich <jbeulich@suse.com>
251
252 * i386-dis.c (SEP_Fixup): New.
253 (SEP): Define.
254 (dis386_twobyte): Use it for sysenter/sysexit.
255 (enum x86_64_isa): Change amd64 enumerator to value 1.
256 (OP_J): Compare isa64 against intel64 instead of amd64.
257 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
258 forms.
259 * i386-tbl.h: Re-generate.
260
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AM
2612020-01-08 Alan Modra <amodra@gmail.com>
262
263 * z8k-dis.c: Include libiberty.h
264 (instr_data_s): Make max_fetched unsigned.
265 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
266 Don't exceed byte_info bounds.
267 (output_instr): Make num_bytes unsigned.
268 (unpack_instr): Likewise for nibl_count and loop.
269 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
270 idx unsigned.
271 * z8k-opc.h: Regenerate.
272
bb82aefe
SV
2732020-01-07 Shahab Vahedi <shahab@synopsys.com>
274
275 * arc-tbl.h (llock): Use 'LLOCK' as class.
276 (llockd): Likewise.
277 (scond): Use 'SCOND' as class.
278 (scondd): Likewise.
279 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
280 (scondd): Likewise.
281
cc6aa1a6
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2822020-01-06 Alan Modra <amodra@gmail.com>
283
284 * m32c-ibld.c: Regenerate.
285
660e62b1
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2862020-01-06 Alan Modra <amodra@gmail.com>
287
288 PR 25344
289 * z80-dis.c (suffix): Don't use a local struct buffer copy.
290 Peek at next byte to prevent recursion on repeated prefix bytes.
291 Ensure uninitialised "mybuf" is not accessed.
292 (print_insn_z80): Don't zero n_fetch and n_used here,..
293 (print_insn_z80_buf): ..do it here instead.
294
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2952020-01-04 Alan Modra <amodra@gmail.com>
296
297 * m32r-ibld.c: Regenerate.
298
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2992020-01-04 Alan Modra <amodra@gmail.com>
300
301 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
302
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3032020-01-04 Alan Modra <amodra@gmail.com>
304
305 * crx-dis.c (match_opcode): Avoid shift left of signed value.
306
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AM
3072020-01-04 Alan Modra <amodra@gmail.com>
308
309 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
310
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JB
3112020-01-03 Jan Beulich <jbeulich@suse.com>
312
5437a02a
JB
313 * aarch64-tbl.h (aarch64_opcode_table): Use
314 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
315
3162020-01-03 Jan Beulich <jbeulich@suse.com>
317
318 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB
319 forms of SUDOT and USDOT.
320
8c45011a
JB
3212020-01-03 Jan Beulich <jbeulich@suse.com>
322
5437a02a 323 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB
324 uzip{1,2}.
325 * opcodes/aarch64-dis-2.c: Re-generate.
326
f4950f76
JB
3272020-01-03 Jan Beulich <jbeulich@suse.com>
328
5437a02a 329 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB
330 FMMLA encoding.
331 * opcodes/aarch64-dis-2.c: Re-generate.
332
6655dba2
SB
3332020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
334
335 * z80-dis.c: Add support for eZ80 and Z80 instructions.
336
b14ce8bf
AM
3372020-01-01 Alan Modra <amodra@gmail.com>
338
339 Update year range in copyright notice of all files.
340
0b114740 341For older changes see ChangeLog-2019
3499769a 342\f
0b114740 343Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
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344
345Copying and distribution of this file, with or without modification,
346are permitted in any medium without royalty provided the copyright
347notice and this notice are preserved.
348
349Local Variables:
350mode: change-log
351left-margin: 8
352fill-column: 74
353version-control: never
354End: