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IBM zSystems: Add support for z16 as CPU name.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
69341966
AK		 12022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
2
3 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
4 table.
5
e3161106
SM		 62022-03-16 Simon Marchi <simon.marchi@efficios.com>
7
8 * configure.ac: Handle bfd_amdgcn_arch.
9 * configure: Re-generate.
10
d17e797f
MR		 112022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
12 Maciej W. Rozycki <macro@orcam.me.uk>
13
14 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
15 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
16 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
17 "bnez" instructions.
18
36d285b9
NC		 192022-02-17 Nick Clifton <nickc@redhat.com>
20
21 * po/sr.po: Updated Serbian translation.
22
a532eb72
ST		 232022-02-14 Sergei Trofimovich <siarheit@google.com>
24
25 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
26 * microblaze-opc.h: Follow 'fsqrt' rename.
27
5fe73d46
NC		 282022-01-24 Nick Clifton <nickc@redhat.com>
29
30 * po/ro.po: Updated Romanian translation.
31 * po/uk.po: Updated Ukranian translation.
32
f908e960
NC		 332022-01-22 Nick Clifton <nickc@redhat.com>
34
35 * configure: Regenerate.
36 * po/opcodes.pot: Regenerate.
37
a74e1cb3
NC		 382022-01-22 Nick Clifton <nickc@redhat.com>
39
40 * 2.38 release branch created.
41
6c037fdb
NC		 422022-01-17 Nick Clifton <nickc@redhat.com>
43
44 * Makefile.in: Regenerate.
45 * po/opcodes.pot: Regenerate.
46
96c7115a
MN		 472021-12-02 Marcus Nilsson <brainbomb@gmail.com>
48
49 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
50 in insn_type on branching instructions.
51
3a337a86
AB		 522021-11-25 Andrew Burgess <aburgess@redhat.com>
53 Simon Cook <simon.cook@embecosm.com>
54
55 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
56 (riscv_options): New static global.
57 (disassembler_options_riscv): New function.
58 (print_riscv_disassembler_options): Rewrite to use
59 disassembler_options_riscv.
60
7060c28e
NC		 612021-11-25 Nick Clifton <nickc@redhat.com>
62
63 PR 28614
64 * aarch64-asm.c: Replace assert(0) with real code.
65 * aarch64-dis.c: Likewise.
66 * aarch64-opc.c: Likewise.
67
79abb939
NC		 682021-11-25 Nick Clifton <nickc@redhat.com>
69
70 * po/fr.po; Updated French translation.
71
2b677209
MR		 722021-10-27 Maciej W. Rozycki <macro@embecosm.com>
73
74 * Makefile.am: Remove obsolete comment.
75 * configure.ac: Refer `libbfd.la' to link shared BFD library
76 except for Cygwin.
77 * Makefile.in: Regenerate.
78 * configure: Regenerate.
79
b9004024
NA		 802021-09-27 Nick Alcock <nick.alcock@oracle.com>
81
82 * configure: Regenerate.
83
4d5d5d46
PB		 842021-09-25 Peter Bergner <bergner@linux.ibm.com>
85
86 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
87 on POWER5 and later.
88
6a7f5766
AB		 892021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
90
91 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
92 before an unknown instruction, '%d' is replaced with the
93 instruction length.
94
718aefcf
NC		 952021-09-02 Nick Clifton <nickc@redhat.com>
96
97 PR 28292
98 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
99 of BFD_RELOC_16.
100
5d9cff51
SV		 1012021-08-17 Shahab Vahedi <shahab@synopsys.com>
102
103 * arc-regs.h (DEF): Fix the register numbers.
104
3ee0cd9e
NC		 1052021-08-10 Nick Clifton <nickc@redhat.com>
106
107 * po/sr.po: Updated Serbian translation.
108
8d56b9fc
CX		 1092021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
110
111 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
112
b180e829
AK		 1132021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
114
115 * s390-opc.txt: Add qpaci.
116
346d80ef
NC		 1172021-07-03 Nick Clifton <nickc@redhat.com>
118
119 * configure: Regenerate.
120 * po/opcodes.pot: Regenerate.
121
51419248
NC		 1222021-07-03 Nick Clifton <nickc@redhat.com>
123
124 * 2.37 release branch created.
125
62194b63
AM		 1262021-07-02 Alan Modra <amodra@gmail.com>
127
128 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
129 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
130 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
131 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
132 (nds32_keyword_gpr): Move declarations to..
133 * nds32-asm.h: ..here, constifying to match definitions.
134
2fe36d31
MF		 1352021-07-01 Mike Frysinger <vapier@gentoo.org>
136
137 * Makefile.am (GUILE): New variable.
138 (CGEN): Use $(GUILE).
139 * Makefile.in: Regenerate.
140
f375d32b
MF		 1412021-07-01 Mike Frysinger <vapier@gentoo.org>
142
143 * mep-asm.c (macros): Mark static & const.
144 (lookup_macro): Change return & m to const.
145 (expand_macro): Change mac to const.
146 (expand_string): Change pmacro to const.
147
9b2beaf7
MF		 1482021-07-01 Mike Frysinger <vapier@gentoo.org>
149
150 * nds32-asm.c (operand_fields): Rename to ...
151 (nds32_operand_fields): ... this.
152 (keyword_gpr): Rename to ...
153 (nds32_keyword_gpr): ... this.
154 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
155 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
156 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
157 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
158 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
159 Mark static.
160 (keywords): Rename to ...
161 (nds32_keywords): ... this.
162 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
163 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
164
ac8ef696
MF		 1652021-07-01 Mike Frysinger <vapier@gentoo.org>
166
167 * z80-dis.c (opc_ed): Make const.
168 (pref_ed): Make p const.
169
52b83874
MF		 1702021-07-01 Mike Frysinger <vapier@gentoo.org>
171
172 * microblaze-dis.c (get_field_special): Make op const.
173 (read_insn_microblaze): Make opr & op const. Rename opcodes to
174 microblaze_opcodes.
175 (print_insn_microblaze): Make op & pop const.
176 (get_insn_microblaze): Make op const. Rename opcodes to
177 microblaze_opcodes.
178 (microblaze_get_target_address): Likewise.
179 * microblaze-opc.h (struct op_code_struct): Make const.
180 Rename opcodes to microblaze_opcodes.
181
6c2ede01
MF		 1822021-07-01 Mike Frysinger <vapier@gentoo.org>
183
184 * aarch64-gen.c (aarch64_opcode_table): Add const.
185 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
186
46b8b3d6
AB		 1872021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
188
189 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
190 available.
191
ded5cb94
AM		 1922021-06-22 Alan Modra <amodra@gmail.com>
193
194 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
195 print separator for pcrel insns.
196
47399e9c
AM		 1972021-06-19 Alan Modra <amodra@gmail.com>
198
199 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
200
d984392e
AM		 2012021-06-19 Alan Modra <amodra@gmail.com>
202
203 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
204 entire buffer.
205
7993124e
AM		 2062021-06-17 Alan Modra <amodra@gmail.com>
207
208 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
209 in table.
210
a38d1396
AM		 2112021-06-03 Alan Modra <amodra@gmail.com>
212
213 PR 1202
214 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
215 Use unsigned int for inst.
216
8f467114
SV		 2172021-06-02 Shahab Vahedi <shahab@synopsys.com>
218
219 * arc-dis.c (arc_option_arg_t): New enumeration.
220 (arc_options): New variable.
221 (disassembler_options_arc): New function.
222 (print_arc_disassembler_options): Reimplement in terms of
223 "disassembler_options_arc".
224
1ff6a3b8
AM		 2252021-05-29 Alan Modra <amodra@gmail.com>
226
227 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
228 Don't special case PPC_OPCODE_RAW.
229 (lookup_prefix): Likewise.
230 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
231 (print_insn_powerpc): ..update caller.
232 * ppc-opc.c (EXT): Define.
233 (powerpc_opcodes): Mark extended mnemonics with EXT.
234 (prefix_opcodes, vle_opcodes): Likewise.
235 (XISEL, XISEL_MASK): Add cr field and simplify.
236 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
237 all isel variants to where the base mnemonic belongs. Sort dstt,
238 dststt and dssall.
239
49149d59
MR		 2402021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
241
242 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
243 COP3 opcode instructions.
244
9573a461
MR		 2452021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
246
247 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
248 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
249 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
250 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
251 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
252 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
253 "cop2", and "cop3" entries.
254
fa495743
MR		 2552021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
256
257 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
258 entries and associated comments.
259
b930964c
MR		 2602021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
261
262 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
263 of "c0".
264
dd844468
MR		 2652021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
266
267 * mips-dis.c (mips_cp1_names_mips): New variable.
268 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
269 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
270 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
271 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
272 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
273 "loongson2f".
274
9204ccd4
MR		 2752021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
276
277 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
278 handling code over to...
279 <OP_REG_CONTROL>: ... this new case.
280 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
281 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
282 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
283 replacing the `G' operand code with `g'. Update "cftc1" and
284 "cftc2" entries replacing the `E' operand code with `y'.
285 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
286 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
287 entries replacing the `G' operand code with `g'.
288
a3fb396f
MR		 2892021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
290
291 * mips-dis.c (mips_cp0_names_r3900): New variable.
292 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
293 for "r3900".
294
cccc84fa
MR		 2952021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
296
297 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
298 and "mtthc2" to using the `G' rather than `g' operand code for
299 the coprocessor control register referred.
300
c9de3168
MR		 3012021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
302
303 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
304 entries with each other.
305
ebcab741
PB		 3062021-05-27 Peter Bergner <bergner@linux.ibm.com>
307
308 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
309
bc30a119
AM		 3102021-05-25 Alan Modra <amodra@gmail.com>
311
312 * cris-desc.c: Regenerate.
313 * cris-desc.h: Regenerate.
314 * cris-opc.h: Regenerate.
315 * po/POTFILES.in: Regenerate.
316
54711280
MF		 3172021-05-24 Mike Frysinger <vapier@gentoo.org>
318
319 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
320 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
321 (CGEN_CPUS): Add cris.
322 (CRIS_DEPS): Define.
323 (stamp-cris): New rule.
324 * cgen.sh: Handle desc action.
325 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
326 * Makefile.in, configure: Regenerate.
327
113bb761
JN		 3282021-05-18 Job Noorman <mtvec@pm.me>
329
330 PR 27814
331 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
332 the elf objects.
333
e683cb41
AC		 3342021-05-17 Alex Coplan <alex.coplan@arm.com>
335
336 * arm-dis.c (mve_opcodes): Fix disassembly of
337 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
338 (is_mve_encoding_conflict): MVE vector loads should not match
339 when P = W = 0.
340 (is_mve_unpredictable): It's not unpredictable to use the same
341 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
342
a680affc
NC		 3432021-05-11 Nick Clifton <nickc@redhat.com>
344
345 PR 27840
346 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
347 the end of the code buffer.
348
0b3e14c9
SH		 3492021-05-06 Stafford Horne <shorne@gmail.com>
350
351 PR 21464
352 * or1k-asm.c: Regenerate.
353
6aee2cb2
MF		 3542021-05-01 Max Filippov <jcmvbkbc@gmail.com>
355
356 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
357 info->insn_info_valid.
358
fe134c65
JB		 3592021-04-26 Jan Beulich <jbeulich@suse.com>
360
361 * i386-opc.tbl (lea): Add Optimize.
362 * opcodes/i386-tbl.h: Re-generate.
363
b3ea7639
MF		 3642020-04-23 Max Filippov <jcmvbkbc@gmail.com>
365
366 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
367 of l32r fetch and display referenced literal value.
368
c1cbb7d8
MF		 3692021-04-23 Max Filippov <jcmvbkbc@gmail.com>
370
371 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
372 to 4 for literal disassembly.
373
02202574
PW		 3742021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
375
376 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
377 for TLBI instruction.
378
cd6608e4
PW		 3792021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
380
381 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
382 DC instruction.
383
fe1640ff
JB		 3842021-04-19 Jan Beulich <jbeulich@suse.com>
385
386 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
387 "qualifier".
388 (convert_mov_to_movewide): Add initializer for "value".
389
100e914d
PW		 3902021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
391
392 * aarch64-opc.c: Add RME system registers.
393
a21b96dd
NC		 3942021-04-16 Lifang Xia <lifang_xia@c-sky.com>
395
396 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
397 "addi d,CV,z" to "c.mv d,CV".
398
43e05cd4
AM		 3992021-04-12 Alan Modra <amodra@gmail.com>
400
401 * configure.ac (--enable-checking): Add support.
402 * config.in: Regenerate.
403 * configure: Regenerate.
404
52efda82
TB		 4052021-04-09 Tejas Belagod <tejas.belagod@arm.com>
406
407 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
408 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
409
c3f72de4
AM		 4102021-04-09 Alan Modra <amodra@gmail.com>
411
412 * ppc-dis.c (struct dis_private): Add "special".
413 (POWERPC_DIALECT): Delete. Replace uses with..
414 (private_data): ..this. New inline function.
415 (disassemble_init_powerpc): Init "special" names.
416 (skip_optional_operands): Add is_pcrel arg, set when detecting R
417 field of prefix instructions.
418 (bsearch_reloc, print_got_plt): New functions.
419 (print_insn_powerpc): For pcrel instructions, print target address
420 and symbol if known, and decode plt and got loads too.
421
ce7d813a
AM		 4222021-04-08 Alan Modra <amodra@gmail.com>
423
424 PR 27684
425 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
426
97bf40d8
AM		 4272021-04-08 Alan Modra <amodra@gmail.com>
428
429 PR 27676
430 * ppc-opc.c (DCBT_EO): Move earlier.
431 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
432 (powerpc_operands): Add THCT and THDS entries.
433 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
434
a2e66773
AM		 4352021-04-06 Alan Modra <amodra@gmail.com>
436
437 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
438 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
439 symbol_at_address_func.
440
ab2af25e
AM		 4412021-04-05 Alan Modra <amodra@gmail.com>
442
443 * configure.ac: Don't check for limits.h, string.h, strings.h or
444 stdlib.h.
445 (AC_ISC_POSIX): Don't invoke.
446 * sysdep.h: Include stdlib.h and string.h unconditionally.
447 * i386-opc.h: Include limits.h unconditionally.
448 * wasm32-dis.c: Likewise.
449 * cgen-opc.c: Don't include alloca-conf.h.
450 * config.in: Regenerate.
451 * configure: Regenerate.
452
e9b095a5
ML		 4532021-04-01 Martin Liska <mliska@suse.cz>
454
455 * arm-dis.c (strneq): Remove strneq and use startswith.
456 * cr16-dis.c (print_insn_cr16): Likewise.
457 * score-dis.c (streq): Likewise.
458 (strneq): Likewise.
459 * score7-dis.c (strneq): Likewise.
460
1cb108e4
AM		 4612021-04-01 Alan Modra <amodra@gmail.com>
462
463 PR 27675
464 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
465
78933a4a
AM		 4662021-03-31 Alan Modra <amodra@gmail.com>
467
468 * sysdep.h (POISON_BFD_BOOLEAN): Define.
469 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
470 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
471 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
472 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
473 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
474 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
475 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
476 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
477 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
478 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
479 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
480 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
481 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
482 and TRUE with true throughout.
483
3dfb1b6d
AM		 4842021-03-31 Alan Modra <amodra@gmail.com>
485
486 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
487 * aarch64-dis.h: Likewise.
488 * aarch64-opc.c: Likewise.
489 * avr-dis.c: Likewise.
490 * csky-dis.c: Likewise.
491 * nds32-asm.c: Likewise.
492 * nds32-dis.c: Likewise.
493 * nfp-dis.c: Likewise.
494 * riscv-dis.c: Likewise.
495 * s12z-dis.c: Likewise.
496 * wasm32-dis.c: Likewise.
497
5e042380
JB		 4982021-03-30 Jan Beulich <jbeulich@suse.com>
499
500 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
501 (i386_seg_prefixes): New.
502 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
503 (i386_seg_prefixes): Declare.
504
34684862
JB		 5052021-03-30 Jan Beulich <jbeulich@suse.com>
506
507 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
508
6288d05f
JB		 5092021-03-30 Jan Beulich <jbeulich@suse.com>
510
511 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
512 * i386-reg.tbl (st): Move down.
513 (st(0)): Delete. Extend comment.
514 * i386-tbl.h: Re-generate.
515
bbe1eca6
JB		 5162021-03-29 Jan Beulich <jbeulich@suse.com>
517
518 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
519 (cmpsd): Move next to cmps.
520 (movsd): Move next to movs.
521 (cmpxchg16b): Move to separate section.
522 (fisttp, fisttpll): Likewise.
523 (monitor, mwait): Likewise.
524 * i386-tbl.h: Re-generate.
525
c8cad9d3
JB		 5262021-03-29 Jan Beulich <jbeulich@suse.com>
527
528 * i386-opc.tbl (psadbw): Add <sse2:comm>.
529 (vpsadbw): Add C.
530 * i386-tbl.h: Re-generate.
531
5cdaf100
JB		 5322021-03-29 Jan Beulich <jbeulich@suse.com>
533
534 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
535 pclmul, gfni): New templates. Use them wherever possible. Move
536 SSE4.1 pextrw into respective section.
537 * i386-tbl.h: Re-generate.
538
73e45eb2
JB		 5392021-03-29 Jan Beulich <jbeulich@suse.com>
540
541 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
542 strtoull(). Bump upper loop bound. Widen masks. Sanity check
543 "length".
544 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
545 Convert all of their uses to representation in opcode.
546
9df6f676
JB		 5472021-03-29 Jan Beulich <jbeulich@suse.com>
548
549 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
550 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
551 value of None. Shrink operands to 3 bits.
552
389d00a5
JB		 5532021-03-29 Jan Beulich <jbeulich@suse.com>
554
555 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 556 "space".
389d00a5
JB		 557 (output_i386_opcode): New local variable "space". Adjust
558 process_i386_opcode_modifier() invocation.
559 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
560 invocation.
561 * i386-tbl.h: Re-generate.
562
63b4cc53
AM		 5632021-03-29 Alan Modra <amodra@gmail.com>
564
565 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
566 (fp_qualifier_p, get_data_pattern): Likewise.
567 (aarch64_get_operand_modifier_from_value): Likewise.
568 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
569 (operand_variant_qualifier_p): Likewise.
570 (qualifier_value_in_range_constraint_p): Likewise.
571 (aarch64_get_qualifier_esize): Likewise.
572 (aarch64_get_qualifier_nelem): Likewise.
573 (aarch64_get_qualifier_standard_value): Likewise.
574 (get_lower_bound, get_upper_bound): Likewise.
575 (aarch64_find_best_match, match_operands_qualifier): Likewise.
576 (aarch64_print_operand): Likewise.
577 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
578 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
579 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
580 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
581 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
582 (print_insn_tic6x): Likewise.
583
3d7d6c1b
AM		 5842021-03-29 Alan Modra <amodra@gmail.com>
585
586 * arc-dis.c (extract_operand_value): Correct NULL cast.
587 * frv-opc.h: Regenerate.
588
c3344b62
JB		 5892021-03-26 Jan Beulich <jbeulich@suse.com>
590
591 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
592 MMX form.
593 * i386-tbl.h: Re-generate.
594
efa30ac3
HAQ		 5952021-03-25 Abid Qadeer <abidh@codesourcery.com>
596
597 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
598 immediate in br.n instruction.
599
596a02ff
JB		 6002021-03-25 Jan Beulich <jbeulich@suse.com>
601
602 * i386-dis.c (XMGatherD, VexGatherD): New.
603 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
604 (print_insn): Check masking for S/G insns.
605 (OP_E_memory): New local variable check_gather. Extend mandatory
606 SIB check. Check register conflicts for (EVEX-encoded) gathers.
607 Extend check for disallowed 16-bit addressing.
608 (OP_VEX): New local variables modrm_reg and sib_index. Convert
609 if()s to switch(). Check register conflicts for (VEX-encoded)
610 gathers. Drop no longer reachable cases.
611 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
612 vgatherdp*.
613
53642852
JB		 6142021-03-25 Jan Beulich <jbeulich@suse.com>
615
616 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
617 zeroing-masking without masking.
618
c0e54661
JB		 6192021-03-25 Jan Beulich <jbeulich@suse.com>
620
621 * i386-opc.tbl (invlpgb): Fix multi-operand form.
622 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
623 single-operand forms as deprecated.
624 * i386-tbl.h: Re-generate.
625
5a403766
AM		 6262021-03-25 Alan Modra <amodra@gmail.com>
627
628 PR 27647
629 * ppc-opc.c (XLOCB_MASK): Delete.
630 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
631 XLBH_MASK.
632 (powerpc_opcodes): Accept a BH field on all extended forms of
633 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
634
9a182d04
JB		 6352021-03-24 Jan Beulich <jbeulich@suse.com>
636
637 * i386-gen.c (output_i386_opcode): Drop processing of
638 opcode_length. Calculate length from base_opcode. Adjust prefix
639 encoding determination.
640 (process_i386_opcodes): Drop output of fake opcode_length.
641 * i386-opc.h (struct insn_template): Drop opcode_length field.
642 * i386-opc.tbl: Drop opcode length field from all templates.
643 * i386-tbl.h: Re-generate.
644
35648716
JB		 6452021-03-24 Jan Beulich <jbeulich@suse.com>
646
647 * i386-gen.c (process_i386_opcode_modifier): Return void. New
648 parameter "prefix". Drop local variable "regular_encoding".
649 Record prefix setting / check for consistency.
650 (output_i386_opcode): Parse opcode_length and base_opcode
651 earlier. Derive prefix encoding. Drop no longer applicable
652 consistency checking. Adjust process_i386_opcode_modifier()
653 invocation.
654 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
655 invocation.
656 * i386-tbl.h: Re-generate.
657
31184569
JB		 6582021-03-24 Jan Beulich <jbeulich@suse.com>
659
660 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
661 check.
662 * i386-opc.h (Prefix_*): Move #define-s.
663 * i386-opc.tbl: Move pseudo prefix enumerator values to
664 extension opcode field. Introduce pseudopfx template.
665 * i386-tbl.h: Re-generate.
666
b933fa4b
JB		 6672021-03-23 Jan Beulich <jbeulich@suse.com>
668
669 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
670 comment.
671 * i386-tbl.h: Re-generate.
672
dac10fb0
JB		 6732021-03-23 Jan Beulich <jbeulich@suse.com>
674
675 * i386-opc.h (struct insn_template): Move cpu_flags field past
676 opcode_modifier one.
677 * i386-tbl.h: Re-generate.
678
441f6aca
JB		 6792021-03-23 Jan Beulich <jbeulich@suse.com>
680
681 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
682 * i386-opc.h (OpcodeSpace): New enumerator.
683 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
684 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
685 SPACE_XOP09, SPACE_XOP0A): ... respectively.
686 (struct i386_opcode_modifier): New field opcodespace. Shrink
687 opcodeprefix field.
688 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
689 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
690 OpcodePrefix uses.
691 * i386-tbl.h: Re-generate.
692
08dedd66
ML		 6932021-03-22 Martin Liska <mliska@suse.cz>
694
695 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
696 * arc-dis.c (parse_option): Likewise.
697 * arm-dis.c (parse_arm_disassembler_options): Likewise.
698 * cris-dis.c (print_with_operands): Likewise.
699 * h8300-dis.c (bfd_h8_disassemble): Likewise.
700 * i386-dis.c (print_insn): Likewise.
701 * ia64-gen.c (fetch_insn_class): Likewise.
702 (parse_resource_users): Likewise.
703 (in_iclass): Likewise.
704 (lookup_specifier): Likewise.
705 (insert_opcode_dependencies): Likewise.
706 * mips-dis.c (parse_mips_ase_option): Likewise.
707 (parse_mips_dis_option): Likewise.
708 * s390-dis.c (disassemble_init_s390): Likewise.
709 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
710
80d49d6a
KLC		 7112021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
712
713 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
714
7fce7ea9
PW		 7152021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
716
717 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
718 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
719
78c84bf9
AM		 7202021-03-12 Alan Modra <amodra@gmail.com>
721
722 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
723
fd1fd061
JB		 7242021-03-11 Jan Beulich <jbeulich@suse.com>
725
726 * i386-dis.c (OP_XMM): Re-order checks.
727
ac7a2311
JB		 7282021-03-11 Jan Beulich <jbeulich@suse.com>
729
730 * i386-dis.c (putop): Drop need_vex check when also checking
731 vex.evex.
732 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
733 checking vex.b.
734
da944c8a
JB		 7352021-03-11 Jan Beulich <jbeulich@suse.com>
736
737 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
738 checks. Move case label past broadcast check.
739
b763d508
JB		 7402021-03-10 Jan Beulich <jbeulich@suse.com>
741
742 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
743 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
744 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
745 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
746 EVEX_W_0F38C7_M_0_L_2): Delete.
747 (REG_EVEX_0F38C7_M_0_L_2): New.
748 (intel_operand_size): Handle VEX and EVEX the same for
749 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
750 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
751 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
752 vex_vsib_q_w_d_mode uses.
753 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
754 0F38A1, and 0F38A3 entries.
755 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
756 entry.
757 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
758 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
759 0F38A3 entries.
760
32e31ad7
JB		 7612021-03-10 Jan Beulich <jbeulich@suse.com>
762
763 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
764 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
765 MOD_VEX_0FXOP_09_12): Rename to ...
766 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
767 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
768 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
769 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
770 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
771 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
772 (reg_table): Adjust comments.
773 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
774 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
775 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
776 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
777 (vex_len_table): Adjust opcode 0A_12 entry.
778 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
779 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
780 (rm_table): Move hreset entry.
781
85ba7507
JB		 7822021-03-10 Jan Beulich <jbeulich@suse.com>
783
784 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
785 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
786 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
787 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
788 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
789 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
790 (get_valid_dis386): Also handle 512-bit vector length when
791 vectoring into vex_len_table[].
792 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
793 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
794 entries.
795 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
796 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
797 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
798 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
799 entries.
800
066f82b9
JB		 8012021-03-10 Jan Beulich <jbeulich@suse.com>
802
803 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
804 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
805 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
806 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
807 entries.
808 * i386-dis-evex-len.h (evex_len_table): Likewise.
809 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
810
fc681dd6
JB		 8112021-03-10 Jan Beulich <jbeulich@suse.com>
812
813 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
814 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
815 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
816 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
817 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
818 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
819 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
820 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
821 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
822 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
823 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
824 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
825 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
826 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
827 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
828 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
829 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
830 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
831 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
832 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
833 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
834 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
835 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
836 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
837 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
838 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
839 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
840 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
841 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
842 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
843 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
844 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
845 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
846 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
847 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
848 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
849 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
850 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
851 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
852 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
853 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
854 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
855 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
856 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
857 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
858 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
859 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
860 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
861 EVEX_W_0F3A43_L_n): New.
862 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
863 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
864 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
865 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
866 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
867 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
868 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
869 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
870 0F385B, 0F38C6, and 0F38C7 entries.
871 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
872 0F38C6 and 0F38C7.
873 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
874 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
875 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
876 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
877
13954a31
JB		 8782021-03-10 Jan Beulich <jbeulich@suse.com>
879
880 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
881 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
882 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
883 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
884 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
885 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
886 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
887 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
888 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
889 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
890 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
891 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
892 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
893 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
894 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
895 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
896 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
897 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
898 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
899 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
900 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
901 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
902 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
903 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
904 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
905 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
906 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
907 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
908 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
909 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
910 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
911 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
912 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
913 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
914 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
915 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
916 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
917 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
918 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
919 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
920 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
921 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
922 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
923 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
924 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
925 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
926 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
927 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
928 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
929 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
930 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
931 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
932 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
933 VEX_W_0F99_P_2_LEN_0): Delete.
934 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
935 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
936 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
937 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
938 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
939 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
940 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
941 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
942 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
943 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
944 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
945 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
946 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
947 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
948 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
949 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
950 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
951 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
952 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
953 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
954 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
955 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
956 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
957 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
958 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
959 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
960 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
961 (prefix_table): No longer link to vex_len_table[] for opcodes
962 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
963 0F92, 0F93, 0F98, and 0F99.
964 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
965 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
966 0F98, and 0F99.
967 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
968 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
969 0F98, and 0F99.
970 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
971 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
972 0F98, and 0F99.
973 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
974 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
975 0F98, and 0F99.
976
14d10c6c
JB		 9772021-03-10 Jan Beulich <jbeulich@suse.com>
978
979 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
980 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
981 REG_VEX_0F73_M_0 respectively.
982 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
983 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
984 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
985 MOD_VEX_0F73_REG_7): Delete.
986 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
987 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
988 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
989 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
990 PREFIX_VEX_0F3AF0_L_0 respectively.
991 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
992 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
993 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
994 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
995 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
996 VEX_LEN_0F38F7): New.
997 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
998 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
999 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1000 0F38F3.
1001 (prefix_table): No longer link to vex_len_table[] for opcodes
1002 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1003 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1004 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1005 0F38F6, 0F38F7, and 0F3AF0.
1006 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1007 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1008 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1009 0F73.
1010
00ec1875
JB		 10112021-03-10 Jan Beulich <jbeulich@suse.com>
1012
1013 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1014 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1015 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1016 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1017 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1018 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1019 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1020 73.
1021 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1022 0F72, and 0F73.
1023 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1024 0F73.
1025
31941983
JB		 10262021-03-10 Jan Beulich <jbeulich@suse.com>
1027
1028 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1029 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1030 (reg_table): Don't link to mod_table[] where not needed. Add
1031 PREFIX_IGNORED to nop entries.
1032 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1033 (mod_table): Add nop entries next to prefetch ones. Drop
1034 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1035 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1036 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1037 PREFIX_OPCODE from endbr* entries.
1038 (get_valid_dis386): Also consider entry's name when zapping
1039 vindex.
1040 (print_insn): Handle PREFIX_IGNORED.
1041
742732c7
JB		 10422021-03-09 Jan Beulich <jbeulich@suse.com>
1043
1044 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1045 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1046 element.
1047 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1048 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1049 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1050 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1051 (struct i386_opcode_modifier): Delete notrackprefixok,
1052 islockable, hleprefixok, and repprefixok fields. Add prefixok
1053 field.
1054 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1055 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1056 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1057 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1058 Replace HLEPrefixOk.
1059 * opcodes/i386-tbl.h: Re-generate.
1060
e93a3b27
JB		 10612021-03-09 Jan Beulich <jbeulich@suse.com>
1062
1063 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1064 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1065 64-bit form.
1066 * opcodes/i386-tbl.h: Re-generate.
1067
75363b6d
JB		 10682021-03-03 Jan Beulich <jbeulich@suse.com>
1069
1070 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1071 for {} instead of {0}. Don't look for '0'.
1072 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1073 size specifiers.
1074
5a9f5403
NC		 10752021-02-19 Nelson Chu <nelson.chu@sifive.com>
1076
1077 PR 27158
1078 * riscv-dis.c (print_insn_args): Updated encoding macros.
1079 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1080 (match_c_addi16sp): Updated encoding macros.
1081 (match_c_lui): Likewise.
1082 (match_c_lui_with_hint): Likewise.
1083 (match_c_addi4spn): Likewise.
1084 (match_c_slli): Likewise.
1085 (match_slli_as_c_slli): Likewise.
1086 (match_c_slli64): Likewise.
1087 (match_srxi_as_c_srxi): Likewise.
1088 (riscv_insn_types): Added .insn css/cl/cs.
1089
3d73d29e
NC		 10902021-02-18 Nelson Chu <nelson.chu@sifive.com>
1091
1092 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1093 (default_priv_spec): Updated type to riscv_spec_class.
1094 (parse_riscv_dis_option): Updated.
1095 * riscv-opc.c: Moved stuff and make the file tidy.
1096
b9b204b3
AM		 10972021-02-17 Alan Modra <amodra@gmail.com>
1098
1099 * wasm32-dis.c: Include limits.h.
1100 (CHAR_BIT): Provide backup define.
1101 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1102 Correct signed overflow checking.
1103
394ae71f
JB		 11042021-02-16 Jan Beulich <jbeulich@suse.com>
1105
1106 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1107 * i386-tbl.h: Re-generate.
1108
b818b220
JB		 11092021-02-16 Jan Beulich <jbeulich@suse.com>
1110
1111 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1112 Oword.
1113 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1114
ba2b480f
AK		 11152021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1116
1117 * s390-mkopc.c (main): Accept arch14 as cpu string.
1118 * s390-opc.txt: Add new arch14 instructions.
1119
95148614
NA		 11202021-02-04 Nick Alcock <nick.alcock@oracle.com>
1121
1122 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1123 favour of LIBINTL.
1124 * configure: Regenerated.
1125
bfd428bc
MF		 11262021-02-08 Mike Frysinger <vapier@gentoo.org>
1127
1128 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1129 * tic54x-opc.c (regs): Rename to ...
1130 (tic54x_regs): ... this.
1131 (mmregs): Rename to ...
1132 (tic54x_mmregs): ... this.
1133 (condition_codes): Rename to ...
1134 (tic54x_condition_codes): ... this.
1135 (cc2_codes): Rename to ...
1136 (tic54x_cc2_codes): ... this.
1137 (cc3_codes): Rename to ...
1138 (tic54x_cc3_codes): ... this.
1139 (status_bits): Rename to ...
1140 (tic54x_status_bits): ... this.
1141 (misc_symbols): Rename to ...
1142 (tic54x_misc_symbols): ... this.
1143
24075dcc
NC		 11442021-02-04 Nelson Chu <nelson.chu@sifive.com>
1145
1146 * riscv-opc.c (MASK_RVB_IMM): Removed.
1147 (riscv_opcodes): Removed zb* instructions.
1148 (riscv_ext_version_table): Removed versions for zb*.
1149
c3ffb8f3
AM		 11502021-01-26 Alan Modra <amodra@gmail.com>
1151
1152 * i386-gen.c (parse_template): Ensure entire template_instance
1153 is initialised.
1154
1942a048
NC		 11552021-01-15 Nelson Chu <nelson.chu@sifive.com>
1156
1157 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1158 (riscv_fpr_names_abi): Likewise.
1159 (riscv_opcodes): Likewise.
1160 (riscv_insn_types): Likewise.
1161
b800637e
NC		 11622021-01-15 Nelson Chu <nelson.chu@sifive.com>
1163
1164 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1165
dcd709e0
NC		 11662021-01-15 Nelson Chu <nelson.chu@sifive.com>
1167
1168 * riscv-dis.c: Comments tidy and improvement.
1169 * riscv-opc.c: Likewise.
1170
5347ed60
AM		 11712021-01-13 Alan Modra <amodra@gmail.com>
1172
1173 * Makefile.in: Regenerate.
1174
d546b610
L		 11752021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1176
1177 PR binutils/26792
1178 * configure.ac: Use GNU_MAKE_JOBSERVER.
1179 * aclocal.m4: Regenerated.
1180 * configure: Likewise.
1181
6d104cac
NC		 11822021-01-12 Nick Clifton <nickc@redhat.com>
1183
1184 * po/sr.po: Updated Serbian translation.
1185
83b33c6c
L		 11862021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1187
1188 PR ld/27173
1189 * configure: Regenerated.
1190
82c70b08
KT		 11912021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1192
1193 * aarch64-asm-2.c: Regenerate.
1194 * aarch64-dis-2.c: Likewise.
1195 * aarch64-opc-2.c: Likewise.
1196 * aarch64-opc.c (aarch64_print_operand):
1197 Delete handling of AARCH64_OPND_CSRE_CSR.
1198 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1199 (CSRE): Likewise.
1200 (_CSRE_INSN): Likewise.
1201 (aarch64_opcode_table): Delete csr.
1202
a8aa72b9
NC		 12032021-01-11 Nick Clifton <nickc@redhat.com>
1204
1205 * po/de.po: Updated German translation.
1206 * po/fr.po: Updated French translation.
1207 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1208 * po/sv.po: Updated Swedish translation.
1209 * po/uk.po: Updated Ukranian translation.
1210
a4966cd9
L		 12112021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1212
1213 * configure: Regenerated.
1214
573fe3fb
NC		 12152021-01-09 Nick Clifton <nickc@redhat.com>
1216
1217 * configure: Regenerate.
1218 * po/opcodes.pot: Regenerate.
1219
055bc77a
NC		 12202021-01-09 Nick Clifton <nickc@redhat.com>
1221
1222 * 2.36 release branch crated.
1223
aae7fcb8
PB		 12242021-01-08 Peter Bergner <bergner@linux.ibm.com>
1225
1226 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1227 (DW, (XRC_MASK): Define.
1228 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1229
64307045
AM		 12302021-01-09 Alan Modra <amodra@gmail.com>
1231
1232 * configure: Regenerate.
1233
ed205222
NC		 12342021-01-08 Nick Clifton <nickc@redhat.com>
1235
1236 * po/sv.po: Updated Swedish translation.
1237
fb932b57
NC		 12382021-01-08 Nick Clifton <nickc@redhat.com>
1239
e84c8716
NC		 1240 PR 27129
1241 * aarch64-dis.c (determine_disassembling_preference): Move call to
1242 aarch64_match_operands_constraint outside of the assertion.
1243 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1244 Replace with a return of FALSE.
1245
fb932b57
NC		 1246 PR 27139
1247 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1248 core system register.
1249
f4782128
ST		 12502021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1251
1252 * configure: Regenerate.
1253
1b0927db
NC		 12542021-01-07 Nick Clifton <nickc@redhat.com>
1255
1256 * po/fr.po: Updated French translation.
1257
3b288c8e
FN		 12582021-01-07 Fredrik Noring <noring@nocrew.org>
1259
1260 * m68k-opc.c (chkl): Change minimum architecture requirement to
1261 m68020.
1262
aa881ecd
PT		 12632021-01-07 Philipp Tomsich <prt@gnu.org>
1264
1265 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1266
2652cfad
CXW		 12672021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1268 Jim Wilson <jimw@sifive.com>
1269 Andrew Waterman <andrew@sifive.com>
1270 Maxim Blinov <maxim.blinov@embecosm.com>
1271 Kito Cheng <kito.cheng@sifive.com>
1272 Nelson Chu <nelson.chu@sifive.com>
1273
1274 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1275 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1276
250d07de
AM		 12772021-01-01 Alan Modra <amodra@gmail.com>
1278
1279 Update year range in copyright notice of all files.
1280
c2795844 1281For older changes see ChangeLog-2020
3499769a 1282\f
a2c58332 1283Copyright (C) 2021-2022 Free Software Foundation, Inc.
3499769a
AM		 1284
1285Copying and distribution of this file, with or without modification,
1286are permitted in any medium without royalty provided the copyright
1287notice and this notice are preserved.
1288
1289Local Variables:
1290mode: change-log
1291left-margin: 8
1292fill-column: 74
1293version-control: never
1294End:
A mirror of the official binutils-gdb repository