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Add support for MIPS R6.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
7361da2c
AB		 12014-09-15 Andrew Bennett <andrew.bennett@imgtec.com>
2 Matthew Fortune <matthew.fortune@imgtec.com>
3
4 * mips-dis.c (mips_arch_choices): Add entries for mips32r6 and
5 mips64r6.
6 (parse_mips_dis_option): Allow MSA and virtualization support for
7 mips64r6.
8 (mips_print_arg_state): Add fields dest_regno and seen_dest.
9 (mips_seen_register): New function.
10 (print_insn_arg): Refactored code to use mips_seen_register
11 function. Add support for OP_SAME_RS_RT, OP_CHECK_PREV and
12 OP_NON_ZERO_REG. Changed OP_REPEAT_DEST_REG case to print out
13 the register rather than aborting.
14 (print_insn_args): Add length argument. Add code to correctly
15 calculate the instruction address for pc relative instructions.
16 (validate_insn_args): New static function.
17 (print_insn_mips): Prevent jalx disassembling for r6. Use
18 validate_insn_args.
19 (print_insn_micromips): Use validate_insn_args.
20 all the arguments are valid.
21 * mips-formats.h (PREV_CHECK): New define.
22 * mips-opc.c (decode_mips_operand): Add support for -a, -b, -d, -s,
23 -t, -u, -v, -w, -x, -y, -A, -B, +I, +O, +R, +:, +\, +", +;
24 (RD_pc): New define.
25 (FS): New define.
26 (I37): New define.
27 (I69): New define.
28 (mips_builtin_opcodes): Add MIPS R6 instructions. Exclude recoded
29 MIPS R6 instructions from MIPS R2 instructions.
30
4b4c407a
L		 312014-09-10 H.J. Lu <hongjiu.lu@intel.com>
32
33 * i386-dis.c (dis386): Replace "P" with "%LP" for iret and sysret.
34 (putop): Handle "%LP".
35
df7b4545
JW		 362014-09-03 Jiong Wang <jiong.wang@arm.com>
37
38 * aarch64-tbl.h (aarch64_opcode_table): Update encoding for mrs/msr.
39 * aarch64-dis-2.c: Update auto-generated file.
40
ee804238
JW		 412014-09-03 Jiong Wang <jiong.wang@arm.com>
42
43 * aarch64-tbl.h (QL_R4NIL): New qualifiers.
44 (aarch64_feature_lse): New feature added.
45 (LSE): New Added.
46 (aarch64_opcode_table): New LSE instructions added. Improve
47 descriptions for ldarb/ldarh/ldar.
48 (aarch64_opcode_table): Describe PAIRREG.
49 * aarch64-opc.h (aarch64_field_kind): Add FLD_lse_sz.
50 * aarch64-opc.c (fields): Add entry for F_LSE_SZ.
51 (aarch64_print_operand): Recognize PAIRREG.
52 (operand_general_constraint_met_p): Check reg pair constraints for CASP
53 instructions.
54 * aarch64-dis.c (aarch64_ext_regno_pair): New extractor for paired reg.
55 (do_special_decoding): Recognize F_LSE_SZ.
56 * aarch64-asm.c (do_special_encoding): Recognize F_LSE_SZ.
57
5575639b
MR		 582014-08-26 Maciej W. Rozycki <macro@codesourcery.com>
59
60 * micromips-opc.c (decode_micromips_operand): Rename `B' to `+J'.
61 (micromips_opcodes): Use "+J" in place of "B" for "hypcall",
62 "sdbbp", "syscall" and "wait".
63
84919466
MR		 642014-08-21 Nathan Sidwell <nathan@codesourcery.com>
65 Maciej W. Rozycki <macro@codesourcery.com>
66
67 * arm-dis.c (print_arm_address): Negate the GPR-relative offset
68 returned if the U bit is set.
69
a6c70539
MR		 702014-08-21 Maciej W. Rozycki <macro@codesourcery.com>
71
72 * micromips-opc.c (micromips_opcodes): Remove #ifdef-ed out
73 48-bit "li" encoding.
74
9ace48f3
AA		 752014-08-19 Andreas Arnez <arnez@linux.vnet.ibm.com>
76
77 * s390-dis.c (s390_insn_length, s390_insn_matches_opcode)
78 (s390_print_insn_with_opcode, opcode_mask_more_specific): New
79 static functions, code was moved from...
80 (print_insn_s390): ...here.
81 (s390_extract_operand): Adjust comment. Change type of first
82 parameter from 'unsigned char *' to 'const bfd_byte *'.
83 (union operand_value): New.
84 (s390_extract_operand): Change return type to union operand_value.
85 Also avoid integer overflow in sign-extension.
86 (s390_print_insn_with_opcode): Adjust to changed return value from
87 s390_extract_operand(). Change "%i" printf format to "%u" for
88 unsigned values.
89 (init_disasm): Simplify initialization of opc_index[]. This also
90 fixes an access after the last element of s390_opcodes[].
91 (print_insn_s390): Simplify the opcode search loop.
92 Check architecture mask against all searched opcodes, not just the
93 first matching one.
94 (s390_print_insn_with_opcode): Drop function pointer dereferences
95 without effect.
96 (print_insn_s390): Likewise.
97 (s390_insn_length): Simplify formula for return value.
98 (s390_print_insn_with_opcode): Avoid special handling for the
99 separator before the first operand. Use new local variable
100 'flags' in place of 'operand->flags'.
101
60ac5798
MF		 1022014-08-14 Mike Frysinger <vapier@gentoo.org>
103
104 * bfin-dis.c (struct private): Change int's to bfd_boolean's.
105 (decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
106 decode_dagMODik_0, decode_LDIMMhalf_0, decode_linkage_0):
107 Change assignment of 1 to priv->comment to TRUE.
108 (print_insn_bfin): Change legal to a bfd_boolean. Change
109 assignment of 0/1 with priv comment and parallel and legal
110 to FALSE/TRUE.
111
b3f3b4b0
MF		 1122014-08-14 Mike Frysinger <vapier@gentoo.org>
113
114 * bfin-dis.c (OUT): Define.
115 (decode_CC2stat_0): Declare new op_names array.
116 Replace multiple if statements with a single one.
117
a4e600b2
MF		 1182014-08-14 Mike Frysinger <vapier@gentoo.org>
119
120 * bfin-dis.c (struct private): Add iw0.
121 (_print_insn_bfin): Assign iw0 to priv.iw0.
122 (print_insn_bfin): Drop ifetch and use priv.iw0.
123
703ec4e8
MF		 1242014-08-13 Mike Frysinger <vapier@gentoo.org>
125
126 * bfin-dis.c (comment, parallel): Move from global scope ...
127 (struct private): ... to this new struct.
128 (decode_ProgCtrl_0, decode_CaCTRL_0, decode_PushPopReg_0,
129 decode_PushPopMultiple_0, decode_ccMV_0, decode_CCflag_0,
130 decode_CC2dreg_0, decode_CC2stat_0, decode_BRCC_0, decode_UJUMP_0,
131 decode_LOGI2op_0, decode_COMPI2opD_0, decode_COMPI2opP_0,
132 decode_dagMODik_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
133 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
134 decode_pseudoOChar_0, decode_pseudodbg_assert_0, _print_insn_bfin,
135 print_insn_bfin): Declare private struct. Use priv's comment and
136 parallel members.
137
ed2c4879
MF		 1382014-08-13 Mike Frysinger <vapier@gentoo.org>
139
140 * bfin-dis.c (ifetch): Do not align pc to 2 bytes.
141 (_print_insn_bfin): Add check for unaligned pc.
142
ba329817
MF		 1432014-08-13 Mike Frysinger <vapier@gentoo.org>
144
145 * bfin-dis.c (ifetch): New function.
146 (_print_insn_bfin, print_insn_bfin): Call new ifetch and return
147 -1 when it errors.
148
43885403
MF		 1492014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
150
151 * micromips-opc.c (COD): Rename throughout to...
152 (CM): New define, update to use INSN_COPROC_MOVE.
153 (LCD): Rename throughout to...
154 (LC): New define, update to use INSN_LOAD_COPROC.
155 * mips-opc.c: Likewise.
156
351cdf24
MF		 1572014-07-29 Matthew Fortune <matthew.fortune@imgtec.com>
158
159 * micromips-opc.c (COD, LCD) New macros.
160 (cfc1, ctc1): Remove FP_S attribute.
161 (dmfc1, mfc1, mfhc1): Add LCD attribute.
162 (dmtc1, mtc1, mthc1): Add COD attribute.
163 * mips-opc.c (cfc1, cftc1, ctc, cttc1): Remove FP_S attribute.
164
90a915bf
IT		 1652014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
166 Alexander Ivchenko <alexander.ivchenko@intel.com>
167 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
168 Sergey Lega <sergey.s.lega@intel.com>
169 Anna Tikhonova <anna.tikhonova@intel.com>
170 Ilya Tocar <ilya.tocar@intel.com>
171 Andrey Turetskiy <andrey.turetskiy@intel.com>
172 Ilya Verbin <ilya.verbin@intel.com>
173 Kirill Yukhin <kirill.yukhin@intel.com>
174 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
175
176 * i386-dis-evex.h: Updated.
177 * i386-dis.c (PREFIX enum): Add PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
178 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0F3A16,
179 PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A50, PREFIX_EVEX_0F3A51,
180 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
181 PREFIX_EVEX_0F3A67.
182 (VEX_LEN enum): Add VEX_LEN_0F92_P_2, VEX_LEN_0F93_P_2,
183 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_2_LEN_0.
184 (VEX_W enum): Add EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
185 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2, EVEX_W_0F57_P_0,
186 EVEX_W_0F57_P_2, EVEX_W_0F78_P_2, EVEX_W_0F79_P_2, EVEX_W_0F7A_P_2,
187 EVEX_W_0F7B_P_2, EVEX_W_0F3838_P_1, EVEX_W_0F3839_P_1,
188 EVEX_W_0F3A16_P_2, EVEX_W_0F3A22_P_2, EVEX_W_0F3A50_P_2,
189 EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2, EVEX_W_0F3A57_P_2,
190 EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2.
191 (prefix_table): Add entries for new instructions.
192 (vex_len_table): Ditto.
193 (vex_w_table): Ditto.
194 (OP_E_memory): Update xmmq_mode handling.
195 * i386-gen.c (cpu_flag_init): Add CPU_AVX512DQ_FLAGS.
196 (cpu_flags): Add CpuAVX512DQ.
197 * i386-init.h: Regenerared.
198 * i386-opc.h (CpuAVX512DQ): New.
199 (i386_cpu_flags): Add cpuavx512dq.
200 * i386-opc.tbl: Add AVX512DQ instructions.
201 * i386-tbl.h: Regenerate.
202
1ba585e8
IT		 2032014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
204 Alexander Ivchenko <alexander.ivchenko@intel.com>
205 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
206 Sergey Lega <sergey.s.lega@intel.com>
207 Anna Tikhonova <anna.tikhonova@intel.com>
208 Ilya Tocar <ilya.tocar@intel.com>
209 Andrey Turetskiy <andrey.turetskiy@intel.com>
210 Ilya Verbin <ilya.verbin@intel.com>
211 Kirill Yukhin <kirill.yukhin@intel.com>
212 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
213
214 * i386-dis-evex.h: Add new instructions (prefixes bellow).
215 * i386-dis.c (fetch_data): Add EdqwS, Edb, Edw, MaskBDE.
216 (enum): Add dqw_swap_mode, db_mode, dw_mode, mask_bd_mode, REG_EVEX_0F71.
217 (PREFIX enum): Add PREFIX_VEX_0F4A, PREFIX_VEX_0F99, PREFIX_VEX_0F3A31,
218 PREFIX_VEX_0F3A33, PREFIX_EVEX_0F60, PREFIX_EVEX_0F61, PREFIX_EVEX_0F63,
219 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
220 PREFIX_EVEX_0F69, PREFIX_EVEX_0F6B, PREFIX_EVEX_0F71_REG_2, PREFIX_EVEX_0F71_REG_4,
221 PREFIX_EVEX_0F71_REG_6, PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_7,
222 PREFIX_EVEX_0F74, PREFIX_EVEX_0F75, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
223 PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5, PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9,
224 PREFIX_EVEX_0FDA, PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
225 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3, PREFIX_EVEX_0FE4,
226 PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8, PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA,
227 PREFIX_EVEX_0FEC, PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
228 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8, PREFIX_EVEX_0FF9,
229 PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD, PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804,
230 PREFIX_EVEX_0F380B, PREFIX_EVEX_0F3810, PREFIX_EVEX_0F381C, PREFIX_EVEX_0F381D,
231 PREFIX_EVEX_0F3820, PREFIX_EVEX_0F3826, PREFIX_EVEX_0F382B, PREFIX_EVEX_0F3830,
232 PREFIX_EVEX_0F3838, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E, PREFIX_EVEX_0F3866,
233 PREFIX_EVEX_0F3875, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879, PREFIX_EVEX_0F387A,
234 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387D, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F3A0F,
235 PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15, PREFIX_EVEX_0F3A20, PREFIX_EVEX_0F3A3E,
236 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A42.
237 (VEX_LEN enum): Add VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_2, VEX_LEN_0F44_P_2,
238 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_2, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
239 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_2,
240 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_2, VEX_LEN_0F99_P_0,
241 VEX_LEN_0F99_P_2, VEX_LEN_0F3A31_P_2, VEX_LEN_0F3A33_P_2, VEX_W_0F41_P_2_LEN_1,
242 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_2_LEN_1,
243 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
244 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, VEX_W_0F90_P_2_LEN_0,
245 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_3_LEN_0, VEX_W_0F93_P_3_LEN_0,
246 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, VEX_W_0F99_P_2_LEN_0,
247 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A33_P_2_LEN_0.
248 (VEX_W enum): Add EVEX_W_0F6B_P_2, EVEX_W_0F6F_P_3, EVEX_W_0F7F_P_3,
249 EVEX_W_0F3810_P_1, EVEX_W_0F3810_P_2, EVEX_W_0F3811_P_2, EVEX_W_0F3812_P_2,
250 EVEX_W_0F3820_P_1, EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2, EVEX_W_0F3828_P_1,
251 EVEX_W_0F3829_P_1, EVEX_W_0F382B_P_2, EVEX_W_0F3830_P_1, EVEX_W_0F3866_P_2,
252 EVEX_W_0F3875_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F387A_P_2,
253 EVEX_W_0F387B_P_2, EVEX_W_0F387D_P_2, EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2,
254 EVEX_W_0F3A3F_P_2, EVEX_W_0F3A42_P_2.
255 (prefix_table): Add entries for new instructions.
256 (vex_table) : Ditto.
257 (vex_len_table): Ditto.
258 (vex_w_table): Ditto.
259 (intel_operand_size): Add db_mode, dw_mode, dqw_swap_mode,
260 mask_bd_mode handling.
261 (OP_E_register): Add dqw_swap_mode, dw_mode, db_mode, mask_bd_mode
262 handling.
263 (OP_E_memory): Add dqw_mode, dw_mode, dqw_swap_mode, dqb_mode, db_mode
264 handling.
265 (OP_G): Add db_mode, dw_mode, dqw_swap_mode, mask_bd_mode handling.
266 (OP_EX): Add dqw_swap_mode handling.
267 (OP_VEX): Add mask_bd_mode handling.
268 (OP_Mask): Add mask_bd_mode handling.
269 * i386-gen.c (cpu_flag_init): Add CPU_AVX512BW_FLAGS.
270 (cpu_flags): Add CpuAVX512BW.
271 * i386-init.h: Regenerated.
272 * i386-opc.h (CpuAVX512BW): New.
273 (i386_cpu_flags): Add cpuavx512bw.
274 * i386-opc.tbl: Add AVX512BW instructions.
275 * i386-tbl.h: Regenerate.
276
99282af6
IT		 2772014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
278 Alexander Ivchenko <alexander.ivchenko@intel.com>
279 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
280 Sergey Lega <sergey.s.lega@intel.com>
281 Anna Tikhonova <anna.tikhonova@intel.com>
282 Ilya Tocar <ilya.tocar@intel.com>
283 Andrey Turetskiy <andrey.turetskiy@intel.com>
284 Ilya Verbin <ilya.verbin@intel.com>
285 Kirill Yukhin <kirill.yukhin@intel.com>
286 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
287
288 * i386-opc.tbl: Add AVX512VL and AVX512CD instructions.
289 * i386-tbl.h: Regenerate.
290
b28d1bda
IT		 2912014-07-22 Sergey Guriev <sergey.s.guriev@intel.com>
292 Alexander Ivchenko <alexander.ivchenko@intel.com>
293 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
294 Sergey Lega <sergey.s.lega@intel.com>
295 Anna Tikhonova <anna.tikhonova@intel.com>
296 Ilya Tocar <ilya.tocar@intel.com>
297 Andrey Turetskiy <andrey.turetskiy@intel.com>
298 Ilya Verbin <ilya.verbin@intel.com>
299 Kirill Yukhin <kirill.yukhin@intel.com>
300 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
301
302 * i386-dis.c (intel_operand_size): Support 128/256 length in
303 vex_vsib_q_w_dq_mode.
304 (OP_E_memory): Add ymmq_mode handling, handle new broadcast.
305 * i386-gen.c (cpu_flag_init): Add CPU_AVX512VL_FLAGS.
306 (cpu_flags): Add CpuAVX512VL.
307 * i386-init.h: Regenerated.
308 * i386-opc.h (CpuAVX512VL): New.
309 (i386_cpu_flags): Add cpuavx512vl.
310 (BROADCAST_1TO4, BROADCAST_1TO2): Define.
311 * i386-opc.tbl: Add AVX512VL instructions.
312 * i386-tbl.h: Regenerate.
313
018dc9be
SK		 3142014-07-20 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
315
316 * or1k-desc.c, * or1k-desc.h, * or1k-opc.c, * or1k-opc.h,
317 * or1k-opinst.c: Regenerate.
318
792f7758
IT		 3192014-07-08 Ilya Tocar <ilya.tocar@intel.com>
320
321 * i386-dis-evex.h (EVEX_W_0F10_P_1_M_1): Fix vmovss.
322 (EVEX_W_0F10_P_3_M_1): Fix vmovsd.
323
35eafcc7
AM		 3242014-07-04 Alan Modra <amodra@gmail.com>
325
326 * configure.ac: Rename from configure.in.
327 * Makefile.in: Regenerate.
328 * config.in: Regenerate.
329
2e98a7bd
AM		 3302014-07-04 Alan Modra <amodra@gmail.com>
331
332 * configure.in: Include bfd/version.m4.
333 (AC_INIT, AM_INIT_AUTOMAKE): Use modern form.
334 (BFD_VERSION): Delete.
335 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Remove bfd/configure.in.
336 * configure: Regenerate.
337 * Makefile.in: Regenerate.
338
f36e8886
BS		 3392014-07-01 Barney Stratford <barney_stratford@fastmail.fm>
340 Senthil Kumar Selvaraj <senthil_kumar.selvaraj@atmel.com>
341 Pitchumani Sivanupandi <pitchumani.s@atmel.com>
342 Soundararajan <Sounderarajan.D@atmel.com>
343
344 * avr-dis.c (avr_operand): Handle constraint j for 16 bit lds/sts.
2e98a7bd
AM		 345 (print_insn_avr): Do not select opcode if insn ISA is avrtiny and
346 machine is not avrtiny.
f36e8886 347
6ddf779d
PDM		 3482014-06-26 Philippe De Muyter <phdm@macqel.be>
349
350 * or1k-desc.h (spr_field_masks): Add U suffix to the end of long
351 constants.
352
c151b1c6
AM		 3532014-06-12 Alan Modra <amodra@gmail.com>
354
355 * or1k-asm.c, * or1k-desc.c, * or1k-desc.h, * or1k-dis.c,
356 * or1k-ibld.c, * or1k-opc.c, * or1k-opc.h, * or1k-opinst.c: Regenerate.
357
d9949a36
L		 3582014-06-10 H.J. Lu <hongjiu.lu@intel.com>
359
360 * i386-dis.c (fwait_prefix): New.
361 (ckprefix): Set fwait_prefix.
362 (print_insn): Properly print prefixes before fwait.
363
a47622ac
AM		 3642014-06-07 Alan Modra <amodra@gmail.com>
365
366 * ppc-opc.c (UISIGNOPT): Define and use with cmpli.
367
270c9937
JB		 3682014-06-05 Joel Brobecker <brobecker@adacore.com>
369
370 * Makefile.am (CONFIG_STATUS_DEPENDENCIES): Add dependency on
371 bfd's development.sh.
372 * Makefile.in, configure: Regenerate.
373
9f445129
NC		 3742014-06-03 Nick Clifton <nickc@redhat.com>
375
376 * msp430-dis.c (msp430_doubleoperand): Use extension_word to
377 decide when extended addressing is being used.
378
ec9a8169
EB		 3792014-06-02 Eric Botcazou <ebotcazou@adacore.com>
380
381 * sparc-opc.c (cas): Disable for LEON.
382 (casl): Likewise.
383
cdf2a8b7
AM		 3842014-05-20 Alan Modra <amodra@gmail.com>
385
386 * m68k-dis.c: Don't include setjmp.h.
387
df18fdba
L		 3882014-05-09 H.J. Lu <hongjiu.lu@intel.com>
389
390 * i386-dis.c (ADDR16_PREFIX): Removed.
391 (ADDR32_PREFIX): Likewise.
392 (DATA16_PREFIX): Likewise.
393 (DATA32_PREFIX): Likewise.
394 (prefix_name): Updated.
395 (print_insn): Simplify data and address size prefixes processing.
396
999b995d
SK		 3972014-05-08 Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
398
399 * or1k-desc.c: Regenerated.
400 * or1k-desc.h: Likewise.
401 * or1k-opc.c: Likewise.
402 * or1k-opc.h: Likewise.
403 * or1k-opinst.c: Likewise.
404
ae52f483
AB		 4052014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
406
407 * mips-opc.c (mips_builtin_opcodes): Add MIPS32r5 eretnc instruction.
408 (I34): New define.
409 (I36): New define.
410 (I66): New define.
411 (I68): New define.
412 * mips-dis.c (mips_arch_choices): Add mips32r3, mips32r5, mips64r3 and
413 mips64r5.
414 (parse_mips_dis_option): Update MSA and virtualization support to
9f445129 415 allow mips64r3 and mips64r5.
ae52f483 416
f7730599
AB		 4172014-05-07 Andrew Bennett <andrew.bennett@imgtec.com>
418
419 * mips-opc.c (G3): Remove I4.
420
285ca992
L		 4212014-05-05 H.J. Lu <hongjiu.lu@intel.com>
422
423 PR binutils/16893
424 * i386-dis.c (twobyte_has_mandatory_prefix): New variable.
425 (end_codep): Likewise.
426 (mandatory_prefix): Likewise.
427 (active_seg_prefix): Likewise.
428 (ckprefix): Set active_seg_prefix to the active segment register
429 prefix.
430 (seg_prefix): Removed.
431 (get_valid_dis386): Use the last of PREFIX_REPNZ and PREFIX_REPZ
432 for prefix index. Ignore the index if it is invalid and the
433 mandatory prefix isn't required.
434 (print_insn): Set mandatory_prefix if the PREFIX_XXX prefix is
435 mandatory. Don't set PREFIX_REPZ/PREFIX_REPNZ/PREFIX_LOCK bits
436 in used_prefixes here. Don't print unused prefixes. Check
437 active_seg_prefix for the active segment register prefix.
438 Restore the DFLAG bit in sizeflag if the data size prefix is
439 unused. Check the unused mandatory PREFIX_XXX prefixes
440 (append_seg): Only print the segment register which gets used.
441 (OP_E_memory): Check active_seg_prefix for the segment register
442 prefix.
443 (OP_OFF): Likewise.
444 (OP_OFF64): Likewise.
445 (OP_DSreg): Set active_seg_prefix to PREFIX_DS if it is unset.
446
8df14d78
L		 4472014-05-02 H.J. Lu <hongjiu.lu@intel.com>
448
449 PR binutils/16886
450 * config.in: Regenerated.
451 * configure: Likewise.
452 * configure.in: Check if sigsetjmp is available.
453 * h8500-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
454 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
455 (print_insn_h8500): Replace setjmp with OPCODES_SIGSETJMP.
456 * i386-dis.c (dis_private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
457 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
458 (print_insn): Replace setjmp with OPCODES_SIGSETJMP.
459 * ns32k-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
460 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
461 (print_insn_ns32k): Replace setjmp with OPCODES_SIGSETJMP.
462 * sysdep.h (OPCODES_SIGJMP_BUF): New macro.
463 (OPCODES_SIGSETJMP): Likewise.
464 (OPCODES_SIGLONGJMP): Likewise.
465 * vax-dis.c (private): Replace jmp_buf with OPCODES_SIGJMP_BUF.
466 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
467 (print_insn_vax): Replace setjmp with OPCODES_SIGSETJMP.
468 * xtensa-dis.c (dis_private): Replace jmp_buf with
469 OPCODES_SIGJMP_BUF.
470 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
471 (print_insn_xtensa): Replace setjmp with OPCODES_SIGSETJMP.
472 * z8k-dis.c(instr_data_s): Replace jmp_buf with OPCODES_SIGJMP_BUF.
473 (fetch_data): Replace longjmp with OPCODES_SIGLONGJMP.
474 (print_insn_z8k): Replace setjmp with OPCODES_SIGSETJMP.
475
86a80a50
L		 4762014-05-01 H.J. Lu <hongjiu.lu@intel.com>
477
478 PR binutils/16891
479 * i386-dis.c (print_insn): Handle prefixes before fwait.
480
a9e18c6a
AM		 4812014-04-26 Alan Modra <amodra@gmail.com>
482
483 * po/POTFILES.in: Regenerate.
484
7d64c587
AB		 4852014-04-23 Andrew Bennett <andrew.bennett@imgtec.com>
486
487 * mips-dis.c (mips_arch_choices): Update mips32r2 and mips64r2
488 to allow the MIPS XPA ASE.
489 (parse_mips_dis_option): Process the -Mxpa option.
490 * mips-opc.c (XPA): New define.
491 (mips_builtin_opcodes): Add MIPS XPA instructions and move the
492 locations of the ctc0 and cfc0 instructions.
493
73589c9d
CS		 4942014-04-22 Christian Svensson <blue@cmd.nu>
495
496 * Makefile.am: Remove openrisc and or32 support. Add support for or1k.
497 * configure.in: Likewise.
498 * disassemble.c: Likewise.
499 * or1k-asm.c: New file.
500 * or1k-desc.c: New file.
501 * or1k-desc.h: New file.
502 * or1k-dis.c: New file.
503 * or1k-ibld.c: New file.
504 * or1k-opc.c: New file.
505 * or1k-opc.h: New file.
506 * or1k-opinst.c: New file.
507 * Makefile.in: Regenerate.
508 * configure: Regenerate.
509 * openrisc-asm.c: Delete.
510 * openrisc-desc.c: Delete.
511 * openrisc-desc.h: Delete.
512 * openrisc-dis.c: Delete.
513 * openrisc-ibld.c: Delete.
514 * openrisc-opc.c: Delete.
515 * openrisc-opc.h: Delete.
516 * or32-dis.c: Delete.
517 * or32-opc.c: Delete.
518
2cf200a4
IT		 5192014-04-04 Ilya Tocar <ilya.tocar@intel.com>
520
521 * i386-dis.c (rm_table): Add encls, enclu.
522 * i386-gen.c (cpu_flag_init): Add CPU_SE1_FLAGS,
523 (cpu_flags): Add CpuSE1.
524 * i386-opc.h (enum): Add CpuSE1.
525 (i386_cpu_flags): Add cpuse1.
526 * i386-opc.tbl: Add encls, enclu.
527 * i386-init.h: Regenerated.
528 * i386-tbl.h: Likewise.
529
31c981bc
AG		 5302014-04-02 Anthony Green <green@moxielogic.com>
531
532 * moxie-opc.c (moxie_form1_opc_info): Add sign-extension
533 instructions, sex.b and sex.s.
534
76dfed02
YZ		 5352014-03-26 Jiong Wang <jiong.wang@arm.com>
536
537 * aarch64-dis.c (aarch64_ext_ldst_elemlist): Check H/S undefined
538 instructions.
539
5fc35d96
IT		 5402014-03-20 Ilya Tocar <ilya.tocar@intel.com>
541
542 * i386-opc.tbl: Change memory size for vgatherpf0qps, vgatherpf1qps,
543 vscatterpf0qps, vscatterpf1qps, vgatherqps, vpgatherqd, vpscatterqd,
544 vscatterqps.
545 * i386-tbl.h: Regenerate.
546
ec92c392
JM		 5472014-03-19 Jose E. Marchesi <jose.marchesi@oracle.com>
548
549 * sparc-dis.c (v9_hpriv_reg_names): Names for %hstick_offset and
550 %hstick_enable added.
551
b8985e5c
NC		 5522014-03-19 Nick Clifton <nickc@redhat.com>
553
554 * rx-decode.opc (bwl): Allow for bogus instructions with a size
555 field of 3.
b41c812c 556 (sbwl, ubwl, SCALE): Likewise.
b8985e5c
NC		 557 * rx-decode.c: Regenerate.
558
fa47fa92
AM		 5592014-03-12 Alan Modra <amodra@gmail.com>
560
561 * Makefile.in: Regenerate.
562
4b95cf5c
AM		 5632014-03-05 Alan Modra <amodra@gmail.com>
564
565 Update copyright years.
566
cd0c81e9 5672014-03-04 Heiher <r@hev.cc>
4ba154f5
RS		 568
569 * mips-dis.c (mips_arch_choices): Usee ISA_MIPS64R2 for Loongson-3A.
570
079b5aec
RS		 5712014-03-04 Richard Sandiford <rdsandiford@googlemail.com>
572
573 * mips-opc.c (mips_builtin_opcodes): Move the udi* instructions
574 so that they come after the Loongson extensions.
575
2c80b753
AM		 5762014-03-03 Alan Modra <amodra@gmail.com>
577
578 * i386-gen.c (process_copyright): Emit copyright notice on one line.
579
b721f1fa
AM		 5802014-02-28 Alan Modra <amodra@gmail.com>
581
582 * msp430-decode.c: Regenerate.
583
f17c8bfc
YZ		 5842014-02-27 Jiong Wang <jiong.wang@arm.com>
585
586 * aarch64-tbl.h (aarch64_opcode_table): Replace IMM0 with
587 FPIMM0 for fcmeq, fcmgt, fcmge, fcmlt and fcmle.
588
a58549dd
YZ		 5892014-02-27 Yufeng Zhang <yufeng.zhang@arm.com>
590
591 * aarch64-opc.c (print_register_offset_address): Call
592 get_int_reg_name to prepare the register name.
593
d6e9dd78
IT		 5942014-02-25 Ilya Tocar <ilya.tocar@intel.com>
595
596 * i386-opc.tbl: Remove wrong variant of vcvtps2ph
597 * i386-tbl.h: Regenerate.
598
5992014-02-20 Ilya Tocar <ilya.tocar@intel.com>
dcf893b5
IT		 600
601 * i386-gen.c (cpu_flag_init): Add CPU_PREFETCHWT1_FLAGS/
602 (cpu_flags): Add CpuPREFETCHWT1.
603 * i386-init.h: Regenerate.
604 * i386-opc.h (CpuPREFETCHWT1): New.
605 (i386_cpu_flags): Add cpuprefetchwt1.
606 * i386-opc.tbl: Cahnge CPU of prefetchwt1 from CpuAVX512PF to CpuPREFETCHWT1.
607 * i386-tbl.h: Regenerate.
608
957d0955
IT		 6092014-02-20 Ilya Tocar <ilya.tocar@intel.com>
610
611 * i386-opc.tbl: Change CPU of vptestnmq, vptestnmd from CpuAVX512CD,
612 to CpuAVX512F.
613 * i386-tbl.h: Regenerate.
614
10632b79
L		 6152014-02-19 H.J. Lu <hongjiu.lu@intel.com>
616
617 * i386-gen.c (output_cpu_flags): Don't output trailing space.
618 (output_opcode_modifier): Likewise.
619 (output_operand_type): Likewise.
620 * i386-init.h: Regenerated.
621 * i386-tbl.h: Likewise.
622
963f3586
IT		 6232014-02-12 Ilya Tocar <ilya.tocar@intel.com>
624
625 * i386-dis.c (MOD enum): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4,
626 MOD_0FC7_REG_5.
627 (PREFIX enum): Add PREFIX_0FAE_REG_7.
628 (reg_table): Add MOD_0FC7_REG_3, MOD_0FC7_REG_4 MOD_0FC7_REG_5.
629 (prefix_table): Add clflusopt.
630 (mod_table): Add xrstors, xsavec, xsaves.
631 * i386-gen.c (cpu_flag_init): Add CPU_CLFLUSHOPT_FLAGS,
632 CPU_XSAVES_FLAGS, CPU_XSAVEC_FLAGS.
633 (cpu_flags): Add CpuClflushOpt, CpuXSAVES, CpuXSAVEC.
634 * i386-init.h: Regenerate.
635 * i386-opc.tbl: Add clflushopt, xrstors, xrstors64, xsaves,
636 xsaves64, xsavec, xsavec64.
637 * i386-tbl.h: Regenerate.
638
c1c69e83
AM		 6392014-02-10 Alan Modra <amodra@gmail.com>
640
641 * po/POTFILES.in: Regenerate.
642 * po/opcodes.pot: Regenerate.
643
eaa9d1ad
MZ		 6442014-01-30 Michael Zolotukhin <michael.v.zolotukhin@gmail.com>
645 Jan Beulich <jbeulich@suse.com>
646
647 PR binutils/16490
648 * i386-dis.c (OP_E_memory): Fix shift computation for
649 vex_vsib_q_w_dq_mode.
650
e2e6193d
RM		 6512014-01-09 Bradley Nelson <bradnelson@google.com>
652 Roland McGrath <mcgrathr@google.com>
653
654 * i386-dis.c (print_insn): Do not touch all_prefixes[-1] when
655 last_rex_prefix is -1.
656
221fd5d5
L		 6572014-01-08 H.J. Lu <hongjiu.lu@intel.com>
658
659 * i386-gen.c (process_copyright): Update copyright year to 2014.
660
b0b0c9fc
MR		 6612014-01-03 Maciej W. Rozycki <macro@codesourcery.com>
662
663 * nds32-asm.c (parse_operand): Fix out-of-range integer constant.
664
5fb776a6 665For older changes see ChangeLog-2013
252b5132 666\f
5fb776a6 667Copyright (C) 2014 Free Software Foundation, Inc.
752937aa
NC		 668
669Copying and distribution of this file, with or without modification,
670are permitted in any medium without royalty provided the copyright
671notice and this notice are preserved.
672
252b5132 673Local Variables:
2f6d2f85
NC		 674mode: change-log
675left-margin: 8
676fill-column: 74
252b5132
RH		 677version-control: never
678End:
A mirror of the official binutils-gdb repository