]> git.ipfire.org Git - thirdparty/binutils-gdb.git/blame - opcodes/ChangeLog
projects / thirdparty / binutils-gdb.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
Allow out-of-order reads of CIEs
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
de6d8dc2
NC		 12019-10-23 Nick Clifton <nickc@redhat.com>
2
3 * rx-dis.c (get_register_name): Fix spelling typo in error
4 message.
5 (get_condition_name, get_flag_name, get_double_register_name)
6 (get_double_register_high_name, get_double_register_low_name)
7 (get_double_control_register_name, get_double_condition_name)
8 (get_opsize_name, get_size_name): Likewise.
9
6207ed28
NC		 102019-10-22 Nick Clifton <nickc@redhat.com>
11
12 * rx-dis.c (get_size_name): New function. Provides safe
13 access to name array.
14 (get_opsize_name): Likewise.
15 (print_insn_rx): Use the accessor functions.
16
12234dfd
NC		 172019-10-16 Nick Clifton <nickc@redhat.com>
18
19 * rx-dis.c (get_register_name): New function. Provides safe
20 access to name array.
21 (get_condition_name, get_flag_name, get_double_register_name)
22 (get_double_register_high_name, get_double_register_low_name)
23 (get_double_control_register_name, get_double_condition_name):
24 Likewise.
25 (print_insn_rx): Use the accessor functions.
26
1d378749
NC		 272019-10-09 Nick Clifton <nickc@redhat.com>
28
29 PR 25041
30 * avr-dis.c (avr_operand): Fix construction of address for lds/sts
31 instructions.
32
d241b910
JB		 332019-10-07 Jan Beulich <jbeulich@suse.com>
34
35 * opcodes/i386-opc.tbl (movsd): Add Dword and IgnoreSize.
36 (cmpsd): Likewise. Move EsSeg to other operand.
37 * opcodes/i386-tbl.h: Re-generate.
38
f5c5b7c1
AM		 392019-09-23 Alan Modra <amodra@gmail.com>
40
41 * m68k-dis.c: Include cpu-m68k.h
42
7beeaeb8
AM		 432019-09-23 Alan Modra <amodra@gmail.com>
44
45 * mips-dis.c: Include elfxx-mips.h. Move "elf-bfd.h" and
46 "elf/mips.h" earlier.
47
3f9aad11
JB		 482018-09-20 Jan Beulich <jbeulich@suse.com>
49
50 PR gas/25012
51 * i386-opc.tbl (push, pop): Re-instate distinct Cpu64 templates
52 with SReg operand.
53 * i386-tbl.h: Re-generate.
54
fd361982
AM		 552019-09-18 Alan Modra <amodra@gmail.com>
56
57 * arc-ext.c: Update throughout for bfd section macro changes.
58
e0b2a78c
SM		 592019-09-18 Simon Marchi <simon.marchi@polymtl.ca>
60
61 * Makefile.in: Re-generate.
62 * configure: Re-generate.
63
7e9ad3a3
JW		 642019-09-17 Maxim Blinov <maxim.blinov@embecosm.com>
65
66 * riscv-opc.c (riscv_opcodes): Change subset field
67 to insn_class field for all instructions.
68 (riscv_insn_types): Likewise.
69
bb695960
PB		 702019-09-16 Phil Blundell <pb@pbcl.net>
71
72 * configure: Regenerated.
73
8063ab7e
MV		 742019-09-10 Miod Vallat <miod@online.fr>
75
76 PR 24982
77 * m68k-opc.c: Correct aliases for tdivsl and tdivul.
78
60391a25
PB		 792019-09-09 Phil Blundell <pb@pbcl.net>
80
81 binutils 2.33 branch created.
82
f44b758d
NC		 832019-09-03 Nick Clifton <nickc@redhat.com>
84
85 PR 24961
86 * tic30-dis.c (get_indirect_operand): Check for bufcnt being
87 greater than zero before indexing via (bufcnt -1).
88
1e4b5e7d
NC		 892019-09-03 Nick Clifton <nickc@redhat.com>
90
91 PR 24958
92 * mmix-dis.c (MAX_REG_NAME_LEN): Define.
93 (MAX_SPEC_REG_NAME_LEN): Define.
94 (struct mmix_dis_info): Use defined constants for array lengths.
95 (get_reg_name): New function.
96 (get_sprec_reg_name): New function.
97 (print_insn_mmix): Use new functions.
98
c4a23bf8
SP		 992019-08-27 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
100
101 * arm-dis.c (mve_opcodes): Add entry for MVE_VMOV_VEC_TO_VEC.
102 (is_mve_undefined): Add case for MVE_VMOV_VEC_TO_VEC.
103 (print_insn_mve): Add condition to check Qm==Qn of VORR instruction.
104
a051e2f3
KT		 1052019-08-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
106
107 * aarch64-opc.c (aarch64_sys_regs): Update encoding of tfsre0_el1,
108 tfsr_el1, tfsr_el2, tfsr_el3, tfsr_el12.
109 (aarch64_sys_reg_supported_p): Update checks for the above.
110
08132bdd
SP		 1112019-08-12 Srinath Parvathaneni <srinath.parvathaneni@arm.com>
112
113 * arm-dis.c (struct mopcode32 mve_opcodes): Modify the mask for
114 cases MVE_SQRSHRL and MVE_UQRSHLL.
115 (print_insn_mve): Add case for specifier 'k' to check
116 specific bit of the instruction.
117
d88bdcb4
PA		 1182019-08-07 Phillipe Antoine <p.antoine@catenacyber.fr>
119
120 PR 24854
121 * arc-dis.c (arc_insn_length): Return 0 rather than aborting when
122 encountering an unknown machine type.
123 (print_insn_arc): Handle arc_insn_length returning 0. In error
124 cases return -1 rather than calling abort.
125
bc750500
JB		 1262019-08-07 Jan Beulich <jbeulich@suse.com>
127
128 * i386-opc.tbl (fld, fstp): Drop FloatMF from extended forms.
129 (fldcw, fnstcw, fstcw, fnstsw, fstsw): Replace FloatMF by
130 IgnoreSize.
131 * i386-tbl.h: Re-generate.
132
23d188c7
BW		 1332019-08-05 Barnaby Wilks <barnaby.wilks@arm.com>
134
135 * arm-dis.c: Only accept signed variants of VQ(R)DMLAH and VQ(R)DMLASH
136 instructions.
137
c0d6f62f
JW		 1382019-07-30 Mel Chen <mel.chen@sifive.com>
139
140 * riscv-opc.c (riscv_opcodes): Set frsr, fssr, frcsr, fscsr, frrm,
141 fsrm, fsrmi, frflags, fsflags, fsflagsi to alias instructions.
142
143 * riscv-opc.c (riscv_opcodes): Adjust order of frsr, frcsr, fssr,
144 fscsr.
145
0f3f7167
CZ		 1462019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
147
148 * arc-dis.c (skip_this_opcode): Check also for 0x07 major opcodes,
149 and MPY class instructions.
150 (parse_option): Add nps400 option.
151 (print_arc_disassembler_options): Add nps400 info.
152
7e126ba3
CZ		 1532019-07-24 Claudiu Zissulescu <claziss@synopsys.com>
154
155 * arc-ext-tbl.h (bspeek): Remove it, added to main table.
156 (bspop): Likewise.
157 (modapp): Likewise.
158 * arc-opc.c (RAD_CHK): Add.
159 * arc-tbl.h: Regenerate.
160
a028026d
KT		 1612019-07-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
162
163 * aarch64-opc.c (aarch64_sys_regs): Add gmid_el1 entry.
164 (aarch64_sys_reg_supported_p): Handle gmid_el1 encoding.
165
ac79ff9e
NC		 1662019-07-22 Barnaby Wilks <barnaby.wilks@arm.com>
167
168 * arm-dis.c (is_mve_unpredictable): Stop marking some MVE
169 instructions as UNPREDICTABLE.
170
231097b0
JM		 1712019-07-19 Jose E. Marchesi <jose.marchesi@oracle.com>
172
173 * bpf-desc.c: Regenerated.
174
1d942ae9
JB		 1752019-07-17 Jan Beulich <jbeulich@suse.com>
176
177 * i386-gen.c (static_assert): Define.
178 (main): Use it.
179 * i386-opc.h (Opcode_Modifier_Max): Rename to ...
180 (Opcode_Modifier_Num): ... this.
181 (Mem): Delete.
182
dfd69174
JB		 1832019-07-16 Jan Beulich <jbeulich@suse.com>
184
185 * i386-gen.c (operand_types): Move RegMem ...
186 (opcode_modifiers): ... here.
187 * i386-opc.h (RegMem): Move to opcode modifer enum.
188 (union i386_operand_type): Move regmem field ...
189 (struct i386_opcode_modifier): ... here.
190 * i386-opc.tbl (RegMem): Define.
191 (mov, movq): Move RegMem on segment, control, debug, and test
192 register flavors.
193 (pextrb): Move RegMem on register only flavors. Add IgnoreSize
194 to non-SSE2AVX flavor.
195 (extractps, pextrw, vcvtps2ph, vextractps, vpextrb, vpextrw):
196 Move RegMem on register only flavors. Drop IgnoreSize from
197 legacy encoding flavors.
198 (movss, movsd, vmovss, vmovsd): Drop RegMem from register only
199 flavors.
200 (vpinsrb, vpinsrw): Drop IgnoreSize where still present on
201 register only flavors.
202 (vmovd): Move RegMem and drop IgnoreSize on register only
203 flavor. Change opcode and operand order to store form.
204 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
205
21df382b
JB		 2062019-07-16 Jan Beulich <jbeulich@suse.com>
207
208 * i386-gen.c (operand_type_init, operand_types): Replace SReg
209 entries.
210 * i386-opc.h (SReg2, SReg3): Replace by ...
211 (SReg): ... this.
212 (union i386_operand_type): Replace sreg fields.
213 * i386-opc.tbl (mov, ): Use SReg.
214 (push, pop): Likewies. Drop i386 and x86-64 specific segment
215 register flavors.
216 * i386-reg.tbl (cs, ds, es, fs, gs, ss, flat): Use SReg.
217 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
218
3719fd55
JM		 2192019-07-15 Jose E. Marchesi <jose.marchesi@oracle.com>
220
221 * bpf-desc.c: Regenerate.
222 * bpf-opc.c: Likewise.
223 * bpf-opc.h: Likewise.
224
92434a14
JM		 2252019-07-14 Jose E. Marchesi <jose.marchesi@oracle.com>
226
227 * bpf-desc.c: Regenerate.
228 * bpf-opc.c: Likewise.
229
43dd7626
HPN		 2302019-07-10 Hans-Peter Nilsson <hp@bitrange.com>
231
232 * arm-dis.c (print_insn_coprocessor): Rename index to
233 index_operand.
234
98602811
JW		 2352019-07-05 Kito Cheng <kito.cheng@sifive.com>
236
237 * riscv-opc.c (riscv_insn_types): Add r4 type.
238
239 * riscv-opc.c (riscv_insn_types): Add b and j type.
240
241 * opcodes/riscv-opc.c (riscv_insn_types): Remove incorrect
242 format for sb type and correct s type.
243
01c1ee4a
RS		 2442019-07-02 Richard Sandiford <richard.sandiford@arm.com>
245
246 * aarch64-tbl.h (aarch64_opcode): Set C_SCAN_MOVPRFX for the
247 SVE FMOV alias of FCPY.
248
83adff69
RS		 2492019-07-02 Richard Sandiford <richard.sandiford@arm.com>
250
251 * aarch64-tbl.h (aarch64_opcode_table): Add C_MAX_ELEM flags
252 to SVE fcvtzs, fcvtzu, scvtf and ucvtf entries.
253
89418844
RS		 2542019-07-02 Richard Sandiford <richard.sandiford@arm.com>
255
256 * aarch64-opc.c (verify_constraints): Skip GPRs when scanning the
257 registers in an instruction prefixed by MOVPRFX.
258
41be57ca
MM		 2592019-07-01 Matthew Malcomson <matthew.malcomson@arm.com>
260
261 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Use new
262 sve_size_13 icode to account for variant behaviour of
263 pmull{t,b}.
264 * aarch64-dis-2.c: Regenerate.
265 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Use new
266 sve_size_13 icode to account for variant behaviour of
267 pmull{t,b}.
268 * aarch64-tbl.h (OP_SVE_VVV_HD_BS): Add new qualifier.
269 (OP_SVE_VVV_Q_D): Add new qualifier.
270 (OP_SVE_VVV_QHD_DBS): Remove now unused qualifier.
271 (struct aarch64_opcode): Split pmull{t,b} into those requiring
272 AES and those not.
273
9d3bf266
JB		 2742019-07-01 Jan Beulich <jbeulich@suse.com>
275
276 * opcodes/i386-gen.c (operand_type_init): Remove
277 OPERAND_TYPE_VEC_IMM4 entry.
278 (operand_types): Remove Vec_Imm4.
279 * opcodes/i386-opc.h (Vec_Imm4): Delete.
280 (union i386_operand_type): Remove vec_imm4.
281 * i386-opc.tbl (vpermil2pd, vpermil2ps): Remove Vec_Imm4.
282 * opcodes/i386-init.h, i386-tbl.h: Re-generate.
283
c3949f43
JB		 2842019-07-01 Jan Beulich <jbeulich@suse.com>
285
286 * i386-opc.tbl (lfence, mfence, sfence, monitor, mwait, vmcall,
287 vmlaunch, vmresume, vmxoff, vmfunc, xgetbv, xsetbv, swapgs,
288 rdtscp, clgi, invlpga, skinit, stgi, vmload, vmmcall, vmrun,
289 vmsave, montmul, xsha1, xsha256, xstorerng, xcryptecb,
290 xcryptcbc, xcryptctr, xcryptcfb, xcryptofb, xstore, clac, stac,
291 monitorx, mwaitx): Drop ImmExt from operand-less forms.
292 * i386-tbl.h: Re-generate.
293
5641ec01
JB		 2942019-07-01 Jan Beulich <jbeulich@suse.com>
295
296 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
297 register operands.
298 * i386-tbl.h: Re-generate.
299
79dec6b7
JB		 3002019-07-01 Jan Beulich <jbeulich@suse.com>
301
302 * i386-opc.tbl (C): New.
303 (paddb, paddw, paddd, paddq, paddsb, paddsw, paddusb, paddusw,
304 pand, pcmpeqb, pcmpeqw, pcmpeqd, pmaddwd, pmulhw, pmullw,
305 por, pxor, andps, cmpeqps, cmpeqss, cmpneqps, cmpneqss,
306 cmpordps, cmpordss, cmpunordps, cmpunordss, orps, pavgb, pavgw,
307 pmaxsw, pmaxub, pminsw, pminub, pmulhuw, xorps, andpd, cmpeqpd,
308 cmpeqsd, cmpneqpd, cmpneqsd, cmpordpd, cmpordsd, cmpunordpd,
309 cmpunordsd, orpd, xorpd, pmuludq, vandpd, vandps, vcmpeq_ospd,
310 vcmpeq_osps, vcmpeq_ossd, vcmpeq_osss, vcmpeqpd, vcmpeqps,
311 vcmpeqsd, vcmpeqss, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uqsd,
312 vcmpeq_uqss, vcmpeq_uspd, vcmpeq_usps, vcmpeq_ussd,
313 vcmpeq_usss, vcmpfalse_ospd, vcmpfalse_osps, vcmpfalse_ossd,
314 vcmpfalse_osss, vcmpfalsepd, vcmpfalseps, vcmpfalsesd,
315 vcmpfalsess, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_oqsd,
316 vcmpneq_oqss, vcmpneq_ospd, vcmpneq_osps, vcmpneq_ossd,
317 vcmpneq_osss, vcmpneqpd, vcmpneqps, vcmpneqsd, vcmpneqss,
318 vcmpneq_uspd, vcmpneq_usps, vcmpneq_ussd, vcmpneq_usss,
319 vcmpordpd, vcmpordps, vcmpordsd, vcmpord_spd, vcmpord_sps,
320 vcmpordss, vcmpord_ssd, vcmpord_sss, vcmptruepd, vcmptrueps,
321 vcmptruesd, vcmptruess, vcmptrue_uspd, vcmptrue_usps,
322 vcmptrue_ussd, vcmptrue_usss, vcmpunordpd, vcmpunordps,
323 vcmpunordsd, vcmpunord_spd, vcmpunord_sps, vcmpunordss,
324 vcmpunord_ssd, vcmpunord_sss, vorpd, vorps, vpaddsb, vpaddsw,
325 vpaddb, vpaddd, vpaddq, vpaddw, vpaddusb, vpaddusw, vpand,
326 vpavgb, vpavgw, vpcmpeqb, vpcmpeqd, vpcmpeqw, vpmaddwd,
327 vpmaxsw, vpmaxub, vpminsw, vpminub, vpmulhuw, vpmulhw, vpmullw,
328 vpmuludq, vpor, vpxor, vxorpd, vxorps): Add C to VEX-encoded
329 flavors.
330 * i386-tbl.h: Re-generate.
331
a0a1771e
JB		 3322019-07-01 Jan Beulich <jbeulich@suse.com>
333
334 * i386-opc.tbl (and, or): Add Optimize to forms allowing two
335 register operands.
336 * i386-tbl.h: Re-generate.
337
cd546e7b
JB		 3382019-07-01 Jan Beulich <jbeulich@suse.com>
339
340 * i386-dis-evex-prefix.h: Use PCLMUL for vpclmulqdq.
341 * i386-opc.tbl (vpclmullqlqdq, vpclmulhqlqdq, vpclmullqhqdq,
342 vpclmulhqhqdq): Add CpuVPCLMULQDQ flavors.
343 * i386-tbl.h: Re-generate.
344
e3bba3fc
JB		 3452019-07-01 Jan Beulich <jbeulich@suse.com>
346
347 * i386-opc.tbl (vextractps, vpextrw, vpinsrw): Remove
348 Disp8MemShift from register only templates.
349 * i386-tbl.h: Re-generate.
350
36cc073e
JB		 3512019-07-01 Jan Beulich <jbeulich@suse.com>
352
353 * i386-dis.c (EXdScalarS, MOD_EVEX_0F10_PREFIX_1,
354 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1,
355 MOD_EVEX_0F11_PREFIX_3, EVEX_W_0F10_P_1_M_0,
356 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_3_M_0, EVEX_W_0F10_P_3_M_1,
357 EVEX_W_0F11_P_1_M_0, EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_3_M_0,
358 EVEX_W_0F11_P_3_M_1): Delete.
359 (EVEX_W_0F10_P_1, EVEX_W_0F10_P_3, EVEX_W_0F11_P_1,
360 EVEX_W_0F11_P_3): New.
361 * i386-dis-evex-mod.h: Remove MOD_EVEX_0F10_PREFIX_1,
362 MOD_EVEX_0F10_PREFIX_3, MOD_EVEX_0F11_PREFIX_1, and
363 MOD_EVEX_0F11_PREFIX_3 table entries.
364 * i386-dis-evex-prefix.h: Adjust PREFIX_EVEX_0F10 and
365 PREFIX_EVEX_0F11 table entries.
366 * i386-dis-evex-w.h: Replace EVEX_W_0F10_P_1_M_{0,1},
367 EVEX_W_0F10_P_3_M_{0,1}, EVEX_W_0F11_P_1_M_{0,1}, and
368 EVEX_W_0F11_P_3_M_{0,1} table entries.
369
219920a7
JB		 3702019-07-01 Jan Beulich <jbeulich@suse.com>
371
372 * i386-dis.c (EXdVex, EXdVexS, EXqVex, EXqVexS, XMVex):
373 Delete.
374
e395f487
L		 3752019-06-27 H.J. Lu <hongjiu.lu@intel.com>
376
377 PR binutils/24719
378 * i386-dis-evex-len.h: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
379 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
380 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
381 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
382 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
383 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
384 EVEX_LEN_0F38C7_R_6_P_2_W_1.
385 * i386-dis-evex-prefix.h: Update PREFIX_EVEX_0F38C6_REG_1,
386 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5 and
387 PREFIX_EVEX_0F38C6_REG_6 entries.
388 * i386-dis-evex-w.h: Update EVEX_W_0F38C7_R_1_P_2,
389 EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2 and
390 EVEX_W_0F38C7_R_6_P_2 entries.
391 * i386-dis.c: Add EVEX_LEN_0F38C6_REG_1_PREFIX_2,
392 EVEX_LEN_0F38C6_REG_2_PREFIX_2, EVEX_LEN_0F38C6_REG_5_PREFIX_2,
393 EVEX_LEN_0F38C6_REG_6_PREFIX_2, EVEX_LEN_0F38C7_R_1_P_2_W_0,
394 EVEX_LEN_0F38C7_R_1_P_2_W_1, EVEX_LEN_0F38C7_R_2_P_2_W_0,
395 EVEX_LEN_0F38C7_R_2_P_2_W_1, EVEX_LEN_0F38C7_R_5_P_2_W_0,
396 EVEX_LEN_0F38C7_R_5_P_2_W_1, EVEX_LEN_0F38C7_R_6_P_2_W_0 and
397 EVEX_LEN_0F38C7_R_6_P_2_W_1 enums.
398
2b7bcc87
JB		 3992019-06-27 Jan Beulich <jbeulich@suse.com>
400
401 * i386-dis.c (VEX_LEN_0F2A_P_1, VEX_LEN_0F2A_P_3,
402 VEX_LEN_0F2C_P_1, VEX_LEN_0F2C_P_3, VEX_LEN_0F2D_P_1,
403 VEX_LEN_0F2D_P_3): Delete.
404 (vex_len_table): Move vcvtsi2ss, vcvtsi2sd, vcvttss2si,
405 vcvttsd2si, vcvtss2si, and vcvtsd2si leaf entries ...
406 (prefix_table): ... here.
407
c1dc7af5
JB		 4082019-06-27 Jan Beulich <jbeulich@suse.com>
409
410 * i386-dis.c (Iq): Delete.
411 (Id): New.
412 (reg_table): Use it for lwpins, lwpval, and bextr. Use Edq for
413 TBM insns.
414 (vex_len_table): Use Edq for vcvtsi2ss, vcvtsi2sd. Use Gdq for
415 vcvttss2si, vcvttsd2si, vcvtss2si, and vcvtsd2si.
416 (OP_E_memory): Also honor needindex when deciding whether an
417 address size prefix needs printing.
418 (OP_I): Remove handling of q_mode. Add handling of d_mode.
419
d7560e2d
JW		 4202019-06-26 Jim Wilson <jimw@sifive.com>
421
422 PR binutils/24739
423 * riscv-dis.c (riscv_disasemble_insn): Set info->endian_code.
424 Set info->display_endian to info->endian_code.
425
2c703856
JB		 4262019-06-25 Jan Beulich <jbeulich@suse.com>
427
428 * i386-gen.c (operand_type_init): Correct OPERAND_TYPE_DEBUG
429 entry. Drop OPERAND_TYPE_ACC entry. Add OPERAND_TYPE_ACC8 and
430 OPERAND_TYPE_ACC16 entries. Adjust OPERAND_TYPE_ACC32 and
431 OPERAND_TYPE_ACC64 entries.
432 * i386-init.h: Re-generate.
433
54fbadc0
JB		 4342019-06-25 Jan Beulich <jbeulich@suse.com>
435
436 * i386-dis.c (Edqa, dqa_mode, EVEX_W_0F2A_P_1, EVEX_W_0F7B_P_1):
437 Delete.
438 (intel_operand_size, OP_E_register, OP_E_memory): Drop handling
439 of dqa_mode.
440 * i386-dis-evex-prefix.h: Move vcvtsi2ss and vcvtusi2ss leaf
441 entries here.
442 * i386-dis-evex-w.h: Drop EVEX_W_0F2A_P_1 and EVEX_W_0F7B_P_1
443 entries. Use Edq for vcvtsi2sd and vcvtusi2sd.
444
a280ab8e
JB		 4452019-06-25 Jan Beulich <jbeulich@suse.com>
446
447 * i386-dis.c (OP_I64): Forword more cases to OP_I(). Drop local
448 variables.
449
e1a1babd
JB		 4502019-06-25 Jan Beulich <jbeulich@suse.com>
451
452 * i386-dis.c (prefix_table): Use Edq for cvtsi2ss and cvtsi2sd.
453 Use Gdq for cvttss2si, cvttsd2si, cvtss2si, and cvtsd2si, and
454 movnti.
d7560e2d 455 * i386-opc.tbl (movnti): Add IgnoreSize.
e1a1babd
JB		 456 * i386-tbl.h: Re-generate.
457
b8364fa7
JB		 4582019-06-25 Jan Beulich <jbeulich@suse.com>
459
460 * i386-opc.tbl (and): Mark Imm8S form for optimization.
461 * i386-tbl.h: Re-generate.
462
ad692897
L		 4632019-06-21 H.J. Lu <hongjiu.lu@intel.com>
464
465 * i386-dis-evex.h: Break into ...
466 * i386-dis-evex-len.h: New file.
467 * i386-dis-evex-mod.h: Likewise.
468 * i386-dis-evex-prefix.h: Likewise.
469 * i386-dis-evex-reg.h: Likewise.
470 * i386-dis-evex-w.h: Likewise.
471 * i386-dis.c: Include i386-dis-evex-reg.h, i386-dis-evex-prefix.h,
472 i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-w.h and
473 i386-dis-evex-mod.h.
474
f0a6222e
L		 4752019-06-19 H.J. Lu <hongjiu.lu@intel.com>
476
477 PR binutils/24700
478 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3819_P_2,
479 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2 and
480 EVEX_W_0F385B_P_2.
481 (evex_len_table): Add EVEX_LEN_0F3819_P_2_W_0,
482 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0,
483 EVEX_LEN_0F381A_P_2_W_1, EVEX_LEN_0F381B_P_2_W_0,
484 EVEX_LEN_0F381B_P_2_W_1, EVEX_LEN_0F385A_P_2_W_0,
485 EVEX_LEN_0F385A_P_2_W_1, EVEX_LEN_0F385B_P_2_W_0 and
486 EVEX_LEN_0F385B_P_2_W_1.
487 * i386-dis.c (EVEX_LEN_0F3819_P_2_W_0): New enum.
488 (EVEX_LEN_0F3819_P_2_W_1): Likewise.
489 (EVEX_LEN_0F381A_P_2_W_0): Likewise.
490 (EVEX_LEN_0F381A_P_2_W_1): Likewise.
491 (EVEX_LEN_0F381B_P_2_W_0): Likewise.
492 (EVEX_LEN_0F381B_P_2_W_1): Likewise.
493 (EVEX_LEN_0F385A_P_2_W_0): Likewise.
494 (EVEX_LEN_0F385A_P_2_W_1): Likewise.
495 (EVEX_LEN_0F385B_P_2_W_0): Likewise.
496 (EVEX_LEN_0F385B_P_2_W_1): Likewise.
497
6e1c90b7
L		 4982019-06-17 H.J. Lu <hongjiu.lu@intel.com>
499
500 PR binutils/24691
501 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A23_P_2,
502 EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
503 EVEX_W_0F3A3B_P_2 and EVEX_W_0F3A43_P_2.
504 (evex_len_table): Add EVEX_LEN_0F3A23_P_2_W_0,
505 EVEX_LEN_0F3A23_P_2_W_1, EVEX_LEN_0F3A38_P_2_W_0,
506 EVEX_LEN_0F3A38_P_2_W_1, EVEX_LEN_0F3A39_P_2_W_0,
507 EVEX_LEN_0F3A39_P_2_W_1, EVEX_LEN_0F3A3A_P_2_W_0,
508 EVEX_LEN_0F3A3A_P_2_W_1, EVEX_LEN_0F3A3B_P_2_W_0,
509 EVEX_LEN_0F3A3B_P_2_W_1, EVEX_LEN_0F3A43_P_2_W_0 and
510 EVEX_LEN_0F3A43_P_2_W_1.
511 * i386-dis.c (EVEX_LEN_0F3A23_P_2_W_0): New enum.
512 (EVEX_LEN_0F3A23_P_2_W_1): Likewise.
513 (EVEX_LEN_0F3A38_P_2_W_0): Likewise.
514 (EVEX_LEN_0F3A38_P_2_W_1): Likewise.
515 (EVEX_LEN_0F3A39_P_2_W_0): Likewise.
516 (EVEX_LEN_0F3A39_P_2_W_1): Likewise.
517 (EVEX_LEN_0F3A3A_P_2_W_0): Likewise.
518 (EVEX_LEN_0F3A3A_P_2_W_1): Likewise.
519 (EVEX_LEN_0F3A3B_P_2_W_0): Likewise.
520 (EVEX_LEN_0F3A3B_P_2_W_1): Likewise.
521 (EVEX_LEN_0F3A43_P_2_W_0): Likewise.
522 (EVEX_LEN_0F3A43_P_2_W_1): Likewise.
523
bcc5a6eb
NC		 5242019-06-14 Nick Clifton <nickc@redhat.com>
525
526 * po/fr.po; Updated French translation.
527
e4c4ac46
SH		 5282019-06-13 Stafford Horne <shorne@gmail.com>
529
530 * or1k-asm.c: Regenerated.
531 * or1k-desc.c: Regenerated.
532 * or1k-desc.h: Regenerated.
533 * or1k-dis.c: Regenerated.
534 * or1k-ibld.c: Regenerated.
535 * or1k-opc.c: Regenerated.
536 * or1k-opc.h: Regenerated.
537 * or1k-opinst.c: Regenerated.
538
a0e44ef5
PB		 5392019-06-12 Peter Bergner <bergner@linux.ibm.com>
540
541 * ppc-opc.c (powerpc_opcodes) <ldmx>: Delete mnemonic.
542
12efd68d
L		 5432019-06-05 H.J. Lu <hongjiu.lu@intel.com>
544
545 PR binutils/24633
546 * i386-dis-evex.h (evex_table): Update EVEX_W_0F3A18_P_2,
547 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2 and EVEX_W_0F3A1B_P_2.
548 (evex_len_table): EVEX_LEN_0F3A18_P_2_W_0,
549 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
550 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
551 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
552 EVEX_LEN_0F3A1B_P_2_W_1.
553 * i386-dis.c (EVEX_LEN_0F3A18_P_2_W_0): New enum.
554 (EVEX_LEN_0F3A18_P_2_W_1): Likewise.
555 (EVEX_LEN_0F3A19_P_2_W_0): Likewise.
556 (EVEX_LEN_0F3A19_P_2_W_1): Likewise.
557 (EVEX_LEN_0F3A1A_P_2_W_0): Likewise.
558 (EVEX_LEN_0F3A1A_P_2_W_1): Likewise.
559 (EVEX_LEN_0F3A1B_P_2_W_0): Likewise.
560 (EVEX_LEN_0F3A1B_P_2_W_1): Likewise.
561
63c6fc6c
L		 5622019-06-04 H.J. Lu <hongjiu.lu@intel.com>
563
564 PR binutils/24626
565 * i386-dis.c (print_insn): Check for unused VEX.vvvv and
566 EVEX.vvvv when disassembling VEX and EVEX instructions.
567 (OP_VEX): Set vex.register_specifier to 0 after readding
568 vex.register_specifier.
569 (OP_Vex_2src_1): Likewise.
570 (OP_Vex_2src_2): Likewise.
571 (OP_LWP_E): Likewise.
572 (OP_EX_Vex): Don't check vex.register_specifier.
573 (OP_XMM_Vex): Likewise.
574
9186c494
L		 5752019-06-04 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
576 Lili Cui <lili.cui@intel.com>
577
578 * i386-dis.c (enum): Add PREFIX_EVEX_0F3868, EVEX_W_0F3868_P_3.
579 * i386-dis-evex.h (evex_table): Add AVX512_VP2INTERSECT
580 instructions.
581 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VP2INTERSECT_FLAGS,
582 CPU_ANY_AVX512_VP2INTERSECT_FLAGS.
583 (cpu_flags): Add CpuAVX512_VP2INTERSECT.
584 * i386-opc.h (enum): Add CpuAVX512_VP2INTERSECT.
585 (i386_cpu_flags): Add cpuavx512_vp2intersect.
586 * i386-opc.tbl: Add AVX512_VP2INTERSECT insns.
587 * i386-init.h: Regenerated.
588 * i386-tbl.h: Likewise.
589
5d79adc4
L		 5902019-06-04 Xuepeng Guo <xuepeng.guo@intel.com>
591 Lili Cui <lili.cui@intel.com>
592
593 * doc/c-i386.texi: Document enqcmd.
594 * testsuite/gas/i386/enqcmd-intel.d: New file.
595 * testsuite/gas/i386/enqcmd-inval.l: Likewise.
596 * testsuite/gas/i386/enqcmd-inval.s: Likewise.
597 * testsuite/gas/i386/enqcmd.d: Likewise.
598 * testsuite/gas/i386/enqcmd.s: Likewise.
599 * testsuite/gas/i386/x86-64-enqcmd-intel.d: Likewise.
600 * testsuite/gas/i386/x86-64-enqcmd-inval.l: Likewise.
601 * testsuite/gas/i386/x86-64-enqcmd-inval.s: Likewise.
602 * testsuite/gas/i386/x86-64-enqcmd.d: Likewise.
603 * testsuite/gas/i386/x86-64-enqcmd.s: Likewise.
604 * testsuite/gas/i386/i386.exp: Run enqcmd-intel, enqcmd-inval,
605 enqcmd, x86-64-enqcmd-intel, x86-64-enqcmd-inval,
606 and x86-64-enqcmd.
607
a9d96ab9
AH		 6082019-06-04 Alan Hayward <alan.hayward@arm.com>
609
610 * arm-dis.c (is_mve_unpredictable): Remove spurious paranthesis.
611
4f6d070a
AM		 6122019-06-03 Alan Modra <amodra@gmail.com>
613
614 * ppc-dis.c (prefix_opcd_indices): Correct size.
615
a2f4b66c
L		 6162019-05-28 H.J. Lu <hongjiu.lu@intel.com>
617
618 PR gas/24625
619 * i386-opc.tbl: Add CheckRegSize to AVX512_BF16 instructions with
620 Disp8ShiftVL.
621 * i386-tbl.h: Regenerated.
622
405b5bd8
AM		 6232019-05-24 Alan Modra <amodra@gmail.com>
624
625 * po/POTFILES.in: Regenerate.
626
8acf1435
PB		 6272019-05-24 Peter Bergner <bergner@linux.ibm.com>
628 Alan Modra <amodra@gmail.com>
629
630 * ppc-opc.c (insert_d34, extract_d34, insert_nsi34, extract_nsi34),
631 (insert_pcrel, extract_pcrel, extract_pcrel0): New functions.
632 (extract_esync, extract_raq, extract_tbr, extract_sxl): Comment.
633 (powerpc_operands <D34, SI34, NSI34, PRA0, PRAQ, PCREL, PCREL0,
634 XTOP>): Define and add entries.
635 (P8LS, PMLS, P_D_MASK, P_DRAPCREL_MASK): Define.
636 (prefix_opcodes): Add pli, paddi, pla, psubi, plwz, plbz, pstw,
637 pstb, plhz, plha, psth, plfs, plfd, pstfs, pstfd, plq, plxsd,
638 plxssp, pld, plwa, pstxsd, pstxssp, pstxv, pstd, and pstq.
639
dd7efa79
PB		 6402019-05-24 Peter Bergner <bergner@linux.ibm.com>
641 Alan Modra <amodra@gmail.com>
642
643 * ppc-dis.c (ppc_opts): Add "future" entry.
644 (PREFIX_OPCD_SEGS): Define.
645 (prefix_opcd_indices): New array.
646 (disassemble_init_powerpc): Initialize prefix_opcd_indices.
647 (lookup_prefix): New function.
648 (print_insn_powerpc): Handle 64-bit prefix instructions.
649 * ppc-opc.c (PREFIX_OP, PREFIX_FORM, SUFFIX_MASK, PREFIX_MASK),
650 (PMRR, POWERXX): Define.
651 (prefix_opcodes): New instruction table.
652 (prefix_num_opcodes): New constant.
653
79472b45
JM		 6542019-05-23 Jose E. Marchesi <jose.marchesi@oracle.com>
655
656 * configure.ac (SHARED_DEPENDENCIES): Add case for bfd_bpf_arch.
657 * configure: Regenerated.
658 * Makefile.am: Add rules for the files generated from cpu/bpf.cpu
659 and cpu/bpf.opc.
660 (HFILES): Add bpf-desc.h and bpf-opc.h.
661 (TARGET_LIBOPCODES_CFILES): Add bpf-asm.c, bpf-desc.c, bpf-dis.c,
662 bpf-ibld.c and bpf-opc.c.
663 (BPF_DEPS): Define.
664 * Makefile.in: Regenerated.
665 * disassemble.c (ARCH_bpf): Define.
666 (disassembler): Add case for bfd_arch_bpf.
667 (disassemble_init_for_target): Likewise.
668 (enum epbf_isa_attr): Define.
669 * disassemble.h: extern print_insn_bpf.
670 * bpf-asm.c: Generated.
671 * bpf-opc.h: Likewise.
672 * bpf-opc.c: Likewise.
673 * bpf-ibld.c: Likewise.
674 * bpf-dis.c: Likewise.
675 * bpf-desc.h: Likewise.
676 * bpf-desc.c: Likewise.
677
ba6cd17f
SD		 6782019-05-21 Sudakshina Das <sudi.das@arm.com>
679
680 * arm-dis.c (coprocessor_opcodes): New instructions for VMRS
681 and VMSR with the new operands.
682
e39c1607
SD		 6832019-05-21 Sudakshina Das <sudi.das@arm.com>
684
685 * arm-dis.c (enum mve_instructions): New enum
686 for csinc, csinv, csneg, csel, cset, csetm, cinv, cinv
687 and cneg.
688 (mve_opcodes): New instructions as above.
689 (is_mve_encoding_conflict): Add cases for csinc, csinv,
690 csneg and csel.
691 (print_insn_mve): Accept new %<bitfield>c and %<bitfield>C.
692
23d00a41
SD		 6932019-05-21 Sudakshina Das <sudi.das@arm.com>
694
695 * arm-dis.c (emun mve_instructions): Updated for new instructions.
696 (mve_opcodes): New instructions for asrl, lsll, lsrl, sqrshrl,
697 sqrshr, sqshl, sqshll, srshr, srshrl, uqrshll, uqrshl, uqshll,
698 uqshl, urshrl and urshr.
699 (is_mve_okay_in_it): Add new instructions to TRUE list.
700 (is_mve_unpredictable): Add cases for UNPRED_R13 and UNPRED_R15.
701 (print_insn_mve): Updated to accept new %j,
702 %<bitfield>m and %<bitfield>n patterns.
703
cd4797ee
FS		 7042019-05-21 Faraz Shahbazker <fshahbazker@wavecomp.com>
705
706 * mips-opc.c (mips_builtin_opcodes): Change source register
707 constraint for DAUI.
708
999b073b
NC		 7092019-05-20 Nick Clifton <nickc@redhat.com>
710
711 * po/fr.po: Updated French translation.
712
14b456f2
AV		 7132019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
714 Michael Collison <michael.collison@arm.com>
715
716 * arm-dis.c (thumb32_opcodes): Add new instructions.
717 (enum mve_instructions): Likewise.
718 (enum mve_undefined): Add new reasons.
719 (is_mve_encoding_conflict): Handle new instructions.
720 (is_mve_undefined): Likewise.
721 (is_mve_unpredictable): Likewise.
722 (print_mve_undefined): Likewise.
723 (print_mve_size): Likewise.
724
f49bb598
AV		 7252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
726 Michael Collison <michael.collison@arm.com>
727
728 * arm-dis.c (thumb32_opcodes): Add new instructions.
729 (enum mve_instructions): Likewise.
730 (is_mve_encoding_conflict): Handle new instructions.
731 (is_mve_undefined): Likewise.
732 (is_mve_unpredictable): Likewise.
733 (print_mve_size): Likewise.
734
56858bea
AV		 7352019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
736 Michael Collison <michael.collison@arm.com>
737
738 * arm-dis.c (thumb32_opcodes): Add new instructions.
739 (enum mve_instructions): Likewise.
740 (is_mve_encoding_conflict): Likewise.
741 (is_mve_unpredictable): Likewise.
742 (print_mve_size): Likewise.
743
e523f101
AV		 7442019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
745 Michael Collison <michael.collison@arm.com>
746
747 * arm-dis.c (thumb32_opcodes): Add new instructions.
748 (enum mve_instructions): Likewise.
749 (is_mve_encoding_conflict): Handle new instructions.
750 (is_mve_undefined): Likewise.
751 (is_mve_unpredictable): Likewise.
752 (print_mve_size): Likewise.
753
66dcaa5d
AV		 7542019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
755 Michael Collison <michael.collison@arm.com>
756
757 * arm-dis.c (thumb32_opcodes): Add new instructions.
758 (enum mve_instructions): Likewise.
759 (is_mve_encoding_conflict): Handle new instructions.
760 (is_mve_undefined): Likewise.
761 (is_mve_unpredictable): Likewise.
762 (print_mve_size): Likewise.
763 (print_insn_mve): Likewise.
764
d052b9b7
AV		 7652019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
766 Michael Collison <michael.collison@arm.com>
767
768 * arm-dis.c (thumb32_opcodes): Add new instructions.
769 (print_insn_thumb32): Handle new instructions.
770
ed63aa17
AV		 7712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
772 Michael Collison <michael.collison@arm.com>
773
774 * arm-dis.c (enum mve_instructions): Add new instructions.
775 (enum mve_undefined): Add new reasons.
776 (is_mve_encoding_conflict): Handle new instructions.
777 (is_mve_undefined): Likewise.
778 (is_mve_unpredictable): Likewise.
779 (print_mve_undefined): Likewise.
780 (print_mve_size): Likewise.
781 (print_mve_shift_n): Likewise.
782 (print_insn_mve): Likewise.
783
897b9bbc
AV		 7842019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
785 Michael Collison <michael.collison@arm.com>
786
787 * arm-dis.c (enum mve_instructions): Add new instructions.
788 (is_mve_encoding_conflict): Handle new instructions.
789 (is_mve_unpredictable): Likewise.
790 (print_mve_rotate): Likewise.
791 (print_mve_size): Likewise.
792 (print_insn_mve): Likewise.
793
1c8f2df8
AV		 7942019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
795 Michael Collison <michael.collison@arm.com>
796
797 * arm-dis.c (enum mve_instructions): Add new instructions.
798 (is_mve_encoding_conflict): Handle new instructions.
799 (is_mve_unpredictable): Likewise.
800 (print_mve_size): Likewise.
801 (print_insn_mve): Likewise.
802
d3b63143
AV		 8032019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
804 Michael Collison <michael.collison@arm.com>
805
806 * arm-dis.c (enum mve_instructions): Add new instructions.
807 (enum mve_undefined): Add new reasons.
808 (is_mve_encoding_conflict): Handle new instructions.
809 (is_mve_undefined): Likewise.
810 (is_mve_unpredictable): Likewise.
811 (print_mve_undefined): Likewise.
812 (print_mve_size): Likewise.
813 (print_insn_mve): Likewise.
814
14925797
AV		 8152019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
816 Michael Collison <michael.collison@arm.com>
817
818 * arm-dis.c (enum mve_instructions): Add new instructions.
819 (is_mve_encoding_conflict): Handle new instructions.
820 (is_mve_undefined): Likewise.
821 (is_mve_unpredictable): Likewise.
822 (print_mve_size): Likewise.
823 (print_insn_mve): Likewise.
824
c507f10b
AV		 8252019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
826 Michael Collison <michael.collison@arm.com>
827
828 * arm-dis.c (enum mve_instructions): Add new instructions.
829 (enum mve_unpredictable): Add new reasons.
830 (enum mve_undefined): Likewise.
831 (is_mve_okay_in_it): Handle new isntructions.
832 (is_mve_encoding_conflict): Likewise.
833 (is_mve_undefined): Likewise.
834 (is_mve_unpredictable): Likewise.
835 (print_mve_vmov_index): Likewise.
836 (print_simd_imm8): Likewise.
837 (print_mve_undefined): Likewise.
838 (print_mve_unpredictable): Likewise.
839 (print_mve_size): Likewise.
840 (print_insn_mve): Likewise.
841
bf0b396d
AV		 8422019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
843 Michael Collison <michael.collison@arm.com>
844
845 * arm-dis.c (enum mve_instructions): Add new instructions.
846 (enum mve_unpredictable): Add new reasons.
847 (enum mve_undefined): Likewise.
848 (is_mve_encoding_conflict): Handle new instructions.
849 (is_mve_undefined): Likewise.
850 (is_mve_unpredictable): Likewise.
851 (print_mve_undefined): Likewise.
852 (print_mve_unpredictable): Likewise.
853 (print_mve_rounding_mode): Likewise.
854 (print_mve_vcvt_size): Likewise.
855 (print_mve_size): Likewise.
856 (print_insn_mve): Likewise.
857
ef1576a1
AV		 8582019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
859 Michael Collison <michael.collison@arm.com>
860
861 * arm-dis.c (enum mve_instructions): Add new instructions.
862 (enum mve_unpredictable): Add new reasons.
863 (enum mve_undefined): Likewise.
864 (is_mve_undefined): Handle new instructions.
865 (is_mve_unpredictable): Likewise.
866 (print_mve_undefined): Likewise.
867 (print_mve_unpredictable): Likewise.
868 (print_mve_size): Likewise.
869 (print_insn_mve): Likewise.
870
aef6d006
AV		 8712019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
872 Michael Collison <michael.collison@arm.com>
873
874 * arm-dis.c (enum mve_instructions): Add new instructions.
875 (enum mve_undefined): Add new reasons.
876 (insns): Add new instructions.
877 (is_mve_encoding_conflict):
878 (print_mve_vld_str_addr): New print function.
879 (is_mve_undefined): Handle new instructions.
880 (is_mve_unpredictable): Likewise.
881 (print_mve_undefined): Likewise.
882 (print_mve_size): Likewise.
883 (print_insn_coprocessor_1): Handle MVE VLDR, VSTR instructions.
884 (print_insn_mve): Handle new operands.
885
04d54ace
AV		 8862019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
887 Michael Collison <michael.collison@arm.com>
888
889 * arm-dis.c (enum mve_instructions): Add new instructions.
890 (enum mve_unpredictable): Add new reasons.
891 (is_mve_encoding_conflict): Handle new instructions.
892 (is_mve_unpredictable): Likewise.
893 (mve_opcodes): Add new instructions.
894 (print_mve_unpredictable): Handle new reasons.
895 (print_mve_register_blocks): New print function.
896 (print_mve_size): Handle new instructions.
897 (print_insn_mve): Likewise.
898
9743db03
AV		 8992019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
900 Michael Collison <michael.collison@arm.com>
901
902 * arm-dis.c (enum mve_instructions): Add new instructions.
903 (enum mve_unpredictable): Add new reasons.
904 (enum mve_undefined): Likewise.
905 (is_mve_encoding_conflict): Handle new instructions.
906 (is_mve_undefined): Likewise.
907 (is_mve_unpredictable): Likewise.
908 (coprocessor_opcodes): Move NEON VDUP from here...
909 (neon_opcodes): ... to here.
910 (mve_opcodes): Add new instructions.
911 (print_mve_undefined): Handle new reasons.
912 (print_mve_unpredictable): Likewise.
913 (print_mve_size): Handle new instructions.
914 (print_insn_neon): Handle vdup.
915 (print_insn_mve): Handle new operands.
916
143275ea
AV		 9172019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
918 Michael Collison <michael.collison@arm.com>
919
920 * arm-dis.c (enum mve_instructions): Add new instructions.
921 (enum mve_unpredictable): Add new values.
922 (mve_opcodes): Add new instructions.
923 (vec_condnames): New array with vector conditions.
924 (mve_predicatenames): New array with predicate suffixes.
925 (mve_vec_sizename): New array with vector sizes.
926 (enum vpt_pred_state): New enum with vector predication states.
927 (struct vpt_block): New struct type for vpt blocks.
928 (vpt_block_state): Global struct to keep track of state.
929 (mve_extract_pred_mask): New helper function.
930 (num_instructions_vpt_block): Likewise.
931 (mark_outside_vpt_block): Likewise.
932 (mark_inside_vpt_block): Likewise.
933 (invert_next_predicate_state): Likewise.
934 (update_next_predicate_state): Likewise.
935 (update_vpt_block_state): Likewise.
936 (is_vpt_instruction): Likewise.
937 (is_mve_encoding_conflict): Add entries for new instructions.
938 (is_mve_unpredictable): Likewise.
939 (print_mve_unpredictable): Handle new cases.
940 (print_instruction_predicate): Likewise.
941 (print_mve_size): New function.
942 (print_vec_condition): New function.
943 (print_insn_mve): Handle vpt blocks and new print operands.
944
f08d8ce3
AV		 9452019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
946
947 * arm-dis.c (print_insn_coprocessor_1): Disable the use of coprocessors
948 8, 14 and 15 for Armv8.1-M Mainline.
949
73cd51e5
AV		 9502019-05-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
951 Michael Collison <michael.collison@arm.com>
952
953 * arm-dis.c (enum mve_instructions): New enum.
954 (enum mve_unpredictable): Likewise.
955 (enum mve_undefined): Likewise.
956 (struct mopcode32): New struct.
957 (is_mve_okay_in_it): New function.
958 (is_mve_architecture): Likewise.
959 (arm_decode_field): Likewise.
960 (arm_decode_field_multiple): Likewise.
961 (is_mve_encoding_conflict): Likewise.
962 (is_mve_undefined): Likewise.
963 (is_mve_unpredictable): Likewise.
964 (print_mve_undefined): Likewise.
965 (print_mve_unpredictable): Likewise.
966 (print_insn_coprocessor_1): Use arm_decode_field_multiple.
967 (print_insn_mve): New function.
968 (print_insn_thumb32): Handle MVE architecture.
969 (select_arm_features): Force thumb for Armv8.1-m Mainline.
970
3076e594
NC		 9712019-05-10 Nick Clifton <nickc@redhat.com>
972
973 PR 24538
974 * ia64-opc.c (ia64_find_matching_opcode): Check for reaching the
975 end of the table prematurely.
976
387e7624
FS		 9772019-05-10 Faraz Shahbazker <fshahbazker@wavecomp.com>
978
979 * mips-opc.c (mips_opcodes): Enable ADD, SUB, DADD and DSUB
980 macros for R6.
981
0067be51
AM		 9822019-05-11 Alan Modra <amodra@gmail.com>
983
984 * ppc-dis.c (print_insn_powerpc) Don't skip optional operands
985 when -Mraw is in effect.
986
42e6288f
MM		 9872019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
988
989 * aarch64-dis-2.c: Regenerate.
990 * aarch64-tbl.h (OP_SVE_BBU): New variant set.
991 (OP_SVE_BBB): New variant set.
992 (OP_SVE_DDDD): New variant set.
993 (OP_SVE_HHH): New variant set.
994 (OP_SVE_HHHU): New variant set.
995 (OP_SVE_SSS): New variant set.
996 (OP_SVE_SSSU): New variant set.
997 (OP_SVE_SHH): New variant set.
998 (OP_SVE_SBBU): New variant set.
999 (OP_SVE_DSS): New variant set.
1000 (OP_SVE_DHHU): New variant set.
1001 (OP_SVE_VMV_HSD_BHS): New variant set.
1002 (OP_SVE_VVU_HSD_BHS): New variant set.
1003 (OP_SVE_VVVU_SD_BH): New variant set.
1004 (OP_SVE_VVVU_BHSD): New variant set.
1005 (OP_SVE_VVV_QHD_DBS): New variant set.
1006 (OP_SVE_VVV_HSD_BHS): New variant set.
1007 (OP_SVE_VVV_HSD_BHS2): New variant set.
1008 (OP_SVE_VVV_BHS_HSD): New variant set.
1009 (OP_SVE_VV_BHS_HSD): New variant set.
1010 (OP_SVE_VVV_SD): New variant set.
1011 (OP_SVE_VVU_BHS_HSD): New variant set.
1012 (OP_SVE_VZVV_SD): New variant set.
1013 (OP_SVE_VZVV_BH): New variant set.
1014 (OP_SVE_VZV_SD): New variant set.
1015 (aarch64_opcode_table): Add sve2 instructions.
1016
28ed815a
MM		 10172019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1018
1019 * aarch64-asm-2.c: Regenerated.
1020 * aarch64-dis-2.c: Regenerated.
1021 * aarch64-opc-2.c: Regenerated.
1022 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1023 for SVE_SHLIMM_UNPRED_22.
1024 (aarch64_print_operand): Add printing for SVE_SHLIMM_UNPRED_22.
1025 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHLIMM_UNPRED_22
1026 operand.
1027
fd1dc4a0
MM		 10282019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1029
1030 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1031 sve_size_tsz_bhs iclass encode.
1032 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1033 sve_size_tsz_bhs iclass decode.
1034
31e36ab3
MM		 10352019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1036
1037 * aarch64-asm-2.c: Regenerated.
1038 * aarch64-dis-2.c: Regenerated.
1039 * aarch64-opc-2.c: Regenerated.
1040 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1041 for SVE_Zm4_11_INDEX.
1042 (aarch64_print_operand): Add printing for SVE_Zm4_11_INDEX.
1043 (fields): Handle SVE_i2h field.
1044 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i2h field.
1045 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm4_11_INDEX operand.
1046
1be5f94f
MM		 10472019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1048
1049 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1050 sve_shift_tsz_bhsd iclass encode.
1051 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1052 sve_shift_tsz_bhsd iclass decode.
1053
3c17238b
MM		 10542019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1055
1056 * aarch64-asm-2.c: Regenerated.
1057 * aarch64-dis-2.c: Regenerated.
1058 * aarch64-opc-2.c: Regenerated.
1059 * aarch64-asm.c (aarch64_ins_sve_shrimm):
1060 (aarch64_encode_variant_using_iclass): Handle
1061 sve_shift_tsz_hsd iclass encode.
1062 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1063 sve_shift_tsz_hsd iclass decode.
1064 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1065 for SVE_SHRIMM_UNPRED_22.
1066 (aarch64_print_operand): Add printing for SVE_SHRIMM_UNPRED_22.
1067 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_SHRIMM_UNPRED_22
1068 operand.
1069
cd50a87a
MM		 10702019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1071
1072 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1073 sve_size_013 iclass encode.
1074 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1075 sve_size_013 iclass decode.
1076
3c705960
MM		 10772019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1078
1079 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1080 sve_size_bh iclass encode.
1081 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1082 sve_size_bh iclass decode.
1083
0a57e14f
MM		 10842019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1085
1086 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1087 sve_size_sd2 iclass encode.
1088 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1089 sve_size_sd2 iclass decode.
1090 * aarch64-opc.c (fields): Handle SVE_sz2 field.
1091 * aarch64-opc.h (enum aarch64_field_kind): New SVE_sz2 field.
1092
c469c864
MM		 10932019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1094
1095 * aarch64-asm-2.c: Regenerated.
1096 * aarch64-dis-2.c: Regenerated.
1097 * aarch64-opc-2.c: Regenerated.
1098 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1099 for SVE_ADDR_ZX.
1100 (aarch64_print_operand): Add printing for SVE_ADDR_ZX.
1101 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_ADDR_ZX operand.
1102
116adc27
MM		 11032019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1104
1105 * aarch64-asm-2.c: Regenerated.
1106 * aarch64-dis-2.c: Regenerated.
1107 * aarch64-opc-2.c: Regenerated.
1108 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1109 for SVE_Zm3_11_INDEX.
1110 (aarch64_print_operand): Add printing for SVE_Zm3_11_INDEX.
1111 (fields): Handle SVE_i3l and SVE_i3h2 fields.
1112 * aarch64-opc.h (enum aarch64_field_kind): New SVE_i3l and SVE_i3h2
1113 fields.
1114 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_Zm3_11_INDEX operand.
1115
3bd82c86
MM		 11162019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1117
1118 * aarch64-asm.c (aarch64_encode_variant_using_iclass): Handle
1119 sve_size_hsd2 iclass encode.
1120 * aarch64-dis.c (aarch64_decode_variant_using_iclass): Handle
1121 sve_size_hsd2 iclass decode.
1122 * aarch64-opc.c (fields): Handle SVE_size field.
1123 * aarch64-opc.h (enum aarch64_field_kind): New SVE_size field.
1124
adccc507
MM		 11252019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1126
1127 * aarch64-asm-2.c: Regenerated.
1128 * aarch64-dis-2.c: Regenerated.
1129 * aarch64-opc-2.c: Regenerated.
1130 * aarch64-opc.c (operand_general_constraint_met_p): Constraint checking
1131 for SVE_IMM_ROT3.
1132 (aarch64_print_operand): Add printing for SVE_IMM_ROT3.
1133 (fields): Handle SVE_rot3 field.
1134 * aarch64-opc.h (enum aarch64_field_kind): New SVE_rot3 field.
1135 * aarch64-tbl.h (AARCH64_OPERANDS): Use new SVE_IMM_ROT3 operand.
1136
5cd99750
MM		 11372019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1138
1139 * aarch64-opc.c (verify_constraints): Check for movprfx for sve2
1140 instructions.
1141
7ce2460a
MM		 11422019-05-09 Matthew Malcomson <matthew.malcomson@arm.com>
1143
1144 * aarch64-tbl.h
1145 (aarch64_feature_sve2, aarch64_feature_sve2aes,
1146 aarch64_feature_sve2sha3, aarch64_feature_sve2sm4,
1147 aarch64_feature_sve2bitperm): New feature sets.
1148 (SVE2, SVE2_AES, SVE2_SHA3, SVE2_SM4, SVE2_BITPERM): New macros
1149 for feature set addresses.
1150 (SVE2_INSN, SVE2_INSNC, SVE2AES_INSN, SVE2SHA3_INSN,
1151 SVE2SM4_INSN, SVE2SM4_INSNC, SVE2BITPERM_INSN): New macros.
1152
41cee089
FS		 11532019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
1154 Faraz Shahbazker <fshahbazker@wavecomp.com>
1155
1156 * mips-dis.c (mips_calculate_combination_ases): Add ISA
1157 argument and set ASE_EVA_R6 appropriately.
1158 (set_default_mips_dis_options): Pass ISA to above.
1159 (parse_mips_dis_option): Likewise.
1160 * mips-opc.c (EVAR6): New macro.
1161 (mips_builtin_opcodes): Add llwpe, scwpe.
1162
b83b4b13
SD		 11632019-05-01 Sudakshina Das <sudi.das@arm.com>
1164
1165 * aarch64-asm-2.c: Regenerated.
1166 * aarch64-dis-2.c: Regenerated.
1167 * aarch64-opc-2.c: Regenerated.
1168 * aarch64-opc.c (operand_general_constraint_met_p): Add case for
1169 AARCH64_OPND_TME_UIMM16.
1170 (aarch64_print_operand): Likewise.
1171 * aarch64-tbl.h (QL_IMM_NIL): New.
1172 (TME): New.
1173 (_TME_INSN): New.
1174 (struct aarch64_opcode): Add tstart, tcommit, ttest and tcancel.
1175
4a90ce95
JD		 11762019-04-29 John Darrington <john@darrington.wattle.id.au>
1177
1178 * s12z-opc.c (shift_discrim): Return OP_INVALID when reading fails.
1179
a45328b9
AB		 11802019-04-26 Andrew Bennett <andrew.bennett@imgtec.com>
1181 Faraz Shahbazker <fshahbazker@wavecomp.com>
1182
1183 * mips-opc.c (mips_builtin_opcodes): Add llwp, lldp, scwp, scdp.
1184
d10be0cb
JD		 11852019-04-24 John Darrington <john@darrington.wattle.id.au>
1186
1187 * s12z-opc.h: Add extern "C" bracketing to help
1188 users who wish to use this interface in c++ code.
1189
a679f24e
JD		 11902019-04-24 John Darrington <john@darrington.wattle.id.au>
1191
1192 * s12z-opc.c (bm_decode): Handle bit map operations with the
1193 "reserved0" mode.
1194
32c36c3c
AV		 11952019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1196
1197 * arm-dis.c (coprocessor_opcodes): Document new %J and %K format
1198 specifier. Add entries for VLDR and VSTR of system registers.
1199 (print_insn_coprocessor): Forbid coprocessor numbers 8, 14 and 15 in
1200 coprocessor instructions on Armv8.1-M Mainline targets. Add handling
1201 of %J and %K format specifier.
1202
efd6b359
AV		 12032019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1204
1205 * arm-dis.c (coprocessor_opcodes): Document new %C format control code.
1206 Add new entries for VSCCLRM instruction.
1207 (print_insn_coprocessor): Handle new %C format control code.
1208
6b0dd094
AV		 12092019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1210
1211 * arm-dis.c (enum isa): New enum.
1212 (struct sopcode32): New structure.
1213 (coprocessor_opcodes): change type of entries to struct sopcode32 and
1214 set isa field of all current entries to ANY.
1215 (print_insn_coprocessor): Change type of insn to struct sopcode32.
1216 Only match an entry if its isa field allows the current mode.
1217
4b5a202f
AV		 12182019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1219
1220 * arm-dis.c (thumb_opcodes): Document %n control code. Add entry for
1221 CLRM.
1222 (print_insn_thumb32): Add logic to print %n CLRM register list.
1223
60f993ce
AV		 12242019-04-15 Sudakshina Das <sudi.das@arm.com>
1225
1226 * arm-dis.c (print_insn_thumb32): Updated to accept new %P
1227 and %Q patterns.
1228
f6b2b12d
AV		 12292019-04-15 Sudakshina Das <sudi.das@arm.com>
1230
1231 * arm-dis.c (thumb32_opcodes): New instruction bfcsel.
1232 (print_insn_thumb32): Edit the switch case for %Z.
1233
1889da70
AV		 12342019-04-15 Sudakshina Das <sudi.das@arm.com>
1235
1236 * arm-dis.c (print_insn_thumb32): Updated to accept new %Z pattern.
1237
65d1bc05
AV		 12382019-04-15 Sudakshina Das <sudi.das@arm.com>
1239
1240 * arm-dis.c (thumb32_opcodes): New instruction bfl.
1241
1caf72a5
AV		 12422019-04-15 Sudakshina Das <sudi.das@arm.com>
1243
1244 * arm-dis.c (print_insn_thumb32): Updated to accept new %Y pattern.
1245
f1c7f421
AV		 12462019-04-15 Sudakshina Das <sudi.das@arm.com>
1247
1248 * arm-dis.c (print_insn_thumb32): Add '%<bitfield>S' to print an
1249 Arm register with r13 and r15 unpredictable.
1250 (thumb32_opcodes): New instructions for bfx and bflx.
1251
4389b29a
AV		 12522019-04-15 Sudakshina Das <sudi.das@arm.com>
1253
1254 * arm-dis.c (thumb32_opcodes): New instructions for bf.
1255
e5d6e09e
AV		 12562019-04-15 Sudakshina Das <sudi.das@arm.com>
1257
1258 * arm-dis.c (print_insn_thumb32): Updated to accept new %W pattern.
1259
e12437dc
AV		 12602019-04-15 Sudakshina Das <sudi.das@arm.com>
1261
1262 * arm-dis.c (print_insn_thumb32): Updated to accept new %G pattern.
1263
031254f2
AV		 12642019-04-15 Thomas Preud'homme <thomas.preudhomme@arm.com>
1265
1266 * arm-dis.c (select_arm_features): Add logic for Armv8.1-M Mainline.
1267
e5a557ac
JD		 12682019-04-12 John Darrington <john@darrington.wattle.id.au>
1269
1270 s12z-dis.c, s12z-opc.c, s12z-opc.h: Replace "operator" with
1271 "optr". ("operator" is a reserved word in c++).
1272
bd7ceb8d
SD		 12732019-04-11 Sudakshina Das <sudi.das@arm.com>
1274
1275 * aarch64-opc.c (aarch64_print_operand): Add case for
1276 AARCH64_OPND_Rt_SP.
1277 (verify_constraints): Likewise.
1278 * aarch64-tbl.h (QL_LDST_AT): Update to add SP qualifier.
1279 (struct aarch64_opcode): Update stg, stzg, st2g, stz2g instructions
1280 to accept Rt|SP as first operand.
1281 (AARCH64_OPERANDS): Add new Rt_SP.
1282 * aarch64-asm-2.c: Regenerated.
1283 * aarch64-dis-2.c: Regenerated.
1284 * aarch64-opc-2.c: Regenerated.
1285
e54010f1
SD		 12862019-04-11 Sudakshina Das <sudi.das@arm.com>
1287
1288 * aarch64-asm-2.c: Regenerated.
1289 * aarch64-dis-2.c: Likewise.
1290 * aarch64-opc-2.c: Likewise.
1291 * aarch64-tbl.h (aarch64_opcode): Add new ldgm and stgm.
1292
7e96e219
RS		 12932019-04-09 Robert Suchanek <robert.suchanek@mips.com>
1294
1295 * mips-opc.c (mips_builtin_opcodes): Add RDHWR rt rd sel.
1296
6f2791d5
L		 12972019-04-08 H.J. Lu <hongjiu.lu@intel.com>
1298
1299 * i386-opc.tbl: Consolidate AVX512 BF16 entries.
1300 * i386-init.h: Regenerated.
1301
e392bad3
AM		 13022019-04-07 Alan Modra <amodra@gmail.com>
1303
1304 * ppc-dis.c (print_insn_powerpc): Use a tiny state machine
1305 op_separator to control printing of spaces, comma and parens
1306 rather than need_comma, need_paren and spaces vars.
1307
dffaa15c
AM		 13082019-04-07 Alan Modra <amodra@gmail.com>
1309
1310 PR 24421
1311 * arm-dis.c (print_insn_coprocessor): Correct bracket placement.
1312 (print_insn_neon, print_insn_arm): Likewise.
1313
d6aab7a1
XG		 13142019-04-05 Xuepeng Guo <xuepeng.guo@intel.com>
1315
1316 * i386-dis-evex.h (evex_table): Updated to support BF16
1317 instructions.
1318 * i386-dis.c (enum): Add EVEX_W_0F3852_P_1, EVEX_W_0F3872_P_1
1319 and EVEX_W_0F3872_P_3.
1320 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BF16_FLAGS.
1321 (cpu_flags): Add bitfield for CpuAVX512_BF16.
1322 * i386-opc.h (enum): Add CpuAVX512_BF16.
1323 (i386_cpu_flags): Add bitfield for cpuavx512_bf16.
1324 * i386-opc.tbl: Add AVX512 BF16 instructions.
1325 * i386-init.h: Regenerated.
1326 * i386-tbl.h: Likewise.
1327
66e85460
AM		 13282019-04-05 Alan Modra <amodra@gmail.com>
1329
1330 * ppc-opc.c (XLBH_MASK): Subtract off BH field from BB_MASK.
1331 (powerpc_opcodes): Reorder bcctr and bclr extended mnemonics
1332 to favour printing of "-" branch hint when using the "y" bit.
1333 Allow BH field on bc{ctr,lr,tar}{,l}{-,+}.
1334
c2b1c275
AM		 13352019-04-05 Alan Modra <amodra@gmail.com>
1336
1337 * ppc-dis.c (print_insn_powerpc): Delay printing spaces after
1338 opcode until first operand is output.
1339
aae9718e
PB		 13402019-04-04 Peter Bergner <bergner@linux.ibm.com>
1341
1342 PR gas/24349
1343 * ppc-opc.c (valid_bo_pre_v2): Add comments.
1344 (valid_bo_post_v2): Add support for 'at' branch hints.
1345 (insert_bo): Only error on branch on ctr.
1346 (get_bo_hint_mask): New function.
1347 (insert_boe): Add new 'branch_taken' formal argument. Add support
1348 for inserting 'at' branch hints.
1349 (extract_boe): Add new 'branch_taken' formal argument. Add support
1350 for extracting 'at' branch hints.
1351 (insert_bom, extract_bom, insert_bop, extract_bop): New functions.
1352 (BOE): Delete operand.
1353 (BOM, BOP): New operands.
1354 (RM): Update value.
1355 (XLYLK, XLYLK_MASK, XLYBB_MASK): Delete.
1356 (powerpc_opcodes) <bc-, bcl-, bca-, bcla-, bclr-, bclrl-, bcctr-,
1357 bcctrl-, bctar-, bctarl->: Replace BOE with BOM.
1358 (powerpc_opcodes) <bc+, bcl+, bca+, bcla+, bclr+, bclrl+, bcctr+,
1359 bcctrl+, bctar+, bctarl+>: Replace BOE with BOP.
1360 <bdnztar, bdnztarl, bdztar, bdztarl, btar, btarl, bdnztar-, bdnztarl-,
1361 bdnztar+, bdnztarl+, bdztar-, bdztarl-, bdztar+, bdztarl+, bgetar,
1362 bnltar, bgetarl, bnltarl, bletar, bngtar, bletarl, bngtarl, bnetar,
1363 bnetarl, bnstar, bnutar, bnstarl, bnutarl, bgetar-, bnltar-, bgetarl-,
1364 bnltarl-, bletar-, bngtar-, bletarl-, bngtarl-, bnetar-, bnetarl-,
1365 bnstar-, bnutar-, bnstarl-, bnutarl-, bgetar+, bnltar+, bgetarl+,
1366 bnltarl+, bletar+, bngtar+, bletarl+, bngtarl+, bnetar+, bnetarl+,
1367 bnstar+, bnutar+, bnstarl+, bnutarl+, blttar, blttarl, bgttar, bgttarl,
1368 beqtar, beqtarl, bsotar, buntar, bsotarl, buntarl, blttar-, blttarl-,
1369 bgttar-, bgttarl-, beqtar-, beqtarl-, bsotar-, buntar-, bsotarl-,
1370 buntarl-, blttar+, blttarl+, bgttar+, bgttarl+, beqtar+, beqtarl+,
1371 bsotar+, buntar+, bsotarl+, buntarl+, bdnzftar, bdnzftarl, bdzftar,
1372 bdzftarl, bftar, bftarl, bftar-, bftarl-, bftar+, bftarl+, bdnzttar,
1373 bdnzttarl, bdzttar, bdzttarl, bttar, bttarl, bttar-, bttarl-, bttar+,
1374 bttarl+>: New extended mnemonics.
1375
96a86c01
AM		 13762019-03-28 Alan Modra <amodra@gmail.com>
1377
1378 PR 24390
1379 * ppc-opc.c (BTF): Define.
1380 (powerpc_opcodes): Use for mtfsb*.
1381 * ppc-dis.c (print_insn_powerpc): Print fields with both
1382 PPC_OPERAND_CR_REG and PPC_OPERAND_CR_BIT as a plain number.
1383
796d6298
TC		 13842019-03-25 Tamar Christina <tamar.christina@arm.com>
1385
1386 * arm-dis.c (struct arm_private_data): Remove has_mapping_symbols.
1387 (mapping_symbol_for_insn): Implement new algorithm.
1388 (print_insn): Remove duplicate code.
1389
60df3720
TC		 13902019-03-25 Tamar Christina <tamar.christina@arm.com>
1391
1392 * aarch64-dis.c (print_insn_aarch64):
1393 Implement override.
1394
51457761
TC		 13952019-03-25 Tamar Christina <tamar.christina@arm.com>
1396
1397 * aarch64-dis.c (print_insn_aarch64): Update the mapping symbol search
1398 order.
1399
53b2f36b
TC		 14002019-03-25 Tamar Christina <tamar.christina@arm.com>
1401
1402 * aarch64-dis.c (last_stop_offset): New.
1403 (print_insn_aarch64): Use stop_offset.
1404
89199bb5
L		 14052019-03-19 H.J. Lu <hongjiu.lu@intel.com>
1406
1407 PR gas/24359
1408 * i386-gen.c (cpu_flag_init): Add CPU_ANY_AVX512F_FLAGS to
1409 CPU_ANY_AVX2_FLAGS.
1410 * i386-init.h: Regenerated.
1411
97ed31ae
L		 14122019-03-18 H.J. Lu <hongjiu.lu@intel.com>
1413
1414 PR gas/24348
1415 * i386-opc.tbl: Add Optimize to vmovdqa32, vmovdqa64, vmovdqu8,
1416 vmovdqu16, vmovdqu32 and vmovdqu64.
1417 * i386-tbl.h: Regenerated.
1418
0919bfe9
AK		 14192019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1420
1421 * s390-opc.txt: Rename selhhhr to selfhr. Remove optional operand
1422 from vstrszb, vstrszh, and vstrszf.
1423
14242019-03-12 Andreas Krebbel <krebbel@linux.ibm.com>
1425
1426 * s390-opc.txt: Add instruction descriptions.
1427
21820ebe
JW		 14282019-02-08 Jim Wilson <jimw@sifive.com>
1429
1430 * riscv-opc.c (riscv_opcodes) <beq>: Use Cz to compress 3 operand form.
1431 <bne>: Likewise.
1432
f7dd2fb2
TC		 14332019-02-07 Tamar Christina <tamar.christina@arm.com>
1434
1435 * arm-dis.c (arm_opcodes): Redefine hlt to armv1.
1436
6456d318
TC		 14372019-02-07 Tamar Christina <tamar.christina@arm.com>
1438
1439 PR binutils/23212
1440 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_sz.
1441 * aarch64-opc.c (verify_elem_sd): New.
1442 (fields): Add FLD_sz entr.
1443 * aarch64-tbl.h (_SIMD_INSN): New.
1444 (aarch64_opcode_table): Add elem_sd verifier to fmla, fmls, fmul and
1445 fmulx scalar and vector by element isns.
1446
4a83b610
NC		 14472019-02-07 Nick Clifton <nickc@redhat.com>
1448
1449 * po/sv.po: Updated Swedish translation.
1450
fc60b8c8
AK		 14512019-01-31 Andreas Krebbel <krebbel@linux.ibm.com>
1452
1453 * s390-mkopc.c (main): Accept arch13 as cpu string.
1454 * s390-opc.c: Add new instruction formats and instruction opcode
1455 masks.
1456 * s390-opc.txt: Add new arch13 instructions.
1457
e10620d3
TC		 14582019-01-25 Sudakshina Das <sudi.das@arm.com>
1459
1460 * aarch64-tbl.h (QL_LDST_AT): Update macro.
1461 (aarch64_opcode): Change encoding for stg, stzg
1462 st2g and st2zg.
1463 * aarch64-asm-2.c: Regenerated.
1464 * aarch64-dis-2.c: Regenerated.
1465 * aarch64-opc-2.c: Regenerated.
1466
20a4ca55
SD		 14672019-01-25 Sudakshina Das <sudi.das@arm.com>
1468
1469 * aarch64-asm-2.c: Regenerated.
1470 * aarch64-dis-2.c: Likewise.
1471 * aarch64-opc-2.c: Likewise.
1472 * aarch64-tbl.h (aarch64_opcode): Add new stzgm.
1473
550fd7bf
SD		 14742019-01-25 Sudakshina Das <sudi.das@arm.com>
1475 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1476
1477 * aarch64-asm.c (aarch64_ins_addr_simple_2): Remove.
1478 * aarch64-asm.h (ins_addr_simple_2): Likeiwse.
1479 * aarch64-dis.c (aarch64_ext_addr_simple_2): Likewise.
1480 * aarch64-dis.h (ext_addr_simple_2): Likewise.
1481 * aarch64-opc.c (operand_general_constraint_met_p): Remove
1482 case for ldstgv_indexed.
1483 (aarch64_print_operand): Remove case for AARCH64_OPND_ADDR_SIMPLE_2.
1484 * aarch64-tbl.h (struct aarch64_opcode): Remove ldgv and stgv.
1485 (AARCH64_OPERANDS): Remove ADDR_SIMPLE_2.
1486 * aarch64-asm-2.c: Regenerated.
1487 * aarch64-dis-2.c: Regenerated.
1488 * aarch64-opc-2.c: Regenerated.
1489
d9938630
NC		 14902019-01-23 Nick Clifton <nickc@redhat.com>
1491
1492 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1493
375cd423
NC		 14942019-01-21 Nick Clifton <nickc@redhat.com>
1495
1496 * po/de.po: Updated German translation.
1497 * po/uk.po: Updated Ukranian translation.
1498
57299f48
CX		 14992019-01-20 Chenghua Xu <paul.hua.gm@gmail.com>
1500 * mips-dis.c (mips_arch_choices): Fix typo in
1501 gs464, gs464e and gs264e descriptors.
1502
f48dfe41
NC		 15032019-01-19 Nick Clifton <nickc@redhat.com>
1504
1505 * configure: Regenerate.
1506 * po/opcodes.pot: Regenerate.
1507
f974f26c
NC		 15082018-06-24 Nick Clifton <nickc@redhat.com>
1509
1510 2.32 branch created.
1511
39f286cd
JD		 15122019-01-09 John Darrington <john@darrington.wattle.id.au>
1513
448b8ca8
JD		 1514 * s12z-dis.c (print_insn_s12z): Do not dereference an operand
1515 if it is null.
1516 -dis.c (opr_emit_disassembly): Do not omit an index if it is
39f286cd
JD		 1517 zero.
1518
3107326d
AP		 15192019-01-09 Andrew Paprocki <andrew@ishiboo.com>
1520
1521 * configure: Regenerate.
1522
7e9ca91e
AM		 15232019-01-07 Alan Modra <amodra@gmail.com>
1524
1525 * configure: Regenerate.
1526 * po/POTFILES.in: Regenerate.
1527
ef1ad42b
JD		 15282019-01-03 John Darrington <john@darrington.wattle.id.au>
1529
1530 * s12z-opc.c: New file.
1531 * s12z-opc.h: New file.
1532 * s12z-dis.c: Removed all code not directly related to display
1533 of instructions. Used the interface provided by the new files
1534 instead.
1535 * Makefile.am (TARGET_LIBOPCODES_CFILES) Add s12z-opc.c.
7e9ca91e 1536 * Makefile.in: Regenerate.
ef1ad42b 1537 * configure.ac (bfd_s12z_arch): Correct the dependencies.
7e9ca91e 1538 * configure: Regenerate.
ef1ad42b 1539
82704155
AM		 15402019-01-01 Alan Modra <amodra@gmail.com>
1541
1542 Update year range in copyright notice of all files.
1543
d5c04e1b 1544For older changes see ChangeLog-2018
3499769a 1545\f
d5c04e1b 1546Copyright (C) 2019 Free Software Foundation, Inc.
3499769a
AM		 1547
1548Copying and distribution of this file, with or without modification,
1549are permitted in any medium without royalty provided the copyright
1550notice and this notice are preserved.
1551
1552Local Variables:
1553mode: change-log
1554left-margin: 8
1555fill-column: 74
1556version-control: never
1557End:
A mirror of the official binutils-gdb repository