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opcodes: cleanup nds32 variables
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
9b2beaf7
MF		 12021-07-01 Mike Frysinger <vapier@gentoo.org>
2
3 * nds32-asm.c (operand_fields): Rename to ...
4 (nds32_operand_fields): ... this.
5 (keyword_gpr): Rename to ...
6 (nds32_keyword_gpr): ... this.
7 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
8 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
9 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
10 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
11 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
12 Mark static.
13 (keywords): Rename to ...
14 (nds32_keywords): ... this.
15 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
16 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
17
ac8ef696
MF		 182021-07-01 Mike Frysinger <vapier@gentoo.org>
19
20 * z80-dis.c (opc_ed): Make const.
21 (pref_ed): Make p const.
22
52b83874
MF		 232021-07-01 Mike Frysinger <vapier@gentoo.org>
24
25 * microblaze-dis.c (get_field_special): Make op const.
26 (read_insn_microblaze): Make opr & op const. Rename opcodes to
27 microblaze_opcodes.
28 (print_insn_microblaze): Make op & pop const.
29 (get_insn_microblaze): Make op const. Rename opcodes to
30 microblaze_opcodes.
31 (microblaze_get_target_address): Likewise.
32 * microblaze-opc.h (struct op_code_struct): Make const.
33 Rename opcodes to microblaze_opcodes.
34
6c2ede01
MF		 352021-07-01 Mike Frysinger <vapier@gentoo.org>
36
37 * aarch64-gen.c (aarch64_opcode_table): Add const.
38 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
39
46b8b3d6
AB		 402021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
41
42 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
43 available.
44
ded5cb94
AM		 452021-06-22 Alan Modra <amodra@gmail.com>
46
47 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
48 print separator for pcrel insns.
49
47399e9c
AM		 502021-06-19 Alan Modra <amodra@gmail.com>
51
52 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
53
d984392e
AM		 542021-06-19 Alan Modra <amodra@gmail.com>
55
56 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
57 entire buffer.
58
7993124e
AM		 592021-06-17 Alan Modra <amodra@gmail.com>
60
61 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
62 in table.
63
a38d1396
AM		 642021-06-03 Alan Modra <amodra@gmail.com>
65
66 PR 1202
67 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
68 Use unsigned int for inst.
69
8f467114
SV		 702021-06-02 Shahab Vahedi <shahab@synopsys.com>
71
72 * arc-dis.c (arc_option_arg_t): New enumeration.
73 (arc_options): New variable.
74 (disassembler_options_arc): New function.
75 (print_arc_disassembler_options): Reimplement in terms of
76 "disassembler_options_arc".
77
1ff6a3b8
AM		 782021-05-29 Alan Modra <amodra@gmail.com>
79
80 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
81 Don't special case PPC_OPCODE_RAW.
82 (lookup_prefix): Likewise.
83 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
84 (print_insn_powerpc): ..update caller.
85 * ppc-opc.c (EXT): Define.
86 (powerpc_opcodes): Mark extended mnemonics with EXT.
87 (prefix_opcodes, vle_opcodes): Likewise.
88 (XISEL, XISEL_MASK): Add cr field and simplify.
89 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
90 all isel variants to where the base mnemonic belongs. Sort dstt,
91 dststt and dssall.
92
49149d59
MR		 932021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
94
95 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
96 COP3 opcode instructions.
97
9573a461
MR		 982021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
99
100 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
101 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
102 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
103 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
104 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
105 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
106 "cop2", and "cop3" entries.
107
fa495743
MR		 1082021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
109
110 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
111 entries and associated comments.
112
b930964c
MR		 1132021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
114
115 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
116 of "c0".
117
dd844468
MR		 1182021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
119
120 * mips-dis.c (mips_cp1_names_mips): New variable.
121 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
122 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
123 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
124 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
125 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
126 "loongson2f".
127
9204ccd4
MR		 1282021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
129
130 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
131 handling code over to...
132 <OP_REG_CONTROL>: ... this new case.
133 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
134 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
135 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
136 replacing the `G' operand code with `g'. Update "cftc1" and
137 "cftc2" entries replacing the `E' operand code with `y'.
138 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
139 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
140 entries replacing the `G' operand code with `g'.
141
a3fb396f
MR		 1422021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
143
144 * mips-dis.c (mips_cp0_names_r3900): New variable.
145 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
146 for "r3900".
147
cccc84fa
MR		 1482021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
149
150 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
151 and "mtthc2" to using the `G' rather than `g' operand code for
152 the coprocessor control register referred.
153
c9de3168
MR		 1542021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
155
156 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
157 entries with each other.
158
ebcab741
PB		 1592021-05-27 Peter Bergner <bergner@linux.ibm.com>
160
161 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
162
bc30a119
AM		 1632021-05-25 Alan Modra <amodra@gmail.com>
164
165 * cris-desc.c: Regenerate.
166 * cris-desc.h: Regenerate.
167 * cris-opc.h: Regenerate.
168 * po/POTFILES.in: Regenerate.
169
54711280
MF		 1702021-05-24 Mike Frysinger <vapier@gentoo.org>
171
172 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
173 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
174 (CGEN_CPUS): Add cris.
175 (CRIS_DEPS): Define.
176 (stamp-cris): New rule.
177 * cgen.sh: Handle desc action.
178 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
179 * Makefile.in, configure: Regenerate.
180
113bb761
JN		 1812021-05-18 Job Noorman <mtvec@pm.me>
182
183 PR 27814
184 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
185 the elf objects.
186
e683cb41
AC		 1872021-05-17 Alex Coplan <alex.coplan@arm.com>
188
189 * arm-dis.c (mve_opcodes): Fix disassembly of
190 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
191 (is_mve_encoding_conflict): MVE vector loads should not match
192 when P = W = 0.
193 (is_mve_unpredictable): It's not unpredictable to use the same
194 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
195
a680affc
NC		 1962021-05-11 Nick Clifton <nickc@redhat.com>
197
198 PR 27840
199 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
200 the end of the code buffer.
201
0b3e14c9
SH		 2022021-05-06 Stafford Horne <shorne@gmail.com>
203
204 PR 21464
205 * or1k-asm.c: Regenerate.
206
6aee2cb2
MF		 2072021-05-01 Max Filippov <jcmvbkbc@gmail.com>
208
209 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
210 info->insn_info_valid.
211
fe134c65
JB		 2122021-04-26 Jan Beulich <jbeulich@suse.com>
213
214 * i386-opc.tbl (lea): Add Optimize.
215 * opcodes/i386-tbl.h: Re-generate.
216
b3ea7639
MF		 2172020-04-23 Max Filippov <jcmvbkbc@gmail.com>
218
219 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
220 of l32r fetch and display referenced literal value.
221
c1cbb7d8
MF		 2222021-04-23 Max Filippov <jcmvbkbc@gmail.com>
223
224 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
225 to 4 for literal disassembly.
226
02202574
PW		 2272021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
228
229 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
230 for TLBI instruction.
231
cd6608e4
PW		 2322021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
233
234 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
235 DC instruction.
236
fe1640ff
JB		 2372021-04-19 Jan Beulich <jbeulich@suse.com>
238
239 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
240 "qualifier".
241 (convert_mov_to_movewide): Add initializer for "value".
242
100e914d
PW		 2432021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
244
245 * aarch64-opc.c: Add RME system registers.
246
a21b96dd
NC		 2472021-04-16 Lifang Xia <lifang_xia@c-sky.com>
248
249 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
250 "addi d,CV,z" to "c.mv d,CV".
251
43e05cd4
AM		 2522021-04-12 Alan Modra <amodra@gmail.com>
253
254 * configure.ac (--enable-checking): Add support.
255 * config.in: Regenerate.
256 * configure: Regenerate.
257
52efda82
TB		 2582021-04-09 Tejas Belagod <tejas.belagod@arm.com>
259
260 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
261 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
262
c3f72de4
AM		 2632021-04-09 Alan Modra <amodra@gmail.com>
264
265 * ppc-dis.c (struct dis_private): Add "special".
266 (POWERPC_DIALECT): Delete. Replace uses with..
267 (private_data): ..this. New inline function.
268 (disassemble_init_powerpc): Init "special" names.
269 (skip_optional_operands): Add is_pcrel arg, set when detecting R
270 field of prefix instructions.
271 (bsearch_reloc, print_got_plt): New functions.
272 (print_insn_powerpc): For pcrel instructions, print target address
273 and symbol if known, and decode plt and got loads too.
274
ce7d813a
AM		 2752021-04-08 Alan Modra <amodra@gmail.com>
276
277 PR 27684
278 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
279
97bf40d8
AM		 2802021-04-08 Alan Modra <amodra@gmail.com>
281
282 PR 27676
283 * ppc-opc.c (DCBT_EO): Move earlier.
284 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
285 (powerpc_operands): Add THCT and THDS entries.
286 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
287
a2e66773
AM		 2882021-04-06 Alan Modra <amodra@gmail.com>
289
290 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
291 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
292 symbol_at_address_func.
293
ab2af25e
AM		 2942021-04-05 Alan Modra <amodra@gmail.com>
295
296 * configure.ac: Don't check for limits.h, string.h, strings.h or
297 stdlib.h.
298 (AC_ISC_POSIX): Don't invoke.
299 * sysdep.h: Include stdlib.h and string.h unconditionally.
300 * i386-opc.h: Include limits.h unconditionally.
301 * wasm32-dis.c: Likewise.
302 * cgen-opc.c: Don't include alloca-conf.h.
303 * config.in: Regenerate.
304 * configure: Regenerate.
305
e9b095a5
ML		 3062021-04-01 Martin Liska <mliska@suse.cz>
307
308 * arm-dis.c (strneq): Remove strneq and use startswith.
309 * cr16-dis.c (print_insn_cr16): Likewise.
310 * score-dis.c (streq): Likewise.
311 (strneq): Likewise.
312 * score7-dis.c (strneq): Likewise.
313
1cb108e4
AM		 3142021-04-01 Alan Modra <amodra@gmail.com>
315
316 PR 27675
317 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
318
78933a4a
AM		 3192021-03-31 Alan Modra <amodra@gmail.com>
320
321 * sysdep.h (POISON_BFD_BOOLEAN): Define.
322 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
323 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
324 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
325 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
326 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
327 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
328 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
329 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
330 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
331 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
332 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
333 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
334 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
335 and TRUE with true throughout.
336
3dfb1b6d
AM		 3372021-03-31 Alan Modra <amodra@gmail.com>
338
339 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
340 * aarch64-dis.h: Likewise.
341 * aarch64-opc.c: Likewise.
342 * avr-dis.c: Likewise.
343 * csky-dis.c: Likewise.
344 * nds32-asm.c: Likewise.
345 * nds32-dis.c: Likewise.
346 * nfp-dis.c: Likewise.
347 * riscv-dis.c: Likewise.
348 * s12z-dis.c: Likewise.
349 * wasm32-dis.c: Likewise.
350
5e042380
JB		 3512021-03-30 Jan Beulich <jbeulich@suse.com>
352
353 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
354 (i386_seg_prefixes): New.
355 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
356 (i386_seg_prefixes): Declare.
357
34684862
JB		 3582021-03-30 Jan Beulich <jbeulich@suse.com>
359
360 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
361
6288d05f
JB		 3622021-03-30 Jan Beulich <jbeulich@suse.com>
363
364 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
365 * i386-reg.tbl (st): Move down.
366 (st(0)): Delete. Extend comment.
367 * i386-tbl.h: Re-generate.
368
bbe1eca6
JB		 3692021-03-29 Jan Beulich <jbeulich@suse.com>
370
371 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
372 (cmpsd): Move next to cmps.
373 (movsd): Move next to movs.
374 (cmpxchg16b): Move to separate section.
375 (fisttp, fisttpll): Likewise.
376 (monitor, mwait): Likewise.
377 * i386-tbl.h: Re-generate.
378
c8cad9d3
JB		 3792021-03-29 Jan Beulich <jbeulich@suse.com>
380
381 * i386-opc.tbl (psadbw): Add <sse2:comm>.
382 (vpsadbw): Add C.
383 * i386-tbl.h: Re-generate.
384
5cdaf100
JB		 3852021-03-29 Jan Beulich <jbeulich@suse.com>
386
387 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
388 pclmul, gfni): New templates. Use them wherever possible. Move
389 SSE4.1 pextrw into respective section.
390 * i386-tbl.h: Re-generate.
391
73e45eb2
JB		 3922021-03-29 Jan Beulich <jbeulich@suse.com>
393
394 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
395 strtoull(). Bump upper loop bound. Widen masks. Sanity check
396 "length".
397 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
398 Convert all of their uses to representation in opcode.
399
9df6f676
JB		 4002021-03-29 Jan Beulich <jbeulich@suse.com>
401
402 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
403 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
404 value of None. Shrink operands to 3 bits.
405
389d00a5
JB		 4062021-03-29 Jan Beulich <jbeulich@suse.com>
407
408 * i386-gen.c (process_i386_opcode_modifier): New parameter
6c2ede01 409 "space".
389d00a5
JB		 410 (output_i386_opcode): New local variable "space". Adjust
411 process_i386_opcode_modifier() invocation.
412 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
413 invocation.
414 * i386-tbl.h: Re-generate.
415
63b4cc53
AM		 4162021-03-29 Alan Modra <amodra@gmail.com>
417
418 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
419 (fp_qualifier_p, get_data_pattern): Likewise.
420 (aarch64_get_operand_modifier_from_value): Likewise.
421 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
422 (operand_variant_qualifier_p): Likewise.
423 (qualifier_value_in_range_constraint_p): Likewise.
424 (aarch64_get_qualifier_esize): Likewise.
425 (aarch64_get_qualifier_nelem): Likewise.
426 (aarch64_get_qualifier_standard_value): Likewise.
427 (get_lower_bound, get_upper_bound): Likewise.
428 (aarch64_find_best_match, match_operands_qualifier): Likewise.
429 (aarch64_print_operand): Likewise.
430 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
431 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
432 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
433 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
434 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
435 (print_insn_tic6x): Likewise.
436
3d7d6c1b
AM		 4372021-03-29 Alan Modra <amodra@gmail.com>
438
439 * arc-dis.c (extract_operand_value): Correct NULL cast.
440 * frv-opc.h: Regenerate.
441
c3344b62
JB		 4422021-03-26 Jan Beulich <jbeulich@suse.com>
443
444 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
445 MMX form.
446 * i386-tbl.h: Re-generate.
447
efa30ac3
HAQ		 4482021-03-25 Abid Qadeer <abidh@codesourcery.com>
449
450 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
451 immediate in br.n instruction.
452
596a02ff
JB		 4532021-03-25 Jan Beulich <jbeulich@suse.com>
454
455 * i386-dis.c (XMGatherD, VexGatherD): New.
456 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
457 (print_insn): Check masking for S/G insns.
458 (OP_E_memory): New local variable check_gather. Extend mandatory
459 SIB check. Check register conflicts for (EVEX-encoded) gathers.
460 Extend check for disallowed 16-bit addressing.
461 (OP_VEX): New local variables modrm_reg and sib_index. Convert
462 if()s to switch(). Check register conflicts for (VEX-encoded)
463 gathers. Drop no longer reachable cases.
464 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
465 vgatherdp*.
466
53642852
JB		 4672021-03-25 Jan Beulich <jbeulich@suse.com>
468
469 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
470 zeroing-masking without masking.
471
c0e54661
JB		 4722021-03-25 Jan Beulich <jbeulich@suse.com>
473
474 * i386-opc.tbl (invlpgb): Fix multi-operand form.
475 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
476 single-operand forms as deprecated.
477 * i386-tbl.h: Re-generate.
478
5a403766
AM		 4792021-03-25 Alan Modra <amodra@gmail.com>
480
481 PR 27647
482 * ppc-opc.c (XLOCB_MASK): Delete.
483 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
484 XLBH_MASK.
485 (powerpc_opcodes): Accept a BH field on all extended forms of
486 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
487
9a182d04
JB		 4882021-03-24 Jan Beulich <jbeulich@suse.com>
489
490 * i386-gen.c (output_i386_opcode): Drop processing of
491 opcode_length. Calculate length from base_opcode. Adjust prefix
492 encoding determination.
493 (process_i386_opcodes): Drop output of fake opcode_length.
494 * i386-opc.h (struct insn_template): Drop opcode_length field.
495 * i386-opc.tbl: Drop opcode length field from all templates.
496 * i386-tbl.h: Re-generate.
497
35648716
JB		 4982021-03-24 Jan Beulich <jbeulich@suse.com>
499
500 * i386-gen.c (process_i386_opcode_modifier): Return void. New
501 parameter "prefix". Drop local variable "regular_encoding".
502 Record prefix setting / check for consistency.
503 (output_i386_opcode): Parse opcode_length and base_opcode
504 earlier. Derive prefix encoding. Drop no longer applicable
505 consistency checking. Adjust process_i386_opcode_modifier()
506 invocation.
507 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
508 invocation.
509 * i386-tbl.h: Re-generate.
510
31184569
JB		 5112021-03-24 Jan Beulich <jbeulich@suse.com>
512
513 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
514 check.
515 * i386-opc.h (Prefix_*): Move #define-s.
516 * i386-opc.tbl: Move pseudo prefix enumerator values to
517 extension opcode field. Introduce pseudopfx template.
518 * i386-tbl.h: Re-generate.
519
b933fa4b
JB		 5202021-03-23 Jan Beulich <jbeulich@suse.com>
521
522 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
523 comment.
524 * i386-tbl.h: Re-generate.
525
dac10fb0
JB		 5262021-03-23 Jan Beulich <jbeulich@suse.com>
527
528 * i386-opc.h (struct insn_template): Move cpu_flags field past
529 opcode_modifier one.
530 * i386-tbl.h: Re-generate.
531
441f6aca
JB		 5322021-03-23 Jan Beulich <jbeulich@suse.com>
533
534 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
535 * i386-opc.h (OpcodeSpace): New enumerator.
536 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
537 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
538 SPACE_XOP09, SPACE_XOP0A): ... respectively.
539 (struct i386_opcode_modifier): New field opcodespace. Shrink
540 opcodeprefix field.
541 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
542 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
543 OpcodePrefix uses.
544 * i386-tbl.h: Re-generate.
545
08dedd66
ML		 5462021-03-22 Martin Liska <mliska@suse.cz>
547
548 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
549 * arc-dis.c (parse_option): Likewise.
550 * arm-dis.c (parse_arm_disassembler_options): Likewise.
551 * cris-dis.c (print_with_operands): Likewise.
552 * h8300-dis.c (bfd_h8_disassemble): Likewise.
553 * i386-dis.c (print_insn): Likewise.
554 * ia64-gen.c (fetch_insn_class): Likewise.
555 (parse_resource_users): Likewise.
556 (in_iclass): Likewise.
557 (lookup_specifier): Likewise.
558 (insert_opcode_dependencies): Likewise.
559 * mips-dis.c (parse_mips_ase_option): Likewise.
560 (parse_mips_dis_option): Likewise.
561 * s390-dis.c (disassemble_init_s390): Likewise.
562 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
563
80d49d6a
KLC		 5642021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
565
566 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
567
7fce7ea9
PW		 5682021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
569
570 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
571 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
572
78c84bf9
AM		 5732021-03-12 Alan Modra <amodra@gmail.com>
574
575 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
576
fd1fd061
JB		 5772021-03-11 Jan Beulich <jbeulich@suse.com>
578
579 * i386-dis.c (OP_XMM): Re-order checks.
580
ac7a2311
JB		 5812021-03-11 Jan Beulich <jbeulich@suse.com>
582
583 * i386-dis.c (putop): Drop need_vex check when also checking
584 vex.evex.
585 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
586 checking vex.b.
587
da944c8a
JB		 5882021-03-11 Jan Beulich <jbeulich@suse.com>
589
590 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
591 checks. Move case label past broadcast check.
592
b763d508
JB		 5932021-03-10 Jan Beulich <jbeulich@suse.com>
594
595 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
596 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
597 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
598 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
599 EVEX_W_0F38C7_M_0_L_2): Delete.
600 (REG_EVEX_0F38C7_M_0_L_2): New.
601 (intel_operand_size): Handle VEX and EVEX the same for
602 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
603 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
604 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
605 vex_vsib_q_w_d_mode uses.
606 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
607 0F38A1, and 0F38A3 entries.
608 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
609 entry.
610 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
611 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
612 0F38A3 entries.
613
32e31ad7
JB		 6142021-03-10 Jan Beulich <jbeulich@suse.com>
615
616 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
617 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
618 MOD_VEX_0FXOP_09_12): Rename to ...
619 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
620 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
621 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
622 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
623 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
624 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
625 (reg_table): Adjust comments.
626 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
627 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
628 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
629 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
630 (vex_len_table): Adjust opcode 0A_12 entry.
631 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
632 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
633 (rm_table): Move hreset entry.
634
85ba7507
JB		 6352021-03-10 Jan Beulich <jbeulich@suse.com>
636
637 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
638 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
639 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
640 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
641 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
642 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
643 (get_valid_dis386): Also handle 512-bit vector length when
644 vectoring into vex_len_table[].
645 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
646 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
647 entries.
648 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
649 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
650 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
651 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
652 entries.
653
066f82b9
JB		 6542021-03-10 Jan Beulich <jbeulich@suse.com>
655
656 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
657 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
658 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
659 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
660 entries.
661 * i386-dis-evex-len.h (evex_len_table): Likewise.
662 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
663
fc681dd6
JB		 6642021-03-10 Jan Beulich <jbeulich@suse.com>
665
666 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
667 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
668 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
669 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
670 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
671 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
672 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
673 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
674 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
675 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
676 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
677 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
678 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
679 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
680 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
681 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
682 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
683 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
684 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
685 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
686 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
687 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
688 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
689 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
690 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
691 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
692 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
693 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
694 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
695 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
696 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
697 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
698 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
699 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
700 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
701 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
702 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
703 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
704 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
705 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
706 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
707 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
708 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
709 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
710 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
711 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
712 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
713 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
714 EVEX_W_0F3A43_L_n): New.
715 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
716 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
717 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
718 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
719 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
720 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
721 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
722 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
723 0F385B, 0F38C6, and 0F38C7 entries.
724 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
725 0F38C6 and 0F38C7.
726 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
727 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
728 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
729 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
730
13954a31
JB		 7312021-03-10 Jan Beulich <jbeulich@suse.com>
732
733 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
734 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
735 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
736 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
737 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
738 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
739 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
740 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
741 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
742 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
743 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
744 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
745 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
746 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
747 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
748 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
749 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
750 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
751 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
752 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
753 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
754 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
755 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
756 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
757 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
758 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
759 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
760 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
761 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
762 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
763 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
764 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
765 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
766 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
767 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
768 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
769 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
770 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
771 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
772 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
773 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
774 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
775 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
776 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
777 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
778 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
779 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
780 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
781 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
782 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
783 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
784 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
785 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
786 VEX_W_0F99_P_2_LEN_0): Delete.
787 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
788 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
789 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
790 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
791 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
792 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
793 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
794 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
795 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
796 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
797 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
798 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
799 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
800 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
801 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
802 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
803 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
804 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
805 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
806 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
807 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
808 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
809 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
810 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
811 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
812 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
813 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
814 (prefix_table): No longer link to vex_len_table[] for opcodes
815 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
816 0F92, 0F93, 0F98, and 0F99.
817 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
818 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
819 0F98, and 0F99.
820 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
821 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
822 0F98, and 0F99.
823 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
824 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
825 0F98, and 0F99.
826 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
827 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
828 0F98, and 0F99.
829
14d10c6c
JB		 8302021-03-10 Jan Beulich <jbeulich@suse.com>
831
832 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
833 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
834 REG_VEX_0F73_M_0 respectively.
835 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
836 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
837 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
838 MOD_VEX_0F73_REG_7): Delete.
839 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
840 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
841 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
842 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
843 PREFIX_VEX_0F3AF0_L_0 respectively.
844 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
845 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
846 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
847 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
848 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
849 VEX_LEN_0F38F7): New.
850 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
851 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
852 0F72, and 0F73. No longer link to vex_len_table[] for opcode
853 0F38F3.
854 (prefix_table): No longer link to vex_len_table[] for opcodes
855 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
856 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
857 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
858 0F38F6, 0F38F7, and 0F3AF0.
859 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
860 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
861 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
862 0F73.
863
00ec1875
JB		 8642021-03-10 Jan Beulich <jbeulich@suse.com>
865
866 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
867 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
868 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
869 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
870 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
871 (MOD_0F71, MOD_0F72, MOD_0F73): New.
872 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
873 73.
874 (reg_table): No longer link to mod_table[] for opcodes 0F71,
875 0F72, and 0F73.
876 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
877 0F73.
878
31941983
JB		 8792021-03-10 Jan Beulich <jbeulich@suse.com>
880
881 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
882 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
883 (reg_table): Don't link to mod_table[] where not needed. Add
884 PREFIX_IGNORED to nop entries.
885 (prefix_table): Replace PREFIX_OPCODE in nop entries.
886 (mod_table): Add nop entries next to prefetch ones. Drop
887 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
888 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
889 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
890 PREFIX_OPCODE from endbr* entries.
891 (get_valid_dis386): Also consider entry's name when zapping
892 vindex.
893 (print_insn): Handle PREFIX_IGNORED.
894
742732c7
JB		 8952021-03-09 Jan Beulich <jbeulich@suse.com>
896
897 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
898 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
899 element.
900 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
901 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
902 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
903 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
904 (struct i386_opcode_modifier): Delete notrackprefixok,
905 islockable, hleprefixok, and repprefixok fields. Add prefixok
906 field.
907 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
908 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
909 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
910 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
911 Replace HLEPrefixOk.
912 * opcodes/i386-tbl.h: Re-generate.
913
e93a3b27
JB		 9142021-03-09 Jan Beulich <jbeulich@suse.com>
915
916 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
917 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
918 64-bit form.
919 * opcodes/i386-tbl.h: Re-generate.
920
75363b6d
JB		 9212021-03-03 Jan Beulich <jbeulich@suse.com>
922
923 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
924 for {} instead of {0}. Don't look for '0'.
925 * i386-opc.tbl: Drop operand count field. Drop redundant operand
926 size specifiers.
927
5a9f5403
NC		 9282021-02-19 Nelson Chu <nelson.chu@sifive.com>
929
930 PR 27158
931 * riscv-dis.c (print_insn_args): Updated encoding macros.
932 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
933 (match_c_addi16sp): Updated encoding macros.
934 (match_c_lui): Likewise.
935 (match_c_lui_with_hint): Likewise.
936 (match_c_addi4spn): Likewise.
937 (match_c_slli): Likewise.
938 (match_slli_as_c_slli): Likewise.
939 (match_c_slli64): Likewise.
940 (match_srxi_as_c_srxi): Likewise.
941 (riscv_insn_types): Added .insn css/cl/cs.
942
3d73d29e
NC		 9432021-02-18 Nelson Chu <nelson.chu@sifive.com>
944
945 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
946 (default_priv_spec): Updated type to riscv_spec_class.
947 (parse_riscv_dis_option): Updated.
948 * riscv-opc.c: Moved stuff and make the file tidy.
949
b9b204b3
AM		 9502021-02-17 Alan Modra <amodra@gmail.com>
951
952 * wasm32-dis.c: Include limits.h.
953 (CHAR_BIT): Provide backup define.
954 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
955 Correct signed overflow checking.
956
394ae71f
JB		 9572021-02-16 Jan Beulich <jbeulich@suse.com>
958
959 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
960 * i386-tbl.h: Re-generate.
961
b818b220
JB		 9622021-02-16 Jan Beulich <jbeulich@suse.com>
963
964 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
965 Oword.
966 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
967
ba2b480f
AK		 9682021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
969
970 * s390-mkopc.c (main): Accept arch14 as cpu string.
971 * s390-opc.txt: Add new arch14 instructions.
972
95148614
NA		 9732021-02-04 Nick Alcock <nick.alcock@oracle.com>
974
975 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
976 favour of LIBINTL.
977 * configure: Regenerated.
978
bfd428bc
MF		 9792021-02-08 Mike Frysinger <vapier@gentoo.org>
980
981 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
982 * tic54x-opc.c (regs): Rename to ...
983 (tic54x_regs): ... this.
984 (mmregs): Rename to ...
985 (tic54x_mmregs): ... this.
986 (condition_codes): Rename to ...
987 (tic54x_condition_codes): ... this.
988 (cc2_codes): Rename to ...
989 (tic54x_cc2_codes): ... this.
990 (cc3_codes): Rename to ...
991 (tic54x_cc3_codes): ... this.
992 (status_bits): Rename to ...
993 (tic54x_status_bits): ... this.
994 (misc_symbols): Rename to ...
995 (tic54x_misc_symbols): ... this.
996
24075dcc
NC		 9972021-02-04 Nelson Chu <nelson.chu@sifive.com>
998
999 * riscv-opc.c (MASK_RVB_IMM): Removed.
1000 (riscv_opcodes): Removed zb* instructions.
1001 (riscv_ext_version_table): Removed versions for zb*.
1002
c3ffb8f3
AM		 10032021-01-26 Alan Modra <amodra@gmail.com>
1004
1005 * i386-gen.c (parse_template): Ensure entire template_instance
1006 is initialised.
1007
1942a048
NC		 10082021-01-15 Nelson Chu <nelson.chu@sifive.com>
1009
1010 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1011 (riscv_fpr_names_abi): Likewise.
1012 (riscv_opcodes): Likewise.
1013 (riscv_insn_types): Likewise.
1014
b800637e
NC		 10152021-01-15 Nelson Chu <nelson.chu@sifive.com>
1016
1017 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1018
dcd709e0
NC		 10192021-01-15 Nelson Chu <nelson.chu@sifive.com>
1020
1021 * riscv-dis.c: Comments tidy and improvement.
1022 * riscv-opc.c: Likewise.
1023
5347ed60
AM		 10242021-01-13 Alan Modra <amodra@gmail.com>
1025
1026 * Makefile.in: Regenerate.
1027
d546b610
L		 10282021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1029
1030 PR binutils/26792
1031 * configure.ac: Use GNU_MAKE_JOBSERVER.
1032 * aclocal.m4: Regenerated.
1033 * configure: Likewise.
1034
6d104cac
NC		 10352021-01-12 Nick Clifton <nickc@redhat.com>
1036
1037 * po/sr.po: Updated Serbian translation.
1038
83b33c6c
L		 10392021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1040
1041 PR ld/27173
1042 * configure: Regenerated.
1043
82c70b08
KT		 10442021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1045
1046 * aarch64-asm-2.c: Regenerate.
1047 * aarch64-dis-2.c: Likewise.
1048 * aarch64-opc-2.c: Likewise.
1049 * aarch64-opc.c (aarch64_print_operand):
1050 Delete handling of AARCH64_OPND_CSRE_CSR.
1051 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1052 (CSRE): Likewise.
1053 (_CSRE_INSN): Likewise.
1054 (aarch64_opcode_table): Delete csr.
1055
a8aa72b9
NC		 10562021-01-11 Nick Clifton <nickc@redhat.com>
1057
1058 * po/de.po: Updated German translation.
1059 * po/fr.po: Updated French translation.
1060 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1061 * po/sv.po: Updated Swedish translation.
1062 * po/uk.po: Updated Ukranian translation.
1063
a4966cd9
L		 10642021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1065
1066 * configure: Regenerated.
1067
573fe3fb
NC		 10682021-01-09 Nick Clifton <nickc@redhat.com>
1069
1070 * configure: Regenerate.
1071 * po/opcodes.pot: Regenerate.
1072
055bc77a
NC		 10732021-01-09 Nick Clifton <nickc@redhat.com>
1074
1075 * 2.36 release branch crated.
1076
aae7fcb8
PB		 10772021-01-08 Peter Bergner <bergner@linux.ibm.com>
1078
1079 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1080 (DW, (XRC_MASK): Define.
1081 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1082
64307045
AM		 10832021-01-09 Alan Modra <amodra@gmail.com>
1084
1085 * configure: Regenerate.
1086
ed205222
NC		 10872021-01-08 Nick Clifton <nickc@redhat.com>
1088
1089 * po/sv.po: Updated Swedish translation.
1090
fb932b57
NC		 10912021-01-08 Nick Clifton <nickc@redhat.com>
1092
e84c8716
NC		 1093 PR 27129
1094 * aarch64-dis.c (determine_disassembling_preference): Move call to
1095 aarch64_match_operands_constraint outside of the assertion.
1096 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1097 Replace with a return of FALSE.
1098
fb932b57
NC		 1099 PR 27139
1100 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1101 core system register.
1102
f4782128
ST		 11032021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1104
1105 * configure: Regenerate.
1106
1b0927db
NC		 11072021-01-07 Nick Clifton <nickc@redhat.com>
1108
1109 * po/fr.po: Updated French translation.
1110
3b288c8e
FN		 11112021-01-07 Fredrik Noring <noring@nocrew.org>
1112
1113 * m68k-opc.c (chkl): Change minimum architecture requirement to
1114 m68020.
1115
aa881ecd
PT		 11162021-01-07 Philipp Tomsich <prt@gnu.org>
1117
1118 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1119
2652cfad
CXW		 11202021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1121 Jim Wilson <jimw@sifive.com>
1122 Andrew Waterman <andrew@sifive.com>
1123 Maxim Blinov <maxim.blinov@embecosm.com>
1124 Kito Cheng <kito.cheng@sifive.com>
1125 Nelson Chu <nelson.chu@sifive.com>
1126
1127 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1128 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1129
250d07de
AM		 11302021-01-01 Alan Modra <amodra@gmail.com>
1131
1132 Update year range in copyright notice of all files.
1133
c2795844 1134For older changes see ChangeLog-2020
3499769a 1135\f
c2795844 1136Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 1137
1138Copying and distribution of this file, with or without modification,
1139are permitted in any medium without royalty provided the copyright
1140notice and this notice are preserved.
1141
1142Local Variables:
1143mode: change-log
1144left-margin: 8
1145fill-column: 74
1146version-control: never
1147End:
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