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Fix missing update in previous patch.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f8c2a965
NC		 12015-11-20 Nick Clifton <nickc@redhat.com>
2
3 * po/zh_CN.po: Updated simplified Chinese translation.
4
c2825638
MW		 52015-11-19 Matthew Wahab <matthew.wahab@arm.com>
6
7 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
8 of MSR PAN immediate operand.
9
e7286c56
NC		 102015-11-16 Nick Clifton <nickc@redhat.com>
11
12 * rx-dis.c (condition_names): Replace always and never with
13 invalid, since the always/never conditions can never be legal.
14
d8bd95ef
TG		 152015-11-13 Tristan Gingold <gingold@adacore.com>
16
17 * configure: Regenerate.
18
a680de9a
PB		 192015-11-11 Alan Modra <amodra@gmail.com>
20 Peter Bergner <bergner@vnet.ibm.com>
21
22 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
23 Add PPC_OPCODE_VSX3 to the vsx entry.
24 (powerpc_init_dialect): Set default dialect to power9.
25 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
26 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
27 extract_l1 insert_xtq6, extract_xtq6): New static functions.
28 (insert_esync): Test for illegal L operand value.
29 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
30 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
31 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
32 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
33 PPCVSX3): New defines.
34 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
35 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
36 <mcrxr>: Use XBFRARB_MASK.
37 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
38 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
39 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
40 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
41 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
42 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
43 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
44 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
45 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
46 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
47 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
48 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
49 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
50 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
51 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
52 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
53 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
54 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
55 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
56 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
57 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
58 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
59 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
60 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
61 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
62 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
63 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
64 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
65 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
66 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
67 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
68 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
69
854eb72b
NC		 702015-11-02 Nick Clifton <nickc@redhat.com>
71
72 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
73 instructions.
74 * rx-decode.c: Regenerate.
75
e292aa7a
NC		 762015-11-02 Nick Clifton <nickc@redhat.com>
77
78 * rx-decode.opc (rx_disp): If the displacement is zero, set the
79 type to RX_Operand_Zero_Indirect.
80 * rx-decode.c: Regenerate.
81 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
82
43cdf5ae
YQ		 832015-10-28 Yao Qi <yao.qi@linaro.org>
84
85 * aarch64-dis.c (aarch64_decode_insn): Add one argument
86 noaliases_p. Update comments. Pass noaliases_p rather than
87 no_aliases to aarch64_opcode_decode.
88 (print_insn_aarch64_word): Pass no_aliases to
89 aarch64_decode_insn.
90
c2f28758
VK		 912015-10-27 Vinay <Vinay.G@kpit.com>
92
93 PR binutils/19159
94 * rl78-decode.opc (MOV): Added offset to DE register in index
95 addressing mode.
96 * rl78-decode.c: Regenerate.
97
46662804
VK		 982015-10-27 Vinay Kumar <vinay.g@kpit.com>
99
100 PR binutils/19158
101 * rl78-decode.opc: Add 's' print operator to instructions that
102 access system registers.
103 * rl78-decode.c: Regenerate.
104 * rl78-dis.c (print_insn_rl78_common): Decode all system
105 registers.
106
02f12cd4
VK		 1072015-10-27 Vinay Kumar <vinay.g@kpit.com>
108
109 PR binutils/19157
110 * rl78-decode.opc: Add 'a' print operator to mov instructions
111 using stack pointer plus index addressing.
112 * rl78-decode.c: Regenerate.
113
485f23cf
AK		 1142015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
115
116 * s390-opc.c: Fix comment.
117 * s390-opc.txt: Change instruction type for troo, trot, trto, and
118 trtt to RRF_U0RER since the second parameter does not need to be a
119 register pair.
120
3f94e60d
NC		 1212015-10-08 Nick Clifton <nickc@redhat.com>
122
123 * arc-dis.c (print_insn_arc): Initiallise insn array.
124
875880c6
YQ		 1252015-10-07 Yao Qi <yao.qi@linaro.org>
126
127 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
128 'name' rather than 'template'.
129 * aarch64-opc.c (aarch64_print_operand): Likewise.
130
886a2506
NC		 1312015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
132
133 * arc-dis.c: Revamped file for ARC support
134 * arc-dis.h: Likewise.
135 * arc-ext.c: Likewise.
136 * arc-ext.h: Likewise.
137 * arc-opc.c: Likewise.
138 * arc-fxi.h: New file.
139 * arc-regs.h: Likewise.
140 * arc-tbl.h: Likewise.
141
36f4aab1
YQ		 1422015-10-02 Yao Qi <yao.qi@linaro.org>
143
144 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
145 argument insn type to aarch64_insn. Rename to ...
146 (aarch64_decode_insn): ... it.
147 (print_insn_aarch64_word): Caller updated.
148
7232d389
YQ		 1492015-10-02 Yao Qi <yao.qi@linaro.org>
150
151 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
152 (print_insn_aarch64_word): Caller updated.
153
7ecc513a
DV		 1542015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
155
156 * s390-mkopc.c (main): Parse htm and vx flag.
157 * s390-opc.txt: Mark instructions from the hardware transactional
158 memory and vector facilities with the "htm"/"vx" flag.
159
b08b78e7
NC		 1602015-09-28 Nick Clifton <nickc@redhat.com>
161
162 * po/de.po: Updated German translation.
163
36f7a941
TR		 1642015-09-28 Tom Rix <tom@bumblecow.com>
165
166 * ppc-opc.c (PPC500): Mark some opcodes as invalid
167
b6518b38
NC		 1682015-09-23 Nick Clifton <nickc@redhat.com>
169
170 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
171 function.
172 * tic30-dis.c (print_branch): Likewise.
173 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
174 value before left shifting.
175 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
176 * hppa-dis.c (print_insn_hppa): Likewise.
177 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
178 array.
179 * msp430-dis.c (msp430_singleoperand): Likewise.
180 (msp430_doubleoperand): Likewise.
181 (print_insn_msp430): Likewise.
182 * nds32-asm.c (parse_operand): Likewise.
183 * sh-opc.h (MASK): Likewise.
184 * v850-dis.c (get_operand_value): Likewise.
185
f04265ec
NC		 1862015-09-22 Nick Clifton <nickc@redhat.com>
187
188 * rx-decode.opc (bwl): Use RX_Bad_Size.
189 (sbwl): Likewise.
190 (ubwl): Likewise. Rename to ubw.
191 (uBWL): Rename to uBW.
192 Replace all references to uBWL with uBW.
193 * rx-decode.c: Regenerate.
194 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
195 (opsize_names): Likewise.
196 (print_insn_rx): Detect and report RX_Bad_Size.
197
6dca4fd1
AB		 1982015-09-22 Anton Blanchard <anton@samba.org>
199
200 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
201
38074311
JM		 2022015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
203
204 * sparc-dis.c (print_insn_sparc): Handle the privileged register
205 %pmcdper.
206
5f40e14d
JS		 2072015-08-24 Jan Stancek <jstancek@redhat.com>
208
209 * i386-dis.c (print_insn): Fix decoding of three byte operands.
210
ab4e4ed5
AF		 2112015-08-21 Alexander Fomin <alexander.fomin@intel.com>
212
213 PR binutils/18257
214 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
215 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
216 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
217 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
218 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
219 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
220 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
221 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
222 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
223 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
224 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
225 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
226 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
227 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
228 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
229 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
230 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
231 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
232 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
233 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
234 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
235 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
236 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
237 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
238 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
239 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
240 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
241 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
242 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
243 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
244 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
245 (vex_w_table): Replace terminals with MOD_TABLE entries for
246 most of mask instructions.
247
919b75f7
AM		 2482015-08-17 Alan Modra <amodra@gmail.com>
249
250 * cgen.sh: Trim trailing space from cgen output.
251 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
252 (print_dis_table): Likewise.
253 * opc2c.c (dump_lines): Likewise.
254 (orig_filename): Warning fix.
255 * ia64-asmtab.c: Regenerate.
256
4ab90a7a
AV		 2572015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
258
259 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
260 and higher with ARM instruction set will now mark the 26-bit
261 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
262 (arm_opcodes): Fix for unpredictable nop being recognized as a
263 teq.
264
40fc1451
SD		 2652015-08-12 Simon Dardis <simon.dardis@imgtec.com>
266
267 * micromips-opc.c (micromips_opcodes): Re-order table so that move
268 based on 'or' is first.
269 * mips-opc.c (mips_builtin_opcodes): Ditto.
270
922c5db5
NC		 2712015-08-11 Nick Clifton <nickc@redhat.com>
272
273 PR 18800
274 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
275 instruction.
276
75fb7498
RS		 2772015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
278
279 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
280
36aed29d
AP		 2812015-08-07 Amit Pawar <Amit.Pawar@amd.com>
282
283 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
284 * i386-init.h: Regenerated.
285
a8484f96
L		 2862015-07-30 H.J. Lu <hongjiu.lu@intel.com>
287
288 PR binutils/13571
289 * i386-dis.c (MOD_0FC3): New.
290 (PREFIX_0FC3): Renamed to ...
291 (PREFIX_MOD_0_0FC3): This.
292 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
293 (prefix_table): Replace Ma with Ev on movntiS.
294 (mod_table): Add MOD_0FC3.
295
37a42ee9
L		 2962015-07-27 H.J. Lu <hongjiu.lu@intel.com>
297
298 * configure: Regenerated.
299
070fe95d
AM		 3002015-07-23 Alan Modra <amodra@gmail.com>
301
302 PR 18708
303 * i386-dis.c (get64): Avoid signed integer overflow.
304
20c2a615
L		 3052015-07-22 Alexander Fomin <alexander.fomin@intel.com>
306
307 PR binutils/18631
308 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
309 "EXEvexHalfBcstXmmq" for the second operand.
310 (EVEX_W_0F79_P_2): Likewise.
311 (EVEX_W_0F7A_P_2): Likewise.
312 (EVEX_W_0F7B_P_2): Likewise.
313
6f1c2142
AM		 3142015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
315
316 * arm-dis.c (print_insn_coprocessor): Added support for quarter
317 float bitfield format.
318 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
319 quarter float bitfield format.
320
8a643cc3
L		 3212015-07-14 H.J. Lu <hongjiu.lu@intel.com>
322
323 * configure: Regenerated.
324
ef5a96d5
AM		 3252015-07-03 Alan Modra <amodra@gmail.com>
326
327 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
328 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
329 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
330
c8c8175b
SL		 3312015-07-01 Sandra Loosemore <sandra@codesourcery.com>
332 Cesar Philippidis <cesar@codesourcery.com>
333
334 * nios2-dis.c (nios2_extract_opcode): New.
335 (nios2_disassembler_state): New.
336 (nios2_find_opcode_hash): Use mach parameter to select correct
337 disassembler state.
338 (nios2_print_insn_arg): Extend to support new R2 argument letters
339 and formats.
340 (print_insn_nios2): Check for 16-bit instruction at end of memory.
341 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
342 (NIOS2_NUM_OPCODES): Rename to...
343 (NIOS2_NUM_R1_OPCODES): This.
344 (nios2_r2_opcodes): New.
345 (NIOS2_NUM_R2_OPCODES): New.
346 (nios2_num_r2_opcodes): New.
347 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
348 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
349 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
350 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
351 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
352
9916071f
AP		 3532015-06-30 Amit Pawar <Amit.Pawar@amd.com>
354
355 * i386-dis.c (OP_Mwaitx): New.
356 (rm_table): Add monitorx/mwaitx.
357 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
358 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
359 (operand_type_init): Add CpuMWAITX.
360 * i386-opc.h (CpuMWAITX): New.
361 (i386_cpu_flags): Add cpumwaitx.
362 * i386-opc.tbl: Add monitorx and mwaitx.
363 * i386-init.h: Regenerated.
364 * i386-tbl.h: Likewise.
365
7b934113
PB		 3662015-06-22 Peter Bergner <bergner@vnet.ibm.com>
367
368 * ppc-opc.c (insert_ls): Test for invalid LS operands.
369 (insert_esync): New function.
370 (LS, WC): Use insert_ls.
371 (ESYNC): Use insert_esync.
372
bdc4de1b
NC		 3732015-06-22 Nick Clifton <nickc@redhat.com>
374
375 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
376 requested region lies beyond it.
377 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
378 looking for 32-bit insns.
379 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
380 data.
381 * sh-dis.c (print_insn_sh): Likewise.
382 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
383 blocks of instructions.
384 * vax-dis.c (print_insn_vax): Check that the requested address
385 does not clash with the stop_vma.
386
11a0cf2e
PB		 3872015-06-19 Peter Bergner <bergner@vnet.ibm.com>
388
070fe95d 389 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 390 * ppc-opc.c (FXM4): Add non-zero optional value.
391 (TBR): Likewise.
392 (SXL): Likewise.
393 (insert_fxm): Handle new default operand value.
394 (extract_fxm): Likewise.
395 (insert_tbr): Likewise.
396 (extract_tbr): Likewise.
397
bdfa8b95
MW		 3982015-06-16 Matthew Wahab <matthew.wahab@arm.com>
399
400 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
401
24b4cf66
SN		 4022015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
403
404 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
405
99a2c561
PB		 4062015-06-12 Peter Bergner <bergner@vnet.ibm.com>
407
408 * ppc-opc.c: Add comment accidentally removed by old commit.
409 (MTMSRD_L): Delete.
410
40f77f82
AM		 4112015-06-04 Peter Bergner <bergner@vnet.ibm.com>
412
413 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
414
13be46a2
NC		 4152015-06-04 Nick Clifton <nickc@redhat.com>
416
417 PR 18474
418 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
419
ddfded2f
MW		 4202015-06-02 Matthew Wahab <matthew.wahab@arm.com>
421
422 * arm-dis.c (arm_opcodes): Add "setpan".
423 (thumb_opcodes): Add "setpan".
424
1af1dd51
MW		 4252015-06-02 Matthew Wahab <matthew.wahab@arm.com>
426
427 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
428 macros.
429
9e1f0fa7
MW		 4302015-06-02 Matthew Wahab <matthew.wahab@arm.com>
431
432 * aarch64-tbl.h (aarch64_feature_rdma): New.
433 (RDMA): New.
434 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
435 * aarch64-asm-2.c: Regenerate.
436 * aarch64-dis-2.c: Regenerate.
437 * aarch64-opc-2.c: Regenerate.
438
290806fd
MW		 4392015-06-02 Matthew Wahab <matthew.wahab@arm.com>
440
441 * aarch64-tbl.h (aarch64_feature_lor): New.
442 (LOR): New.
443 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
444 "stllrb", "stllrh".
445 * aarch64-asm-2.c: Regenerate.
446 * aarch64-dis-2.c: Regenerate.
447 * aarch64-opc-2.c: Regenerate.
448
f21cce2c
MW		 4492015-06-01 Matthew Wahab <matthew.wahab@arm.com>
450
451 * aarch64-opc.c (F_ARCHEXT): New.
452 (aarch64_sys_regs): Add "pan".
453 (aarch64_sys_reg_supported_p): New.
454 (aarch64_pstatefields): Add "pan".
455 (aarch64_pstatefield_supported_p): New.
456
d194d186
JB		 4572015-06-01 Jan Beulich <jbeulich@suse.com>
458
459 * i386-tbl.h: Regenerate.
460
3a8547d2
JB		 4612015-06-01 Jan Beulich <jbeulich@suse.com>
462
463 * i386-dis.c (print_insn): Swap rounding mode specifier and
464 general purpose register in Intel mode.
465
015c54d5
JB		 4662015-06-01 Jan Beulich <jbeulich@suse.com>
467
468 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
469 * i386-tbl.h: Regenerate.
470
071f0063
L		 4712015-05-18 H.J. Lu <hongjiu.lu@intel.com>
472
473 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
474 * i386-init.h: Regenerated.
475
5db04b09
L		 4762015-05-15 H.J. Lu <hongjiu.lu@intel.com>
477
478 PR binutis/18386
479 * i386-dis.c: Add comments for '@'.
480 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
481 (enum x86_64_isa): New.
482 (isa64): Likewise.
483 (print_i386_disassembler_options): Add amd64 and intel64.
484 (print_insn): Handle amd64 and intel64.
485 (putop): Handle '@'.
486 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
487 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
488 * i386-opc.h (AMD64): New.
489 (CpuIntel64): Likewise.
490 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
491 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
492 Mark direct call/jmp without Disp16|Disp32 as Intel64.
493 * i386-init.h: Regenerated.
494 * i386-tbl.h: Likewise.
495
4bc0608a
PB		 4962015-05-14 Peter Bergner <bergner@vnet.ibm.com>
497
498 * ppc-opc.c (IH) New define.
499 (powerpc_opcodes) <wait>: Do not enable for POWER7.
500 <tlbie>: Add RS operand for POWER7.
501 <slbia>: Add IH operand for POWER6.
502
70cead07
L		 5032015-05-11 H.J. Lu <hongjiu.lu@intel.com>
504
505 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
506 direct branch.
507 (jmp): Likewise.
508 * i386-tbl.h: Regenerated.
509
7b6d09fb
L		 5102015-05-11 H.J. Lu <hongjiu.lu@intel.com>
511
512 * configure.ac: Support bfd_iamcu_arch.
513 * disassemble.c (disassembler): Support bfd_iamcu_arch.
514 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
515 CPU_IAMCU_COMPAT_FLAGS.
516 (cpu_flags): Add CpuIAMCU.
517 * i386-opc.h (CpuIAMCU): New.
518 (i386_cpu_flags): Add cpuiamcu.
519 * configure: Regenerated.
520 * i386-init.h: Likewise.
521 * i386-tbl.h: Likewise.
522
31955f99
L		 5232015-05-08 H.J. Lu <hongjiu.lu@intel.com>
524
525 PR binutis/18386
526 * i386-dis.c (X86_64_E8): New.
527 (X86_64_E9): Likewise.
528 Update comments on 'T', 'U', 'V'. Add comments for '^'.
529 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
530 (x86_64_table): Add X86_64_E8 and X86_64_E9.
531 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
532 (putop): Handle '^'.
533 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
534 REX_W.
535
0952813b
DD		 5362015-04-30 DJ Delorie <dj@redhat.com>
537
538 * disassemble.c (disassembler): Choose suitable disassembler based
539 on E_ABI.
540 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
541 it to decode mul/div insns.
542 * rl78-decode.c: Regenerate.
543 * rl78-dis.c (print_insn_rl78): Rename to...
544 (print_insn_rl78_common): ...this, take ISA parameter.
545 (print_insn_rl78): New.
546 (print_insn_rl78_g10): New.
547 (print_insn_rl78_g13): New.
548 (print_insn_rl78_g14): New.
549 (rl78_get_disassembler): New.
550
f9d3ecaa
NC		 5512015-04-29 Nick Clifton <nickc@redhat.com>
552
553 * po/fr.po: Updated French translation.
554
4fff86c5
PB		 5552015-04-27 Peter Bergner <bergner@vnet.ibm.com>
556
557 * ppc-opc.c (DCBT_EO): New define.
558 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
559 <lharx>: Likewise.
560 <stbcx.>: Likewise.
561 <sthcx.>: Likewise.
562 <waitrsv>: Do not enable for POWER7 and later.
563 <waitimpl>: Likewise.
564 <dcbt>: Default to the two operand form of the instruction for all
565 "old" cpus. For "new" cpus, use the operand ordering that matches
566 whether the cpu is server or embedded.
567 <dcbtst>: Likewise.
568
3b78cfe1
AK		 5692015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
570
571 * s390-opc.c: New instruction type VV0UU2.
572 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
573 and WFC.
574
04d824a4
JB		 5752015-04-23 Jan Beulich <jbeulich@suse.com>
576
577 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
578 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
579 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
580 (vfpclasspd, vfpclassps): Add %XZ.
581
09708981
L		 5822015-04-15 H.J. Lu <hongjiu.lu@intel.com>
583
584 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
585 (PREFIX_UD_REPZ): Likewise.
586 (PREFIX_UD_REPNZ): Likewise.
587 (PREFIX_UD_DATA): Likewise.
588 (PREFIX_UD_ADDR): Likewise.
589 (PREFIX_UD_LOCK): Likewise.
590
3888916d
L		 5912015-04-15 H.J. Lu <hongjiu.lu@intel.com>
592
593 * i386-dis.c (prefix_requirement): Removed.
594 (print_insn): Don't set prefix_requirement. Check
595 dp->prefix_requirement instead of prefix_requirement.
596
f24bcbaa
L		 5972015-04-15 H.J. Lu <hongjiu.lu@intel.com>
598
599 PR binutils/17898
600 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
601 (PREFIX_MOD_0_0FC7_REG_6): This.
602 (PREFIX_MOD_3_0FC7_REG_6): New.
603 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
604 (prefix_table): Replace PREFIX_0FC7_REG_6 with
605 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
606 PREFIX_MOD_3_0FC7_REG_7.
607 (mod_table): Replace PREFIX_0FC7_REG_6 with
608 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
609 PREFIX_MOD_3_0FC7_REG_7.
610
507bd325
L		 6112015-04-15 H.J. Lu <hongjiu.lu@intel.com>
612
613 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
614 (PREFIX_MANDATORY_REPNZ): Likewise.
615 (PREFIX_MANDATORY_DATA): Likewise.
616 (PREFIX_MANDATORY_ADDR): Likewise.
617 (PREFIX_MANDATORY_LOCK): Likewise.
618 (PREFIX_MANDATORY): Likewise.
619 (PREFIX_UD_SHIFT): Set to 8
620 (PREFIX_UD_REPZ): Updated.
621 (PREFIX_UD_REPNZ): Likewise.
622 (PREFIX_UD_DATA): Likewise.
623 (PREFIX_UD_ADDR): Likewise.
624 (PREFIX_UD_LOCK): Likewise.
625 (PREFIX_IGNORED_SHIFT): New.
626 (PREFIX_IGNORED_REPZ): Likewise.
627 (PREFIX_IGNORED_REPNZ): Likewise.
628 (PREFIX_IGNORED_DATA): Likewise.
629 (PREFIX_IGNORED_ADDR): Likewise.
630 (PREFIX_IGNORED_LOCK): Likewise.
631 (PREFIX_OPCODE): Likewise.
632 (PREFIX_IGNORED): Likewise.
633 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
634 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
635 (three_byte_table): Likewise.
636 (mod_table): Likewise.
637 (mandatory_prefix): Renamed to ...
638 (prefix_requirement): This.
639 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
640 Update PREFIX_90 entry.
641 (get_valid_dis386): Check prefix_requirement to see if a prefix
642 should be ignored.
643 (print_insn): Replace mandatory_prefix with prefix_requirement.
644
f0fba320
RL		 6452015-04-15 Renlin Li <renlin.li@arm.com>
646
647 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
648 use it for ssat and ssat16.
649 (print_insn_thumb32): Add handle case for 'D' control code.
650
bf890a93
IT		 6512015-04-06 Ilya Tocar <ilya.tocar@intel.com>
652 H.J. Lu <hongjiu.lu@intel.com>
653
654 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
655 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
656 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
657 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
658 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
659 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
660 Fill prefix_requirement field.
661 (struct dis386): Add prefix_requirement field.
662 (dis386): Fill prefix_requirement field.
663 (dis386_twobyte): Ditto.
664 (twobyte_has_mandatory_prefix_: Remove.
665 (reg_table): Fill prefix_requirement field.
666 (prefix_table): Ditto.
667 (x86_64_table): Ditto.
668 (three_byte_table): Ditto.
669 (xop_table): Ditto.
670 (vex_table): Ditto.
671 (vex_len_table): Ditto.
672 (vex_w_table): Ditto.
673 (mod_table): Ditto.
674 (bad_opcode): Ditto.
675 (print_insn): Use prefix_requirement.
676 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
677 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
678 (float_reg): Ditto.
679
2f783c1f
MF		 6802015-03-30 Mike Frysinger <vapier@gentoo.org>
681
682 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
683
b9d94d62
L		 6842015-03-29 H.J. Lu <hongjiu.lu@intel.com>
685
686 * Makefile.in: Regenerated.
687
27c49e9a
AB		 6882015-03-25 Anton Blanchard <anton@samba.org>
689
690 * ppc-dis.c (disassemble_init_powerpc): Only initialise
691 powerpc_opcd_indices and vle_opcd_indices once.
692
c4e676f1
AB		 6932015-03-25 Anton Blanchard <anton@samba.org>
694
695 * ppc-opc.c (powerpc_opcodes): Add slbfee.
696
823d2571
TG		 6972015-03-24 Terry Guo <terry.guo@arm.com>
698
699 * arm-dis.c (opcode32): Updated to use new arm feature struct.
700 (opcode16): Likewise.
701 (coprocessor_opcodes): Replace bit with feature struct.
702 (neon_opcodes): Likewise.
703 (arm_opcodes): Likewise.
704 (thumb_opcodes): Likewise.
705 (thumb32_opcodes): Likewise.
706 (print_insn_coprocessor): Likewise.
707 (print_insn_arm): Likewise.
708 (select_arm_features): Follow new feature struct.
709
029f3522
GG		 7102015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
711
712 * i386-dis.c (rm_table): Add clzero.
713 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
714 Add CPU_CLZERO_FLAGS.
715 (cpu_flags): Add CpuCLZERO.
716 * i386-opc.h: Add CpuCLZERO.
717 * i386-opc.tbl: Add clzero.
718 * i386-init.h: Re-generated.
719 * i386-tbl.h: Re-generated.
720
6914869a
AB		 7212015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
722
723 * mips-opc.c (decode_mips_operand): Fix constraint issues
724 with u and y operands.
725
21e20815
AB		 7262015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
727
728 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
729
6b1d7593
AK		 7302015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
731
732 * s390-opc.c: Add new IBM z13 instructions.
733 * s390-opc.txt: Likewise.
734
c8f89a34
JW		 7352015-03-10 Renlin Li <renlin.li@arm.com>
736
737 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
738 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
739 related alias.
740 * aarch64-asm-2.c: Regenerate.
741 * aarch64-dis-2.c: Likewise.
742 * aarch64-opc-2.c: Likewise.
743
d8282f0e
JW		 7442015-03-03 Jiong Wang <jiong.wang@arm.com>
745
746 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
747
ac994365
OE		 7482015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
749
750 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
751 arch_sh_up.
752 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
753 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
754
fd63f640
V		 7552015-02-23 Vinay <Vinay.G@kpit.com>
756
757 * rl78-decode.opc (MOV): Added space between two operands for
758 'mov' instruction in index addressing mode.
759 * rl78-decode.c: Regenerate.
760
f63c1776
PA		 7612015-02-19 Pedro Alves <palves@redhat.com>
762
763 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
764
07774fcc
PA		 7652015-02-10 Pedro Alves <palves@redhat.com>
766 Tom Tromey <tromey@redhat.com>
767
768 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
769 microblaze_and, microblaze_xor.
770 * microblaze-opc.h (opcodes): Adjust.
771
3f8107ab
AM		 7722015-01-28 James Bowman <james.bowman@ftdichip.com>
773
774 * Makefile.am: Add FT32 files.
775 * configure.ac: Handle FT32.
776 * disassemble.c (disassembler): Call print_insn_ft32.
777 * ft32-dis.c: New file.
778 * ft32-opc.c: New file.
779 * Makefile.in: Regenerate.
780 * configure: Regenerate.
781 * po/POTFILES.in: Regenerate.
782
e5fe4957
KLC		 7832015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
784
785 * nds32-asm.c (keyword_sr): Add new system registers.
786
1e2e8c52
AK		 7872015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
788
789 * s390-dis.c (s390_extract_operand): Support vector register
790 operands.
791 (s390_print_insn_with_opcode): Support new operands types and add
792 new handling of optional operands.
793 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
794 and include opcode/s390.h instead.
795 (struct op_struct): New field `flags'.
796 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
797 (dumpTable): Dump flags.
798 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
799 string.
800 * s390-opc.c: Add new operands types, instruction formats, and
801 instruction masks.
802 (s390_opformats): Add new formats for .insn.
803 * s390-opc.txt: Add new instructions.
804
b90efa5b 8052015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 806
b90efa5b 807 Update year range in copyright notice of all files.
bffb6004 808
b90efa5b 809For older changes see ChangeLog-2014
252b5132 810\f
b90efa5b 811Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 812
813Copying and distribution of this file, with or without modification,
814are permitted in any medium without royalty provided the copyright
815notice and this notice are preserved.
816
252b5132 817Local Variables:
2f6d2f85
NC		 818mode: change-log
819left-margin: 8
820fill-column: 74
252b5132
RH		 821version-control: never
822End:
A mirror of the official binutils-gdb repository