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[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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ae3e98b4
AM		 12020-09-02 Alan Modra <amodra@gmail.com>
2
3 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
4 * bpf-ibld.c: Regenerate.
5 * epiphany-ibld.c: Regenerate.
6 * fr30-ibld.c: Regenerate.
7 * frv-ibld.c: Regenerate.
8 * ip2k-ibld.c: Regenerate.
9 * iq2000-ibld.c: Regenerate.
10 * lm32-ibld.c: Regenerate.
11 * m32c-ibld.c: Regenerate.
12 * m32r-ibld.c: Regenerate.
13 * mep-ibld.c: Regenerate.
14 * mt-ibld.c: Regenerate.
15 * or1k-ibld.c: Regenerate.
16 * xc16x-ibld.c: Regenerate.
17 * xstormy16-ibld.c: Regenerate.
18
427202d9
AM		 192020-09-02 Alan Modra <amodra@gmail.com>
20
21 * bfin-dis.c (MASKBITS): Use SIGNBIT.
22
4211a340
CQ		 232020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
24
25 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
26 to CSKYV2_ISA_3E3R3 instruction set.
27
8119cc38
CQ		 282020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
29
30 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
31
8dbe96f0
AM		 322020-09-01 Alan Modra <amodra@gmail.com>
33
34 * mep-ibld.c: Regenerate.
35
e2e82b11
CQ		 362020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
37
38 * csky-dis.c (csky_output_operand): Assign dis_info.value for
39 OPRND_TYPE_VREG.
40
2781f857
AM		 412020-08-30 Alan Modra <amodra@gmail.com>
42
43 * cr16-dis.c: Formatting.
44 (parameter): Delete struct typedef. Use dwordU instead
45 throughout file.
46 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
47 and tbitb.
48 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
49
0c0577f6
AM		 502020-08-29 Alan Modra <amodra@gmail.com>
51
52 PR 26446
53 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
54 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
55
a1e60a1b
AM		 562020-08-28 Alan Modra <amodra@gmail.com>
57
58 PR 26449
59 PR 26450
60 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
61 (extract_normal): Likewise.
62 (insert_normal): Likewise, and move past zero length test.
63 (put_insn_int_value): Handle mask for zero length, use 1UL.
64 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
65 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
66 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
67 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
68
0861f561
CQ		 692020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
70
71 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
72 (csky_dis_info): Add member isa.
73 (csky_find_inst_info): Skip instructions that do not belong to
74 current CPU.
75 (csky_get_disassembler): Get infomation from attribute section.
76 (print_insn_csky): Set defualt ISA flag.
77 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
78 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
79 isa_flag32'type to unsigned 64 bits.
80
31b3f3e6
JM		 812020-08-26 Jose E. Marchesi <jemarch@gnu.org>
82
83 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
84
4449c81a
DF		 852020-08-26 David Faust <david.faust@oracle.com>
86
87 * bpf-desc.c: Regenerate.
88 * bpf-desc.h: Likewise.
89 * bpf-opc.c: Likewise.
90 * bpf-opc.h: Likewise.
91 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
92 ISA when appropriate.
93
8640c87d
AM		 942020-08-25 Alan Modra <amodra@gmail.com>
95
96 PR 26504
97 * vax-dis.c (parse_disassembler_options): Always add at least one
98 to entry_addr_total_slots.
99
531c73a3
CQ		 1002020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
101
102 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
103 in other CPUs to speed up disassembling.
104 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
105 Change plsli.u16 to plsli.16, change sync's operand format.
106
d04aee0f
CQ		 1072020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
108
109 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
110
ccf61261
NC		 1112020-08-21 Nick Clifton <nickc@redhat.com>
112
113 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
114 symbols.
115
d285ba8d
CQ		 1162020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
117
118 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
119
18a8a00e
AM		 1202020-08-19 Alan Modra <amodra@gmail.com>
121
122 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
123 vcmpuq and xvtlsbb.
124
587a4371
PB		 1252020-08-18 Peter Bergner <bergner@linux.ibm.com>
126
127 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
128 <xvcvbf16spn>: ...to this.
129
2e49fd1e
AC		 1302020-08-12 Alex Coplan <alex.coplan@arm.com>
131
132 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
133
79ddc884
NC		 1342020-08-12 Nick Clifton <nickc@redhat.com>
135
136 * po/sr.po: Updated Serbian translation.
137
08770ec2
AM		 1382020-08-11 Alan Modra <amodra@gmail.com>
139
140 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
141
f7cb161e
PW		 1422020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
143
144 * aarch64-opc.c (aarch64_print_operand):
145 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
146 (aarch64_sys_reg_supported_p): Function removed.
147 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
148 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
149 into this function.
150
3eb65174
AM		 1512020-08-10 Alan Modra <amodra@gmail.com>
152
153 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
154 instructions.
155
8b2742a1
AM		 1562020-08-10 Alan Modra <amodra@gmail.com>
157
158 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
159 Enable icbt for power5, miso for power8.
160
5fbec329
AM		 1612020-08-10 Alan Modra <amodra@gmail.com>
162
163 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
164 mtvsrd, and similarly for mfvsrd.
165
563a3225
CG		 1662020-08-04 Christian Groessler <chris@groessler.org>
167 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
168
169 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
170 opcodes (special "out" to absolute address).
171 * z8k-opc.h: Regenerate.
172
41eb8e88
L		 1732020-07-30 H.J. Lu <hongjiu.lu@intel.com>
174
175 PR gas/26305
176 * i386-opc.h (Prefix_Disp8): New.
177 (Prefix_Disp16): Likewise.
178 (Prefix_Disp32): Likewise.
179 (Prefix_Load): Likewise.
180 (Prefix_Store): Likewise.
181 (Prefix_VEX): Likewise.
182 (Prefix_VEX3): Likewise.
183 (Prefix_EVEX): Likewise.
184 (Prefix_REX): Likewise.
185 (Prefix_NoOptimize): Likewise.
186 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
187 * i386-tbl.h: Regenerated.
188
98116973
AA		 1892020-07-29 Andreas Arnez <arnez@linux.ibm.com>
190
191 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
192 default case with abort() instead of printing an error message and
193 continuing, to avoid a maybe-uninitialized warning.
194
2dddfa20
NC		 1952020-07-24 Nick Clifton <nickc@redhat.com>
196
197 * po/de.po: Updated German translation.
198
bf4ba07c
JB		 1992020-07-21 Jan Beulich <jbeulich@suse.com>
200
201 * i386-dis.c (OP_E_memory): Revert previous change.
202
04c662e2
L		 2032020-07-15 H.J. Lu <hongjiu.lu@intel.com>
204
205 PR gas/26237
206 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
207 without base nor index registers.
208
f0e8d0ba
JB		 2092020-07-15 Jan Beulich <jbeulich@suse.com>
210
211 * i386-dis.c (putop): Move 'V' and 'W' handling.
212
c3f5525f
JB		 2132020-07-15 Jan Beulich <jbeulich@suse.com>
214
215 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
216 construct for push/pop of register.
217 (putop): Honor cond when handling 'P'. Drop handling of plain
218 'V'.
219
36938cab
JB		 2202020-07-15 Jan Beulich <jbeulich@suse.com>
221
222 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
223 description. Drop '&' description. Use P for push of immediate,
224 pushf/popf, enter, and leave. Use %LP for lret/retf.
225 (dis386_twobyte): Use P for push/pop of fs/gs.
226 (reg_table): Use P for push/pop. Use @ for near call/jmp.
227 (x86_64_table): Use P for far call/jmp.
228 (putop): Drop handling of 'U' and '&'. Move and adjust handling
229 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
230 labels.
231 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
232 and dqw_mode (unconditional).
233
8e58ef80
L		 2342020-07-14 H.J. Lu <hongjiu.lu@intel.com>
235
236 PR gas/26237
237 * i386-dis.c (OP_E_memory): Without base nor index registers,
238 32-bit displacement to 64 bits.
239
570b0ed6
CZ		 2402020-07-14 Claudiu Zissulescu <claziss@gmail.com>
241
242 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
243 faulty double register pair is detected.
244
bfbd9438
JB		 2452020-07-14 Jan Beulich <jbeulich@suse.com>
246
247 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
248
78467458
JB		 2492020-07-14 Jan Beulich <jbeulich@suse.com>
250
251 * i386-dis.c (OP_R, Rm): Delete.
252 (MOD_0F24, MOD_0F26): Rename to ...
253 (X86_64_0F24, X86_64_0F26): ... respectively.
254 (dis386): Update 'L' and 'Z' comments.
255 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
256 table references.
257 (mod_table): Move opcode 0F24 and 0F26 entries ...
258 (x86_64_table): ... here.
259 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
260 'Z' case block.
261
464d2b65
JB		 2622020-07-14 Jan Beulich <jbeulich@suse.com>
263
264 * i386-dis.c (Rd, Rdq, MaskR): Delete.
265 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
266 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
267 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
268 MOD_EVEX_0F387C): New enumerators.
269 (reg_table): Use Edq for rdssp.
270 (prefix_table): Use Edq for incssp.
271 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
272 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
273 ktest*, and kshift*. Use Edq / MaskE for kmov*.
274 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
275 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
276 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
277 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
278 0F3828_P_1 and 0F3838_P_1.
279 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
280 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
281
035e7389
JB		 2822020-07-14 Jan Beulich <jbeulich@suse.com>
283
284 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
285 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
286 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
287 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
288 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
289 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
290 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
291 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
292 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
293 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
294 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
295 (reg_table, prefix_table, three_byte_table, vex_table,
296 vex_len_table, mod_table, rm_table): Replace / remove respective
297 entries.
298 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
299 of PREFIX_DATA in used_prefixes.
300
bb5b3501
JB		 3012020-07-14 Jan Beulich <jbeulich@suse.com>
302
303 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
304 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
305 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
306 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
307 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
308 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
309 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
310 VEX_W_0F3A33_L_0): Delete.
311 (dis386): Adjust "BW" description.
312 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
313 0F3A31, 0F3A32, and 0F3A33.
314 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
315 entries.
316 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
317 entries.
318
7531c613
JB		 3192020-07-14 Jan Beulich <jbeulich@suse.com>
320
321 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
322 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
323 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
324 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
325 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
326 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
327 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
328 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
329 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
330 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
331 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
332 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
333 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
334 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
335 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
336 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
337 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
338 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
339 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
340 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
341 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
342 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
343 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
344 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
345 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
346 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
347 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
348 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
349 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
350 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
351 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
352 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
353 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
354 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
355 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
356 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
357 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
358 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
359 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
360 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
361 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
362 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
363 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
364 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
365 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
366 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
367 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
368 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
369 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
370 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
371 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
372 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
373 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
374 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
375 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
376 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
377 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
378 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
379 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
380 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
381 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
382 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
383 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
384 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
385 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
386 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
387 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
388 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
389 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
390 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
391 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
392 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
393 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
394 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
395 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
396 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
397 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
398 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
399 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
400 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
401 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
402 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
403 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
404 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
405 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
406 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
407 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
408 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
409 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
410 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
411 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
412 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
413 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
414 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
415 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
416 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
417 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
418 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
419 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
420 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
421 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
422 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
423 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
424 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
425 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
426 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
427 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
428 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
429 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
430 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
431 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
432 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
433 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
434 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
435 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
436 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
437 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
438 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
439 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
440 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
441 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
442 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
443 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
444 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
445 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
446 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
447 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
448 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
449 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
450 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
451 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
452 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
453 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
454 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
455 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
456 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
457 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
458 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
459 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
460 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
461 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
462 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
463 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
464 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
465 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
466 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
467 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
468 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
469 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
470 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
471 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
472 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
473 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
474 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
475 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
476 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
477 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
478 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
479 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
480 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
481 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
482 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
483 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
484 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
485 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
486 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
487 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
488 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
489 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
490 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
491 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
492 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
493 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
494 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
495 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
496 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
497 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
498 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
499 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
500 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
501 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
502 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
503 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
504 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
505 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
506 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
507 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
508 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
509 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
510 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
511 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
512 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
513 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
514 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
515 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
516 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
517 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
518 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
519 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
520 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
521 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
522 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
523 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
524 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
525 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
526 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
527 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
528 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
529 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
530 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
531 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
532 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
533 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
534 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
535 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
536 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
537 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
538 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
539 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
540 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
541 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
542 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
543 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
544 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
545 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
546 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
547 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
548 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
549 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
550 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
551 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
552 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
553 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
554 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
555 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
556 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
557 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
558 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
559 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
560 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
561 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
562 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
563 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
564 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
565 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
566 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
567 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
568 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
569 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
570 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
571 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
572 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
573 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
574 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
575 EVEX_W_0F3A72_P_2): Rename to ...
576 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
577 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
578 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
579 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
580 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
581 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
582 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
583 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
584 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
585 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
586 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
587 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
588 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
589 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
590 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
591 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
592 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
593 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
594 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
595 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
596 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
597 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
598 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
599 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
600 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
601 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
602 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
603 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
604 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
605 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
606 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
607 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
608 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
609 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
610 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
611 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
612 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
613 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
614 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
615 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
616 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
617 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
618 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
619 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
620 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
621 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
622 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
623 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
624 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
625 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
626 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
627 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
628 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
629 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
630 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
631 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
632 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
633 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
634 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
635 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
636 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
637 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
638 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
639 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
640 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
641 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
642 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
643 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
644 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
645 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
646 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
647 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
648 respectively.
649 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
650 vex_w_table, mod_table): Replace / remove respective entries.
651 (print_insn): Move up dp->prefix_requirement handling. Handle
652 PREFIX_DATA.
653 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
654 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
655 Replace / remove respective entries.
656
17d3c7ec
JB		 6572020-07-14 Jan Beulich <jbeulich@suse.com>
658
659 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
660 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
661 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
662 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
663 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
664 the latter two.
665 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
666 0F2C, 0F2D, 0F2E, and 0F2F.
667 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
668 0F2F table entries.
669
41f5efc6
JB		 6702020-07-14 Jan Beulich <jbeulich@suse.com>
671
672 * i386-dis.c (OP_VexR, VexScalarR): New.
673 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
674 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
675 need_vex_reg): Delete.
676 (prefix_table): Replace VexScalar by VexScalarR and
677 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
678 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
679 (vex_len_table): Replace EXqVexScalarS by EXqS.
680 (get_valid_dis386): Don't set need_vex_reg.
681 (print_insn): Don't initialize need_vex_reg.
682 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
683 q_scalar_swap_mode cases.
684 (OP_EX): Don't check for d_scalar_swap_mode and
685 q_scalar_swap_mode.
686 (OP_VEX): Done check need_vex_reg.
687 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
688 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
689 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
690
89e65d17
JB		 6912020-07-14 Jan Beulich <jbeulich@suse.com>
692
693 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
694 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
695 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
696 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
697 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
698 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
699 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
700 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
701 (vex_table): Replace Vex128 by Vex.
702 (vex_len_table): Likewise. Adjust referenced enum names.
703 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
704 referenced enum names.
705 (OP_VEX): Drop vex128_mode and vex256_mode cases.
706 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
707
492a76aa
JB		 7082020-07-14 Jan Beulich <jbeulich@suse.com>
709
710 * i386-dis.c (dis386): "LW" description now applies to "DQ".
711 (putop): Handle "DQ". Don't handle "LW" anymore.
712 (prefix_table, mod_table): Replace %LW by %DQ.
713 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
714
059edf8b
JB		 7152020-07-14 Jan Beulich <jbeulich@suse.com>
716
717 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
718 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
719 d_scalar_swap_mode case handling. Move shift adjsutment into
720 the case its applicable to.
721
4726e9a4
JB		 7222020-07-14 Jan Beulich <jbeulich@suse.com>
723
724 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
725 (EXbScalar, EXwScalar): Fold to ...
726 (EXbwUnit): ... this.
727 (b_scalar_mode, w_scalar_mode): Fold to ...
728 (bw_unit_mode): ... this.
729 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
730 w_scalar_mode handling by bw_unit_mode one.
731 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
732 ...
733 * i386-dis-evex-prefix.h: ... here.
734
b24d668c
JB		 7352020-07-14 Jan Beulich <jbeulich@suse.com>
736
737 * i386-dis.c (PCMPESTR_Fixup): Delete.
738 (dis386): Adjust "LQ" description.
739 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
740 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
741 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
742 vpcmpestrm, and vpcmpestri.
743 (putop): Honor "cond" when handling LQ.
744 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
745 vcvtsi2ss and vcvtusi2ss.
746 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
747 vcvtsi2sd and vcvtusi2sd.
748
c4de7606
JB		 7492020-07-14 Jan Beulich <jbeulich@suse.com>
750
751 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
752 (simd_cmp_op): Add const.
753 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
754 (CMP_Fixup): Handle VEX case.
755 (prefix_table): Replace VCMP by CMP.
756 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
757
9ab00b61
JB		 7582020-07-14 Jan Beulich <jbeulich@suse.com>
759
760 * i386-dis.c (MOVBE_Fixup): Delete.
761 (Mv): Define.
762 (prefix_table): Use Mv for movbe entries.
763
2875b28a
JB		 7642020-07-14 Jan Beulich <jbeulich@suse.com>
765
766 * i386-dis.c (CRC32_Fixup): Delete.
767 (prefix_table): Use Eb/Ev for crc32 entries.
768
e184e611
JB		 7692020-07-14 Jan Beulich <jbeulich@suse.com>
770
771 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
772 Conditionalize invocations of "USED_REX (0)".
773
e8b5d5f9
JB		 7742020-07-14 Jan Beulich <jbeulich@suse.com>
775
776 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
777 CH, DH, BH, AX, DX): Delete.
778 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
779 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
780 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
781
260cd341
LC		 7822020-07-10 Lili Cui <lili.cui@intel.com>
783
784 * i386-dis.c (TMM): New.
785 (EXtmm): Likewise.
786 (VexTmm): Likewise.
787 (MVexSIBMEM): Likewise.
788 (tmm_mode): Likewise.
789 (vex_sibmem_mode): Likewise.
790 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
791 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
792 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
793 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
794 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
795 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
796 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
797 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
798 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
799 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
800 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
801 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
802 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
803 (PREFIX_VEX_0F3849_X86_64): Likewise.
804 (PREFIX_VEX_0F384B_X86_64): Likewise.
805 (PREFIX_VEX_0F385C_X86_64): Likewise.
806 (PREFIX_VEX_0F385E_X86_64): Likewise.
807 (X86_64_VEX_0F3849): Likewise.
808 (X86_64_VEX_0F384B): Likewise.
809 (X86_64_VEX_0F385C): Likewise.
810 (X86_64_VEX_0F385E): Likewise.
811 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
812 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
813 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
814 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
815 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
816 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
817 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
818 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
819 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
820 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
821 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
822 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
823 (VEX_W_0F3849_X86_64_P_0): Likewise.
824 (VEX_W_0F3849_X86_64_P_2): Likewise.
825 (VEX_W_0F3849_X86_64_P_3): Likewise.
826 (VEX_W_0F384B_X86_64_P_1): Likewise.
827 (VEX_W_0F384B_X86_64_P_2): Likewise.
828 (VEX_W_0F384B_X86_64_P_3): Likewise.
829 (VEX_W_0F385C_X86_64_P_1): Likewise.
830 (VEX_W_0F385E_X86_64_P_0): Likewise.
831 (VEX_W_0F385E_X86_64_P_1): Likewise.
832 (VEX_W_0F385E_X86_64_P_2): Likewise.
833 (VEX_W_0F385E_X86_64_P_3): Likewise.
834 (names_tmm): Likewise.
835 (att_names_tmm): Likewise.
836 (intel_operand_size): Handle void_mode.
837 (OP_XMM): Handle tmm_mode.
838 (OP_EX): Likewise.
839 (OP_VEX): Likewise.
840 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
841 CpuAMX_BF16 and CpuAMX_TILE.
842 (operand_type_shorthands): Add RegTMM.
843 (operand_type_init): Likewise.
844 (operand_types): Add Tmmword.
845 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
846 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
847 * i386-opc.h (CpuAMX_INT8): New.
848 (CpuAMX_BF16): Likewise.
849 (CpuAMX_TILE): Likewise.
850 (SIBMEM): Likewise.
851 (Tmmword): Likewise.
852 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
853 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
854 (i386_operand_type): Add tmmword.
855 * i386-opc.tbl: Add AMX instructions.
856 * i386-reg.tbl: Add AMX registers.
857 * i386-init.h: Regenerated.
858 * i386-tbl.h: Likewise.
859
467bbef0
JB		 8602020-07-08 Jan Beulich <jbeulich@suse.com>
861
862 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
863 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
864 Rename to ...
865 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
866 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
867 respectively.
868 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
869 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
870 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
871 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
872 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
873 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
874 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
875 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
876 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
877 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
878 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
879 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
880 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
881 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
882 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
883 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
884 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
885 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
886 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
887 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
888 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
889 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
890 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
891 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
892 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
893 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
894 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
895 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
896 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
897 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
898 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
899 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
900 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
901 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
902 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
903 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
904 (reg_table): Re-order XOP entries. Adjust their operands.
905 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
906 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
907 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
908 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
909 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
910 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
911 entries by references ...
912 (vex_len_table): ... to resepctive new entries here. For several
913 new and existing entries reference ...
914 (vex_w_table): ... new entries here.
915 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
916
6384fd9e
JB		 9172020-07-08 Jan Beulich <jbeulich@suse.com>
918
919 * i386-dis.c (XMVexScalarI4): Define.
920 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
921 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
922 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
923 (vex_len_table): Move scalar FMA4 entries ...
924 (prefix_table): ... here.
925 (OP_REG_VexI4): Handle scalar_mode.
926 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
927 * i386-tbl.h: Re-generate.
928
e6123d0c
JB		 9292020-07-08 Jan Beulich <jbeulich@suse.com>
930
931 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
932 Vex_2src_2): Delete.
933 (OP_VexW, VexW): New.
934 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
935 for shifts and rotates by register.
936
93abb146
JB		 9372020-07-08 Jan Beulich <jbeulich@suse.com>
938
939 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
940 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
941 OP_EX_VexReg): Delete.
942 (OP_VexI4, VexI4): New.
943 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
944 (prefix_table): ... here.
945 (print_insn): Drop setting of vex_w_done.
946
b13b1bc0
JB		 9472020-07-08 Jan Beulich <jbeulich@suse.com>
948
949 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
950 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
951 (xop_table): Replace operands of 4-operand insns.
952 (OP_REG_VexI4): Move VEX.W based operand swaping here.
953
f337259f
CZ		 9542020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
955
956 * arc-opc.c (insert_rbd): New function.
957 (RBD): Define.
958 (RBDdup): Likewise.
959 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
960 instructions.
961
931452b6
JB		 9622020-07-07 Jan Beulich <jbeulich@suse.com>
963
964 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
965 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
966 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
967 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
968 Delete.
969 (putop): Handle "BW".
970 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
971 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
972 and 0F3A3F ...
973 * i386-dis-evex-prefix.h: ... here.
974
b5b098c2
JB		 9752020-07-06 Jan Beulich <jbeulich@suse.com>
976
977 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
978 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
979 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
980 VEX_W_0FXOP_09_83): New enumerators.
981 (xop_table): Reference the above.
982 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
983 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
984 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
985 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
986
21a3faeb
JB		 9872020-07-06 Jan Beulich <jbeulich@suse.com>
988
989 * i386-dis.c (EVEX_W_0F3838_P_1,
990 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
991 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
992 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
993 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
994 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
995 (putop): Centralize management of last[]. Delete SAVE_LAST.
996 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
997 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
998 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
999 * i386-dis-evex-prefix.h: here.
1000
bc152a17
JB		 10012020-07-06 Jan Beulich <jbeulich@suse.com>
1002
1003 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1004 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1005 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1006 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1007 enumerators.
1008 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1009 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1010 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1011 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1012 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1013 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1014 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1015 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1016 these, respectively.
1017 * i386-dis-evex-len.h: Adjust comments.
1018 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1019 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1020 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1021 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1022 MOD_EVEX_0F385B_P_2_W_1 table entries.
1023 * i386-dis-evex-w.h: Reference mod_table[] for
1024 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1025 EVEX_W_0F385B_P_2.
1026
c82a99a0
JB		 10272020-07-06 Jan Beulich <jbeulich@suse.com>
1028
1029 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1030 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1031 EXymm.
1032 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1033 Likewise. Mark 256-bit entries invalid.
1034
fedfb81e
JB		 10352020-07-06 Jan Beulich <jbeulich@suse.com>
1036
1037 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1038 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1039 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1040 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1041 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1042 PREFIX_EVEX_0F382B): Delete.
1043 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1044 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1045 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1046 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1047 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1048 to ...
1049 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1050 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1051 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1052 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1053 respectively.
1054 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1055 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1056 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1057 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1058 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1059 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1060 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1061 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1062 PREFIX_EVEX_0F382B): Remove table entries.
1063 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1064 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1065 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1066
3a57774c
JB		 10672020-07-06 Jan Beulich <jbeulich@suse.com>
1068
1069 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1070 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1071 enumerators.
1072 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1073 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1074 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1075 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1076 entries.
1077
e74d9fa9
JB		 10782020-07-06 Jan Beulich <jbeulich@suse.com>
1079
1080 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1081 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1082 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1083 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1084 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1085 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1086 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1087 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1088 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1089 entries.
1090
6431c801
JB		 10912020-07-06 Jan Beulich <jbeulich@suse.com>
1092
1093 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1094 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1095 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1096 respectively.
1097 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1098 entries.
1099 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1100 opcode 0F3A1D.
1101 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1102 entry.
1103 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1104
6df22cf6
JB		 11052020-07-06 Jan Beulich <jbeulich@suse.com>
1106
1107 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1108 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1109 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1110 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1111 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1112 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1113 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1114 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1115 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1116 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1117 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1118 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1119 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1120 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1121 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1122 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1123 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1124 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1125 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1126 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1127 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1128 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1129 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1130 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1131 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1132 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1133 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1134 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1135 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1136 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1137 (prefix_table): Add EXxEVexR to FMA table entries.
1138 (OP_Rounding): Move abort() invocation.
1139 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1140 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1141 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1142 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1143 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1144 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1145 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1146 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1147 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1148 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1149 0F3ACE, 0F3ACF.
1150 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1151 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1152 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1153 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1154 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1155 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1156 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1157 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1158 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1159 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1160 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1161 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1162 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1163 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1164 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1165 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1166 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1167 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1168 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1169 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1170 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1171 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1172 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1173 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1174 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1175 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1176 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1177 Delete table entries.
1178 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1179 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1180 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1181 Likewise.
1182
39e0f456
JB		 11832020-07-06 Jan Beulich <jbeulich@suse.com>
1184
1185 * i386-dis.c (EXqScalarS): Delete.
1186 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1187 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1188
5b872f7d
JB		 11892020-07-06 Jan Beulich <jbeulich@suse.com>
1190
1191 * i386-dis.c (safe-ctype.h): Include.
1192 (EXdScalar, EXqScalar): Delete.
1193 (d_scalar_mode, q_scalar_mode): Delete.
1194 (prefix_table, vex_len_table): Use EXxmm_md in place of
1195 EXdScalar and EXxmm_mq in place of EXqScalar.
1196 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1197 d_scalar_mode and q_scalar_mode.
1198 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1199 (vmovsd): Use EXxmm_mq.
1200
ddc73fa9
NC		 12012020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1202
1203 PR 26204
1204 * arc-dis.c: Fix spelling mistake.
1205 * po/opcodes.pot: Regenerate.
1206
17550be7
NC		 12072020-07-06 Nick Clifton <nickc@redhat.com>
1208
1209 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1210 * po/uk.po: Updated Ukranian translation.
1211
b19d852d
NC		 12122020-07-04 Nick Clifton <nickc@redhat.com>
1213
1214 * configure: Regenerate.
1215 * po/opcodes.pot: Regenerate.
1216
b115b9fd
NC		 12172020-07-04 Nick Clifton <nickc@redhat.com>
1218
1219 Binutils 2.35 branch created.
1220
c2ecccb3
L		 12212020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1222
1223 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1224 * i386-opc.h (VexSwapSources): New.
1225 (i386_opcode_modifier): Add vexswapsources.
1226 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1227 with two source operands swapped.
1228 * i386-tbl.h: Regenerated.
1229
08ccfccf
NC		 12302020-06-30 Nelson Chu <nelson.chu@sifive.com>
1231
1232 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1233 unprivileged CSR can also be initialized.
1234
279edac5
AM		 12352020-06-29 Alan Modra <amodra@gmail.com>
1236
1237 * arm-dis.c: Use C style comments.
1238 * cr16-opc.c: Likewise.
1239 * ft32-dis.c: Likewise.
1240 * moxie-opc.c: Likewise.
1241 * tic54x-dis.c: Likewise.
1242 * s12z-opc.c: Remove useless comment.
1243 * xgate-dis.c: Likewise.
1244
e978ad62
L		 12452020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1246
1247 * i386-opc.tbl: Add a blank line.
1248
63112cd6
L		 12492020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1250
1251 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1252 (VecSIB128): Renamed to ...
1253 (VECSIB128): This.
1254 (VecSIB256): Renamed to ...
1255 (VECSIB256): This.
1256 (VecSIB512): Renamed to ...
1257 (VECSIB512): This.
1258 (VecSIB): Renamed to ...
1259 (SIB): This.
1260 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1261 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1262 (VecSIB256): Likewise.
1263 (VecSIB512): Likewise.
79b32e73 1264 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1265 and VecSIB512, respectively.
1266
d1c36125
JB		 12672020-06-26 Jan Beulich <jbeulich@suse.com>
1268
1269 * i386-dis.c: Adjust description of I macro.
1270 (x86_64_table): Drop use of I.
1271 (float_mem): Replace use of I.
1272 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1273
2a1bb84c
JB		 12742020-06-26 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-dis.c: (print_insn): Avoid straight assignment to
1277 priv.orig_sizeflag when processing -M sub-options.
1278
8f570d62
JB		 12792020-06-25 Jan Beulich <jbeulich@suse.com>
1280
1281 * i386-dis.c: Adjust description of J macro.
1282 (dis386, x86_64_table, mod_table): Replace J.
1283 (putop): Remove handling of J.
1284
464dc4af
JB		 12852020-06-25 Jan Beulich <jbeulich@suse.com>
1286
1287 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1288
589958d6
JB		 12892020-06-25 Jan Beulich <jbeulich@suse.com>
1290
1291 * i386-dis.c: Adjust description of "LQ" macro.
1292 (dis386_twobyte): Use LQ for sysret.
1293 (putop): Adjust handling of LQ.
1294
39ff0b81
NC		 12952020-06-22 Nelson Chu <nelson.chu@sifive.com>
1296
1297 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1298 * riscv-dis.c: Include elfxx-riscv.h.
1299
d27c357a
JB		 13002020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1301
1302 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1303
6fde587f
CL		 13042020-06-17 Lili Cui <lili.cui@intel.com>
1305
1306 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1307
efe30057
L		 13082020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1309
1310 PR gas/26115
1311 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1312 * i386-opc.tbl: Likewise.
1313 * i386-tbl.h: Regenerated.
1314
d8af286f
NC		 13152020-06-12 Nelson Chu <nelson.chu@sifive.com>
1316
1317 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1318
14962256
AC		 13192020-06-11 Alex Coplan <alex.coplan@arm.com>
1320
1321 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1322 (SR_CORE): Likewise.
1323 (SR_FEAT): Likewise.
1324 (SR_RNG): Likewise.
1325 (SR_V8_1): Likewise.
1326 (SR_V8_2): Likewise.
1327 (SR_V8_3): Likewise.
1328 (SR_V8_4): Likewise.
1329 (SR_PAN): Likewise.
1330 (SR_RAS): Likewise.
1331 (SR_SSBS): Likewise.
1332 (SR_SVE): Likewise.
1333 (SR_ID_PFR2): Likewise.
1334 (SR_PROFILE): Likewise.
1335 (SR_MEMTAG): Likewise.
1336 (SR_SCXTNUM): Likewise.
1337 (aarch64_sys_regs): Refactor to store feature information in the table.
1338 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1339 that now describe their own features.
1340 (aarch64_pstatefield_supported_p): Likewise.
1341
f9630fa6
L		 13422020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1343
1344 * i386-dis.c (prefix_table): Fix a typo in comments.
1345
73239888
JB		 13462020-06-09 Jan Beulich <jbeulich@suse.com>
1347
1348 * i386-dis.c (rex_ignored): Delete.
1349 (ckprefix): Drop rex_ignored initialization.
1350 (get_valid_dis386): Drop setting of rex_ignored.
1351 (print_insn): Drop checking of rex_ignored. Don't record data
1352 size prefix as used with VEX-and-alike encodings.
1353
18897deb
JB		 13542020-06-09 Jan Beulich <jbeulich@suse.com>
1355
1356 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1357 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1358 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1359 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1360 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1361 VEX_0F12, and VEX_0F16.
1362 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1363 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1364 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1365 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1366 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1367 MOD_VEX_0F16_PREFIX_2 entries.
1368
97e6786a
JB		 13692020-06-09 Jan Beulich <jbeulich@suse.com>
1370
1371 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1372 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1373 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1374 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1375 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1376 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1377 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1378 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1379 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1380 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1381 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1382 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1383 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1384 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1385 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1386 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1387 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1388 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1389 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1390 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1391 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1392 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1393 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1394 EVEX_W_0FC6_P_2): Delete.
1395 (print_insn): Add EVEX.W vs embedded prefix consistency check
1396 to prefix validation.
1397 * i386-dis-evex.h (evex_table): Don't further descend for
1398 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1399 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1400 and 0F2B.
1401 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1402 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1403 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1404 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1405 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1406 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1407 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1408 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1409 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1410 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1411 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1412 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1413 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1414 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1415 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1416 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1417 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1418 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1419 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1420 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1421 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1422 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1423 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1424 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1425 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1426 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1427 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1428
bf926894
JB		 14292020-06-09 Jan Beulich <jbeulich@suse.com>
1430
1431 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1432 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1433 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1434 vmovmskpX.
1435 (print_insn): Drop pointless check against bad_opcode. Split
1436 prefix validation into legacy and VEX-and-alike parts.
1437 (putop): Re-work 'X' macro handling.
1438
a5aaedb9
JB		 14392020-06-09 Jan Beulich <jbeulich@suse.com>
1440
1441 * i386-dis.c (MOD_0F51): Rename to ...
1442 (MOD_0F50): ... this.
1443
26417f19
AC		 14442020-06-08 Alex Coplan <alex.coplan@arm.com>
1445
1446 * arm-dis.c (arm_opcodes): Add dfb.
1447 (thumb32_opcodes): Add dfb.
1448
8a6fb3f9
JB		 14492020-06-08 Jan Beulich <jbeulich@suse.com>
1450
1451 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1452
1424c35d
AM		 14532020-06-06 Alan Modra <amodra@gmail.com>
1454
1455 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1456
d3d1cc7b
AM		 14572020-06-05 Alan Modra <amodra@gmail.com>
1458
1459 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1460 size is large enough.
1461
d8740be1
JM		 14622020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1463
1464 * disassemble.c (disassemble_init_for_target): Set endian_code for
1465 bpf targets.
1466 * bpf-desc.c: Regenerate.
1467 * bpf-opc.c: Likewise.
1468 * bpf-dis.c: Likewise.
1469
e9bffec9
JM		 14702020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1471
1472 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1473 (cgen_put_insn_value): Likewise.
1474 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1475 * cgen-dis.in (print_insn): Likewise.
1476 * cgen-ibld.in (insert_1): Likewise.
1477 (insert_1): Likewise.
1478 (insert_insn_normal): Likewise.
1479 (extract_1): Likewise.
1480 * bpf-dis.c: Regenerate.
1481 * bpf-ibld.c: Likewise.
1482 * bpf-ibld.c: Likewise.
1483 * cgen-dis.in: Likewise.
1484 * cgen-ibld.in: Likewise.
1485 * cgen-opc.c: Likewise.
1486 * epiphany-dis.c: Likewise.
1487 * epiphany-ibld.c: Likewise.
1488 * fr30-dis.c: Likewise.
1489 * fr30-ibld.c: Likewise.
1490 * frv-dis.c: Likewise.
1491 * frv-ibld.c: Likewise.
1492 * ip2k-dis.c: Likewise.
1493 * ip2k-ibld.c: Likewise.
1494 * iq2000-dis.c: Likewise.
1495 * iq2000-ibld.c: Likewise.
1496 * lm32-dis.c: Likewise.
1497 * lm32-ibld.c: Likewise.
1498 * m32c-dis.c: Likewise.
1499 * m32c-ibld.c: Likewise.
1500 * m32r-dis.c: Likewise.
1501 * m32r-ibld.c: Likewise.
1502 * mep-dis.c: Likewise.
1503 * mep-ibld.c: Likewise.
1504 * mt-dis.c: Likewise.
1505 * mt-ibld.c: Likewise.
1506 * or1k-dis.c: Likewise.
1507 * or1k-ibld.c: Likewise.
1508 * xc16x-dis.c: Likewise.
1509 * xc16x-ibld.c: Likewise.
1510 * xstormy16-dis.c: Likewise.
1511 * xstormy16-ibld.c: Likewise.
1512
b3db6d07
JM		 15132020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1514
1515 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1516 (print_insn_): Handle instruction endian.
1517 * bpf-dis.c: Regenerate.
1518 * bpf-desc.c: Regenerate.
1519 * epiphany-dis.c: Likewise.
1520 * epiphany-desc.c: Likewise.
1521 * fr30-dis.c: Likewise.
1522 * fr30-desc.c: Likewise.
1523 * frv-dis.c: Likewise.
1524 * frv-desc.c: Likewise.
1525 * ip2k-dis.c: Likewise.
1526 * ip2k-desc.c: Likewise.
1527 * iq2000-dis.c: Likewise.
1528 * iq2000-desc.c: Likewise.
1529 * lm32-dis.c: Likewise.
1530 * lm32-desc.c: Likewise.
1531 * m32c-dis.c: Likewise.
1532 * m32c-desc.c: Likewise.
1533 * m32r-dis.c: Likewise.
1534 * m32r-desc.c: Likewise.
1535 * mep-dis.c: Likewise.
1536 * mep-desc.c: Likewise.
1537 * mt-dis.c: Likewise.
1538 * mt-desc.c: Likewise.
1539 * or1k-dis.c: Likewise.
1540 * or1k-desc.c: Likewise.
1541 * xc16x-dis.c: Likewise.
1542 * xc16x-desc.c: Likewise.
1543 * xstormy16-dis.c: Likewise.
1544 * xstormy16-desc.c: Likewise.
1545
4ee4189f
NC		 15462020-06-03 Nick Clifton <nickc@redhat.com>
1547
1548 * po/sr.po: Updated Serbian translation.
1549
44730156
NC		 15502020-06-03 Nelson Chu <nelson.chu@sifive.com>
1551
1552 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1553 (riscv_get_priv_spec_class): Likewise.
1554
3c3d0376
AM		 15552020-06-01 Alan Modra <amodra@gmail.com>
1556
1557 * bpf-desc.c: Regenerate.
1558
78c1c354
JM		 15592020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1560 David Faust <david.faust@oracle.com>
1561
1562 * bpf-desc.c: Regenerate.
1563 * bpf-opc.h: Likewise.
1564 * bpf-opc.c: Likewise.
1565 * bpf-dis.c: Likewise.
1566
efcf5fb5
AM		 15672020-05-28 Alan Modra <amodra@gmail.com>
1568
1569 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1570 values.
1571
ab382d64
AM		 15722020-05-28 Alan Modra <amodra@gmail.com>
1573
1574 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1575 immediates.
1576 (print_insn_ns32k): Revert last change.
1577
151f5de4
NC		 15782020-05-28 Nick Clifton <nickc@redhat.com>
1579
1580 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1581 static.
1582
25e1eca8
SL		 15832020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1584
1585 Fix extraction of signed constants in nios2 disassembler (again).
1586
1587 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1588 extractions of signed fields.
1589
57b17940
SSF		 15902020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1591
1592 * s390-opc.txt: Relocate vector load/store instructions with
1593 additional alignment parameter and change architecture level
1594 constraint from z14 to z13.
1595
d96bf37b
AM		 15962020-05-21 Alan Modra <amodra@gmail.com>
1597
1598 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1599 * sparc-dis.c: Likewise.
1600 * tic4x-dis.c: Likewise.
1601 * xtensa-dis.c: Likewise.
1602 * bpf-desc.c: Regenerate.
1603 * epiphany-desc.c: Regenerate.
1604 * fr30-desc.c: Regenerate.
1605 * frv-desc.c: Regenerate.
1606 * ip2k-desc.c: Regenerate.
1607 * iq2000-desc.c: Regenerate.
1608 * lm32-desc.c: Regenerate.
1609 * m32c-desc.c: Regenerate.
1610 * m32r-desc.c: Regenerate.
1611 * mep-asm.c: Regenerate.
1612 * mep-desc.c: Regenerate.
1613 * mt-desc.c: Regenerate.
1614 * or1k-desc.c: Regenerate.
1615 * xc16x-desc.c: Regenerate.
1616 * xstormy16-desc.c: Regenerate.
1617
8f595e9b
NC		 16182020-05-20 Nelson Chu <nelson.chu@sifive.com>
1619
1620 * riscv-opc.c (riscv_ext_version_table): The table used to store
1621 all information about the supported spec and the corresponding ISA
1622 versions. Currently, only Zicsr is supported to verify the
1623 correctness of Z sub extension settings. Others will be supported
1624 in the future patches.
1625 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1626 classes and the corresponding strings.
1627 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1628 spec class by giving a ISA spec string.
1629 * riscv-opc.c (struct priv_spec_t): New structure.
1630 (struct priv_spec_t priv_specs): List for all supported privilege spec
1631 classes and the corresponding strings.
1632 (riscv_get_priv_spec_class): New function. Get the corresponding
1633 privilege spec class by giving a spec string.
1634 (riscv_get_priv_spec_name): New function. Get the corresponding
1635 privilege spec string by giving a CSR version class.
1636 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1637 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1638 according to the chosen version. Build a hash table riscv_csr_hash to
1639 store the valid CSR for the chosen pirv verison. Dump the direct
1640 CSR address rather than it's name if it is invalid.
1641 (parse_riscv_dis_option_without_args): New function. Parse the options
1642 without arguments.
1643 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1644 parse the options without arguments first, and then handle the options
1645 with arguments. Add the new option -Mpriv-spec, which has argument.
1646 * riscv-dis.c (print_riscv_disassembler_options): Add description
1647 about the new OBJDUMP option.
1648
3d205eb4
PB		 16492020-05-19 Peter Bergner <bergner@linux.ibm.com>
1650
1651 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1652 WC values on POWER10 sync, dcbf and wait instructions.
1653 (insert_pl, extract_pl): New functions.
1654 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1655 (LS3): New , 3-bit L for sync.
1656 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1657 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1658 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1659 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1660 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1661 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1662 <wait>: Enable PL operand on POWER10.
1663 <dcbf>: Enable L3OPT operand on POWER10.
1664 <sync>: Enable SC2 operand on POWER10.
1665
a501eb44
SH		 16662020-05-19 Stafford Horne <shorne@gmail.com>
1667
1668 PR 25184
1669 * or1k-asm.c: Regenerate.
1670 * or1k-desc.c: Regenerate.
1671 * or1k-desc.h: Regenerate.
1672 * or1k-dis.c: Regenerate.
1673 * or1k-ibld.c: Regenerate.
1674 * or1k-opc.c: Regenerate.
1675 * or1k-opc.h: Regenerate.
1676 * or1k-opinst.c: Regenerate.
1677
3b646889
AM		 16782020-05-11 Alan Modra <amodra@gmail.com>
1679
1680 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1681 xsmaxcqp, xsmincqp.
1682
9cc4ce88
AM		 16832020-05-11 Alan Modra <amodra@gmail.com>
1684
1685 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1686 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1687
5d57bc3f
AM		 16882020-05-11 Alan Modra <amodra@gmail.com>
1689
1690 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1691
66ef5847
AM		 16922020-05-11 Alan Modra <amodra@gmail.com>
1693
1694 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1695 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1696
4f3e9537
PB		 16972020-05-11 Peter Bergner <bergner@linux.ibm.com>
1698
1699 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1700 mnemonics.
1701
ec40e91c
AM		 17022020-05-11 Alan Modra <amodra@gmail.com>
1703
1704 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1705 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1706 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1707 (prefix_opcodes): Add xxeval.
1708
d7e97a76
AM		 17092020-05-11 Alan Modra <amodra@gmail.com>
1710
1711 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1712 xxgenpcvwm, xxgenpcvdm.
1713
fdefed7c
AM		 17142020-05-11 Alan Modra <amodra@gmail.com>
1715
1716 * ppc-opc.c (MP, VXVAM_MASK): Define.
1717 (VXVAPS_MASK): Use VXVA_MASK.
1718 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1719 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1720 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1721 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1722
aa3c112f
AM		 17232020-05-11 Alan Modra <amodra@gmail.com>
1724 Peter Bergner <bergner@linux.ibm.com>
1725
1726 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1727 New functions.
1728 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1729 YMSK2, XA6a, XA6ap, XB6a entries.
1730 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1731 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1732 (PPCVSX4): Define.
1733 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1734 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1735 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1736 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1737 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1738 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1739 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1740 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1741 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1742 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1743 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1744 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1745 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1746 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1747
6edbfd3b
AM		 17482020-05-11 Alan Modra <amodra@gmail.com>
1749
1750 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1751 (insert_xts, extract_xts): New functions.
1752 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1753 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1754 (VXRC_MASK, VXSH_MASK): Define.
1755 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1756 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1757 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1758 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1759 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1760 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1761 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1762
c7d7aea2
AM		 17632020-05-11 Alan Modra <amodra@gmail.com>
1764
1765 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1766 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1767 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1768 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1769 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1770
94ba9882
AM		 17712020-05-11 Alan Modra <amodra@gmail.com>
1772
1773 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1774 (XTP, DQXP, DQXP_MASK): Define.
1775 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1776 (prefix_opcodes): Add plxvp and pstxvp.
1777
f4791f1a
AM		 17782020-05-11 Alan Modra <amodra@gmail.com>
1779
1780 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1781 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1782 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1783
3ff0a5ba
PB		 17842020-05-11 Peter Bergner <bergner@linux.ibm.com>
1785
1786 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1787
afef4fe9
PB		 17882020-05-11 Peter Bergner <bergner@linux.ibm.com>
1789
1790 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1791 (L1OPT): Define.
1792 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1793
1224c05d
PB		 17942020-05-11 Peter Bergner <bergner@linux.ibm.com>
1795
1796 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1797
6bbb0c05
AM		 17982020-05-11 Alan Modra <amodra@gmail.com>
1799
1800 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1801
7c1f4227
AM		 18022020-05-11 Alan Modra <amodra@gmail.com>
1803
1804 * ppc-dis.c (ppc_opts): Add "power10" entry.
1805 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1806 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1807
73199c2b
NC		 18082020-05-11 Nick Clifton <nickc@redhat.com>
1809
1810 * po/fr.po: Updated French translation.
1811
09c1e68a
AC		 18122020-04-30 Alex Coplan <alex.coplan@arm.com>
1813
1814 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1815 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1816 (operand_general_constraint_met_p): validate
1817 AARCH64_OPND_UNDEFINED.
1818 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1819 for FLD_imm16_2.
1820 * aarch64-asm-2.c: Regenerated.
1821 * aarch64-dis-2.c: Regenerated.
1822 * aarch64-opc-2.c: Regenerated.
1823
9654d51a
NC		 18242020-04-29 Nick Clifton <nickc@redhat.com>
1825
1826 PR 22699
1827 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1828 and SETRC insns.
1829
c2e71e57
NC		 18302020-04-29 Nick Clifton <nickc@redhat.com>
1831
1832 * po/sv.po: Updated Swedish translation.
1833
5c936ef5
NC		 18342020-04-29 Nick Clifton <nickc@redhat.com>
1835
1836 PR 22699
1837 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1838 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1839 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1840 IMM0_8U case.
1841
bb2a1453
AS		 18422020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1843
1844 PR 25848
1845 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1846 cmpi only on m68020up and cpu32.
1847
c2e5c986
SD		 18482020-04-20 Sudakshina Das <sudi.das@arm.com>
1849
1850 * aarch64-asm.c (aarch64_ins_none): New.
1851 * aarch64-asm.h (ins_none): New declaration.
1852 * aarch64-dis.c (aarch64_ext_none): New.
1853 * aarch64-dis.h (ext_none): New declaration.
1854 * aarch64-opc.c (aarch64_print_operand): Update case for
1855 AARCH64_OPND_BARRIER_PSB.
1856 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1857 (AARCH64_OPERANDS): Update inserter/extracter for
1858 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1859 * aarch64-asm-2.c: Regenerated.
1860 * aarch64-dis-2.c: Regenerated.
1861 * aarch64-opc-2.c: Regenerated.
1862
8a6e1d1d
SD		 18632020-04-20 Sudakshina Das <sudi.das@arm.com>
1864
1865 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1866 (aarch64_feature_ras, RAS): Likewise.
1867 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1868 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1869 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1870 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1871 * aarch64-asm-2.c: Regenerated.
1872 * aarch64-dis-2.c: Regenerated.
1873 * aarch64-opc-2.c: Regenerated.
1874
e409955d
FS		 18752020-04-17 Fredrik Strupe <fredrik@strupe.net>
1876
1877 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1878 (print_insn_neon): Support disassembly of conditional
1879 instructions.
1880
c54a9b56
DF		 18812020-02-16 David Faust <david.faust@oracle.com>
1882
1883 * bpf-desc.c: Regenerate.
1884 * bpf-desc.h: Likewise.
1885 * bpf-opc.c: Regenerate.
1886 * bpf-opc.h: Likewise.
1887
bb651e8b
CL		 18882020-04-07 Lili Cui <lili.cui@intel.com>
1889
1890 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1891 (prefix_table): New instructions (see prefixes above).
1892 (rm_table): Likewise
1893 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1894 CPU_ANY_TSXLDTRK_FLAGS.
1895 (cpu_flags): Add CpuTSXLDTRK.
1896 * i386-opc.h (enum): Add CpuTSXLDTRK.
1897 (i386_cpu_flags): Add cputsxldtrk.
1898 * i386-opc.tbl: Add XSUSPLDTRK insns.
1899 * i386-init.h: Regenerate.
1900 * i386-tbl.h: Likewise.
1901
4b27d27c
L		 19022020-04-02 Lili Cui <lili.cui@intel.com>
1903
1904 * i386-dis.c (prefix_table): New instructions serialize.
1905 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1906 CPU_ANY_SERIALIZE_FLAGS.
1907 (cpu_flags): Add CpuSERIALIZE.
1908 * i386-opc.h (enum): Add CpuSERIALIZE.
1909 (i386_cpu_flags): Add cpuserialize.
1910 * i386-opc.tbl: Add SERIALIZE insns.
1911 * i386-init.h: Regenerate.
1912 * i386-tbl.h: Likewise.
1913
832a5807
AM		 19142020-03-26 Alan Modra <amodra@gmail.com>
1915
1916 * disassemble.h (opcodes_assert): Declare.
1917 (OPCODES_ASSERT): Define.
1918 * disassemble.c: Don't include assert.h. Include opintl.h.
1919 (opcodes_assert): New function.
1920 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1921 (bfd_h8_disassemble): Reduce size of data array. Correctly
1922 calculate maxlen. Omit insn decoding when insn length exceeds
1923 maxlen. Exit from nibble loop when looking for E, before
1924 accessing next data byte. Move processing of E outside loop.
1925 Replace tests of maxlen in loop with assertions.
1926
4c4addbe
AM		 19272020-03-26 Alan Modra <amodra@gmail.com>
1928
1929 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1930
a18cd0ca
AM		 19312020-03-25 Alan Modra <amodra@gmail.com>
1932
1933 * z80-dis.c (suffix): Init mybuf.
1934
57cb32b3
AM		 19352020-03-22 Alan Modra <amodra@gmail.com>
1936
1937 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1938 successflly read from section.
1939
beea5cc1
AM		 19402020-03-22 Alan Modra <amodra@gmail.com>
1941
1942 * arc-dis.c (find_format): Use ISO C string concatenation rather
1943 than line continuation within a string. Don't access needs_limm
1944 before testing opcode != NULL.
1945
03704c77
AM		 19462020-03-22 Alan Modra <amodra@gmail.com>
1947
1948 * ns32k-dis.c (print_insn_arg): Update comment.
1949 (print_insn_ns32k): Reduce size of index_offset array, and
1950 initialize, passing -1 to print_insn_arg for args that are not
1951 an index. Don't exit arg loop early. Abort on bad arg number.
1952
d1023b5d
AM		 19532020-03-22 Alan Modra <amodra@gmail.com>
1954
1955 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1956 * s12z-opc.c: Formatting.
1957 (operands_f): Return an int.
1958 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1959 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1960 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1961 (exg_sex_discrim): Likewise.
1962 (create_immediate_operand, create_bitfield_operand),
1963 (create_register_operand_with_size, create_register_all_operand),
1964 (create_register_all16_operand, create_simple_memory_operand),
1965 (create_memory_operand, create_memory_auto_operand): Don't
1966 segfault on malloc failure.
1967 (z_ext24_decode): Return an int status, negative on fail, zero
1968 on success.
1969 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1970 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1971 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1972 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1973 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1974 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1975 (loop_primitive_decode, shift_decode, psh_pul_decode),
1976 (bit_field_decode): Similarly.
1977 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1978 to return value, update callers.
1979 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1980 Don't segfault on NULL operand.
1981 (decode_operation): Return OP_INVALID on first fail.
1982 (decode_s12z): Check all reads, returning -1 on fail.
1983
340f3ac8
AM		 19842020-03-20 Alan Modra <amodra@gmail.com>
1985
1986 * metag-dis.c (print_insn_metag): Don't ignore status from
1987 read_memory_func.
1988
fe90ae8a
AM		 19892020-03-20 Alan Modra <amodra@gmail.com>
1990
1991 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1992 Initialize parts of buffer not written when handling a possible
1993 2-byte insn at end of section. Don't attempt decoding of such
1994 an insn by the 4-byte machinery.
1995
833d919c
AM		 19962020-03-20 Alan Modra <amodra@gmail.com>
1997
1998 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1999 partially filled buffer. Prevent lookup of 4-byte insns when
2000 only VLE 2-byte insns are possible due to section size. Print
2001 ".word" rather than ".long" for 2-byte leftovers.
2002
327ef784
NC		 20032020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2004
2005 PR 25641
2006 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2007
1673df32
JB		 20082020-03-13 Jan Beulich <jbeulich@suse.com>
2009
2010 * i386-dis.c (X86_64_0D): Rename to ...
2011 (X86_64_0E): ... this.
2012
384f3689
L		 20132020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2014
2015 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2016 * Makefile.in: Regenerated.
2017
865e2027
JB		 20182020-03-09 Jan Beulich <jbeulich@suse.com>
2019
2020 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2021 3-operand pseudos.
2022 * i386-tbl.h: Re-generate.
2023
2f13234b
JB		 20242020-03-09 Jan Beulich <jbeulich@suse.com>
2025
2026 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2027 vprot*, vpsha*, and vpshl*.
2028 * i386-tbl.h: Re-generate.
2029
3fabc179
JB		 20302020-03-09 Jan Beulich <jbeulich@suse.com>
2031
2032 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2033 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2034 * i386-tbl.h: Re-generate.
2035
3677e4c1
JB		 20362020-03-09 Jan Beulich <jbeulich@suse.com>
2037
2038 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2039 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2040 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2041 * i386-tbl.h: Re-generate.
2042
4c4898e8
JB		 20432020-03-09 Jan Beulich <jbeulich@suse.com>
2044
2045 * i386-gen.c (struct template_arg, struct template_instance,
2046 struct template_param, struct template, templates,
2047 parse_template, expand_templates): New.
2048 (process_i386_opcodes): Various local variables moved to
2049 expand_templates. Call parse_template and expand_templates.
2050 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2051 * i386-tbl.h: Re-generate.
2052
bc49bfd8
JB		 20532020-03-06 Jan Beulich <jbeulich@suse.com>
2054
2055 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2056 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2057 register and memory source templates. Replace VexW= by VexW*
2058 where applicable.
2059 * i386-tbl.h: Re-generate.
2060
4873e243
JB		 20612020-03-06 Jan Beulich <jbeulich@suse.com>
2062
2063 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2064 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2065 * i386-tbl.h: Re-generate.
2066
672a349b
JB		 20672020-03-06 Jan Beulich <jbeulich@suse.com>
2068
2069 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2070 * i386-tbl.h: Re-generate.
2071
4ed21b58
JB		 20722020-03-06 Jan Beulich <jbeulich@suse.com>
2073
2074 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2075 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2076 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2077 VexW0 on SSE2AVX variants.
2078 (vmovq): Drop NoRex64 from XMM/XMM variants.
2079 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2080 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2081 applicable use VexW0.
2082 * i386-tbl.h: Re-generate.
2083
643bb870
JB		 20842020-03-06 Jan Beulich <jbeulich@suse.com>
2085
2086 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2087 * i386-opc.h (Rex64): Delete.
2088 (struct i386_opcode_modifier): Remove rex64 field.
2089 * i386-opc.tbl (crc32): Drop Rex64.
2090 Replace Rex64 with Size64 everywhere else.
2091 * i386-tbl.h: Re-generate.
2092
a23b33b3
JB		 20932020-03-06 Jan Beulich <jbeulich@suse.com>
2094
2095 * i386-dis.c (OP_E_memory): Exclude recording of used address
2096 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2097 addressed memory operands for MPX insns.
2098
a0497384
JB		 20992020-03-06 Jan Beulich <jbeulich@suse.com>
2100
2101 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2102 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2103 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2104 (ptwrite): Split into non-64-bit and 64-bit forms.
2105 * i386-tbl.h: Re-generate.
2106
b630c145
JB		 21072020-03-06 Jan Beulich <jbeulich@suse.com>
2108
2109 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2110 template.
2111 * i386-tbl.h: Re-generate.
2112
a847e322
JB		 21132020-03-04 Jan Beulich <jbeulich@suse.com>
2114
2115 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2116 (prefix_table): Move vmmcall here. Add vmgexit.
2117 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2118 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2119 (cpu_flags): Add CpuSEV_ES entry.
2120 * i386-opc.h (CpuSEV_ES): New.
2121 (union i386_cpu_flags): Add cpusev_es field.
2122 * i386-opc.tbl (vmgexit): New.
2123 * i386-init.h, i386-tbl.h: Re-generate.
2124
3cd7f3e3
L		 21252020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2126
2127 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2128 with MnemonicSize.
2129 * i386-opc.h (IGNORESIZE): New.
2130 (DEFAULTSIZE): Likewise.
2131 (IgnoreSize): Removed.
2132 (DefaultSize): Likewise.
2133 (MnemonicSize): New.
2134 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2135 mnemonicsize.
2136 * i386-opc.tbl (IgnoreSize): New.
2137 (DefaultSize): Likewise.
2138 * i386-tbl.h: Regenerated.
2139
b8ba1385
SB		 21402020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2141
2142 PR 25627
2143 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2144 instructions.
2145
10d97a0f
L		 21462020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2147
2148 PR gas/25622
2149 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2150 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2151 * i386-tbl.h: Regenerated.
2152
dc1e8a47
AM		 21532020-02-26 Alan Modra <amodra@gmail.com>
2154
2155 * aarch64-asm.c: Indent labels correctly.
2156 * aarch64-dis.c: Likewise.
2157 * aarch64-gen.c: Likewise.
2158 * aarch64-opc.c: Likewise.
2159 * alpha-dis.c: Likewise.
2160 * i386-dis.c: Likewise.
2161 * nds32-asm.c: Likewise.
2162 * nfp-dis.c: Likewise.
2163 * visium-dis.c: Likewise.
2164
265b4673
CZ		 21652020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2166
2167 * arc-regs.h (int_vector_base): Make it available for all ARC
2168 CPUs.
2169
bd0cf5a6
NC		 21702020-02-20 Nelson Chu <nelson.chu@sifive.com>
2171
2172 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2173 changed.
2174
fa164239
JW		 21752020-02-19 Nelson Chu <nelson.chu@sifive.com>
2176
2177 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2178 c.mv/c.li if rs1 is zero.
2179
272a84b1
L		 21802020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2181
2182 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2183 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2184 CPU_POPCNT_FLAGS.
2185 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2186 * i386-opc.h (CpuABM): Removed.
2187 (CpuPOPCNT): New.
2188 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2189 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2190 popcnt. Remove CpuABM from lzcnt.
2191 * i386-init.h: Regenerated.
2192 * i386-tbl.h: Likewise.
2193
1f730c46
JB		 21942020-02-17 Jan Beulich <jbeulich@suse.com>
2195
2196 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2197 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2198 VexW1 instead of open-coding them.
2199 * i386-tbl.h: Re-generate.
2200
c8f8eebc
JB		 22012020-02-17 Jan Beulich <jbeulich@suse.com>
2202
2203 * i386-opc.tbl (AddrPrefixOpReg): Define.
2204 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2205 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2206 templates. Drop NoRex64.
2207 * i386-tbl.h: Re-generate.
2208
b9915cbc
JB		 22092020-02-17 Jan Beulich <jbeulich@suse.com>
2210
2211 PR gas/6518
2212 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2213 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2214 into Intel syntax instance (with Unpsecified) and AT&T one
2215 (without).
2216 (vcvtneps2bf16): Likewise, along with folding the two so far
2217 separate ones.
2218 * i386-tbl.h: Re-generate.
2219
ce504911
L		 22202020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2221
2222 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2223 CPU_ANY_SSE4A_FLAGS.
2224
dabec65d
AM		 22252020-02-17 Alan Modra <amodra@gmail.com>
2226
2227 * i386-gen.c (cpu_flag_init): Correct last change.
2228
af5c13b0
L		 22292020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2230
2231 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2232 CPU_ANY_SSE4_FLAGS.
2233
6867aac0
L		 22342020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2235
2236 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2237 (movzx): Likewise.
2238
65fca059
JB		 22392020-02-14 Jan Beulich <jbeulich@suse.com>
2240
2241 PR gas/25438
2242 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2243 destination for Cpu64-only variant.
2244 (movzx): Fold patterns.
2245 * i386-tbl.h: Re-generate.
2246
7deea9aa
JB		 22472020-02-13 Jan Beulich <jbeulich@suse.com>
2248
2249 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2250 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2251 CPU_ANY_SSE4_FLAGS entry.
2252 * i386-init.h: Re-generate.
2253
6c0946d0
JB		 22542020-02-12 Jan Beulich <jbeulich@suse.com>
2255
2256 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2257 with Unspecified, making the present one AT&T syntax only.
2258 * i386-tbl.h: Re-generate.
2259
ddb56fe6
JB		 22602020-02-12 Jan Beulich <jbeulich@suse.com>
2261
2262 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2263 * i386-tbl.h: Re-generate.
2264
5990e377
JB		 22652020-02-12 Jan Beulich <jbeulich@suse.com>
2266
2267 PR gas/24546
2268 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2269 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2270 Amd64 and Intel64 templates.
2271 (call, jmp): Likewise for far indirect variants. Dro
2272 Unspecified.
2273 * i386-tbl.h: Re-generate.
2274
50128d0c
JB		 22752020-02-11 Jan Beulich <jbeulich@suse.com>
2276
2277 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2278 * i386-opc.h (ShortForm): Delete.
2279 (struct i386_opcode_modifier): Remove shortform field.
2280 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2281 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2282 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2283 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2284 Drop ShortForm.
2285 * i386-tbl.h: Re-generate.
2286
1e05b5c4
JB		 22872020-02-11 Jan Beulich <jbeulich@suse.com>
2288
2289 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2290 fucompi): Drop ShortForm from operand-less templates.
2291 * i386-tbl.h: Re-generate.
2292
2f5dd314
AM		 22932020-02-11 Alan Modra <amodra@gmail.com>
2294
2295 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2296 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2297 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2298 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2299 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2300
5aae9ae9
MM		 23012020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2302
2303 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2304 (cde_opcodes): Add VCX* instructions.
2305
4934a27c
MM		 23062020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2307 Matthew Malcomson <matthew.malcomson@arm.com>
2308
2309 * arm-dis.c (struct cdeopcode32): New.
2310 (CDE_OPCODE): New macro.
2311 (cde_opcodes): New disassembly table.
2312 (regnames): New option to table.
2313 (cde_coprocs): New global variable.
2314 (print_insn_cde): New
2315 (print_insn_thumb32): Use print_insn_cde.
2316 (parse_arm_disassembler_options): Parse coprocN args.
2317
4b5aaf5f
L		 23182020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2319
2320 PR gas/25516
2321 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2322 with ISA64.
2323 * i386-opc.h (AMD64): Removed.
2324 (Intel64): Likewose.
2325 (AMD64): New.
2326 (INTEL64): Likewise.
2327 (INTEL64ONLY): Likewise.
2328 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2329 * i386-opc.tbl (Amd64): New.
2330 (Intel64): Likewise.
2331 (Intel64Only): Likewise.
2332 Replace AMD64 with Amd64. Update sysenter/sysenter with
2333 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2334 * i386-tbl.h: Regenerated.
2335
9fc0b501
SB		 23362020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2337
2338 PR 25469
2339 * z80-dis.c: Add support for GBZ80 opcodes.
2340
c5d7be0c
AM		 23412020-02-04 Alan Modra <amodra@gmail.com>
2342
2343 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2344
44e4546f
AM		 23452020-02-03 Alan Modra <amodra@gmail.com>
2346
2347 * m32c-ibld.c: Regenerate.
2348
b2b1453a
AM		 23492020-02-01 Alan Modra <amodra@gmail.com>
2350
2351 * frv-ibld.c: Regenerate.
2352
4102be5c
JB		 23532020-01-31 Jan Beulich <jbeulich@suse.com>
2354
2355 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2356 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2357 (OP_E_memory): Replace xmm_mdq_mode case label by
2358 vex_scalar_w_dq_mode one.
2359 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2360
825bd36c
JB		 23612020-01-31 Jan Beulich <jbeulich@suse.com>
2362
2363 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2364 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2365 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2366 (intel_operand_size): Drop vex_w_dq_mode case label.
2367
c3036ed0
RS		 23682020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2369
2370 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2371 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2372
0c115f84
AM		 23732020-01-30 Alan Modra <amodra@gmail.com>
2374
2375 * m32c-ibld.c: Regenerate.
2376
bd434cc4
JM		 23772020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2378
2379 * bpf-opc.c: Regenerate.
2380
aeab2b26
JB		 23812020-01-30 Jan Beulich <jbeulich@suse.com>
2382
2383 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2384 (dis386): Use them to replace C2/C3 table entries.
2385 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2386 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2387 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2388 * i386-tbl.h: Re-generate.
2389
62b3f548
JB		 23902020-01-30 Jan Beulich <jbeulich@suse.com>
2391
2392 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2393 forms.
2394 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2395 DefaultSize.
2396 * i386-tbl.h: Re-generate.
2397
1bd8ae10
AM		 23982020-01-30 Alan Modra <amodra@gmail.com>
2399
2400 * tic4x-dis.c (tic4x_dp): Make unsigned.
2401
bc31405e
L		 24022020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2403 Jan Beulich <jbeulich@suse.com>
2404
2405 PR binutils/25445
2406 * i386-dis.c (MOVSXD_Fixup): New function.
2407 (movsxd_mode): New enum.
2408 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2409 (intel_operand_size): Handle movsxd_mode.
2410 (OP_E_register): Likewise.
2411 (OP_G): Likewise.
2412 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2413 register on movsxd. Add movsxd with 16-bit destination register
2414 for AMD64 and Intel64 ISAs.
2415 * i386-tbl.h: Regenerated.
2416
7568c93b
TC		 24172020-01-27 Tamar Christina <tamar.christina@arm.com>
2418
2419 PR 25403
2420 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2421 * aarch64-asm-2.c: Regenerate
2422 * aarch64-dis-2.c: Likewise.
2423 * aarch64-opc-2.c: Likewise.
2424
c006a730
JB		 24252020-01-21 Jan Beulich <jbeulich@suse.com>
2426
2427 * i386-opc.tbl (sysret): Drop DefaultSize.
2428 * i386-tbl.h: Re-generate.
2429
c906a69a
JB		 24302020-01-21 Jan Beulich <jbeulich@suse.com>
2431
2432 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2433 Dword.
2434 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2435 * i386-tbl.h: Re-generate.
2436
26916852
NC		 24372020-01-20 Nick Clifton <nickc@redhat.com>
2438
2439 * po/de.po: Updated German translation.
2440 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2441 * po/uk.po: Updated Ukranian translation.
2442
4d6cbb64
AM		 24432020-01-20 Alan Modra <amodra@gmail.com>
2444
2445 * hppa-dis.c (fput_const): Remove useless cast.
2446
2bddb71a
AM		 24472020-01-20 Alan Modra <amodra@gmail.com>
2448
2449 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2450
1b1bb2c6
NC		 24512020-01-18 Nick Clifton <nickc@redhat.com>
2452
2453 * configure: Regenerate.
2454 * po/opcodes.pot: Regenerate.
2455
ae774686
NC		 24562020-01-18 Nick Clifton <nickc@redhat.com>
2457
2458 Binutils 2.34 branch created.
2459
07f1f3aa
CB		 24602020-01-17 Christian Biesinger <cbiesinger@google.com>
2461
2462 * opintl.h: Fix spelling error (seperate).
2463
42e04b36
L		 24642020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2465
2466 * i386-opc.tbl: Add {vex} pseudo prefix.
2467 * i386-tbl.h: Regenerated.
2468
2da2eaf4
AV		 24692020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2470
2471 PR 25376
2472 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2473 (neon_opcodes): Likewise.
2474 (select_arm_features): Make sure we enable MVE bits when selecting
2475 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2476 any architecture.
2477
d0849eed
JB		 24782020-01-16 Jan Beulich <jbeulich@suse.com>
2479
2480 * i386-opc.tbl: Drop stale comment from XOP section.
2481
9cf70a44
JB		 24822020-01-16 Jan Beulich <jbeulich@suse.com>
2483
2484 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2485 (extractps): Add VexWIG to SSE2AVX forms.
2486 * i386-tbl.h: Re-generate.
2487
4814632e
JB		 24882020-01-16 Jan Beulich <jbeulich@suse.com>
2489
2490 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2491 Size64 from and use VexW1 on SSE2AVX forms.
2492 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2493 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2494 * i386-tbl.h: Re-generate.
2495
aad09917
AM		 24962020-01-15 Alan Modra <amodra@gmail.com>
2497
2498 * tic4x-dis.c (tic4x_version): Make unsigned long.
2499 (optab, optab_special, registernames): New file scope vars.
2500 (tic4x_print_register): Set up registernames rather than
2501 malloc'd registertable.
2502 (tic4x_disassemble): Delete optable and optable_special. Use
2503 optab and optab_special instead. Throw away old optab,
2504 optab_special and registernames when info->mach changes.
2505
7a6bf3be
SB		 25062020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2507
2508 PR 25377
2509 * z80-dis.c (suffix): Use .db instruction to generate double
2510 prefix.
2511
ca1eaac0
AM		 25122020-01-14 Alan Modra <amodra@gmail.com>
2513
2514 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2515 values to unsigned before shifting.
2516
1d67fe3b
TT		 25172020-01-13 Thomas Troeger <tstroege@gmx.de>
2518
2519 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2520 flow instructions.
2521 (print_insn_thumb16, print_insn_thumb32): Likewise.
2522 (print_insn): Initialize the insn info.
2523 * i386-dis.c (print_insn): Initialize the insn info fields, and
2524 detect jumps.
2525
5e4f7e05
CZ		 25262012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2527
2528 * arc-opc.c (C_NE): Make it required.
2529
b9fe6b8a
CZ		 25302012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2531
2532 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2533 reserved register name.
2534
90dee485
AM		 25352020-01-13 Alan Modra <amodra@gmail.com>
2536
2537 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2538 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2539
febda64f
AM		 25402020-01-13 Alan Modra <amodra@gmail.com>
2541
2542 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2543 result of wasm_read_leb128 in a uint64_t and check that bits
2544 are not lost when copying to other locals. Use uint32_t for
2545 most locals. Use PRId64 when printing int64_t.
2546
df08b588
AM		 25472020-01-13 Alan Modra <amodra@gmail.com>
2548
2549 * score-dis.c: Formatting.
2550 * score7-dis.c: Formatting.
2551
b2c759ce
AM		 25522020-01-13 Alan Modra <amodra@gmail.com>
2553
2554 * score-dis.c (print_insn_score48): Use unsigned variables for
2555 unsigned values. Don't left shift negative values.
2556 (print_insn_score32): Likewise.
2557 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2558
5496abe1
AM		 25592020-01-13 Alan Modra <amodra@gmail.com>
2560
2561 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2562
202e762b
AM		 25632020-01-13 Alan Modra <amodra@gmail.com>
2564
2565 * fr30-ibld.c: Regenerate.
2566
7ef412cf
AM		 25672020-01-13 Alan Modra <amodra@gmail.com>
2568
2569 * xgate-dis.c (print_insn): Don't left shift signed value.
2570 (ripBits): Formatting, use 1u.
2571
7f578b95
AM		 25722020-01-10 Alan Modra <amodra@gmail.com>
2573
2574 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2575 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2576
441af85b
AM		 25772020-01-10 Alan Modra <amodra@gmail.com>
2578
2579 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2580 and XRREG value earlier to avoid a shift with negative exponent.
2581 * m10200-dis.c (disassemble): Similarly.
2582
bce58db4
NC		 25832020-01-09 Nick Clifton <nickc@redhat.com>
2584
2585 PR 25224
2586 * z80-dis.c (ld_ii_ii): Use correct cast.
2587
40c75bc8
SB		 25882020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2589
2590 PR 25224
2591 * z80-dis.c (ld_ii_ii): Use character constant when checking
2592 opcode byte value.
2593
d835a58b
JB		 25942020-01-09 Jan Beulich <jbeulich@suse.com>
2595
2596 * i386-dis.c (SEP_Fixup): New.
2597 (SEP): Define.
2598 (dis386_twobyte): Use it for sysenter/sysexit.
2599 (enum x86_64_isa): Change amd64 enumerator to value 1.
2600 (OP_J): Compare isa64 against intel64 instead of amd64.
2601 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2602 forms.
2603 * i386-tbl.h: Re-generate.
2604
030a2e78
AM		 26052020-01-08 Alan Modra <amodra@gmail.com>
2606
2607 * z8k-dis.c: Include libiberty.h
2608 (instr_data_s): Make max_fetched unsigned.
2609 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2610 Don't exceed byte_info bounds.
2611 (output_instr): Make num_bytes unsigned.
2612 (unpack_instr): Likewise for nibl_count and loop.
2613 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2614 idx unsigned.
2615 * z8k-opc.h: Regenerate.
2616
bb82aefe
SV		 26172020-01-07 Shahab Vahedi <shahab@synopsys.com>
2618
2619 * arc-tbl.h (llock): Use 'LLOCK' as class.
2620 (llockd): Likewise.
2621 (scond): Use 'SCOND' as class.
2622 (scondd): Likewise.
2623 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2624 (scondd): Likewise.
2625
cc6aa1a6
AM		 26262020-01-06 Alan Modra <amodra@gmail.com>
2627
2628 * m32c-ibld.c: Regenerate.
2629
660e62b1
AM		 26302020-01-06 Alan Modra <amodra@gmail.com>
2631
2632 PR 25344
2633 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2634 Peek at next byte to prevent recursion on repeated prefix bytes.
2635 Ensure uninitialised "mybuf" is not accessed.
2636 (print_insn_z80): Don't zero n_fetch and n_used here,..
2637 (print_insn_z80_buf): ..do it here instead.
2638
c9ae58fe
AM		 26392020-01-04 Alan Modra <amodra@gmail.com>
2640
2641 * m32r-ibld.c: Regenerate.
2642
5f57d4ec
AM		 26432020-01-04 Alan Modra <amodra@gmail.com>
2644
2645 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2646
2c5c1196
AM		 26472020-01-04 Alan Modra <amodra@gmail.com>
2648
2649 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2650
2e98c6c5
AM		 26512020-01-04 Alan Modra <amodra@gmail.com>
2652
2653 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2654
567dfba2
JB		 26552020-01-03 Jan Beulich <jbeulich@suse.com>
2656
5437a02a
JB		 2657 * aarch64-tbl.h (aarch64_opcode_table): Use
2658 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2659
26602020-01-03 Jan Beulich <jbeulich@suse.com>
2661
2662 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2663 forms of SUDOT and USDOT.
2664
8c45011a
JB		 26652020-01-03 Jan Beulich <jbeulich@suse.com>
2666
5437a02a 2667 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2668 uzip{1,2}.
2669 * opcodes/aarch64-dis-2.c: Re-generate.
2670
f4950f76
JB		 26712020-01-03 Jan Beulich <jbeulich@suse.com>
2672
5437a02a 2673 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2674 FMMLA encoding.
2675 * opcodes/aarch64-dis-2.c: Re-generate.
2676
6655dba2
SB		 26772020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2678
2679 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2680
b14ce8bf
AM		 26812020-01-01 Alan Modra <amodra@gmail.com>
2682
2683 Update year range in copyright notice of all files.
2684
0b114740 2685For older changes see ChangeLog-2019
3499769a 2686\f
0b114740 2687Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2688
2689Copying and distribution of this file, with or without modification,
2690are permitted in any medium without royalty provided the copyright
2691notice and this notice are preserved.
2692
2693Local Variables:
2694mode: change-log
2695left-margin: 8
2696fill-column: 74
2697version-control: never
2698End:
A mirror of the official binutils-gdb repository