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x86-64: fix {,V}PCMPESTR{I,M} disassembly in Intel mode
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b24d668c
JB		 12020-07-14 Jan Beulich <jbeulich@suse.com>
2
3 * i386-dis.c (PCMPESTR_Fixup): Delete.
4 (dis386): Adjust "LQ" description.
5 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
6 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
7 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
8 vpcmpestrm, and vpcmpestri.
9 (putop): Honor "cond" when handling LQ.
10 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
11 vcvtsi2ss and vcvtusi2ss.
12 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
13 vcvtsi2sd and vcvtusi2sd.
14
c4de7606
JB		 152020-07-14 Jan Beulich <jbeulich@suse.com>
16
17 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
18 (simd_cmp_op): Add const.
19 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
20 (CMP_Fixup): Handle VEX case.
21 (prefix_table): Replace VCMP by CMP.
22 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
23
9ab00b61
JB		 242020-07-14 Jan Beulich <jbeulich@suse.com>
25
26 * i386-dis.c (MOVBE_Fixup): Delete.
27 (Mv): Define.
28 (prefix_table): Use Mv for movbe entries.
29
2875b28a
JB		 302020-07-14 Jan Beulich <jbeulich@suse.com>
31
32 * i386-dis.c (CRC32_Fixup): Delete.
33 (prefix_table): Use Eb/Ev for crc32 entries.
34
e184e611
JB		 352020-07-14 Jan Beulich <jbeulich@suse.com>
36
37 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
38 Conditionalize invocations of "USED_REX (0)".
39
e8b5d5f9
JB		 402020-07-14 Jan Beulich <jbeulich@suse.com>
41
42 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
43 CH, DH, BH, AX, DX): Delete.
44 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
45 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
46 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
47
260cd341
LC		 482020-07-10 Lili Cui <lili.cui@intel.com>
49
50 * i386-dis.c (TMM): New.
51 (EXtmm): Likewise.
52 (VexTmm): Likewise.
53 (MVexSIBMEM): Likewise.
54 (tmm_mode): Likewise.
55 (vex_sibmem_mode): Likewise.
56 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
57 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
58 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
59 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
60 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
61 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
62 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
63 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
64 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
65 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
66 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
67 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
68 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
69 (PREFIX_VEX_0F3849_X86_64): Likewise.
70 (PREFIX_VEX_0F384B_X86_64): Likewise.
71 (PREFIX_VEX_0F385C_X86_64): Likewise.
72 (PREFIX_VEX_0F385E_X86_64): Likewise.
73 (X86_64_VEX_0F3849): Likewise.
74 (X86_64_VEX_0F384B): Likewise.
75 (X86_64_VEX_0F385C): Likewise.
76 (X86_64_VEX_0F385E): Likewise.
77 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
78 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
79 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
80 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
81 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
82 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
83 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
84 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
85 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
86 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
87 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
88 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
89 (VEX_W_0F3849_X86_64_P_0): Likewise.
90 (VEX_W_0F3849_X86_64_P_2): Likewise.
91 (VEX_W_0F3849_X86_64_P_3): Likewise.
92 (VEX_W_0F384B_X86_64_P_1): Likewise.
93 (VEX_W_0F384B_X86_64_P_2): Likewise.
94 (VEX_W_0F384B_X86_64_P_3): Likewise.
95 (VEX_W_0F385C_X86_64_P_1): Likewise.
96 (VEX_W_0F385E_X86_64_P_0): Likewise.
97 (VEX_W_0F385E_X86_64_P_1): Likewise.
98 (VEX_W_0F385E_X86_64_P_2): Likewise.
99 (VEX_W_0F385E_X86_64_P_3): Likewise.
100 (names_tmm): Likewise.
101 (att_names_tmm): Likewise.
102 (intel_operand_size): Handle void_mode.
103 (OP_XMM): Handle tmm_mode.
104 (OP_EX): Likewise.
105 (OP_VEX): Likewise.
106 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
107 CpuAMX_BF16 and CpuAMX_TILE.
108 (operand_type_shorthands): Add RegTMM.
109 (operand_type_init): Likewise.
110 (operand_types): Add Tmmword.
111 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
112 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
113 * i386-opc.h (CpuAMX_INT8): New.
114 (CpuAMX_BF16): Likewise.
115 (CpuAMX_TILE): Likewise.
116 (SIBMEM): Likewise.
117 (Tmmword): Likewise.
118 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
119 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
120 (i386_operand_type): Add tmmword.
121 * i386-opc.tbl: Add AMX instructions.
122 * i386-reg.tbl: Add AMX registers.
123 * i386-init.h: Regenerated.
124 * i386-tbl.h: Likewise.
125
467bbef0
JB		 1262020-07-08 Jan Beulich <jbeulich@suse.com>
127
128 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
129 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
130 Rename to ...
131 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
132 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
133 respectively.
134 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
135 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
136 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
137 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
138 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
139 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
140 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
141 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
142 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
143 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
144 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
145 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
146 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
147 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
148 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
149 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
150 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
151 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
152 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
153 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
154 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
155 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
156 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
157 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
158 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
159 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
160 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
161 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
162 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
163 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
164 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
165 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
166 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
167 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
168 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
169 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
170 (reg_table): Re-order XOP entries. Adjust their operands.
171 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
172 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
173 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
174 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
175 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
176 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
177 entries by references ...
178 (vex_len_table): ... to resepctive new entries here. For several
179 new and existing entries reference ...
180 (vex_w_table): ... new entries here.
181 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
182
6384fd9e
JB		 1832020-07-08 Jan Beulich <jbeulich@suse.com>
184
185 * i386-dis.c (XMVexScalarI4): Define.
186 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
187 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
188 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
189 (vex_len_table): Move scalar FMA4 entries ...
190 (prefix_table): ... here.
191 (OP_REG_VexI4): Handle scalar_mode.
192 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
193 * i386-tbl.h: Re-generate.
194
e6123d0c
JB		 1952020-07-08 Jan Beulich <jbeulich@suse.com>
196
197 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
198 Vex_2src_2): Delete.
199 (OP_VexW, VexW): New.
200 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
201 for shifts and rotates by register.
202
93abb146
JB		 2032020-07-08 Jan Beulich <jbeulich@suse.com>
204
205 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
206 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
207 OP_EX_VexReg): Delete.
208 (OP_VexI4, VexI4): New.
209 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
210 (prefix_table): ... here.
211 (print_insn): Drop setting of vex_w_done.
212
b13b1bc0
JB		 2132020-07-08 Jan Beulich <jbeulich@suse.com>
214
215 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
216 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
217 (xop_table): Replace operands of 4-operand insns.
218 (OP_REG_VexI4): Move VEX.W based operand swaping here.
219
f337259f
CZ		 2202020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
221
222 * arc-opc.c (insert_rbd): New function.
223 (RBD): Define.
224 (RBDdup): Likewise.
225 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
226 instructions.
227
931452b6
JB		 2282020-07-07 Jan Beulich <jbeulich@suse.com>
229
230 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
231 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
232 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
233 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
234 Delete.
235 (putop): Handle "BW".
236 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
237 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
238 and 0F3A3F ...
239 * i386-dis-evex-prefix.h: ... here.
240
b5b098c2
JB		 2412020-07-06 Jan Beulich <jbeulich@suse.com>
242
243 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
244 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
245 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
246 VEX_W_0FXOP_09_83): New enumerators.
247 (xop_table): Reference the above.
248 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
249 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
250 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
251 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
252
21a3faeb
JB		 2532020-07-06 Jan Beulich <jbeulich@suse.com>
254
255 * i386-dis.c (EVEX_W_0F3838_P_1,
256 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
257 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
258 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
259 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
260 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
261 (putop): Centralize management of last[]. Delete SAVE_LAST.
262 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
263 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
264 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
265 * i386-dis-evex-prefix.h: here.
266
bc152a17
JB		 2672020-07-06 Jan Beulich <jbeulich@suse.com>
268
269 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
270 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
271 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
272 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
273 enumerators.
274 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
275 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
276 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
277 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
278 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
279 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
280 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
281 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
282 these, respectively.
283 * i386-dis-evex-len.h: Adjust comments.
284 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
285 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
286 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
287 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
288 MOD_EVEX_0F385B_P_2_W_1 table entries.
289 * i386-dis-evex-w.h: Reference mod_table[] for
290 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
291 EVEX_W_0F385B_P_2.
292
c82a99a0
JB		 2932020-07-06 Jan Beulich <jbeulich@suse.com>
294
295 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
296 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
297 EXymm.
298 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
299 Likewise. Mark 256-bit entries invalid.
300
fedfb81e
JB		 3012020-07-06 Jan Beulich <jbeulich@suse.com>
302
303 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
304 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
305 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
306 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
307 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
308 PREFIX_EVEX_0F382B): Delete.
309 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
310 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
311 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
312 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
313 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
314 to ...
315 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
316 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
317 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
318 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
319 respectively.
320 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
321 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
322 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
323 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
324 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
325 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
326 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
327 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
328 PREFIX_EVEX_0F382B): Remove table entries.
329 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
330 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
331 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
332
3a57774c
JB		 3332020-07-06 Jan Beulich <jbeulich@suse.com>
334
335 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
336 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
337 enumerators.
338 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
339 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
340 EVEX_LEN_0F3A01_P_2_W_1 table entries.
341 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
342 entries.
343
e74d9fa9
JB		 3442020-07-06 Jan Beulich <jbeulich@suse.com>
345
346 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
347 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
348 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
349 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
350 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
351 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
352 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
353 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
354 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
355 entries.
356
6431c801
JB		 3572020-07-06 Jan Beulich <jbeulich@suse.com>
358
359 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
360 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
361 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
362 respectively.
363 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
364 entries.
365 * i386-dis-evex.h (evex_table): Reference VEX table entry for
366 opcode 0F3A1D.
367 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
368 entry.
369 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
370
6df22cf6
JB		 3712020-07-06 Jan Beulich <jbeulich@suse.com>
372
373 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
374 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
375 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
376 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
377 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
378 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
379 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
380 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
381 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
382 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
383 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
384 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
385 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
386 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
387 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
388 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
389 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
390 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
391 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
392 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
393 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
394 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
395 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
396 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
397 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
398 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
399 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
400 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
401 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
402 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
403 (prefix_table): Add EXxEVexR to FMA table entries.
404 (OP_Rounding): Move abort() invocation.
405 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
406 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
407 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
408 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
409 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
410 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
411 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
412 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
413 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
414 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
415 0F3ACE, 0F3ACF.
416 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
417 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
418 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
419 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
420 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
421 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
422 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
423 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
424 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
425 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
426 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
427 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
428 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
429 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
430 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
431 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
432 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
433 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
434 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
435 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
436 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
437 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
438 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
439 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
440 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
441 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
442 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
443 Delete table entries.
444 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
445 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
446 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
447 Likewise.
448
39e0f456
JB		 4492020-07-06 Jan Beulich <jbeulich@suse.com>
450
451 * i386-dis.c (EXqScalarS): Delete.
452 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
453 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
454
5b872f7d
JB		 4552020-07-06 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (safe-ctype.h): Include.
458 (EXdScalar, EXqScalar): Delete.
459 (d_scalar_mode, q_scalar_mode): Delete.
460 (prefix_table, vex_len_table): Use EXxmm_md in place of
461 EXdScalar and EXxmm_mq in place of EXqScalar.
462 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
463 d_scalar_mode and q_scalar_mode.
464 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
465 (vmovsd): Use EXxmm_mq.
466
ddc73fa9
NC		 4672020-07-06 Yuri Chornoivan <yurchor@ukr.net>
468
469 PR 26204
470 * arc-dis.c: Fix spelling mistake.
471 * po/opcodes.pot: Regenerate.
472
17550be7
NC		 4732020-07-06 Nick Clifton <nickc@redhat.com>
474
475 * po/pt_BR.po: Updated Brazilian Portugugese translation.
476 * po/uk.po: Updated Ukranian translation.
477
b19d852d
NC		 4782020-07-04 Nick Clifton <nickc@redhat.com>
479
480 * configure: Regenerate.
481 * po/opcodes.pot: Regenerate.
482
b115b9fd
NC		 4832020-07-04 Nick Clifton <nickc@redhat.com>
484
485 Binutils 2.35 branch created.
486
c2ecccb3
L		 4872020-07-02 H.J. Lu <hongjiu.lu@intel.com>
488
489 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
490 * i386-opc.h (VexSwapSources): New.
491 (i386_opcode_modifier): Add vexswapsources.
492 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
493 with two source operands swapped.
494 * i386-tbl.h: Regenerated.
495
08ccfccf
NC		 4962020-06-30 Nelson Chu <nelson.chu@sifive.com>
497
498 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
499 unprivileged CSR can also be initialized.
500
279edac5
AM		 5012020-06-29 Alan Modra <amodra@gmail.com>
502
503 * arm-dis.c: Use C style comments.
504 * cr16-opc.c: Likewise.
505 * ft32-dis.c: Likewise.
506 * moxie-opc.c: Likewise.
507 * tic54x-dis.c: Likewise.
508 * s12z-opc.c: Remove useless comment.
509 * xgate-dis.c: Likewise.
510
e978ad62
L		 5112020-06-26 H.J. Lu <hongjiu.lu@intel.com>
512
513 * i386-opc.tbl: Add a blank line.
514
63112cd6
L		 5152020-06-26 H.J. Lu <hongjiu.lu@intel.com>
516
517 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
518 (VecSIB128): Renamed to ...
519 (VECSIB128): This.
520 (VecSIB256): Renamed to ...
521 (VECSIB256): This.
522 (VecSIB512): Renamed to ...
523 (VECSIB512): This.
524 (VecSIB): Renamed to ...
525 (SIB): This.
526 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 527 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 528 (VecSIB256): Likewise.
529 (VecSIB512): Likewise.
79b32e73 530 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 531 and VecSIB512, respectively.
532
d1c36125
JB		 5332020-06-26 Jan Beulich <jbeulich@suse.com>
534
535 * i386-dis.c: Adjust description of I macro.
536 (x86_64_table): Drop use of I.
537 (float_mem): Replace use of I.
538 (putop): Remove handling of I. Adjust setting/clearing of "alt".
539
2a1bb84c
JB		 5402020-06-26 Jan Beulich <jbeulich@suse.com>
541
542 * i386-dis.c: (print_insn): Avoid straight assignment to
543 priv.orig_sizeflag when processing -M sub-options.
544
8f570d62
JB		 5452020-06-25 Jan Beulich <jbeulich@suse.com>
546
547 * i386-dis.c: Adjust description of J macro.
548 (dis386, x86_64_table, mod_table): Replace J.
549 (putop): Remove handling of J.
550
464dc4af
JB		 5512020-06-25 Jan Beulich <jbeulich@suse.com>
552
553 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
554
589958d6
JB		 5552020-06-25 Jan Beulich <jbeulich@suse.com>
556
557 * i386-dis.c: Adjust description of "LQ" macro.
558 (dis386_twobyte): Use LQ for sysret.
559 (putop): Adjust handling of LQ.
560
39ff0b81
NC		 5612020-06-22 Nelson Chu <nelson.chu@sifive.com>
562
563 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
564 * riscv-dis.c: Include elfxx-riscv.h.
565
d27c357a
JB		 5662020-06-18 H.J. Lu <hongjiu.lu@intel.com>
567
568 * i386-dis.c (prefix_table): Revert the last vmgexit change.
569
6fde587f
CL		 5702020-06-17 Lili Cui <lili.cui@intel.com>
571
572 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
573
efe30057
L		 5742020-06-14 H.J. Lu <hongjiu.lu@intel.com>
575
576 PR gas/26115
577 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
578 * i386-opc.tbl: Likewise.
579 * i386-tbl.h: Regenerated.
580
d8af286f
NC		 5812020-06-12 Nelson Chu <nelson.chu@sifive.com>
582
583 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
584
14962256
AC		 5852020-06-11 Alex Coplan <alex.coplan@arm.com>
586
587 * aarch64-opc.c (SYSREG): New macro for describing system registers.
588 (SR_CORE): Likewise.
589 (SR_FEAT): Likewise.
590 (SR_RNG): Likewise.
591 (SR_V8_1): Likewise.
592 (SR_V8_2): Likewise.
593 (SR_V8_3): Likewise.
594 (SR_V8_4): Likewise.
595 (SR_PAN): Likewise.
596 (SR_RAS): Likewise.
597 (SR_SSBS): Likewise.
598 (SR_SVE): Likewise.
599 (SR_ID_PFR2): Likewise.
600 (SR_PROFILE): Likewise.
601 (SR_MEMTAG): Likewise.
602 (SR_SCXTNUM): Likewise.
603 (aarch64_sys_regs): Refactor to store feature information in the table.
604 (aarch64_sys_reg_supported_p): Collapse logic for system registers
605 that now describe their own features.
606 (aarch64_pstatefield_supported_p): Likewise.
607
f9630fa6
L		 6082020-06-09 H.J. Lu <hongjiu.lu@intel.com>
609
610 * i386-dis.c (prefix_table): Fix a typo in comments.
611
73239888
JB		 6122020-06-09 Jan Beulich <jbeulich@suse.com>
613
614 * i386-dis.c (rex_ignored): Delete.
615 (ckprefix): Drop rex_ignored initialization.
616 (get_valid_dis386): Drop setting of rex_ignored.
617 (print_insn): Drop checking of rex_ignored. Don't record data
618 size prefix as used with VEX-and-alike encodings.
619
18897deb
JB		 6202020-06-09 Jan Beulich <jbeulich@suse.com>
621
622 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
623 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
624 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
625 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
626 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
627 VEX_0F12, and VEX_0F16.
628 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
629 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
630 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
631 from movlps and movhlps. New MOD_0F12_PREFIX_2,
632 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
633 MOD_VEX_0F16_PREFIX_2 entries.
634
97e6786a
JB		 6352020-06-09 Jan Beulich <jbeulich@suse.com>
636
637 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
638 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
639 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
640 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
641 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
642 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
643 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
644 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
645 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
646 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
647 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
648 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
649 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
650 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
651 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
652 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
653 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
654 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
655 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
656 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
657 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
658 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
659 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
660 EVEX_W_0FC6_P_2): Delete.
661 (print_insn): Add EVEX.W vs embedded prefix consistency check
662 to prefix validation.
663 * i386-dis-evex.h (evex_table): Don't further descend for
664 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
665 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
666 and 0F2B.
667 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
668 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
669 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
670 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
671 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
672 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
673 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
674 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
675 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
676 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
677 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
678 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
679 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
680 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
681 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
682 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
683 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
684 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
685 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
686 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
687 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
688 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
689 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
690 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
691 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
692 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
693 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
694
bf926894
JB		 6952020-06-09 Jan Beulich <jbeulich@suse.com>
696
697 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
698 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
699 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
700 vmovmskpX.
701 (print_insn): Drop pointless check against bad_opcode. Split
702 prefix validation into legacy and VEX-and-alike parts.
703 (putop): Re-work 'X' macro handling.
704
a5aaedb9
JB		 7052020-06-09 Jan Beulich <jbeulich@suse.com>
706
707 * i386-dis.c (MOD_0F51): Rename to ...
708 (MOD_0F50): ... this.
709
26417f19
AC		 7102020-06-08 Alex Coplan <alex.coplan@arm.com>
711
712 * arm-dis.c (arm_opcodes): Add dfb.
713 (thumb32_opcodes): Add dfb.
714
8a6fb3f9
JB		 7152020-06-08 Jan Beulich <jbeulich@suse.com>
716
717 * i386-opc.h (reg_entry): Const-qualify reg_name field.
718
1424c35d
AM		 7192020-06-06 Alan Modra <amodra@gmail.com>
720
721 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
722
d3d1cc7b
AM		 7232020-06-05 Alan Modra <amodra@gmail.com>
724
725 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
726 size is large enough.
727
d8740be1
JM		 7282020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
729
730 * disassemble.c (disassemble_init_for_target): Set endian_code for
731 bpf targets.
732 * bpf-desc.c: Regenerate.
733 * bpf-opc.c: Likewise.
734 * bpf-dis.c: Likewise.
735
e9bffec9
JM		 7362020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
737
738 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
739 (cgen_put_insn_value): Likewise.
740 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
741 * cgen-dis.in (print_insn): Likewise.
742 * cgen-ibld.in (insert_1): Likewise.
743 (insert_1): Likewise.
744 (insert_insn_normal): Likewise.
745 (extract_1): Likewise.
746 * bpf-dis.c: Regenerate.
747 * bpf-ibld.c: Likewise.
748 * bpf-ibld.c: Likewise.
749 * cgen-dis.in: Likewise.
750 * cgen-ibld.in: Likewise.
751 * cgen-opc.c: Likewise.
752 * epiphany-dis.c: Likewise.
753 * epiphany-ibld.c: Likewise.
754 * fr30-dis.c: Likewise.
755 * fr30-ibld.c: Likewise.
756 * frv-dis.c: Likewise.
757 * frv-ibld.c: Likewise.
758 * ip2k-dis.c: Likewise.
759 * ip2k-ibld.c: Likewise.
760 * iq2000-dis.c: Likewise.
761 * iq2000-ibld.c: Likewise.
762 * lm32-dis.c: Likewise.
763 * lm32-ibld.c: Likewise.
764 * m32c-dis.c: Likewise.
765 * m32c-ibld.c: Likewise.
766 * m32r-dis.c: Likewise.
767 * m32r-ibld.c: Likewise.
768 * mep-dis.c: Likewise.
769 * mep-ibld.c: Likewise.
770 * mt-dis.c: Likewise.
771 * mt-ibld.c: Likewise.
772 * or1k-dis.c: Likewise.
773 * or1k-ibld.c: Likewise.
774 * xc16x-dis.c: Likewise.
775 * xc16x-ibld.c: Likewise.
776 * xstormy16-dis.c: Likewise.
777 * xstormy16-ibld.c: Likewise.
778
b3db6d07
JM		 7792020-06-04 Jose E. Marchesi <jemarch@gnu.org>
780
781 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
782 (print_insn_): Handle instruction endian.
783 * bpf-dis.c: Regenerate.
784 * bpf-desc.c: Regenerate.
785 * epiphany-dis.c: Likewise.
786 * epiphany-desc.c: Likewise.
787 * fr30-dis.c: Likewise.
788 * fr30-desc.c: Likewise.
789 * frv-dis.c: Likewise.
790 * frv-desc.c: Likewise.
791 * ip2k-dis.c: Likewise.
792 * ip2k-desc.c: Likewise.
793 * iq2000-dis.c: Likewise.
794 * iq2000-desc.c: Likewise.
795 * lm32-dis.c: Likewise.
796 * lm32-desc.c: Likewise.
797 * m32c-dis.c: Likewise.
798 * m32c-desc.c: Likewise.
799 * m32r-dis.c: Likewise.
800 * m32r-desc.c: Likewise.
801 * mep-dis.c: Likewise.
802 * mep-desc.c: Likewise.
803 * mt-dis.c: Likewise.
804 * mt-desc.c: Likewise.
805 * or1k-dis.c: Likewise.
806 * or1k-desc.c: Likewise.
807 * xc16x-dis.c: Likewise.
808 * xc16x-desc.c: Likewise.
809 * xstormy16-dis.c: Likewise.
810 * xstormy16-desc.c: Likewise.
811
4ee4189f
NC		 8122020-06-03 Nick Clifton <nickc@redhat.com>
813
814 * po/sr.po: Updated Serbian translation.
815
44730156
NC		 8162020-06-03 Nelson Chu <nelson.chu@sifive.com>
817
818 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
819 (riscv_get_priv_spec_class): Likewise.
820
3c3d0376
AM		 8212020-06-01 Alan Modra <amodra@gmail.com>
822
823 * bpf-desc.c: Regenerate.
824
78c1c354
JM		 8252020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
826 David Faust <david.faust@oracle.com>
827
828 * bpf-desc.c: Regenerate.
829 * bpf-opc.h: Likewise.
830 * bpf-opc.c: Likewise.
831 * bpf-dis.c: Likewise.
832
efcf5fb5
AM		 8332020-05-28 Alan Modra <amodra@gmail.com>
834
835 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
836 values.
837
ab382d64
AM		 8382020-05-28 Alan Modra <amodra@gmail.com>
839
840 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
841 immediates.
842 (print_insn_ns32k): Revert last change.
843
151f5de4
NC		 8442020-05-28 Nick Clifton <nickc@redhat.com>
845
846 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
847 static.
848
25e1eca8
SL		 8492020-05-26 Sandra Loosemore <sandra@codesourcery.com>
850
851 Fix extraction of signed constants in nios2 disassembler (again).
852
853 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
854 extractions of signed fields.
855
57b17940
SSF		 8562020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
857
858 * s390-opc.txt: Relocate vector load/store instructions with
859 additional alignment parameter and change architecture level
860 constraint from z14 to z13.
861
d96bf37b
AM		 8622020-05-21 Alan Modra <amodra@gmail.com>
863
864 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
865 * sparc-dis.c: Likewise.
866 * tic4x-dis.c: Likewise.
867 * xtensa-dis.c: Likewise.
868 * bpf-desc.c: Regenerate.
869 * epiphany-desc.c: Regenerate.
870 * fr30-desc.c: Regenerate.
871 * frv-desc.c: Regenerate.
872 * ip2k-desc.c: Regenerate.
873 * iq2000-desc.c: Regenerate.
874 * lm32-desc.c: Regenerate.
875 * m32c-desc.c: Regenerate.
876 * m32r-desc.c: Regenerate.
877 * mep-asm.c: Regenerate.
878 * mep-desc.c: Regenerate.
879 * mt-desc.c: Regenerate.
880 * or1k-desc.c: Regenerate.
881 * xc16x-desc.c: Regenerate.
882 * xstormy16-desc.c: Regenerate.
883
8f595e9b
NC		 8842020-05-20 Nelson Chu <nelson.chu@sifive.com>
885
886 * riscv-opc.c (riscv_ext_version_table): The table used to store
887 all information about the supported spec and the corresponding ISA
888 versions. Currently, only Zicsr is supported to verify the
889 correctness of Z sub extension settings. Others will be supported
890 in the future patches.
891 (struct isa_spec_t, isa_specs): List for all supported ISA spec
892 classes and the corresponding strings.
893 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
894 spec class by giving a ISA spec string.
895 * riscv-opc.c (struct priv_spec_t): New structure.
896 (struct priv_spec_t priv_specs): List for all supported privilege spec
897 classes and the corresponding strings.
898 (riscv_get_priv_spec_class): New function. Get the corresponding
899 privilege spec class by giving a spec string.
900 (riscv_get_priv_spec_name): New function. Get the corresponding
901 privilege spec string by giving a CSR version class.
902 * riscv-dis.c: Updated since DECLARE_CSR is changed.
903 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
904 according to the chosen version. Build a hash table riscv_csr_hash to
905 store the valid CSR for the chosen pirv verison. Dump the direct
906 CSR address rather than it's name if it is invalid.
907 (parse_riscv_dis_option_without_args): New function. Parse the options
908 without arguments.
909 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
910 parse the options without arguments first, and then handle the options
911 with arguments. Add the new option -Mpriv-spec, which has argument.
912 * riscv-dis.c (print_riscv_disassembler_options): Add description
913 about the new OBJDUMP option.
914
3d205eb4
PB		 9152020-05-19 Peter Bergner <bergner@linux.ibm.com>
916
917 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
918 WC values on POWER10 sync, dcbf and wait instructions.
919 (insert_pl, extract_pl): New functions.
920 (L2OPT, LS, WC): Use insert_ls and extract_ls.
921 (LS3): New , 3-bit L for sync.
922 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
923 (SC2, PL): New, 2-bit SC and PL for sync and wait.
924 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
925 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
926 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
927 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
928 <wait>: Enable PL operand on POWER10.
929 <dcbf>: Enable L3OPT operand on POWER10.
930 <sync>: Enable SC2 operand on POWER10.
931
a501eb44
SH		 9322020-05-19 Stafford Horne <shorne@gmail.com>
933
934 PR 25184
935 * or1k-asm.c: Regenerate.
936 * or1k-desc.c: Regenerate.
937 * or1k-desc.h: Regenerate.
938 * or1k-dis.c: Regenerate.
939 * or1k-ibld.c: Regenerate.
940 * or1k-opc.c: Regenerate.
941 * or1k-opc.h: Regenerate.
942 * or1k-opinst.c: Regenerate.
943
3b646889
AM		 9442020-05-11 Alan Modra <amodra@gmail.com>
945
946 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
947 xsmaxcqp, xsmincqp.
948
9cc4ce88
AM		 9492020-05-11 Alan Modra <amodra@gmail.com>
950
951 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
952 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
953
5d57bc3f
AM		 9542020-05-11 Alan Modra <amodra@gmail.com>
955
956 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
957
66ef5847
AM		 9582020-05-11 Alan Modra <amodra@gmail.com>
959
960 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
961 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
962
4f3e9537
PB		 9632020-05-11 Peter Bergner <bergner@linux.ibm.com>
964
965 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
966 mnemonics.
967
ec40e91c
AM		 9682020-05-11 Alan Modra <amodra@gmail.com>
969
970 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
971 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
972 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
973 (prefix_opcodes): Add xxeval.
974
d7e97a76
AM		 9752020-05-11 Alan Modra <amodra@gmail.com>
976
977 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
978 xxgenpcvwm, xxgenpcvdm.
979
fdefed7c
AM		 9802020-05-11 Alan Modra <amodra@gmail.com>
981
982 * ppc-opc.c (MP, VXVAM_MASK): Define.
983 (VXVAPS_MASK): Use VXVA_MASK.
984 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
985 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
986 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
987 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
988
aa3c112f
AM		 9892020-05-11 Alan Modra <amodra@gmail.com>
990 Peter Bergner <bergner@linux.ibm.com>
991
992 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
993 New functions.
994 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
995 YMSK2, XA6a, XA6ap, XB6a entries.
996 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
997 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
998 (PPCVSX4): Define.
999 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1000 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1001 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1002 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1003 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1004 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1005 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1006 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1007 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1008 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1009 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1010 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1011 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1012 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1013
6edbfd3b
AM		 10142020-05-11 Alan Modra <amodra@gmail.com>
1015
1016 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1017 (insert_xts, extract_xts): New functions.
1018 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1019 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1020 (VXRC_MASK, VXSH_MASK): Define.
1021 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1022 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1023 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1024 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1025 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1026 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1027 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1028
c7d7aea2
AM		 10292020-05-11 Alan Modra <amodra@gmail.com>
1030
1031 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1032 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1033 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1034 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1035 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1036
94ba9882
AM		 10372020-05-11 Alan Modra <amodra@gmail.com>
1038
1039 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1040 (XTP, DQXP, DQXP_MASK): Define.
1041 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1042 (prefix_opcodes): Add plxvp and pstxvp.
1043
f4791f1a
AM		 10442020-05-11 Alan Modra <amodra@gmail.com>
1045
1046 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1047 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1048 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1049
3ff0a5ba
PB		 10502020-05-11 Peter Bergner <bergner@linux.ibm.com>
1051
1052 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1053
afef4fe9
PB		 10542020-05-11 Peter Bergner <bergner@linux.ibm.com>
1055
1056 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1057 (L1OPT): Define.
1058 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1059
1224c05d
PB		 10602020-05-11 Peter Bergner <bergner@linux.ibm.com>
1061
1062 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1063
6bbb0c05
AM		 10642020-05-11 Alan Modra <amodra@gmail.com>
1065
1066 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1067
7c1f4227
AM		 10682020-05-11 Alan Modra <amodra@gmail.com>
1069
1070 * ppc-dis.c (ppc_opts): Add "power10" entry.
1071 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1072 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1073
73199c2b
NC		 10742020-05-11 Nick Clifton <nickc@redhat.com>
1075
1076 * po/fr.po: Updated French translation.
1077
09c1e68a
AC		 10782020-04-30 Alex Coplan <alex.coplan@arm.com>
1079
1080 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1081 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1082 (operand_general_constraint_met_p): validate
1083 AARCH64_OPND_UNDEFINED.
1084 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1085 for FLD_imm16_2.
1086 * aarch64-asm-2.c: Regenerated.
1087 * aarch64-dis-2.c: Regenerated.
1088 * aarch64-opc-2.c: Regenerated.
1089
9654d51a
NC		 10902020-04-29 Nick Clifton <nickc@redhat.com>
1091
1092 PR 22699
1093 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1094 and SETRC insns.
1095
c2e71e57
NC		 10962020-04-29 Nick Clifton <nickc@redhat.com>
1097
1098 * po/sv.po: Updated Swedish translation.
1099
5c936ef5
NC		 11002020-04-29 Nick Clifton <nickc@redhat.com>
1101
1102 PR 22699
1103 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1104 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1105 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1106 IMM0_8U case.
1107
bb2a1453
AS		 11082020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1109
1110 PR 25848
1111 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1112 cmpi only on m68020up and cpu32.
1113
c2e5c986
SD		 11142020-04-20 Sudakshina Das <sudi.das@arm.com>
1115
1116 * aarch64-asm.c (aarch64_ins_none): New.
1117 * aarch64-asm.h (ins_none): New declaration.
1118 * aarch64-dis.c (aarch64_ext_none): New.
1119 * aarch64-dis.h (ext_none): New declaration.
1120 * aarch64-opc.c (aarch64_print_operand): Update case for
1121 AARCH64_OPND_BARRIER_PSB.
1122 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1123 (AARCH64_OPERANDS): Update inserter/extracter for
1124 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1125 * aarch64-asm-2.c: Regenerated.
1126 * aarch64-dis-2.c: Regenerated.
1127 * aarch64-opc-2.c: Regenerated.
1128
8a6e1d1d
SD		 11292020-04-20 Sudakshina Das <sudi.das@arm.com>
1130
1131 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1132 (aarch64_feature_ras, RAS): Likewise.
1133 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1134 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1135 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1136 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1137 * aarch64-asm-2.c: Regenerated.
1138 * aarch64-dis-2.c: Regenerated.
1139 * aarch64-opc-2.c: Regenerated.
1140
e409955d
FS		 11412020-04-17 Fredrik Strupe <fredrik@strupe.net>
1142
1143 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1144 (print_insn_neon): Support disassembly of conditional
1145 instructions.
1146
c54a9b56
DF		 11472020-02-16 David Faust <david.faust@oracle.com>
1148
1149 * bpf-desc.c: Regenerate.
1150 * bpf-desc.h: Likewise.
1151 * bpf-opc.c: Regenerate.
1152 * bpf-opc.h: Likewise.
1153
bb651e8b
CL		 11542020-04-07 Lili Cui <lili.cui@intel.com>
1155
1156 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1157 (prefix_table): New instructions (see prefixes above).
1158 (rm_table): Likewise
1159 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1160 CPU_ANY_TSXLDTRK_FLAGS.
1161 (cpu_flags): Add CpuTSXLDTRK.
1162 * i386-opc.h (enum): Add CpuTSXLDTRK.
1163 (i386_cpu_flags): Add cputsxldtrk.
1164 * i386-opc.tbl: Add XSUSPLDTRK insns.
1165 * i386-init.h: Regenerate.
1166 * i386-tbl.h: Likewise.
1167
4b27d27c
L		 11682020-04-02 Lili Cui <lili.cui@intel.com>
1169
1170 * i386-dis.c (prefix_table): New instructions serialize.
1171 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1172 CPU_ANY_SERIALIZE_FLAGS.
1173 (cpu_flags): Add CpuSERIALIZE.
1174 * i386-opc.h (enum): Add CpuSERIALIZE.
1175 (i386_cpu_flags): Add cpuserialize.
1176 * i386-opc.tbl: Add SERIALIZE insns.
1177 * i386-init.h: Regenerate.
1178 * i386-tbl.h: Likewise.
1179
832a5807
AM		 11802020-03-26 Alan Modra <amodra@gmail.com>
1181
1182 * disassemble.h (opcodes_assert): Declare.
1183 (OPCODES_ASSERT): Define.
1184 * disassemble.c: Don't include assert.h. Include opintl.h.
1185 (opcodes_assert): New function.
1186 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1187 (bfd_h8_disassemble): Reduce size of data array. Correctly
1188 calculate maxlen. Omit insn decoding when insn length exceeds
1189 maxlen. Exit from nibble loop when looking for E, before
1190 accessing next data byte. Move processing of E outside loop.
1191 Replace tests of maxlen in loop with assertions.
1192
4c4addbe
AM		 11932020-03-26 Alan Modra <amodra@gmail.com>
1194
1195 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1196
a18cd0ca
AM		 11972020-03-25 Alan Modra <amodra@gmail.com>
1198
1199 * z80-dis.c (suffix): Init mybuf.
1200
57cb32b3
AM		 12012020-03-22 Alan Modra <amodra@gmail.com>
1202
1203 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1204 successflly read from section.
1205
beea5cc1
AM		 12062020-03-22 Alan Modra <amodra@gmail.com>
1207
1208 * arc-dis.c (find_format): Use ISO C string concatenation rather
1209 than line continuation within a string. Don't access needs_limm
1210 before testing opcode != NULL.
1211
03704c77
AM		 12122020-03-22 Alan Modra <amodra@gmail.com>
1213
1214 * ns32k-dis.c (print_insn_arg): Update comment.
1215 (print_insn_ns32k): Reduce size of index_offset array, and
1216 initialize, passing -1 to print_insn_arg for args that are not
1217 an index. Don't exit arg loop early. Abort on bad arg number.
1218
d1023b5d
AM		 12192020-03-22 Alan Modra <amodra@gmail.com>
1220
1221 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1222 * s12z-opc.c: Formatting.
1223 (operands_f): Return an int.
1224 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1225 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1226 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1227 (exg_sex_discrim): Likewise.
1228 (create_immediate_operand, create_bitfield_operand),
1229 (create_register_operand_with_size, create_register_all_operand),
1230 (create_register_all16_operand, create_simple_memory_operand),
1231 (create_memory_operand, create_memory_auto_operand): Don't
1232 segfault on malloc failure.
1233 (z_ext24_decode): Return an int status, negative on fail, zero
1234 on success.
1235 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1236 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1237 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1238 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1239 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1240 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1241 (loop_primitive_decode, shift_decode, psh_pul_decode),
1242 (bit_field_decode): Similarly.
1243 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1244 to return value, update callers.
1245 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1246 Don't segfault on NULL operand.
1247 (decode_operation): Return OP_INVALID on first fail.
1248 (decode_s12z): Check all reads, returning -1 on fail.
1249
340f3ac8
AM		 12502020-03-20 Alan Modra <amodra@gmail.com>
1251
1252 * metag-dis.c (print_insn_metag): Don't ignore status from
1253 read_memory_func.
1254
fe90ae8a
AM		 12552020-03-20 Alan Modra <amodra@gmail.com>
1256
1257 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1258 Initialize parts of buffer not written when handling a possible
1259 2-byte insn at end of section. Don't attempt decoding of such
1260 an insn by the 4-byte machinery.
1261
833d919c
AM		 12622020-03-20 Alan Modra <amodra@gmail.com>
1263
1264 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1265 partially filled buffer. Prevent lookup of 4-byte insns when
1266 only VLE 2-byte insns are possible due to section size. Print
1267 ".word" rather than ".long" for 2-byte leftovers.
1268
327ef784
NC		 12692020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1270
1271 PR 25641
1272 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1273
1673df32
JB		 12742020-03-13 Jan Beulich <jbeulich@suse.com>
1275
1276 * i386-dis.c (X86_64_0D): Rename to ...
1277 (X86_64_0E): ... this.
1278
384f3689
L		 12792020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1280
1281 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1282 * Makefile.in: Regenerated.
1283
865e2027
JB		 12842020-03-09 Jan Beulich <jbeulich@suse.com>
1285
1286 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1287 3-operand pseudos.
1288 * i386-tbl.h: Re-generate.
1289
2f13234b
JB		 12902020-03-09 Jan Beulich <jbeulich@suse.com>
1291
1292 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1293 vprot*, vpsha*, and vpshl*.
1294 * i386-tbl.h: Re-generate.
1295
3fabc179
JB		 12962020-03-09 Jan Beulich <jbeulich@suse.com>
1297
1298 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1299 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1300 * i386-tbl.h: Re-generate.
1301
3677e4c1
JB		 13022020-03-09 Jan Beulich <jbeulich@suse.com>
1303
1304 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1305 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1306 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1307 * i386-tbl.h: Re-generate.
1308
4c4898e8
JB		 13092020-03-09 Jan Beulich <jbeulich@suse.com>
1310
1311 * i386-gen.c (struct template_arg, struct template_instance,
1312 struct template_param, struct template, templates,
1313 parse_template, expand_templates): New.
1314 (process_i386_opcodes): Various local variables moved to
1315 expand_templates. Call parse_template and expand_templates.
1316 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1317 * i386-tbl.h: Re-generate.
1318
bc49bfd8
JB		 13192020-03-06 Jan Beulich <jbeulich@suse.com>
1320
1321 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1322 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1323 register and memory source templates. Replace VexW= by VexW*
1324 where applicable.
1325 * i386-tbl.h: Re-generate.
1326
4873e243
JB		 13272020-03-06 Jan Beulich <jbeulich@suse.com>
1328
1329 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1330 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1331 * i386-tbl.h: Re-generate.
1332
672a349b
JB		 13332020-03-06 Jan Beulich <jbeulich@suse.com>
1334
1335 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1336 * i386-tbl.h: Re-generate.
1337
4ed21b58
JB		 13382020-03-06 Jan Beulich <jbeulich@suse.com>
1339
1340 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1341 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1342 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1343 VexW0 on SSE2AVX variants.
1344 (vmovq): Drop NoRex64 from XMM/XMM variants.
1345 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1346 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1347 applicable use VexW0.
1348 * i386-tbl.h: Re-generate.
1349
643bb870
JB		 13502020-03-06 Jan Beulich <jbeulich@suse.com>
1351
1352 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1353 * i386-opc.h (Rex64): Delete.
1354 (struct i386_opcode_modifier): Remove rex64 field.
1355 * i386-opc.tbl (crc32): Drop Rex64.
1356 Replace Rex64 with Size64 everywhere else.
1357 * i386-tbl.h: Re-generate.
1358
a23b33b3
JB		 13592020-03-06 Jan Beulich <jbeulich@suse.com>
1360
1361 * i386-dis.c (OP_E_memory): Exclude recording of used address
1362 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1363 addressed memory operands for MPX insns.
1364
a0497384
JB		 13652020-03-06 Jan Beulich <jbeulich@suse.com>
1366
1367 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1368 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1369 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1370 (ptwrite): Split into non-64-bit and 64-bit forms.
1371 * i386-tbl.h: Re-generate.
1372
b630c145
JB		 13732020-03-06 Jan Beulich <jbeulich@suse.com>
1374
1375 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1376 template.
1377 * i386-tbl.h: Re-generate.
1378
a847e322
JB		 13792020-03-04 Jan Beulich <jbeulich@suse.com>
1380
1381 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
1382 (prefix_table): Move vmmcall here. Add vmgexit.
1383 (rm_table): Replace vmmcall entry by prefix_table[] escape.
1384 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
1385 (cpu_flags): Add CpuSEV_ES entry.
1386 * i386-opc.h (CpuSEV_ES): New.
1387 (union i386_cpu_flags): Add cpusev_es field.
1388 * i386-opc.tbl (vmgexit): New.
1389 * i386-init.h, i386-tbl.h: Re-generate.
1390
3cd7f3e3
L		 13912020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1392
1393 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
1394 with MnemonicSize.
1395 * i386-opc.h (IGNORESIZE): New.
1396 (DEFAULTSIZE): Likewise.
1397 (IgnoreSize): Removed.
1398 (DefaultSize): Likewise.
1399 (MnemonicSize): New.
1400 (i386_opcode_modifier): Replace ignoresize/defaultsize with
1401 mnemonicsize.
1402 * i386-opc.tbl (IgnoreSize): New.
1403 (DefaultSize): Likewise.
1404 * i386-tbl.h: Regenerated.
1405
b8ba1385
SB		 14062020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1407
1408 PR 25627
1409 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
1410 instructions.
1411
10d97a0f
L		 14122020-03-03 H.J. Lu <hongjiu.lu@intel.com>
1413
1414 PR gas/25622
1415 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
1416 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
1417 * i386-tbl.h: Regenerated.
1418
dc1e8a47
AM		 14192020-02-26 Alan Modra <amodra@gmail.com>
1420
1421 * aarch64-asm.c: Indent labels correctly.
1422 * aarch64-dis.c: Likewise.
1423 * aarch64-gen.c: Likewise.
1424 * aarch64-opc.c: Likewise.
1425 * alpha-dis.c: Likewise.
1426 * i386-dis.c: Likewise.
1427 * nds32-asm.c: Likewise.
1428 * nfp-dis.c: Likewise.
1429 * visium-dis.c: Likewise.
1430
265b4673
CZ		 14312020-02-25 Claudiu Zissulescu <claziss@gmail.com>
1432
1433 * arc-regs.h (int_vector_base): Make it available for all ARC
1434 CPUs.
1435
bd0cf5a6
NC		 14362020-02-20 Nelson Chu <nelson.chu@sifive.com>
1437
1438 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
1439 changed.
1440
fa164239
JW		 14412020-02-19 Nelson Chu <nelson.chu@sifive.com>
1442
1443 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
1444 c.mv/c.li if rs1 is zero.
1445
272a84b1
L		 14462020-02-17 H.J. Lu <hongjiu.lu@intel.com>
1447
1448 * i386-gen.c (cpu_flag_init): Replace CpuABM with
1449 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
1450 CPU_POPCNT_FLAGS.
1451 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
1452 * i386-opc.h (CpuABM): Removed.
1453 (CpuPOPCNT): New.
1454 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
1455 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
1456 popcnt. Remove CpuABM from lzcnt.
1457 * i386-init.h: Regenerated.
1458 * i386-tbl.h: Likewise.
1459
1f730c46
JB		 14602020-02-17 Jan Beulich <jbeulich@suse.com>
1461
1462 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
1463 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
1464 VexW1 instead of open-coding them.
1465 * i386-tbl.h: Re-generate.
1466
c8f8eebc
JB		 14672020-02-17 Jan Beulich <jbeulich@suse.com>
1468
1469 * i386-opc.tbl (AddrPrefixOpReg): Define.
1470 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
1471 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
1472 templates. Drop NoRex64.
1473 * i386-tbl.h: Re-generate.
1474
b9915cbc
JB		 14752020-02-17 Jan Beulich <jbeulich@suse.com>
1476
1477 PR gas/6518
1478 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
1479 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
1480 into Intel syntax instance (with Unpsecified) and AT&T one
1481 (without).
1482 (vcvtneps2bf16): Likewise, along with folding the two so far
1483 separate ones.
1484 * i386-tbl.h: Re-generate.
1485
ce504911
L		 14862020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1487
1488 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
1489 CPU_ANY_SSE4A_FLAGS.
1490
dabec65d
AM		 14912020-02-17 Alan Modra <amodra@gmail.com>
1492
1493 * i386-gen.c (cpu_flag_init): Correct last change.
1494
af5c13b0
L		 14952020-02-16 H.J. Lu <hongjiu.lu@intel.com>
1496
1497 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
1498 CPU_ANY_SSE4_FLAGS.
1499
6867aac0
L		 15002020-02-14 H.J. Lu <hongjiu.lu@intel.com>
1501
1502 * i386-opc.tbl (movsx): Remove Intel syntax comments.
1503 (movzx): Likewise.
1504
65fca059
JB		 15052020-02-14 Jan Beulich <jbeulich@suse.com>
1506
1507 PR gas/25438
1508 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
1509 destination for Cpu64-only variant.
1510 (movzx): Fold patterns.
1511 * i386-tbl.h: Re-generate.
1512
7deea9aa
JB		 15132020-02-13 Jan Beulich <jbeulich@suse.com>
1514
1515 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
1516 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
1517 CPU_ANY_SSE4_FLAGS entry.
1518 * i386-init.h: Re-generate.
1519
6c0946d0
JB		 15202020-02-12 Jan Beulich <jbeulich@suse.com>
1521
1522 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
1523 with Unspecified, making the present one AT&T syntax only.
1524 * i386-tbl.h: Re-generate.
1525
ddb56fe6
JB		 15262020-02-12 Jan Beulich <jbeulich@suse.com>
1527
1528 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
1529 * i386-tbl.h: Re-generate.
1530
5990e377
JB		 15312020-02-12 Jan Beulich <jbeulich@suse.com>
1532
1533 PR gas/24546
1534 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
1535 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
1536 Amd64 and Intel64 templates.
1537 (call, jmp): Likewise for far indirect variants. Dro
1538 Unspecified.
1539 * i386-tbl.h: Re-generate.
1540
50128d0c
JB		 15412020-02-11 Jan Beulich <jbeulich@suse.com>
1542
1543 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
1544 * i386-opc.h (ShortForm): Delete.
1545 (struct i386_opcode_modifier): Remove shortform field.
1546 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
1547 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
1548 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
1549 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
1550 Drop ShortForm.
1551 * i386-tbl.h: Re-generate.
1552
1e05b5c4
JB		 15532020-02-11 Jan Beulich <jbeulich@suse.com>
1554
1555 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
1556 fucompi): Drop ShortForm from operand-less templates.
1557 * i386-tbl.h: Re-generate.
1558
2f5dd314
AM		 15592020-02-11 Alan Modra <amodra@gmail.com>
1560
1561 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
1562 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
1563 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
1564 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
1565 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
1566
5aae9ae9
MM		 15672020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
1568
1569 * arm-dis.c (print_insn_cde): Define 'V' parse character.
1570 (cde_opcodes): Add VCX* instructions.
1571
4934a27c
MM		 15722020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
1573 Matthew Malcomson <matthew.malcomson@arm.com>
1574
1575 * arm-dis.c (struct cdeopcode32): New.
1576 (CDE_OPCODE): New macro.
1577 (cde_opcodes): New disassembly table.
1578 (regnames): New option to table.
1579 (cde_coprocs): New global variable.
1580 (print_insn_cde): New
1581 (print_insn_thumb32): Use print_insn_cde.
1582 (parse_arm_disassembler_options): Parse coprocN args.
1583
4b5aaf5f
L		 15842020-02-10 H.J. Lu <hongjiu.lu@intel.com>
1585
1586 PR gas/25516
1587 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
1588 with ISA64.
1589 * i386-opc.h (AMD64): Removed.
1590 (Intel64): Likewose.
1591 (AMD64): New.
1592 (INTEL64): Likewise.
1593 (INTEL64ONLY): Likewise.
1594 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
1595 * i386-opc.tbl (Amd64): New.
1596 (Intel64): Likewise.
1597 (Intel64Only): Likewise.
1598 Replace AMD64 with Amd64. Update sysenter/sysenter with
1599 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
1600 * i386-tbl.h: Regenerated.
1601
9fc0b501
SB		 16022020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
1603
1604 PR 25469
1605 * z80-dis.c: Add support for GBZ80 opcodes.
1606
c5d7be0c
AM		 16072020-02-04 Alan Modra <amodra@gmail.com>
1608
1609 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
1610
44e4546f
AM		 16112020-02-03 Alan Modra <amodra@gmail.com>
1612
1613 * m32c-ibld.c: Regenerate.
1614
b2b1453a
AM		 16152020-02-01 Alan Modra <amodra@gmail.com>
1616
1617 * frv-ibld.c: Regenerate.
1618
4102be5c
JB		 16192020-01-31 Jan Beulich <jbeulich@suse.com>
1620
1621 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
1622 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
1623 (OP_E_memory): Replace xmm_mdq_mode case label by
1624 vex_scalar_w_dq_mode one.
1625 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
1626
825bd36c
JB		 16272020-01-31 Jan Beulich <jbeulich@suse.com>
1628
1629 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
1630 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
1631 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
1632 (intel_operand_size): Drop vex_w_dq_mode case label.
1633
c3036ed0
RS		 16342020-01-31 Richard Sandiford <richard.sandiford@arm.com>
1635
1636 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
1637 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
1638
0c115f84
AM		 16392020-01-30 Alan Modra <amodra@gmail.com>
1640
1641 * m32c-ibld.c: Regenerate.
1642
bd434cc4
JM		 16432020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
1644
1645 * bpf-opc.c: Regenerate.
1646
aeab2b26
JB		 16472020-01-30 Jan Beulich <jbeulich@suse.com>
1648
1649 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
1650 (dis386): Use them to replace C2/C3 table entries.
1651 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
1652 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
1653 ones. Use Size64 instead of DefaultSize on Intel64 ones.
1654 * i386-tbl.h: Re-generate.
1655
62b3f548
JB		 16562020-01-30 Jan Beulich <jbeulich@suse.com>
1657
1658 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
1659 forms.
1660 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
1661 DefaultSize.
1662 * i386-tbl.h: Re-generate.
1663
1bd8ae10
AM		 16642020-01-30 Alan Modra <amodra@gmail.com>
1665
1666 * tic4x-dis.c (tic4x_dp): Make unsigned.
1667
bc31405e
L		 16682020-01-27 H.J. Lu <hongjiu.lu@intel.com>
1669 Jan Beulich <jbeulich@suse.com>
1670
1671 PR binutils/25445
1672 * i386-dis.c (MOVSXD_Fixup): New function.
1673 (movsxd_mode): New enum.
1674 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
1675 (intel_operand_size): Handle movsxd_mode.
1676 (OP_E_register): Likewise.
1677 (OP_G): Likewise.
1678 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
1679 register on movsxd. Add movsxd with 16-bit destination register
1680 for AMD64 and Intel64 ISAs.
1681 * i386-tbl.h: Regenerated.
1682
7568c93b
TC		 16832020-01-27 Tamar Christina <tamar.christina@arm.com>
1684
1685 PR 25403
1686 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
1687 * aarch64-asm-2.c: Regenerate
1688 * aarch64-dis-2.c: Likewise.
1689 * aarch64-opc-2.c: Likewise.
1690
c006a730
JB		 16912020-01-21 Jan Beulich <jbeulich@suse.com>
1692
1693 * i386-opc.tbl (sysret): Drop DefaultSize.
1694 * i386-tbl.h: Re-generate.
1695
c906a69a
JB		 16962020-01-21 Jan Beulich <jbeulich@suse.com>
1697
1698 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
1699 Dword.
1700 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
1701 * i386-tbl.h: Re-generate.
1702
26916852
NC		 17032020-01-20 Nick Clifton <nickc@redhat.com>
1704
1705 * po/de.po: Updated German translation.
1706 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1707 * po/uk.po: Updated Ukranian translation.
1708
4d6cbb64
AM		 17092020-01-20 Alan Modra <amodra@gmail.com>
1710
1711 * hppa-dis.c (fput_const): Remove useless cast.
1712
2bddb71a
AM		 17132020-01-20 Alan Modra <amodra@gmail.com>
1714
1715 * arm-dis.c (print_insn_arm): Wrap 'T' value.
1716
1b1bb2c6
NC		 17172020-01-18 Nick Clifton <nickc@redhat.com>
1718
1719 * configure: Regenerate.
1720 * po/opcodes.pot: Regenerate.
1721
ae774686
NC		 17222020-01-18 Nick Clifton <nickc@redhat.com>
1723
1724 Binutils 2.34 branch created.
1725
07f1f3aa
CB		 17262020-01-17 Christian Biesinger <cbiesinger@google.com>
1727
1728 * opintl.h: Fix spelling error (seperate).
1729
42e04b36
L		 17302020-01-17 H.J. Lu <hongjiu.lu@intel.com>
1731
1732 * i386-opc.tbl: Add {vex} pseudo prefix.
1733 * i386-tbl.h: Regenerated.
1734
2da2eaf4
AV		 17352020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
1736
1737 PR 25376
1738 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
1739 (neon_opcodes): Likewise.
1740 (select_arm_features): Make sure we enable MVE bits when selecting
1741 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
1742 any architecture.
1743
d0849eed
JB		 17442020-01-16 Jan Beulich <jbeulich@suse.com>
1745
1746 * i386-opc.tbl: Drop stale comment from XOP section.
1747
9cf70a44
JB		 17482020-01-16 Jan Beulich <jbeulich@suse.com>
1749
1750 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
1751 (extractps): Add VexWIG to SSE2AVX forms.
1752 * i386-tbl.h: Re-generate.
1753
4814632e
JB		 17542020-01-16 Jan Beulich <jbeulich@suse.com>
1755
1756 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
1757 Size64 from and use VexW1 on SSE2AVX forms.
1758 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
1759 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
1760 * i386-tbl.h: Re-generate.
1761
aad09917
AM		 17622020-01-15 Alan Modra <amodra@gmail.com>
1763
1764 * tic4x-dis.c (tic4x_version): Make unsigned long.
1765 (optab, optab_special, registernames): New file scope vars.
1766 (tic4x_print_register): Set up registernames rather than
1767 malloc'd registertable.
1768 (tic4x_disassemble): Delete optable and optable_special. Use
1769 optab and optab_special instead. Throw away old optab,
1770 optab_special and registernames when info->mach changes.
1771
7a6bf3be
SB		 17722020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
1773
1774 PR 25377
1775 * z80-dis.c (suffix): Use .db instruction to generate double
1776 prefix.
1777
ca1eaac0
AM		 17782020-01-14 Alan Modra <amodra@gmail.com>
1779
1780 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
1781 values to unsigned before shifting.
1782
1d67fe3b
TT		 17832020-01-13 Thomas Troeger <tstroege@gmx.de>
1784
1785 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
1786 flow instructions.
1787 (print_insn_thumb16, print_insn_thumb32): Likewise.
1788 (print_insn): Initialize the insn info.
1789 * i386-dis.c (print_insn): Initialize the insn info fields, and
1790 detect jumps.
1791
5e4f7e05
CZ		 17922012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1793
1794 * arc-opc.c (C_NE): Make it required.
1795
b9fe6b8a
CZ		 17962012-01-13 Claudiu Zissulescu <claziss@gmail.com>
1797
1798 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
1799 reserved register name.
1800
90dee485
AM		 18012020-01-13 Alan Modra <amodra@gmail.com>
1802
1803 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
1804 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
1805
febda64f
AM		 18062020-01-13 Alan Modra <amodra@gmail.com>
1807
1808 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
1809 result of wasm_read_leb128 in a uint64_t and check that bits
1810 are not lost when copying to other locals. Use uint32_t for
1811 most locals. Use PRId64 when printing int64_t.
1812
df08b588
AM		 18132020-01-13 Alan Modra <amodra@gmail.com>
1814
1815 * score-dis.c: Formatting.
1816 * score7-dis.c: Formatting.
1817
b2c759ce
AM		 18182020-01-13 Alan Modra <amodra@gmail.com>
1819
1820 * score-dis.c (print_insn_score48): Use unsigned variables for
1821 unsigned values. Don't left shift negative values.
1822 (print_insn_score32): Likewise.
1823 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
1824
5496abe1
AM		 18252020-01-13 Alan Modra <amodra@gmail.com>
1826
1827 * tic4x-dis.c (tic4x_print_register): Remove dead code.
1828
202e762b
AM		 18292020-01-13 Alan Modra <amodra@gmail.com>
1830
1831 * fr30-ibld.c: Regenerate.
1832
7ef412cf
AM		 18332020-01-13 Alan Modra <amodra@gmail.com>
1834
1835 * xgate-dis.c (print_insn): Don't left shift signed value.
1836 (ripBits): Formatting, use 1u.
1837
7f578b95
AM		 18382020-01-10 Alan Modra <amodra@gmail.com>
1839
1840 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
1841 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
1842
441af85b
AM		 18432020-01-10 Alan Modra <amodra@gmail.com>
1844
1845 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
1846 and XRREG value earlier to avoid a shift with negative exponent.
1847 * m10200-dis.c (disassemble): Similarly.
1848
bce58db4
NC		 18492020-01-09 Nick Clifton <nickc@redhat.com>
1850
1851 PR 25224
1852 * z80-dis.c (ld_ii_ii): Use correct cast.
1853
40c75bc8
SB		 18542020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
1855
1856 PR 25224
1857 * z80-dis.c (ld_ii_ii): Use character constant when checking
1858 opcode byte value.
1859
d835a58b
JB		 18602020-01-09 Jan Beulich <jbeulich@suse.com>
1861
1862 * i386-dis.c (SEP_Fixup): New.
1863 (SEP): Define.
1864 (dis386_twobyte): Use it for sysenter/sysexit.
1865 (enum x86_64_isa): Change amd64 enumerator to value 1.
1866 (OP_J): Compare isa64 against intel64 instead of amd64.
1867 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
1868 forms.
1869 * i386-tbl.h: Re-generate.
1870
030a2e78
AM		 18712020-01-08 Alan Modra <amodra@gmail.com>
1872
1873 * z8k-dis.c: Include libiberty.h
1874 (instr_data_s): Make max_fetched unsigned.
1875 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
1876 Don't exceed byte_info bounds.
1877 (output_instr): Make num_bytes unsigned.
1878 (unpack_instr): Likewise for nibl_count and loop.
1879 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
1880 idx unsigned.
1881 * z8k-opc.h: Regenerate.
1882
bb82aefe
SV		 18832020-01-07 Shahab Vahedi <shahab@synopsys.com>
1884
1885 * arc-tbl.h (llock): Use 'LLOCK' as class.
1886 (llockd): Likewise.
1887 (scond): Use 'SCOND' as class.
1888 (scondd): Likewise.
1889 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
1890 (scondd): Likewise.
1891
cc6aa1a6
AM		 18922020-01-06 Alan Modra <amodra@gmail.com>
1893
1894 * m32c-ibld.c: Regenerate.
1895
660e62b1
AM		 18962020-01-06 Alan Modra <amodra@gmail.com>
1897
1898 PR 25344
1899 * z80-dis.c (suffix): Don't use a local struct buffer copy.
1900 Peek at next byte to prevent recursion on repeated prefix bytes.
1901 Ensure uninitialised "mybuf" is not accessed.
1902 (print_insn_z80): Don't zero n_fetch and n_used here,..
1903 (print_insn_z80_buf): ..do it here instead.
1904
c9ae58fe
AM		 19052020-01-04 Alan Modra <amodra@gmail.com>
1906
1907 * m32r-ibld.c: Regenerate.
1908
5f57d4ec
AM		 19092020-01-04 Alan Modra <amodra@gmail.com>
1910
1911 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
1912
2c5c1196
AM		 19132020-01-04 Alan Modra <amodra@gmail.com>
1914
1915 * crx-dis.c (match_opcode): Avoid shift left of signed value.
1916
2e98c6c5
AM		 19172020-01-04 Alan Modra <amodra@gmail.com>
1918
1919 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
1920
567dfba2
JB		 19212020-01-03 Jan Beulich <jbeulich@suse.com>
1922
5437a02a
JB		 1923 * aarch64-tbl.h (aarch64_opcode_table): Use
1924 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
1925
19262020-01-03 Jan Beulich <jbeulich@suse.com>
1927
1928 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 1929 forms of SUDOT and USDOT.
1930
8c45011a
JB		 19312020-01-03 Jan Beulich <jbeulich@suse.com>
1932
5437a02a 1933 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 1934 uzip{1,2}.
1935 * opcodes/aarch64-dis-2.c: Re-generate.
1936
f4950f76
JB		 19372020-01-03 Jan Beulich <jbeulich@suse.com>
1938
5437a02a 1939 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 1940 FMMLA encoding.
1941 * opcodes/aarch64-dis-2.c: Re-generate.
1942
6655dba2
SB		 19432020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
1944
1945 * z80-dis.c: Add support for eZ80 and Z80 instructions.
1946
b14ce8bf
AM		 19472020-01-01 Alan Modra <amodra@gmail.com>
1948
1949 Update year range in copyright notice of all files.
1950
0b114740 1951For older changes see ChangeLog-2019
3499769a 1952\f
0b114740 1953Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 1954
1955Copying and distribution of this file, with or without modification,
1956are permitted in any medium without royalty provided the copyright
1957notice and this notice are preserved.
1958
1959Local Variables:
1960mode: change-log
1961left-margin: 8
1962fill-column: 74
1963version-control: never
1964End:
A mirror of the official binutils-gdb repository