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x86-64: have value properly checked when resolving fixup
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
b3ea7639
MF		 12020-04-23 Max Filippov <jcmvbkbc@gmail.com>
2
3 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
4 of l32r fetch and display referenced literal value.
5
c1cbb7d8
MF		 62021-04-23 Max Filippov <jcmvbkbc@gmail.com>
7
8 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
9 to 4 for literal disassembly.
10
02202574
PW		 112021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
12
13 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
14 for TLBI instruction.
15
cd6608e4
PW		 162021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
17
18 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
19 DC instruction.
20
fe1640ff
JB		 212021-04-19 Jan Beulich <jbeulich@suse.com>
22
23 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
24 "qualifier".
25 (convert_mov_to_movewide): Add initializer for "value".
26
100e914d
PW		 272021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
28
29 * aarch64-opc.c: Add RME system registers.
30
a21b96dd
NC		 312021-04-16 Lifang Xia <lifang_xia@c-sky.com>
32
33 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
34 "addi d,CV,z" to "c.mv d,CV".
35
43e05cd4
AM		 362021-04-12 Alan Modra <amodra@gmail.com>
37
38 * configure.ac (--enable-checking): Add support.
39 * config.in: Regenerate.
40 * configure: Regenerate.
41
52efda82
TB		 422021-04-09 Tejas Belagod <tejas.belagod@arm.com>
43
44 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
45 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
46
c3f72de4
AM		 472021-04-09 Alan Modra <amodra@gmail.com>
48
49 * ppc-dis.c (struct dis_private): Add "special".
50 (POWERPC_DIALECT): Delete. Replace uses with..
51 (private_data): ..this. New inline function.
52 (disassemble_init_powerpc): Init "special" names.
53 (skip_optional_operands): Add is_pcrel arg, set when detecting R
54 field of prefix instructions.
55 (bsearch_reloc, print_got_plt): New functions.
56 (print_insn_powerpc): For pcrel instructions, print target address
57 and symbol if known, and decode plt and got loads too.
58
ce7d813a
AM		 592021-04-08 Alan Modra <amodra@gmail.com>
60
61 PR 27684
62 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
63
97bf40d8
AM		 642021-04-08 Alan Modra <amodra@gmail.com>
65
66 PR 27676
67 * ppc-opc.c (DCBT_EO): Move earlier.
68 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
69 (powerpc_operands): Add THCT and THDS entries.
70 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
71
a2e66773
AM		 722021-04-06 Alan Modra <amodra@gmail.com>
73
74 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
75 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
76 symbol_at_address_func.
77
ab2af25e
AM		 782021-04-05 Alan Modra <amodra@gmail.com>
79
80 * configure.ac: Don't check for limits.h, string.h, strings.h or
81 stdlib.h.
82 (AC_ISC_POSIX): Don't invoke.
83 * sysdep.h: Include stdlib.h and string.h unconditionally.
84 * i386-opc.h: Include limits.h unconditionally.
85 * wasm32-dis.c: Likewise.
86 * cgen-opc.c: Don't include alloca-conf.h.
87 * config.in: Regenerate.
88 * configure: Regenerate.
89
e9b095a5
ML		 902021-04-01 Martin Liska <mliska@suse.cz>
91
92 * arm-dis.c (strneq): Remove strneq and use startswith.
93 * cr16-dis.c (print_insn_cr16): Likewise.
94 * score-dis.c (streq): Likewise.
95 (strneq): Likewise.
96 * score7-dis.c (strneq): Likewise.
97
1cb108e4
AM		 982021-04-01 Alan Modra <amodra@gmail.com>
99
100 PR 27675
101 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
102
78933a4a
AM		 1032021-03-31 Alan Modra <amodra@gmail.com>
104
105 * sysdep.h (POISON_BFD_BOOLEAN): Define.
106 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
107 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
108 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
109 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
110 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
111 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
112 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
113 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
114 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
115 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
116 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
117 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
118 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
119 and TRUE with true throughout.
120
3dfb1b6d
AM		 1212021-03-31 Alan Modra <amodra@gmail.com>
122
123 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
124 * aarch64-dis.h: Likewise.
125 * aarch64-opc.c: Likewise.
126 * avr-dis.c: Likewise.
127 * csky-dis.c: Likewise.
128 * nds32-asm.c: Likewise.
129 * nds32-dis.c: Likewise.
130 * nfp-dis.c: Likewise.
131 * riscv-dis.c: Likewise.
132 * s12z-dis.c: Likewise.
133 * wasm32-dis.c: Likewise.
134
5e042380
JB		 1352021-03-30 Jan Beulich <jbeulich@suse.com>
136
137 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
138 (i386_seg_prefixes): New.
139 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
140 (i386_seg_prefixes): Declare.
141
34684862
JB		 1422021-03-30 Jan Beulich <jbeulich@suse.com>
143
144 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
145
6288d05f
JB		 1462021-03-30 Jan Beulich <jbeulich@suse.com>
147
148 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
149 * i386-reg.tbl (st): Move down.
150 (st(0)): Delete. Extend comment.
151 * i386-tbl.h: Re-generate.
152
bbe1eca6
JB		 1532021-03-29 Jan Beulich <jbeulich@suse.com>
154
155 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
156 (cmpsd): Move next to cmps.
157 (movsd): Move next to movs.
158 (cmpxchg16b): Move to separate section.
159 (fisttp, fisttpll): Likewise.
160 (monitor, mwait): Likewise.
161 * i386-tbl.h: Re-generate.
162
c8cad9d3
JB		 1632021-03-29 Jan Beulich <jbeulich@suse.com>
164
165 * i386-opc.tbl (psadbw): Add <sse2:comm>.
166 (vpsadbw): Add C.
167 * i386-tbl.h: Re-generate.
168
5cdaf100
JB		 1692021-03-29 Jan Beulich <jbeulich@suse.com>
170
171 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
172 pclmul, gfni): New templates. Use them wherever possible. Move
173 SSE4.1 pextrw into respective section.
174 * i386-tbl.h: Re-generate.
175
73e45eb2
JB		 1762021-03-29 Jan Beulich <jbeulich@suse.com>
177
178 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
179 strtoull(). Bump upper loop bound. Widen masks. Sanity check
180 "length".
181 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
182 Convert all of their uses to representation in opcode.
183
9df6f676
JB		 1842021-03-29 Jan Beulich <jbeulich@suse.com>
185
186 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
187 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
188 value of None. Shrink operands to 3 bits.
189
389d00a5
JB		 1902021-03-29 Jan Beulich <jbeulich@suse.com>
191
192 * i386-gen.c (process_i386_opcode_modifier): New parameter
193 "space".
194 (output_i386_opcode): New local variable "space". Adjust
195 process_i386_opcode_modifier() invocation.
196 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
197 invocation.
198 * i386-tbl.h: Re-generate.
199
63b4cc53
AM		 2002021-03-29 Alan Modra <amodra@gmail.com>
201
202 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
203 (fp_qualifier_p, get_data_pattern): Likewise.
204 (aarch64_get_operand_modifier_from_value): Likewise.
205 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
206 (operand_variant_qualifier_p): Likewise.
207 (qualifier_value_in_range_constraint_p): Likewise.
208 (aarch64_get_qualifier_esize): Likewise.
209 (aarch64_get_qualifier_nelem): Likewise.
210 (aarch64_get_qualifier_standard_value): Likewise.
211 (get_lower_bound, get_upper_bound): Likewise.
212 (aarch64_find_best_match, match_operands_qualifier): Likewise.
213 (aarch64_print_operand): Likewise.
214 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
215 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
216 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
217 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
218 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
219 (print_insn_tic6x): Likewise.
220
3d7d6c1b
AM		 2212021-03-29 Alan Modra <amodra@gmail.com>
222
223 * arc-dis.c (extract_operand_value): Correct NULL cast.
224 * frv-opc.h: Regenerate.
225
c3344b62
JB		 2262021-03-26 Jan Beulich <jbeulich@suse.com>
227
228 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
229 MMX form.
230 * i386-tbl.h: Re-generate.
231
efa30ac3
HAQ		 2322021-03-25 Abid Qadeer <abidh@codesourcery.com>
233
234 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
235 immediate in br.n instruction.
236
596a02ff
JB		 2372021-03-25 Jan Beulich <jbeulich@suse.com>
238
239 * i386-dis.c (XMGatherD, VexGatherD): New.
240 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
241 (print_insn): Check masking for S/G insns.
242 (OP_E_memory): New local variable check_gather. Extend mandatory
243 SIB check. Check register conflicts for (EVEX-encoded) gathers.
244 Extend check for disallowed 16-bit addressing.
245 (OP_VEX): New local variables modrm_reg and sib_index. Convert
246 if()s to switch(). Check register conflicts for (VEX-encoded)
247 gathers. Drop no longer reachable cases.
248 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
249 vgatherdp*.
250
53642852
JB		 2512021-03-25 Jan Beulich <jbeulich@suse.com>
252
253 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
254 zeroing-masking without masking.
255
c0e54661
JB		 2562021-03-25 Jan Beulich <jbeulich@suse.com>
257
258 * i386-opc.tbl (invlpgb): Fix multi-operand form.
259 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
260 single-operand forms as deprecated.
261 * i386-tbl.h: Re-generate.
262
5a403766
AM		 2632021-03-25 Alan Modra <amodra@gmail.com>
264
265 PR 27647
266 * ppc-opc.c (XLOCB_MASK): Delete.
267 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
268 XLBH_MASK.
269 (powerpc_opcodes): Accept a BH field on all extended forms of
270 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
271
9a182d04
JB		 2722021-03-24 Jan Beulich <jbeulich@suse.com>
273
274 * i386-gen.c (output_i386_opcode): Drop processing of
275 opcode_length. Calculate length from base_opcode. Adjust prefix
276 encoding determination.
277 (process_i386_opcodes): Drop output of fake opcode_length.
278 * i386-opc.h (struct insn_template): Drop opcode_length field.
279 * i386-opc.tbl: Drop opcode length field from all templates.
280 * i386-tbl.h: Re-generate.
281
35648716
JB		 2822021-03-24 Jan Beulich <jbeulich@suse.com>
283
284 * i386-gen.c (process_i386_opcode_modifier): Return void. New
285 parameter "prefix". Drop local variable "regular_encoding".
286 Record prefix setting / check for consistency.
287 (output_i386_opcode): Parse opcode_length and base_opcode
288 earlier. Derive prefix encoding. Drop no longer applicable
289 consistency checking. Adjust process_i386_opcode_modifier()
290 invocation.
291 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
292 invocation.
293 * i386-tbl.h: Re-generate.
294
31184569
JB		 2952021-03-24 Jan Beulich <jbeulich@suse.com>
296
297 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
298 check.
299 * i386-opc.h (Prefix_*): Move #define-s.
300 * i386-opc.tbl: Move pseudo prefix enumerator values to
301 extension opcode field. Introduce pseudopfx template.
302 * i386-tbl.h: Re-generate.
303
b933fa4b
JB		 3042021-03-23 Jan Beulich <jbeulich@suse.com>
305
306 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
307 comment.
308 * i386-tbl.h: Re-generate.
309
dac10fb0
JB		 3102021-03-23 Jan Beulich <jbeulich@suse.com>
311
312 * i386-opc.h (struct insn_template): Move cpu_flags field past
313 opcode_modifier one.
314 * i386-tbl.h: Re-generate.
315
441f6aca
JB		 3162021-03-23 Jan Beulich <jbeulich@suse.com>
317
318 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
319 * i386-opc.h (OpcodeSpace): New enumerator.
320 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
321 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
322 SPACE_XOP09, SPACE_XOP0A): ... respectively.
323 (struct i386_opcode_modifier): New field opcodespace. Shrink
324 opcodeprefix field.
325 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
326 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
327 OpcodePrefix uses.
328 * i386-tbl.h: Re-generate.
329
08dedd66
ML		 3302021-03-22 Martin Liska <mliska@suse.cz>
331
332 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
333 * arc-dis.c (parse_option): Likewise.
334 * arm-dis.c (parse_arm_disassembler_options): Likewise.
335 * cris-dis.c (print_with_operands): Likewise.
336 * h8300-dis.c (bfd_h8_disassemble): Likewise.
337 * i386-dis.c (print_insn): Likewise.
338 * ia64-gen.c (fetch_insn_class): Likewise.
339 (parse_resource_users): Likewise.
340 (in_iclass): Likewise.
341 (lookup_specifier): Likewise.
342 (insert_opcode_dependencies): Likewise.
343 * mips-dis.c (parse_mips_ase_option): Likewise.
344 (parse_mips_dis_option): Likewise.
345 * s390-dis.c (disassemble_init_s390): Likewise.
346 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
347
80d49d6a
KLC		 3482021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
349
350 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
351
7fce7ea9
PW		 3522021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
353
354 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
355 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
356
78c84bf9
AM		 3572021-03-12 Alan Modra <amodra@gmail.com>
358
359 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
360
fd1fd061
JB		 3612021-03-11 Jan Beulich <jbeulich@suse.com>
362
363 * i386-dis.c (OP_XMM): Re-order checks.
364
ac7a2311
JB		 3652021-03-11 Jan Beulich <jbeulich@suse.com>
366
367 * i386-dis.c (putop): Drop need_vex check when also checking
368 vex.evex.
369 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
370 checking vex.b.
371
da944c8a
JB		 3722021-03-11 Jan Beulich <jbeulich@suse.com>
373
374 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
375 checks. Move case label past broadcast check.
376
b763d508
JB		 3772021-03-10 Jan Beulich <jbeulich@suse.com>
378
379 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
380 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
381 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
382 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
383 EVEX_W_0F38C7_M_0_L_2): Delete.
384 (REG_EVEX_0F38C7_M_0_L_2): New.
385 (intel_operand_size): Handle VEX and EVEX the same for
386 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
387 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
388 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
389 vex_vsib_q_w_d_mode uses.
390 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
391 0F38A1, and 0F38A3 entries.
392 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
393 entry.
394 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
395 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
396 0F38A3 entries.
397
32e31ad7
JB		 3982021-03-10 Jan Beulich <jbeulich@suse.com>
399
400 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
401 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
402 MOD_VEX_0FXOP_09_12): Rename to ...
403 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
404 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
405 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
406 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
407 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
408 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
409 (reg_table): Adjust comments.
410 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
411 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
412 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
413 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
414 (vex_len_table): Adjust opcode 0A_12 entry.
415 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
416 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
417 (rm_table): Move hreset entry.
418
85ba7507
JB		 4192021-03-10 Jan Beulich <jbeulich@suse.com>
420
421 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
422 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
423 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
424 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
425 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
426 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
427 (get_valid_dis386): Also handle 512-bit vector length when
428 vectoring into vex_len_table[].
429 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
430 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
431 entries.
432 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
433 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
434 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
435 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
436 entries.
437
066f82b9
JB		 4382021-03-10 Jan Beulich <jbeulich@suse.com>
439
440 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
441 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
442 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
443 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
444 entries.
445 * i386-dis-evex-len.h (evex_len_table): Likewise.
446 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
447
fc681dd6
JB		 4482021-03-10 Jan Beulich <jbeulich@suse.com>
449
450 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
451 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
452 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
453 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
454 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
455 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
456 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
457 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
458 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
459 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
460 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
461 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
462 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
463 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
464 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
465 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
466 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
467 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
468 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
469 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
470 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
471 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
472 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
473 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
474 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
475 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
476 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
477 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
478 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
479 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
480 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
481 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
482 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
483 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
484 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
485 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
486 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
487 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
488 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
489 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
490 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
491 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
492 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
493 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
494 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
495 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
496 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
497 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
498 EVEX_W_0F3A43_L_n): New.
499 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
500 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
501 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
502 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
503 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
504 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
505 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
506 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
507 0F385B, 0F38C6, and 0F38C7 entries.
508 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
509 0F38C6 and 0F38C7.
510 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
511 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
512 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
513 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
514
13954a31
JB		 5152021-03-10 Jan Beulich <jbeulich@suse.com>
516
517 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
518 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
519 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
520 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
521 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
522 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
523 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
524 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
525 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
526 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
527 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
528 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
529 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
530 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
531 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
532 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
533 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
534 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
535 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
536 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
537 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
538 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
539 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
540 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
541 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
542 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
543 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
544 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
545 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
546 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
547 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
548 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
549 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
550 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
551 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
552 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
553 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
554 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
555 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
556 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
557 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
558 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
559 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
560 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
561 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
562 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
563 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
564 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
565 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
566 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
567 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
568 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
569 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
570 VEX_W_0F99_P_2_LEN_0): Delete.
571 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
572 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
573 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
574 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
575 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
576 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
577 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
578 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
579 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
580 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
581 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
582 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
583 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
584 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
585 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
586 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
587 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
588 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
589 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
590 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
591 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
592 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
593 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
594 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
595 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
596 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
597 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
598 (prefix_table): No longer link to vex_len_table[] for opcodes
599 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
600 0F92, 0F93, 0F98, and 0F99.
601 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
602 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
603 0F98, and 0F99.
604 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
605 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
606 0F98, and 0F99.
607 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
608 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
609 0F98, and 0F99.
610 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
611 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
612 0F98, and 0F99.
613
14d10c6c
JB		 6142021-03-10 Jan Beulich <jbeulich@suse.com>
615
616 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
617 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
618 REG_VEX_0F73_M_0 respectively.
619 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
620 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
621 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
622 MOD_VEX_0F73_REG_7): Delete.
623 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
624 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
625 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
626 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
627 PREFIX_VEX_0F3AF0_L_0 respectively.
628 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
629 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
630 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
631 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
632 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
633 VEX_LEN_0F38F7): New.
634 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
635 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
636 0F72, and 0F73. No longer link to vex_len_table[] for opcode
637 0F38F3.
638 (prefix_table): No longer link to vex_len_table[] for opcodes
639 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
640 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
641 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
642 0F38F6, 0F38F7, and 0F3AF0.
643 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
644 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
645 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
646 0F73.
647
00ec1875
JB		 6482021-03-10 Jan Beulich <jbeulich@suse.com>
649
650 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
651 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
652 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
653 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
654 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
655 (MOD_0F71, MOD_0F72, MOD_0F73): New.
656 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
657 73.
658 (reg_table): No longer link to mod_table[] for opcodes 0F71,
659 0F72, and 0F73.
660 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
661 0F73.
662
31941983
JB		 6632021-03-10 Jan Beulich <jbeulich@suse.com>
664
665 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
666 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
667 (reg_table): Don't link to mod_table[] where not needed. Add
668 PREFIX_IGNORED to nop entries.
669 (prefix_table): Replace PREFIX_OPCODE in nop entries.
670 (mod_table): Add nop entries next to prefetch ones. Drop
671 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
672 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
673 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
674 PREFIX_OPCODE from endbr* entries.
675 (get_valid_dis386): Also consider entry's name when zapping
676 vindex.
677 (print_insn): Handle PREFIX_IGNORED.
678
742732c7
JB		 6792021-03-09 Jan Beulich <jbeulich@suse.com>
680
681 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
682 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
683 element.
684 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
685 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
686 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
687 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
688 (struct i386_opcode_modifier): Delete notrackprefixok,
689 islockable, hleprefixok, and repprefixok fields. Add prefixok
690 field.
691 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
692 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
693 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
694 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
695 Replace HLEPrefixOk.
696 * opcodes/i386-tbl.h: Re-generate.
697
e93a3b27
JB		 6982021-03-09 Jan Beulich <jbeulich@suse.com>
699
700 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
701 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
702 64-bit form.
703 * opcodes/i386-tbl.h: Re-generate.
704
75363b6d
JB		 7052021-03-03 Jan Beulich <jbeulich@suse.com>
706
707 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
708 for {} instead of {0}. Don't look for '0'.
709 * i386-opc.tbl: Drop operand count field. Drop redundant operand
710 size specifiers.
711
5a9f5403
NC		 7122021-02-19 Nelson Chu <nelson.chu@sifive.com>
713
714 PR 27158
715 * riscv-dis.c (print_insn_args): Updated encoding macros.
716 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
717 (match_c_addi16sp): Updated encoding macros.
718 (match_c_lui): Likewise.
719 (match_c_lui_with_hint): Likewise.
720 (match_c_addi4spn): Likewise.
721 (match_c_slli): Likewise.
722 (match_slli_as_c_slli): Likewise.
723 (match_c_slli64): Likewise.
724 (match_srxi_as_c_srxi): Likewise.
725 (riscv_insn_types): Added .insn css/cl/cs.
726
3d73d29e
NC		 7272021-02-18 Nelson Chu <nelson.chu@sifive.com>
728
729 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
730 (default_priv_spec): Updated type to riscv_spec_class.
731 (parse_riscv_dis_option): Updated.
732 * riscv-opc.c: Moved stuff and make the file tidy.
733
b9b204b3
AM		 7342021-02-17 Alan Modra <amodra@gmail.com>
735
736 * wasm32-dis.c: Include limits.h.
737 (CHAR_BIT): Provide backup define.
738 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
739 Correct signed overflow checking.
740
394ae71f
JB		 7412021-02-16 Jan Beulich <jbeulich@suse.com>
742
743 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
744 * i386-tbl.h: Re-generate.
745
b818b220
JB		 7462021-02-16 Jan Beulich <jbeulich@suse.com>
747
748 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
749 Oword.
750 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
751
ba2b480f
AK		 7522021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
753
754 * s390-mkopc.c (main): Accept arch14 as cpu string.
755 * s390-opc.txt: Add new arch14 instructions.
756
95148614
NA		 7572021-02-04 Nick Alcock <nick.alcock@oracle.com>
758
759 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
760 favour of LIBINTL.
761 * configure: Regenerated.
762
bfd428bc
MF		 7632021-02-08 Mike Frysinger <vapier@gentoo.org>
764
765 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
766 * tic54x-opc.c (regs): Rename to ...
767 (tic54x_regs): ... this.
768 (mmregs): Rename to ...
769 (tic54x_mmregs): ... this.
770 (condition_codes): Rename to ...
771 (tic54x_condition_codes): ... this.
772 (cc2_codes): Rename to ...
773 (tic54x_cc2_codes): ... this.
774 (cc3_codes): Rename to ...
775 (tic54x_cc3_codes): ... this.
776 (status_bits): Rename to ...
777 (tic54x_status_bits): ... this.
778 (misc_symbols): Rename to ...
779 (tic54x_misc_symbols): ... this.
780
24075dcc
NC		 7812021-02-04 Nelson Chu <nelson.chu@sifive.com>
782
783 * riscv-opc.c (MASK_RVB_IMM): Removed.
784 (riscv_opcodes): Removed zb* instructions.
785 (riscv_ext_version_table): Removed versions for zb*.
786
c3ffb8f3
AM		 7872021-01-26 Alan Modra <amodra@gmail.com>
788
789 * i386-gen.c (parse_template): Ensure entire template_instance
790 is initialised.
791
1942a048
NC		 7922021-01-15 Nelson Chu <nelson.chu@sifive.com>
793
794 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
795 (riscv_fpr_names_abi): Likewise.
796 (riscv_opcodes): Likewise.
797 (riscv_insn_types): Likewise.
798
b800637e
NC		 7992021-01-15 Nelson Chu <nelson.chu@sifive.com>
800
801 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
802
dcd709e0
NC		 8032021-01-15 Nelson Chu <nelson.chu@sifive.com>
804
805 * riscv-dis.c: Comments tidy and improvement.
806 * riscv-opc.c: Likewise.
807
5347ed60
AM		 8082021-01-13 Alan Modra <amodra@gmail.com>
809
810 * Makefile.in: Regenerate.
811
d546b610
L		 8122021-01-12 H.J. Lu <hongjiu.lu@intel.com>
813
814 PR binutils/26792
815 * configure.ac: Use GNU_MAKE_JOBSERVER.
816 * aclocal.m4: Regenerated.
817 * configure: Likewise.
818
6d104cac
NC		 8192021-01-12 Nick Clifton <nickc@redhat.com>
820
821 * po/sr.po: Updated Serbian translation.
822
83b33c6c
L		 8232021-01-11 H.J. Lu <hongjiu.lu@intel.com>
824
825 PR ld/27173
826 * configure: Regenerated.
827
82c70b08
KT		 8282021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
829
830 * aarch64-asm-2.c: Regenerate.
831 * aarch64-dis-2.c: Likewise.
832 * aarch64-opc-2.c: Likewise.
833 * aarch64-opc.c (aarch64_print_operand):
834 Delete handling of AARCH64_OPND_CSRE_CSR.
835 * aarch64-tbl.h (aarch64_feature_csre): Delete.
836 (CSRE): Likewise.
837 (_CSRE_INSN): Likewise.
838 (aarch64_opcode_table): Delete csr.
839
a8aa72b9
NC		 8402021-01-11 Nick Clifton <nickc@redhat.com>
841
842 * po/de.po: Updated German translation.
843 * po/fr.po: Updated French translation.
844 * po/pt_BR.po: Updated Brazilian Portuguese translation.
845 * po/sv.po: Updated Swedish translation.
846 * po/uk.po: Updated Ukranian translation.
847
a4966cd9
L		 8482021-01-09 H.J. Lu <hongjiu.lu@intel.com>
849
850 * configure: Regenerated.
851
573fe3fb
NC		 8522021-01-09 Nick Clifton <nickc@redhat.com>
853
854 * configure: Regenerate.
855 * po/opcodes.pot: Regenerate.
856
055bc77a
NC		 8572021-01-09 Nick Clifton <nickc@redhat.com>
858
859 * 2.36 release branch crated.
860
aae7fcb8
PB		 8612021-01-08 Peter Bergner <bergner@linux.ibm.com>
862
863 * ppc-opc.c (insert_dw, (extract_dw): New functions.
864 (DW, (XRC_MASK): Define.
865 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
866
64307045
AM		 8672021-01-09 Alan Modra <amodra@gmail.com>
868
869 * configure: Regenerate.
870
ed205222
NC		 8712021-01-08 Nick Clifton <nickc@redhat.com>
872
873 * po/sv.po: Updated Swedish translation.
874
fb932b57
NC		 8752021-01-08 Nick Clifton <nickc@redhat.com>
876
e84c8716
NC		 877 PR 27129
878 * aarch64-dis.c (determine_disassembling_preference): Move call to
879 aarch64_match_operands_constraint outside of the assertion.
880 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
881 Replace with a return of FALSE.
882
fb932b57
NC		 883 PR 27139
884 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
885 core system register.
886
f4782128
ST		 8872021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
888
889 * configure: Regenerate.
890
1b0927db
NC		 8912021-01-07 Nick Clifton <nickc@redhat.com>
892
893 * po/fr.po: Updated French translation.
894
3b288c8e
FN		 8952021-01-07 Fredrik Noring <noring@nocrew.org>
896
897 * m68k-opc.c (chkl): Change minimum architecture requirement to
898 m68020.
899
aa881ecd
PT		 9002021-01-07 Philipp Tomsich <prt@gnu.org>
901
902 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
903
2652cfad
CXW		 9042021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
905 Jim Wilson <jimw@sifive.com>
906 Andrew Waterman <andrew@sifive.com>
907 Maxim Blinov <maxim.blinov@embecosm.com>
908 Kito Cheng <kito.cheng@sifive.com>
909 Nelson Chu <nelson.chu@sifive.com>
910
911 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
912 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
913
250d07de
AM		 9142021-01-01 Alan Modra <amodra@gmail.com>
915
916 Update year range in copyright notice of all files.
917
c2795844 918For older changes see ChangeLog-2020
3499769a 919\f
c2795844 920Copyright (C) 2021 Free Software Foundation, Inc.
3499769a
AM		 921
922Copying and distribution of this file, with or without modification,
923are permitted in any medium without royalty provided the copyright
924notice and this notice are preserved.
925
926Local Variables:
927mode: change-log
928left-margin: 8
929fill-column: 74
930version-control: never
931End:
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