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Commit | Line | Data |
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bbe1eca6 JB |
1 | 2021-03-29 Jan Beulich <jbeulich@suse.com> |
2 | ||
3 | * i386-opc.tbl (movq, movabs): Move next to mov counterparts. | |
4 | (cmpsd): Move next to cmps. | |
5 | (movsd): Move next to movs. | |
6 | (cmpxchg16b): Move to separate section. | |
7 | (fisttp, fisttpll): Likewise. | |
8 | (monitor, mwait): Likewise. | |
9 | * i386-tbl.h: Re-generate. | |
10 | ||
c8cad9d3 JB |
11 | 2021-03-29 Jan Beulich <jbeulich@suse.com> |
12 | ||
13 | * i386-opc.tbl (psadbw): Add <sse2:comm>. | |
14 | (vpsadbw): Add C. | |
15 | * i386-tbl.h: Re-generate. | |
16 | ||
5cdaf100 JB |
17 | 2021-03-29 Jan Beulich <jbeulich@suse.com> |
18 | ||
19 | * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes, | |
20 | pclmul, gfni): New templates. Use them wherever possible. Move | |
21 | SSE4.1 pextrw into respective section. | |
22 | * i386-tbl.h: Re-generate. | |
23 | ||
73e45eb2 JB |
24 | 2021-03-29 Jan Beulich <jbeulich@suse.com> |
25 | ||
26 | * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use | |
27 | strtoull(). Bump upper loop bound. Widen masks. Sanity check | |
28 | "length". | |
29 | * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete. | |
30 | Convert all of their uses to representation in opcode. | |
31 | ||
9df6f676 JB |
32 | 2021-03-29 Jan Beulich <jbeulich@suse.com> |
33 | ||
34 | * i386-opc.h (struct insn_template): Shrink base_opcode to 16 | |
35 | bits. Shrink extension_opcode to 9 bits. Make it signed. Change | |
36 | value of None. Shrink operands to 3 bits. | |
37 | ||
389d00a5 JB |
38 | 2021-03-29 Jan Beulich <jbeulich@suse.com> |
39 | ||
40 | * i386-gen.c (process_i386_opcode_modifier): New parameter | |
41 | "space". | |
42 | (output_i386_opcode): New local variable "space". Adjust | |
43 | process_i386_opcode_modifier() invocation. | |
44 | (process_i386_opcodes): Adjust process_i386_opcode_modifier() | |
45 | invocation. | |
46 | * i386-tbl.h: Re-generate. | |
47 | ||
63b4cc53 AM |
48 | 2021-03-29 Alan Modra <amodra@gmail.com> |
49 | ||
50 | * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression. | |
51 | (fp_qualifier_p, get_data_pattern): Likewise. | |
52 | (aarch64_get_operand_modifier_from_value): Likewise. | |
53 | (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise. | |
54 | (operand_variant_qualifier_p): Likewise. | |
55 | (qualifier_value_in_range_constraint_p): Likewise. | |
56 | (aarch64_get_qualifier_esize): Likewise. | |
57 | (aarch64_get_qualifier_nelem): Likewise. | |
58 | (aarch64_get_qualifier_standard_value): Likewise. | |
59 | (get_lower_bound, get_upper_bound): Likewise. | |
60 | (aarch64_find_best_match, match_operands_qualifier): Likewise. | |
61 | (aarch64_print_operand): Likewise. | |
62 | * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise. | |
63 | (operand_need_sign_extension, operand_need_shift_by_two): Likewise. | |
64 | (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise. | |
65 | * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise. | |
66 | * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise. | |
67 | (print_insn_tic6x): Likewise. | |
68 | ||
3d7d6c1b AM |
69 | 2021-03-29 Alan Modra <amodra@gmail.com> |
70 | ||
71 | * arc-dis.c (extract_operand_value): Correct NULL cast. | |
72 | * frv-opc.h: Regenerate. | |
73 | ||
c3344b62 JB |
74 | 2021-03-26 Jan Beulich <jbeulich@suse.com> |
75 | ||
76 | * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to | |
77 | MMX form. | |
78 | * i386-tbl.h: Re-generate. | |
79 | ||
efa30ac3 HAQ |
80 | 2021-03-25 Abid Qadeer <abidh@codesourcery.com> |
81 | ||
82 | * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of | |
83 | immediate in br.n instruction. | |
84 | ||
596a02ff JB |
85 | 2021-03-25 Jan Beulich <jbeulich@suse.com> |
86 | ||
87 | * i386-dis.c (XMGatherD, VexGatherD): New. | |
88 | (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*. | |
89 | (print_insn): Check masking for S/G insns. | |
90 | (OP_E_memory): New local variable check_gather. Extend mandatory | |
91 | SIB check. Check register conflicts for (EVEX-encoded) gathers. | |
92 | Extend check for disallowed 16-bit addressing. | |
93 | (OP_VEX): New local variables modrm_reg and sib_index. Convert | |
94 | if()s to switch(). Check register conflicts for (VEX-encoded) | |
95 | gathers. Drop no longer reachable cases. | |
96 | * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and | |
97 | vgatherdp*. | |
98 | ||
53642852 JB |
99 | 2021-03-25 Jan Beulich <jbeulich@suse.com> |
100 | ||
101 | * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying | |
102 | zeroing-masking without masking. | |
103 | ||
c0e54661 JB |
104 | 2021-03-25 Jan Beulich <jbeulich@suse.com> |
105 | ||
106 | * i386-opc.tbl (invlpgb): Fix multi-operand form. | |
107 | (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark | |
108 | single-operand forms as deprecated. | |
109 | * i386-tbl.h: Re-generate. | |
110 | ||
5a403766 AM |
111 | 2021-03-25 Alan Modra <amodra@gmail.com> |
112 | ||
113 | PR 27647 | |
114 | * ppc-opc.c (XLOCB_MASK): Delete. | |
115 | (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using | |
116 | XLBH_MASK. | |
117 | (powerpc_opcodes): Accept a BH field on all extended forms of | |
118 | bclr, bclrl, bcctr, bcctrl, bctar, bctarl. | |
119 | ||
9a182d04 JB |
120 | 2021-03-24 Jan Beulich <jbeulich@suse.com> |
121 | ||
122 | * i386-gen.c (output_i386_opcode): Drop processing of | |
123 | opcode_length. Calculate length from base_opcode. Adjust prefix | |
124 | encoding determination. | |
125 | (process_i386_opcodes): Drop output of fake opcode_length. | |
126 | * i386-opc.h (struct insn_template): Drop opcode_length field. | |
127 | * i386-opc.tbl: Drop opcode length field from all templates. | |
128 | * i386-tbl.h: Re-generate. | |
129 | ||
35648716 JB |
130 | 2021-03-24 Jan Beulich <jbeulich@suse.com> |
131 | ||
132 | * i386-gen.c (process_i386_opcode_modifier): Return void. New | |
133 | parameter "prefix". Drop local variable "regular_encoding". | |
134 | Record prefix setting / check for consistency. | |
135 | (output_i386_opcode): Parse opcode_length and base_opcode | |
136 | earlier. Derive prefix encoding. Drop no longer applicable | |
137 | consistency checking. Adjust process_i386_opcode_modifier() | |
138 | invocation. | |
139 | (process_i386_opcodes): Adjust process_i386_opcode_modifier() | |
140 | invocation. | |
141 | * i386-tbl.h: Re-generate. | |
142 | ||
31184569 JB |
143 | 2021-03-24 Jan Beulich <jbeulich@suse.com> |
144 | ||
145 | * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix | |
146 | check. | |
147 | * i386-opc.h (Prefix_*): Move #define-s. | |
148 | * i386-opc.tbl: Move pseudo prefix enumerator values to | |
149 | extension opcode field. Introduce pseudopfx template. | |
150 | * i386-tbl.h: Re-generate. | |
151 | ||
b933fa4b JB |
152 | 2021-03-23 Jan Beulich <jbeulich@suse.com> |
153 | ||
154 | * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend | |
155 | comment. | |
156 | * i386-tbl.h: Re-generate. | |
157 | ||
dac10fb0 JB |
158 | 2021-03-23 Jan Beulich <jbeulich@suse.com> |
159 | ||
160 | * i386-opc.h (struct insn_template): Move cpu_flags field past | |
161 | opcode_modifier one. | |
162 | * i386-tbl.h: Re-generate. | |
163 | ||
441f6aca JB |
164 | 2021-03-23 Jan Beulich <jbeulich@suse.com> |
165 | ||
166 | * i386-gen.c (opcode_modifiers): New OpcodeSpace element. | |
167 | * i386-opc.h (OpcodeSpace): New enumerator. | |
168 | (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ... | |
169 | (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08, | |
170 | SPACE_XOP09, SPACE_XOP0A): ... respectively. | |
171 | (struct i386_opcode_modifier): New field opcodespace. Shrink | |
172 | opcodeprefix field. | |
173 | i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08, | |
174 | SpaceXOP09, SpaceXOP0A): Define. Use them to replace | |
175 | OpcodePrefix uses. | |
176 | * i386-tbl.h: Re-generate. | |
177 | ||
08dedd66 ML |
178 | 2021-03-22 Martin Liska <mliska@suse.cz> |
179 | ||
180 | * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith. | |
181 | * arc-dis.c (parse_option): Likewise. | |
182 | * arm-dis.c (parse_arm_disassembler_options): Likewise. | |
183 | * cris-dis.c (print_with_operands): Likewise. | |
184 | * h8300-dis.c (bfd_h8_disassemble): Likewise. | |
185 | * i386-dis.c (print_insn): Likewise. | |
186 | * ia64-gen.c (fetch_insn_class): Likewise. | |
187 | (parse_resource_users): Likewise. | |
188 | (in_iclass): Likewise. | |
189 | (lookup_specifier): Likewise. | |
190 | (insert_opcode_dependencies): Likewise. | |
191 | * mips-dis.c (parse_mips_ase_option): Likewise. | |
192 | (parse_mips_dis_option): Likewise. | |
193 | * s390-dis.c (disassemble_init_s390): Likewise. | |
194 | * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise. | |
195 | ||
80d49d6a KLC |
196 | 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com> |
197 | ||
198 | * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions. | |
199 | ||
7fce7ea9 PW |
200 | 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com> |
201 | ||
202 | * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1, | |
203 | icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers. | |
204 | ||
78c84bf9 AM |
205 | 2021-03-12 Alan Modra <amodra@gmail.com> |
206 | ||
207 | * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo. | |
208 | ||
fd1fd061 JB |
209 | 2021-03-11 Jan Beulich <jbeulich@suse.com> |
210 | ||
211 | * i386-dis.c (OP_XMM): Re-order checks. | |
212 | ||
ac7a2311 JB |
213 | 2021-03-11 Jan Beulich <jbeulich@suse.com> |
214 | ||
215 | * i386-dis.c (putop): Drop need_vex check when also checking | |
216 | vex.evex. | |
217 | (intel_operand_size, OP_E_memory): Drop vex.evex check when also | |
218 | checking vex.b. | |
219 | ||
da944c8a JB |
220 | 2021-03-11 Jan Beulich <jbeulich@suse.com> |
221 | ||
222 | * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast | |
223 | checks. Move case label past broadcast check. | |
224 | ||
b763d508 JB |
225 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
226 | ||
227 | * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX, | |
228 | vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode, | |
229 | REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1, | |
230 | EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3, | |
231 | EVEX_W_0F38C7_M_0_L_2): Delete. | |
232 | (REG_EVEX_0F38C7_M_0_L_2): New. | |
233 | (intel_operand_size): Handle VEX and EVEX the same for | |
234 | vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop | |
235 | vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases. | |
236 | (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and | |
237 | vex_vsib_q_w_d_mode uses. | |
238 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893, | |
239 | 0F38A1, and 0F38A3 entries. | |
240 | * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7 | |
241 | entry. | |
242 | * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries. | |
243 | * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and | |
244 | 0F38A3 entries. | |
245 | ||
32e31ad7 JB |
246 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
247 | ||
248 | * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0, | |
249 | REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0, | |
250 | MOD_VEX_0FXOP_09_12): Rename to ... | |
251 | (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0, | |
252 | REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these. | |
253 | (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT, | |
254 | RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26, | |
255 | X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, | |
256 | X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move. | |
257 | (reg_table): Adjust comments. | |
258 | (x86_64_table): Move X86_64_0F24, X86_64_0F26, | |
259 | X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C, | |
260 | X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries. | |
261 | (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries. | |
262 | (vex_len_table): Adjust opcode 0A_12 entry. | |
263 | (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, | |
264 | MOD_C5_32BIT, and MOD_XOP_09_12 entries. | |
265 | (rm_table): Move hreset entry. | |
266 | ||
85ba7507 JB |
267 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
268 | ||
269 | * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1, | |
270 | EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6, | |
271 | EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15, | |
272 | EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20, | |
273 | EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete. | |
274 | (EVEX_LEN_0F3816, EVEX_W_0FD6): New. | |
275 | (get_valid_dis386): Also handle 512-bit vector length when | |
276 | vectoring into vex_len_table[]. | |
277 | * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5, | |
278 | 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 | |
279 | entries. | |
280 | * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6, | |
281 | 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries. | |
282 | * i386-dis-evex-prefix.h: Adjust 0F7E entry. | |
283 | * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21 | |
284 | entries. | |
285 | ||
066f82b9 JB |
286 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
287 | ||
288 | * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1): | |
289 | Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively. | |
290 | EVEX_W_0F3A00, EVEX_W_0F3A01): Delete. | |
291 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01 | |
292 | entries. | |
293 | * i386-dis-evex-len.h (evex_len_table): Likewise. | |
294 | * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries. | |
295 | ||
fc681dd6 JB |
296 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
297 | ||
298 | * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7, | |
299 | MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, | |
300 | MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, | |
301 | MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1, | |
302 | MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2, | |
303 | MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6, | |
304 | MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, | |
305 | MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6 | |
306 | EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1, | |
307 | EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0, | |
308 | EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0, | |
309 | EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0, | |
310 | EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0, | |
311 | EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0, | |
312 | EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0, | |
313 | EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1, | |
314 | EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1, | |
315 | EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1, | |
316 | EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1, | |
317 | EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0, | |
318 | EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1, | |
319 | EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0, | |
320 | EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1, | |
321 | EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0, | |
322 | EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1, | |
323 | EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819, | |
324 | EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B, | |
325 | EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0, | |
326 | EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0, | |
327 | EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B, | |
328 | EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A, | |
329 | EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete. | |
330 | REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0, | |
331 | REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A, | |
332 | MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B, | |
333 | MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819, | |
334 | EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0, | |
335 | EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0, | |
336 | EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0, | |
337 | EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A, | |
338 | EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38, | |
339 | EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B, | |
340 | EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n, | |
341 | EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n, | |
342 | EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2, | |
343 | EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2, | |
344 | EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n, | |
345 | EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2, | |
346 | EVEX_W_0F3A43_L_n): New. | |
347 | * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A, | |
348 | 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, | |
349 | 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries. | |
350 | * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[] | |
351 | for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7, | |
352 | 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A, | |
353 | 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6. | |
354 | * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A, | |
355 | 0F385B, 0F38C6, and 0F38C7 entries. | |
356 | * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes | |
357 | 0F38C6 and 0F38C7. | |
358 | * i386-dis-evex-w.h: No longer link to evex_len_table[] for | |
359 | opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, | |
360 | 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to | |
361 | evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B. | |
362 | ||
13954a31 JB |
363 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
364 | ||
365 | * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1, | |
366 | MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1, | |
367 | MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1, | |
368 | MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1, | |
369 | MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1, | |
370 | MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1, | |
371 | MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1, | |
372 | MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1, | |
373 | MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1, | |
374 | MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1, | |
375 | MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1, | |
376 | MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1, | |
377 | MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
378 | MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
379 | MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
380 | MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
381 | MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0, | |
382 | MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0, | |
383 | MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0, | |
384 | MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0, | |
385 | MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0, | |
386 | MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0, | |
387 | MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0, | |
388 | MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0, | |
389 | MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0, | |
390 | PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44, | |
391 | PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, | |
392 | PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90, | |
393 | PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93, | |
394 | PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0, | |
395 | VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2, | |
396 | VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0, | |
397 | VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2, | |
398 | VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0, | |
399 | VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2, | |
400 | VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0, | |
401 | VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2, | |
402 | VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2, | |
403 | VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2, | |
404 | VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1, | |
405 | VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1, | |
406 | VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0, | |
407 | VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1, | |
408 | VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1, | |
409 | VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1, | |
410 | VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1, | |
411 | VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1, | |
412 | VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0, | |
413 | VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0, | |
414 | VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0, | |
415 | VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0, | |
416 | VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0, | |
417 | VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0, | |
418 | VEX_W_0F99_P_2_LEN_0): Delete. | |
419 | MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0, | |
420 | MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1, | |
421 | MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0, | |
422 | MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0, | |
423 | MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0, | |
424 | PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0, | |
425 | PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0, | |
426 | PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0, | |
427 | PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0, | |
428 | PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0, | |
429 | PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0, | |
430 | PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0, | |
431 | PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0, | |
432 | PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0, | |
433 | PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0, | |
434 | PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0, | |
435 | PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0, | |
436 | PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0, | |
437 | PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42, | |
438 | VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47, | |
439 | VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91, | |
440 | VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99, | |
441 | VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1, | |
442 | VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1, | |
443 | VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0, | |
444 | VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1, | |
445 | VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New. | |
446 | (prefix_table): No longer link to vex_len_table[] for opcodes | |
447 | 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, | |
448 | 0F92, 0F93, 0F98, and 0F99. | |
449 | (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42, | |
450 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
451 | 0F98, and 0F99. | |
452 | (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42, | |
453 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
454 | 0F98, and 0F99. | |
455 | (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42, | |
456 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
457 | 0F98, and 0F99. | |
458 | (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42, | |
459 | 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93, | |
460 | 0F98, and 0F99. | |
461 | ||
14d10c6c JB |
462 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
463 | ||
464 | * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73): | |
465 | Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and | |
466 | REG_VEX_0F73_M_0 respectively. | |
467 | (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6, | |
468 | MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6, | |
469 | MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6, | |
470 | MOD_VEX_0F73_REG_7): Delete. | |
471 | (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New. | |
472 | (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7, | |
473 | PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0, | |
474 | PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0, | |
475 | PREFIX_VEX_0F3AF0_L_0 respectively. | |
476 | (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3, | |
477 | VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3, | |
478 | VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1, | |
479 | VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete. | |
480 | (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6, | |
481 | VEX_LEN_0F38F7): New. | |
482 | (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0. | |
483 | (reg_table): No longer link to mod_table[] for VEX opcodes 0F71, | |
484 | 0F72, and 0F73. No longer link to vex_len_table[] for opcode | |
485 | 0F38F3. | |
486 | (prefix_table): No longer link to vex_len_table[] for opcodes | |
487 | 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. | |
488 | (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and | |
489 | 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5, | |
490 | 0F38F6, 0F38F7, and 0F3AF0. | |
491 | (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to | |
492 | prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0. | |
493 | (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and | |
494 | 0F73. | |
495 | ||
00ec1875 JB |
496 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
497 | ||
498 | * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to | |
499 | REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively. | |
500 | (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2, | |
501 | MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3, | |
502 | MOD_0F73_REG_6, MOD_0F73_REG_7): Delete. | |
503 | (MOD_0F71, MOD_0F72, MOD_0F73): New. | |
504 | (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and | |
505 | 73. | |
506 | (reg_table): No longer link to mod_table[] for opcodes 0F71, | |
507 | 0F72, and 0F73. | |
508 | (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and | |
509 | 0F73. | |
510 | ||
31941983 JB |
511 | 2021-03-10 Jan Beulich <jbeulich@suse.com> |
512 | ||
513 | * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5, | |
514 | MOD_0F18_REG_6, MOD_0F18_REG_7): Delete. | |
515 | (reg_table): Don't link to mod_table[] where not needed. Add | |
516 | PREFIX_IGNORED to nop entries. | |
517 | (prefix_table): Replace PREFIX_OPCODE in nop entries. | |
518 | (mod_table): Add nop entries next to prefetch ones. Drop | |
519 | MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and | |
520 | MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries. | |
521 | (rm_table): Add PREFIX_IGNORED to nop entries. Drop | |
522 | PREFIX_OPCODE from endbr* entries. | |
523 | (get_valid_dis386): Also consider entry's name when zapping | |
524 | vindex. | |
525 | (print_insn): Handle PREFIX_IGNORED. | |
526 | ||
742732c7 JB |
527 | 2021-03-09 Jan Beulich <jbeulich@suse.com> |
528 | ||
529 | * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk, | |
530 | IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk | |
531 | element. | |
532 | * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone, | |
533 | HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete. | |
534 | (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack, | |
535 | PrefixLock, PrefixHLELock, PrefixHLEAny): Define. | |
536 | (struct i386_opcode_modifier): Delete notrackprefixok, | |
537 | islockable, hleprefixok, and repprefixok fields. Add prefixok | |
538 | field. | |
539 | * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny, | |
540 | HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define. | |
541 | (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg, | |
542 | not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b): | |
543 | Replace HLEPrefixOk. | |
544 | * opcodes/i386-tbl.h: Re-generate. | |
545 | ||
e93a3b27 JB |
546 | 2021-03-09 Jan Beulich <jbeulich@suse.com> |
547 | ||
548 | * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit. | |
549 | * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from | |
550 | 64-bit form. | |
551 | * opcodes/i386-tbl.h: Re-generate. | |
552 | ||
75363b6d JB |
553 | 2021-03-03 Jan Beulich <jbeulich@suse.com> |
554 | ||
555 | * i386-gen.c (output_i386_opcode): Don't get operand count. Look | |
556 | for {} instead of {0}. Don't look for '0'. | |
557 | * i386-opc.tbl: Drop operand count field. Drop redundant operand | |
558 | size specifiers. | |
559 | ||
5a9f5403 NC |
560 | 2021-02-19 Nelson Chu <nelson.chu@sifive.com> |
561 | ||
562 | PR 27158 | |
563 | * riscv-dis.c (print_insn_args): Updated encoding macros. | |
564 | * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM. | |
565 | (match_c_addi16sp): Updated encoding macros. | |
566 | (match_c_lui): Likewise. | |
567 | (match_c_lui_with_hint): Likewise. | |
568 | (match_c_addi4spn): Likewise. | |
569 | (match_c_slli): Likewise. | |
570 | (match_slli_as_c_slli): Likewise. | |
571 | (match_c_slli64): Likewise. | |
572 | (match_srxi_as_c_srxi): Likewise. | |
573 | (riscv_insn_types): Added .insn css/cl/cs. | |
574 | ||
3d73d29e NC |
575 | 2021-02-18 Nelson Chu <nelson.chu@sifive.com> |
576 | ||
577 | * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h. | |
578 | (default_priv_spec): Updated type to riscv_spec_class. | |
579 | (parse_riscv_dis_option): Updated. | |
580 | * riscv-opc.c: Moved stuff and make the file tidy. | |
581 | ||
b9b204b3 AM |
582 | 2021-02-17 Alan Modra <amodra@gmail.com> |
583 | ||
584 | * wasm32-dis.c: Include limits.h. | |
585 | (CHAR_BIT): Provide backup define. | |
586 | (wasm_read_leb128): Use CHAR_BIT to size "result" in bits. | |
587 | Correct signed overflow checking. | |
588 | ||
394ae71f JB |
589 | 2021-02-16 Jan Beulich <jbeulich@suse.com> |
590 | ||
591 | * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant. | |
592 | * i386-tbl.h: Re-generate. | |
593 | ||
b818b220 JB |
594 | 2021-02-16 Jan Beulich <jbeulich@suse.com> |
595 | ||
596 | * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor | |
597 | Oword. | |
598 | * i386-opc.tbl (CpuFP, Mmword, Oword): Define. | |
599 | ||
ba2b480f AK |
600 | 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com> |
601 | ||
602 | * s390-mkopc.c (main): Accept arch14 as cpu string. | |
603 | * s390-opc.txt: Add new arch14 instructions. | |
604 | ||
95148614 NA |
605 | 2021-02-04 Nick Alcock <nick.alcock@oracle.com> |
606 | ||
607 | * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in | |
608 | favour of LIBINTL. | |
609 | * configure: Regenerated. | |
610 | ||
bfd428bc MF |
611 | 2021-02-08 Mike Frysinger <vapier@gentoo.org> |
612 | ||
613 | * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs. | |
614 | * tic54x-opc.c (regs): Rename to ... | |
615 | (tic54x_regs): ... this. | |
616 | (mmregs): Rename to ... | |
617 | (tic54x_mmregs): ... this. | |
618 | (condition_codes): Rename to ... | |
619 | (tic54x_condition_codes): ... this. | |
620 | (cc2_codes): Rename to ... | |
621 | (tic54x_cc2_codes): ... this. | |
622 | (cc3_codes): Rename to ... | |
623 | (tic54x_cc3_codes): ... this. | |
624 | (status_bits): Rename to ... | |
625 | (tic54x_status_bits): ... this. | |
626 | (misc_symbols): Rename to ... | |
627 | (tic54x_misc_symbols): ... this. | |
628 | ||
24075dcc NC |
629 | 2021-02-04 Nelson Chu <nelson.chu@sifive.com> |
630 | ||
631 | * riscv-opc.c (MASK_RVB_IMM): Removed. | |
632 | (riscv_opcodes): Removed zb* instructions. | |
633 | (riscv_ext_version_table): Removed versions for zb*. | |
634 | ||
c3ffb8f3 AM |
635 | 2021-01-26 Alan Modra <amodra@gmail.com> |
636 | ||
637 | * i386-gen.c (parse_template): Ensure entire template_instance | |
638 | is initialised. | |
639 | ||
1942a048 NC |
640 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
641 | ||
642 | * riscv-opc.c (riscv_gpr_names_abi): Aligned the code. | |
643 | (riscv_fpr_names_abi): Likewise. | |
644 | (riscv_opcodes): Likewise. | |
645 | (riscv_insn_types): Likewise. | |
646 | ||
b800637e NC |
647 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
648 | ||
649 | * riscv-dis.c (parse_riscv_dis_option): Fix typos of message. | |
650 | ||
dcd709e0 NC |
651 | 2021-01-15 Nelson Chu <nelson.chu@sifive.com> |
652 | ||
653 | * riscv-dis.c: Comments tidy and improvement. | |
654 | * riscv-opc.c: Likewise. | |
655 | ||
5347ed60 AM |
656 | 2021-01-13 Alan Modra <amodra@gmail.com> |
657 | ||
658 | * Makefile.in: Regenerate. | |
659 | ||
d546b610 L |
660 | 2021-01-12 H.J. Lu <hongjiu.lu@intel.com> |
661 | ||
662 | PR binutils/26792 | |
663 | * configure.ac: Use GNU_MAKE_JOBSERVER. | |
664 | * aclocal.m4: Regenerated. | |
665 | * configure: Likewise. | |
666 | ||
6d104cac NC |
667 | 2021-01-12 Nick Clifton <nickc@redhat.com> |
668 | ||
669 | * po/sr.po: Updated Serbian translation. | |
670 | ||
83b33c6c L |
671 | 2021-01-11 H.J. Lu <hongjiu.lu@intel.com> |
672 | ||
673 | PR ld/27173 | |
674 | * configure: Regenerated. | |
675 | ||
82c70b08 KT |
676 | 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com> |
677 | ||
678 | * aarch64-asm-2.c: Regenerate. | |
679 | * aarch64-dis-2.c: Likewise. | |
680 | * aarch64-opc-2.c: Likewise. | |
681 | * aarch64-opc.c (aarch64_print_operand): | |
682 | Delete handling of AARCH64_OPND_CSRE_CSR. | |
683 | * aarch64-tbl.h (aarch64_feature_csre): Delete. | |
684 | (CSRE): Likewise. | |
685 | (_CSRE_INSN): Likewise. | |
686 | (aarch64_opcode_table): Delete csr. | |
687 | ||
a8aa72b9 NC |
688 | 2021-01-11 Nick Clifton <nickc@redhat.com> |
689 | ||
690 | * po/de.po: Updated German translation. | |
691 | * po/fr.po: Updated French translation. | |
692 | * po/pt_BR.po: Updated Brazilian Portuguese translation. | |
693 | * po/sv.po: Updated Swedish translation. | |
694 | * po/uk.po: Updated Ukranian translation. | |
695 | ||
a4966cd9 L |
696 | 2021-01-09 H.J. Lu <hongjiu.lu@intel.com> |
697 | ||
698 | * configure: Regenerated. | |
699 | ||
573fe3fb NC |
700 | 2021-01-09 Nick Clifton <nickc@redhat.com> |
701 | ||
702 | * configure: Regenerate. | |
703 | * po/opcodes.pot: Regenerate. | |
704 | ||
055bc77a NC |
705 | 2021-01-09 Nick Clifton <nickc@redhat.com> |
706 | ||
707 | * 2.36 release branch crated. | |
708 | ||
aae7fcb8 PB |
709 | 2021-01-08 Peter Bergner <bergner@linux.ibm.com> |
710 | ||
711 | * ppc-opc.c (insert_dw, (extract_dw): New functions. | |
712 | (DW, (XRC_MASK): Define. | |
713 | (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics. | |
714 | ||
64307045 AM |
715 | 2021-01-09 Alan Modra <amodra@gmail.com> |
716 | ||
717 | * configure: Regenerate. | |
718 | ||
ed205222 NC |
719 | 2021-01-08 Nick Clifton <nickc@redhat.com> |
720 | ||
721 | * po/sv.po: Updated Swedish translation. | |
722 | ||
fb932b57 NC |
723 | 2021-01-08 Nick Clifton <nickc@redhat.com> |
724 | ||
e84c8716 NC |
725 | PR 27129 |
726 | * aarch64-dis.c (determine_disassembling_preference): Move call to | |
727 | aarch64_match_operands_constraint outside of the assertion. | |
728 | * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert. | |
729 | Replace with a return of FALSE. | |
730 | ||
fb932b57 NC |
731 | PR 27139 |
732 | * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a | |
733 | core system register. | |
734 | ||
f4782128 ST |
735 | 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org> |
736 | ||
737 | * configure: Regenerate. | |
738 | ||
1b0927db NC |
739 | 2021-01-07 Nick Clifton <nickc@redhat.com> |
740 | ||
741 | * po/fr.po: Updated French translation. | |
742 | ||
3b288c8e FN |
743 | 2021-01-07 Fredrik Noring <noring@nocrew.org> |
744 | ||
745 | * m68k-opc.c (chkl): Change minimum architecture requirement to | |
746 | m68020. | |
747 | ||
aa881ecd PT |
748 | 2021-01-07 Philipp Tomsich <prt@gnu.org> |
749 | ||
750 | * riscv-opc.c (riscv_opcodes): Add pause hint instruction. | |
751 | ||
2652cfad CXW |
752 | 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com> |
753 | Jim Wilson <jimw@sifive.com> | |
754 | Andrew Waterman <andrew@sifive.com> | |
755 | Maxim Blinov <maxim.blinov@embecosm.com> | |
756 | Kito Cheng <kito.cheng@sifive.com> | |
757 | Nelson Chu <nelson.chu@sifive.com> | |
758 | ||
759 | * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions. | |
760 | (MASK_RVB_IMM): Used for rev8 and orc.b encoding. | |
761 | ||
250d07de AM |
762 | 2021-01-01 Alan Modra <amodra@gmail.com> |
763 | ||
764 | Update year range in copyright notice of all files. | |
765 | ||
c2795844 | 766 | For older changes see ChangeLog-2020 |
3499769a | 767 | \f |
c2795844 | 768 | Copyright (C) 2021 Free Software Foundation, Inc. |
3499769a AM |
769 | |
770 | Copying and distribution of this file, with or without modification, | |
771 | are permitted in any medium without royalty provided the copyright | |
772 | notice and this notice are preserved. | |
773 | ||
774 | Local Variables: | |
775 | mode: change-log | |
776 | left-margin: 8 | |
777 | fill-column: 74 | |
778 | version-control: never | |
779 | End: |