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c4694f17
TG		 12020-09-23 Lili Cui <lili.cui@intel.com>
2
3 * i386-dis.c (enum): Add REG_0F38D8_PREFIX_1,
4 MOD_0F38FA_PREFIX_1, MOD_0F38FB_PREFIX_1,
5 MOD_0F38DC_PREFIX_1, MOD_0F38DD_PREFIX_1,
6 MOD_0F38DE_PREFIX_1, MOD_0F38DF_PREFIX_1,
7 PREFIX_0F38D8, PREFIX_0F38FA, PREFIX_0F38FB.
8 (reg_table): New instructions (see prefixes above).
9 (prefix_table): Likewise.
10 (three_byte_table): Likewise.
11 (mod_table): Likewise
12 * i386-gen.c (cpu_flag_init): Add CPU_KL_FLAGS, CPU_WIDE_KL_FLAGS,
13 CPU_ANY_KL_FLAGS and CPU_ANY_WIDE_KL_FLAGS.
14 (cpu_flags): Likewise.
15 (operand_type_init): Likewise.
16 * i386-opc.h (enum): Add CpuKL and CpuWide_KL.
17 (i386_cpu_flags): Add cpukl and cpuwide_kl.
18 * i386-opc.tbl: Add KL and WIDE_KL insns.
19 * i386-init.h: Regenerate.
20 * i386-tbl.h: Likewise.
21
c73eac96
AM		 222020-09-21 Alan Modra <amodra@gmail.com>
23
24 * rx-dis.c (flag_names): Add missing comma.
25 (register_names, flag_names, double_register_names),
26 (double_register_high_names, double_register_low_names),
27 (double_control_register_names, double_condition_names): Remove
28 trailing commas.
29
6e25f888
DF		 302020-09-18 David Faust <david.faust@oracle.com>
31
32 * bpf-desc.c: Regenerate.
33 * bpf-desc.h: Likewise.
34 * bpf-opc.c: Likewise.
35 * bpf-opc.h: Likewise.
36
c568ac5f
AB		 372020-09-16 Andrew Burgess <andrew.burgess@embecosm.com>
38
39 * csky-dis.c (csky_get_disassembler): Don't return NULL when there
40 is no BFD.
41
c1229f84
AM		 422020-09-16 Alan Modra <amodra@gmail.com>
43
44 * ppc-dis.c (ppc_symbol_is_valid): Adjust elf_symbol_from invocation.
45
7ad57880
NC		 462020-09-10 Nick Clifton <nickc@redhat.com>
47
48 * ppc-dis.c (ppc_symbol_is_valid): New function. Returns false
49 for hidden, local, no-type symbols.
50 (disassemble_init_powerpc): Point the symbol_is_valid field in the
51 info structure at the new function.
52
79c8d443
CQ		 532020-09-10 Cooper Qu <cooper.qu@linux.alibaba.com>
54
55 * csky-opc.h (csky_v2_opcodes): Add L2Cache instructions.
56 * testsuite/gas/csky/cskyv2_ck860.d : Adjust to icache.iva
57 opcode fixing.
58
0332f662
NC		 592020-09-10 Nick Clifton <nickc@redhat.com>
60
61 * csky-dis.c (csky_output_operand): Coerce the immediate values to
62 long before printing.
63
23bef3fe
AM		 642020-09-10 Alan Modra <amodra@gmail.com>
65
66 * csky-dis.c (csky_output_operand): Don't sprintf str to itself.
67
6a1ed910
CQ		 682020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
69
70 * csky-opc.h (csky_v2_opcodes): Change mvtc and mulsw's
71 ISA flag.
72
1feede9b
CQ		 732020-09-07 Cooper Qu <cooper.qu@linux.alibaba.com>
74
75 * csky-dis.c (csky_output_operand): Add handlers for
76 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
77 OPRND_TYPE_DFLOAT_FMOVI. Refine OPRND_TYPE_FREGLIST_DASH
78 to support FPUV3 instructions.
79 * csky-opc.h (enum operand_type): New enum OPRND_TYPE_IMM9b,
80 OPRND_TYPE_HFLOAT_FMOVI, OPRND_TYPE_SFLOAT_FMOVI and
81 OPRND_TYPE_DFLOAT_FMOVI.
82 (OPRND_MASK_4_5, OPRND_MASK_6, OPRND_MASK_6_7, OPRND_MASK_6_8,
83 OPRND_MASK_7, OPRND_MASK_7_8, OPRND_MASK_17_24,
84 OPRND_MASK_20, OPRND_MASK_20_21, OPRND_MASK_20_22,
85 OPRND_MASK_20_23, OPRND_MASK_20_24, OPRND_MASK_20_25,
86 OPRND_MASK_0_3or5_8, OPRND_MASK_0_3or6_7, OPRND_MASK_0_3or25,
87 OPRND_MASK_0_4or21_24, OPRND_MASK_5or20_21,
88 OPRND_MASK_5or20_22, OPRND_MASK_5or20_23, OPRND_MASK_5or20_24,
89 OPRND_MASK_5or20_25, OPRND_MASK_8_9or21_25,
90 OPRND_MASK_8_9or16_25, OPRND_MASK_4_6or20, OPRND_MASK_5_7or20,
91 OPRND_MASK_4_5or20or25, OPRND_MASK_4_6or20or25,
92 OPRND_MASK_4_7or20or25, OPRND_MASK_6_9or17_24,
93 OPRND_MASK_6_7or20, OPRND_MASK_6or20, OPRND_MASK_7or20,
94 OPRND_MASK_5or8_9or16_25, OPRND_MASK_5or8_9or20_25): Define.
95 (csky_v2_opcodes): Add FPUV3 instructions.
96
38cf07a6
AC		 972020-09-08 Alex Coplan <alex.coplan@arm.com>
98
99 * aarch64-dis.c (print_operands): Pass CPU features to
100 aarch64_print_operand().
101 * aarch64-opc.c (aarch64_print_operand): Use CPU features to determine
102 preferred disassembly of system registers.
103 (SR_RNG): Refactor to use new SR_FEAT2 macro.
104 (SR_FEAT2): New.
105 (SR_V8_1_A): New.
106 (SR_V8_4_A): New.
107 (SR_V8_A): New.
108 (SR_V8_R): New.
109 (SR_EXPAND_ELx): New.
110 (SR_EXPAND_EL12): New.
111 (aarch64_sys_regs): Specify which registers are only on
112 A-profile, add R-profile system registers.
113 (ENC_BARLAR): New.
114 (PRBARn_ELx): New.
115 (PRLARn_ELx): New.
116 (aarch64_sys_ins_reg_supported_p): Reject EL3 registers for
117 Armv8-R AArch64.
118
03fb3142
AC		 1192020-09-08 Alex Coplan <alex.coplan@arm.com>
120
121 * aarch64-tbl.h (aarch64_feature_v8_r): New.
122 (ARMV8_R): New.
123 (V8_R_INSN): New.
124 (aarch64_opcode_table): Add dfb.
125 * aarch64-opc-2.c: Regenerate.
126 * aarch64-asm-2.c: Regenerate.
127 * aarch64-dis-2.c: Regenerate.
128
95830c98
AC		 1292020-09-08 Alex Coplan <alex.coplan@arm.com>
130
131 * aarch64-dis.c (arch_variant): New.
132 (determine_disassembling_preference): Disassemble according to
133 arch variant.
134 (select_aarch64_variant): New.
135 (print_insn_aarch64): Set feature set.
136
7c80dd4c
AM		 1372020-09-02 Alan Modra <amodra@gmail.com>
138
139 * v850-opc.c (insert_i5div1, insert_i5div2, insert_i5div3),
140 (insert_d5_4, insert_d8_6, insert_d8_7, insert_v8, insert_d9),
141 (insert_u16_loop, insert_d16_15, insert_d16_16, insert_d17_16),
142 (insert_d22, insert_d23, insert_d23_align1, insert_i9, insert_u9),
143 (insert_spe, insert_r4, insert_POS, insert_WIDTH, insert_SELID),
144 (insert_VECTOR8, insert_VECTOR5, insert_CACHEOP, insert_PREFOP),
145 (nsert_IMM10U, insert_SRSEL1, insert_SRSEL2): Use unsigned long
146 for value parameter and update code to suit.
147 (extract_d9, extract_d16_15, extract_d16_16, extract_d17_16),
148 (extract_d22, extract_d23, extract_i9): Use unsigned long variables.
149
b4b39349
AM		 1502020-09-02 Alan Modra <amodra@gmail.com>
151
152 * i386-dis.c (OP_E_memory): Don't cast to signed type when
153 negating.
154 (get32, get32s): Use unsigned types in shift expressions.
155
caf4537a
AM		 1562020-09-02 Alan Modra <amodra@gmail.com>
157
158 * csky-dis.c (print_insn_csky): Use unsigned type for "given".
159
3c5097ea
AM		 1602020-09-02 Alan Modra <amodra@gmail.com>
161
162 * crx-dis.c: Whitespace.
163 (print_arg): Use unsigned type for longdisp and mask variables,
164 and for left shift constant.
165
ae3e98b4
AM		 1662020-09-02 Alan Modra <amodra@gmail.com>
167
168 * cgen-ibld.in (insert_normal, extract_normal): Use 1UL in left shift.
169 * bpf-ibld.c: Regenerate.
170 * epiphany-ibld.c: Regenerate.
171 * fr30-ibld.c: Regenerate.
172 * frv-ibld.c: Regenerate.
173 * ip2k-ibld.c: Regenerate.
174 * iq2000-ibld.c: Regenerate.
175 * lm32-ibld.c: Regenerate.
176 * m32c-ibld.c: Regenerate.
177 * m32r-ibld.c: Regenerate.
178 * mep-ibld.c: Regenerate.
179 * mt-ibld.c: Regenerate.
180 * or1k-ibld.c: Regenerate.
181 * xc16x-ibld.c: Regenerate.
182 * xstormy16-ibld.c: Regenerate.
183
427202d9
AM		 1842020-09-02 Alan Modra <amodra@gmail.com>
185
186 * bfin-dis.c (MASKBITS): Use SIGNBIT.
187
4211a340
CQ		 1882020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
189
190 * csky-opc.h (csky_v2_opcodes): Move divul and divsl
191 to CSKYV2_ISA_3E3R3 instruction set.
192
8119cc38
CQ		 1932020-09-02 Cooper Qu <cooper.qu@linux.alibaba.com>
194
195 * csky-opc.h (csky_v2_opcodes): Fix Encode of mulsws.
196
8dbe96f0
AM		 1972020-09-01 Alan Modra <amodra@gmail.com>
198
199 * mep-ibld.c: Regenerate.
200
e2e82b11
CQ		 2012020-08-31 Cooper Qu <cooper.qu@linux.alibaba.com>
202
203 * csky-dis.c (csky_output_operand): Assign dis_info.value for
204 OPRND_TYPE_VREG.
205
2781f857
AM		 2062020-08-30 Alan Modra <amodra@gmail.com>
207
208 * cr16-dis.c: Formatting.
209 (parameter): Delete struct typedef. Use dwordU instead
210 throughout file.
211 (make_argument <arg_idxr>): Simplify detection of cbitb, sbitb
212 and tbitb.
213 (make_argument <arg_cr>): Extract 20-bit field not 16-bit.
214
0c0577f6
AM		 2152020-08-29 Alan Modra <amodra@gmail.com>
216
217 PR 26446
218 * csky-opc.h (MAX_OPRND_NUM): Define to 5.
219 (union csky_operand): Use MAX_OPRND_NUM to size oprnds array.
220
a1e60a1b
AM		 2212020-08-28 Alan Modra <amodra@gmail.com>
222
223 PR 26449
224 PR 26450
225 * cgen-ibld.in (insert_1): Use 1UL in forming mask.
226 (extract_normal): Likewise.
227 (insert_normal): Likewise, and move past zero length test.
228 (put_insn_int_value): Handle mask for zero length, use 1UL.
229 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
230 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
231 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
232 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
233
0861f561
CQ		 2342020-08-28 Cooper Qu <cooper.qu@linux.alibaba.com>
235
236 * csky-dis.c (CSKY_DEFAULT_ISA): Define.
237 (csky_dis_info): Add member isa.
238 (csky_find_inst_info): Skip instructions that do not belong to
239 current CPU.
240 (csky_get_disassembler): Get infomation from attribute section.
241 (print_insn_csky): Set defualt ISA flag.
242 * csky.h (CSKY_ISA_VDSP_2): Rename from CSKY_ISA_VDSP_V2.
243 * csky-opc.h (struct csky_opcode): Change isa_flag16 and
244 isa_flag32'type to unsigned 64 bits.
245
31b3f3e6
JM		 2462020-08-26 Jose E. Marchesi <jemarch@gnu.org>
247
248 * disassemble.c (enum epbf_isa_attr): Add ISA_XBPFBE, ISA_EBPFMAX.
249
4449c81a
DF		 2502020-08-26 David Faust <david.faust@oracle.com>
251
252 * bpf-desc.c: Regenerate.
253 * bpf-desc.h: Likewise.
254 * bpf-opc.c: Likewise.
255 * bpf-opc.h: Likewise.
256 * disassemble.c (disassemble_init_for_target): Set bits for xBPF
257 ISA when appropriate.
258
8640c87d
AM		 2592020-08-25 Alan Modra <amodra@gmail.com>
260
261 PR 26504
262 * vax-dis.c (parse_disassembler_options): Always add at least one
263 to entry_addr_total_slots.
264
531c73a3
CQ		 2652020-08-24 Cooper Qu <cooper.qu@linux.alibaba.com>
266
267 * csky-dis.c (csky_find_inst_info): Skip CK860's instructions
268 in other CPUs to speed up disassembling.
269 * csky-opc.h (csky_v2_opcodes): Add CK860's instructions,
270 Change plsli.u16 to plsli.16, change sync's operand format.
271
d04aee0f
CQ		 2722020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
273
274 * csky-opc.h (csky_v2_opcodes): Add instruction bnezad.
275
ccf61261
NC		 2762020-08-21 Nick Clifton <nickc@redhat.com>
277
278 * aarch64-dis.c (get_sym_code_type): Return FALSE for non-ELF
279 symbols.
280
d285ba8d
CQ		 2812020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
282
283 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
284
18a8a00e
AM		 2852020-08-19 Alan Modra <amodra@gmail.com>
286
287 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
288 vcmpuq and xvtlsbb.
289
587a4371
PB		 2902020-08-18 Peter Bergner <bergner@linux.ibm.com>
291
292 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
293 <xvcvbf16spn>: ...to this.
294
2e49fd1e
AC		 2952020-08-12 Alex Coplan <alex.coplan@arm.com>
296
297 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
298
79ddc884
NC		 2992020-08-12 Nick Clifton <nickc@redhat.com>
300
301 * po/sr.po: Updated Serbian translation.
302
08770ec2
AM		 3032020-08-11 Alan Modra <amodra@gmail.com>
304
305 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
306
f7cb161e
PW		 3072020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
308
309 * aarch64-opc.c (aarch64_print_operand):
310 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
311 (aarch64_sys_reg_supported_p): Function removed.
312 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
313 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
314 into this function.
315
3eb65174
AM		 3162020-08-10 Alan Modra <amodra@gmail.com>
317
318 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
319 instructions.
320
8b2742a1
AM		 3212020-08-10 Alan Modra <amodra@gmail.com>
322
323 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
324 Enable icbt for power5, miso for power8.
325
5fbec329
AM		 3262020-08-10 Alan Modra <amodra@gmail.com>
327
328 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
329 mtvsrd, and similarly for mfvsrd.
330
563a3225
CG		 3312020-08-04 Christian Groessler <chris@groessler.org>
332 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
333
334 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
335 opcodes (special "out" to absolute address).
336 * z8k-opc.h: Regenerate.
337
41eb8e88
L		 3382020-07-30 H.J. Lu <hongjiu.lu@intel.com>
339
340 PR gas/26305
341 * i386-opc.h (Prefix_Disp8): New.
342 (Prefix_Disp16): Likewise.
343 (Prefix_Disp32): Likewise.
344 (Prefix_Load): Likewise.
345 (Prefix_Store): Likewise.
346 (Prefix_VEX): Likewise.
347 (Prefix_VEX3): Likewise.
348 (Prefix_EVEX): Likewise.
349 (Prefix_REX): Likewise.
350 (Prefix_NoOptimize): Likewise.
351 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
352 * i386-tbl.h: Regenerated.
353
98116973
AA		 3542020-07-29 Andreas Arnez <arnez@linux.ibm.com>
355
356 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
357 default case with abort() instead of printing an error message and
358 continuing, to avoid a maybe-uninitialized warning.
359
2dddfa20
NC		 3602020-07-24 Nick Clifton <nickc@redhat.com>
361
362 * po/de.po: Updated German translation.
363
bf4ba07c
JB		 3642020-07-21 Jan Beulich <jbeulich@suse.com>
365
366 * i386-dis.c (OP_E_memory): Revert previous change.
367
04c662e2
L		 3682020-07-15 H.J. Lu <hongjiu.lu@intel.com>
369
370 PR gas/26237
371 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
372 without base nor index registers.
373
f0e8d0ba
JB		 3742020-07-15 Jan Beulich <jbeulich@suse.com>
375
376 * i386-dis.c (putop): Move 'V' and 'W' handling.
377
c3f5525f
JB		 3782020-07-15 Jan Beulich <jbeulich@suse.com>
379
380 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
381 construct for push/pop of register.
382 (putop): Honor cond when handling 'P'. Drop handling of plain
383 'V'.
384
36938cab
JB		 3852020-07-15 Jan Beulich <jbeulich@suse.com>
386
387 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
388 description. Drop '&' description. Use P for push of immediate,
389 pushf/popf, enter, and leave. Use %LP for lret/retf.
390 (dis386_twobyte): Use P for push/pop of fs/gs.
391 (reg_table): Use P for push/pop. Use @ for near call/jmp.
392 (x86_64_table): Use P for far call/jmp.
393 (putop): Drop handling of 'U' and '&'. Move and adjust handling
394 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
395 labels.
396 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
397 and dqw_mode (unconditional).
398
8e58ef80
L		 3992020-07-14 H.J. Lu <hongjiu.lu@intel.com>
400
401 PR gas/26237
402 * i386-dis.c (OP_E_memory): Without base nor index registers,
403 32-bit displacement to 64 bits.
404
570b0ed6
CZ		 4052020-07-14 Claudiu Zissulescu <claziss@gmail.com>
406
407 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
408 faulty double register pair is detected.
409
bfbd9438
JB		 4102020-07-14 Jan Beulich <jbeulich@suse.com>
411
412 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
413
78467458
JB		 4142020-07-14 Jan Beulich <jbeulich@suse.com>
415
416 * i386-dis.c (OP_R, Rm): Delete.
417 (MOD_0F24, MOD_0F26): Rename to ...
418 (X86_64_0F24, X86_64_0F26): ... respectively.
419 (dis386): Update 'L' and 'Z' comments.
420 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
421 table references.
422 (mod_table): Move opcode 0F24 and 0F26 entries ...
423 (x86_64_table): ... here.
424 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
425 'Z' case block.
426
464d2b65
JB		 4272020-07-14 Jan Beulich <jbeulich@suse.com>
428
429 * i386-dis.c (Rd, Rdq, MaskR): Delete.
430 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
431 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
432 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
433 MOD_EVEX_0F387C): New enumerators.
434 (reg_table): Use Edq for rdssp.
435 (prefix_table): Use Edq for incssp.
436 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
437 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
438 ktest*, and kshift*. Use Edq / MaskE for kmov*.
439 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
440 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
441 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
442 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
443 0F3828_P_1 and 0F3838_P_1.
444 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
445 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
446
035e7389
JB		 4472020-07-14 Jan Beulich <jbeulich@suse.com>
448
449 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
450 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
451 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
452 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
453 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
454 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
455 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
456 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
457 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
458 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
459 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
460 (reg_table, prefix_table, three_byte_table, vex_table,
461 vex_len_table, mod_table, rm_table): Replace / remove respective
462 entries.
463 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
464 of PREFIX_DATA in used_prefixes.
465
bb5b3501
JB		 4662020-07-14 Jan Beulich <jbeulich@suse.com>
467
468 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
469 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
470 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
471 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
472 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
473 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
474 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
475 VEX_W_0F3A33_L_0): Delete.
476 (dis386): Adjust "BW" description.
477 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
478 0F3A31, 0F3A32, and 0F3A33.
479 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
480 entries.
481 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
482 entries.
483
7531c613
JB		 4842020-07-14 Jan Beulich <jbeulich@suse.com>
485
486 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
487 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
488 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
489 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
490 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
491 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
492 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
493 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
494 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
495 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
496 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
497 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
498 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
499 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
500 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
501 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
502 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
503 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
504 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
505 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
506 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
507 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
508 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
509 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
510 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
511 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
512 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
513 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
514 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
515 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
516 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
517 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
518 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
519 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
520 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
521 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
522 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
523 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
524 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
525 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
526 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
527 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
528 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
529 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
530 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
531 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
532 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
533 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
534 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
535 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
536 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
537 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
538 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
539 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
540 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
541 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
542 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
543 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
544 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
545 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
546 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
547 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
548 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
549 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
550 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
551 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
552 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
553 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
554 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
555 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
556 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
557 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
558 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
559 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
560 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
561 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
562 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
563 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
564 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
565 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
566 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
567 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
568 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
569 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
570 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
571 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
572 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
573 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
574 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
575 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
576 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
577 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
578 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
579 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
580 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
581 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
582 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
583 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
584 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
585 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
586 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
587 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
588 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
589 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
590 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
591 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
592 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
593 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
594 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
595 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
596 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
597 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
598 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
599 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
600 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
601 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
602 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
603 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
604 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
605 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
606 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
607 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
608 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
609 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
610 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
611 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
612 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
613 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
614 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
615 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
616 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
617 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
618 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
619 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
620 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
621 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
622 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
623 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
624 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
625 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
626 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
627 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
628 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
629 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
630 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
631 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
632 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
633 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
634 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
635 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
636 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
637 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
638 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
639 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
640 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
641 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
642 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
643 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
644 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
645 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
646 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
647 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
648 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
649 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
650 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
651 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
652 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
653 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
654 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
655 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
656 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
657 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
658 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
659 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
660 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
661 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
662 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
663 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
664 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
665 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
666 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
667 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
668 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
669 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
670 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
671 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
672 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
673 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
674 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
675 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
676 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
677 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
678 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
679 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
680 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
681 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
682 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
683 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
684 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
685 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
686 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
687 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
688 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
689 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
690 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
691 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
692 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
693 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
694 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
695 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
696 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
697 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
698 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
699 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
700 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
701 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
702 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
703 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
704 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
705 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
706 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
707 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
708 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
709 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
710 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
711 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
712 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
713 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
714 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
715 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
716 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
717 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
718 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
719 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
720 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
721 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
722 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
723 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
724 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
725 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
726 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
727 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
728 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
729 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
730 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
731 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
732 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
733 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
734 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
735 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
736 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
737 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
738 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
739 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
740 EVEX_W_0F3A72_P_2): Rename to ...
741 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
742 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
743 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
744 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
745 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
746 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
747 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
748 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
749 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
750 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
751 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
752 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
753 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
754 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
755 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
756 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
757 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
758 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
759 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
760 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
761 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
762 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
763 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
764 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
765 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
766 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
767 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
768 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
769 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
770 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
771 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
772 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
773 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
774 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
775 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
776 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
777 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
778 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
779 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
780 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
781 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
782 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
783 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
784 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
785 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
786 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
787 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
788 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
789 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
790 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
791 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
792 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
793 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
794 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
795 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
796 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
797 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
798 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
799 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
800 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
801 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
802 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
803 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
804 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
805 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
806 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
807 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
808 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
809 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
810 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
811 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
812 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
813 respectively.
814 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
815 vex_w_table, mod_table): Replace / remove respective entries.
816 (print_insn): Move up dp->prefix_requirement handling. Handle
817 PREFIX_DATA.
818 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
819 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
820 Replace / remove respective entries.
821
17d3c7ec
JB		 8222020-07-14 Jan Beulich <jbeulich@suse.com>
823
824 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
825 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
826 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
827 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
828 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
829 the latter two.
830 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
831 0F2C, 0F2D, 0F2E, and 0F2F.
832 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
833 0F2F table entries.
834
41f5efc6
JB		 8352020-07-14 Jan Beulich <jbeulich@suse.com>
836
837 * i386-dis.c (OP_VexR, VexScalarR): New.
838 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
839 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
840 need_vex_reg): Delete.
841 (prefix_table): Replace VexScalar by VexScalarR and
842 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
843 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
844 (vex_len_table): Replace EXqVexScalarS by EXqS.
845 (get_valid_dis386): Don't set need_vex_reg.
846 (print_insn): Don't initialize need_vex_reg.
847 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
848 q_scalar_swap_mode cases.
849 (OP_EX): Don't check for d_scalar_swap_mode and
850 q_scalar_swap_mode.
851 (OP_VEX): Done check need_vex_reg.
852 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
853 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
854 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
855
89e65d17
JB		 8562020-07-14 Jan Beulich <jbeulich@suse.com>
857
858 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
859 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
860 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
861 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
862 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
863 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
864 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
865 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
866 (vex_table): Replace Vex128 by Vex.
867 (vex_len_table): Likewise. Adjust referenced enum names.
868 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
869 referenced enum names.
870 (OP_VEX): Drop vex128_mode and vex256_mode cases.
871 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
872
492a76aa
JB		 8732020-07-14 Jan Beulich <jbeulich@suse.com>
874
875 * i386-dis.c (dis386): "LW" description now applies to "DQ".
876 (putop): Handle "DQ". Don't handle "LW" anymore.
877 (prefix_table, mod_table): Replace %LW by %DQ.
878 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
879
059edf8b
JB		 8802020-07-14 Jan Beulich <jbeulich@suse.com>
881
882 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
883 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
884 d_scalar_swap_mode case handling. Move shift adjsutment into
885 the case its applicable to.
886
4726e9a4
JB		 8872020-07-14 Jan Beulich <jbeulich@suse.com>
888
889 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
890 (EXbScalar, EXwScalar): Fold to ...
891 (EXbwUnit): ... this.
892 (b_scalar_mode, w_scalar_mode): Fold to ...
893 (bw_unit_mode): ... this.
894 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
895 w_scalar_mode handling by bw_unit_mode one.
896 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
897 ...
898 * i386-dis-evex-prefix.h: ... here.
899
b24d668c
JB		 9002020-07-14 Jan Beulich <jbeulich@suse.com>
901
902 * i386-dis.c (PCMPESTR_Fixup): Delete.
903 (dis386): Adjust "LQ" description.
904 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
905 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
906 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
907 vpcmpestrm, and vpcmpestri.
908 (putop): Honor "cond" when handling LQ.
909 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
910 vcvtsi2ss and vcvtusi2ss.
911 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
912 vcvtsi2sd and vcvtusi2sd.
913
c4de7606
JB		 9142020-07-14 Jan Beulich <jbeulich@suse.com>
915
916 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
917 (simd_cmp_op): Add const.
918 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
919 (CMP_Fixup): Handle VEX case.
920 (prefix_table): Replace VCMP by CMP.
921 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
922
9ab00b61
JB		 9232020-07-14 Jan Beulich <jbeulich@suse.com>
924
925 * i386-dis.c (MOVBE_Fixup): Delete.
926 (Mv): Define.
927 (prefix_table): Use Mv for movbe entries.
928
2875b28a
JB		 9292020-07-14 Jan Beulich <jbeulich@suse.com>
930
931 * i386-dis.c (CRC32_Fixup): Delete.
932 (prefix_table): Use Eb/Ev for crc32 entries.
933
e184e611
JB		 9342020-07-14 Jan Beulich <jbeulich@suse.com>
935
936 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
937 Conditionalize invocations of "USED_REX (0)".
938
e8b5d5f9
JB		 9392020-07-14 Jan Beulich <jbeulich@suse.com>
940
941 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
942 CH, DH, BH, AX, DX): Delete.
943 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
944 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
945 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
946
260cd341
LC		 9472020-07-10 Lili Cui <lili.cui@intel.com>
948
949 * i386-dis.c (TMM): New.
950 (EXtmm): Likewise.
951 (VexTmm): Likewise.
952 (MVexSIBMEM): Likewise.
953 (tmm_mode): Likewise.
954 (vex_sibmem_mode): Likewise.
955 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
956 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
957 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
958 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
959 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
960 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
961 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
962 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
963 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
964 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
965 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
966 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
967 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
968 (PREFIX_VEX_0F3849_X86_64): Likewise.
969 (PREFIX_VEX_0F384B_X86_64): Likewise.
970 (PREFIX_VEX_0F385C_X86_64): Likewise.
971 (PREFIX_VEX_0F385E_X86_64): Likewise.
972 (X86_64_VEX_0F3849): Likewise.
973 (X86_64_VEX_0F384B): Likewise.
974 (X86_64_VEX_0F385C): Likewise.
975 (X86_64_VEX_0F385E): Likewise.
976 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
977 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
978 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
979 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
980 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
981 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
982 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
983 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
984 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
985 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
986 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
987 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
988 (VEX_W_0F3849_X86_64_P_0): Likewise.
989 (VEX_W_0F3849_X86_64_P_2): Likewise.
990 (VEX_W_0F3849_X86_64_P_3): Likewise.
991 (VEX_W_0F384B_X86_64_P_1): Likewise.
992 (VEX_W_0F384B_X86_64_P_2): Likewise.
993 (VEX_W_0F384B_X86_64_P_3): Likewise.
994 (VEX_W_0F385C_X86_64_P_1): Likewise.
995 (VEX_W_0F385E_X86_64_P_0): Likewise.
996 (VEX_W_0F385E_X86_64_P_1): Likewise.
997 (VEX_W_0F385E_X86_64_P_2): Likewise.
998 (VEX_W_0F385E_X86_64_P_3): Likewise.
999 (names_tmm): Likewise.
1000 (att_names_tmm): Likewise.
1001 (intel_operand_size): Handle void_mode.
1002 (OP_XMM): Handle tmm_mode.
1003 (OP_EX): Likewise.
1004 (OP_VEX): Likewise.
1005 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
1006 CpuAMX_BF16 and CpuAMX_TILE.
1007 (operand_type_shorthands): Add RegTMM.
1008 (operand_type_init): Likewise.
1009 (operand_types): Add Tmmword.
1010 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1011 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
1012 * i386-opc.h (CpuAMX_INT8): New.
1013 (CpuAMX_BF16): Likewise.
1014 (CpuAMX_TILE): Likewise.
1015 (SIBMEM): Likewise.
1016 (Tmmword): Likewise.
1017 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
1018 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
1019 (i386_operand_type): Add tmmword.
1020 * i386-opc.tbl: Add AMX instructions.
1021 * i386-reg.tbl: Add AMX registers.
1022 * i386-init.h: Regenerated.
1023 * i386-tbl.h: Likewise.
1024
467bbef0
JB		 10252020-07-08 Jan Beulich <jbeulich@suse.com>
1026
1027 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
1028 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
1029 Rename to ...
1030 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
1031 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
1032 respectively.
1033 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
1034 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
1035 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
1036 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
1037 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
1038 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
1039 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
1040 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
1041 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
1042 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
1043 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
1044 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
1045 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
1046 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
1047 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
1048 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
1049 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
1050 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
1051 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
1052 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
1053 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
1054 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
1055 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
1056 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
1057 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
1058 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
1059 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
1060 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
1061 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
1062 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
1063 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
1064 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
1065 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
1066 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
1067 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
1068 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
1069 (reg_table): Re-order XOP entries. Adjust their operands.
1070 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
1071 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
1072 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
1073 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
1074 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
1075 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
1076 entries by references ...
1077 (vex_len_table): ... to resepctive new entries here. For several
1078 new and existing entries reference ...
1079 (vex_w_table): ... new entries here.
1080 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
1081
6384fd9e
JB		 10822020-07-08 Jan Beulich <jbeulich@suse.com>
1083
1084 * i386-dis.c (XMVexScalarI4): Define.
1085 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
1086 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
1087 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
1088 (vex_len_table): Move scalar FMA4 entries ...
1089 (prefix_table): ... here.
1090 (OP_REG_VexI4): Handle scalar_mode.
1091 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
1092 * i386-tbl.h: Re-generate.
1093
e6123d0c
JB		 10942020-07-08 Jan Beulich <jbeulich@suse.com>
1095
1096 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
1097 Vex_2src_2): Delete.
1098 (OP_VexW, VexW): New.
1099 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
1100 for shifts and rotates by register.
1101
93abb146
JB		 11022020-07-08 Jan Beulich <jbeulich@suse.com>
1103
1104 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
1105 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
1106 OP_EX_VexReg): Delete.
1107 (OP_VexI4, VexI4): New.
1108 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
1109 (prefix_table): ... here.
1110 (print_insn): Drop setting of vex_w_done.
1111
b13b1bc0
JB		 11122020-07-08 Jan Beulich <jbeulich@suse.com>
1113
1114 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
1115 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
1116 (xop_table): Replace operands of 4-operand insns.
1117 (OP_REG_VexI4): Move VEX.W based operand swaping here.
1118
f337259f
CZ		 11192020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
1120
1121 * arc-opc.c (insert_rbd): New function.
1122 (RBD): Define.
1123 (RBDdup): Likewise.
1124 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
1125 instructions.
1126
931452b6
JB		 11272020-07-07 Jan Beulich <jbeulich@suse.com>
1128
1129 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
1130 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
1131 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
1132 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
1133 Delete.
1134 (putop): Handle "BW".
1135 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
1136 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
1137 and 0F3A3F ...
1138 * i386-dis-evex-prefix.h: ... here.
1139
b5b098c2
JB		 11402020-07-06 Jan Beulich <jbeulich@suse.com>
1141
1142 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
1143 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
1144 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
1145 VEX_W_0FXOP_09_83): New enumerators.
1146 (xop_table): Reference the above.
1147 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
1148 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
1149 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
1150 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
1151
21a3faeb
JB		 11522020-07-06 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-dis.c (EVEX_W_0F3838_P_1,
1155 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
1156 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
1157 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
1158 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
1159 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
1160 (putop): Centralize management of last[]. Delete SAVE_LAST.
1161 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
1162 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
1163 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
1164 * i386-dis-evex-prefix.h: here.
1165
bc152a17
JB		 11662020-07-06 Jan Beulich <jbeulich@suse.com>
1167
1168 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
1169 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
1170 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
1171 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
1172 enumerators.
1173 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
1174 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
1175 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
1176 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
1177 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
1178 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
1179 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
1180 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
1181 these, respectively.
1182 * i386-dis-evex-len.h: Adjust comments.
1183 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
1184 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
1185 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
1186 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
1187 MOD_EVEX_0F385B_P_2_W_1 table entries.
1188 * i386-dis-evex-w.h: Reference mod_table[] for
1189 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
1190 EVEX_W_0F385B_P_2.
1191
c82a99a0
JB		 11922020-07-06 Jan Beulich <jbeulich@suse.com>
1193
1194 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
1195 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
1196 EXymm.
1197 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
1198 Likewise. Mark 256-bit entries invalid.
1199
fedfb81e
JB		 12002020-07-06 Jan Beulich <jbeulich@suse.com>
1201
1202 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1203 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1204 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1205 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1206 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1207 PREFIX_EVEX_0F382B): Delete.
1208 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
1209 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
1210 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
1211 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
1212 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
1213 to ...
1214 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
1215 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
1216 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
1217 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
1218 respectively.
1219 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
1220 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
1221 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1222 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
1223 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
1224 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
1225 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
1226 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
1227 PREFIX_EVEX_0F382B): Remove table entries.
1228 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
1229 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
1230 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
1231
3a57774c
JB		 12322020-07-06 Jan Beulich <jbeulich@suse.com>
1233
1234 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
1235 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
1236 enumerators.
1237 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
1238 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
1239 EVEX_LEN_0F3A01_P_2_W_1 table entries.
1240 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1241 entries.
1242
e74d9fa9
JB		 12432020-07-06 Jan Beulich <jbeulich@suse.com>
1244
1245 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
1246 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
1247 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1248 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
1249 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
1250 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
1251 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
1252 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
1253 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
1254 entries.
1255
6431c801
JB		 12562020-07-06 Jan Beulich <jbeulich@suse.com>
1257
1258 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
1259 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
1260 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
1261 respectively.
1262 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
1263 entries.
1264 * i386-dis-evex.h (evex_table): Reference VEX table entry for
1265 opcode 0F3A1D.
1266 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
1267 entry.
1268 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
1269
6df22cf6
JB		 12702020-07-06 Jan Beulich <jbeulich@suse.com>
1271
1272 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1273 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1274 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1275 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1276 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1277 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1278 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1279 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1280 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1281 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1282 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1283 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1284 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1285 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1286 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1287 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1288 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1289 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1290 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1291 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1292 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1293 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1294 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1295 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1296 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1297 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1298 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1299 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1300 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1301 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1302 (prefix_table): Add EXxEVexR to FMA table entries.
1303 (OP_Rounding): Move abort() invocation.
1304 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1305 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1306 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1307 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1308 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1309 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1310 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1311 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1312 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1313 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1314 0F3ACE, 0F3ACF.
1315 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1316 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1317 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1318 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1319 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1320 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1321 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1322 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1323 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1324 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1325 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1326 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1327 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1328 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1329 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1330 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1331 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1332 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1333 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1334 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1335 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1336 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1337 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1338 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1339 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1340 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1341 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1342 Delete table entries.
1343 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1344 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1345 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1346 Likewise.
1347
39e0f456
JB		 13482020-07-06 Jan Beulich <jbeulich@suse.com>
1349
1350 * i386-dis.c (EXqScalarS): Delete.
1351 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1352 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1353
5b872f7d
JB		 13542020-07-06 Jan Beulich <jbeulich@suse.com>
1355
1356 * i386-dis.c (safe-ctype.h): Include.
1357 (EXdScalar, EXqScalar): Delete.
1358 (d_scalar_mode, q_scalar_mode): Delete.
1359 (prefix_table, vex_len_table): Use EXxmm_md in place of
1360 EXdScalar and EXxmm_mq in place of EXqScalar.
1361 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1362 d_scalar_mode and q_scalar_mode.
1363 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1364 (vmovsd): Use EXxmm_mq.
1365
ddc73fa9
NC		 13662020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1367
1368 PR 26204
1369 * arc-dis.c: Fix spelling mistake.
1370 * po/opcodes.pot: Regenerate.
1371
17550be7
NC		 13722020-07-06 Nick Clifton <nickc@redhat.com>
1373
1374 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1375 * po/uk.po: Updated Ukranian translation.
1376
b19d852d
NC		 13772020-07-04 Nick Clifton <nickc@redhat.com>
1378
1379 * configure: Regenerate.
1380 * po/opcodes.pot: Regenerate.
1381
b115b9fd
NC		 13822020-07-04 Nick Clifton <nickc@redhat.com>
1383
1384 Binutils 2.35 branch created.
1385
c2ecccb3
L		 13862020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1387
1388 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1389 * i386-opc.h (VexSwapSources): New.
1390 (i386_opcode_modifier): Add vexswapsources.
1391 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1392 with two source operands swapped.
1393 * i386-tbl.h: Regenerated.
1394
08ccfccf
NC		 13952020-06-30 Nelson Chu <nelson.chu@sifive.com>
1396
1397 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1398 unprivileged CSR can also be initialized.
1399
279edac5
AM		 14002020-06-29 Alan Modra <amodra@gmail.com>
1401
1402 * arm-dis.c: Use C style comments.
1403 * cr16-opc.c: Likewise.
1404 * ft32-dis.c: Likewise.
1405 * moxie-opc.c: Likewise.
1406 * tic54x-dis.c: Likewise.
1407 * s12z-opc.c: Remove useless comment.
1408 * xgate-dis.c: Likewise.
1409
e978ad62
L		 14102020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1411
1412 * i386-opc.tbl: Add a blank line.
1413
63112cd6
L		 14142020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1415
1416 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1417 (VecSIB128): Renamed to ...
1418 (VECSIB128): This.
1419 (VecSIB256): Renamed to ...
1420 (VECSIB256): This.
1421 (VecSIB512): Renamed to ...
1422 (VECSIB512): This.
1423 (VecSIB): Renamed to ...
1424 (SIB): This.
1425 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1426 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1427 (VecSIB256): Likewise.
1428 (VecSIB512): Likewise.
79b32e73 1429 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1430 and VecSIB512, respectively.
1431
d1c36125
JB		 14322020-06-26 Jan Beulich <jbeulich@suse.com>
1433
1434 * i386-dis.c: Adjust description of I macro.
1435 (x86_64_table): Drop use of I.
1436 (float_mem): Replace use of I.
1437 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1438
2a1bb84c
JB		 14392020-06-26 Jan Beulich <jbeulich@suse.com>
1440
1441 * i386-dis.c: (print_insn): Avoid straight assignment to
1442 priv.orig_sizeflag when processing -M sub-options.
1443
8f570d62
JB		 14442020-06-25 Jan Beulich <jbeulich@suse.com>
1445
1446 * i386-dis.c: Adjust description of J macro.
1447 (dis386, x86_64_table, mod_table): Replace J.
1448 (putop): Remove handling of J.
1449
464dc4af
JB		 14502020-06-25 Jan Beulich <jbeulich@suse.com>
1451
1452 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1453
589958d6
JB		 14542020-06-25 Jan Beulich <jbeulich@suse.com>
1455
1456 * i386-dis.c: Adjust description of "LQ" macro.
1457 (dis386_twobyte): Use LQ for sysret.
1458 (putop): Adjust handling of LQ.
1459
39ff0b81
NC		 14602020-06-22 Nelson Chu <nelson.chu@sifive.com>
1461
1462 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1463 * riscv-dis.c: Include elfxx-riscv.h.
1464
d27c357a
JB		 14652020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1466
1467 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1468
6fde587f
CL		 14692020-06-17 Lili Cui <lili.cui@intel.com>
1470
1471 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1472
efe30057
L		 14732020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1474
1475 PR gas/26115
1476 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1477 * i386-opc.tbl: Likewise.
1478 * i386-tbl.h: Regenerated.
1479
d8af286f
NC		 14802020-06-12 Nelson Chu <nelson.chu@sifive.com>
1481
1482 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1483
14962256
AC		 14842020-06-11 Alex Coplan <alex.coplan@arm.com>
1485
1486 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1487 (SR_CORE): Likewise.
1488 (SR_FEAT): Likewise.
1489 (SR_RNG): Likewise.
1490 (SR_V8_1): Likewise.
1491 (SR_V8_2): Likewise.
1492 (SR_V8_3): Likewise.
1493 (SR_V8_4): Likewise.
1494 (SR_PAN): Likewise.
1495 (SR_RAS): Likewise.
1496 (SR_SSBS): Likewise.
1497 (SR_SVE): Likewise.
1498 (SR_ID_PFR2): Likewise.
1499 (SR_PROFILE): Likewise.
1500 (SR_MEMTAG): Likewise.
1501 (SR_SCXTNUM): Likewise.
1502 (aarch64_sys_regs): Refactor to store feature information in the table.
1503 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1504 that now describe their own features.
1505 (aarch64_pstatefield_supported_p): Likewise.
1506
f9630fa6
L		 15072020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1508
1509 * i386-dis.c (prefix_table): Fix a typo in comments.
1510
73239888
JB		 15112020-06-09 Jan Beulich <jbeulich@suse.com>
1512
1513 * i386-dis.c (rex_ignored): Delete.
1514 (ckprefix): Drop rex_ignored initialization.
1515 (get_valid_dis386): Drop setting of rex_ignored.
1516 (print_insn): Drop checking of rex_ignored. Don't record data
1517 size prefix as used with VEX-and-alike encodings.
1518
18897deb
JB		 15192020-06-09 Jan Beulich <jbeulich@suse.com>
1520
1521 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1522 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1523 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1524 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1525 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1526 VEX_0F12, and VEX_0F16.
1527 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1528 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1529 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1530 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1531 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1532 MOD_VEX_0F16_PREFIX_2 entries.
1533
97e6786a
JB		 15342020-06-09 Jan Beulich <jbeulich@suse.com>
1535
1536 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1537 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1538 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1539 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1540 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1541 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1542 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1543 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1544 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1545 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1546 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1547 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1548 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1549 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1550 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1551 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1552 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1553 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1554 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1555 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1556 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1557 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1558 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1559 EVEX_W_0FC6_P_2): Delete.
1560 (print_insn): Add EVEX.W vs embedded prefix consistency check
1561 to prefix validation.
1562 * i386-dis-evex.h (evex_table): Don't further descend for
1563 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1564 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1565 and 0F2B.
1566 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1567 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1568 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1569 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1570 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1571 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1572 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1573 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1574 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1575 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1576 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1577 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1578 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1579 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1580 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1581 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1582 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1583 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1584 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1585 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1586 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1587 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1588 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1589 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1590 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1591 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1592 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1593
bf926894
JB		 15942020-06-09 Jan Beulich <jbeulich@suse.com>
1595
1596 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1597 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1598 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1599 vmovmskpX.
1600 (print_insn): Drop pointless check against bad_opcode. Split
1601 prefix validation into legacy and VEX-and-alike parts.
1602 (putop): Re-work 'X' macro handling.
1603
a5aaedb9
JB		 16042020-06-09 Jan Beulich <jbeulich@suse.com>
1605
1606 * i386-dis.c (MOD_0F51): Rename to ...
1607 (MOD_0F50): ... this.
1608
26417f19
AC		 16092020-06-08 Alex Coplan <alex.coplan@arm.com>
1610
1611 * arm-dis.c (arm_opcodes): Add dfb.
1612 (thumb32_opcodes): Add dfb.
1613
8a6fb3f9
JB		 16142020-06-08 Jan Beulich <jbeulich@suse.com>
1615
1616 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1617
1424c35d
AM		 16182020-06-06 Alan Modra <amodra@gmail.com>
1619
1620 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1621
d3d1cc7b
AM		 16222020-06-05 Alan Modra <amodra@gmail.com>
1623
1624 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1625 size is large enough.
1626
d8740be1
JM		 16272020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1628
1629 * disassemble.c (disassemble_init_for_target): Set endian_code for
1630 bpf targets.
1631 * bpf-desc.c: Regenerate.
1632 * bpf-opc.c: Likewise.
1633 * bpf-dis.c: Likewise.
1634
e9bffec9
JM		 16352020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1636
1637 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1638 (cgen_put_insn_value): Likewise.
1639 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1640 * cgen-dis.in (print_insn): Likewise.
1641 * cgen-ibld.in (insert_1): Likewise.
1642 (insert_1): Likewise.
1643 (insert_insn_normal): Likewise.
1644 (extract_1): Likewise.
1645 * bpf-dis.c: Regenerate.
1646 * bpf-ibld.c: Likewise.
1647 * bpf-ibld.c: Likewise.
1648 * cgen-dis.in: Likewise.
1649 * cgen-ibld.in: Likewise.
1650 * cgen-opc.c: Likewise.
1651 * epiphany-dis.c: Likewise.
1652 * epiphany-ibld.c: Likewise.
1653 * fr30-dis.c: Likewise.
1654 * fr30-ibld.c: Likewise.
1655 * frv-dis.c: Likewise.
1656 * frv-ibld.c: Likewise.
1657 * ip2k-dis.c: Likewise.
1658 * ip2k-ibld.c: Likewise.
1659 * iq2000-dis.c: Likewise.
1660 * iq2000-ibld.c: Likewise.
1661 * lm32-dis.c: Likewise.
1662 * lm32-ibld.c: Likewise.
1663 * m32c-dis.c: Likewise.
1664 * m32c-ibld.c: Likewise.
1665 * m32r-dis.c: Likewise.
1666 * m32r-ibld.c: Likewise.
1667 * mep-dis.c: Likewise.
1668 * mep-ibld.c: Likewise.
1669 * mt-dis.c: Likewise.
1670 * mt-ibld.c: Likewise.
1671 * or1k-dis.c: Likewise.
1672 * or1k-ibld.c: Likewise.
1673 * xc16x-dis.c: Likewise.
1674 * xc16x-ibld.c: Likewise.
1675 * xstormy16-dis.c: Likewise.
1676 * xstormy16-ibld.c: Likewise.
1677
b3db6d07
JM		 16782020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1679
1680 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1681 (print_insn_): Handle instruction endian.
1682 * bpf-dis.c: Regenerate.
1683 * bpf-desc.c: Regenerate.
1684 * epiphany-dis.c: Likewise.
1685 * epiphany-desc.c: Likewise.
1686 * fr30-dis.c: Likewise.
1687 * fr30-desc.c: Likewise.
1688 * frv-dis.c: Likewise.
1689 * frv-desc.c: Likewise.
1690 * ip2k-dis.c: Likewise.
1691 * ip2k-desc.c: Likewise.
1692 * iq2000-dis.c: Likewise.
1693 * iq2000-desc.c: Likewise.
1694 * lm32-dis.c: Likewise.
1695 * lm32-desc.c: Likewise.
1696 * m32c-dis.c: Likewise.
1697 * m32c-desc.c: Likewise.
1698 * m32r-dis.c: Likewise.
1699 * m32r-desc.c: Likewise.
1700 * mep-dis.c: Likewise.
1701 * mep-desc.c: Likewise.
1702 * mt-dis.c: Likewise.
1703 * mt-desc.c: Likewise.
1704 * or1k-dis.c: Likewise.
1705 * or1k-desc.c: Likewise.
1706 * xc16x-dis.c: Likewise.
1707 * xc16x-desc.c: Likewise.
1708 * xstormy16-dis.c: Likewise.
1709 * xstormy16-desc.c: Likewise.
1710
4ee4189f
NC		 17112020-06-03 Nick Clifton <nickc@redhat.com>
1712
1713 * po/sr.po: Updated Serbian translation.
1714
44730156
NC		 17152020-06-03 Nelson Chu <nelson.chu@sifive.com>
1716
1717 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1718 (riscv_get_priv_spec_class): Likewise.
1719
3c3d0376
AM		 17202020-06-01 Alan Modra <amodra@gmail.com>
1721
1722 * bpf-desc.c: Regenerate.
1723
78c1c354
JM		 17242020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1725 David Faust <david.faust@oracle.com>
1726
1727 * bpf-desc.c: Regenerate.
1728 * bpf-opc.h: Likewise.
1729 * bpf-opc.c: Likewise.
1730 * bpf-dis.c: Likewise.
1731
efcf5fb5
AM		 17322020-05-28 Alan Modra <amodra@gmail.com>
1733
1734 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1735 values.
1736
ab382d64
AM		 17372020-05-28 Alan Modra <amodra@gmail.com>
1738
1739 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1740 immediates.
1741 (print_insn_ns32k): Revert last change.
1742
151f5de4
NC		 17432020-05-28 Nick Clifton <nickc@redhat.com>
1744
1745 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1746 static.
1747
25e1eca8
SL		 17482020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1749
1750 Fix extraction of signed constants in nios2 disassembler (again).
1751
1752 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1753 extractions of signed fields.
1754
57b17940
SSF		 17552020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1756
1757 * s390-opc.txt: Relocate vector load/store instructions with
1758 additional alignment parameter and change architecture level
1759 constraint from z14 to z13.
1760
d96bf37b
AM		 17612020-05-21 Alan Modra <amodra@gmail.com>
1762
1763 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1764 * sparc-dis.c: Likewise.
1765 * tic4x-dis.c: Likewise.
1766 * xtensa-dis.c: Likewise.
1767 * bpf-desc.c: Regenerate.
1768 * epiphany-desc.c: Regenerate.
1769 * fr30-desc.c: Regenerate.
1770 * frv-desc.c: Regenerate.
1771 * ip2k-desc.c: Regenerate.
1772 * iq2000-desc.c: Regenerate.
1773 * lm32-desc.c: Regenerate.
1774 * m32c-desc.c: Regenerate.
1775 * m32r-desc.c: Regenerate.
1776 * mep-asm.c: Regenerate.
1777 * mep-desc.c: Regenerate.
1778 * mt-desc.c: Regenerate.
1779 * or1k-desc.c: Regenerate.
1780 * xc16x-desc.c: Regenerate.
1781 * xstormy16-desc.c: Regenerate.
1782
8f595e9b
NC		 17832020-05-20 Nelson Chu <nelson.chu@sifive.com>
1784
1785 * riscv-opc.c (riscv_ext_version_table): The table used to store
1786 all information about the supported spec and the corresponding ISA
1787 versions. Currently, only Zicsr is supported to verify the
1788 correctness of Z sub extension settings. Others will be supported
1789 in the future patches.
1790 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1791 classes and the corresponding strings.
1792 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1793 spec class by giving a ISA spec string.
1794 * riscv-opc.c (struct priv_spec_t): New structure.
1795 (struct priv_spec_t priv_specs): List for all supported privilege spec
1796 classes and the corresponding strings.
1797 (riscv_get_priv_spec_class): New function. Get the corresponding
1798 privilege spec class by giving a spec string.
1799 (riscv_get_priv_spec_name): New function. Get the corresponding
1800 privilege spec string by giving a CSR version class.
1801 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1802 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1803 according to the chosen version. Build a hash table riscv_csr_hash to
1804 store the valid CSR for the chosen pirv verison. Dump the direct
1805 CSR address rather than it's name if it is invalid.
1806 (parse_riscv_dis_option_without_args): New function. Parse the options
1807 without arguments.
1808 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1809 parse the options without arguments first, and then handle the options
1810 with arguments. Add the new option -Mpriv-spec, which has argument.
1811 * riscv-dis.c (print_riscv_disassembler_options): Add description
1812 about the new OBJDUMP option.
1813
3d205eb4
PB		 18142020-05-19 Peter Bergner <bergner@linux.ibm.com>
1815
1816 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1817 WC values on POWER10 sync, dcbf and wait instructions.
1818 (insert_pl, extract_pl): New functions.
1819 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1820 (LS3): New , 3-bit L for sync.
1821 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1822 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1823 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1824 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1825 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1826 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1827 <wait>: Enable PL operand on POWER10.
1828 <dcbf>: Enable L3OPT operand on POWER10.
1829 <sync>: Enable SC2 operand on POWER10.
1830
a501eb44
SH		 18312020-05-19 Stafford Horne <shorne@gmail.com>
1832
1833 PR 25184
1834 * or1k-asm.c: Regenerate.
1835 * or1k-desc.c: Regenerate.
1836 * or1k-desc.h: Regenerate.
1837 * or1k-dis.c: Regenerate.
1838 * or1k-ibld.c: Regenerate.
1839 * or1k-opc.c: Regenerate.
1840 * or1k-opc.h: Regenerate.
1841 * or1k-opinst.c: Regenerate.
1842
3b646889
AM		 18432020-05-11 Alan Modra <amodra@gmail.com>
1844
1845 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1846 xsmaxcqp, xsmincqp.
1847
9cc4ce88
AM		 18482020-05-11 Alan Modra <amodra@gmail.com>
1849
1850 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1851 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1852
5d57bc3f
AM		 18532020-05-11 Alan Modra <amodra@gmail.com>
1854
1855 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1856
66ef5847
AM		 18572020-05-11 Alan Modra <amodra@gmail.com>
1858
1859 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1860 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1861
4f3e9537
PB		 18622020-05-11 Peter Bergner <bergner@linux.ibm.com>
1863
1864 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1865 mnemonics.
1866
ec40e91c
AM		 18672020-05-11 Alan Modra <amodra@gmail.com>
1868
1869 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1870 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1871 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1872 (prefix_opcodes): Add xxeval.
1873
d7e97a76
AM		 18742020-05-11 Alan Modra <amodra@gmail.com>
1875
1876 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1877 xxgenpcvwm, xxgenpcvdm.
1878
fdefed7c
AM		 18792020-05-11 Alan Modra <amodra@gmail.com>
1880
1881 * ppc-opc.c (MP, VXVAM_MASK): Define.
1882 (VXVAPS_MASK): Use VXVA_MASK.
1883 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1884 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1885 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1886 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1887
aa3c112f
AM		 18882020-05-11 Alan Modra <amodra@gmail.com>
1889 Peter Bergner <bergner@linux.ibm.com>
1890
1891 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1892 New functions.
1893 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1894 YMSK2, XA6a, XA6ap, XB6a entries.
1895 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1896 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1897 (PPCVSX4): Define.
1898 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1899 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1900 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1901 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1902 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1903 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1904 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1905 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1906 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1907 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1908 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1909 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1910 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1911 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1912
6edbfd3b
AM		 19132020-05-11 Alan Modra <amodra@gmail.com>
1914
1915 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1916 (insert_xts, extract_xts): New functions.
1917 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1918 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1919 (VXRC_MASK, VXSH_MASK): Define.
1920 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1921 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1922 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1923 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1924 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1925 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1926 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1927
c7d7aea2
AM		 19282020-05-11 Alan Modra <amodra@gmail.com>
1929
1930 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1931 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1932 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1933 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1934 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1935
94ba9882
AM		 19362020-05-11 Alan Modra <amodra@gmail.com>
1937
1938 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1939 (XTP, DQXP, DQXP_MASK): Define.
1940 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1941 (prefix_opcodes): Add plxvp and pstxvp.
1942
f4791f1a
AM		 19432020-05-11 Alan Modra <amodra@gmail.com>
1944
1945 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1946 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1947 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1948
3ff0a5ba
PB		 19492020-05-11 Peter Bergner <bergner@linux.ibm.com>
1950
1951 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1952
afef4fe9
PB		 19532020-05-11 Peter Bergner <bergner@linux.ibm.com>
1954
1955 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1956 (L1OPT): Define.
1957 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1958
1224c05d
PB		 19592020-05-11 Peter Bergner <bergner@linux.ibm.com>
1960
1961 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1962
6bbb0c05
AM		 19632020-05-11 Alan Modra <amodra@gmail.com>
1964
1965 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1966
7c1f4227
AM		 19672020-05-11 Alan Modra <amodra@gmail.com>
1968
1969 * ppc-dis.c (ppc_opts): Add "power10" entry.
1970 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1971 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1972
73199c2b
NC		 19732020-05-11 Nick Clifton <nickc@redhat.com>
1974
1975 * po/fr.po: Updated French translation.
1976
09c1e68a
AC		 19772020-04-30 Alex Coplan <alex.coplan@arm.com>
1978
1979 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1980 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1981 (operand_general_constraint_met_p): validate
1982 AARCH64_OPND_UNDEFINED.
1983 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1984 for FLD_imm16_2.
1985 * aarch64-asm-2.c: Regenerated.
1986 * aarch64-dis-2.c: Regenerated.
1987 * aarch64-opc-2.c: Regenerated.
1988
9654d51a
NC		 19892020-04-29 Nick Clifton <nickc@redhat.com>
1990
1991 PR 22699
1992 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1993 and SETRC insns.
1994
c2e71e57
NC		 19952020-04-29 Nick Clifton <nickc@redhat.com>
1996
1997 * po/sv.po: Updated Swedish translation.
1998
5c936ef5
NC		 19992020-04-29 Nick Clifton <nickc@redhat.com>
2000
2001 PR 22699
2002 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
2003 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
2004 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
2005 IMM0_8U case.
2006
bb2a1453
AS		 20072020-04-21 Andreas Schwab <schwab@linux-m68k.org>
2008
2009 PR 25848
2010 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
2011 cmpi only on m68020up and cpu32.
2012
c2e5c986
SD		 20132020-04-20 Sudakshina Das <sudi.das@arm.com>
2014
2015 * aarch64-asm.c (aarch64_ins_none): New.
2016 * aarch64-asm.h (ins_none): New declaration.
2017 * aarch64-dis.c (aarch64_ext_none): New.
2018 * aarch64-dis.h (ext_none): New declaration.
2019 * aarch64-opc.c (aarch64_print_operand): Update case for
2020 AARCH64_OPND_BARRIER_PSB.
2021 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
2022 (AARCH64_OPERANDS): Update inserter/extracter for
2023 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
2024 * aarch64-asm-2.c: Regenerated.
2025 * aarch64-dis-2.c: Regenerated.
2026 * aarch64-opc-2.c: Regenerated.
2027
8a6e1d1d
SD		 20282020-04-20 Sudakshina Das <sudi.das@arm.com>
2029
2030 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
2031 (aarch64_feature_ras, RAS): Likewise.
2032 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
2033 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
2034 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
2035 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
2036 * aarch64-asm-2.c: Regenerated.
2037 * aarch64-dis-2.c: Regenerated.
2038 * aarch64-opc-2.c: Regenerated.
2039
e409955d
FS		 20402020-04-17 Fredrik Strupe <fredrik@strupe.net>
2041
2042 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
2043 (print_insn_neon): Support disassembly of conditional
2044 instructions.
2045
c54a9b56
DF		 20462020-02-16 David Faust <david.faust@oracle.com>
2047
2048 * bpf-desc.c: Regenerate.
2049 * bpf-desc.h: Likewise.
2050 * bpf-opc.c: Regenerate.
2051 * bpf-opc.h: Likewise.
2052
bb651e8b
CL		 20532020-04-07 Lili Cui <lili.cui@intel.com>
2054
2055 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
2056 (prefix_table): New instructions (see prefixes above).
2057 (rm_table): Likewise
2058 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
2059 CPU_ANY_TSXLDTRK_FLAGS.
2060 (cpu_flags): Add CpuTSXLDTRK.
2061 * i386-opc.h (enum): Add CpuTSXLDTRK.
2062 (i386_cpu_flags): Add cputsxldtrk.
2063 * i386-opc.tbl: Add XSUSPLDTRK insns.
2064 * i386-init.h: Regenerate.
2065 * i386-tbl.h: Likewise.
2066
4b27d27c
L		 20672020-04-02 Lili Cui <lili.cui@intel.com>
2068
2069 * i386-dis.c (prefix_table): New instructions serialize.
2070 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
2071 CPU_ANY_SERIALIZE_FLAGS.
2072 (cpu_flags): Add CpuSERIALIZE.
2073 * i386-opc.h (enum): Add CpuSERIALIZE.
2074 (i386_cpu_flags): Add cpuserialize.
2075 * i386-opc.tbl: Add SERIALIZE insns.
2076 * i386-init.h: Regenerate.
2077 * i386-tbl.h: Likewise.
2078
832a5807
AM		 20792020-03-26 Alan Modra <amodra@gmail.com>
2080
2081 * disassemble.h (opcodes_assert): Declare.
2082 (OPCODES_ASSERT): Define.
2083 * disassemble.c: Don't include assert.h. Include opintl.h.
2084 (opcodes_assert): New function.
2085 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
2086 (bfd_h8_disassemble): Reduce size of data array. Correctly
2087 calculate maxlen. Omit insn decoding when insn length exceeds
2088 maxlen. Exit from nibble loop when looking for E, before
2089 accessing next data byte. Move processing of E outside loop.
2090 Replace tests of maxlen in loop with assertions.
2091
4c4addbe
AM		 20922020-03-26 Alan Modra <amodra@gmail.com>
2093
2094 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
2095
a18cd0ca
AM		 20962020-03-25 Alan Modra <amodra@gmail.com>
2097
2098 * z80-dis.c (suffix): Init mybuf.
2099
57cb32b3
AM		 21002020-03-22 Alan Modra <amodra@gmail.com>
2101
2102 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
2103 successflly read from section.
2104
beea5cc1
AM		 21052020-03-22 Alan Modra <amodra@gmail.com>
2106
2107 * arc-dis.c (find_format): Use ISO C string concatenation rather
2108 than line continuation within a string. Don't access needs_limm
2109 before testing opcode != NULL.
2110
03704c77
AM		 21112020-03-22 Alan Modra <amodra@gmail.com>
2112
2113 * ns32k-dis.c (print_insn_arg): Update comment.
2114 (print_insn_ns32k): Reduce size of index_offset array, and
2115 initialize, passing -1 to print_insn_arg for args that are not
2116 an index. Don't exit arg loop early. Abort on bad arg number.
2117
d1023b5d
AM		 21182020-03-22 Alan Modra <amodra@gmail.com>
2119
2120 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
2121 * s12z-opc.c: Formatting.
2122 (operands_f): Return an int.
2123 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
2124 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
2125 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
2126 (exg_sex_discrim): Likewise.
2127 (create_immediate_operand, create_bitfield_operand),
2128 (create_register_operand_with_size, create_register_all_operand),
2129 (create_register_all16_operand, create_simple_memory_operand),
2130 (create_memory_operand, create_memory_auto_operand): Don't
2131 segfault on malloc failure.
2132 (z_ext24_decode): Return an int status, negative on fail, zero
2133 on success.
2134 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
2135 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
2136 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
2137 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
2138 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
2139 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
2140 (loop_primitive_decode, shift_decode, psh_pul_decode),
2141 (bit_field_decode): Similarly.
2142 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
2143 to return value, update callers.
2144 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
2145 Don't segfault on NULL operand.
2146 (decode_operation): Return OP_INVALID on first fail.
2147 (decode_s12z): Check all reads, returning -1 on fail.
2148
340f3ac8
AM		 21492020-03-20 Alan Modra <amodra@gmail.com>
2150
2151 * metag-dis.c (print_insn_metag): Don't ignore status from
2152 read_memory_func.
2153
fe90ae8a
AM		 21542020-03-20 Alan Modra <amodra@gmail.com>
2155
2156 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
2157 Initialize parts of buffer not written when handling a possible
2158 2-byte insn at end of section. Don't attempt decoding of such
2159 an insn by the 4-byte machinery.
2160
833d919c
AM		 21612020-03-20 Alan Modra <amodra@gmail.com>
2162
2163 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
2164 partially filled buffer. Prevent lookup of 4-byte insns when
2165 only VLE 2-byte insns are possible due to section size. Print
2166 ".word" rather than ".long" for 2-byte leftovers.
2167
327ef784
NC		 21682020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
2169
2170 PR 25641
2171 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
2172
1673df32
JB		 21732020-03-13 Jan Beulich <jbeulich@suse.com>
2174
2175 * i386-dis.c (X86_64_0D): Rename to ...
2176 (X86_64_0E): ... this.
2177
384f3689
L		 21782020-03-09 H.J. Lu <hongjiu.lu@intel.com>
2179
2180 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
2181 * Makefile.in: Regenerated.
2182
865e2027
JB		 21832020-03-09 Jan Beulich <jbeulich@suse.com>
2184
2185 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
2186 3-operand pseudos.
2187 * i386-tbl.h: Re-generate.
2188
2f13234b
JB		 21892020-03-09 Jan Beulich <jbeulich@suse.com>
2190
2191 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
2192 vprot*, vpsha*, and vpshl*.
2193 * i386-tbl.h: Re-generate.
2194
3fabc179
JB		 21952020-03-09 Jan Beulich <jbeulich@suse.com>
2196
2197 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
2198 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
2199 * i386-tbl.h: Re-generate.
2200
3677e4c1
JB		 22012020-03-09 Jan Beulich <jbeulich@suse.com>
2202
2203 * i386-gen.c (set_bitfield): Ignore zero-length field names.
2204 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
2205 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
2206 * i386-tbl.h: Re-generate.
2207
4c4898e8
JB		 22082020-03-09 Jan Beulich <jbeulich@suse.com>
2209
2210 * i386-gen.c (struct template_arg, struct template_instance,
2211 struct template_param, struct template, templates,
2212 parse_template, expand_templates): New.
2213 (process_i386_opcodes): Various local variables moved to
2214 expand_templates. Call parse_template and expand_templates.
2215 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
2216 * i386-tbl.h: Re-generate.
2217
bc49bfd8
JB		 22182020-03-06 Jan Beulich <jbeulich@suse.com>
2219
2220 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
2221 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
2222 register and memory source templates. Replace VexW= by VexW*
2223 where applicable.
2224 * i386-tbl.h: Re-generate.
2225
4873e243
JB		 22262020-03-06 Jan Beulich <jbeulich@suse.com>
2227
2228 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
2229 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
2230 * i386-tbl.h: Re-generate.
2231
672a349b
JB		 22322020-03-06 Jan Beulich <jbeulich@suse.com>
2233
2234 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
2235 * i386-tbl.h: Re-generate.
2236
4ed21b58
JB		 22372020-03-06 Jan Beulich <jbeulich@suse.com>
2238
2239 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
2240 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
2241 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
2242 VexW0 on SSE2AVX variants.
2243 (vmovq): Drop NoRex64 from XMM/XMM variants.
2244 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
2245 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
2246 applicable use VexW0.
2247 * i386-tbl.h: Re-generate.
2248
643bb870
JB		 22492020-03-06 Jan Beulich <jbeulich@suse.com>
2250
2251 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
2252 * i386-opc.h (Rex64): Delete.
2253 (struct i386_opcode_modifier): Remove rex64 field.
2254 * i386-opc.tbl (crc32): Drop Rex64.
2255 Replace Rex64 with Size64 everywhere else.
2256 * i386-tbl.h: Re-generate.
2257
a23b33b3
JB		 22582020-03-06 Jan Beulich <jbeulich@suse.com>
2259
2260 * i386-dis.c (OP_E_memory): Exclude recording of used address
2261 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
2262 addressed memory operands for MPX insns.
2263
a0497384
JB		 22642020-03-06 Jan Beulich <jbeulich@suse.com>
2265
2266 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
2267 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
2268 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
2269 (ptwrite): Split into non-64-bit and 64-bit forms.
2270 * i386-tbl.h: Re-generate.
2271
b630c145
JB		 22722020-03-06 Jan Beulich <jbeulich@suse.com>
2273
2274 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
2275 template.
2276 * i386-tbl.h: Re-generate.
2277
a847e322
JB		 22782020-03-04 Jan Beulich <jbeulich@suse.com>
2279
2280 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2281 (prefix_table): Move vmmcall here. Add vmgexit.
2282 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2283 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2284 (cpu_flags): Add CpuSEV_ES entry.
2285 * i386-opc.h (CpuSEV_ES): New.
2286 (union i386_cpu_flags): Add cpusev_es field.
2287 * i386-opc.tbl (vmgexit): New.
2288 * i386-init.h, i386-tbl.h: Re-generate.
2289
3cd7f3e3
L		 22902020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2291
2292 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2293 with MnemonicSize.
2294 * i386-opc.h (IGNORESIZE): New.
2295 (DEFAULTSIZE): Likewise.
2296 (IgnoreSize): Removed.
2297 (DefaultSize): Likewise.
2298 (MnemonicSize): New.
2299 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2300 mnemonicsize.
2301 * i386-opc.tbl (IgnoreSize): New.
2302 (DefaultSize): Likewise.
2303 * i386-tbl.h: Regenerated.
2304
b8ba1385
SB		 23052020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2306
2307 PR 25627
2308 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2309 instructions.
2310
10d97a0f
L		 23112020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2312
2313 PR gas/25622
2314 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2315 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2316 * i386-tbl.h: Regenerated.
2317
dc1e8a47
AM		 23182020-02-26 Alan Modra <amodra@gmail.com>
2319
2320 * aarch64-asm.c: Indent labels correctly.
2321 * aarch64-dis.c: Likewise.
2322 * aarch64-gen.c: Likewise.
2323 * aarch64-opc.c: Likewise.
2324 * alpha-dis.c: Likewise.
2325 * i386-dis.c: Likewise.
2326 * nds32-asm.c: Likewise.
2327 * nfp-dis.c: Likewise.
2328 * visium-dis.c: Likewise.
2329
265b4673
CZ		 23302020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2331
2332 * arc-regs.h (int_vector_base): Make it available for all ARC
2333 CPUs.
2334
bd0cf5a6
NC		 23352020-02-20 Nelson Chu <nelson.chu@sifive.com>
2336
2337 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2338 changed.
2339
fa164239
JW		 23402020-02-19 Nelson Chu <nelson.chu@sifive.com>
2341
2342 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2343 c.mv/c.li if rs1 is zero.
2344
272a84b1
L		 23452020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2346
2347 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2348 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2349 CPU_POPCNT_FLAGS.
2350 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2351 * i386-opc.h (CpuABM): Removed.
2352 (CpuPOPCNT): New.
2353 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2354 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2355 popcnt. Remove CpuABM from lzcnt.
2356 * i386-init.h: Regenerated.
2357 * i386-tbl.h: Likewise.
2358
1f730c46
JB		 23592020-02-17 Jan Beulich <jbeulich@suse.com>
2360
2361 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2362 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2363 VexW1 instead of open-coding them.
2364 * i386-tbl.h: Re-generate.
2365
c8f8eebc
JB		 23662020-02-17 Jan Beulich <jbeulich@suse.com>
2367
2368 * i386-opc.tbl (AddrPrefixOpReg): Define.
2369 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2370 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2371 templates. Drop NoRex64.
2372 * i386-tbl.h: Re-generate.
2373
b9915cbc
JB		 23742020-02-17 Jan Beulich <jbeulich@suse.com>
2375
2376 PR gas/6518
2377 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2378 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2379 into Intel syntax instance (with Unpsecified) and AT&T one
2380 (without).
2381 (vcvtneps2bf16): Likewise, along with folding the two so far
2382 separate ones.
2383 * i386-tbl.h: Re-generate.
2384
ce504911
L		 23852020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2386
2387 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2388 CPU_ANY_SSE4A_FLAGS.
2389
dabec65d
AM		 23902020-02-17 Alan Modra <amodra@gmail.com>
2391
2392 * i386-gen.c (cpu_flag_init): Correct last change.
2393
af5c13b0
L		 23942020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2395
2396 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2397 CPU_ANY_SSE4_FLAGS.
2398
6867aac0
L		 23992020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2400
2401 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2402 (movzx): Likewise.
2403
65fca059
JB		 24042020-02-14 Jan Beulich <jbeulich@suse.com>
2405
2406 PR gas/25438
2407 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2408 destination for Cpu64-only variant.
2409 (movzx): Fold patterns.
2410 * i386-tbl.h: Re-generate.
2411
7deea9aa
JB		 24122020-02-13 Jan Beulich <jbeulich@suse.com>
2413
2414 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2415 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2416 CPU_ANY_SSE4_FLAGS entry.
2417 * i386-init.h: Re-generate.
2418
6c0946d0
JB		 24192020-02-12 Jan Beulich <jbeulich@suse.com>
2420
2421 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2422 with Unspecified, making the present one AT&T syntax only.
2423 * i386-tbl.h: Re-generate.
2424
ddb56fe6
JB		 24252020-02-12 Jan Beulich <jbeulich@suse.com>
2426
2427 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2428 * i386-tbl.h: Re-generate.
2429
5990e377
JB		 24302020-02-12 Jan Beulich <jbeulich@suse.com>
2431
2432 PR gas/24546
2433 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2434 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2435 Amd64 and Intel64 templates.
2436 (call, jmp): Likewise for far indirect variants. Dro
2437 Unspecified.
2438 * i386-tbl.h: Re-generate.
2439
50128d0c
JB		 24402020-02-11 Jan Beulich <jbeulich@suse.com>
2441
2442 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2443 * i386-opc.h (ShortForm): Delete.
2444 (struct i386_opcode_modifier): Remove shortform field.
2445 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2446 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2447 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2448 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2449 Drop ShortForm.
2450 * i386-tbl.h: Re-generate.
2451
1e05b5c4
JB		 24522020-02-11 Jan Beulich <jbeulich@suse.com>
2453
2454 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2455 fucompi): Drop ShortForm from operand-less templates.
2456 * i386-tbl.h: Re-generate.
2457
2f5dd314
AM		 24582020-02-11 Alan Modra <amodra@gmail.com>
2459
2460 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2461 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2462 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2463 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2464 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2465
5aae9ae9
MM		 24662020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2467
2468 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2469 (cde_opcodes): Add VCX* instructions.
2470
4934a27c
MM		 24712020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2472 Matthew Malcomson <matthew.malcomson@arm.com>
2473
2474 * arm-dis.c (struct cdeopcode32): New.
2475 (CDE_OPCODE): New macro.
2476 (cde_opcodes): New disassembly table.
2477 (regnames): New option to table.
2478 (cde_coprocs): New global variable.
2479 (print_insn_cde): New
2480 (print_insn_thumb32): Use print_insn_cde.
2481 (parse_arm_disassembler_options): Parse coprocN args.
2482
4b5aaf5f
L		 24832020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2484
2485 PR gas/25516
2486 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2487 with ISA64.
2488 * i386-opc.h (AMD64): Removed.
2489 (Intel64): Likewose.
2490 (AMD64): New.
2491 (INTEL64): Likewise.
2492 (INTEL64ONLY): Likewise.
2493 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2494 * i386-opc.tbl (Amd64): New.
2495 (Intel64): Likewise.
2496 (Intel64Only): Likewise.
2497 Replace AMD64 with Amd64. Update sysenter/sysenter with
2498 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2499 * i386-tbl.h: Regenerated.
2500
9fc0b501
SB		 25012020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2502
2503 PR 25469
2504 * z80-dis.c: Add support for GBZ80 opcodes.
2505
c5d7be0c
AM		 25062020-02-04 Alan Modra <amodra@gmail.com>
2507
2508 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2509
44e4546f
AM		 25102020-02-03 Alan Modra <amodra@gmail.com>
2511
2512 * m32c-ibld.c: Regenerate.
2513
b2b1453a
AM		 25142020-02-01 Alan Modra <amodra@gmail.com>
2515
2516 * frv-ibld.c: Regenerate.
2517
4102be5c
JB		 25182020-01-31 Jan Beulich <jbeulich@suse.com>
2519
2520 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2521 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2522 (OP_E_memory): Replace xmm_mdq_mode case label by
2523 vex_scalar_w_dq_mode one.
2524 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2525
825bd36c
JB		 25262020-01-31 Jan Beulich <jbeulich@suse.com>
2527
2528 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2529 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2530 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2531 (intel_operand_size): Drop vex_w_dq_mode case label.
2532
c3036ed0
RS		 25332020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2534
2535 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2536 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2537
0c115f84
AM		 25382020-01-30 Alan Modra <amodra@gmail.com>
2539
2540 * m32c-ibld.c: Regenerate.
2541
bd434cc4
JM		 25422020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2543
2544 * bpf-opc.c: Regenerate.
2545
aeab2b26
JB		 25462020-01-30 Jan Beulich <jbeulich@suse.com>
2547
2548 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2549 (dis386): Use them to replace C2/C3 table entries.
2550 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2551 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2552 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2553 * i386-tbl.h: Re-generate.
2554
62b3f548
JB		 25552020-01-30 Jan Beulich <jbeulich@suse.com>
2556
2557 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2558 forms.
2559 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2560 DefaultSize.
2561 * i386-tbl.h: Re-generate.
2562
1bd8ae10
AM		 25632020-01-30 Alan Modra <amodra@gmail.com>
2564
2565 * tic4x-dis.c (tic4x_dp): Make unsigned.
2566
bc31405e
L		 25672020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2568 Jan Beulich <jbeulich@suse.com>
2569
2570 PR binutils/25445
2571 * i386-dis.c (MOVSXD_Fixup): New function.
2572 (movsxd_mode): New enum.
2573 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2574 (intel_operand_size): Handle movsxd_mode.
2575 (OP_E_register): Likewise.
2576 (OP_G): Likewise.
2577 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2578 register on movsxd. Add movsxd with 16-bit destination register
2579 for AMD64 and Intel64 ISAs.
2580 * i386-tbl.h: Regenerated.
2581
7568c93b
TC		 25822020-01-27 Tamar Christina <tamar.christina@arm.com>
2583
2584 PR 25403
2585 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2586 * aarch64-asm-2.c: Regenerate
2587 * aarch64-dis-2.c: Likewise.
2588 * aarch64-opc-2.c: Likewise.
2589
c006a730
JB		 25902020-01-21 Jan Beulich <jbeulich@suse.com>
2591
2592 * i386-opc.tbl (sysret): Drop DefaultSize.
2593 * i386-tbl.h: Re-generate.
2594
c906a69a
JB		 25952020-01-21 Jan Beulich <jbeulich@suse.com>
2596
2597 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2598 Dword.
2599 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2600 * i386-tbl.h: Re-generate.
2601
26916852
NC		 26022020-01-20 Nick Clifton <nickc@redhat.com>
2603
2604 * po/de.po: Updated German translation.
2605 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2606 * po/uk.po: Updated Ukranian translation.
2607
4d6cbb64
AM		 26082020-01-20 Alan Modra <amodra@gmail.com>
2609
2610 * hppa-dis.c (fput_const): Remove useless cast.
2611
2bddb71a
AM		 26122020-01-20 Alan Modra <amodra@gmail.com>
2613
2614 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2615
1b1bb2c6
NC		 26162020-01-18 Nick Clifton <nickc@redhat.com>
2617
2618 * configure: Regenerate.
2619 * po/opcodes.pot: Regenerate.
2620
ae774686
NC		 26212020-01-18 Nick Clifton <nickc@redhat.com>
2622
2623 Binutils 2.34 branch created.
2624
07f1f3aa
CB		 26252020-01-17 Christian Biesinger <cbiesinger@google.com>
2626
2627 * opintl.h: Fix spelling error (seperate).
2628
42e04b36
L		 26292020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2630
2631 * i386-opc.tbl: Add {vex} pseudo prefix.
2632 * i386-tbl.h: Regenerated.
2633
2da2eaf4
AV		 26342020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2635
2636 PR 25376
2637 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2638 (neon_opcodes): Likewise.
2639 (select_arm_features): Make sure we enable MVE bits when selecting
2640 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2641 any architecture.
2642
d0849eed
JB		 26432020-01-16 Jan Beulich <jbeulich@suse.com>
2644
2645 * i386-opc.tbl: Drop stale comment from XOP section.
2646
9cf70a44
JB		 26472020-01-16 Jan Beulich <jbeulich@suse.com>
2648
2649 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2650 (extractps): Add VexWIG to SSE2AVX forms.
2651 * i386-tbl.h: Re-generate.
2652
4814632e
JB		 26532020-01-16 Jan Beulich <jbeulich@suse.com>
2654
2655 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2656 Size64 from and use VexW1 on SSE2AVX forms.
2657 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2658 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2659 * i386-tbl.h: Re-generate.
2660
aad09917
AM		 26612020-01-15 Alan Modra <amodra@gmail.com>
2662
2663 * tic4x-dis.c (tic4x_version): Make unsigned long.
2664 (optab, optab_special, registernames): New file scope vars.
2665 (tic4x_print_register): Set up registernames rather than
2666 malloc'd registertable.
2667 (tic4x_disassemble): Delete optable and optable_special. Use
2668 optab and optab_special instead. Throw away old optab,
2669 optab_special and registernames when info->mach changes.
2670
7a6bf3be
SB		 26712020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2672
2673 PR 25377
2674 * z80-dis.c (suffix): Use .db instruction to generate double
2675 prefix.
2676
ca1eaac0
AM		 26772020-01-14 Alan Modra <amodra@gmail.com>
2678
2679 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2680 values to unsigned before shifting.
2681
1d67fe3b
TT		 26822020-01-13 Thomas Troeger <tstroege@gmx.de>
2683
2684 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2685 flow instructions.
2686 (print_insn_thumb16, print_insn_thumb32): Likewise.
2687 (print_insn): Initialize the insn info.
2688 * i386-dis.c (print_insn): Initialize the insn info fields, and
2689 detect jumps.
2690
5e4f7e05
CZ		 26912012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2692
2693 * arc-opc.c (C_NE): Make it required.
2694
b9fe6b8a
CZ		 26952012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2696
2697 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2698 reserved register name.
2699
90dee485
AM		 27002020-01-13 Alan Modra <amodra@gmail.com>
2701
2702 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2703 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2704
febda64f
AM		 27052020-01-13 Alan Modra <amodra@gmail.com>
2706
2707 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2708 result of wasm_read_leb128 in a uint64_t and check that bits
2709 are not lost when copying to other locals. Use uint32_t for
2710 most locals. Use PRId64 when printing int64_t.
2711
df08b588
AM		 27122020-01-13 Alan Modra <amodra@gmail.com>
2713
2714 * score-dis.c: Formatting.
2715 * score7-dis.c: Formatting.
2716
b2c759ce
AM		 27172020-01-13 Alan Modra <amodra@gmail.com>
2718
2719 * score-dis.c (print_insn_score48): Use unsigned variables for
2720 unsigned values. Don't left shift negative values.
2721 (print_insn_score32): Likewise.
2722 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2723
5496abe1
AM		 27242020-01-13 Alan Modra <amodra@gmail.com>
2725
2726 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2727
202e762b
AM		 27282020-01-13 Alan Modra <amodra@gmail.com>
2729
2730 * fr30-ibld.c: Regenerate.
2731
7ef412cf
AM		 27322020-01-13 Alan Modra <amodra@gmail.com>
2733
2734 * xgate-dis.c (print_insn): Don't left shift signed value.
2735 (ripBits): Formatting, use 1u.
2736
7f578b95
AM		 27372020-01-10 Alan Modra <amodra@gmail.com>
2738
2739 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2740 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2741
441af85b
AM		 27422020-01-10 Alan Modra <amodra@gmail.com>
2743
2744 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2745 and XRREG value earlier to avoid a shift with negative exponent.
2746 * m10200-dis.c (disassemble): Similarly.
2747
bce58db4
NC		 27482020-01-09 Nick Clifton <nickc@redhat.com>
2749
2750 PR 25224
2751 * z80-dis.c (ld_ii_ii): Use correct cast.
2752
40c75bc8
SB		 27532020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2754
2755 PR 25224
2756 * z80-dis.c (ld_ii_ii): Use character constant when checking
2757 opcode byte value.
2758
d835a58b
JB		 27592020-01-09 Jan Beulich <jbeulich@suse.com>
2760
2761 * i386-dis.c (SEP_Fixup): New.
2762 (SEP): Define.
2763 (dis386_twobyte): Use it for sysenter/sysexit.
2764 (enum x86_64_isa): Change amd64 enumerator to value 1.
2765 (OP_J): Compare isa64 against intel64 instead of amd64.
2766 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2767 forms.
2768 * i386-tbl.h: Re-generate.
2769
030a2e78
AM		 27702020-01-08 Alan Modra <amodra@gmail.com>
2771
2772 * z8k-dis.c: Include libiberty.h
2773 (instr_data_s): Make max_fetched unsigned.
2774 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2775 Don't exceed byte_info bounds.
2776 (output_instr): Make num_bytes unsigned.
2777 (unpack_instr): Likewise for nibl_count and loop.
2778 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2779 idx unsigned.
2780 * z8k-opc.h: Regenerate.
2781
bb82aefe
SV		 27822020-01-07 Shahab Vahedi <shahab@synopsys.com>
2783
2784 * arc-tbl.h (llock): Use 'LLOCK' as class.
2785 (llockd): Likewise.
2786 (scond): Use 'SCOND' as class.
2787 (scondd): Likewise.
2788 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2789 (scondd): Likewise.
2790
cc6aa1a6
AM		 27912020-01-06 Alan Modra <amodra@gmail.com>
2792
2793 * m32c-ibld.c: Regenerate.
2794
660e62b1
AM		 27952020-01-06 Alan Modra <amodra@gmail.com>
2796
2797 PR 25344
2798 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2799 Peek at next byte to prevent recursion on repeated prefix bytes.
2800 Ensure uninitialised "mybuf" is not accessed.
2801 (print_insn_z80): Don't zero n_fetch and n_used here,..
2802 (print_insn_z80_buf): ..do it here instead.
2803
c9ae58fe
AM		 28042020-01-04 Alan Modra <amodra@gmail.com>
2805
2806 * m32r-ibld.c: Regenerate.
2807
5f57d4ec
AM		 28082020-01-04 Alan Modra <amodra@gmail.com>
2809
2810 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2811
2c5c1196
AM		 28122020-01-04 Alan Modra <amodra@gmail.com>
2813
2814 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2815
2e98c6c5
AM		 28162020-01-04 Alan Modra <amodra@gmail.com>
2817
2818 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2819
567dfba2
JB		 28202020-01-03 Jan Beulich <jbeulich@suse.com>
2821
5437a02a
JB		 2822 * aarch64-tbl.h (aarch64_opcode_table): Use
2823 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2824
28252020-01-03 Jan Beulich <jbeulich@suse.com>
2826
2827 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2828 forms of SUDOT and USDOT.
2829
8c45011a
JB		 28302020-01-03 Jan Beulich <jbeulich@suse.com>
2831
5437a02a 2832 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2833 uzip{1,2}.
2834 * opcodes/aarch64-dis-2.c: Re-generate.
2835
f4950f76
JB		 28362020-01-03 Jan Beulich <jbeulich@suse.com>
2837
5437a02a 2838 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2839 FMMLA encoding.
2840 * opcodes/aarch64-dis-2.c: Re-generate.
2841
6655dba2
SB		 28422020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2843
2844 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2845
b14ce8bf
AM		 28462020-01-01 Alan Modra <amodra@gmail.com>
2847
2848 Update year range in copyright notice of all files.
2849
0b114740 2850For older changes see ChangeLog-2019
3499769a 2851\f
0b114740 2852Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2853
2854Copying and distribution of this file, with or without modification,
2855are permitted in any medium without royalty provided the copyright
2856notice and this notice are preserved.
2857
2858Local Variables:
2859mode: change-log
2860left-margin: 8
2861fill-column: 74
2862version-control: never
2863End:
A mirror of the official binutils-gdb repository