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S/390: Fix instruction type of troo, trot, trto, and trtt.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
3f94e60d
NC		 12015-10-08 Nick Clifton <nickc@redhat.com>
2
3 * arc-dis.c (print_insn_arc): Initiallise insn array.
4
875880c6
YQ		 52015-10-07 Yao Qi <yao.qi@linaro.org>
6
7 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
8 'name' rather than 'template'.
9 * aarch64-opc.c (aarch64_print_operand): Likewise.
10
886a2506
NC		 112015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
12
13 * arc-dis.c: Revamped file for ARC support
14 * arc-dis.h: Likewise.
15 * arc-ext.c: Likewise.
16 * arc-ext.h: Likewise.
17 * arc-opc.c: Likewise.
18 * arc-fxi.h: New file.
19 * arc-regs.h: Likewise.
20 * arc-tbl.h: Likewise.
21
36f4aab1
YQ		 222015-10-02 Yao Qi <yao.qi@linaro.org>
23
24 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
25 argument insn type to aarch64_insn. Rename to ...
26 (aarch64_decode_insn): ... it.
27 (print_insn_aarch64_word): Caller updated.
28
7232d389
YQ		 292015-10-02 Yao Qi <yao.qi@linaro.org>
30
31 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
32 (print_insn_aarch64_word): Caller updated.
33
7ecc513a
DV		 342015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
35
36 * s390-mkopc.c (main): Parse htm and vx flag.
37 * s390-opc.txt: Mark instructions from the hardware transactional
38 memory and vector facilities with the "htm"/"vx" flag.
39
b08b78e7
NC		 402015-09-28 Nick Clifton <nickc@redhat.com>
41
42 * po/de.po: Updated German translation.
43
36f7a941
TR		 442015-09-28 Tom Rix <tom@bumblecow.com>
45
46 * ppc-opc.c (PPC500): Mark some opcodes as invalid
47
b6518b38
NC		 482015-09-23 Nick Clifton <nickc@redhat.com>
49
50 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
51 function.
52 * tic30-dis.c (print_branch): Likewise.
53 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
54 value before left shifting.
55 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
56 * hppa-dis.c (print_insn_hppa): Likewise.
57 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
58 array.
59 * msp430-dis.c (msp430_singleoperand): Likewise.
60 (msp430_doubleoperand): Likewise.
61 (print_insn_msp430): Likewise.
62 * nds32-asm.c (parse_operand): Likewise.
63 * sh-opc.h (MASK): Likewise.
64 * v850-dis.c (get_operand_value): Likewise.
65
f04265ec
NC		 662015-09-22 Nick Clifton <nickc@redhat.com>
67
68 * rx-decode.opc (bwl): Use RX_Bad_Size.
69 (sbwl): Likewise.
70 (ubwl): Likewise. Rename to ubw.
71 (uBWL): Rename to uBW.
72 Replace all references to uBWL with uBW.
73 * rx-decode.c: Regenerate.
74 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
75 (opsize_names): Likewise.
76 (print_insn_rx): Detect and report RX_Bad_Size.
77
6dca4fd1
AB		 782015-09-22 Anton Blanchard <anton@samba.org>
79
80 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
81
38074311
JM		 822015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
83
84 * sparc-dis.c (print_insn_sparc): Handle the privileged register
85 %pmcdper.
86
5f40e14d
JS		 872015-08-24 Jan Stancek <jstancek@redhat.com>
88
89 * i386-dis.c (print_insn): Fix decoding of three byte operands.
90
ab4e4ed5
AF		 912015-08-21 Alexander Fomin <alexander.fomin@intel.com>
92
93 PR binutils/18257
94 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
95 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
96 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
97 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
98 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
99 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
100 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
101 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
102 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
103 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
104 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
105 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
106 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
107 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
108 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
109 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
110 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
111 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
112 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
113 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
114 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
115 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
116 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
117 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
118 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
119 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
120 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
121 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
122 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
123 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
124 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
125 (vex_w_table): Replace terminals with MOD_TABLE entries for
126 most of mask instructions.
127
919b75f7
AM		 1282015-08-17 Alan Modra <amodra@gmail.com>
129
130 * cgen.sh: Trim trailing space from cgen output.
131 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
132 (print_dis_table): Likewise.
133 * opc2c.c (dump_lines): Likewise.
134 (orig_filename): Warning fix.
135 * ia64-asmtab.c: Regenerate.
136
4ab90a7a
AV		 1372015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
138
139 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
140 and higher with ARM instruction set will now mark the 26-bit
141 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
142 (arm_opcodes): Fix for unpredictable nop being recognized as a
143 teq.
144
40fc1451
SD		 1452015-08-12 Simon Dardis <simon.dardis@imgtec.com>
146
147 * micromips-opc.c (micromips_opcodes): Re-order table so that move
148 based on 'or' is first.
149 * mips-opc.c (mips_builtin_opcodes): Ditto.
150
922c5db5
NC		 1512015-08-11 Nick Clifton <nickc@redhat.com>
152
153 PR 18800
154 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
155 instruction.
156
75fb7498
RS		 1572015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
158
159 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
160
36aed29d
AP		 1612015-08-07 Amit Pawar <Amit.Pawar@amd.com>
162
163 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
164 * i386-init.h: Regenerated.
165
a8484f96
L		 1662015-07-30 H.J. Lu <hongjiu.lu@intel.com>
167
168 PR binutils/13571
169 * i386-dis.c (MOD_0FC3): New.
170 (PREFIX_0FC3): Renamed to ...
171 (PREFIX_MOD_0_0FC3): This.
172 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
173 (prefix_table): Replace Ma with Ev on movntiS.
174 (mod_table): Add MOD_0FC3.
175
37a42ee9
L		 1762015-07-27 H.J. Lu <hongjiu.lu@intel.com>
177
178 * configure: Regenerated.
179
070fe95d
AM		 1802015-07-23 Alan Modra <amodra@gmail.com>
181
182 PR 18708
183 * i386-dis.c (get64): Avoid signed integer overflow.
184
20c2a615
L		 1852015-07-22 Alexander Fomin <alexander.fomin@intel.com>
186
187 PR binutils/18631
188 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
189 "EXEvexHalfBcstXmmq" for the second operand.
190 (EVEX_W_0F79_P_2): Likewise.
191 (EVEX_W_0F7A_P_2): Likewise.
192 (EVEX_W_0F7B_P_2): Likewise.
193
6f1c2142
AM		 1942015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
195
196 * arm-dis.c (print_insn_coprocessor): Added support for quarter
197 float bitfield format.
198 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
199 quarter float bitfield format.
200
8a643cc3
L		 2012015-07-14 H.J. Lu <hongjiu.lu@intel.com>
202
203 * configure: Regenerated.
204
ef5a96d5
AM		 2052015-07-03 Alan Modra <amodra@gmail.com>
206
207 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
208 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
209 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
210
c8c8175b
SL		 2112015-07-01 Sandra Loosemore <sandra@codesourcery.com>
212 Cesar Philippidis <cesar@codesourcery.com>
213
214 * nios2-dis.c (nios2_extract_opcode): New.
215 (nios2_disassembler_state): New.
216 (nios2_find_opcode_hash): Use mach parameter to select correct
217 disassembler state.
218 (nios2_print_insn_arg): Extend to support new R2 argument letters
219 and formats.
220 (print_insn_nios2): Check for 16-bit instruction at end of memory.
221 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
222 (NIOS2_NUM_OPCODES): Rename to...
223 (NIOS2_NUM_R1_OPCODES): This.
224 (nios2_r2_opcodes): New.
225 (NIOS2_NUM_R2_OPCODES): New.
226 (nios2_num_r2_opcodes): New.
227 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
228 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
229 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
230 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
231 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
232
9916071f
AP		 2332015-06-30 Amit Pawar <Amit.Pawar@amd.com>
234
235 * i386-dis.c (OP_Mwaitx): New.
236 (rm_table): Add monitorx/mwaitx.
237 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
238 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
239 (operand_type_init): Add CpuMWAITX.
240 * i386-opc.h (CpuMWAITX): New.
241 (i386_cpu_flags): Add cpumwaitx.
242 * i386-opc.tbl: Add monitorx and mwaitx.
243 * i386-init.h: Regenerated.
244 * i386-tbl.h: Likewise.
245
7b934113
PB		 2462015-06-22 Peter Bergner <bergner@vnet.ibm.com>
247
248 * ppc-opc.c (insert_ls): Test for invalid LS operands.
249 (insert_esync): New function.
250 (LS, WC): Use insert_ls.
251 (ESYNC): Use insert_esync.
252
bdc4de1b
NC		 2532015-06-22 Nick Clifton <nickc@redhat.com>
254
255 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
256 requested region lies beyond it.
257 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
258 looking for 32-bit insns.
259 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
260 data.
261 * sh-dis.c (print_insn_sh): Likewise.
262 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
263 blocks of instructions.
264 * vax-dis.c (print_insn_vax): Check that the requested address
265 does not clash with the stop_vma.
266
11a0cf2e
PB		 2672015-06-19 Peter Bergner <bergner@vnet.ibm.com>
268
070fe95d 269 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 270 * ppc-opc.c (FXM4): Add non-zero optional value.
271 (TBR): Likewise.
272 (SXL): Likewise.
273 (insert_fxm): Handle new default operand value.
274 (extract_fxm): Likewise.
275 (insert_tbr): Likewise.
276 (extract_tbr): Likewise.
277
bdfa8b95
MW		 2782015-06-16 Matthew Wahab <matthew.wahab@arm.com>
279
280 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
281
24b4cf66
SN		 2822015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
283
284 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
285
99a2c561
PB		 2862015-06-12 Peter Bergner <bergner@vnet.ibm.com>
287
288 * ppc-opc.c: Add comment accidentally removed by old commit.
289 (MTMSRD_L): Delete.
290
40f77f82
AM		 2912015-06-04 Peter Bergner <bergner@vnet.ibm.com>
292
293 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
294
13be46a2
NC		 2952015-06-04 Nick Clifton <nickc@redhat.com>
296
297 PR 18474
298 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
299
ddfded2f
MW		 3002015-06-02 Matthew Wahab <matthew.wahab@arm.com>
301
302 * arm-dis.c (arm_opcodes): Add "setpan".
303 (thumb_opcodes): Add "setpan".
304
1af1dd51
MW		 3052015-06-02 Matthew Wahab <matthew.wahab@arm.com>
306
307 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
308 macros.
309
9e1f0fa7
MW		 3102015-06-02 Matthew Wahab <matthew.wahab@arm.com>
311
312 * aarch64-tbl.h (aarch64_feature_rdma): New.
313 (RDMA): New.
314 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
315 * aarch64-asm-2.c: Regenerate.
316 * aarch64-dis-2.c: Regenerate.
317 * aarch64-opc-2.c: Regenerate.
318
290806fd
MW		 3192015-06-02 Matthew Wahab <matthew.wahab@arm.com>
320
321 * aarch64-tbl.h (aarch64_feature_lor): New.
322 (LOR): New.
323 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
324 "stllrb", "stllrh".
325 * aarch64-asm-2.c: Regenerate.
326 * aarch64-dis-2.c: Regenerate.
327 * aarch64-opc-2.c: Regenerate.
328
f21cce2c
MW		 3292015-06-01 Matthew Wahab <matthew.wahab@arm.com>
330
331 * aarch64-opc.c (F_ARCHEXT): New.
332 (aarch64_sys_regs): Add "pan".
333 (aarch64_sys_reg_supported_p): New.
334 (aarch64_pstatefields): Add "pan".
335 (aarch64_pstatefield_supported_p): New.
336
d194d186
JB		 3372015-06-01 Jan Beulich <jbeulich@suse.com>
338
339 * i386-tbl.h: Regenerate.
340
3a8547d2
JB		 3412015-06-01 Jan Beulich <jbeulich@suse.com>
342
343 * i386-dis.c (print_insn): Swap rounding mode specifier and
344 general purpose register in Intel mode.
345
015c54d5
JB		 3462015-06-01 Jan Beulich <jbeulich@suse.com>
347
348 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
349 * i386-tbl.h: Regenerate.
350
071f0063
L		 3512015-05-18 H.J. Lu <hongjiu.lu@intel.com>
352
353 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
354 * i386-init.h: Regenerated.
355
5db04b09
L		 3562015-05-15 H.J. Lu <hongjiu.lu@intel.com>
357
358 PR binutis/18386
359 * i386-dis.c: Add comments for '@'.
360 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
361 (enum x86_64_isa): New.
362 (isa64): Likewise.
363 (print_i386_disassembler_options): Add amd64 and intel64.
364 (print_insn): Handle amd64 and intel64.
365 (putop): Handle '@'.
366 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
367 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
368 * i386-opc.h (AMD64): New.
369 (CpuIntel64): Likewise.
370 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
371 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
372 Mark direct call/jmp without Disp16|Disp32 as Intel64.
373 * i386-init.h: Regenerated.
374 * i386-tbl.h: Likewise.
375
4bc0608a
PB		 3762015-05-14 Peter Bergner <bergner@vnet.ibm.com>
377
378 * ppc-opc.c (IH) New define.
379 (powerpc_opcodes) <wait>: Do not enable for POWER7.
380 <tlbie>: Add RS operand for POWER7.
381 <slbia>: Add IH operand for POWER6.
382
70cead07
L		 3832015-05-11 H.J. Lu <hongjiu.lu@intel.com>
384
385 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
386 direct branch.
387 (jmp): Likewise.
388 * i386-tbl.h: Regenerated.
389
7b6d09fb
L		 3902015-05-11 H.J. Lu <hongjiu.lu@intel.com>
391
392 * configure.ac: Support bfd_iamcu_arch.
393 * disassemble.c (disassembler): Support bfd_iamcu_arch.
394 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
395 CPU_IAMCU_COMPAT_FLAGS.
396 (cpu_flags): Add CpuIAMCU.
397 * i386-opc.h (CpuIAMCU): New.
398 (i386_cpu_flags): Add cpuiamcu.
399 * configure: Regenerated.
400 * i386-init.h: Likewise.
401 * i386-tbl.h: Likewise.
402
31955f99
L		 4032015-05-08 H.J. Lu <hongjiu.lu@intel.com>
404
405 PR binutis/18386
406 * i386-dis.c (X86_64_E8): New.
407 (X86_64_E9): Likewise.
408 Update comments on 'T', 'U', 'V'. Add comments for '^'.
409 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
410 (x86_64_table): Add X86_64_E8 and X86_64_E9.
411 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
412 (putop): Handle '^'.
413 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
414 REX_W.
415
0952813b
DD		 4162015-04-30 DJ Delorie <dj@redhat.com>
417
418 * disassemble.c (disassembler): Choose suitable disassembler based
419 on E_ABI.
420 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
421 it to decode mul/div insns.
422 * rl78-decode.c: Regenerate.
423 * rl78-dis.c (print_insn_rl78): Rename to...
424 (print_insn_rl78_common): ...this, take ISA parameter.
425 (print_insn_rl78): New.
426 (print_insn_rl78_g10): New.
427 (print_insn_rl78_g13): New.
428 (print_insn_rl78_g14): New.
429 (rl78_get_disassembler): New.
430
f9d3ecaa
NC		 4312015-04-29 Nick Clifton <nickc@redhat.com>
432
433 * po/fr.po: Updated French translation.
434
4fff86c5
PB		 4352015-04-27 Peter Bergner <bergner@vnet.ibm.com>
436
437 * ppc-opc.c (DCBT_EO): New define.
438 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
439 <lharx>: Likewise.
440 <stbcx.>: Likewise.
441 <sthcx.>: Likewise.
442 <waitrsv>: Do not enable for POWER7 and later.
443 <waitimpl>: Likewise.
444 <dcbt>: Default to the two operand form of the instruction for all
445 "old" cpus. For "new" cpus, use the operand ordering that matches
446 whether the cpu is server or embedded.
447 <dcbtst>: Likewise.
448
3b78cfe1
AK		 4492015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
450
451 * s390-opc.c: New instruction type VV0UU2.
452 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
453 and WFC.
454
04d824a4
JB		 4552015-04-23 Jan Beulich <jbeulich@suse.com>
456
457 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
458 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
459 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
460 (vfpclasspd, vfpclassps): Add %XZ.
461
09708981
L		 4622015-04-15 H.J. Lu <hongjiu.lu@intel.com>
463
464 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
465 (PREFIX_UD_REPZ): Likewise.
466 (PREFIX_UD_REPNZ): Likewise.
467 (PREFIX_UD_DATA): Likewise.
468 (PREFIX_UD_ADDR): Likewise.
469 (PREFIX_UD_LOCK): Likewise.
470
3888916d
L		 4712015-04-15 H.J. Lu <hongjiu.lu@intel.com>
472
473 * i386-dis.c (prefix_requirement): Removed.
474 (print_insn): Don't set prefix_requirement. Check
475 dp->prefix_requirement instead of prefix_requirement.
476
f24bcbaa
L		 4772015-04-15 H.J. Lu <hongjiu.lu@intel.com>
478
479 PR binutils/17898
480 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
481 (PREFIX_MOD_0_0FC7_REG_6): This.
482 (PREFIX_MOD_3_0FC7_REG_6): New.
483 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
484 (prefix_table): Replace PREFIX_0FC7_REG_6 with
485 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
486 PREFIX_MOD_3_0FC7_REG_7.
487 (mod_table): Replace PREFIX_0FC7_REG_6 with
488 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
489 PREFIX_MOD_3_0FC7_REG_7.
490
507bd325
L		 4912015-04-15 H.J. Lu <hongjiu.lu@intel.com>
492
493 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
494 (PREFIX_MANDATORY_REPNZ): Likewise.
495 (PREFIX_MANDATORY_DATA): Likewise.
496 (PREFIX_MANDATORY_ADDR): Likewise.
497 (PREFIX_MANDATORY_LOCK): Likewise.
498 (PREFIX_MANDATORY): Likewise.
499 (PREFIX_UD_SHIFT): Set to 8
500 (PREFIX_UD_REPZ): Updated.
501 (PREFIX_UD_REPNZ): Likewise.
502 (PREFIX_UD_DATA): Likewise.
503 (PREFIX_UD_ADDR): Likewise.
504 (PREFIX_UD_LOCK): Likewise.
505 (PREFIX_IGNORED_SHIFT): New.
506 (PREFIX_IGNORED_REPZ): Likewise.
507 (PREFIX_IGNORED_REPNZ): Likewise.
508 (PREFIX_IGNORED_DATA): Likewise.
509 (PREFIX_IGNORED_ADDR): Likewise.
510 (PREFIX_IGNORED_LOCK): Likewise.
511 (PREFIX_OPCODE): Likewise.
512 (PREFIX_IGNORED): Likewise.
513 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
514 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
515 (three_byte_table): Likewise.
516 (mod_table): Likewise.
517 (mandatory_prefix): Renamed to ...
518 (prefix_requirement): This.
519 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
520 Update PREFIX_90 entry.
521 (get_valid_dis386): Check prefix_requirement to see if a prefix
522 should be ignored.
523 (print_insn): Replace mandatory_prefix with prefix_requirement.
524
f0fba320
RL		 5252015-04-15 Renlin Li <renlin.li@arm.com>
526
527 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
528 use it for ssat and ssat16.
529 (print_insn_thumb32): Add handle case for 'D' control code.
530
bf890a93
IT		 5312015-04-06 Ilya Tocar <ilya.tocar@intel.com>
532 H.J. Lu <hongjiu.lu@intel.com>
533
534 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
535 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
536 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
537 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
538 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
539 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
540 Fill prefix_requirement field.
541 (struct dis386): Add prefix_requirement field.
542 (dis386): Fill prefix_requirement field.
543 (dis386_twobyte): Ditto.
544 (twobyte_has_mandatory_prefix_: Remove.
545 (reg_table): Fill prefix_requirement field.
546 (prefix_table): Ditto.
547 (x86_64_table): Ditto.
548 (three_byte_table): Ditto.
549 (xop_table): Ditto.
550 (vex_table): Ditto.
551 (vex_len_table): Ditto.
552 (vex_w_table): Ditto.
553 (mod_table): Ditto.
554 (bad_opcode): Ditto.
555 (print_insn): Use prefix_requirement.
556 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
557 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
558 (float_reg): Ditto.
559
2f783c1f
MF		 5602015-03-30 Mike Frysinger <vapier@gentoo.org>
561
562 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
563
b9d94d62
L		 5642015-03-29 H.J. Lu <hongjiu.lu@intel.com>
565
566 * Makefile.in: Regenerated.
567
27c49e9a
AB		 5682015-03-25 Anton Blanchard <anton@samba.org>
569
570 * ppc-dis.c (disassemble_init_powerpc): Only initialise
571 powerpc_opcd_indices and vle_opcd_indices once.
572
c4e676f1
AB		 5732015-03-25 Anton Blanchard <anton@samba.org>
574
575 * ppc-opc.c (powerpc_opcodes): Add slbfee.
576
823d2571
TG		 5772015-03-24 Terry Guo <terry.guo@arm.com>
578
579 * arm-dis.c (opcode32): Updated to use new arm feature struct.
580 (opcode16): Likewise.
581 (coprocessor_opcodes): Replace bit with feature struct.
582 (neon_opcodes): Likewise.
583 (arm_opcodes): Likewise.
584 (thumb_opcodes): Likewise.
585 (thumb32_opcodes): Likewise.
586 (print_insn_coprocessor): Likewise.
587 (print_insn_arm): Likewise.
588 (select_arm_features): Follow new feature struct.
589
029f3522
GG		 5902015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
591
592 * i386-dis.c (rm_table): Add clzero.
593 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
594 Add CPU_CLZERO_FLAGS.
595 (cpu_flags): Add CpuCLZERO.
596 * i386-opc.h: Add CpuCLZERO.
597 * i386-opc.tbl: Add clzero.
598 * i386-init.h: Re-generated.
599 * i386-tbl.h: Re-generated.
600
6914869a
AB		 6012015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
602
603 * mips-opc.c (decode_mips_operand): Fix constraint issues
604 with u and y operands.
605
21e20815
AB		 6062015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
607
608 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
609
6b1d7593
AK		 6102015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
611
612 * s390-opc.c: Add new IBM z13 instructions.
613 * s390-opc.txt: Likewise.
614
c8f89a34
JW		 6152015-03-10 Renlin Li <renlin.li@arm.com>
616
617 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
618 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
619 related alias.
620 * aarch64-asm-2.c: Regenerate.
621 * aarch64-dis-2.c: Likewise.
622 * aarch64-opc-2.c: Likewise.
623
d8282f0e
JW		 6242015-03-03 Jiong Wang <jiong.wang@arm.com>
625
626 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
627
ac994365
OE		 6282015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
629
630 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
631 arch_sh_up.
632 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
633 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
634
fd63f640
V		 6352015-02-23 Vinay <Vinay.G@kpit.com>
636
637 * rl78-decode.opc (MOV): Added space between two operands for
638 'mov' instruction in index addressing mode.
639 * rl78-decode.c: Regenerate.
640
f63c1776
PA		 6412015-02-19 Pedro Alves <palves@redhat.com>
642
643 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
644
07774fcc
PA		 6452015-02-10 Pedro Alves <palves@redhat.com>
646 Tom Tromey <tromey@redhat.com>
647
648 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
649 microblaze_and, microblaze_xor.
650 * microblaze-opc.h (opcodes): Adjust.
651
3f8107ab
AM		 6522015-01-28 James Bowman <james.bowman@ftdichip.com>
653
654 * Makefile.am: Add FT32 files.
655 * configure.ac: Handle FT32.
656 * disassemble.c (disassembler): Call print_insn_ft32.
657 * ft32-dis.c: New file.
658 * ft32-opc.c: New file.
659 * Makefile.in: Regenerate.
660 * configure: Regenerate.
661 * po/POTFILES.in: Regenerate.
662
e5fe4957
KLC		 6632015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
664
665 * nds32-asm.c (keyword_sr): Add new system registers.
666
1e2e8c52
AK		 6672015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
668
669 * s390-dis.c (s390_extract_operand): Support vector register
670 operands.
671 (s390_print_insn_with_opcode): Support new operands types and add
672 new handling of optional operands.
673 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
674 and include opcode/s390.h instead.
675 (struct op_struct): New field `flags'.
676 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
677 (dumpTable): Dump flags.
678 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
679 string.
680 * s390-opc.c: Add new operands types, instruction formats, and
681 instruction masks.
682 (s390_opformats): Add new formats for .insn.
683 * s390-opc.txt: Add new instructions.
684
b90efa5b 6852015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 686
b90efa5b 687 Update year range in copyright notice of all files.
bffb6004 688
b90efa5b 689For older changes see ChangeLog-2014
252b5132 690\f
b90efa5b 691Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 692
693Copying and distribution of this file, with or without modification,
694are permitted in any medium without royalty provided the copyright
695notice and this notice are preserved.
696
252b5132 697Local Variables:
2f6d2f85
NC		 698mode: change-log
699left-margin: 8
700fill-column: 74
252b5132
RH		 701version-control: never
702End:
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