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CSKY: Support two operands form for bloop.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
d285ba8d
CQ		 12020-08-21 Cooper Qu <cooper.qu@linux.alibaba.com>
2
3 * csky-opc.h (csky_v2_opcodes): Add two operands form for bloop.
4
18a8a00e
AM		 52020-08-19 Alan Modra <amodra@gmail.com>
6
7 * ppc-opc.c (powerpc_opcodes): Replace OBF with BF for vcmpsq,
8 vcmpuq and xvtlsbb.
9
587a4371
PB		 102020-08-18 Peter Bergner <bergner@linux.ibm.com>
11
12 * ppc-opc.c (powerpc_opcodes) <xvcvbf16sp>: Rename from this...
13 <xvcvbf16spn>: ...to this.
14
2e49fd1e
AC		 152020-08-12 Alex Coplan <alex.coplan@arm.com>
16
17 * aarch64-opc.c (aarch64_sys_regs): Add MPAM registers.
18
79ddc884
NC		 192020-08-12 Nick Clifton <nickc@redhat.com>
20
21 * po/sr.po: Updated Serbian translation.
22
08770ec2
AM		 232020-08-11 Alan Modra <amodra@gmail.com>
24
25 * ppc-opc.c (powerpc_opcodes): Move cctpl, cctpm and cctph.
26
f7cb161e
PW		 272020-08-10 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
28
29 * aarch64-opc.c (aarch64_print_operand):
30 (aarch64_sys_reg_deprecated_p): Functions paramaters changed.
31 (aarch64_sys_reg_supported_p): Function removed.
32 (aarch64_sys_ins_reg_supported_p): Functions paramaters changed.
33 (aarch64_sys_ins_reg_supported_p): Merged aarch64_sys_reg_supported_p
34 into this function.
35
3eb65174
AM		 362020-08-10 Alan Modra <amodra@gmail.com>
37
38 * ppc-opc.c (powerpc_opcodes): Add many mtspr and mfspr extended
39 instructions.
40
8b2742a1
AM		 412020-08-10 Alan Modra <amodra@gmail.com>
42
43 * ppc-opc.c (powerpc_opcodes): Add exser, msgsndu, msgclru.
44 Enable icbt for power5, miso for power8.
45
5fbec329
AM		 462020-08-10 Alan Modra <amodra@gmail.com>
47
48 * ppc-opc.c (powerpc_opcodes): Prioritise mtfprd and mtvrd over
49 mtvsrd, and similarly for mfvsrd.
50
563a3225
CG		 512020-08-04 Christian Groessler <chris@groessler.org>
52 Tadashi G. Takaoka <tadashi.g.takaoka@gmail.com>
53
54 * z8kgen.c (opt): Fix "sout imm16,rs" and "soutb imm16,rbs"
55 opcodes (special "out" to absolute address).
56 * z8k-opc.h: Regenerate.
57
41eb8e88
L		 582020-07-30 H.J. Lu <hongjiu.lu@intel.com>
59
60 PR gas/26305
61 * i386-opc.h (Prefix_Disp8): New.
62 (Prefix_Disp16): Likewise.
63 (Prefix_Disp32): Likewise.
64 (Prefix_Load): Likewise.
65 (Prefix_Store): Likewise.
66 (Prefix_VEX): Likewise.
67 (Prefix_VEX3): Likewise.
68 (Prefix_EVEX): Likewise.
69 (Prefix_REX): Likewise.
70 (Prefix_NoOptimize): Likewise.
71 * i386-opc.tbl: Use Prefix_XXX on pseudo prefixes. Add {disp16}.
72 * i386-tbl.h: Regenerated.
73
98116973
AA		 742020-07-29 Andreas Arnez <arnez@linux.ibm.com>
75
76 * s390-mkopc.c (insertExpandedMnemonic): Handle unreachable
77 default case with abort() instead of printing an error message and
78 continuing, to avoid a maybe-uninitialized warning.
79
2dddfa20
NC		 802020-07-24 Nick Clifton <nickc@redhat.com>
81
82 * po/de.po: Updated German translation.
83
bf4ba07c
JB		 842020-07-21 Jan Beulich <jbeulich@suse.com>
85
86 * i386-dis.c (OP_E_memory): Revert previous change.
87
04c662e2
L		 882020-07-15 H.J. Lu <hongjiu.lu@intel.com>
89
90 PR gas/26237
91 * i386-dis.c (OP_E_memory): Don't display eiz with no scale
92 without base nor index registers.
93
f0e8d0ba
JB		 942020-07-15 Jan Beulich <jbeulich@suse.com>
95
96 * i386-dis.c (putop): Move 'V' and 'W' handling.
97
c3f5525f
JB		 982020-07-15 Jan Beulich <jbeulich@suse.com>
99
100 * i386-dis.c (dis386): Adjust 'V' description. Use P-based
101 construct for push/pop of register.
102 (putop): Honor cond when handling 'P'. Drop handling of plain
103 'V'.
104
36938cab
JB		 1052020-07-15 Jan Beulich <jbeulich@suse.com>
106
107 * i386-dis.c (dis386): Adjust 'P', 'T', 'U', and '@'
108 description. Drop '&' description. Use P for push of immediate,
109 pushf/popf, enter, and leave. Use %LP for lret/retf.
110 (dis386_twobyte): Use P for push/pop of fs/gs.
111 (reg_table): Use P for push/pop. Use @ for near call/jmp.
112 (x86_64_table): Use P for far call/jmp.
113 (putop): Drop handling of 'U' and '&'. Move and adjust handling
114 of '@'. Adjust handling of 'P' and 'T'. Drop case_P and case_Q
115 labels.
116 (OP_J): Drop marking of REX_W as used for v_mode (ISA-dependent)
117 and dqw_mode (unconditional).
118
8e58ef80
L		 1192020-07-14 H.J. Lu <hongjiu.lu@intel.com>
120
121 PR gas/26237
122 * i386-dis.c (OP_E_memory): Without base nor index registers,
123 32-bit displacement to 64 bits.
124
570b0ed6
CZ		 1252020-07-14 Claudiu Zissulescu <claziss@gmail.com>
126
127 * arc-dis.c (print_insn_arc): Detect and emit a warning when a
128 faulty double register pair is detected.
129
bfbd9438
JB		 1302020-07-14 Jan Beulich <jbeulich@suse.com>
131
132 * i386-dis.c (OP_D): Print dr<N> instead of db<N> in Intel mode.
133
78467458
JB		 1342020-07-14 Jan Beulich <jbeulich@suse.com>
135
136 * i386-dis.c (OP_R, Rm): Delete.
137 (MOD_0F24, MOD_0F26): Rename to ...
138 (X86_64_0F24, X86_64_0F26): ... respectively.
139 (dis386): Update 'L' and 'Z' comments.
140 (dis386_twobyte): Replace Rm by Em. Change opcode 0F24 and 0F26
141 table references.
142 (mod_table): Move opcode 0F24 and 0F26 entries ...
143 (x86_64_table): ... here.
144 (putop): Drop handling of 'L'. Set modrm.mod to 3 for 'Z'. Move
145 'Z' case block.
146
464d2b65
JB		 1472020-07-14 Jan Beulich <jbeulich@suse.com>
148
149 * i386-dis.c (Rd, Rdq, MaskR): Delete.
150 (MOD_EVEX_0F3828_P_1, MOD_EVEX_0F382A_P_1_W_1,
151 MOD_EVEX_0F3838_P_1, MOD_EVEX_0F383A_P_1_W_0,
152 MOD_EVEX_0F387A_W_0, MOD_EVEX_0F387B_W_0,
153 MOD_EVEX_0F387C): New enumerators.
154 (reg_table): Use Edq for rdssp.
155 (prefix_table): Use Edq for incssp.
156 (mod_table): Use Rm for move to/from %tr. Use MaskE for kand*,
157 kandn*, knot*, kor*, kxnor*, kxor*, kadd*, kunpck*, kortest*,
158 ktest*, and kshift*. Use Edq / MaskE for kmov*.
159 * i386-dis-evex.h: Reference mod_table[] for opcode 0F387C.
160 * i386-dis-evex-mod.h: New entries for opcodes 0F3828, 0F382A,
161 0F3838, 0F383A, 0F387A, 0F387B, and 0F387C.
162 * i386-dis-evex-prefix.h: Reference mod_table[] for opcodes
163 0F3828_P_1 and 0F3838_P_1.
164 * i386-dis-evex-w.h: Reference mod_table[] for opcodes
165 0F382A_P_1, 0F383A_P_1, 0F387A, and 0F387B.
166
035e7389
JB		 1672020-07-14 Jan Beulich <jbeulich@suse.com>
168
169 * i386-dis.c (PREFIX_0F01_REG_7_MOD_3_RM_3,
170 PREFIX_0FAE_REG_5_MOD_0, PREFIX_0FC3_MOD_0, PREFIX_0F38C8,
171 PREFIX_0F38C9, PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC,
172 PREFIX_0F38CD, PREFIX_0F38F9, PREFIX_0F3ACC, PREFIX_VEX_0F77,
173 PREFIX_VEX_0F38F2, PREFIX_VEX_0F38F3_REG_1,
174 PREFIX_VEX_0F38F3_REG_2, PREFIX_VEX_0F38F3_REG_3): Delete.
175 (MOD_0F38F9_PREFIX_0, VEX_LEN_0F77_P_0, VEX_LEN_0F38F2_P_0,
176 VEX_LEN_0F38F3_R_1_P_0, VEX_LEN_0F38F3_R_2_P_0,
177 VEX_LEN_0F38F3_R_3_P_0): Rename to ...
178 (MOD_0F38F9, VEX_LEN_0F77, VEX_LEN_0F38F2, VEX_LEN_0F38F3_R_1,
179 VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3): ... these respectively.
180 (reg_table, prefix_table, three_byte_table, vex_table,
181 vex_len_table, mod_table, rm_table): Replace / remove respective
182 entries.
183 (intel_operand_size, OP_E_register, OP_G): Avoid undue setting
184 of PREFIX_DATA in used_prefixes.
185
bb5b3501
JB		 1862020-07-14 Jan Beulich <jbeulich@suse.com>
187
188 * i386-dis.c (MOD_VEX_0F3A30_L_0_W_0, MOD_VEX_0F3A30_L_0_W_1,
189 MOD_VEX_0F3A31_L_0_W_0, MOD_VEX_0F3A31_L_0_W_1,
190 MOD_VEX_0F3A32_L_0_W_0, MOD_VEX_0F3A32_L_0_W_1,
191 MOD_VEX_0F3A33_L_0_W_0, MOD_VEX_0F3A33_L_0_W_1): Replace by ...
192 (MOD_VEX_0F3A30_L_0, MOD_VEX_0F3A31_L_0,
193 MOD_VEX_0F3A32_L_0, MOD_VEX_0F3A33_L_0): ... these.
194 (VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
195 VEX_W_0F3A33_L_0): Delete.
196 (dis386): Adjust "BW" description.
197 (vex_len_table): Refer to mod_table[] for opcodes 0F3A30,
198 0F3A31, 0F3A32, and 0F3A33.
199 (vex_w_table): Delete opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
200 entries.
201 (mod_table): Replace opcode 0F3A30, 0F3A31, 0F3A32, and 0F3A33
202 entries.
203
7531c613
JB		 2042020-07-14 Jan Beulich <jbeulich@suse.com>
205
206 * i386-dis.c (PREFIX_0F6C, PREFIX_0F6D, PREFIX_0F73_REG_3,
207 PREFIX_0F73_REG_7, PREFIX_0F3810, PREFIX_0F3814, PREFIX_0F3815,
208 PREFIX_0F3817, PREFIX_0F3820, PREFIX_0F3821, PREFIX_0F3822,
209 PREFIX_0F3823, PREFIX_0F3824, PREFIX_0F3825, PREFIX_0F3828,
210 PREFIX_0F3829, PREFIX_0F382A, PREFIX_0F382B, PREFIX_0F3830,
211 PREFIX_0F3831, PREFIX_0F3832, PREFIX_0F3833, PREFIX_0F3834,
212 PREFIX_0F3835, PREFIX_0F3837, PREFIX_0F3838, PREFIX_0F3839,
213 PREFIX_0F383A, PREFIX_0F383B, PREFIX_0F383C, PREFIX_0F383D,
214 PREFIX_0F383E, PREFIX_0F383F, PREFIX_0F3840, PREFIX_0F3841,
215 PREFIX_0F3880, PREFIX_0F3881, PREFIX_0F3882, PREFIX_0F38CF,
216 PREFIX_0F38DB, PREFIX_0F38DC, PREFIX_0F38DD, PREFIX_0F38DE,
217 PREFIX_0F38DF, PREFIX_0F38F5, PREFIX_0F3A08, PREFIX_0F3A09,
218 PREFIX_0F3A0A, PREFIX_0F3A0B, PREFIX_0F3A0C, PREFIX_0F3A0D,
219 PREFIX_0F3A0E, PREFIX_0F3A14, PREFIX_0F3A15, PREFIX_0F3A16,
220 PREFIX_0F3A17, PREFIX_0F3A20, PREFIX_0F3A21, PREFIX_0F3A22,
221 PREFIX_0F3A40, PREFIX_0F3A41, PREFIX_0F3A42, PREFIX_0F3A44,
222 PREFIX_0F3A60, PREFIX_0F3A61, PREFIX_0F3A62, PREFIX_0F3A63,
223 PREFIX_0F3ACE, PREFIX_0F3ACF, PREFIX_0F3ADF, PREFIX_VEX_0F60,
224 PREFIX_VEX_0F61, PREFIX_VEX_0F62, PREFIX_VEX_0F63,
225 PREFIX_VEX_0F64, PREFIX_VEX_0F65, PREFIX_VEX_0F66,
226 PREFIX_VEX_0F67, PREFIX_VEX_0F68, PREFIX_VEX_0F69,
227 PREFIX_VEX_0F6A, PREFIX_VEX_0F6B, PREFIX_VEX_0F6C,
228 PREFIX_VEX_0F6D, PREFIX_VEX_0F6E, PREFIX_VEX_0F71_REG_2,
229 PREFIX_VEX_0F71_REG_4, PREFIX_VEX_0F71_REG_6,
230 PREFIX_VEX_0F72_REG_2, PREFIX_VEX_0F72_REG_4,
231 PREFIX_VEX_0F72_REG_6, PREFIX_VEX_0F73_REG_2,
232 PREFIX_VEX_0F73_REG_3, PREFIX_VEX_0F73_REG_6,
233 PREFIX_VEX_0F73_REG_7, PREFIX_VEX_0F74,
234 PREFIX_VEX_0F75, PREFIX_VEX_0F76, PREFIX_VEX_0FC4,
235 PREFIX_VEX_0FC5, PREFIX_VEX_0FD1, PREFIX_VEX_0FD2,
236 PREFIX_VEX_0FD3, PREFIX_VEX_0FD4, PREFIX_VEX_0FD5,
237 PREFIX_VEX_0FD6, PREFIX_VEX_0FD7, PREFIX_VEX_0FD8,
238 PREFIX_VEX_0FD9, PREFIX_VEX_0FDA, PREFIX_VEX_0FDB,
239 PREFIX_VEX_0FDC, PREFIX_VEX_0FDD, PREFIX_VEX_0FDE,
240 PREFIX_VEX_0FDF, PREFIX_VEX_0FE0, PREFIX_VEX_0FE1,
241 PREFIX_VEX_0FE2, PREFIX_VEX_0FE3, PREFIX_VEX_0FE4,
242 PREFIX_VEX_0FE5, PREFIX_VEX_0FE7, PREFIX_VEX_0FE8,
243 PREFIX_VEX_0FE9, PREFIX_VEX_0FEA, PREFIX_VEX_0FEB,
244 PREFIX_VEX_0FEC, PREFIX_VEX_0FED, PREFIX_VEX_0FEE,
245 PREFIX_VEX_0FEF, PREFIX_VEX_0FF1, PREFIX_VEX_0FF2,
246 PREFIX_VEX_0FF3, PREFIX_VEX_0FF4, PREFIX_VEX_0FF5,
247 PREFIX_VEX_0FF6, PREFIX_VEX_0FF7, PREFIX_VEX_0FF8,
248 PREFIX_VEX_0FF9, PREFIX_VEX_0FFA, PREFIX_VEX_0FFB,
249 PREFIX_VEX_0FFC, PREFIX_VEX_0FFD, PREFIX_VEX_0FFE,
250 PREFIX_VEX_0F3800, PREFIX_VEX_0F3801, PREFIX_VEX_0F3802,
251 PREFIX_VEX_0F3803, PREFIX_VEX_0F3804, PREFIX_VEX_0F3805,
252 PREFIX_VEX_0F3806, PREFIX_VEX_0F3807, PREFIX_VEX_0F3808,
253 PREFIX_VEX_0F3809, PREFIX_VEX_0F380A, PREFIX_VEX_0F380B,
254 PREFIX_VEX_0F380C, PREFIX_VEX_0F380D, PREFIX_VEX_0F380E,
255 PREFIX_VEX_0F380F, PREFIX_VEX_0F3813, PREFIX_VEX_0F3816,
256 PREFIX_VEX_0F3817, PREFIX_VEX_0F3818, PREFIX_VEX_0F3819,
257 PREFIX_VEX_0F381A, PREFIX_VEX_0F381C, PREFIX_VEX_0F381D,
258 PREFIX_VEX_0F381E, PREFIX_VEX_0F3820, PREFIX_VEX_0F3821,
259 PREFIX_VEX_0F3822, PREFIX_VEX_0F3823, PREFIX_VEX_0F3824,
260 PREFIX_VEX_0F3825, PREFIX_VEX_0F3828, PREFIX_VEX_0F3829,
261 PREFIX_VEX_0F382A, PREFIX_VEX_0F382B, PREFIX_VEX_0F382C,
262 PREFIX_VEX_0F382D, PREFIX_VEX_0F382E, PREFIX_VEX_0F382F,
263 PREFIX_VEX_0F3830, PREFIX_VEX_0F3831, PREFIX_VEX_0F3832,
264 PREFIX_VEX_0F3833, PREFIX_VEX_0F3834, PREFIX_VEX_0F3835,
265 PREFIX_VEX_0F3836, PREFIX_VEX_0F3837, PREFIX_VEX_0F3838,
266 PREFIX_VEX_0F3839, PREFIX_VEX_0F383A, PREFIX_VEX_0F383B,
267 PREFIX_VEX_0F383C, PREFIX_VEX_0F383D, PREFIX_VEX_0F383E,
268 PREFIX_VEX_0F383F, PREFIX_VEX_0F3840, PREFIX_VEX_0F3841,
269 PREFIX_VEX_0F3845, PREFIX_VEX_0F3846, PREFIX_VEX_0F3847,
270 PREFIX_VEX_0F3858, PREFIX_VEX_0F3859, PREFIX_VEX_0F385A,
271 PREFIX_VEX_0F3878, PREFIX_VEX_0F3879, PREFIX_VEX_0F388C,
272 PREFIX_VEX_0F388E, PREFIX_VEX_0F3890, PREFIX_VEX_0F3891,
273 PREFIX_VEX_0F3892, PREFIX_VEX_0F3893, PREFIX_VEX_0F3896,
274 PREFIX_VEX_0F3897, PREFIX_VEX_0F3898, PREFIX_VEX_0F3899,
275 PREFIX_VEX_0F389A, PREFIX_VEX_0F389B, PREFIX_VEX_0F389C,
276 PREFIX_VEX_0F389D, PREFIX_VEX_0F389E, PREFIX_VEX_0F389F,
277 PREFIX_VEX_0F38A6, PREFIX_VEX_0F38A7, PREFIX_VEX_0F38A8,
278 PREFIX_VEX_0F38A9, PREFIX_VEX_0F38AA, PREFIX_VEX_0F38AB,
279 PREFIX_VEX_0F38AC, PREFIX_VEX_0F38AD, PREFIX_VEX_0F38AE,
280 PREFIX_VEX_0F38AF, PREFIX_VEX_0F38B6, PREFIX_VEX_0F38B7,
281 PREFIX_VEX_0F38B8, PREFIX_VEX_0F38B9, PREFIX_VEX_0F38BA,
282 PREFIX_VEX_0F38BB, PREFIX_VEX_0F38BC, PREFIX_VEX_0F38BD,
283 PREFIX_VEX_0F38BE, PREFIX_VEX_0F38BF, PREFIX_VEX_0F38CF,
284 PREFIX_VEX_0F38DB, PREFIX_VEX_0F38DC, PREFIX_VEX_0F38DD,
285 PREFIX_VEX_0F38DE, PREFIX_VEX_0F38DF, PREFIX_VEX_0F3A00,
286 PREFIX_VEX_0F3A01, PREFIX_VEX_0F3A02, PREFIX_VEX_0F3A04,
287 PREFIX_VEX_0F3A05, PREFIX_VEX_0F3A06, PREFIX_VEX_0F3A08,
288 PREFIX_VEX_0F3A09, PREFIX_VEX_0F3A0A, PREFIX_VEX_0F3A0B,
289 PREFIX_VEX_0F3A0C, PREFIX_VEX_0F3A0D, PREFIX_VEX_0F3A0E,
290 PREFIX_VEX_0F3A0F, PREFIX_VEX_0F3A14, PREFIX_VEX_0F3A15,
291 PREFIX_VEX_0F3A16, PREFIX_VEX_0F3A17, PREFIX_VEX_0F3A18,
292 PREFIX_VEX_0F3A19, PREFIX_VEX_0F3A1D, PREFIX_VEX_0F3A20,
293 PREFIX_VEX_0F3A21, PREFIX_VEX_0F3A22, PREFIX_VEX_0F3A30,
294 PREFIX_VEX_0F3A31, PREFIX_VEX_0F3A32, PREFIX_VEX_0F3A33,
295 PREFIX_VEX_0F3A38, PREFIX_VEX_0F3A39, PREFIX_VEX_0F3A40,
296 PREFIX_VEX_0F3A41, PREFIX_VEX_0F3A42, PREFIX_VEX_0F3A44,
297 PREFIX_VEX_0F3A46, PREFIX_VEX_0F3A48, PREFIX_VEX_0F3A49,
298 PREFIX_VEX_0F3A4A, PREFIX_VEX_0F3A4B, PREFIX_VEX_0F3A4C,
299 PREFIX_VEX_0F3A5C, PREFIX_VEX_0F3A5D, PREFIX_VEX_0F3A5E,
300 PREFIX_VEX_0F3A5F, PREFIX_VEX_0F3A60, PREFIX_VEX_0F3A61,
301 PREFIX_VEX_0F3A62, PREFIX_VEX_0F3A63, PREFIX_VEX_0F3A68,
302 PREFIX_VEX_0F3A69, PREFIX_VEX_0F3A6A, PREFIX_VEX_0F3A6B,
303 PREFIX_VEX_0F3A6C, PREFIX_VEX_0F3A6D, PREFIX_VEX_0F3A6E,
304 PREFIX_VEX_0F3A6F, PREFIX_VEX_0F3A78, PREFIX_VEX_0F3A79,
305 PREFIX_VEX_0F3A7A, PREFIX_VEX_0F3A7B, PREFIX_VEX_0F3A7C,
306 PREFIX_VEX_0F3A7D, PREFIX_VEX_0F3A7E, PREFIX_VEX_0F3A7F,
307 PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF, PREFIX_VEX_0F3ADF,
308 PREFIX_EVEX_0F64, PREFIX_EVEX_0F65, PREFIX_EVEX_0F66,
309 PREFIX_EVEX_0F6E, PREFIX_EVEX_0F71_REG_2,
310 PREFIX_EVEX_0F71_REG_4, PREFIX_EVEX_0F71_REG_6,
311 PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
312 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
313 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
314 PREFIX_EVEX_0F73_REG_3, PREFIX_EVEX_0F73_REG_6,
315 PREFIX_EVEX_0F73_REG_7, PREFIX_EVEX_0F74, PREFIX_EVEX_0F75,
316 PREFIX_EVEX_0F76, PREFIX_EVEX_0FC4, PREFIX_EVEX_0FC5,
317 PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB, PREFIX_EVEX_0FDF,
318 PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE7, PREFIX_EVEX_0FEB,
319 PREFIX_EVEX_0FEF, PREFIX_EVEX_0F380D, PREFIX_EVEX_0F3816,
320 PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A, PREFIX_EVEX_0F381B,
321 PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F, PREFIX_EVEX_0F382C,
322 PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
323 PREFIX_EVEX_0F383B, PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F,
324 PREFIX_EVEX_0F3840, PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843,
325 PREFIX_EVEX_0F3844, PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846,
326 PREFIX_EVEX_0F3847, PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D,
327 PREFIX_EVEX_0F384E, PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3850,
328 PREFIX_EVEX_0F3851, PREFIX_EVEX_0F3854, PREFIX_EVEX_0F3855,
329 PREFIX_EVEX_0F3859, PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B,
330 PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863, PREFIX_EVEX_0F3864,
331 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3866, PREFIX_EVEX_0F3870,
332 PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3875,
333 PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877, PREFIX_EVEX_0F387A,
334 PREFIX_EVEX_0F387B, PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387D,
335 PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F, PREFIX_EVEX_0F3883,
336 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
337 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F388D, PREFIX_EVEX_0F388F,
338 PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891, PREFIX_EVEX_0F3892,
339 PREFIX_EVEX_0F3893, PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1,
340 PREFIX_EVEX_0F38A2, PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38B4,
341 PREFIX_EVEX_0F38B5, PREFIX_EVEX_0F38C4,
342 PREFIX_EVEX_0F38C6_REG_1, PREFIX_EVEX_0F38C6_REG_2,
343 PREFIX_EVEX_0F38C6_REG_5, PREFIX_EVEX_0F38C6_REG_6,
344 PREFIX_EVEX_0F38C7_REG_1, PREFIX_EVEX_0F38C7_REG_2,
345 PREFIX_EVEX_0F38C7_REG_5, PREFIX_EVEX_0F38C7_REG_6,
346 PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA, PREFIX_EVEX_0F38CB,
347 PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD, PREFIX_EVEX_0F3A00,
348 PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03, PREFIX_EVEX_0F3A05,
349 PREFIX_EVEX_0F3A08, PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A,
350 PREFIX_EVEX_0F3A0B, PREFIX_EVEX_0F3A14, PREFIX_EVEX_0F3A15,
351 PREFIX_EVEX_0F3A16, PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18,
352 PREFIX_EVEX_0F3A19, PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B,
353 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A20,
354 PREFIX_EVEX_0F3A21, PREFIX_EVEX_0F3A22, PREFIX_EVEX_0F3A23,
355 PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26, PREFIX_EVEX_0F3A27,
356 PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39, PREFIX_EVEX_0F3A3A,
357 PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E, PREFIX_EVEX_0F3A3F,
358 PREFIX_EVEX_0F3A42, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A50,
359 PREFIX_EVEX_0F3A51, PREFIX_EVEX_0F3A54, PREFIX_EVEX_0F3A55,
360 PREFIX_EVEX_0F3A56, PREFIX_EVEX_0F3A57, PREFIX_EVEX_0F3A66,
361 PREFIX_EVEX_0F3A67, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
362 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73): Delete.
363 (MOD_0F382A_PREFIX_2, MOD_0F38F5_PREFIX_2,
364 MOD_VEX_0FD7_PREFIX_2, MOD_VEX_0FE7_PREFIX_2,
365 MOD_VEX_0F381A_PREFIX_2, MOD_VEX_0F382A_PREFIX_2,
366 MOD_VEX_0F382C_PREFIX_2, MOD_VEX_0F382D_PREFIX_2,
367 MOD_VEX_0F382E_PREFIX_2, MOD_VEX_0F382F_PREFIX_2,
368 MOD_VEX_0F385A_PREFIX_2, MOD_VEX_0F388C_PREFIX_2,
369 MOD_VEX_0F388E_PREFIX_2, MOD_VEX_W_0_0F3A30_P_2_LEN_0,
370 MOD_VEX_W_1_0F3A30_P_2_LEN_0, MOD_VEX_W_0_0F3A31_P_2_LEN_0,
371 MOD_VEX_W_1_0F3A31_P_2_LEN_0, MOD_VEX_W_0_0F3A32_P_2_LEN_0,
372 MOD_VEX_W_1_0F3A32_P_2_LEN_0, MOD_VEX_W_0_0F3A33_P_2_LEN_0,
373 MOD_VEX_W_1_0F3A33_P_2_LEN_0, MOD_EVEX_0F381A_P_2_W_0,
374 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
375 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
376 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0,
377 MOD_EVEX_0F385B_P_2_W_1, VEX_LEN_0F6E_P_2,
378 VEX_LEN_0FC4_P_2, VEX_LEN_0FC5_P_2, VEX_LEN_0FD6_P_2,
379 VEX_LEN_0FF7_P_2, VEX_LEN_0F3816_P_2, VEX_LEN_0F3819_P_2,
380 VEX_LEN_0F381A_P_2_M_0, VEX_LEN_0F3836_P_2,
381 VEX_LEN_0F3841_P_2, VEX_LEN_0F385A_P_2_M_0,
382 VEX_LEN_0F38DB_P_2, VEX_LEN_0F3A00_P_2, VEX_LEN_0F3A01_P_2,
383 VEX_LEN_0F3A06_P_2, VEX_LEN_0F3A14_P_2, VEX_LEN_0F3A15_P_2,
384 VEX_LEN_0F3A16_P_2, VEX_LEN_0F3A17_P_2, VEX_LEN_0F3A18_P_2,
385 VEX_LEN_0F3A19_P_2, VEX_LEN_0F3A20_P_2, VEX_LEN_0F3A21_P_2,
386 VEX_LEN_0F3A22_P_2, VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A31_P_2,
387 VEX_LEN_0F3A32_P_2, VEX_LEN_0F3A33_P_2, VEX_LEN_0F3A38_P_2,
388 VEX_LEN_0F3A39_P_2, VEX_LEN_0F3A41_P_2, VEX_LEN_0F3A46_P_2,
389 VEX_LEN_0F3A60_P_2, VEX_LEN_0F3A61_P_2, VEX_LEN_0F3A62_P_2,
390 VEX_LEN_0F3A63_P_2, VEX_LEN_0F3ADF_P_2, EVEX_LEN_0F6E_P_2,
391 EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2, EVEX_LEN_0FD6_P_2,
392 EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3819_P_2_W_0,
393 EVEX_LEN_0F3819_P_2_W_1, EVEX_LEN_0F381A_P_2_W_0_M_0,
394 EVEX_LEN_0F381A_P_2_W_1_M_0, EVEX_LEN_0F381B_P_2_W_0_M_0,
395 EVEX_LEN_0F381B_P_2_W_1_M_0, EVEX_LEN_0F3836_P_2,
396 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
397 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0,
398 EVEX_LEN_0F38C6_REG_1_PREFIX_2, EVEX_LEN_0F38C6_REG_2_PREFIX_2,
399 EVEX_LEN_0F38C6_REG_5_PREFIX_2, EVEX_LEN_0F38C6_REG_6_PREFIX_2,
400 EVEX_LEN_0F38C7_R_1_P_2_W_0, EVEX_LEN_0F38C7_R_1_P_2_W_1,
401 EVEX_LEN_0F38C7_R_2_P_2_W_0, EVEX_LEN_0F38C7_R_2_P_2_W_1,
402 EVEX_LEN_0F38C7_R_5_P_2_W_0, EVEX_LEN_0F38C7_R_5_P_2_W_1,
403 EVEX_LEN_0F38C7_R_6_P_2_W_0, EVEX_LEN_0F38C7_R_6_P_2_W_1,
404 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1,
405 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
406 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A18_P_2_W_0,
407 EVEX_LEN_0F3A18_P_2_W_1, EVEX_LEN_0F3A19_P_2_W_0,
408 EVEX_LEN_0F3A19_P_2_W_1, EVEX_LEN_0F3A1A_P_2_W_0,
409 EVEX_LEN_0F3A1A_P_2_W_1, EVEX_LEN_0F3A1B_P_2_W_0,
410 EVEX_LEN_0F3A1B_P_2_W_1, EVEX_LEN_0F3A20_P_2,
411 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2,
412 EVEX_LEN_0F3A23_P_2_W_0, EVEX_LEN_0F3A23_P_2_W_1,
413 EVEX_LEN_0F3A38_P_2_W_0, EVEX_LEN_0F3A38_P_2_W_1,
414 EVEX_LEN_0F3A39_P_2_W_0, EVEX_LEN_0F3A39_P_2_W_1,
415 EVEX_LEN_0F3A3A_P_2_W_0, EVEX_LEN_0F3A3A_P_2_W_1,
416 EVEX_LEN_0F3A3B_P_2_W_0, EVEX_LEN_0F3A3B_P_2_W_1,
417 EVEX_LEN_0F3A43_P_2_W_0, EVEX_LEN_0F3A43_P_2_W_1
418 VEX_W_0F380C_P_2, VEX_W_0F380D_P_2, VEX_W_0F380E_P_2,
419 VEX_W_0F380F_P_2, VEX_W_0F3813_P_2, VEX_W_0F3816_P_2,
420 VEX_W_0F3818_P_2, VEX_W_0F3819_P_2,
421 VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F382C_P_2_M_0,
422 VEX_W_0F382D_P_2_M_0, VEX_W_0F382E_P_2_M_0,
423 VEX_W_0F382F_P_2_M_0, VEX_W_0F3836_P_2,
424 VEX_W_0F3846_P_2, VEX_W_0F3858_P_2, VEX_W_0F3859_P_2,
425 VEX_W_0F385A_P_2_M_0_L_0, VEX_W_0F3878_P_2,
426 VEX_W_0F3879_P_2, VEX_W_0F38CF_P_2, VEX_W_0F3A00_P_2,
427 VEX_W_0F3A01_P_2, VEX_W_0F3A02_P_2, VEX_W_0F3A04_P_2,
428 VEX_W_0F3A05_P_2, VEX_W_0F3A06_P_2_L_0,
429 VEX_W_0F3A18_P_2_L_0, VEX_W_0F3A19_P_2_L_0,
430 VEX_W_0F3A1D_P_2, VEX_W_0F3A30_P_2_LEN_0,
431 VEX_W_0F3A31_P_2_LEN_0, VEX_W_0F3A32_P_2_LEN_0,
432 VEX_W_0F3A33_P_2_LEN_0, VEX_W_0F3A38_P_2_L_0,
433 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0,
434 VEX_W_0F3A4A_P_2, VEX_W_0F3A4B_P_2, VEX_W_0F3A4C_P_2,
435 VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2, EVEX_W_0F66_P_2,
436 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2,
437 EVEX_W_0F73_R_2_P_2, EVEX_W_0F73_R_6_P_2,
438 EVEX_W_0F76_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE7_P_2,
439 EVEX_W_0F380D_P_2, EVEX_W_0F3819_P_2,
440 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2,
441 EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
442 EVEX_W_0F3837_P_2, EVEX_W_0F3859_P_2,
443 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2,
444 EVEX_W_0F3870_P_2, EVEX_W_0F387A_P_2,
445 EVEX_W_0F387B_P_2, EVEX_W_0F3883_P_2,
446 EVEX_W_0F3891_P_2, EVEX_W_0F3893_P_2,
447 EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
448 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2,
449 EVEX_W_0F38C7_R_5_P_2, EVEX_W_0F38C7_R_6_P_2,
450 EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
451 EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
452 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2,
453 EVEX_W_0F3A0B_P_2, EVEX_W_0F3A18_P_2,
454 EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
455 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A21_P_2,
456 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2,
457 EVEX_W_0F3A39_P_2, EVEX_W_0F3A3A_P_2,
458 EVEX_W_0F3A3B_P_2, EVEX_W_0F3A42_P_2,
459 EVEX_W_0F3A43_P_2, EVEX_W_0F3A70_P_2,
460 EVEX_W_0F3A72_P_2): Rename to ...
461 (MOD_0F382A, MOD_0F38F5, MOD_VEX_0FD7, MOD_VEX_0FE7,
462 MOD_VEX_0F381A, MOD_VEX_0F382A, MOD_VEX_0F382C, MOD_VEX_0F382D,
463 MOD_VEX_0F382E, MOD_VEX_0F382F, MOD_VEX_0F385A, MOD_VEX_0F388C,
464 MOD_VEX_0F388E, MOD_VEX_0F3A30_L_0_W_0,
465 MOD_VEX_0F3A30_L_0_W_1, MOD_VEX_0F3A31_L_0_W_0,
466 MOD_VEX_0F3A31_L_0_W_1, MOD_VEX_0F3A32_L_0_W_0,
467 MOD_VEX_0F3A32_L_0_W_1, MOD_VEX_0F3A33_L_0_W_0,
468 MOD_VEX_0F3A33_L_0_W_1, MOD_EVEX_0F381A_W_0,
469 MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0, MOD_EVEX_0F381B_W_1,
470 MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1, MOD_EVEX_0F385B_W_0,
471 MOD_EVEX_0F385B_W_1, VEX_LEN_0F6E, VEX_LEN_0FC4, VEX_LEN_0FC5,
472 VEX_LEN_0FD6, VEX_LEN_0FF7, VEX_LEN_0F3816, VEX_LEN_0F3819,
473 VEX_LEN_0F381A_M_0, VEX_LEN_0F3836, VEX_LEN_0F3841,
474 VEX_LEN_0F385A_M_0, VEX_LEN_0F38DB, VEX_LEN_0F3A00,
475 VEX_LEN_0F3A01, VEX_LEN_0F3A06, VEX_LEN_0F3A14, VEX_LEN_0F3A15,
476 VEX_LEN_0F3A16, VEX_LEN_0F3A17, VEX_LEN_0F3A18, VEX_LEN_0F3A19,
477 VEX_LEN_0F3A20, VEX_LEN_0F3A21, VEX_LEN_0F3A22, VEX_LEN_0F3A30,
478 VEX_LEN_0F3A31, VEX_LEN_0F3A32, VEX_LEN_0F3A33, VEX_LEN_0F3A38,
479 VEX_LEN_0F3A39, VEX_LEN_0F3A41, VEX_LEN_0F3A46, VEX_LEN_0F3A60,
480 VEX_LEN_0F3A61, VEX_LEN_0F3A62, VEX_LEN_0F3A63, VEX_LEN_0F3ADF,
481 EVEX_LEN_0F6E, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
482 EVEX_LEN_0F3816, EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
483 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
484 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
485 EVEX_LEN_0F3836, EVEX_LEN_0F385A_W_0_M_0,
486 EVEX_LEN_0F385A_W_1_M_0, EVEX_LEN_0F385B_W_0_M_0,
487 EVEX_LEN_0F385B_W_1_M_0, EVEX_LEN_0F38C6_R_1_M_0,
488 EVEX_LEN_0F38C6_R_2_M_0, EVEX_LEN_0F38C6_R_5_M_0,
489 EVEX_LEN_0F38C6_R_6_M_0, EVEX_LEN_0F38C7_R_1_M_0_W_0,
490 EVEX_LEN_0F38C7_R_1_M_0_W_1, EVEX_LEN_0F38C7_R_2_M_0_W_0,
491 EVEX_LEN_0F38C7_R_2_M_0_W_1, EVEX_LEN_0F38C7_R_5_M_0_W_0,
492 EVEX_LEN_0F38C7_R_5_M_0_W_1, EVEX_LEN_0F38C7_R_6_M_0_W_0,
493 EVEX_LEN_0F38C7_R_6_M_0_W_1, EVEX_LEN_0F3A00_W_1,
494 EVEX_LEN_0F3A01_W_1, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
495 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A18_W_0,
496 EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
497 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0,
498 EVEX_LEN_0F3A1A_W_1, EVEX_LEN_0F3A1B_W_0,
499 EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A20, EVEX_LEN_0F3A21_W_0,
500 EVEX_LEN_0F3A22, EVEX_LEN_0F3A23_W_0, EVEX_LEN_0F3A23_W_1,
501 EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
502 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1,
503 EVEX_LEN_0F3A3A_W_0, EVEX_LEN_0F3A3A_W_1,
504 EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
505 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1
506 VEX_W_0F380C, VEX_W_0F380D, VEX_W_0F380E, VEX_W_0F380F,
507 VEX_W_0F3813, VEX_W_0F3816_L_1, VEX_W_0F3818,
508 VEX_W_0F3819_L_1, VEX_W_0F381A_M_0_L_1, VEX_W_0F382C_M_0,
509 VEX_W_0F382D_M_0, VEX_W_0F382E_M_0, VEX_W_0F382F_M_0,
510 VEX_W_0F3836, VEX_W_0F3846, VEX_W_0F3858, VEX_W_0F3859,
511 VEX_W_0F385A_M_0_L_0, VEX_W_0F3878, VEX_W_0F3879,
512 VEX_W_0F38CF, VEX_W_0F3A00_L_1, VEX_W_0F3A01_L_1,
513 VEX_W_0F3A02, VEX_W_0F3A04, VEX_W_0F3A05, VEX_W_0F3A06_L_1,
514 VEX_W_0F3A18_L_1, VEX_W_0F3A19_L_1, VEX_W_0F3A1D,
515 VEX_W_0F3A30_L_0, VEX_W_0F3A31_L_0, VEX_W_0F3A32_L_0,
516 VEX_W_0F3A33_L_0, VEX_W_0F3A38_L_1, VEX_W_0F3A39_L_1,
517 VEX_W_0F3A46_L_1, VEX_W_0F3A4A, VEX_W_0F3A4B, VEX_W_0F3A4C,
518 VEX_W_0F3ACE, VEX_W_0F3ACF, EVEX_W_0F66, EVEX_W_0F72_R_2,
519 EVEX_W_0F72_R_6, EVEX_W_0F73_R_2, EVEX_W_0F73_R_6,
520 EVEX_W_0F76, EVEX_W_0FD6_L_0, EVEX_W_0FE7, EVEX_W_0F380D,
521 EVEX_W_0F3819, EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F381E,
522 EVEX_W_0F381F, EVEX_W_0F3837, EVEX_W_0F3859, EVEX_W_0F385A,
523 EVEX_W_0F385B, EVEX_W_0F3870, EVEX_W_0F387A, EVEX_W_0F387B,
524 EVEX_W_0F3883, EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1,
525 EVEX_W_0F38A3, EVEX_W_0F38C7_R_1_M_0,
526 EVEX_W_0F38C7_R_2_M_0, EVEX_W_0F38C7_R_5_M_0,
527 EVEX_W_0F38C7_R_6_M_0, EVEX_W_0F3A00, EVEX_W_0F3A01,
528 EVEX_W_0F3A05, EVEX_W_0F3A08, EVEX_W_0F3A09, EVEX_W_0F3A0A,
529 EVEX_W_0F3A0B, EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A,
530 EVEX_W_0F3A1B, EVEX_W_0F3A21, EVEX_W_0F3A23, EVEX_W_0F3A38,
531 EVEX_W_0F3A39, EVEX_W_0F3A3A, EVEX_W_0F3A3B, EVEX_W_0F3A42,
532 EVEX_W_0F3A43, EVEX_W_0F3A70, EVEX_W_0F3A72): ... these
533 respectively.
534 (dis386_twobyte, three_byte_table, vex_table, vex_len_table,
535 vex_w_table, mod_table): Replace / remove respective entries.
536 (print_insn): Move up dp->prefix_requirement handling. Handle
537 PREFIX_DATA.
538 * i386-dis-evex.h, i386-dis-evex-len.h, i386-dis-evex-mod.h,
539 i386-dis-evex-prefix.h, i386-dis-evex-reg.h, i386-dis-evex-w.h:
540 Replace / remove respective entries.
541
17d3c7ec
JB		 5422020-07-14 Jan Beulich <jbeulich@suse.com>
543
544 * i386-dis.c (PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
545 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F): Delete.
546 (prefix_table): Add EXxEVexS operand to vcvttss2si, vcvttsd2si,
547 vcvtss2si, vcvtsd2si, vucomiss, and vucomisd table entries.
548 Retain X macro and PREFIX_OPCODE use from tjhe EVEX table for
549 the latter two.
550 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
551 0F2C, 0F2D, 0F2E, and 0F2F.
552 * i386-dis-evex-prefix.h: Delete opcode 0F2C, 0F2D, 0F2E, and
553 0F2F table entries.
554
41f5efc6
JB		 5552020-07-14 Jan Beulich <jbeulich@suse.com>
556
557 * i386-dis.c (OP_VexR, VexScalarR): New.
558 (OP_EX_Vex, OP_XMM_Vex, EXdVexScalarS, EXqVexScalarS,
559 XMVexScalar, d_scalar_swap_mode, q_scalar_swap_mode,
560 need_vex_reg): Delete.
561 (prefix_table): Replace VexScalar by VexScalarR and
562 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
563 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
564 (vex_len_table): Replace EXqVexScalarS by EXqS.
565 (get_valid_dis386): Don't set need_vex_reg.
566 (print_insn): Don't initialize need_vex_reg.
567 (intel_operand_size, OP_E_memory): Drop d_scalar_swap_mode and
568 q_scalar_swap_mode cases.
569 (OP_EX): Don't check for d_scalar_swap_mode and
570 q_scalar_swap_mode.
571 (OP_VEX): Done check need_vex_reg.
572 * i386-dis-evex-w.h: Replace VexScalar by VexScalarR and
573 XMVexScalar by XMScalar for vmovss and vmovsd. Replace
574 EXdVexScalarS by EXdS and EXqVexScalarS by EXqS.
575
89e65d17
JB		 5762020-07-14 Jan Beulich <jbeulich@suse.com>
577
578 * i386-dis.c (Vex128, Vex256, vex128_mode, vex256_mode): Delete.
579 (VEX_W_0F381A_P_2_M_0, VEX_W_0F385A_P_2_M_0, VEX_W_0F3A06_P_2,
580 VEX_W_0F3A18_P_2, VEX_W_0F3A19_P_2, VEX_W_0F3A38_P_2,
581 VEX_W_0F3A39_P_2, VEX_W_0F3A46_P_2): Rename to ...
582 (VEX_W_0F381A_P_2_M_0_L_0, VEX_W_0F385A_P_2_M_0_L_0,
583 VEX_W_0F3A06_P_2_L_0, VEX_W_0F3A18_P_2_L_0,
584 VEX_W_0F3A19_P_2_L_0, VEX_W_0F3A38_P_2_L_0,
585 VEX_W_0F3A39_P_2_L_0, VEX_W_0F3A46_P_2_L_0): ... respectively.
586 (vex_table): Replace Vex128 by Vex.
587 (vex_len_table): Likewise. Adjust referenced enum names.
588 (vex_w_table): Replace Vex128 and Vex256 by Vex. Adjust
589 referenced enum names.
590 (OP_VEX): Drop vex128_mode and vex256_mode cases.
591 * i386-dis-evex-len.h (evex_len_table): Replace Vex128 by Vex.
592
492a76aa
JB		 5932020-07-14 Jan Beulich <jbeulich@suse.com>
594
595 * i386-dis.c (dis386): "LW" description now applies to "DQ".
596 (putop): Handle "DQ". Don't handle "LW" anymore.
597 (prefix_table, mod_table): Replace %LW by %DQ.
598 * i386-dis-evex-len.h, i386-dis-evex-prefix.h: Likewise.
599
059edf8b
JB		 6002020-07-14 Jan Beulich <jbeulich@suse.com>
601
602 * i386-dis.c (OP_E_memory): Move xmm_mw_mode, xmm_mb_mode,
603 dqd_mode, xmm_md_mode, d_mode, d_swap_mode, and
604 d_scalar_swap_mode case handling. Move shift adjsutment into
605 the case its applicable to.
606
4726e9a4
JB		 6072020-07-14 Jan Beulich <jbeulich@suse.com>
608
609 * i386-dis.c (EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2): Delete.
610 (EXbScalar, EXwScalar): Fold to ...
611 (EXbwUnit): ... this.
612 (b_scalar_mode, w_scalar_mode): Fold to ...
613 (bw_unit_mode): ... this.
614 (intel_operand_size, OP_E_memory): Replace b_scalar_mode /
615 w_scalar_mode handling by bw_unit_mode one.
616 * i386-dis-evex-w.h: Move entries for opcodes 0F3862 and 0F3863
617 ...
618 * i386-dis-evex-prefix.h: ... here.
619
b24d668c
JB		 6202020-07-14 Jan Beulich <jbeulich@suse.com>
621
622 * i386-dis.c (PCMPESTR_Fixup): Delete.
623 (dis386): Adjust "LQ" description.
624 (prefix_table): Make %LQ apply to AT&T case only for cvtsi2ss,
625 cvtsi2sd, ptwrite, vcvtsi2ss, and vcvtsi2sd. Replace use of
626 PCMPESTR_Fixup by !%LQ and EXx for pcmpestrm, pcmpestri,
627 vpcmpestrm, and vpcmpestri.
628 (putop): Honor "cond" when handling LQ.
629 * i386-dis-evex-prefix.h: Make %LQ apply to AT&T case only for
630 vcvtsi2ss and vcvtusi2ss.
631 * i386-dis-evex-w.h: Make %LQ apply to AT&T case only for
632 vcvtsi2sd and vcvtusi2sd.
633
c4de7606
JB		 6342020-07-14 Jan Beulich <jbeulich@suse.com>
635
636 * i386-dis.c (VCMP_Fixup, VCMP): Delete.
637 (simd_cmp_op): Add const.
638 (vex_cmp_op): Move up and drop initial 8 entries. Add const.
639 (CMP_Fixup): Handle VEX case.
640 (prefix_table): Replace VCMP by CMP.
641 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Likewise.
642
9ab00b61
JB		 6432020-07-14 Jan Beulich <jbeulich@suse.com>
644
645 * i386-dis.c (MOVBE_Fixup): Delete.
646 (Mv): Define.
647 (prefix_table): Use Mv for movbe entries.
648
2875b28a
JB		 6492020-07-14 Jan Beulich <jbeulich@suse.com>
650
651 * i386-dis.c (CRC32_Fixup): Delete.
652 (prefix_table): Use Eb/Ev for crc32 entries.
653
e184e611
JB		 6542020-07-14 Jan Beulich <jbeulich@suse.com>
655
656 * i386-dis.c (OP_E_register, OP_G, OP_REG, CRC32_Fixup):
657 Conditionalize invocations of "USED_REX (0)".
658
e8b5d5f9
JB		 6592020-07-14 Jan Beulich <jbeulich@suse.com>
660
661 * i386-dis.c (eBX, eCX, eDX, eSP, eBP, eSI, eDI, DL, BL, AH,
662 CH, DH, BH, AX, DX): Delete.
663 (OP_IMREG): Drop handling of eBX_reg, eCX_reg, eDX_reg, eSP_reg,
664 eBP_reg, eSI_reg, eDI_reg, dl_reg, bl_reg, ah_reg, ch_reg,
665 dh_reg, bh_reg, ax_reg, and dx_reg. Simplify what's left.
666
260cd341
LC		 6672020-07-10 Lili Cui <lili.cui@intel.com>
668
669 * i386-dis.c (TMM): New.
670 (EXtmm): Likewise.
671 (VexTmm): Likewise.
672 (MVexSIBMEM): Likewise.
673 (tmm_mode): Likewise.
674 (vex_sibmem_mode): Likewise.
675 (REG_VEX_0F3849_X86_64_P_0_W_0_M_1): Likewise.
676 (MOD_VEX_0F3849_X86_64_P_0_W_0): Likewise.
677 (MOD_VEX_0F3849_X86_64_P_2_W_0): Likewise.
678 (MOD_VEX_0F3849_X86_64_P_3_W_0): Likewise.
679 (MOD_VEX_0F384B_X86_64_P_1_W_0): Likewise.
680 (MOD_VEX_0F384B_X86_64_P_2_W_0): Likewise.
681 (MOD_VEX_0F384B_X86_64_P_3_W_0): Likewise.
682 (MOD_VEX_0F385C_X86_64_P_1_W_0): Likewise.
683 (MOD_VEX_0F385E_X86_64_P_0_W_0): Likewise.
684 (MOD_VEX_0F385E_X86_64_P_1_W_0): Likewise.
685 (MOD_VEX_0F385E_X86_64_P_2_W_0): Likewise.
686 (MOD_VEX_0F385E_X86_64_P_3_W_0): Likewise.
687 (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0): Likewise.
688 (PREFIX_VEX_0F3849_X86_64): Likewise.
689 (PREFIX_VEX_0F384B_X86_64): Likewise.
690 (PREFIX_VEX_0F385C_X86_64): Likewise.
691 (PREFIX_VEX_0F385E_X86_64): Likewise.
692 (X86_64_VEX_0F3849): Likewise.
693 (X86_64_VEX_0F384B): Likewise.
694 (X86_64_VEX_0F385C): Likewise.
695 (X86_64_VEX_0F385E): Likewise.
696 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0): Likewise.
697 (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0): Likewise.
698 (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0): Likewise.
699 (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0): Likewise.
700 (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0): Likewise.
701 (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0): Likewise.
702 (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0): Likewise.
703 (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0): Likewise.
704 (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0): Likewise.
705 (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0): Likewise.
706 (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0): Likewise.
707 (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0): Likewise.
708 (VEX_W_0F3849_X86_64_P_0): Likewise.
709 (VEX_W_0F3849_X86_64_P_2): Likewise.
710 (VEX_W_0F3849_X86_64_P_3): Likewise.
711 (VEX_W_0F384B_X86_64_P_1): Likewise.
712 (VEX_W_0F384B_X86_64_P_2): Likewise.
713 (VEX_W_0F384B_X86_64_P_3): Likewise.
714 (VEX_W_0F385C_X86_64_P_1): Likewise.
715 (VEX_W_0F385E_X86_64_P_0): Likewise.
716 (VEX_W_0F385E_X86_64_P_1): Likewise.
717 (VEX_W_0F385E_X86_64_P_2): Likewise.
718 (VEX_W_0F385E_X86_64_P_3): Likewise.
719 (names_tmm): Likewise.
720 (att_names_tmm): Likewise.
721 (intel_operand_size): Handle void_mode.
722 (OP_XMM): Handle tmm_mode.
723 (OP_EX): Likewise.
724 (OP_VEX): Likewise.
725 * i386-gen.c (cpu_flag_init): Add entries for CpuAMX_INT8,
726 CpuAMX_BF16 and CpuAMX_TILE.
727 (operand_type_shorthands): Add RegTMM.
728 (operand_type_init): Likewise.
729 (operand_types): Add Tmmword.
730 (cpu_flag_init): Add CPU_AMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
731 (cpu_flags): Add CpuAMX_INT8, CpuAMX_BF16 and CpuAMX_TILE.
732 * i386-opc.h (CpuAMX_INT8): New.
733 (CpuAMX_BF16): Likewise.
734 (CpuAMX_TILE): Likewise.
735 (SIBMEM): Likewise.
736 (Tmmword): Likewise.
737 (i386_cpu_flags): Add cpuamx_int8, cpuamx_bf16 and cpuamx_tile.
738 (i386_opcode_modifier): Extend width of fields vexvvvv and sib.
739 (i386_operand_type): Add tmmword.
740 * i386-opc.tbl: Add AMX instructions.
741 * i386-reg.tbl: Add AMX registers.
742 * i386-init.h: Regenerated.
743 * i386-tbl.h: Likewise.
744
467bbef0
JB		 7452020-07-08 Jan Beulich <jbeulich@suse.com>
746
747 * i386-dis.c (OP_LWPCB_E, OP_LWP_E): Delete.
748 (REG_XOP_LWPCB, REG_XOP_LWP, REG_XOP_TBM_01, REG_XOP_TBM_02):
749 Rename to ...
750 (REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
751 REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0): ... these
752 respectively.
753 (MOD_VEX_0FXOP_09_12, VEX_LEN_0FXOP_08_85, VEX_LEN_0FXOP_08_86,
754 VEX_LEN_0FXOP_08_87, VEX_LEN_0FXOP_08_8E, VEX_LEN_0FXOP_08_8F,
755 VEX_LEN_0FXOP_08_95, VEX_LEN_0FXOP_08_96, VEX_LEN_0FXOP_08_97,
756 VEX_LEN_0FXOP_08_9E, VEX_LEN_0FXOP_08_9F, VEX_LEN_0FXOP_08_A3,
757 VEX_LEN_0FXOP_08_A6, VEX_LEN_0FXOP_08_B6, VEX_LEN_0FXOP_08_C0,
758 VEX_LEN_0FXOP_08_C1, VEX_LEN_0FXOP_08_C2, VEX_LEN_0FXOP_08_C3,
759 VEX_LEN_0FXOP_09_01, VEX_LEN_0FXOP_09_02, VEX_LEN_0FXOP_09_12_M_1,
760 VEX_LEN_0FXOP_09_90, VEX_LEN_0FXOP_09_91, VEX_LEN_0FXOP_09_92,
761 VEX_LEN_0FXOP_09_93, VEX_LEN_0FXOP_09_94, VEX_LEN_0FXOP_09_95,
762 VEX_LEN_0FXOP_09_96, VEX_LEN_0FXOP_09_97, VEX_LEN_0FXOP_09_98,
763 VEX_LEN_0FXOP_09_99, VEX_LEN_0FXOP_09_9A, VEX_LEN_0FXOP_09_9B,
764 VEX_LEN_0FXOP_09_C1, VEX_LEN_0FXOP_09_C2, VEX_LEN_0FXOP_09_C3,
765 VEX_LEN_0FXOP_09_C6, VEX_LEN_0FXOP_09_C7, VEX_LEN_0FXOP_09_CB,
766 VEX_LEN_0FXOP_09_D1, VEX_LEN_0FXOP_09_D2, VEX_LEN_0FXOP_09_D3,
767 VEX_LEN_0FXOP_09_D6, VEX_LEN_0FXOP_09_D7, VEX_LEN_0FXOP_09_DB,
768 VEX_LEN_0FXOP_09_E1, VEX_LEN_0FXOP_09_E2, VEX_LEN_0FXOP_09_E3,
769 VEX_LEN_0FXOP_0A_12, VEX_W_0FXOP_08_85_L_0,
770 VEX_W_0FXOP_08_86_L_0, VEX_W_0FXOP_08_87_L_0,
771 VEX_W_0FXOP_08_8E_L_0, VEX_W_0FXOP_08_8F_L_0,
772 VEX_W_0FXOP_08_95_L_0, VEX_W_0FXOP_08_96_L_0,
773 VEX_W_0FXOP_08_97_L_0, VEX_W_0FXOP_08_9E_L_0,
774 VEX_W_0FXOP_08_9F_L_0, VEX_W_0FXOP_08_A6_L_0,
775 VEX_W_0FXOP_08_B6_L_0, VEX_W_0FXOP_08_C0_L_0,
776 VEX_W_0FXOP_08_C1_L_0, VEX_W_0FXOP_08_C2_L_0,
777 VEX_W_0FXOP_08_C3_L_0, VEX_W_0FXOP_08_CC_L_0,
778 VEX_W_0FXOP_08_CD_L_0, VEX_W_0FXOP_08_CE_L_0,
779 VEX_W_0FXOP_08_CF_L_0, VEX_W_0FXOP_08_EC_L_0,
780 VEX_W_0FXOP_08_ED_L_0, VEX_W_0FXOP_08_EE_L_0,
781 VEX_W_0FXOP_08_EF_L_0, VEX_W_0FXOP_09_C1_L_0,
782 VEX_W_0FXOP_09_C2_L_0, VEX_W_0FXOP_09_C3_L_0,
783 VEX_W_0FXOP_09_C6_L_0, VEX_W_0FXOP_09_C7_L_0,
784 VEX_W_0FXOP_09_CB_L_0, VEX_W_0FXOP_09_D1_L_0,
785 VEX_W_0FXOP_09_D2_L_0, VEX_W_0FXOP_09_D3_L_0,
786 VEX_W_0FXOP_09_D6_L_0, VEX_W_0FXOP_09_D7_L_0,
787 VEX_W_0FXOP_09_DB_L_0, VEX_W_0FXOP_09_E1_L_0,
788 VEX_W_0FXOP_09_E2_L_0, VEX_W_0FXOP_09_E3_L_0): New enumerators.
789 (reg_table): Re-order XOP entries. Adjust their operands.
790 (xop_table): Replace 08_85, 08_86, 08_87, 08_8E, 08_8F, 08_95,
791 08_96, 08_97, 08_9E, 08_9F, 08_A3, 08_A6, 08_B6, 08_C0, 08_C1,
792 08_C2, 08_C3, 09_01, 09_02, 09_12, 09_90, 09_91, 09_92, 09_93,
793 09_94, 09_95, 09_96, 09_97, 09_98, 09_99, 09_9A, 09_9B, 09_C1,
794 09_C2, 09_C3, 09_C6, 09_C7, 09_CB, 09_D1, 09_D2, 09_D3, 09_D6,
795 09_D7, 09_DB, 09_E1, 09_E2, 09_E3, and VEX_LEN_0FXOP_0A_12
796 entries by references ...
797 (vex_len_table): ... to resepctive new entries here. For several
798 new and existing entries reference ...
799 (vex_w_table): ... new entries here.
800 (mod_table): New MOD_VEX_0FXOP_09_12 entry.
801
6384fd9e
JB		 8022020-07-08 Jan Beulich <jbeulich@suse.com>
803
804 * i386-dis.c (XMVexScalarI4): Define.
805 (VEX_LEN_0F3A6A_P_2, VEX_LEN_0F3A6B_P_2, VEX_LEN_0F3A6E_P_2,
806 VEX_LEN_0F3A6F_P_2, VEX_LEN_0F3A7A_P_2, VEX_LEN_0F3A7B_P_2,
807 VEX_LEN_0F3A7E_P_2, VEX_LEN_0F3A7F_P_2): Delete.
808 (vex_len_table): Move scalar FMA4 entries ...
809 (prefix_table): ... here.
810 (OP_REG_VexI4): Handle scalar_mode.
811 * i386-opc.tbl: Use VexLIG for scalar FMA4 insns.
812 * i386-tbl.h: Re-generate.
813
e6123d0c
JB		 8142020-07-08 Jan Beulich <jbeulich@suse.com>
815
816 * i386-dis.c (OP_Vex_2src_1, OP_Vex_2src_2, Vex_2src_1,
817 Vex_2src_2): Delete.
818 (OP_VexW, VexW): New.
819 (xop_table): Use EXx for rotates by immediate. Use EXx and VexW
820 for shifts and rotates by register.
821
93abb146
JB		 8222020-07-08 Jan Beulich <jbeulich@suse.com>
823
824 * i386-dis.c (OP_EX_VexImmW, OP_XMM_VexW, EXVexImmW, XMVexW,
825 VEX_W_0F3A48_P_2, VEX_W_0F3A49_P_2, vex_w_done, get_vex_imm8,
826 OP_EX_VexReg): Delete.
827 (OP_VexI4, VexI4): New.
828 (vex_w_table): Move vpermil2ps and vpermil2pd entries ...
829 (prefix_table): ... here.
830 (print_insn): Drop setting of vex_w_done.
831
b13b1bc0
JB		 8322020-07-08 Jan Beulich <jbeulich@suse.com>
833
834 * i386-dis.c (OP_EX_VexW, EXVexW, EXdVexW, EXqVexW): Delete.
835 (prefix_table, vex_len_table): Replace operands for FMA4 insns.
836 (xop_table): Replace operands of 4-operand insns.
837 (OP_REG_VexI4): Move VEX.W based operand swaping here.
838
f337259f
CZ		 8392020-07-07 Claudiu Zissulescu <claziss@synopsys.com>
840
841 * arc-opc.c (insert_rbd): New function.
842 (RBD): Define.
843 (RBDdup): Likewise.
844 * arc-tbl.h (vadd2, vadd4h, vmac2h, vmpy2h, vsub4h): Update
845 instructions.
846
931452b6
JB		 8472020-07-07 Jan Beulich <jbeulich@suse.com>
848
849 * i386-dis.c (EVEX_W_0F3826_P_1, EVEX_W_0F3826_P_2,
850 EVEX_W_0F3828_P_1, EVEX_W_0F3829_P_1, EVEX_W_0F3854_P_2,
851 EVEX_W_0F3866_P_2, EVEX_W_0F3875_P_2, EVEX_W_0F387D_P_2,
852 EVEX_W_0F388D_P_2, EVEX_W_0F3A3E_P_2, EVEX_W_0F3A3F_P_2):
853 Delete.
854 (putop): Handle "BW".
855 * i386-dis-evex-w.h: Move entries for opcodes 0F3826, 0F3826,
856 0F3828, 0F3829, 0F3854, 0F3866, 0F3875, 0F387D, 0F388D, 0F3A3E,
857 and 0F3A3F ...
858 * i386-dis-evex-prefix.h: ... here.
859
b5b098c2
JB		 8602020-07-06 Jan Beulich <jbeulich@suse.com>
861
862 * i386-dis.c (VEX_LEN_0FXOP_09_80, VEX_LEN_0FXOP_09_81): Delete.
863 (VEX_LEN_0FXOP_09_82_W_0, VEX_LEN_0FXOP_09_83_W_0,
864 VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81, VEX_W_0FXOP_09_82,
865 VEX_W_0FXOP_09_83): New enumerators.
866 (xop_table): Reference the above.
867 (vex_len_table): Replace vfrczp* entries by vfrczs* ones.
868 (vex_w_table): New VEX_W_0FXOP_09_80, VEX_W_0FXOP_09_81,
869 VEX_W_0FXOP_09_82, and VEX_W_0FXOP_09_83 entries.
870 (get_valid_dis386): Return bad_opcode for XOP.PP != 0.
871
21a3faeb
JB		 8722020-07-06 Jan Beulich <jbeulich@suse.com>
873
874 * i386-dis.c (EVEX_W_0F3838_P_1,
875 EVEX_W_0F3839_P_1, EVEX_W_0F3840_P_2, EVEX_W_0F3855_P_2,
876 EVEX_W_0F3868_P_3, EVEX_W_0F3871_P_2, EVEX_W_0F3873_P_2,
877 EVEX_W_0F3A50_P_2, EVEX_W_0F3A51_P_2, EVEX_W_0F3A56_P_2,
878 EVEX_W_0F3A57_P_2, EVEX_W_0F3A66_P_2, EVEX_W_0F3A67_P_2,
879 EVEX_W_0F3A71_P_2, EVEX_W_0F3A73_P_2): Delete.
880 (putop): Centralize management of last[]. Delete SAVE_LAST.
881 * i386-dis-evex-w.h: Move entries for opcodes 0F3838, 0F3839,
882 0F3840, 0F3855, 0F3868, 0F3871, 0F3873, 0F3A50, 0F3A51, 0F3A56,
883 0F3A57, 0F3A66, 0F3A67, 0F3A71, and 0F3A73 ...
884 * i386-dis-evex-prefix.h: here.
885
bc152a17
JB		 8862020-07-06 Jan Beulich <jbeulich@suse.com>
887
888 * i386-dis.c (MOD_EVEX_0F381A_P_2_W_0, MOD_EVEX_0F381A_P_2_W_1,
889 MOD_EVEX_0F381B_P_2_W_0, MOD_EVEX_0F381B_P_2_W_1,
890 MOD_EVEX_0F385A_P_2_W_0, MOD_EVEX_0F385A_P_2_W_1,
891 MOD_EVEX_0F385B_P_2_W_0, MOD_EVEX_0F385B_P_2_W_1): New
892 enumerators.
893 (EVEX_LEN_0F381A_P_2_W_0, EVEX_LEN_0F381A_P_2_W_1,
894 EVEX_LEN_0F381B_P_2_W_0, EVEX_LEN_0F381B_P_2_W_1,
895 EVEX_LEN_0F385A_P_2_W_0, EVEX_LEN_0F385A_P_2_W_1,
896 EVEX_LEN_0F385B_P_2_W_0, EVEX_LEN_0F385B_P_2_W_1): Rename to ...
897 (EVEX_LEN_0F381A_P_2_W_0_M_0, EVEX_LEN_0F381A_P_2_W_1_M_0,
898 EVEX_LEN_0F381B_P_2_W_0_M_0, EVEX_LEN_0F381B_P_2_W_1_M_0,
899 EVEX_LEN_0F385A_P_2_W_0_M_0, EVEX_LEN_0F385A_P_2_W_1_M_0,
900 EVEX_LEN_0F385B_P_2_W_0_M_0, EVEX_LEN_0F385B_P_2_W_1_M_0): ...
901 these, respectively.
902 * i386-dis-evex-len.h: Adjust comments.
903 * i386-dis-evex-mod.h: New MOD_EVEX_0F381A_P_2_W_0,
904 MOD_EVEX_0F381A_P_2_W_1, MOD_EVEX_0F381B_P_2_W_0,
905 MOD_EVEX_0F381B_P_2_W_1, MOD_EVEX_0F385A_P_2_W_0,
906 MOD_EVEX_0F385A_P_2_W_1, MOD_EVEX_0F385B_P_2_W_0, and
907 MOD_EVEX_0F385B_P_2_W_1 table entries.
908 * i386-dis-evex-w.h: Reference mod_table[] for
909 EVEX_W_0F381A_P_2, EVEX_W_0F381B_P_2, EVEX_W_0F385A_P_2, and
910 EVEX_W_0F385B_P_2.
911
c82a99a0
JB		 9122020-07-06 Jan Beulich <jbeulich@suse.com>
913
914 * i386-dis-evex-len.h (vbroadcastf32x8, vbroadcasti32x8,
915 vinsertf32x8, vinsertf64x4, vextractf32x8, vextractf64x4): Use
916 EXymm.
917 (vinserti32x8, vinserti64x4, vextracti32x8, vextracti64x4):
918 Likewise. Mark 256-bit entries invalid.
919
fedfb81e
JB		 9202020-07-06 Jan Beulich <jbeulich@suse.com>
921
922 * i386-dis.c (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
923 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
924 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
925 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
926 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
927 PREFIX_EVEX_0F382B): Delete.
928 (EVEX_W_0F62_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6B_P_2,
929 EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2, EVEX_W_0FD2_P_2,
930 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FF2_P_2,
931 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2,
932 EVEX_W_0FFB_P_2, EVEX_W_0FFE_P_2, EVEX_W_0F382B_P_2): Rename
933 to ...
934 (EVEX_W_0F62, EVEX_W_0F6A, EVEX_W_0F6B, EVEX_W_0F6C,
935 EVEX_W_0F6D, EVEX_W_0FD2, EVEX_W_0FD3, EVEX_W_0FD4,
936 EVEX_W_0FF2, EVEX_W_0FF3, EVEX_W_0FF4, EVEX_W_0FFA,
937 EVEX_W_0FFB, EVEX_W_0FFE, EVEX_W_0F382B): ... these
938 respectively.
939 * i386-dis-evex.h (evex_table): Reference VEX_W table entries
940 for opcodes 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4,
941 0FF2, 0FF3, 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
942 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F62, PREFIX_EVEX_0F6A,
943 PREFIX_EVEX_0F6B, PREFIX_EVEX_0F6C, PREFIX_EVEX_0F6D,
944 PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3, PREFIX_EVEX_0FD4,
945 PREFIX_EVEX_0FF2, PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4,
946 PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB, PREFIX_EVEX_0FFE,
947 PREFIX_EVEX_0F382B): Remove table entries.
948 * i386-dis-evex-w.h: Reference VEX table entries for opcodes
949 0F62, 0F6A, 0F6B, 0F6C, 0F6D, 0FD2, 0FD3, 0FD4, 0FF2, 0FF3,
950 0FF4, 0FFA, 0FFB, 0FFE, 0F382B.
951
3a57774c
JB		 9522020-07-06 Jan Beulich <jbeulich@suse.com>
953
954 * i386-dis.c (EVEX_LEN_0F3816_P_2, EVEX_LEN_0F3836_P_2,
955 EVEX_LEN_0F3A00_P_2_W_1, EVEX_LEN_0F3A01_P_2_W_1): New
956 enumerators.
957 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0F3816_P_2,
958 EVEX_LEN_0F3836_P_2, EVEX_LEN_0F3A00_P_2_W_1, and
959 EVEX_LEN_0F3A01_P_2_W_1 table entries.
960 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
961 entries.
962
e74d9fa9
JB		 9632020-07-06 Jan Beulich <jbeulich@suse.com>
964
965 * i386-dis.c (EVEX_LEN_0FC4_P_2, EVEX_LEN_0FC5_P_2,
966 EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2, EVEX_LEN_0F3A16_P_2,
967 EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
968 EVEX_LEN_0F3A21_P_2_W_0, EVEX_LEN_0F3A22_P_2): New enumerators.
969 * i386-dis-evex-len.h (evex_len_table): New EVEX_LEN_0FC4_P_2,
970 EVEX_LEN_0FC5_P_2, EVEX_LEN_0F3A14_P_2, EVEX_LEN_0F3A15_P_2,
971 EVEX_LEN_0F3A16_P_2, EVEX_LEN_0F3A17_P_2, EVEX_LEN_0F3A20_P_2,
972 EVEX_LEN_0F3A21_P_2_W_0, and EVEX_LEN_0F3A22_P_2 table entries.
973 * i386-dis-evex-prefix.h, i386-dis-evex-w.h: Reference the above
974 entries.
975
6431c801
JB		 9762020-07-06 Jan Beulich <jbeulich@suse.com>
977
978 * i386-dis.c (PREFIX_EVEX_0F3A1D, EVEX_W_0F3A1D_P_2): Delete.
979 (VEX_W_0F3813_P_2, VEX_W_0F3A1D_P_2): New enumerators.
980 (prefix_table): Reference VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2
981 respectively.
982 (vex_w_table): New VEX_W_0F3813_P_2 and VEX_W_0F3A1D_P_2 table
983 entries.
984 * i386-dis-evex.h (evex_table): Reference VEX table entry for
985 opcode 0F3A1D.
986 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F3A1D): Delete table
987 entry.
988 * i386-dis-evex-w.h (EVEX_W_0F3A1D_P_2): Likewise.
989
6df22cf6
JB		 9902020-07-06 Jan Beulich <jbeulich@suse.com>
991
992 * i386-dis.c (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
993 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
994 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
995 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
996 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
997 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
998 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
999 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1000 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1001 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1002 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1003 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1004 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1005 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1006 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1007 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1008 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1009 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1010 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1011 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1012 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1013 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1014 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1015 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1016 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1017 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1018 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF,
1019 EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2, EVEX_W_0F3858_P_2,
1020 EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2, EVEX_W_0F3A04_P_2,
1021 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2): Delete.
1022 (prefix_table): Add EXxEVexR to FMA table entries.
1023 (OP_Rounding): Move abort() invocation.
1024 * i386-dis-evex.h (evex_table): Reference VEX table for opcodes
1025 0F60, 0F61, 0F63, 0F67, 0F68, 0F69, 0FD1, 0FD5, 0FD8, 0FD9,
1026 0FDA, 0FDC, 0FDD, 0FDE, 0FE0, 0FE1, 0FE3, 0FE4, 0FE5, 0FE8,
1027 0FE9, 0FEA, 0FEC, 0FED, 0FEE, 0FF1, 0FF5, 0FF6, 0FF8, 0FF9,
1028 0FFC, 0FFD, 0F3800, 0F3804, 0F380B, 0F380C, 0F3818, 0F381C,
1029 0F381D, 0F383C, 0F383E, 0F3858, 0F3878, 0F3879, 0F3896, 0F3897,
1030 0F3898, 0F3899, 0F389C, 0F389D, 0F389E, 0F389F, 0F38A6, 0F38A7,
1031 0F38A8, 0F38A9, 0F38AC, 0F38AD, 0F38AE, 0F38AF, 0F38B6, 0F38B7,
1032 0F38B8, 0F38B9, 0F38BA, 0F38BB, 0F38BC, 0F38BD, 0F38BE, 0F38BF,
1033 0F38CF, 0F38DC, 0F38DD, 0F38DE, 0F38DF, 0F3A04, 0F3A0F, 0F3A44,
1034 0F3ACE, 0F3ACF.
1035 * i386-dis-evex-prefix.h (PREFIX_EVEX_0F60, PREFIX_EVEX_0F61,
1036 PREFIX_EVEX_0F63, PREFIX_EVEX_0F67, PREFIX_EVEX_0F68,
1037 PREFIX_EVEX_0F69, PREFIX_EVEX_0FD1, PREFIX_EVEX_0FD5,
1038 PREFIX_EVEX_0FD8, PREFIX_EVEX_0FD9, PREFIX_EVEX_0FDA,
1039 PREFIX_EVEX_0FDC, PREFIX_EVEX_0FDD, PREFIX_EVEX_0FDE,
1040 PREFIX_EVEX_0FE0, PREFIX_EVEX_0FE1, PREFIX_EVEX_0FE3,
1041 PREFIX_EVEX_0FE4, PREFIX_EVEX_0FE5, PREFIX_EVEX_0FE8,
1042 PREFIX_EVEX_0FE9, PREFIX_EVEX_0FEA, PREFIX_EVEX_0FEC,
1043 PREFIX_EVEX_0FED, PREFIX_EVEX_0FEE, PREFIX_EVEX_0FF1,
1044 PREFIX_EVEX_0FF5, PREFIX_EVEX_0FF6, PREFIX_EVEX_0FF8,
1045 PREFIX_EVEX_0FF9, PREFIX_EVEX_0FFC, PREFIX_EVEX_0FFD,
1046 PREFIX_EVEX_0F3800, PREFIX_EVEX_0F3804, PREFIX_EVEX_0F380B,
1047 PREFIX_EVEX_0F380C, PREFIX_EVEX_0F3818, PREFIX_EVEX_0F381C,
1048 PREFIX_EVEX_0F381D, PREFIX_EVEX_0F383C, PREFIX_EVEX_0F383E,
1049 PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3878, PREFIX_EVEX_0F3879,
1050 PREFIX_EVEX_0F3896, PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898,
1051 PREFIX_EVEX_0F3899, PREFIX_EVEX_0F389C, PREFIX_EVEX_0F389D,
1052 PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F, PREFIX_EVEX_0F38A6,
1053 PREFIX_EVEX_0F38A7, PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9,
1054 PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD, PREFIX_EVEX_0F38AE,
1055 PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6, PREFIX_EVEX_0F38B7,
1056 PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9, PREFIX_EVEX_0F38BA,
1057 PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC, PREFIX_EVEX_0F38BD,
1058 PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF, PREFIX_EVEX_0F38CF,
1059 PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD, PREFIX_EVEX_0F38DE,
1060 PREFIX_EVEX_0F38DF, PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A0F,
1061 PREFIX_EVEX_0F3A44, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF):
1062 Delete table entries.
1063 * i386-dis-evex-w.h (EVEX_W_0F380C_P_2, EVEX_W_0F3818_P_2,
1064 EVEX_W_0F3858_P_2, EVEX_W_0F3878_P_2, EVEX_W_0F3879_P_2,
1065 EVEX_W_0F3A04_P_2, EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2):
1066 Likewise.
1067
39e0f456
JB		 10682020-07-06 Jan Beulich <jbeulich@suse.com>
1069
1070 * i386-dis.c (EXqScalarS): Delete.
1071 (vex_len_table): Replace EXqScalarS by EXqVexScalarS.
1072 * i386-dis-evex-w.h (vmovq): Use EXqVexScalarS.
1073
5b872f7d
JB		 10742020-07-06 Jan Beulich <jbeulich@suse.com>
1075
1076 * i386-dis.c (safe-ctype.h): Include.
1077 (EXdScalar, EXqScalar): Delete.
1078 (d_scalar_mode, q_scalar_mode): Delete.
1079 (prefix_table, vex_len_table): Use EXxmm_md in place of
1080 EXdScalar and EXxmm_mq in place of EXqScalar.
1081 (intel_operand_size, OP_E_memory, OP_EX): Remove uses of
1082 d_scalar_mode and q_scalar_mode.
1083 * i386-dis-evex-w.h (vmovss): Use EXxmm_md.
1084 (vmovsd): Use EXxmm_mq.
1085
ddc73fa9
NC		 10862020-07-06 Yuri Chornoivan <yurchor@ukr.net>
1087
1088 PR 26204
1089 * arc-dis.c: Fix spelling mistake.
1090 * po/opcodes.pot: Regenerate.
1091
17550be7
NC		 10922020-07-06 Nick Clifton <nickc@redhat.com>
1093
1094 * po/pt_BR.po: Updated Brazilian Portugugese translation.
1095 * po/uk.po: Updated Ukranian translation.
1096
b19d852d
NC		 10972020-07-04 Nick Clifton <nickc@redhat.com>
1098
1099 * configure: Regenerate.
1100 * po/opcodes.pot: Regenerate.
1101
b115b9fd
NC		 11022020-07-04 Nick Clifton <nickc@redhat.com>
1103
1104 Binutils 2.35 branch created.
1105
c2ecccb3
L		 11062020-07-02 H.J. Lu <hongjiu.lu@intel.com>
1107
1108 * i386-gen.c (opcode_modifiers): Add VexSwapSources.
1109 * i386-opc.h (VexSwapSources): New.
1110 (i386_opcode_modifier): Add vexswapsources.
1111 * i386-opc.tbl: Add VexSwapSources to BMI2 and BMI instructions
1112 with two source operands swapped.
1113 * i386-tbl.h: Regenerated.
1114
08ccfccf
NC		 11152020-06-30 Nelson Chu <nelson.chu@sifive.com>
1116
1117 * riscv-dis.c (print_insn_args, case 'E'): Updated. Let the
1118 unprivileged CSR can also be initialized.
1119
279edac5
AM		 11202020-06-29 Alan Modra <amodra@gmail.com>
1121
1122 * arm-dis.c: Use C style comments.
1123 * cr16-opc.c: Likewise.
1124 * ft32-dis.c: Likewise.
1125 * moxie-opc.c: Likewise.
1126 * tic54x-dis.c: Likewise.
1127 * s12z-opc.c: Remove useless comment.
1128 * xgate-dis.c: Likewise.
1129
e978ad62
L		 11302020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1131
1132 * i386-opc.tbl: Add a blank line.
1133
63112cd6
L		 11342020-06-26 H.J. Lu <hongjiu.lu@intel.com>
1135
1136 * i386-gen.c (opcode_modifiers): Replace VecSIB with SIB.
1137 (VecSIB128): Renamed to ...
1138 (VECSIB128): This.
1139 (VecSIB256): Renamed to ...
1140 (VECSIB256): This.
1141 (VecSIB512): Renamed to ...
1142 (VECSIB512): This.
1143 (VecSIB): Renamed to ...
1144 (SIB): This.
1145 (i386_opcode_modifier): Replace vecsib with sib.
79b32e73 1146 * i386-opc.tbl (VecSIB128): New.
63112cd6
L		 1147 (VecSIB256): Likewise.
1148 (VecSIB512): Likewise.
79b32e73 1149 Replace VecSIB=1, VecSIB=2 and VecSIB=3 with VecSIB128, VecSIB256
63112cd6
L		 1150 and VecSIB512, respectively.
1151
d1c36125
JB		 11522020-06-26 Jan Beulich <jbeulich@suse.com>
1153
1154 * i386-dis.c: Adjust description of I macro.
1155 (x86_64_table): Drop use of I.
1156 (float_mem): Replace use of I.
1157 (putop): Remove handling of I. Adjust setting/clearing of "alt".
1158
2a1bb84c
JB		 11592020-06-26 Jan Beulich <jbeulich@suse.com>
1160
1161 * i386-dis.c: (print_insn): Avoid straight assignment to
1162 priv.orig_sizeflag when processing -M sub-options.
1163
8f570d62
JB		 11642020-06-25 Jan Beulich <jbeulich@suse.com>
1165
1166 * i386-dis.c: Adjust description of J macro.
1167 (dis386, x86_64_table, mod_table): Replace J.
1168 (putop): Remove handling of J.
1169
464dc4af
JB		 11702020-06-25 Jan Beulich <jbeulich@suse.com>
1171
1172 * i386-dis.c: (float_mem): Reduce alternatives for fstpt and fldpt.
1173
589958d6
JB		 11742020-06-25 Jan Beulich <jbeulich@suse.com>
1175
1176 * i386-dis.c: Adjust description of "LQ" macro.
1177 (dis386_twobyte): Use LQ for sysret.
1178 (putop): Adjust handling of LQ.
1179
39ff0b81
NC		 11802020-06-22 Nelson Chu <nelson.chu@sifive.com>
1181
1182 * riscv-opc.c: Move the structures and functions to bfd/elfxx-riscv.c.
1183 * riscv-dis.c: Include elfxx-riscv.h.
1184
d27c357a
JB		 11852020-06-18 H.J. Lu <hongjiu.lu@intel.com>
1186
1187 * i386-dis.c (prefix_table): Revert the last vmgexit change.
1188
6fde587f
CL		 11892020-06-17 Lili Cui <lili.cui@intel.com>
1190
1191 * i386-dis.c (prefix_table): Delete the incorrect vmgexit.
1192
efe30057
L		 11932020-06-14 H.J. Lu <hongjiu.lu@intel.com>
1194
1195 PR gas/26115
1196 * i386-dis.c (prefix_table): Replace xsuspldtrk with xsusldtrk.
1197 * i386-opc.tbl: Likewise.
1198 * i386-tbl.h: Regenerated.
1199
d8af286f
NC		 12002020-06-12 Nelson Chu <nelson.chu@sifive.com>
1201
1202 * riscv-opc.c (priv_specs): Remove v1.9 and PRIV_SPEC_CLASS_1P9.
1203
14962256
AC		 12042020-06-11 Alex Coplan <alex.coplan@arm.com>
1205
1206 * aarch64-opc.c (SYSREG): New macro for describing system registers.
1207 (SR_CORE): Likewise.
1208 (SR_FEAT): Likewise.
1209 (SR_RNG): Likewise.
1210 (SR_V8_1): Likewise.
1211 (SR_V8_2): Likewise.
1212 (SR_V8_3): Likewise.
1213 (SR_V8_4): Likewise.
1214 (SR_PAN): Likewise.
1215 (SR_RAS): Likewise.
1216 (SR_SSBS): Likewise.
1217 (SR_SVE): Likewise.
1218 (SR_ID_PFR2): Likewise.
1219 (SR_PROFILE): Likewise.
1220 (SR_MEMTAG): Likewise.
1221 (SR_SCXTNUM): Likewise.
1222 (aarch64_sys_regs): Refactor to store feature information in the table.
1223 (aarch64_sys_reg_supported_p): Collapse logic for system registers
1224 that now describe their own features.
1225 (aarch64_pstatefield_supported_p): Likewise.
1226
f9630fa6
L		 12272020-06-09 H.J. Lu <hongjiu.lu@intel.com>
1228
1229 * i386-dis.c (prefix_table): Fix a typo in comments.
1230
73239888
JB		 12312020-06-09 Jan Beulich <jbeulich@suse.com>
1232
1233 * i386-dis.c (rex_ignored): Delete.
1234 (ckprefix): Drop rex_ignored initialization.
1235 (get_valid_dis386): Drop setting of rex_ignored.
1236 (print_insn): Drop checking of rex_ignored. Don't record data
1237 size prefix as used with VEX-and-alike encodings.
1238
18897deb
JB		 12392020-06-09 Jan Beulich <jbeulich@suse.com>
1240
1241 * i386-dis.c (MOD_0F12_PREFIX_2, MOD_0F16_PREFIX_2,
1242 MOD_VEX_0F12_PREFIX_2, MOD_VEX_0F16_PREFIX_2): New enumerators.
1243 (VEX_LEN_0F12_P_2, VEX_LEN_0F16_P_2): Delete.
1244 (VEX_LEN_0F12_P_2_M_0, VEX_LEN_0F16_P_2_M_0): Define.
1245 (prefix_table): Decode MOD for cases 2 of opcodes 0F12, 0F16,
1246 VEX_0F12, and VEX_0F16.
1247 (vex_len_table): Use X for vmovlp* and vmovh*s. Drop
1248 VEX_LEN_0F12_P_2 and VEX_LEN_0F16_P_2 entries.
1249 (mod_table): Use X for movlpX and movhpX. Drop PREFIX_OPCODE
1250 from movlps and movhlps. New MOD_0F12_PREFIX_2,
1251 MOD_0F16_PREFIX_2, MOD_VEX_0F12_PREFIX_2, and
1252 MOD_VEX_0F16_PREFIX_2 entries.
1253
97e6786a
JB		 12542020-06-09 Jan Beulich <jbeulich@suse.com>
1255
1256 * i386-dis.c (MOD_EVEX_0F12_PREFIX_2, MOD_EVEX_0F13,
1257 MOD_EVEX_0F16_PREFIX_2, MOD_EVEX_0F17, MOD_EVEX_0F2B): New enumerators.
1258 (PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1259 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F29,
1260 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F54, PREFIX_EVEX_0F55,
1261 PREFIX_EVEX_0F56, PREFIX_EVEX_0F57, PREFIX_EVEX_0FC6,
1262 EVEX_W_0F10_P_0, EVEX_W_0F10_P_2, EVEX_W_0F11_P_0,
1263 EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_2,
1264 EVEX_W_0F13_P_0, EVEX_W_0F13_P_2, EVEX_W_0F14_P_0,
1265 EVEX_W_0F14_P_2, EVEX_W_0F15_P_0, EVEX_W_0F15_P_2,
1266 EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0,
1267 EVEX_W_0F17_P_2, EVEX_W_0F28_P_0, EVEX_W_0F28_P_2,
1268 EVEX_W_0F29_P_0, EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0,
1269 EVEX_W_0F2B_P_2, EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2,
1270 EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0,
1271 EVEX_W_0F51_P_2, EVEX_W_0F54_P_0, EVEX_W_0F54_P_2,
1272 EVEX_W_0F55_P_0, EVEX_W_0F55_P_2, EVEX_W_0F56_P_0,
1273 EVEX_W_0F56_P_2, EVEX_W_0F57_P_0, EVEX_W_0F57_P_2,
1274 EVEX_W_0F58_P_0, EVEX_W_0F58_P_2, EVEX_W_0F59_P_0,
1275 EVEX_W_0F59_P_2, EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2,
1276 EVEX_W_0F5D_P_0, EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0,
1277 EVEX_W_0F5E_P_2, EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2,
1278 EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0,
1279 EVEX_W_0FC6_P_2): Delete.
1280 (print_insn): Add EVEX.W vs embedded prefix consistency check
1281 to prefix validation.
1282 * i386-dis-evex.h (evex_table): Don't further descend for
1283 vunpcklpX, vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX,
1284 and vshufpX. Continue with MOD decoding for opcodes 0F13, 0F17,
1285 and 0F2B.
1286 * i386-dis-evex-mod.h: Add/adjust vmovlpX/vmovhpX entries.
1287 * i386-dis-evex-prefix.h: Don't further descend for vmovupX,
1288 vucomisX, vcomisX, vsqrtpX, vaddpX, vmulpX, vsubpX, vminpX,
1289 vdivpX, vmaxpX, and vcmppX. Continue with MOD decoding for cases
1290 2 of PREFIX_EVEX_0F12, PREFIX_EVEX_0F16, and PREFIX_EVEX_0F29.
1291 Drop PREFIX_EVEX_0F13, PREFIX_EVEX_0F14, PREFIX_EVEX_0F15,
1292 PREFIX_EVEX_0F17, PREFIX_EVEX_0F28, PREFIX_EVEX_0F2B,
1293 PREFIX_EVEX_0F54, PREFIX_EVEX_0F55, PREFIX_EVEX_0F56,
1294 PREFIX_EVEX_0F57, and PREFIX_EVEX_0FC6 entries.
1295 * i386-dis-evex-w.h: Drop EVEX_W_0F10_P_0, EVEX_W_0F10_P_2,
1296 EVEX_W_0F11_P_0, EVEX_W_0F11_P_2, EVEX_W_0F12_P_0_M_0,
1297 EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
1298 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2,
1299 EVEX_W_0F15_P_0, EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0,
1300 EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
1301 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0,
1302 EVEX_W_0F29_P_2, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
1303 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0,
1304 EVEX_W_0F2F_P_2, EVEX_W_0F51_P_0, EVEX_W_0F51_P_2,
1305 EVEX_W_0F54_P_0, EVEX_W_0F54_P_2, EVEX_W_0F55_P_0,
1306 EVEX_W_0F55_P_2, EVEX_W_0F56_P_0, EVEX_W_0F56_P_2,
1307 EVEX_W_0F57_P_0, EVEX_W_0F57_P_2, EVEX_W_0F58_P_0,
1308 EVEX_W_0F58_P_2, EVEX_W_0F59_P_0, EVEX_W_0F59_P_2,
1309 EVEX_W_0F5C_P_0, EVEX_W_0F5C_P_2, EVEX_W_0F5D_P_0,
1310 EVEX_W_0F5D_P_2, EVEX_W_0F5E_P_0, EVEX_W_0F5E_P_2,
1311 EVEX_W_0F5F_P_0, EVEX_W_0F5F_P_2, EVEX_W_0FC2_P_0,
1312 EVEX_W_0FC2_P_2, EVEX_W_0FC6_P_0, and EVEX_W_0FC6_P_2 entries.
1313
bf926894
JB		 13142020-06-09 Jan Beulich <jbeulich@suse.com>
1315
1316 * i386-dis.c (vex_table): Use PREFIX_OPCODE for vunpcklpX,
1317 vunpckhpX, vmovapX, vandpX, vandnpX, vorpX, vxorpX and vshufpX.
1318 (vex_len_table) : Likewise for vmovlpX, vmovhpX, vmovntpX, and
1319 vmovmskpX.
1320 (print_insn): Drop pointless check against bad_opcode. Split
1321 prefix validation into legacy and VEX-and-alike parts.
1322 (putop): Re-work 'X' macro handling.
1323
a5aaedb9
JB		 13242020-06-09 Jan Beulich <jbeulich@suse.com>
1325
1326 * i386-dis.c (MOD_0F51): Rename to ...
1327 (MOD_0F50): ... this.
1328
26417f19
AC		 13292020-06-08 Alex Coplan <alex.coplan@arm.com>
1330
1331 * arm-dis.c (arm_opcodes): Add dfb.
1332 (thumb32_opcodes): Add dfb.
1333
8a6fb3f9
JB		 13342020-06-08 Jan Beulich <jbeulich@suse.com>
1335
1336 * i386-opc.h (reg_entry): Const-qualify reg_name field.
1337
1424c35d
AM		 13382020-06-06 Alan Modra <amodra@gmail.com>
1339
1340 * ppc-dis.c (ppc_opts): Accept -mpwr10/-Mpwr10.
1341
d3d1cc7b
AM		 13422020-06-05 Alan Modra <amodra@gmail.com>
1343
1344 * cgen-dis.c (hash_insn_array): Increase size of buf. Assert
1345 size is large enough.
1346
d8740be1
JM		 13472020-06-04 Jose E. Marchesi <jose.marchesi@oracle.com>
1348
1349 * disassemble.c (disassemble_init_for_target): Set endian_code for
1350 bpf targets.
1351 * bpf-desc.c: Regenerate.
1352 * bpf-opc.c: Likewise.
1353 * bpf-dis.c: Likewise.
1354
e9bffec9
JM		 13552020-06-03 Jose E. Marchesi <jose.marchesi@oracle.com>
1356
1357 * cgen-opc.c (cgen_get_insn_value): Get an `endian' argument.
1358 (cgen_put_insn_value): Likewise.
1359 (cgen_lookup_insn): Pass endianness to cgen_{get,put}_insn_value.
1360 * cgen-dis.in (print_insn): Likewise.
1361 * cgen-ibld.in (insert_1): Likewise.
1362 (insert_1): Likewise.
1363 (insert_insn_normal): Likewise.
1364 (extract_1): Likewise.
1365 * bpf-dis.c: Regenerate.
1366 * bpf-ibld.c: Likewise.
1367 * bpf-ibld.c: Likewise.
1368 * cgen-dis.in: Likewise.
1369 * cgen-ibld.in: Likewise.
1370 * cgen-opc.c: Likewise.
1371 * epiphany-dis.c: Likewise.
1372 * epiphany-ibld.c: Likewise.
1373 * fr30-dis.c: Likewise.
1374 * fr30-ibld.c: Likewise.
1375 * frv-dis.c: Likewise.
1376 * frv-ibld.c: Likewise.
1377 * ip2k-dis.c: Likewise.
1378 * ip2k-ibld.c: Likewise.
1379 * iq2000-dis.c: Likewise.
1380 * iq2000-ibld.c: Likewise.
1381 * lm32-dis.c: Likewise.
1382 * lm32-ibld.c: Likewise.
1383 * m32c-dis.c: Likewise.
1384 * m32c-ibld.c: Likewise.
1385 * m32r-dis.c: Likewise.
1386 * m32r-ibld.c: Likewise.
1387 * mep-dis.c: Likewise.
1388 * mep-ibld.c: Likewise.
1389 * mt-dis.c: Likewise.
1390 * mt-ibld.c: Likewise.
1391 * or1k-dis.c: Likewise.
1392 * or1k-ibld.c: Likewise.
1393 * xc16x-dis.c: Likewise.
1394 * xc16x-ibld.c: Likewise.
1395 * xstormy16-dis.c: Likewise.
1396 * xstormy16-ibld.c: Likewise.
1397
b3db6d07
JM		 13982020-06-04 Jose E. Marchesi <jemarch@gnu.org>
1399
1400 * cgen-dis.in (cpu_desc_list): New field `insn_endian'.
1401 (print_insn_): Handle instruction endian.
1402 * bpf-dis.c: Regenerate.
1403 * bpf-desc.c: Regenerate.
1404 * epiphany-dis.c: Likewise.
1405 * epiphany-desc.c: Likewise.
1406 * fr30-dis.c: Likewise.
1407 * fr30-desc.c: Likewise.
1408 * frv-dis.c: Likewise.
1409 * frv-desc.c: Likewise.
1410 * ip2k-dis.c: Likewise.
1411 * ip2k-desc.c: Likewise.
1412 * iq2000-dis.c: Likewise.
1413 * iq2000-desc.c: Likewise.
1414 * lm32-dis.c: Likewise.
1415 * lm32-desc.c: Likewise.
1416 * m32c-dis.c: Likewise.
1417 * m32c-desc.c: Likewise.
1418 * m32r-dis.c: Likewise.
1419 * m32r-desc.c: Likewise.
1420 * mep-dis.c: Likewise.
1421 * mep-desc.c: Likewise.
1422 * mt-dis.c: Likewise.
1423 * mt-desc.c: Likewise.
1424 * or1k-dis.c: Likewise.
1425 * or1k-desc.c: Likewise.
1426 * xc16x-dis.c: Likewise.
1427 * xc16x-desc.c: Likewise.
1428 * xstormy16-dis.c: Likewise.
1429 * xstormy16-desc.c: Likewise.
1430
4ee4189f
NC		 14312020-06-03 Nick Clifton <nickc@redhat.com>
1432
1433 * po/sr.po: Updated Serbian translation.
1434
44730156
NC		 14352020-06-03 Nelson Chu <nelson.chu@sifive.com>
1436
1437 * riscv-opc.c (riscv_get_isa_spec_class): Change bfd_boolean to int.
1438 (riscv_get_priv_spec_class): Likewise.
1439
3c3d0376
AM		 14402020-06-01 Alan Modra <amodra@gmail.com>
1441
1442 * bpf-desc.c: Regenerate.
1443
78c1c354
JM		 14442020-05-28 Jose E. Marchesi <jose.marchesi@oracle.com>
1445 David Faust <david.faust@oracle.com>
1446
1447 * bpf-desc.c: Regenerate.
1448 * bpf-opc.h: Likewise.
1449 * bpf-opc.c: Likewise.
1450 * bpf-dis.c: Likewise.
1451
efcf5fb5
AM		 14522020-05-28 Alan Modra <amodra@gmail.com>
1453
1454 * nios2-dis.c (nios2_print_insn_arg): Avoid shift left of negative
1455 values.
1456
ab382d64
AM		 14572020-05-28 Alan Modra <amodra@gmail.com>
1458
1459 * ns32k-dis.c (print_insn_arg): Handle d value of 'f' for
1460 immediates.
1461 (print_insn_ns32k): Revert last change.
1462
151f5de4
NC		 14632020-05-28 Nick Clifton <nickc@redhat.com>
1464
1465 * ns32k-dis.c (print_insn_ns32k): Change the arg_bufs array to
1466 static.
1467
25e1eca8
SL		 14682020-05-26 Sandra Loosemore <sandra@codesourcery.com>
1469
1470 Fix extraction of signed constants in nios2 disassembler (again).
1471
1472 * nios2-dis.c (nios2_print_insn_arg): Add explicit casts to
1473 extractions of signed fields.
1474
57b17940
SSF		 14752020-05-26 Stefan Schulze Frielinghaus <stefansf@linux.ibm.com>
1476
1477 * s390-opc.txt: Relocate vector load/store instructions with
1478 additional alignment parameter and change architecture level
1479 constraint from z14 to z13.
1480
d96bf37b
AM		 14812020-05-21 Alan Modra <amodra@gmail.com>
1482
1483 * arc-ext.c: Replace "if (x) free (x)" with "free (x)" throughout.
1484 * sparc-dis.c: Likewise.
1485 * tic4x-dis.c: Likewise.
1486 * xtensa-dis.c: Likewise.
1487 * bpf-desc.c: Regenerate.
1488 * epiphany-desc.c: Regenerate.
1489 * fr30-desc.c: Regenerate.
1490 * frv-desc.c: Regenerate.
1491 * ip2k-desc.c: Regenerate.
1492 * iq2000-desc.c: Regenerate.
1493 * lm32-desc.c: Regenerate.
1494 * m32c-desc.c: Regenerate.
1495 * m32r-desc.c: Regenerate.
1496 * mep-asm.c: Regenerate.
1497 * mep-desc.c: Regenerate.
1498 * mt-desc.c: Regenerate.
1499 * or1k-desc.c: Regenerate.
1500 * xc16x-desc.c: Regenerate.
1501 * xstormy16-desc.c: Regenerate.
1502
8f595e9b
NC		 15032020-05-20 Nelson Chu <nelson.chu@sifive.com>
1504
1505 * riscv-opc.c (riscv_ext_version_table): The table used to store
1506 all information about the supported spec and the corresponding ISA
1507 versions. Currently, only Zicsr is supported to verify the
1508 correctness of Z sub extension settings. Others will be supported
1509 in the future patches.
1510 (struct isa_spec_t, isa_specs): List for all supported ISA spec
1511 classes and the corresponding strings.
1512 (riscv_get_isa_spec_class): New function. Get the corresponding ISA
1513 spec class by giving a ISA spec string.
1514 * riscv-opc.c (struct priv_spec_t): New structure.
1515 (struct priv_spec_t priv_specs): List for all supported privilege spec
1516 classes and the corresponding strings.
1517 (riscv_get_priv_spec_class): New function. Get the corresponding
1518 privilege spec class by giving a spec string.
1519 (riscv_get_priv_spec_name): New function. Get the corresponding
1520 privilege spec string by giving a CSR version class.
1521 * riscv-dis.c: Updated since DECLARE_CSR is changed.
1522 * riscv-dis.c: Add new disassembler option -Mpriv-spec to dump the CSR
1523 according to the chosen version. Build a hash table riscv_csr_hash to
1524 store the valid CSR for the chosen pirv verison. Dump the direct
1525 CSR address rather than it's name if it is invalid.
1526 (parse_riscv_dis_option_without_args): New function. Parse the options
1527 without arguments.
1528 (parse_riscv_dis_option): Call parse_riscv_dis_option_without_args to
1529 parse the options without arguments first, and then handle the options
1530 with arguments. Add the new option -Mpriv-spec, which has argument.
1531 * riscv-dis.c (print_riscv_disassembler_options): Add description
1532 about the new OBJDUMP option.
1533
3d205eb4
PB		 15342020-05-19 Peter Bergner <bergner@linux.ibm.com>
1535
1536 * ppc-opc.c (insert_ls, extract_ls): Handle 3-bit L fields and new
1537 WC values on POWER10 sync, dcbf and wait instructions.
1538 (insert_pl, extract_pl): New functions.
1539 (L2OPT, LS, WC): Use insert_ls and extract_ls.
1540 (LS3): New , 3-bit L for sync.
1541 (LS3, L3OPT): New, 3-bit L for sync and dcbf.
1542 (SC2, PL): New, 2-bit SC and PL for sync and wait.
1543 (XWCPL_MASK, XL3RT_MASK, XSYNCLS_MASK): New instruction masks.
1544 (XOPL3, XWCPL, XSYNCLS): New opcode macros.
1545 (powerpc_opcodes) <dcbflp, dcbfps, dcbstps pause_short, phwsync,
1546 plwsync, stcisync, stncisync, stsync, waitrsv>: New extended mnemonics.
1547 <wait>: Enable PL operand on POWER10.
1548 <dcbf>: Enable L3OPT operand on POWER10.
1549 <sync>: Enable SC2 operand on POWER10.
1550
a501eb44
SH		 15512020-05-19 Stafford Horne <shorne@gmail.com>
1552
1553 PR 25184
1554 * or1k-asm.c: Regenerate.
1555 * or1k-desc.c: Regenerate.
1556 * or1k-desc.h: Regenerate.
1557 * or1k-dis.c: Regenerate.
1558 * or1k-ibld.c: Regenerate.
1559 * or1k-opc.c: Regenerate.
1560 * or1k-opc.h: Regenerate.
1561 * or1k-opinst.c: Regenerate.
1562
3b646889
AM		 15632020-05-11 Alan Modra <amodra@gmail.com>
1564
1565 * ppc-opc (powerpc_opcodes): Add xscmpeqqp, xscmpgeqp, xscmpgtqp,
1566 xsmaxcqp, xsmincqp.
1567
9cc4ce88
AM		 15682020-05-11 Alan Modra <amodra@gmail.com>
1569
1570 * ppc-opc.c (powerpc_opcodes): Add lxvrbx, lxvrhx, lxvrwx, lxvrdx,
1571 stxvrbx, stxvrhx, stxvrwx, stxvrdx.
1572
5d57bc3f
AM		 15732020-05-11 Alan Modra <amodra@gmail.com>
1574
1575 * ppc-opc.c (powerpc_opcodes): Add xvtlsbb.
1576
66ef5847
AM		 15772020-05-11 Alan Modra <amodra@gmail.com>
1578
1579 * ppc-opc.c (powerpc_opcodes): Add vstribl, vstribr, vstrihl, vstrihr,
1580 vclrlb, vclrrb, vstribl., vstribr., vstrihl., vstrihr..
1581
4f3e9537
PB		 15822020-05-11 Peter Bergner <bergner@linux.ibm.com>
1583
1584 * ppc-opc.c (powerpc_opcodes) <setbc, setbcr, setnbc, setnbcr>: New
1585 mnemonics.
1586
ec40e91c
AM		 15872020-05-11 Alan Modra <amodra@gmail.com>
1588
1589 * ppc-opc.c (UIM8, P_U8XX4_MASK): Define.
1590 (powerpc_opcodes): Add vgnb, vcfuged, vpextd, vpdepd, vclzdm,
1591 vctzdm, cntlzdm, pdepd, pextd, cfuged, cnttzdm.
1592 (prefix_opcodes): Add xxeval.
1593
d7e97a76
AM		 15942020-05-11 Alan Modra <amodra@gmail.com>
1595
1596 * ppc-opc.c (powerpc_opcodes): Add xxgenpcvbm, xxgenpcvhm,
1597 xxgenpcvwm, xxgenpcvdm.
1598
fdefed7c
AM		 15992020-05-11 Alan Modra <amodra@gmail.com>
1600
1601 * ppc-opc.c (MP, VXVAM_MASK): Define.
1602 (VXVAPS_MASK): Use VXVA_MASK.
1603 (powerpc_opcodes): Add mtvsrbmi, vexpandbm, vexpandhm, vexpandwm,
1604 vexpanddm, vexpandqm, vextractbm, vextracthm, vextractwm,
1605 vextractdm, vextractqm, mtvsrbm, mtvsrhm, mtvsrwm, mtvsrdm, mtvsrqm,
1606 vcntmbb, vcntmbh, vcntmbw, vcntmbd.
1607
aa3c112f
AM		 16082020-05-11 Alan Modra <amodra@gmail.com>
1609 Peter Bergner <bergner@linux.ibm.com>
1610
1611 * ppc-opc.c (insert_xa6a, extract_xa6a, insert_xb6a, extract_xb6a):
1612 New functions.
1613 (powerpc_operands): Define ACC, PMSK8, PMSK4, PMSK2, XMSK, YMSK,
1614 YMSK2, XA6a, XA6ap, XB6a entries.
1615 (PMMIRR, P_X_MASK, P_XX1_MASK, P_GER_MASK): Define
1616 (P_GER2_MASK, P_GER4_MASK, P_GER8_MASK, P_GER64_MASK): Define.
1617 (PPCVSX4): Define.
1618 (powerpc_opcodes): Add xxmfacc, xxmtacc, xxsetaccz,
1619 xvi8ger4pp, xvi8ger4, xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger,
1620 xvi4ger8pp, xvi4ger8, xvi16ger2spp, xvi16ger2s, xvbf16ger2pp,
1621 xvbf16ger2, xvf64gerpp, xvf64ger, xvi16ger2, xvf16ger2np,
1622 xvf32gernp, xvi8ger4spp, xvi16ger2pp, xvbf16ger2np, xvf64gernp,
1623 xvf16ger2pn, xvf32gerpn, xvbf16ger2pn, xvf64gerpn, xvf16ger2nn,
1624 xvf32gernn, xvbf16ger2nn, xvf64gernn, xvcvbf16sp, xvcvspbf16.
1625 (prefix_opcodes): Add pmxvi8ger4pp, pmxvi8ger4, pmxvf16ger2pp,
1626 pmxvf16ger2, pmxvf32gerpp, pmxvf32ger, pmxvi4ger8pp, pmxvi4ger8,
1627 pmxvi16ger2spp, pmxvi16ger2s, pmxvbf16ger2pp, pmxvbf16ger2,
1628 pmxvf64gerpp, pmxvf64ger, pmxvi16ger2, pmxvf16ger2np, pmxvf32gernp,
1629 pmxvi8ger4spp, pmxvi16ger2pp, pmxvbf16ger2np, pmxvf64gernp,
1630 pmxvf16ger2pn, pmxvf32gerpn, pmxvbf16ger2pn, pmxvf64gerpn,
1631 pmxvf16ger2nn, pmxvf32gernn, pmxvbf16ger2nn, pmxvf64gernn.
1632
6edbfd3b
AM		 16332020-05-11 Alan Modra <amodra@gmail.com>
1634
1635 * ppc-opc.c (insert_imm32, extract_imm32): New functions.
1636 (insert_xts, extract_xts): New functions.
1637 (IMM32, UIM3, IX, UIM5, SH3, XTS, P8RR): Define.
1638 (P_XX4_MASK, P_UXX4_MASK, VSOP, P_VS_MASK, P_VSI_MASK): Define.
1639 (VXRC_MASK, VXSH_MASK): Define.
1640 (powerpc_opcodes): Add vinsbvlx, vsldbi, vextdubvlx, vextdubvrx,
1641 vextduhvlx, vextduhvrx, vextduwvlx, vextduwvrx, vextddvlx,
1642 vextddvrx, vinshvlx, vinswvlx, vinsw, vinsbvrx, vinshvrx,
1643 vinswvrx, vinsd, vinsblx, vsrdbi, vinshlx, vinswlx, vinsdlx,
1644 vinsbrx, vinshrx, vinswrx, vinsdrx, lxvkq.
1645 (prefix_opcodes): Add xxsplti32dx, xxspltidp, xxspltiw, xxblendvb,
1646 xxblendvh, xxblendvw, xxblendvd, xxpermx.
1647
c7d7aea2
AM		 16482020-05-11 Alan Modra <amodra@gmail.com>
1649
1650 * ppc-opc.c (powerpc_opcodes): Add vrlq, vdivuq, vmsumcud, vrlqmi,
1651 vmuloud, vcmpuq, vslq, vdivsq, vcmpsq, vrlqnm, vcmpequq, vmulosd,
1652 vsrq, vdiveuq, vcmpgtuq, vmuleud, vsraq, vdivesq, vcmpgtsq, vmulesd,
1653 vcmpequq., vextsd2q, vmoduq, vcmpgtuq., vmodsq, vcmpgtsq., xscvqpuqz,
1654 xscvuqqp, xscvqpsqz, xscvsqqp, dcffixqq, dctfixqq.
1655
94ba9882
AM		 16562020-05-11 Alan Modra <amodra@gmail.com>
1657
1658 * ppc-opc.c (insert_xtp, extract_xtp): New functions.
1659 (XTP, DQXP, DQXP_MASK): Define.
1660 (powerpc_opcodes): Add lxvp, stxvp, lxvpx, stxvpx.
1661 (prefix_opcodes): Add plxvp and pstxvp.
1662
f4791f1a
AM		 16632020-05-11 Alan Modra <amodra@gmail.com>
1664
1665 * ppc-opc.c (powerpc_opcodes): Add vdivuw, vdivud, vdivsw, vmulld,
1666 vdivsd, vmulhuw, vdiveuw, vmulhud, vdiveud, vmulhsw, vdivesw,
1667 vmulhsd, vdivesd, vmoduw, vmodud, vmodsw, vmodsd.
1668
3ff0a5ba
PB		 16692020-05-11 Peter Bergner <bergner@linux.ibm.com>
1670
1671 * ppc-opc.c (powerpc_opcodes) <brd, brh, brw>: New mnemonics.
1672
afef4fe9
PB		 16732020-05-11 Peter Bergner <bergner@linux.ibm.com>
1674
1675 * ppc-opc.c (insert_l1opt, extract_l1opt): New functions.
1676 (L1OPT): Define.
1677 (powerpc_opcodes) <paste.>: Add L operand for cpu POWER10.
1678
1224c05d
PB		 16792020-05-11 Peter Bergner <bergner@linux.ibm.com>
1680
1681 * ppc-opc.c (powerpc_opcodes) <slbiag>: Add variant with L operand.
1682
6bbb0c05
AM		 16832020-05-11 Alan Modra <amodra@gmail.com>
1684
1685 * ppc-dis.c (powerpc_init_dialect): Default to "power10".
1686
7c1f4227
AM		 16872020-05-11 Alan Modra <amodra@gmail.com>
1688
1689 * ppc-dis.c (ppc_opts): Add "power10" entry.
1690 (print_insn_powerpc): Update for PPC_OPCODE_POWER10 renaming.
1691 * ppc-opc.c (POWER10): Rename from POWERXX. Update all uses.
1692
73199c2b
NC		 16932020-05-11 Nick Clifton <nickc@redhat.com>
1694
1695 * po/fr.po: Updated French translation.
1696
09c1e68a
AC		 16972020-04-30 Alex Coplan <alex.coplan@arm.com>
1698
1699 * aarch64-opc.h (enum aarch64_field_kind): Add FLD_imm16_2.
1700 * aarch64-opc.c (fields): Add entry for FLD_imm16_2.
1701 (operand_general_constraint_met_p): validate
1702 AARCH64_OPND_UNDEFINED.
1703 * aarch64-tbl.h (aarch64_opcode_table): Add udf instruction, entry
1704 for FLD_imm16_2.
1705 * aarch64-asm-2.c: Regenerated.
1706 * aarch64-dis-2.c: Regenerated.
1707 * aarch64-opc-2.c: Regenerated.
1708
9654d51a
NC		 17092020-04-29 Nick Clifton <nickc@redhat.com>
1710
1711 PR 22699
1712 * sh-opc.h: Also use unsigned 8-bit immediate values for the LDRC
1713 and SETRC insns.
1714
c2e71e57
NC		 17152020-04-29 Nick Clifton <nickc@redhat.com>
1716
1717 * po/sv.po: Updated Swedish translation.
1718
5c936ef5
NC		 17192020-04-29 Nick Clifton <nickc@redhat.com>
1720
1721 PR 22699
1722 * sh-opc.h (IMM0_8): Replace with IMM0_8S and IMM0_8U. Use
1723 IMM0_8S for arithmetic insns and IMM0_8U for logical insns.
1724 * sh-dis.c (print_insn_sh): Change IMM0_8 case to IMM0_8S and add
1725 IMM0_8U case.
1726
bb2a1453
AS		 17272020-04-21 Andreas Schwab <schwab@linux-m68k.org>
1728
1729 PR 25848
1730 * m68k-opc.c (m68k_opcodes): Allow pc-rel for second operand of
1731 cmpi only on m68020up and cpu32.
1732
c2e5c986
SD		 17332020-04-20 Sudakshina Das <sudi.das@arm.com>
1734
1735 * aarch64-asm.c (aarch64_ins_none): New.
1736 * aarch64-asm.h (ins_none): New declaration.
1737 * aarch64-dis.c (aarch64_ext_none): New.
1738 * aarch64-dis.h (ext_none): New declaration.
1739 * aarch64-opc.c (aarch64_print_operand): Update case for
1740 AARCH64_OPND_BARRIER_PSB.
1741 * aarch64-tbl.h (aarch64_opcode_table): Add tsb.
1742 (AARCH64_OPERANDS): Update inserter/extracter for
1743 AARCH64_OPND_BARRIER_PSB to use new dummy functions.
1744 * aarch64-asm-2.c: Regenerated.
1745 * aarch64-dis-2.c: Regenerated.
1746 * aarch64-opc-2.c: Regenerated.
1747
8a6e1d1d
SD		 17482020-04-20 Sudakshina Das <sudi.das@arm.com>
1749
1750 * aarch64-tbl.h (aarch64_feature_bti, BTI, BTI_INSN): Remove.
1751 (aarch64_feature_ras, RAS): Likewise.
1752 (aarch64_feature_stat_profile, STAT_PROFILE): Likewise.
1753 (aarch64_opcode_table): Update bti, xpaclri, pacia1716, pacib1716,
1754 autia1716, autib1716, esb, psb, dgh, paciaz, paciasp, pacibz, pacibsp,
1755 autiaz, autiasp, autibz, autibsp to be CORE_INSN.
1756 * aarch64-asm-2.c: Regenerated.
1757 * aarch64-dis-2.c: Regenerated.
1758 * aarch64-opc-2.c: Regenerated.
1759
e409955d
FS		 17602020-04-17 Fredrik Strupe <fredrik@strupe.net>
1761
1762 * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
1763 (print_insn_neon): Support disassembly of conditional
1764 instructions.
1765
c54a9b56
DF		 17662020-02-16 David Faust <david.faust@oracle.com>
1767
1768 * bpf-desc.c: Regenerate.
1769 * bpf-desc.h: Likewise.
1770 * bpf-opc.c: Regenerate.
1771 * bpf-opc.h: Likewise.
1772
bb651e8b
CL		 17732020-04-07 Lili Cui <lili.cui@intel.com>
1774
1775 * i386-dis.c (enum): Add PREFIX_0F01_REG_5_MOD_3_RM_1,
1776 (prefix_table): New instructions (see prefixes above).
1777 (rm_table): Likewise
1778 * i386-gen.c (cpu_flag_init): Add CPU_TSXLDTRK_FLAGS,
1779 CPU_ANY_TSXLDTRK_FLAGS.
1780 (cpu_flags): Add CpuTSXLDTRK.
1781 * i386-opc.h (enum): Add CpuTSXLDTRK.
1782 (i386_cpu_flags): Add cputsxldtrk.
1783 * i386-opc.tbl: Add XSUSPLDTRK insns.
1784 * i386-init.h: Regenerate.
1785 * i386-tbl.h: Likewise.
1786
4b27d27c
L		 17872020-04-02 Lili Cui <lili.cui@intel.com>
1788
1789 * i386-dis.c (prefix_table): New instructions serialize.
1790 * i386-gen.c (cpu_flag_init): Add CPU_SERIALIZE_FLAGS,
1791 CPU_ANY_SERIALIZE_FLAGS.
1792 (cpu_flags): Add CpuSERIALIZE.
1793 * i386-opc.h (enum): Add CpuSERIALIZE.
1794 (i386_cpu_flags): Add cpuserialize.
1795 * i386-opc.tbl: Add SERIALIZE insns.
1796 * i386-init.h: Regenerate.
1797 * i386-tbl.h: Likewise.
1798
832a5807
AM		 17992020-03-26 Alan Modra <amodra@gmail.com>
1800
1801 * disassemble.h (opcodes_assert): Declare.
1802 (OPCODES_ASSERT): Define.
1803 * disassemble.c: Don't include assert.h. Include opintl.h.
1804 (opcodes_assert): New function.
1805 * h8300-dis.c (bfd_h8_disassemble_init): Use OPCODES_ASSERT.
1806 (bfd_h8_disassemble): Reduce size of data array. Correctly
1807 calculate maxlen. Omit insn decoding when insn length exceeds
1808 maxlen. Exit from nibble loop when looking for E, before
1809 accessing next data byte. Move processing of E outside loop.
1810 Replace tests of maxlen in loop with assertions.
1811
4c4addbe
AM		 18122020-03-26 Alan Modra <amodra@gmail.com>
1813
1814 * arc-dis.c (find_format): Init needs_limm. Simplify use of limm.
1815
a18cd0ca
AM		 18162020-03-25 Alan Modra <amodra@gmail.com>
1817
1818 * z80-dis.c (suffix): Init mybuf.
1819
57cb32b3
AM		 18202020-03-22 Alan Modra <amodra@gmail.com>
1821
1822 * h8300-dis.c (bfd_h8_disassemble): Limit data[] access to that
1823 successflly read from section.
1824
beea5cc1
AM		 18252020-03-22 Alan Modra <amodra@gmail.com>
1826
1827 * arc-dis.c (find_format): Use ISO C string concatenation rather
1828 than line continuation within a string. Don't access needs_limm
1829 before testing opcode != NULL.
1830
03704c77
AM		 18312020-03-22 Alan Modra <amodra@gmail.com>
1832
1833 * ns32k-dis.c (print_insn_arg): Update comment.
1834 (print_insn_ns32k): Reduce size of index_offset array, and
1835 initialize, passing -1 to print_insn_arg for args that are not
1836 an index. Don't exit arg loop early. Abort on bad arg number.
1837
d1023b5d
AM		 18382020-03-22 Alan Modra <amodra@gmail.com>
1839
1840 * s12z-dis.c (abstract_read_memory): Don't print error on EOI.
1841 * s12z-opc.c: Formatting.
1842 (operands_f): Return an int.
1843 (opr_n_bytes_p1): Return -1 on reaching buffer memory limit.
1844 (opr_n_bytes2, bfextins_n_bytes, mul_n_bytes, bm_n_bytes),
1845 (shift_n_bytes, mov_imm_opr_n_bytes, loop_prim_n_bytes),
1846 (exg_sex_discrim): Likewise.
1847 (create_immediate_operand, create_bitfield_operand),
1848 (create_register_operand_with_size, create_register_all_operand),
1849 (create_register_all16_operand, create_simple_memory_operand),
1850 (create_memory_operand, create_memory_auto_operand): Don't
1851 segfault on malloc failure.
1852 (z_ext24_decode): Return an int status, negative on fail, zero
1853 on success.
1854 (x_imm1, imm1_decode, trap_decode, z_opr_decode, z_opr_decode2),
1855 (imm1234, reg_s_imm, reg_s_opr, z_imm1234_8base, z_imm1234_0base),
1856 (z_tfr, z_reg, reg_xy, lea_reg_xys_opr, lea_reg_xys, rel_15_7),
1857 (decode_rel_15_7, cmp_xy, sub_d6_x_y, sub_d6_y_x),
1858 (ld_18bit_decode, mul_decode, bm_decode, bm_rel_decode),
1859 (mov_imm_opr, ld_18bit_decode, exg_sex_decode),
1860 (loop_primitive_decode, shift_decode, psh_pul_decode),
1861 (bit_field_decode): Similarly.
1862 (z_decode_signed_value, decode_signed_value): Similarly. Add arg
1863 to return value, update callers.
1864 (x_opr_decode_with_size): Check all reads, returning NULL on fail.
1865 Don't segfault on NULL operand.
1866 (decode_operation): Return OP_INVALID on first fail.
1867 (decode_s12z): Check all reads, returning -1 on fail.
1868
340f3ac8
AM		 18692020-03-20 Alan Modra <amodra@gmail.com>
1870
1871 * metag-dis.c (print_insn_metag): Don't ignore status from
1872 read_memory_func.
1873
fe90ae8a
AM		 18742020-03-20 Alan Modra <amodra@gmail.com>
1875
1876 * nds32-dis.c (print_insn_nds32): Remove unnecessary casts.
1877 Initialize parts of buffer not written when handling a possible
1878 2-byte insn at end of section. Don't attempt decoding of such
1879 an insn by the 4-byte machinery.
1880
833d919c
AM		 18812020-03-20 Alan Modra <amodra@gmail.com>
1882
1883 * ppc-dis.c (print_insn_powerpc): Only clear needed bytes of
1884 partially filled buffer. Prevent lookup of 4-byte insns when
1885 only VLE 2-byte insns are possible due to section size. Print
1886 ".word" rather than ".long" for 2-byte leftovers.
1887
327ef784
NC		 18882020-03-17 Sergey Belyashov <sergey.belyashov@gmail.com>
1889
1890 PR 25641
1891 * z80-dis.c: Fix disassembling ED+A4/AC/B4/BC opcodes.
1892
1673df32
JB		 18932020-03-13 Jan Beulich <jbeulich@suse.com>
1894
1895 * i386-dis.c (X86_64_0D): Rename to ...
1896 (X86_64_0E): ... this.
1897
384f3689
L		 18982020-03-09 H.J. Lu <hongjiu.lu@intel.com>
1899
1900 * Makefile.am ($(srcdir)/i386-init.h): Also pass -P to $(CPP).
1901 * Makefile.in: Regenerated.
1902
865e2027
JB		 19032020-03-09 Jan Beulich <jbeulich@suse.com>
1904
1905 * i386-opc.tbl (avx_irel): New. Use is for AVX512 vpcmp*
1906 3-operand pseudos.
1907 * i386-tbl.h: Re-generate.
1908
2f13234b
JB		 19092020-03-09 Jan Beulich <jbeulich@suse.com>
1910
1911 * i386-opc.tbl (xop_elem, xop_irel, xop_sign): New. Use them for XOP vpcom*,
1912 vprot*, vpsha*, and vpshl*.
1913 * i386-tbl.h: Re-generate.
1914
3fabc179
JB		 19152020-03-09 Jan Beulich <jbeulich@suse.com>
1916
1917 * i386-opc.tbl (avx_frel): New. Use it for AVX/AVX512 vcmpps,
1918 vcmpss, vcmppd, and vcmpsd 3-operand pseudo-ops.
1919 * i386-tbl.h: Re-generate.
1920
3677e4c1
JB		 19212020-03-09 Jan Beulich <jbeulich@suse.com>
1922
1923 * i386-gen.c (set_bitfield): Ignore zero-length field names.
1924 * i386-opc.tbl (sse_frel): New. Use it for SSE/SSE2 cmpps,
1925 cmpss, cmppd, and cmpsd 2-operand pseudo-ops.
1926 * i386-tbl.h: Re-generate.
1927
4c4898e8
JB		 19282020-03-09 Jan Beulich <jbeulich@suse.com>
1929
1930 * i386-gen.c (struct template_arg, struct template_instance,
1931 struct template_param, struct template, templates,
1932 parse_template, expand_templates): New.
1933 (process_i386_opcodes): Various local variables moved to
1934 expand_templates. Call parse_template and expand_templates.
1935 * i386-opc.tbl (cc): New. Use it for Jcc, SETcc, and CMOVcc.
1936 * i386-tbl.h: Re-generate.
1937
bc49bfd8
JB		 19382020-03-06 Jan Beulich <jbeulich@suse.com>
1939
1940 * i386-opc.tbl (vcvtdq2pd, vcvtps2pd, vcvtudq2pd, vcvtps2ph,
1941 vcvtps2qq, vcvtps2uqq, vcvttps2qq, vcvttps2uqq): Fold separate
1942 register and memory source templates. Replace VexW= by VexW*
1943 where applicable.
1944 * i386-tbl.h: Re-generate.
1945
4873e243
JB		 19462020-03-06 Jan Beulich <jbeulich@suse.com>
1947
1948 * i386-opc.tbl: Drop IgnoreSize from various SIMD insns. Replace
1949 VexW= by VexW* and VexVVVV=1 by just VexVVVV where applicable.
1950 * i386-tbl.h: Re-generate.
1951
672a349b
JB		 19522020-03-06 Jan Beulich <jbeulich@suse.com>
1953
1954 * i386-opc.tbl (fildll, fistpll, fisttpll): Add ATTSyntax.
1955 * i386-tbl.h: Re-generate.
1956
4ed21b58
JB		 19572020-03-06 Jan Beulich <jbeulich@suse.com>
1958
1959 * i386-opc.tbl (movq): Drop NoRex64 from XMM/XMM SSE2AVX variants.
1960 (movmskps, pextrw, pinsrw, pmovmskb, movmskpd, extractps,
1961 pextrb, pinsrb, roundsd): Drop NoRex64 and where applicable use
1962 VexW0 on SSE2AVX variants.
1963 (vmovq): Drop NoRex64 from XMM/XMM variants.
1964 (vextractps, vmovmskpd, vmovmskps, vpextrb, vpextrw, vpinsrb,
1965 vpinsrw, vpmovmskb, vroundsd, vpmovmskb): Drop NoRex64 and where
1966 applicable use VexW0.
1967 * i386-tbl.h: Re-generate.
1968
643bb870
JB		 19692020-03-06 Jan Beulich <jbeulich@suse.com>
1970
1971 * i386-gen.c (opcode_modifiers): Remove Rex64 field.
1972 * i386-opc.h (Rex64): Delete.
1973 (struct i386_opcode_modifier): Remove rex64 field.
1974 * i386-opc.tbl (crc32): Drop Rex64.
1975 Replace Rex64 with Size64 everywhere else.
1976 * i386-tbl.h: Re-generate.
1977
a23b33b3
JB		 19782020-03-06 Jan Beulich <jbeulich@suse.com>
1979
1980 * i386-dis.c (OP_E_memory): Exclude recording of used address
1981 prefix for "bnd" modes only in 64-bit mode. Don't decode 16-bit
1982 addressed memory operands for MPX insns.
1983
a0497384
JB		 19842020-03-06 Jan Beulich <jbeulich@suse.com>
1985
1986 * i386-opc.tbl (movmskps, mwait, vmread, vmwrite, invept,
1987 invvpid, invpcid, rdfsbase, rdgsbase, wrfsbase, wrgsbase, adcx,
1988 adox, mwaitx, rdpid, movdiri): Add IgnoreSize.
1989 (ptwrite): Split into non-64-bit and 64-bit forms.
1990 * i386-tbl.h: Re-generate.
1991
b630c145
JB		 19922020-03-06 Jan Beulich <jbeulich@suse.com>
1993
1994 * i386-opc.tbl (tpause, umwait): Add IgnoreSize. Add 3-operand
1995 template.
1996 * i386-tbl.h: Re-generate.
1997
a847e322
JB		 19982020-03-04 Jan Beulich <jbeulich@suse.com>
1999
2000 * i386-dis.c (PREFIX_0F01_REG_3_RM_1): New.
2001 (prefix_table): Move vmmcall here. Add vmgexit.
2002 (rm_table): Replace vmmcall entry by prefix_table[] escape.
2003 * i386-gen.c (cpu_flag_init): Add CPU_SEV_ES_FLAGS entry.
2004 (cpu_flags): Add CpuSEV_ES entry.
2005 * i386-opc.h (CpuSEV_ES): New.
2006 (union i386_cpu_flags): Add cpusev_es field.
2007 * i386-opc.tbl (vmgexit): New.
2008 * i386-init.h, i386-tbl.h: Re-generate.
2009
3cd7f3e3
L		 20102020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2011
2012 * i386-gen.c (opcode_modifiers): Replace IgnoreSize/DefaultSize
2013 with MnemonicSize.
2014 * i386-opc.h (IGNORESIZE): New.
2015 (DEFAULTSIZE): Likewise.
2016 (IgnoreSize): Removed.
2017 (DefaultSize): Likewise.
2018 (MnemonicSize): New.
2019 (i386_opcode_modifier): Replace ignoresize/defaultsize with
2020 mnemonicsize.
2021 * i386-opc.tbl (IgnoreSize): New.
2022 (DefaultSize): Likewise.
2023 * i386-tbl.h: Regenerated.
2024
b8ba1385
SB		 20252020-03-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2026
2027 PR 25627
2028 * z80-dis.c: Fix disassembly of LD IY,(HL) and D (HL),IX
2029 instructions.
2030
10d97a0f
L		 20312020-03-03 H.J. Lu <hongjiu.lu@intel.com>
2032
2033 PR gas/25622
2034 * i386-opc.tbl: Add IgnoreSize to cvtsi2sd, cvtsi2ss, vcvtsi2sd,
2035 vcvtsi2ss, vcvtusi2sd and vcvtusi2ss for AT&T syntax.
2036 * i386-tbl.h: Regenerated.
2037
dc1e8a47
AM		 20382020-02-26 Alan Modra <amodra@gmail.com>
2039
2040 * aarch64-asm.c: Indent labels correctly.
2041 * aarch64-dis.c: Likewise.
2042 * aarch64-gen.c: Likewise.
2043 * aarch64-opc.c: Likewise.
2044 * alpha-dis.c: Likewise.
2045 * i386-dis.c: Likewise.
2046 * nds32-asm.c: Likewise.
2047 * nfp-dis.c: Likewise.
2048 * visium-dis.c: Likewise.
2049
265b4673
CZ		 20502020-02-25 Claudiu Zissulescu <claziss@gmail.com>
2051
2052 * arc-regs.h (int_vector_base): Make it available for all ARC
2053 CPUs.
2054
bd0cf5a6
NC		 20552020-02-20 Nelson Chu <nelson.chu@sifive.com>
2056
2057 * riscv-dis.c (print_insn_args): Updated since the DECLARE_CSR is
2058 changed.
2059
fa164239
JW		 20602020-02-19 Nelson Chu <nelson.chu@sifive.com>
2061
2062 * riscv-opc.c (riscv_opcodes): Convert add/addi to the compressed
2063 c.mv/c.li if rs1 is zero.
2064
272a84b1
L		 20652020-02-17 H.J. Lu <hongjiu.lu@intel.com>
2066
2067 * i386-gen.c (cpu_flag_init): Replace CpuABM with
2068 CpuLZCNT|CpuPOPCNT. Add CpuPOPCNT to CPU_SSE4_2_FLAGS. Add
2069 CPU_POPCNT_FLAGS.
2070 (cpu_flags): Remove CpuABM. Add CpuPOPCNT.
2071 * i386-opc.h (CpuABM): Removed.
2072 (CpuPOPCNT): New.
2073 (i386_cpu_flags): Remove cpuabm. Add cpupopcnt.
2074 * i386-opc.tbl: Replace CpuABM|CpuSSE4_2 with CpuPOPCNT on
2075 popcnt. Remove CpuABM from lzcnt.
2076 * i386-init.h: Regenerated.
2077 * i386-tbl.h: Likewise.
2078
1f730c46
JB		 20792020-02-17 Jan Beulich <jbeulich@suse.com>
2080
2081 * i386-opc.tbl (vcvtsi2sd, vcvtsi2ss, vcvtusi2sd, vcvtusi2ss):
2082 Fold CpuNo64 and Cpu64 templates. Use VexLIG/EVexLIG and VexW0/
2083 VexW1 instead of open-coding them.
2084 * i386-tbl.h: Re-generate.
2085
c8f8eebc
JB		 20862020-02-17 Jan Beulich <jbeulich@suse.com>
2087
2088 * i386-opc.tbl (AddrPrefixOpReg): Define.
2089 (monitor, invlpga, vmload, vmrun, vmsave, clzero, monitorx,
2090 umonitor, movdir64b, enqcmd, enqcmds): Fold Cpu64 and CpuNo64
2091 templates. Drop NoRex64.
2092 * i386-tbl.h: Re-generate.
2093
b9915cbc
JB		 20942020-02-17 Jan Beulich <jbeulich@suse.com>
2095
2096 PR gas/6518
2097 * i386-opc.tbl (vcvtpd2dq, vcvtpd2ps, vcvttpd2dq, vcvtpd2udq,
2098 vcvttpd2udq, vcvtqq2ps, vcvtuqq2ps): Split XMM/YMM source forms
2099 into Intel syntax instance (with Unpsecified) and AT&T one
2100 (without).
2101 (vcvtneps2bf16): Likewise, along with folding the two so far
2102 separate ones.
2103 * i386-tbl.h: Re-generate.
2104
ce504911
L		 21052020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2106
2107 * i386-gen.c (cpu_flag_init): Remove CPU_ANY_SSE3_FLAGS from
2108 CPU_ANY_SSE4A_FLAGS.
2109
dabec65d
AM		 21102020-02-17 Alan Modra <amodra@gmail.com>
2111
2112 * i386-gen.c (cpu_flag_init): Correct last change.
2113
af5c13b0
L		 21142020-02-16 H.J. Lu <hongjiu.lu@intel.com>
2115
2116 * i386-gen.c (cpu_flag_init): Add CPU_ANY_SSE4A_FLAGS. Remove
2117 CPU_ANY_SSE4_FLAGS.
2118
6867aac0
L		 21192020-02-14 H.J. Lu <hongjiu.lu@intel.com>
2120
2121 * i386-opc.tbl (movsx): Remove Intel syntax comments.
2122 (movzx): Likewise.
2123
65fca059
JB		 21242020-02-14 Jan Beulich <jbeulich@suse.com>
2125
2126 PR gas/25438
2127 * i386-opc.tbl (movsx): Fold patterns. Also allow Reg32 as
2128 destination for Cpu64-only variant.
2129 (movzx): Fold patterns.
2130 * i386-tbl.h: Re-generate.
2131
7deea9aa
JB		 21322020-02-13 Jan Beulich <jbeulich@suse.com>
2133
2134 * i386-gen.c (cpu_flag_init): Move CpuSSE4a from
2135 CPU_ANY_SSE_FLAGS entry to CPU_ANY_SSE3_FLAGS one. Add
2136 CPU_ANY_SSE4_FLAGS entry.
2137 * i386-init.h: Re-generate.
2138
6c0946d0
JB		 21392020-02-12 Jan Beulich <jbeulich@suse.com>
2140
2141 * i386-opc.tbl (vfpclasspd, vfpclassps): Add Intel sytax form
2142 with Unspecified, making the present one AT&T syntax only.
2143 * i386-tbl.h: Re-generate.
2144
ddb56fe6
JB		 21452020-02-12 Jan Beulich <jbeulich@suse.com>
2146
2147 * i386-opc.tbl (jmp): Fold CpuNo64 and Amd64 direct variants.
2148 * i386-tbl.h: Re-generate.
2149
5990e377
JB		 21502020-02-12 Jan Beulich <jbeulich@suse.com>
2151
2152 PR gas/24546
2153 * i386-dis.c (putop): Handle REX.W in '^' case for Intel64 mode.
2154 * i386-opc.tbl (lfs, lgs, lss, lcall, ljmp): Split into
2155 Amd64 and Intel64 templates.
2156 (call, jmp): Likewise for far indirect variants. Dro
2157 Unspecified.
2158 * i386-tbl.h: Re-generate.
2159
50128d0c
JB		 21602020-02-11 Jan Beulich <jbeulich@suse.com>
2161
2162 * i386-gen.c (opcode_modifiers): Remove ShortForm entry.
2163 * i386-opc.h (ShortForm): Delete.
2164 (struct i386_opcode_modifier): Remove shortform field.
2165 * i386-opc.tbl (mov, movabs, push, pop, xchg, inc, dec, fld,
2166 fst, fstp, fxch, fcom, fcomp, fucom, fucomp, fadd, faddp, fsub,
2167 fsubp, fsubr, fsubrp, fmul, fmulp, fdiv, fdivp, fdivr, fdivrp,
2168 ffreep, bswap, fcmov*, fcomi, fcomip, fucomi, fucomip, movq):
2169 Drop ShortForm.
2170 * i386-tbl.h: Re-generate.
2171
1e05b5c4
JB		 21722020-02-11 Jan Beulich <jbeulich@suse.com>
2173
2174 * i386-opc.tbl (fcomi, fucomi, fcomip, fcompi, fucomip,
2175 fucompi): Drop ShortForm from operand-less templates.
2176 * i386-tbl.h: Re-generate.
2177
2f5dd314
AM		 21782020-02-11 Alan Modra <amodra@gmail.com>
2179
2180 * cgen-ibld.in (extract_normal): Set *valuep on all return paths.
2181 * bpf-ibld.c, * epiphany-ibld.c, * fr30-ibld.c, * frv-ibld.c,
2182 * ip2k-ibld.c, * iq2000-ibld.c, * lm32-ibld.c, * m32c-ibld.c,
2183 * m32r-ibld.c, * mep-ibld.c, * mt-ibld.c, * or1k-ibld.c,
2184 * xc16x-ibld.c, * xstormy16-ibld.c: Regenerate.
2185
5aae9ae9
MM		 21862020-02-10 Matthew Malcomson <matthew.malcomson@arm.com>
2187
2188 * arm-dis.c (print_insn_cde): Define 'V' parse character.
2189 (cde_opcodes): Add VCX* instructions.
2190
4934a27c
MM		 21912020-02-10 Stam Markianos-Wright <stam.markianos-wright@arm.com>
2192 Matthew Malcomson <matthew.malcomson@arm.com>
2193
2194 * arm-dis.c (struct cdeopcode32): New.
2195 (CDE_OPCODE): New macro.
2196 (cde_opcodes): New disassembly table.
2197 (regnames): New option to table.
2198 (cde_coprocs): New global variable.
2199 (print_insn_cde): New
2200 (print_insn_thumb32): Use print_insn_cde.
2201 (parse_arm_disassembler_options): Parse coprocN args.
2202
4b5aaf5f
L		 22032020-02-10 H.J. Lu <hongjiu.lu@intel.com>
2204
2205 PR gas/25516
2206 * i386-gen.c (opcode_modifiers): Replace AMD64 and Intel64
2207 with ISA64.
2208 * i386-opc.h (AMD64): Removed.
2209 (Intel64): Likewose.
2210 (AMD64): New.
2211 (INTEL64): Likewise.
2212 (INTEL64ONLY): Likewise.
2213 (i386_opcode_modifier): Replace amd64 and intel64 with isa64.
2214 * i386-opc.tbl (Amd64): New.
2215 (Intel64): Likewise.
2216 (Intel64Only): Likewise.
2217 Replace AMD64 with Amd64. Update sysenter/sysenter with
2218 Cpu64 and Intel64Only. Remove AMD64 from sysenter/sysenter.
2219 * i386-tbl.h: Regenerated.
2220
9fc0b501
SB		 22212020-02-07 Sergey Belyashov <sergey.belyashov@gmail.com>
2222
2223 PR 25469
2224 * z80-dis.c: Add support for GBZ80 opcodes.
2225
c5d7be0c
AM		 22262020-02-04 Alan Modra <amodra@gmail.com>
2227
2228 * d30v-dis.c (print_insn): Make "val" and "opnum" unsigned.
2229
44e4546f
AM		 22302020-02-03 Alan Modra <amodra@gmail.com>
2231
2232 * m32c-ibld.c: Regenerate.
2233
b2b1453a
AM		 22342020-02-01 Alan Modra <amodra@gmail.com>
2235
2236 * frv-ibld.c: Regenerate.
2237
4102be5c
JB		 22382020-01-31 Jan Beulich <jbeulich@suse.com>
2239
2240 * i386-dis.c (EXxmm_mdq, xmm_mdq_mode): Delete.
2241 (intel_operand_size, OP_EX): Drop xmm_mdq_mode case label.
2242 (OP_E_memory): Replace xmm_mdq_mode case label by
2243 vex_scalar_w_dq_mode one.
2244 * i386-dis-evex-prefix.h: Replace EXxmm_mdq by EXVexWdqScalar.
2245
825bd36c
JB		 22462020-01-31 Jan Beulich <jbeulich@suse.com>
2247
2248 * i386-dis.c (EXVexWdq, vex_w_dq_mode): Delete.
2249 (vex_vsib_d_w_dq_mode, vex_vsib_q_w_dq_mode,
2250 vex_scalar_w_dq_mode): Don't refer to vex_w_dq_mode in comments.
2251 (intel_operand_size): Drop vex_w_dq_mode case label.
2252
c3036ed0
RS		 22532020-01-31 Richard Sandiford <richard.sandiford@arm.com>
2254
2255 * aarch64-tbl.h (aarch64_opcode): Set C_MAX_ELEM for SVE bfcvt.
2256 Remove C_SCAN_MOVPRFX for SVE bfcvtnt.
2257
0c115f84
AM		 22582020-01-30 Alan Modra <amodra@gmail.com>
2259
2260 * m32c-ibld.c: Regenerate.
2261
bd434cc4
JM		 22622020-01-30 Jose E. Marchesi <jose.marchesi@oracle.com>
2263
2264 * bpf-opc.c: Regenerate.
2265
aeab2b26
JB		 22662020-01-30 Jan Beulich <jbeulich@suse.com>
2267
2268 * i386-dis.c (X86_64_C2, X86_64_C3): New enumerators.
2269 (dis386): Use them to replace C2/C3 table entries.
2270 (x86_64_table): Add X86_64_C2 and X86_64_C3 entries.
2271 * i386-opc.tbl (ret): Split Cpu64 entries into AMD64 and Intel64
2272 ones. Use Size64 instead of DefaultSize on Intel64 ones.
2273 * i386-tbl.h: Re-generate.
2274
62b3f548
JB		 22752020-01-30 Jan Beulich <jbeulich@suse.com>
2276
2277 * i386-opc.tbl (call): Drop DefaultSize from Intel64 JumpDword
2278 forms.
2279 (fldenv, fnstenv, fstenv, fnsave, fsave, frstor): Drop
2280 DefaultSize.
2281 * i386-tbl.h: Re-generate.
2282
1bd8ae10
AM		 22832020-01-30 Alan Modra <amodra@gmail.com>
2284
2285 * tic4x-dis.c (tic4x_dp): Make unsigned.
2286
bc31405e
L		 22872020-01-27 H.J. Lu <hongjiu.lu@intel.com>
2288 Jan Beulich <jbeulich@suse.com>
2289
2290 PR binutils/25445
2291 * i386-dis.c (MOVSXD_Fixup): New function.
2292 (movsxd_mode): New enum.
2293 (x86_64_table): Use MOVSXD_Fixup and movsxd_mode on movsxd.
2294 (intel_operand_size): Handle movsxd_mode.
2295 (OP_E_register): Likewise.
2296 (OP_G): Likewise.
2297 * i386-opc.tbl: Remove Rex64 and allow 32-bit destination
2298 register on movsxd. Add movsxd with 16-bit destination register
2299 for AMD64 and Intel64 ISAs.
2300 * i386-tbl.h: Regenerated.
2301
7568c93b
TC		 23022020-01-27 Tamar Christina <tamar.christina@arm.com>
2303
2304 PR 25403
2305 * aarch64-tbl.h (struct aarch64_opcode): Re-order cfinv.
2306 * aarch64-asm-2.c: Regenerate
2307 * aarch64-dis-2.c: Likewise.
2308 * aarch64-opc-2.c: Likewise.
2309
c006a730
JB		 23102020-01-21 Jan Beulich <jbeulich@suse.com>
2311
2312 * i386-opc.tbl (sysret): Drop DefaultSize.
2313 * i386-tbl.h: Re-generate.
2314
c906a69a
JB		 23152020-01-21 Jan Beulich <jbeulich@suse.com>
2316
2317 * i386-opc.tbl (vcvtneps2bf16x): Add Broadcast, Xmmword, and
2318 Dword.
2319 (vcvtneps2bf16y): Add Broadcast, Ymmword, and Dword.
2320 * i386-tbl.h: Re-generate.
2321
26916852
NC		 23222020-01-20 Nick Clifton <nickc@redhat.com>
2323
2324 * po/de.po: Updated German translation.
2325 * po/pt_BR.po: Updated Brazilian Portuguese translation.
2326 * po/uk.po: Updated Ukranian translation.
2327
4d6cbb64
AM		 23282020-01-20 Alan Modra <amodra@gmail.com>
2329
2330 * hppa-dis.c (fput_const): Remove useless cast.
2331
2bddb71a
AM		 23322020-01-20 Alan Modra <amodra@gmail.com>
2333
2334 * arm-dis.c (print_insn_arm): Wrap 'T' value.
2335
1b1bb2c6
NC		 23362020-01-18 Nick Clifton <nickc@redhat.com>
2337
2338 * configure: Regenerate.
2339 * po/opcodes.pot: Regenerate.
2340
ae774686
NC		 23412020-01-18 Nick Clifton <nickc@redhat.com>
2342
2343 Binutils 2.34 branch created.
2344
07f1f3aa
CB		 23452020-01-17 Christian Biesinger <cbiesinger@google.com>
2346
2347 * opintl.h: Fix spelling error (seperate).
2348
42e04b36
L		 23492020-01-17 H.J. Lu <hongjiu.lu@intel.com>
2350
2351 * i386-opc.tbl: Add {vex} pseudo prefix.
2352 * i386-tbl.h: Regenerated.
2353
2da2eaf4
AV		 23542020-01-16 Andre Vieira <andre.simoesdiasvieira@arm.com>
2355
2356 PR 25376
2357 * opcodes/arm-dis.c (coprocessor_opcodes): Use CORE_HIGH for MVE bits.
2358 (neon_opcodes): Likewise.
2359 (select_arm_features): Make sure we enable MVE bits when selecting
2360 armv8.1-m.main. Make sure we do not enable MVE bits when not selecting
2361 any architecture.
2362
d0849eed
JB		 23632020-01-16 Jan Beulich <jbeulich@suse.com>
2364
2365 * i386-opc.tbl: Drop stale comment from XOP section.
2366
9cf70a44
JB		 23672020-01-16 Jan Beulich <jbeulich@suse.com>
2368
2369 * i386-opc.tbl (movq): Add VexWIG to SSE2AVX XMM->XMM forms.
2370 (extractps): Add VexWIG to SSE2AVX forms.
2371 * i386-tbl.h: Re-generate.
2372
4814632e
JB		 23732020-01-16 Jan Beulich <jbeulich@suse.com>
2374
2375 * i386-opc.tbl (pextrq, pinsrq): Drop IgnoreSize and Qword. Drop
2376 Size64 from and use VexW1 on SSE2AVX forms.
2377 (vpextrq, vpinsrq): Drop IgnoreSize and Qword. Drop Size64 from
2378 VEX-encoded forms. Add Cpu64 to EVEX-encoded forms. Use VexW1.
2379 * i386-tbl.h: Re-generate.
2380
aad09917
AM		 23812020-01-15 Alan Modra <amodra@gmail.com>
2382
2383 * tic4x-dis.c (tic4x_version): Make unsigned long.
2384 (optab, optab_special, registernames): New file scope vars.
2385 (tic4x_print_register): Set up registernames rather than
2386 malloc'd registertable.
2387 (tic4x_disassemble): Delete optable and optable_special. Use
2388 optab and optab_special instead. Throw away old optab,
2389 optab_special and registernames when info->mach changes.
2390
7a6bf3be
SB		 23912020-01-14 Sergey Belyashov <sergey.belyashov@gmail.com>
2392
2393 PR 25377
2394 * z80-dis.c (suffix): Use .db instruction to generate double
2395 prefix.
2396
ca1eaac0
AM		 23972020-01-14 Alan Modra <amodra@gmail.com>
2398
2399 * z8k-dis.c (unpack_instr): Formatting. Cast unsigned short
2400 values to unsigned before shifting.
2401
1d67fe3b
TT		 24022020-01-13 Thomas Troeger <tstroege@gmx.de>
2403
2404 * arm-dis.c (print_insn_arm): Fill in insn info fields for control
2405 flow instructions.
2406 (print_insn_thumb16, print_insn_thumb32): Likewise.
2407 (print_insn): Initialize the insn info.
2408 * i386-dis.c (print_insn): Initialize the insn info fields, and
2409 detect jumps.
2410
5e4f7e05
CZ		 24112012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2412
2413 * arc-opc.c (C_NE): Make it required.
2414
b9fe6b8a
CZ		 24152012-01-13 Claudiu Zissulescu <claziss@gmail.com>
2416
2417 * opcode/arc-dis.c (regnames): Correct ACCL/ACCH naming, fix typo
2418 reserved register name.
2419
90dee485
AM		 24202020-01-13 Alan Modra <amodra@gmail.com>
2421
2422 * ns32k-dis.c (Is_gen): Use strchr, add 'f'.
2423 (print_insn_ns32k): Adjust ioffset for 'f' index_offset.
2424
febda64f
AM		 24252020-01-13 Alan Modra <amodra@gmail.com>
2426
2427 * wasm32-dis.c (print_insn_wasm32): Localise variables. Store
2428 result of wasm_read_leb128 in a uint64_t and check that bits
2429 are not lost when copying to other locals. Use uint32_t for
2430 most locals. Use PRId64 when printing int64_t.
2431
df08b588
AM		 24322020-01-13 Alan Modra <amodra@gmail.com>
2433
2434 * score-dis.c: Formatting.
2435 * score7-dis.c: Formatting.
2436
b2c759ce
AM		 24372020-01-13 Alan Modra <amodra@gmail.com>
2438
2439 * score-dis.c (print_insn_score48): Use unsigned variables for
2440 unsigned values. Don't left shift negative values.
2441 (print_insn_score32): Likewise.
2442 * score7-dis.c (print_insn_score32, print_insn_score16): Likewise.
2443
5496abe1
AM		 24442020-01-13 Alan Modra <amodra@gmail.com>
2445
2446 * tic4x-dis.c (tic4x_print_register): Remove dead code.
2447
202e762b
AM		 24482020-01-13 Alan Modra <amodra@gmail.com>
2449
2450 * fr30-ibld.c: Regenerate.
2451
7ef412cf
AM		 24522020-01-13 Alan Modra <amodra@gmail.com>
2453
2454 * xgate-dis.c (print_insn): Don't left shift signed value.
2455 (ripBits): Formatting, use 1u.
2456
7f578b95
AM		 24572020-01-10 Alan Modra <amodra@gmail.com>
2458
2459 * tilepro-opc.c (parse_insn_tilepro): Make opval unsigned.
2460 * tilegx-opc.c (parse_insn_tilegx): Likewise. Delete raw_opval.
2461
441af85b
AM		 24622020-01-10 Alan Modra <amodra@gmail.com>
2463
2464 * m10300-dis.c (disassemble): Move extraction of DREG, AREG, RREG,
2465 and XRREG value earlier to avoid a shift with negative exponent.
2466 * m10200-dis.c (disassemble): Similarly.
2467
bce58db4
NC		 24682020-01-09 Nick Clifton <nickc@redhat.com>
2469
2470 PR 25224
2471 * z80-dis.c (ld_ii_ii): Use correct cast.
2472
40c75bc8
SB		 24732020-01-03 Sergey Belyashov <sergey.belyashov@gmail.com>
2474
2475 PR 25224
2476 * z80-dis.c (ld_ii_ii): Use character constant when checking
2477 opcode byte value.
2478
d835a58b
JB		 24792020-01-09 Jan Beulich <jbeulich@suse.com>
2480
2481 * i386-dis.c (SEP_Fixup): New.
2482 (SEP): Define.
2483 (dis386_twobyte): Use it for sysenter/sysexit.
2484 (enum x86_64_isa): Change amd64 enumerator to value 1.
2485 (OP_J): Compare isa64 against intel64 instead of amd64.
2486 * i386-opc.tbl (sysenter, sysexit): Split into AMD64 and Intel64
2487 forms.
2488 * i386-tbl.h: Re-generate.
2489
030a2e78
AM		 24902020-01-08 Alan Modra <amodra@gmail.com>
2491
2492 * z8k-dis.c: Include libiberty.h
2493 (instr_data_s): Make max_fetched unsigned.
2494 (z8k_lookup_instr): Make nibl_index and tabl_index unsigned.
2495 Don't exceed byte_info bounds.
2496 (output_instr): Make num_bytes unsigned.
2497 (unpack_instr): Likewise for nibl_count and loop.
2498 * z8kgen.c (gas <opcode_entry_type>): Make noperands, length and
2499 idx unsigned.
2500 * z8k-opc.h: Regenerate.
2501
bb82aefe
SV		 25022020-01-07 Shahab Vahedi <shahab@synopsys.com>
2503
2504 * arc-tbl.h (llock): Use 'LLOCK' as class.
2505 (llockd): Likewise.
2506 (scond): Use 'SCOND' as class.
2507 (scondd): Likewise.
2508 (llockd): Set data_size_mode to 'C_ZZ_D' which is 64-bit.
2509 (scondd): Likewise.
2510
cc6aa1a6
AM		 25112020-01-06 Alan Modra <amodra@gmail.com>
2512
2513 * m32c-ibld.c: Regenerate.
2514
660e62b1
AM		 25152020-01-06 Alan Modra <amodra@gmail.com>
2516
2517 PR 25344
2518 * z80-dis.c (suffix): Don't use a local struct buffer copy.
2519 Peek at next byte to prevent recursion on repeated prefix bytes.
2520 Ensure uninitialised "mybuf" is not accessed.
2521 (print_insn_z80): Don't zero n_fetch and n_used here,..
2522 (print_insn_z80_buf): ..do it here instead.
2523
c9ae58fe
AM		 25242020-01-04 Alan Modra <amodra@gmail.com>
2525
2526 * m32r-ibld.c: Regenerate.
2527
5f57d4ec
AM		 25282020-01-04 Alan Modra <amodra@gmail.com>
2529
2530 * cr16-dis.c (cr16_match_opcode): Avoid shift left of signed value.
2531
2c5c1196
AM		 25322020-01-04 Alan Modra <amodra@gmail.com>
2533
2534 * crx-dis.c (match_opcode): Avoid shift left of signed value.
2535
2e98c6c5
AM		 25362020-01-04 Alan Modra <amodra@gmail.com>
2537
2538 * d30v-dis.c (print_insn): Avoid signed overflow in left shift.
2539
567dfba2
JB		 25402020-01-03 Jan Beulich <jbeulich@suse.com>
2541
5437a02a
JB		 2542 * aarch64-tbl.h (aarch64_opcode_table): Use
2543 SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}.
2544
25452020-01-03 Jan Beulich <jbeulich@suse.com>
2546
2547 * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD
567dfba2
JB		 2548 forms of SUDOT and USDOT.
2549
8c45011a
JB		 25502020-01-03 Jan Beulich <jbeulich@suse.com>
2551
5437a02a 2552 * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from
8c45011a
JB		 2553 uzip{1,2}.
2554 * opcodes/aarch64-dis-2.c: Re-generate.
2555
f4950f76
JB		 25562020-01-03 Jan Beulich <jbeulich@suse.com>
2557
5437a02a 2558 * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit
f4950f76
JB		 2559 FMMLA encoding.
2560 * opcodes/aarch64-dis-2.c: Re-generate.
2561
6655dba2
SB		 25622020-01-02 Sergey Belyashov <sergey.belyashov@gmail.com>
2563
2564 * z80-dis.c: Add support for eZ80 and Z80 instructions.
2565
b14ce8bf
AM		 25662020-01-01 Alan Modra <amodra@gmail.com>
2567
2568 Update year range in copyright notice of all files.
2569
0b114740 2570For older changes see ChangeLog-2019
3499769a 2571\f
0b114740 2572Copyright (C) 2020 Free Software Foundation, Inc.
3499769a
AM		 2573
2574Copying and distribution of this file, with or without modification,
2575are permitted in any medium without royalty provided the copyright
2576notice and this notice are preserved.
2577
2578Local Variables:
2579mode: change-log
2580left-margin: 8
2581fill-column: 74
2582version-control: never
2583End:
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