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4fd0a9fd
MW		 12015-12-14 Matthew Wahab <matthew.wahab@arm.com>
2
3 * aarch64-asm-2.c: Regenerate.
4 * aarch64-dis-2.c: Regenerate.
5 * aarch64-opc-2.c: Regenerate.
6 * aarch64-tbl.h (QL_SSHIFT_H): New.
7 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
8 and fcvtzu to the Adv.SIMD scalar shift by immediate group.
9
b5b0f34c
MW		 102015-12-14 Matthew Wahab <matthew.wahab@arm.com>
11
12 * aarch64-asm-2.c: Regenerate.
13 * aarch64-dis-2.c: Regenerate.
14 * aarch64-opc-2.c: Regenerate.
15 * aarch64-tbl.h (QL_VSHIFT_H): New.
16 (aarch64_opcode_table): Add fp16 versions of scvtf, fcvtzs, ucvtf
17 and fcvtzu to the Adv.SIMD shift by immediate group.
18
b195470d
MW		 192015-12-14 Matthew Wahab <matthew.wahab@arm.com>
20
21 * aarch64-asm-2.c: Regenerate.
22 * aarch64-dis-2.c: Regenerate.
23 * aarch64-opc-2.c: Regenerate.
24 * aarch64-tbl.h (QL_SISD_PAIR_H): New.
25 (aarch64_opcode_table): Add fp16 versions of fmaxnmp, faddp,
26 fmaxp, fminnmp, fminp to the Adv.SIMD scalar pairwise group.
27
3067d3b9
MW		 282015-12-14 Matthew Wahab <matthew.wahab@arm.coM>
29
30 * aarch64-dis.c (get_vreg_qualifier_from_value): Update comment
31 and adjust calculation to ignore qualifier for type 2H.
32 * aarch64-opc.c (aarch64_opnd_qualifier): Add "2H".
33
4b5fc357
MW		 342015-12-14 Matthew Wahab <matthew.wahab@arm.com>
35
36 * aarch64-asm-2.c: Regenerate.
37 * aarch64-dis-2.c: Regenerate.
38 * aarch64-opc-2.c: Regenerate.
39 * aarch64-tbl.h (QL_SIMD_IMM_H): New.
40 (aarch64_opcode_table): Add fp16 version of fmov to the Adv.SIMD
41 modified immediate group.
42
bb515fea
MW		 432015-12-14 Matthew Wahab <matthew.wahab@arm.com>
44
45 * aarch64-asm-2.c: Regenerate.
46 * aarch64-dis-2.c: Regenerate.
47 * aarch64-opc-2.c: Regenerate.
48 * aarch64-tbl.h (QL_XLANES_FP_H): New.
49 (aarch64_opcode_table): Add fp16 versions of fmaxnmv, fmaxv,
50 fminnmv, fminv to the Adv.SIMD across lanes group.
51
5f7728b7
MW		 522015-12-14 Matthew Wahab <matthew.wahab@arm.com>
53
54 * aarch64-asm-2.c: Regenerate.
55 * aarch64-dis-2.c: Regenerate.
56 * aarch64-opc-2.c: Regenerate.
57 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of fmla,
58 fmls, fmul and fmulx to the scalar indexed element group.
59
42f23f62
MW		 602015-12-14 Matthew Wahab <matthew.wahab@arm.com>
61
62 * aarch64-asm-2.c: Regenerate.
63 * aarch64-dis-2.c: Regenerate.
64 * aarch64-opc-2.c: Regenerate.
65 * aarch64-tbl.h (QL_ELEMENT_FP_H): New.
66 (aarch64_opcode_table): Add fp16 versions of fmla, fmls, fmul and
67 fmulx to the vector indexed element group.
68
80776b29
MW		 692015-12-14 Matthew Wahab <matthew.wahab@arm.com>
70
71 * aarch64-asm-2.c: Regenerate.
72 * aarch64-dis-2.c: Regenerate.
73 * aarch64-opc-2.c: Regenerate.
74 * aarch64-tbl.h (QL_SISD_FCMP_H_0): new.
75 (QL_S_2SAMEH): New.
76 (aarch64_opcode_table): Add fp16 versions of fcvtns, fcvtms,
77 fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fcvtps, fcvtzs, frecpe,
78 frecpx, fcvtnu, fcvtmu, fcvtau, ucvtf, fcmge, fcmle, fcvtpu,
79 fcvtzu and frsqrte to the scalar two register misc. group.
80
f3aa142b
MW		 812015-12-14 Matthew Wahab <matthew.wahab@arm.com>
82
83 * aarch64-asm-2.c: Regenerate.
84 * aarch64-dis-2.c: Regenerate.
85 * aarch64-opc-2.c: Regenerate.
86 * aarch64-tbl.h (QL_V2SAMEH): New.
87 (aarch64_opcode_table): Add fp16 versions of frintn, frintm,
88 fcvtns, fcvtms, fcvtas, scvtf, fcmgt, fcmeq, fcmlt, fabs, frintp,
89 frintz, fcvtps, fcvtzs, frecpe, frinta, frintx, fcvtnu, fcvtmu,
90 fcvtau, ucvtf, fcmge, fcmle, fneg, frinti, fcvtpu, fcvtzu, frsqrte
91 and fsqrt to the vector register misc. group.
92
6b4680fb
MW		 932015-12-14 Matthew Wahab <matthew.wahab@arm.com>
94
95 * aarch64-asm-2.c: Regenerate.
96 * aarch64-dis-2.c: Regenerate.
97 * aarch64-opc-2.c: Regenerate.
98 * aarch64-tbl.h (aarch64_opcode_table): Add fp16 versions of
99 fmulx, fcmeq, frecps, frsqrts, fcmge, facge, fabd, fcmgt and facgt
100 to the scalar three same group.
101
51d543ed
MW		 1022015-12-14 Matthew Wahab <matthew.wahab@arm.com>
103
104 * aarch64-asm-2.c: Regenerate.
105 * aarch64-dis-2.c: Regenerate.
106 * aarch64-opc-2.c: Regenerate.
107 * aarch64-tbl.h (QL_V3SAMEH): New.
108 (aarch64_opcode_table): Add fp16 versions of fmaxnm, fmla, fadd,
109 fmulx, fcmeq, fmax, frecps, fminnm, fmls, fsub, fmin, frsqrts,
110 fmaxnmp, faddp, fmul, fcmge, facge, fmaxp, fdiv, fminnmp, fabd,
111 fcmgt, facgt and fminp to the vector three same group.
112
40d16a76
MW		 1132015-12-14 Matthew Wahab <matthew.wahab@arm.com>
114
115 * aarch64-tbl.h (aarch64_feature_simd_f16): New.
116 (SIMD_F16): New.
117
63511907
MW		 1182015-12-14 Matthew Wahab <matthew.wahab@arm.com>
119
120 * aarch64-opc.c (aarch64_sys_reg_supported_p): Add mistakenly
121 removed statement.
122 (aarch64_pstatefield_supported_p): Move feature checks for AT
123 registers ..
124 (aarch64_sys_ins_reg_supported_p): .. to here.
125
b817670b
AM		 1262015-12-12 Alan Modra <amodra@gmail.com>
127
128 PR 19359
129 * ppc-opc.c (insert_fxm): Remove "ignored" from error message.
130 (powerpc_opcodes): Remove single-operand mfcr.
131
9ed608f9
MW		 1322015-12-11 Matthew Wahab <matthew.wahab@arm.com>
133
134 * aarch64-asm.c (aarch64_ins_hint): New.
135 * aarch64-asm.h (aarch64_ins_hint): Declare.
136 * aarch64-dis.c (aarch64_ext_hint): New.
137 * aarch64-dis.h (aarch64_ext_hint): Declare.
138 * aarch64-opc-2.c: Regenerate.
139 * aarch64-opc.c (aarch64_hint_options): New.
140 * aarch64-tbl.h (AARCH64_OPERANDS): Fix typos.
141
a0f7013a
MW		 1422015-12-11 Matthew Wahab <matthew.wahab@arm.com>
143
144 * aarch64-gen.c (find_alias_opcode): Set max_num_aliases to 16.
145
55c144e6
MW		 1462015-12-11 Matthew Wahab <matthew.wahab@arm.com>
147
148 * aarch64-opc.c (aarch64_sys_reg): Add pbmlimitr_el1, pmbptr_el1,
149 pmbsr_el1, pmbidr_el1, pmscr_el1, pmsicr_el1, pmsirr_el1,
150 pmsfcr_el1, pmsevfr_el1, pmslatfr_el1, pmsidr_el1, pmscr_el2 and
151 pmscr_el2.
152 (aarch64_sys_reg_supported_p): Add architecture feature tests for
153 the new registers.
154
22a5455c
MW		 1552015-12-10 Matthew Wahab <matthew.wahab@arm.com>
156
157 * aarch64-opc.c (aarch64_sys_regs_at): Add "s1e1rp" and "s1e1wp".
158 (aarch64_sys_ins_reg_supported_p): Add ARMv8.2 system register
159 feature test for "s1e1rp" and "s1e1wp".
160
d6bf7ce6
MW		 1612015-12-10 Matthew Wahab <matthew.wahab@arm.com>
162
163 * aarch64-opc.c (aarch64_sys_regs_dc): Add "cvap".
164 (aarch64_sys_ins_reg_supported_p): New.
165
ea2deeec
MW		 1662015-12-10 Matthew Wahab <matthew.wahab@arm.com>
167
168 * aarch64-dis.c (aarch64_ext_regrt_sysins): Replace use of has_xt
169 with aarch64_sys_ins_reg_has_xt.
170 (aarch64_ext_sysins_op): Likewise.
171 * aarch64-opc.c (operand_general_constraint_met_p): Likewise.
172 (F_HASXT): New.
173 (aarch64_sys_regs_ic): Update for changes to aarch64_sys_ins_reg.
174 (aarch64_sys_regs_dc): Likewise.
175 (aarch64_sys_regs_at): Likewise.
176 (aarch64_sys_regs_tlbi): Likewise.
177 (aarch64_sys_ins_reg_has_xt): New.
178
6479e48e
MW		 1792015-12-10 Matthew Wahab <matthew.wahab@arm.com>
180
181 * aarch64-opc.c (aarch64_sys_regs): Add "uao".
182 (aarch64_sys_reg_supported_p): Add comment. Add checks for "uao".
183 (aarch64_pstatefields): Add "uao".
184 (aarch64_pstatefield_supported_p): Add checks for "uao".
185
47f81142
MW		 1862015-12-10 Matthew Wahab <matthew.wahab@arm.com>
187
188 * aarch64-opc.c (aarch64_sys_regs): Add "vsesr_el2", "erridr_el1",
189 "errselr_el1", "erxfr_el1", "erxctlr", "erxaddr_el1",
190 "erxmisc0_el1", "erxmisc1_el1", "disr_el1" and "vdisr_el2".
191 (aarch64_sys_reg_supported_p): Add architecture feature tests for
192 new registers.
193
c8a6db6f
MW		 1942015-12-10 Matthew Wahab <matthew.wahab@arm.com>
195
196 * aarch64-asm-2.c: Regenerate.
197 * aarch64-dis-2.c: Regenerate.
198 * aarch64-tbl.h (aarch64_feature_ras): New.
199 (RAS): New.
200 (aarch64_opcode_table): Add "esb".
201
8eab4136
L		 2022015-12-09 H.J. Lu <hongjiu.lu@intel.com>
203
204 * i386-dis.c (MOD_0F01_REG_5): New.
205 (RM_0F01_REG_5): Likewise.
206 (reg_table): Use MOD_0F01_REG_5.
207 (mod_table): Add MOD_0F01_REG_5.
208 (rm_table): Add RM_0F01_REG_5.
209 * i386-gen.c (cpu_flag_init): Add CPU_OSPKE_FLAGS.
210 (cpu_flags): Add CpuOSPKE.
211 * i386-opc.h (CpuOSPKE): New.
212 (i386_cpu_flags): Add cpuospke.
213 * i386-opc.tbl: Add rdpkru and wrpkru instructions.
214 * i386-init.h: Regenerated.
215 * i386-tbl.h: Likewise.
216
1eac08cc
DD		 2172015-12-07 DJ Delorie <dj@redhat.com>
218
219 * rl78-decode.opc: Enable MULU for all ISAs.
220 * rl78-decode.c: Regenerate.
221
dd2887fc
AM		 2222015-12-07 Alan Modra <amodra@gmail.com>
223
224 * opcodes/ppc-opc.c (powerpc_opcodes): Sort power9 insns by
225 major opcode/xop.
226
24b368f8
CZ		 2272015-12-04 Claudiu Zissulescu <claziss@synopsys.com>
228
229 * arc-dis.c (special_flag_p): Match full mnemonic.
230 * arc-opc.c (print_insn_arc): Check section size to read
231 appropriate number of bytes. Fix printing.
232 * arc-tbl.h: Fix instruction table. Allow clri/seti instruction without
233 arguments.
234
3395762e
AV		 2352015-12-02 Andre Vieira <andre.simoesdiasvieira@arm.com>
236
237 * arm-dis.c (arm_opcodes): <ldaexh>: Fix typo...
238 <ldah>: ... to this.
239
622b9eb1
MW		 2402015-11-27 Matthew Wahab <matthew.wahab@arm.com>
241
242 * aarch64-asm-2.c: Regenerate.
243 * aarch64-dis-2.c: Regenerate.
244 * aarch64-opc-2.c: Regenerate.
245 * aarch64-tbl.h (QL_FIX2FP_H, QL_FP2FIX_H): New.
246 (QL_INT2FP_H, QL_FP2INT_H): New.
247 (QL_FP2_H, QL_FP3_H, QL_FP4_H): New
248 (QL_DST_H): New.
249 (QL_FCCMP_H): New.
250 (aarch64_opcode_table): Add 16-bit variants of scvt, ucvtf,
251 fcvtzs, fcvtzu, fcvtns, fcvtnu, scvtf, ucvtf, fcvtas, fcvtau,
252 fmov, fcvtpos, fcvtpu, fcvtms, fcvtmu, fcvtzs, fcvtzu, fccmp,
253 fccmpe, fcmp, fcmpe, fabs, fneg, fsqrt, frintn, frintp, frintm,
254 frintz, frinta, frintx, frinti, fmul, fdiv, fadd, fsub, fmax,
255 fmin, fmaxnm, fminnm, fnmul, fmadd, fmsub, fnmadd, fnmsub and
256 fcsel.
257
cf86120b
MW		 2582015-11-27 Matthew Wahab <matthew.wahab@arm.com>
259
260 * aarch64-opc.c (half_conv_t): New.
261 (expand_fp_imm): Replace is_dp flag with the parameter size to
262 specify the number of bytes for the required expansion. Treat
263 a 16-bit expansion like a 32-bit expansion. Add check for an
264 unsupported size request. Update comment.
265 (aarch64_print_operand): Update to support 16-bit floating point
266 values. Update for changes to expand_fp_imm.
267
3bd894a7
MW		 2682015-11-27 Matthew Wahab <matthew.wahab@arm.com>
269
270 * aarch64-tbl.h (aarch64_feature_fp_f16): New.
271 (FP_F16): New.
272
64357d2e
MW		 2732015-11-27 Matthew Wahab <matthew.wahab@arm.com>
274
275 * aarch64-asm-2.c: Regenerate.
276 * aarch64-dis-2.c: Regenerate.
277 * aarch64-opc-2.c: Regenerate.
278 * aarch64-tbl.h (aarchr64_opcode_table): Update "rev", add
279 "rev64".
280
d685192a
MW		 2812015-11-27 Matthew Wahab <matthew.wahab@arm.com>
282
283 * aarch64-asm-2.c: Regenerate.
284 * aarch64-asm.c (convert_bfc_to_bfm): New.
285 (convert_to_real): Add case for OP_BFC.
286 * aarch64-dis-2.c: Regenerate.
287 * aarch64-dis.c: (convert_bfm_to_bfc): New.
288 (convert_to_alias): Add case for OP_BFC.
289 * aarch64-opc-2.c: Regenerate.
290 * aarch64-opc.c (operand_general_constraint_met_p): Weaken assert
291 to allow width operand in three-operand instructions.
292 * aarch64-tbl.h (QL_BF1): New.
293 (aarch64_feature_v8_2): New.
294 (ARMV8_2): New.
295 (aarch64_opcode_table): Add "bfc".
296
35822b38
MW		 2972015-11-27 Matthew Wahab <matthew.wahab@arm.com>
298
299 * aarch64-asm-2.c: Regenerate.
300 * aarch64-dis-2.c: Regenerate.
301 * aarch64-dis.c: Weaken assert.
302 * aarch64-gen.c: Include the instruction in the list of its
303 possible aliases.
304
1a04d1a7
MW		 3052015-11-27 Matthew Wahab <matthew.wahab@arm.com>
306
307 * aarch64-opc.c (aarch64_sys_regs): Add "id_aa64mmfr2_el1".
308 (aarch64_sys_reg_supported_p): Add ARMv8.2 system register
309 feature test.
310
e49d43ff
TG		 3112015-11-23 Tristan Gingold <gingold@adacore.com>
312
313 * arm-dis.c (print_insn): Also set is_thumb for Mach-O.
314
250aafa4
MW		 3152015-11-20 Matthew Wahab <matthew.wahab@arm.com>
316
317 * aarch64-opc.c (aarch64_sys_regs): Add spsr_el12, elr_el12,
318 sctlr_el12, cpacr_el12, ttbr1_el2, ttbr0_el12, ttbr1_el12,
319 tcr_el12, afsr0_el12, afsr1_el12, esr_el12, far_el12, mair_el12,
320 amair_el12, vbar_el12, contextidr_el2, contextidr_el12,
321 cntkctl_el12, cntp_tval_el02, cntp_ctl_el02, cntp_cval_el02,
322 cntv_tval_el02, cntv_ctl_el02, cntv_cval_el02, cnthv_tval_el2,
323 cnthv_ctl_el2, cnthv_cval_el2.
324 (aarch64_sys_reg_supported_p): Update for the new system
325 registers.
326
a915c10f
NC		 3272015-11-20 Nick Clifton <nickc@redhat.com>
328
329 PR binutils/19224
330 * h8300-dis.c (bfd_h8_disassemble): Remove redundant if clause.
331
f8c2a965
NC		 3322015-11-20 Nick Clifton <nickc@redhat.com>
333
334 * po/zh_CN.po: Updated simplified Chinese translation.
335
c2825638
MW		 3362015-11-19 Matthew Wahab <matthew.wahab@arm.com>
337
338 * aarch64-opc.c (operand_general_constraint_met_p): Check validity
339 of MSR PAN immediate operand.
340
e7286c56
NC		 3412015-11-16 Nick Clifton <nickc@redhat.com>
342
343 * rx-dis.c (condition_names): Replace always and never with
344 invalid, since the always/never conditions can never be legal.
345
d8bd95ef
TG		 3462015-11-13 Tristan Gingold <gingold@adacore.com>
347
348 * configure: Regenerate.
349
a680de9a
PB		 3502015-11-11 Alan Modra <amodra@gmail.com>
351 Peter Bergner <bergner@vnet.ibm.com>
352
353 * ppc-dis.c (ppc_opts): Add "power9" and "pwr9" entries.
354 Add PPC_OPCODE_VSX3 to the vsx entry.
355 (powerpc_init_dialect): Set default dialect to power9.
356 * ppc-opc.c (insert_dcmxs, extract_dcmxs, insert_dxd, extract_dxd,
357 insert_dxdn, extract_dxdn, insert_l0, extract_l0, insert_l1,
358 extract_l1 insert_xtq6, extract_xtq6): New static functions.
359 (insert_esync): Test for illegal L operand value.
360 (DCMX, DCMXS, DXD, NDXD, L0, L1, RC, FC, UIM6, X_R, RIC, PRS, XSQ6,
361 XTQ6, LRAND, IMM8, DQX, DQX_MASK, DX, DX_MASK, VXVAPS_MASK, VXVA,XVA,
362 XX2VA, XVARC, XBF_MASK, XX2UIM4_MASK, XX2BFD_MASK, XX2DCMXS_MASK,
363 XVA_MASK, XRLA_MASK, XBFRARB_MASK, XLRAND_MASK, POWER9, PPCVEC3,
364 PPCVSX3): New defines.
365 (powerpc_opcodes) <ps_cmpu0, ps_cmpo0, ps_cmpu1, ps_cmpo1, fcmpu,
366 fcmpo, ftdiv, ftsqrt>: Use XBF_MASK.
367 <mcrxr>: Use XBFRARB_MASK.
368 <addpcis, bcdcfn., bcdcfsq., bcdcfz., bcdcpsgn., bcdctn., bcdctsq.,
369 bcdctz., bcds., bcdsetsgn., bcdsr., bcdtrunc., bcdus., bcdutrunc.,
370 cmpeqb, cmprb, cnttzd, cnttzd., cnttzw, cnttzw., copy, copy_first,
371 cp_abort, darn, dtstsfi, dtstsfiq, extswsli, extswsli., ldat, ldmx,
372 lwat, lxsd, lxsibzx, lxsihzx, lxssp, lxv, lxvb16x, lxvh8x, lxvl, lxvll,
373 lxvwsx, lxvx, maddhd, maddhdu, maddld, mcrxrx, mfvsrld, modsd, modsw,
374 modud, moduw, msgsync, mtvsrdd, mtvsrws, paste, paste., paste_last,
375 rmieg, setb, slbieg, slbsync, stdat, stop, stwat, stxsd, stxsibx,
376 stxsihx, stxssp, stxv, stxvb16x, stxvh8x, stxvl, stxvll, stxvx,
377 subpcis, urfid, vbpermd, vclzlsbb, vcmpneb, vcmpneb., vcmpneh,
378 vcmpneh., vcmpnew, vcmpnew., vcmpnezb, vcmpnezb., vcmpnezh, vcmpnezh.,
379 vcmpnezw, vcmpnezw., vctzb, vctzd, vctzh, vctzlsbb, vctzw, vextractd,
380 vextractub, vextractuh, vextractuw, vextsb2d, vextsb2w, vextsh2d,
381 vextsh2w, vextsw2d, vextublx, vextubrx, vextuhlx, vextuhrx, vextuwlx,
382 vextuwrx, vinsertb, vinsertd, vinserth, vinsertw, vmul10cuq,
383 vmul10ecuq, vmul10euq, vmul10uq, vnegd, vnegw, vpermr, vprtybd,
384 vprtybq, vprtybw, vrldmi, vrldnm, vrlwmi, vrlwnm, vslv, vsrv, wait,
385 xsabsqp, xsaddqp, xsaddqpo, xscmpeqdp, xscmpexpdp, xscmpexpqp,
386 xscmpgedp, xscmpgtdp, xscmpnedp, xscmpoqp, xscmpuqp, xscpsgnqp,
387 xscvdphp, xscvdpqp, xscvhpdp, xscvqpdp, xscvqpdpo, xscvqpsdz,
388 xscvqpswz, xscvqpudz, xscvqpuwz, xscvsdqp, xscvudqp, xsdivqp,
389 xsdivqpo, xsiexpdp, xsiexpqp, xsmaddqp, xsmaddqpo, xsmaxcdp,
390 xsmaxjdp, xsmincdp, xsminjdp, xsmsubqp, xsmsubqpo, xsmulqp, xsmulqpo,
391 xsnabsqp, xsnegqp, xsnmaddqp, xsnmaddqpo, xsnmsubqp, xsnmsubqpo,
392 xsrqpi, xsrqpix, xsrqpxp, xssqrtqp, xssqrtqpo, xssubqp, xssubqpo,
393 xststdcdp, xststdcqp, xststdcsp, xsxexpdp, xsxexpqp, xsxsigdp,
394 xsxsigqp, xvcmpnedp, xvcmpnedp., xvcmpnesp, xvcmpnesp., xvcvhpsp,
395 xvcvsphp, xviexpdp, xviexpsp, xvtstdcdp, xvtstdcsp, xvxexpdp,
396 xvxexpsp, xvxsigdp, xvxsigsp, xxbrd, xxbrh, xxbrq, xxbrw, xxextractuw,
397 xxinsertw, xxperm, xxpermr, xxspltib>: New instructions.
398 <doze, nap, sleep, rvwinkle, waitasec, lxvx, stxvx>: Disable on POWER9.
399 <tlbiel, tlbie, sync, slbmfev, slbmfee>: Add additional operands.
400
854eb72b
NC		 4012015-11-02 Nick Clifton <nickc@redhat.com>
402
403 * rx-decode.opc (rx_decode_opcode): Decode extra NOP
404 instructions.
405 * rx-decode.c: Regenerate.
406
e292aa7a
NC		 4072015-11-02 Nick Clifton <nickc@redhat.com>
408
409 * rx-decode.opc (rx_disp): If the displacement is zero, set the
410 type to RX_Operand_Zero_Indirect.
411 * rx-decode.c: Regenerate.
412 * rx-dis (print_insn): Handle RX_Operand_Zero_Indirect.
413
43cdf5ae
YQ		 4142015-10-28 Yao Qi <yao.qi@linaro.org>
415
416 * aarch64-dis.c (aarch64_decode_insn): Add one argument
417 noaliases_p. Update comments. Pass noaliases_p rather than
418 no_aliases to aarch64_opcode_decode.
419 (print_insn_aarch64_word): Pass no_aliases to
420 aarch64_decode_insn.
421
c2f28758
VK		 4222015-10-27 Vinay <Vinay.G@kpit.com>
423
424 PR binutils/19159
425 * rl78-decode.opc (MOV): Added offset to DE register in index
426 addressing mode.
427 * rl78-decode.c: Regenerate.
428
46662804
VK		 4292015-10-27 Vinay Kumar <vinay.g@kpit.com>
430
431 PR binutils/19158
432 * rl78-decode.opc: Add 's' print operator to instructions that
433 access system registers.
434 * rl78-decode.c: Regenerate.
435 * rl78-dis.c (print_insn_rl78_common): Decode all system
436 registers.
437
02f12cd4
VK		 4382015-10-27 Vinay Kumar <vinay.g@kpit.com>
439
440 PR binutils/19157
441 * rl78-decode.opc: Add 'a' print operator to mov instructions
442 using stack pointer plus index addressing.
443 * rl78-decode.c: Regenerate.
444
485f23cf
AK		 4452015-10-14 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
446
447 * s390-opc.c: Fix comment.
448 * s390-opc.txt: Change instruction type for troo, trot, trto, and
449 trtt to RRF_U0RER since the second parameter does not need to be a
450 register pair.
451
3f94e60d
NC		 4522015-10-08 Nick Clifton <nickc@redhat.com>
453
454 * arc-dis.c (print_insn_arc): Initiallise insn array.
455
875880c6
YQ		 4562015-10-07 Yao Qi <yao.qi@linaro.org>
457
458 * aarch64-dis.c (aarch64_ext_sysins_op): Access field
459 'name' rather than 'template'.
460 * aarch64-opc.c (aarch64_print_operand): Likewise.
461
886a2506
NC		 4622015-10-07 Claudiu Zissulescu <claziss@synopsys.com>
463
464 * arc-dis.c: Revamped file for ARC support
465 * arc-dis.h: Likewise.
466 * arc-ext.c: Likewise.
467 * arc-ext.h: Likewise.
468 * arc-opc.c: Likewise.
469 * arc-fxi.h: New file.
470 * arc-regs.h: Likewise.
471 * arc-tbl.h: Likewise.
472
36f4aab1
YQ		 4732015-10-02 Yao Qi <yao.qi@linaro.org>
474
475 * aarch64-dis.c (disas_aarch64_insn): Remove static. Change
476 argument insn type to aarch64_insn. Rename to ...
477 (aarch64_decode_insn): ... it.
478 (print_insn_aarch64_word): Caller updated.
479
7232d389
YQ		 4802015-10-02 Yao Qi <yao.qi@linaro.org>
481
482 * aarch64-dis.c (disas_aarch64_insn): Remove argument PC.
483 (print_insn_aarch64_word): Caller updated.
484
7ecc513a
DV		 4852015-09-29 Dominik Vogt <vogt@linux.vnet.ibm.com>
486
487 * s390-mkopc.c (main): Parse htm and vx flag.
488 * s390-opc.txt: Mark instructions from the hardware transactional
489 memory and vector facilities with the "htm"/"vx" flag.
490
b08b78e7
NC		 4912015-09-28 Nick Clifton <nickc@redhat.com>
492
493 * po/de.po: Updated German translation.
494
36f7a941
TR		 4952015-09-28 Tom Rix <tom@bumblecow.com>
496
497 * ppc-opc.c (PPC500): Mark some opcodes as invalid
498
b6518b38
NC		 4992015-09-23 Nick Clifton <nickc@redhat.com>
500
501 * bfin-dis.c (fmtconst): Remove unnecessary call to the abs
502 function.
503 * tic30-dis.c (print_branch): Likewise.
504 * cgen-asm.c (cgen_parse_signed_integer): Cast integer to signed
505 value before left shifting.
506 * fr30-ibld.c (fr30_cgen_extract_operand): Likewise.
507 * hppa-dis.c (print_insn_hppa): Likewise.
508 * mips-dis.c (mips_cp0sel_names_mipsr5900): Delete unused static
509 array.
510 * msp430-dis.c (msp430_singleoperand): Likewise.
511 (msp430_doubleoperand): Likewise.
512 (print_insn_msp430): Likewise.
513 * nds32-asm.c (parse_operand): Likewise.
514 * sh-opc.h (MASK): Likewise.
515 * v850-dis.c (get_operand_value): Likewise.
516
f04265ec
NC		 5172015-09-22 Nick Clifton <nickc@redhat.com>
518
519 * rx-decode.opc (bwl): Use RX_Bad_Size.
520 (sbwl): Likewise.
521 (ubwl): Likewise. Rename to ubw.
522 (uBWL): Rename to uBW.
523 Replace all references to uBWL with uBW.
524 * rx-decode.c: Regenerate.
525 * rx-dis.c (size_names): Add entry for RX_Bad_Size.
526 (opsize_names): Likewise.
527 (print_insn_rx): Detect and report RX_Bad_Size.
528
6dca4fd1
AB		 5292015-09-22 Anton Blanchard <anton@samba.org>
530
531 * ppc-opc.c (powerpc_opcodes): Add mfdscr, mfctrl, mtdscr and mtctrl.
532
38074311
JM		 5332015-08-25 Jose E. Marchesi <jose.marchesi@oracle.com>
534
535 * sparc-dis.c (print_insn_sparc): Handle the privileged register
536 %pmcdper.
537
5f40e14d
JS		 5382015-08-24 Jan Stancek <jstancek@redhat.com>
539
540 * i386-dis.c (print_insn): Fix decoding of three byte operands.
541
ab4e4ed5
AF		 5422015-08-21 Alexander Fomin <alexander.fomin@intel.com>
543
544 PR binutils/18257
545 * i386-dis.c: Use MOD_TABLE for most of mask instructions.
546 (MOD enum): Add MOD_VEX_W_0_0F41_P_0_LEN_1,
547 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
548 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
549 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
550 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
551 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
552 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
553 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
554 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
555 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
556 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
557 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
558 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
559 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
560 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
561 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
562 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
563 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
564 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
565 MOD_VEX_W_0_0F92_P_3_LEN_0, MOD_VEX_W_1_0F92_P_3_LEN_0,
566 MOD_VEX_W_0_0F93_P_0_LEN_0, MOD_VEX_W_0_0F93_P_2_LEN_0,
567 MOD_VEX_W_0_0F93_P_3_LEN_0, MOD_VEX_W_1_0F93_P_3_LEN_0,
568 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
569 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
570 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
571 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
572 MOD_VEX_W_0_0F3A30_P_2_LEN_0, MOD_VEX_W_1_0F3A30_P_2_LEN_0,
573 MOD_VEX_W_0_0F3A31_P_2_LEN_0, MOD_VEX_W_1_0F3A31_P_2_LEN_0,
574 MOD_VEX_W_0_0F3A32_P_2_LEN_0, MOD_VEX_W_1_0F3A32_P_2_LEN_0,
575 MOD_VEX_W_0_0F3A33_P_2_LEN_0, MOD_VEX_W_1_0F3A33_P_2_LEN_0.
576 (vex_w_table): Replace terminals with MOD_TABLE entries for
577 most of mask instructions.
578
919b75f7
AM		 5792015-08-17 Alan Modra <amodra@gmail.com>
580
581 * cgen.sh: Trim trailing space from cgen output.
582 * ia64-gen.c (print_dependency_table): Don't generate trailing space.
583 (print_dis_table): Likewise.
584 * opc2c.c (dump_lines): Likewise.
585 (orig_filename): Warning fix.
586 * ia64-asmtab.c: Regenerate.
587
4ab90a7a
AV		 5882015-08-13 Andre Vieira <andre.simoesdiasvieira@arm.com>
589
590 * arm-dis.c (print_insn_arm): Disassembling for all targets V6
591 and higher with ARM instruction set will now mark the 26-bit
592 versions of teq,tst,cmn and cmp as UNPREDICTABLE.
593 (arm_opcodes): Fix for unpredictable nop being recognized as a
594 teq.
595
40fc1451
SD		 5962015-08-12 Simon Dardis <simon.dardis@imgtec.com>
597
598 * micromips-opc.c (micromips_opcodes): Re-order table so that move
599 based on 'or' is first.
600 * mips-opc.c (mips_builtin_opcodes): Ditto.
601
922c5db5
NC		 6022015-08-11 Nick Clifton <nickc@redhat.com>
603
604 PR 18800
605 * aarch64-tbl.h (aarch64_opcode_table): Fix mask for SIMD EXT
606 instruction.
607
75fb7498
RS		 6082015-08-10 Robert Suchanek <robert.suchanek@imgtec.com>
609
610 * mips-opc.c (mips_builtin_opcodes): Add "sigrie".
611
36aed29d
AP		 6122015-08-07 Amit Pawar <Amit.Pawar@amd.com>
613
614 * i386-gen.c: Remove CpuFMA4 from CPU_ZNVER1_FLAGS.
615 * i386-init.h: Regenerated.
616
a8484f96
L		 6172015-07-30 H.J. Lu <hongjiu.lu@intel.com>
618
619 PR binutils/13571
620 * i386-dis.c (MOD_0FC3): New.
621 (PREFIX_0FC3): Renamed to ...
622 (PREFIX_MOD_0_0FC3): This.
623 (dis386_twobyte): Replace PREFIX_0FC3 with MOD_0FC3.
624 (prefix_table): Replace Ma with Ev on movntiS.
625 (mod_table): Add MOD_0FC3.
626
37a42ee9
L		 6272015-07-27 H.J. Lu <hongjiu.lu@intel.com>
628
629 * configure: Regenerated.
630
070fe95d
AM		 6312015-07-23 Alan Modra <amodra@gmail.com>
632
633 PR 18708
634 * i386-dis.c (get64): Avoid signed integer overflow.
635
20c2a615
L		 6362015-07-22 Alexander Fomin <alexander.fomin@intel.com>
637
638 PR binutils/18631
639 * i386-dis-evex.h (EVEX_W_0F78_P_2): Replace "EXxmmq" with
640 "EXEvexHalfBcstXmmq" for the second operand.
641 (EVEX_W_0F79_P_2): Likewise.
642 (EVEX_W_0F7A_P_2): Likewise.
643 (EVEX_W_0F7B_P_2): Likewise.
644
6f1c2142
AM		 6452015-07-16 Alessandro Marzocchi <alessandro.marzocchi@gmail.com>
646
647 * arm-dis.c (print_insn_coprocessor): Added support for quarter
648 float bitfield format.
649 (coprocessor_opcodes): Changed VFP vmov reg,immediate to use new
650 quarter float bitfield format.
651
8a643cc3
L		 6522015-07-14 H.J. Lu <hongjiu.lu@intel.com>
653
654 * configure: Regenerated.
655
ef5a96d5
AM		 6562015-07-03 Alan Modra <amodra@gmail.com>
657
658 * ppc-opc.c (PPC750, PPC7450, PPC860): Define using PPC_OPCODE_*.
659 * ppc-dis.c (ppc_opts): Add 821, 850 and 860 entries. Add
660 PPC_OPCODE_7450 to 7450 entry. Add PPC_OPCODE_750 to 750cl entry.
661
c8c8175b
SL		 6622015-07-01 Sandra Loosemore <sandra@codesourcery.com>
663 Cesar Philippidis <cesar@codesourcery.com>
664
665 * nios2-dis.c (nios2_extract_opcode): New.
666 (nios2_disassembler_state): New.
667 (nios2_find_opcode_hash): Use mach parameter to select correct
668 disassembler state.
669 (nios2_print_insn_arg): Extend to support new R2 argument letters
670 and formats.
671 (print_insn_nios2): Check for 16-bit instruction at end of memory.
672 * nios2-opc.c (nios2_builtin_regs): Add R2 register attributes.
673 (NIOS2_NUM_OPCODES): Rename to...
674 (NIOS2_NUM_R1_OPCODES): This.
675 (nios2_r2_opcodes): New.
676 (NIOS2_NUM_R2_OPCODES): New.
677 (nios2_num_r2_opcodes): New.
678 (nios2_r2_asi_n_mappings, nios2_num_r2_asi_n_mappings): New.
679 (nios2_r2_shi_n_mappings, nios2_num_r2_shi_n_mappings): New.
680 (nios2_r2_andi_n_mappings, nios2_num_r2_andi_n_mappings): New.
681 (nios2_r2_reg3_mappings, nios2_num_r2_reg3_mappings): New.
682 (nios2_r2_reg_range_mappings, nios2_num_r2_reg_range_mappings): New.
683
9916071f
AP		 6842015-06-30 Amit Pawar <Amit.Pawar@amd.com>
685
686 * i386-dis.c (OP_Mwaitx): New.
687 (rm_table): Add monitorx/mwaitx.
688 * i386-gen.c (cpu_flag_init): Add CpuMWAITX to CPU_BDVER4_FLAGS
689 and CPU_ZNVER1_FLAGS. Add CPU_MWAITX_FLAGS.
690 (operand_type_init): Add CpuMWAITX.
691 * i386-opc.h (CpuMWAITX): New.
692 (i386_cpu_flags): Add cpumwaitx.
693 * i386-opc.tbl: Add monitorx and mwaitx.
694 * i386-init.h: Regenerated.
695 * i386-tbl.h: Likewise.
696
7b934113
PB		 6972015-06-22 Peter Bergner <bergner@vnet.ibm.com>
698
699 * ppc-opc.c (insert_ls): Test for invalid LS operands.
700 (insert_esync): New function.
701 (LS, WC): Use insert_ls.
702 (ESYNC): Use insert_esync.
703
bdc4de1b
NC		 7042015-06-22 Nick Clifton <nickc@redhat.com>
705
706 * dis-buf.c (buffer_read_memory): Fail is stop_vma is set and the
707 requested region lies beyond it.
708 * bfin-dis.c (print_insn_bfin): Ignore sysop instructions when
709 looking for 32-bit insns.
710 * mcore-dis.c (print_insn_mcore): Disable stop_vma when reading
711 data.
712 * sh-dis.c (print_insn_sh): Likewise.
713 * tic6x-dis.c (print_insn_tic6x): Disable stop_vma when reading
714 blocks of instructions.
715 * vax-dis.c (print_insn_vax): Check that the requested address
716 does not clash with the stop_vma.
717
11a0cf2e
PB		 7182015-06-19 Peter Bergner <bergner@vnet.ibm.com>
719
070fe95d 720 * ppc-dis.h (skip_optional_operands): Use ppc_optional_operand_value.
11a0cf2e
PB		 721 * ppc-opc.c (FXM4): Add non-zero optional value.
722 (TBR): Likewise.
723 (SXL): Likewise.
724 (insert_fxm): Handle new default operand value.
725 (extract_fxm): Likewise.
726 (insert_tbr): Likewise.
727 (extract_tbr): Likewise.
728
bdfa8b95
MW		 7292015-06-16 Matthew Wahab <matthew.wahab@arm.com>
730
731 * arch64-opc.c (aarch64_sys_regs): Add "id_mmfr4_el1".
732
24b4cf66
SN		 7332015-06-16 Szabolcs Nagy <szabolcs.nagy@arm.com>
734
735 * arm-dis.c (print_insn_coprocessor): Avoid negative shift.
736
99a2c561
PB		 7372015-06-12 Peter Bergner <bergner@vnet.ibm.com>
738
739 * ppc-opc.c: Add comment accidentally removed by old commit.
740 (MTMSRD_L): Delete.
741
40f77f82
AM		 7422015-06-04 Peter Bergner <bergner@vnet.ibm.com>
743
744 * ppc-opc.c: (powerpc_opcodes) <hwsync>: New extended mnemonic.
745
13be46a2
NC		 7462015-06-04 Nick Clifton <nickc@redhat.com>
747
748 PR 18474
749 * msp430-dis.c (msp430_nooperands): Fix check for emulated insns.
750
ddfded2f
MW		 7512015-06-02 Matthew Wahab <matthew.wahab@arm.com>
752
753 * arm-dis.c (arm_opcodes): Add "setpan".
754 (thumb_opcodes): Add "setpan".
755
1af1dd51
MW		 7562015-06-02 Matthew Wahab <matthew.wahab@arm.com>
757
758 * arm-dis.c (select_arm_features): Rework to avoid used of redefined
759 macros.
760
9e1f0fa7
MW		 7612015-06-02 Matthew Wahab <matthew.wahab@arm.com>
762
763 * aarch64-tbl.h (aarch64_feature_rdma): New.
764 (RDMA): New.
765 (aarch64_opcode_table): Add "sqrmlah" and "sqrdmlsh" instructions.
766 * aarch64-asm-2.c: Regenerate.
767 * aarch64-dis-2.c: Regenerate.
768 * aarch64-opc-2.c: Regenerate.
769
290806fd
MW		 7702015-06-02 Matthew Wahab <matthew.wahab@arm.com>
771
772 * aarch64-tbl.h (aarch64_feature_lor): New.
773 (LOR): New.
774 (aarch64_opdocde_table): Add "ldlar", "ldlarb", "ldlarh", "stllr",
775 "stllrb", "stllrh".
776 * aarch64-asm-2.c: Regenerate.
777 * aarch64-dis-2.c: Regenerate.
778 * aarch64-opc-2.c: Regenerate.
779
f21cce2c
MW		 7802015-06-01 Matthew Wahab <matthew.wahab@arm.com>
781
782 * aarch64-opc.c (F_ARCHEXT): New.
783 (aarch64_sys_regs): Add "pan".
784 (aarch64_sys_reg_supported_p): New.
785 (aarch64_pstatefields): Add "pan".
786 (aarch64_pstatefield_supported_p): New.
787
d194d186
JB		 7882015-06-01 Jan Beulich <jbeulich@suse.com>
789
790 * i386-tbl.h: Regenerate.
791
3a8547d2
JB		 7922015-06-01 Jan Beulich <jbeulich@suse.com>
793
794 * i386-dis.c (print_insn): Swap rounding mode specifier and
795 general purpose register in Intel mode.
796
015c54d5
JB		 7972015-06-01 Jan Beulich <jbeulich@suse.com>
798
799 * i386-opc.tbl: New IntelSyntax entries for vcvt{,u}si2s{d,s}.
800 * i386-tbl.h: Regenerate.
801
071f0063
L		 8022015-05-18 H.J. Lu <hongjiu.lu@intel.com>
803
804 * i386-opc.tbl: Remove Disp32 from AMD64 direct call/jmp.
805 * i386-init.h: Regenerated.
806
5db04b09
L		 8072015-05-15 H.J. Lu <hongjiu.lu@intel.com>
808
809 PR binutis/18386
810 * i386-dis.c: Add comments for '@'.
811 (x86_64_table): Use '@' on call/jmp for X86_64_E8/X86_64_E9.
812 (enum x86_64_isa): New.
813 (isa64): Likewise.
814 (print_i386_disassembler_options): Add amd64 and intel64.
815 (print_insn): Handle amd64 and intel64.
816 (putop): Handle '@'.
817 (OP_J): Don't ignore the operand size prefix for AMD64 in 64-bit.
818 * i386-gen.c (cpu_flags): Add CpuAMD64 and CpuIntel64.
819 * i386-opc.h (AMD64): New.
820 (CpuIntel64): Likewise.
821 (i386_cpu_flags): Add cpuamd64 and cpuintel64.
822 * i386-opc.tbl: Add direct call/jmp with Disp16|Disp32 for AMD64.
823 Mark direct call/jmp without Disp16|Disp32 as Intel64.
824 * i386-init.h: Regenerated.
825 * i386-tbl.h: Likewise.
826
4bc0608a
PB		 8272015-05-14 Peter Bergner <bergner@vnet.ibm.com>
828
829 * ppc-opc.c (IH) New define.
830 (powerpc_opcodes) <wait>: Do not enable for POWER7.
831 <tlbie>: Add RS operand for POWER7.
832 <slbia>: Add IH operand for POWER6.
833
70cead07
L		 8342015-05-11 H.J. Lu <hongjiu.lu@intel.com>
835
836 * opcodes/i386-opc.tbl (call): Remove Disp16|Disp32 from 64-bit
837 direct branch.
838 (jmp): Likewise.
839 * i386-tbl.h: Regenerated.
840
7b6d09fb
L		 8412015-05-11 H.J. Lu <hongjiu.lu@intel.com>
842
843 * configure.ac: Support bfd_iamcu_arch.
844 * disassemble.c (disassembler): Support bfd_iamcu_arch.
845 * i386-gen.c (cpu_flag_init): Add CPU_IAMCU_FLAGS and
846 CPU_IAMCU_COMPAT_FLAGS.
847 (cpu_flags): Add CpuIAMCU.
848 * i386-opc.h (CpuIAMCU): New.
849 (i386_cpu_flags): Add cpuiamcu.
850 * configure: Regenerated.
851 * i386-init.h: Likewise.
852 * i386-tbl.h: Likewise.
853
31955f99
L		 8542015-05-08 H.J. Lu <hongjiu.lu@intel.com>
855
856 PR binutis/18386
857 * i386-dis.c (X86_64_E8): New.
858 (X86_64_E9): Likewise.
859 Update comments on 'T', 'U', 'V'. Add comments for '^'.
860 (dis386): Replace callT/jmpT with X86_64_E8/X86_64_E9.
861 (x86_64_table): Add X86_64_E8 and X86_64_E9.
862 (mod_table): Replace {T|} with ^ on Jcall/Jmp.
863 (putop): Handle '^'.
864 (OP_J): Ignore the operand size prefix in 64-bit. Don't check
865 REX_W.
866
0952813b
DD		 8672015-04-30 DJ Delorie <dj@redhat.com>
868
869 * disassemble.c (disassembler): Choose suitable disassembler based
870 on E_ABI.
871 * rl78-decode.opc (rl78_decode_opcode): Take ISA parameter. Use
872 it to decode mul/div insns.
873 * rl78-decode.c: Regenerate.
874 * rl78-dis.c (print_insn_rl78): Rename to...
875 (print_insn_rl78_common): ...this, take ISA parameter.
876 (print_insn_rl78): New.
877 (print_insn_rl78_g10): New.
878 (print_insn_rl78_g13): New.
879 (print_insn_rl78_g14): New.
880 (rl78_get_disassembler): New.
881
f9d3ecaa
NC		 8822015-04-29 Nick Clifton <nickc@redhat.com>
883
884 * po/fr.po: Updated French translation.
885
4fff86c5
PB		 8862015-04-27 Peter Bergner <bergner@vnet.ibm.com>
887
888 * ppc-opc.c (DCBT_EO): New define.
889 (powerpc_opcodes) <lbarx>: Enable for POWER8 and later.
890 <lharx>: Likewise.
891 <stbcx.>: Likewise.
892 <sthcx.>: Likewise.
893 <waitrsv>: Do not enable for POWER7 and later.
894 <waitimpl>: Likewise.
895 <dcbt>: Default to the two operand form of the instruction for all
896 "old" cpus. For "new" cpus, use the operand ordering that matches
897 whether the cpu is server or embedded.
898 <dcbtst>: Likewise.
899
3b78cfe1
AK		 9002015-04-27 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
901
902 * s390-opc.c: New instruction type VV0UU2.
903 * s390-opc.txt: Fix instruction types for VFCE, VLDE, VFSQ, WFK,
904 and WFC.
905
04d824a4
JB		 9062015-04-23 Jan Beulich <jbeulich@suse.com>
907
908 * i386-dis.c (putop): Extend "XY" handling to AVX512. Handle "XZ".
909 * i386-dis-evex.h.c (vcvtpd2ps, vcvtqq2ps, vcvttpd2udq,
910 vcvtpd2udq, vcvtuqq2ps, vcvttpd2dq, vcvtpd2dq): Add %XY.
911 (vfpclasspd, vfpclassps): Add %XZ.
912
09708981
L		 9132015-04-15 H.J. Lu <hongjiu.lu@intel.com>
914
915 * i386-dis.c (PREFIX_UD_SHIFT): Removed.
916 (PREFIX_UD_REPZ): Likewise.
917 (PREFIX_UD_REPNZ): Likewise.
918 (PREFIX_UD_DATA): Likewise.
919 (PREFIX_UD_ADDR): Likewise.
920 (PREFIX_UD_LOCK): Likewise.
921
3888916d
L		 9222015-04-15 H.J. Lu <hongjiu.lu@intel.com>
923
924 * i386-dis.c (prefix_requirement): Removed.
925 (print_insn): Don't set prefix_requirement. Check
926 dp->prefix_requirement instead of prefix_requirement.
927
f24bcbaa
L		 9282015-04-15 H.J. Lu <hongjiu.lu@intel.com>
929
930 PR binutils/17898
931 * i386-dis.c (PREFIX_0FC7_REG_6): Renamed to ...
932 (PREFIX_MOD_0_0FC7_REG_6): This.
933 (PREFIX_MOD_3_0FC7_REG_6): New.
934 (PREFIX_MOD_3_0FC7_REG_7): Likewise.
935 (prefix_table): Replace PREFIX_0FC7_REG_6 with
936 PREFIX_MOD_0_0FC7_REG_6. Add PREFIX_MOD_3_0FC7_REG_6 and
937 PREFIX_MOD_3_0FC7_REG_7.
938 (mod_table): Replace PREFIX_0FC7_REG_6 with
939 PREFIX_MOD_0_0FC7_REG_6. Use PREFIX_MOD_3_0FC7_REG_6 and
940 PREFIX_MOD_3_0FC7_REG_7.
941
507bd325
L		 9422015-04-15 H.J. Lu <hongjiu.lu@intel.com>
943
944 * i386-dis.c (PREFIX_MANDATORY_REPZ): Removed.
945 (PREFIX_MANDATORY_REPNZ): Likewise.
946 (PREFIX_MANDATORY_DATA): Likewise.
947 (PREFIX_MANDATORY_ADDR): Likewise.
948 (PREFIX_MANDATORY_LOCK): Likewise.
949 (PREFIX_MANDATORY): Likewise.
950 (PREFIX_UD_SHIFT): Set to 8
951 (PREFIX_UD_REPZ): Updated.
952 (PREFIX_UD_REPNZ): Likewise.
953 (PREFIX_UD_DATA): Likewise.
954 (PREFIX_UD_ADDR): Likewise.
955 (PREFIX_UD_LOCK): Likewise.
956 (PREFIX_IGNORED_SHIFT): New.
957 (PREFIX_IGNORED_REPZ): Likewise.
958 (PREFIX_IGNORED_REPNZ): Likewise.
959 (PREFIX_IGNORED_DATA): Likewise.
960 (PREFIX_IGNORED_ADDR): Likewise.
961 (PREFIX_IGNORED_LOCK): Likewise.
962 (PREFIX_OPCODE): Likewise.
963 (PREFIX_IGNORED): Likewise.
964 (Bad_Opcode): Replace PREFIX_MANDATORY with 0.
965 (dis386_twobyte): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
966 (three_byte_table): Likewise.
967 (mod_table): Likewise.
968 (mandatory_prefix): Renamed to ...
969 (prefix_requirement): This.
970 (prefix_table): Replace PREFIX_MANDATORY with PREFIX_OPCODE.
971 Update PREFIX_90 entry.
972 (get_valid_dis386): Check prefix_requirement to see if a prefix
973 should be ignored.
974 (print_insn): Replace mandatory_prefix with prefix_requirement.
975
f0fba320
RL		 9762015-04-15 Renlin Li <renlin.li@arm.com>
977
978 * arm-dis.c (thumb32_opcodes): Define 'D' format control code,
979 use it for ssat and ssat16.
980 (print_insn_thumb32): Add handle case for 'D' control code.
981
bf890a93
IT		 9822015-04-06 Ilya Tocar <ilya.tocar@intel.com>
983 H.J. Lu <hongjiu.lu@intel.com>
984
985 * i386-dis-evex.h (evex_table): Fill prefix_requirement field.
986 * i386-dis.c (PREFIX_MANDATORY_REPZ, PREFIX_MANDATORY_REPNZ,
987 PREFIX_MANDATORY_DATA, PREFIX_MANDATORY_ADDR, PREFIX_MANDATORY_LOCK,
988 PREFIX_UD_SHIFT, PREFIX_UD_REPZ, REFIX_UD_REPNZ, PREFIX_UD_DATA,
989 PREFIX_UD_ADDR, PREFIX_UD_LOCK, PREFIX_MANDATORY): Define.
990 (Bad_Opcode, FLOAT, DIS386, DIS386_PREFIX, THREE_BYTE_TABLE_PREFIX):
991 Fill prefix_requirement field.
992 (struct dis386): Add prefix_requirement field.
993 (dis386): Fill prefix_requirement field.
994 (dis386_twobyte): Ditto.
995 (twobyte_has_mandatory_prefix_: Remove.
996 (reg_table): Fill prefix_requirement field.
997 (prefix_table): Ditto.
998 (x86_64_table): Ditto.
999 (three_byte_table): Ditto.
1000 (xop_table): Ditto.
1001 (vex_table): Ditto.
1002 (vex_len_table): Ditto.
1003 (vex_w_table): Ditto.
1004 (mod_table): Ditto.
1005 (bad_opcode): Ditto.
1006 (print_insn): Use prefix_requirement.
1007 (FGRPd9_2, FGRPd9_4, FGRPd9_5, FGRPd9_6, FGRPd9_7, FGRPda_5, FGRPdb_4,
1008 FGRPde_3, FGRPdf_4): Fill prefix_requirement field.
1009 (float_reg): Ditto.
1010
2f783c1f
MF		 10112015-03-30 Mike Frysinger <vapier@gentoo.org>
1012
1013 * d10v-opc.c (d10v_reg_name_cnt): Convert old style prototype.
1014
b9d94d62
L		 10152015-03-29 H.J. Lu <hongjiu.lu@intel.com>
1016
1017 * Makefile.in: Regenerated.
1018
27c49e9a
AB		 10192015-03-25 Anton Blanchard <anton@samba.org>
1020
1021 * ppc-dis.c (disassemble_init_powerpc): Only initialise
1022 powerpc_opcd_indices and vle_opcd_indices once.
1023
c4e676f1
AB		 10242015-03-25 Anton Blanchard <anton@samba.org>
1025
1026 * ppc-opc.c (powerpc_opcodes): Add slbfee.
1027
823d2571
TG		 10282015-03-24 Terry Guo <terry.guo@arm.com>
1029
1030 * arm-dis.c (opcode32): Updated to use new arm feature struct.
1031 (opcode16): Likewise.
1032 (coprocessor_opcodes): Replace bit with feature struct.
1033 (neon_opcodes): Likewise.
1034 (arm_opcodes): Likewise.
1035 (thumb_opcodes): Likewise.
1036 (thumb32_opcodes): Likewise.
1037 (print_insn_coprocessor): Likewise.
1038 (print_insn_arm): Likewise.
1039 (select_arm_features): Follow new feature struct.
1040
029f3522
GG		 10412015-03-17 Ganesh Gopalasubramanian <Ganesh.Gopalasubramanian@amd.com>
1042
1043 * i386-dis.c (rm_table): Add clzero.
1044 * i386-gen.c (cpu_flag_init): Add new CPU_ZNVER1_FLAGS.
1045 Add CPU_CLZERO_FLAGS.
1046 (cpu_flags): Add CpuCLZERO.
1047 * i386-opc.h: Add CpuCLZERO.
1048 * i386-opc.tbl: Add clzero.
1049 * i386-init.h: Re-generated.
1050 * i386-tbl.h: Re-generated.
1051
6914869a
AB		 10522015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1053
1054 * mips-opc.c (decode_mips_operand): Fix constraint issues
1055 with u and y operands.
1056
21e20815
AB		 10572015-03-13 Andrew Bennett <andrew.bennett@imgtec.com>
1058
1059 * mips-opc.c (mips_builtin_opcodes): Add evp and dvp instructions.
1060
6b1d7593
AK		 10612015-03-10 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1062
1063 * s390-opc.c: Add new IBM z13 instructions.
1064 * s390-opc.txt: Likewise.
1065
c8f89a34
JW		 10662015-03-10 Renlin Li <renlin.li@arm.com>
1067
1068 * aarch64-tbl.h (aarch64_opcode_table): Remove strub, ldurb, ldursb,
1069 stur, ldur, sturh, ldurh, ldursh, ldursw, prfum F_HAS_ALIAS flag and
1070 related alias.
1071 * aarch64-asm-2.c: Regenerate.
1072 * aarch64-dis-2.c: Likewise.
1073 * aarch64-opc-2.c: Likewise.
1074
d8282f0e
JW		 10752015-03-03 Jiong Wang <jiong.wang@arm.com>
1076
1077 * arm-dis.c (arm_symbol_is_valid): Skip ARM private symbols.
1078
ac994365
OE		 10792015-02-25 Oleg Endo <olegendo@gcc.gnu.org>
1080
1081 * sh-opc.h (clrs, sets): Mark as arch_sh3_nommu_up instead of
1082 arch_sh_up.
1083 (pref): Mark as arch_sh2a_nofpu_or_sh3_nommu_up instead of
1084 arch_sh2a_nofpu_or_sh4_nommu_nofpu_up.
1085
fd63f640
V		 10862015-02-23 Vinay <Vinay.G@kpit.com>
1087
1088 * rl78-decode.opc (MOV): Added space between two operands for
1089 'mov' instruction in index addressing mode.
1090 * rl78-decode.c: Regenerate.
1091
f63c1776
PA		 10922015-02-19 Pedro Alves <palves@redhat.com>
1093
1094 * microblaze-dis.h [__cplusplus]: Wrap in extern "C".
1095
07774fcc
PA		 10962015-02-10 Pedro Alves <palves@redhat.com>
1097 Tom Tromey <tromey@redhat.com>
1098
1099 * microblaze-opcm.h (or, and, xor): Rename to microblaze_or,
1100 microblaze_and, microblaze_xor.
1101 * microblaze-opc.h (opcodes): Adjust.
1102
3f8107ab
AM		 11032015-01-28 James Bowman <james.bowman@ftdichip.com>
1104
1105 * Makefile.am: Add FT32 files.
1106 * configure.ac: Handle FT32.
1107 * disassemble.c (disassembler): Call print_insn_ft32.
1108 * ft32-dis.c: New file.
1109 * ft32-opc.c: New file.
1110 * Makefile.in: Regenerate.
1111 * configure: Regenerate.
1112 * po/POTFILES.in: Regenerate.
1113
e5fe4957
KLC		 11142015-01-28 Kuan-Lin Chen <kuanlinchentw@gmail.com>
1115
1116 * nds32-asm.c (keyword_sr): Add new system registers.
1117
1e2e8c52
AK		 11182015-01-16 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1119
1120 * s390-dis.c (s390_extract_operand): Support vector register
1121 operands.
1122 (s390_print_insn_with_opcode): Support new operands types and add
1123 new handling of optional operands.
1124 * s390-mkopc.c (s390_opcode_mode_val, s390_opcode_cpu_val): Remove
1125 and include opcode/s390.h instead.
1126 (struct op_struct): New field `flags'.
1127 (insertOpcode, insertExpandedMnemonic): New parameter `flags'.
1128 (dumpTable): Dump flags.
1129 (main): Parse flags from the s390-opc.txt file. Add z13 as cpu
1130 string.
1131 * s390-opc.c: Add new operands types, instruction formats, and
1132 instruction masks.
1133 (s390_opformats): Add new formats for .insn.
1134 * s390-opc.txt: Add new instructions.
1135
b90efa5b 11362015-01-01 Alan Modra <amodra@gmail.com>
bffb6004 1137
b90efa5b 1138 Update year range in copyright notice of all files.
bffb6004 1139
b90efa5b 1140For older changes see ChangeLog-2014
252b5132 1141\f
b90efa5b 1142Copyright (C) 2015 Free Software Foundation, Inc.
752937aa
NC		 1143
1144Copying and distribution of this file, with or without modification,
1145are permitted in any medium without royalty provided the copyright
1146notice and this notice are preserved.
1147
252b5132 1148Local Variables:
2f6d2f85
NC		 1149mode: change-log
1150left-margin: 8
1151fill-column: 74
252b5132
RH		 1152version-control: never
1153End:
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