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* gas/config/tc-arm.c (arm_ext_v6z): Remove.
[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
CommitLineData
f4c65163
MGD		 12010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
2
3 * arm-dis.c (arm_opcodes): SMC implies Security Extensions.
4 (thumb32_opcodes): Likewise.
5
60e5ef9f
MGD		 62010-09-23 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
7
8 * arm-dis.c (arm_opcodes): Add support for pldw.
9 (thumb32_opcodes): Likewise.
10
7a360e83
MF		 112010-09-22 Robin Getz <robin.getz@analog.com>
12
13 * bfin-dis.c (fmtconst): Cast address to 32bits.
14
35fc57f3
MF		 152010-09-22 Mike Frysinger <vapier@gentoo.org>
16
17 * bfin-dis.c (decode_REGMV_0): Rewrite valid combo checks.
18
219b747a
MF		 192010-09-22 Robin Getz <robin.getz@analog.com>
20
21 * bfin-dis.c (decode_ProgCtrl_0): Check for parallel insns.
22 Reject P6/P7 to TESTSET.
23 (decode_PushPopReg_0): Check for parallel insns. Reject pushing
24 SP onto the stack.
25 (decode_PushPopMultiple_0): Check for parallel insns. Make sure
26 P/D fields match all the time.
27 (decode_CCflag_0): Check for parallel insns. Verify x/y fields
28 are 0 for accumulator compares.
29 (decode_CC2stat_0): Check for parallel insns. Reject CC<op>CC.
30 (decode_CaCTRL_0, decode_ccMV_0, decode_CC2dreg_0, decode_BRCC_0,
31 decode_UJUMP_0, decode_LOGI2op_0, decode_COMPI2opD_0,
32 decode_COMPI2opP_0, decode_LoopSetup_0, decode_LDIMMhalf_0,
33 decode_CALLa_0, decode_linkage_0, decode_pseudoDEBUG_0,
34 decode_pseudoOChar_0, decode_pseudodbg_assert_0): Check for parallel
35 insns.
36 (decode_dagMODim_0): Verify br field for IREG ops.
37 (decode_LDST_0): Reject preg load into same preg.
38 (_print_insn_bfin): Handle returns for ILLEGAL decodes.
39 (print_insn_bfin): Likewise.
40
775f1cf0
MF		 412010-09-22 Mike Frysinger <vapier@gentoo.org>
42
43 * bfin-dis.c (decode_PushPopMultiple_0): Return 0 when pr > 5.
44
0b7691fd
MF		 452010-09-22 Robin Getz <robin.getz@analog.com>
46
47 * bfin-dis.c (decode_dsp32shiftimm_0): Add missing "S" flag.
48
b2459327
MF		 492010-09-22 Mike Frysinger <vapier@gentoo.org>
50
51 * bfin-dis.c (decode_CC2stat_0): Decode all ASTAT bits.
52
50e2162a
MF		 532010-09-22 Robin Getz <robin.getz@analog.com>
54
55 * bfin-dis.c (IS_DREG, IS_PREG, IS_GENREG, IS_DAGREG): Reject
56 register values greater than 8.
57 (IS_RESERVEDREG, allreg, mostreg): New helpers.
58 (decode_ProgCtrl_0): Call IS_DREG/IS_PREG as appropriate.
59 (decode_PushPopReg_0): Call mostreg/allreg as appropriate.
60 (decode_CC2dreg_0): Check valid CC register number.
61
a01eda85
MF		 622010-09-22 Robin Getz <robin.getz@analog.com>
63
64 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after DBG.
65
22215ae0
MF		 662010-09-22 Robin Getz <robin.getz@analog.com>
67
68 * bfin-dis.c (machine_registers): Add AC0_COPY, V_COPY, and RND_MOD.
69 (reg_names): Likewise.
70 (decode_statbits): Likewise; while reformatting to make manageable.
71
73a63ccf
MF		 722010-09-22 Mike Frysinger <vapier@gentoo.org>
73
74 * bfin-dis.c (decode_pseudoDEBUG_0): Add space after OUTC.
75 (decode_pseudoOChar_0): New function.
76 (_print_insn_bfin): Remove #if 0 and call new decode_pseudoOChar_0.
77
59a82d23
MF		 782010-09-22 Robin Getz <robin.getz@analog.com>
79
80 * bfin-dis.c (decode_dsp32shift_0): Decode sub opcodes 2/2 as
81 LSHIFT instead of SHIFT.
82
528c6277
MF		 832010-09-22 Mike Frysinger <vapier@gentoo.org>
84
85 * bfin-dis.c (constant_formats): Constify the whole structure.
86 (fmtconst): Add const to return value.
87 (reg_names): Mark const.
88 (decode_multfunc): Mark s0/s1 as const.
89 (decode_macfunc): Mark a/sop as const.
90
db472d6f
MGD		 912010-09-17 Tejas Belagod <tejas.belagod@arm.com>
92
93 * arm_dis.c (coprocessor_opcodes): Add MRC entry for APSR_nzcv.
94
f6690563
MR		 952010-09-14 Maciej W. Rozycki <macro@codesourcery.com>
96
97 * mips-opc.c (mips_builtin_opcodes): Add "sync_acquire",
98 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb".
99
8901a3cd
PM		 1002010-09-10 Pierre Muller <muller@ics.u-strasbg.fr>
101
102 * src/opcodes/dlx-dis.c (print_insn_dlx): Use dlx_insn type for
103 dlx_insn_type array.
104
d9e3625e
L		 1052010-08-31 H.J. Lu <hongjiu.lu@intel.com>
106
107 PR binutils/11960
108 * i386-dis.c (sIv): New.
109 (dis386): Replace Iq with sIv on "pushT".
110 (reg_table): Replace T with {T|} on callT, JcallT, jmpT and JjmpT.
111 (x86_64_table): Replace {T|}/{P|} with P.
112 (putop): Add 'w' to 'T'/'P' if needed for Intel syntax.
113 (OP_sI): Update v_mode. Remove w_mode.
114
f383de66
NF		 1152010-08-27 Nathan Froyd <froydnj@codesourcery.com>
116
117 * ppc-opc.c (powerpc_opcodes) [lswx,lswi,stswx,stswi]: Deprecate
118 on E500 and E500MC.
119
1ab03f4b
L		 1202010-08-17 H.J. Lu <hongjiu.lu@intel.com>
121
122 * i386-dis.c (reg_table): Replace Eb with Mb on prefetch and
123 prefetchw.
124
22109423
L		 1252010-08-06 Quentin Neill <quentin.neill@amd.com>
126
127 * i386-gen.c (cpu_flag_init): Define CpuNop extension flag, add
128 to processor flags for PENTIUMPRO processors and later.
129 * i386-opc.h (enum): Add CpuNop.
130 (i386_cpu_flags): Add cpunop bit.
131 * i386-opc.tbl: Change nop cpu_flags.
132 * i386-init.h: Regenerated.
133 * i386-tbl.h: Likewise.
134
b49dfb4a
L		 1352010-08-06 Quentin Neill <quentin.neill@amd.com>
136
137 * i386-opc.h (enum): Fix typos in comments.
138
6ca4eb77
AM		 1392010-08-06 Alan Modra <amodra@gmail.com>
140
141 * disassemble.c: Formatting.
142 (disassemble_init_for_target <ARCH_m32c>): Comment on endian.
143
92d4d42e
L		 1442010-08-05 H.J. Lu <hongjiu.lu@intel.com>
145
146 * i386-opc.tbl: Add Cpu186 to ud1/ud2/ud2a/ud2b.
147 * i386-tbl.h: Regenerated.
148
b414985b
L		 1492010-08-05 H.J. Lu <hongjiu.lu@intel.com>
150
151 * i386-dis.c (dis386_twobyte): Replace ud2a/ud2b with ud2/ud1.
152
153 * i386-opc.tbl: Add ud1. Remove Cpu686 from ud2/ud2a/ud2b.
154 * i386-tbl.h: Regenerated.
155
f9c7014e
DD		 1562010-07-29 DJ Delorie <dj@redhat.com>
157
158 * rx-decode.opc (SRR): New.
159 (rx_decode_opcode): Use it for movbi and movbir. Decode NOP2 (mov
160 r0,r0) and NOP3 (max r0,r0) special cases.
161 * rx-decode.c: Regenerate.
6ca4eb77 162
592a252b
L		 1632010-07-28 H.J. Lu <hongjiu.lu@intel.com>
164
165 * i386-dis.c: Add 0F to VEX opcode enums.
166
3cf79a01
DD		 1672010-07-27 DJ Delorie <dj@redhat.com>
168
169 * rx-decode.opc (store_flags): Remove, replace with F_* macros.
170 (rx_decode_opcode): Likewise.
171 * rx-decode.c: Regenerate.
172
1cd986c5
NC		 1732010-07-23 Naveen.H.S <naveen.S@kpitcummins.com>
174 Ina Pandit <ina.pandit@kpitcummins.com>
175
176 * v850-dis.c (v850_sreg_names): Updated structure for system
177 registers.
178 (float_cc_names): new structure for condition codes.
179 (print_value): Update the function that prints value.
180 (get_operand_value): New function to get the operand value.
181 (disassemble): Updated to handle the disassembly of instructions.
182 (print_insn_v850): Updated function to print instruction for different
183 families.
184 * opcodes/v850-opc.c (v850_msg_is_out_of_range, insert_i5div1,
185 extract_i5div1, insert_i5div2, extract_i5div2, insert_i5div3,
186 extract_i5div3, insert_d5_4, extract_d5_4, extract_d8_6,
187 insert_d8_7, extract_d8_7, insert_v8, extract_v8, insert_u16_loop,
188 extract_u16_loop, insert_d16_15, extract_d16_15, insert_d16_16,
189 extract_d16_16, nsert_d17_16, extract_d17_16, insert_d22,
190 extract_d22, insert_d23, extract_d23, insert_i9, extract_i9,
191 insert_u9, extract_u9, extract_spe, insert_r4, extract_r4): New.
192 (insert_d8_7, insert_d5_4, insert_i5div): Remove.
193 (v850_operands): Update with the relocation name. Also update
194 the instructions with specific set of processors.
195
52e7f43d
RE		 1962010-07-08 Tejas Belagod <tejas.belagod@arm.com>
197
198 * arm-dis.c (print_insn_arm): Add cases for printing more
199 symbolic operands.
200 (print_insn_thumb32): Likewise.
201
c680e7f6
MR		 2022010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
203
204 * mips-dis.c (print_insn_mips): Correct branch instruction type
205 determination.
206
9a2c7088
MR		 2072010-07-06 Maciej W. Rozycki <macro@codesourcery.com>
208
209 * mips-dis.c (print_mips16_insn_arg): Remove branch instruction
210 type and delay slot determination.
211 (print_insn_mips16): Extend branch instruction type and delay
212 slot determination to cover all instructions.
213 * mips16-opc.c (BR): Remove macro.
214 (UBR, CBR): New macros.
215 (mips16_opcodes): Update branch annotation for "b", "beqz",
216 "bnez", "bteqz" and "btnez". Add branch annotation for "jalrc"
217 and "jrc".
218
d7d9a9f8
L		 2192010-07-05 H.J. Lu <hongjiu.lu@intel.com>
220
221 AVX Programming Reference (June, 2010)
222 * i386-dis.c (mod_table): Replace rdrnd with rdrand.
223 * i386-opc.tbl: Likewise.
224 * i386-tbl.h: Regenerated.
225
77321f53
L		 2262010-07-05 H.J. Lu <hongjiu.lu@intel.com>
227
228 * i386-opc.h (CpuFSGSBase): Fix a typo in comments.
229
7102e95e
AS		 2302010-07-03 Andreas Schwab <schwab@linux-m68k.org>
231
232 * ppc-dis.c (powerpc_init_dialect): Cast PPC_OPCODE_xxx to
233 ppc_cpu_t before inverting.
3a5530ea
AS		 234 (ppc_parse_cpu): Likewise.
235 (print_insn_powerpc): Likewise.
7102e95e 236
bdc70b4a
AM		 2372010-07-03 Alan Modra <amodra@gmail.com>
238
239 * ppc-dis.c (ppc_opts, powerpc_init_dialect): Remove old opcode flags.
240 * ppc-opc.c (PPC32, POWER32, COM32, CLASSIC): Delete.
241 (PPC64, MFDEC2): Update.
242 (NON32, NO371): Define.
243 (powerpc_opcode): Update to not use old opcode flags, and avoid
244 -m601 duplicates.
245
21375995
DD		 2462010-07-03 DJ Delorie <dj@delorie.com>
247
248 * m32c-ibld.c: Regenerate.
249
81a0b7e2
AM		 2502010-07-03 Alan Modra <amodra@gmail.com>
251
252 * ppc-opc.c (PWR2COM): Define.
253 (PPCPWR2): Add PPC_OPCODE_COMMON.
254 (powerpc_opcodes): Add "subc", "subco", "subco.", "fcir", "fcir.",
255 "fcirz", "fcirz." to -mcom opcodes. Remove "mfsri", "dclst",
256 "rac" from -mcom.
257
c7b8aa3a
L		 2582010-07-01 H.J. Lu <hongjiu.lu@intel.com>
259
260 AVX Programming Reference (June, 2010)
261 * i386-dis.c (PREFIX_0FAE_REG_0): New.
262 (PREFIX_0FAE_REG_1): Likewise.
263 (PREFIX_0FAE_REG_2): Likewise.
264 (PREFIX_0FAE_REG_3): Likewise.
265 (PREFIX_VEX_3813): Likewise.
266 (PREFIX_VEX_3A1D): Likewise.
267 (prefix_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
268 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3, PREFIX_VEX_3813 and
269 PREFIX_VEX_3A1D.
270 (vex_table): Add PREFIX_VEX_3813 and PREFIX_VEX_3A1D.
271 (mod_table): Add PREFIX_0FAE_REG_0, PREFIX_0FAE_REG_1,
272 PREFIX_0FAE_REG_2, PREFIX_0FAE_REG_3 xsaveopt and rdrnd.
273
274 * i386-gen.c (cpu_flag_init): Add CPU_XSAVEOPT_FLAGS,
275 CPU_FSGSBASE_FLAGS, CPU_RDRND_FLAGS and CPU_F16C_FLAGS.
276 (cpu_flags): Add CpuXsaveopt, CpuFSGSBase, CpuRdRnd and CpuF16C.
277
278 * i386-opc.h (CpuXsaveopt): New.
77321f53 279 (CpuFSGSBase): Likewise.
c7b8aa3a
L		 280 (CpuRdRnd): Likewise.
281 (CpuF16C): Likewise.
282 (i386_cpu_flags): Add cpuxsaveopt, cpufsgsbase, cpurdrnd and
283 cpuf16c.
284
285 * i386-opc.tbl: Add xsaveopt, rdfsbase, rdgsbase, rdrnd,
286 wrfsbase, wrgsbase, vcvtph2ps and vcvtps2ph.
a00eb5e8
L		 287 * i386-init.h: Regenerated.
288 * i386-tbl.h: Likewise.
c7b8aa3a 289
09a8ad8d
AM		 2902010-07-01 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
291
292 * ppc-opc.c (powerpc_opcodes): Revert deprecation of mfocrf, mtcrf
293 and mtocrf on EFS.
294
360cfc9c
AM		 2952010-06-29 Alan Modra <amodra@gmail.com>
296
297 * maxq-dis.c: Delete file.
298 * Makefile.am: Remove references to maxq.
299 * configure.in: Likewise.
300 * disassemble.c: Likewise.
301 * Makefile.in: Regenerate.
302 * configure: Regenerate.
303 * po/POTFILES.in: Regenerate.
304
dc898d5e
AM		 3052010-06-29 Alan Modra <amodra@gmail.com>
306
307 * mep-dis.c: Regenerate.
308
8e560766
MGD		 3092010-06-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
310
311 * arm-disc.c (parse_insn_neon): Fix Neon alignment syntax.
312
c7e2358a
AM		 3132010-06-27 Alan Modra <amodra@gmail.com>
314
315 * arc-dis.c (arc_sprintf): Delete set but unused variables.
316 (decodeInstr): Likewise.
317 * dlx-dis.c (print_insn_dlx): Likewise.
318 * h8300-dis.c (bfd_h8_disassemble_init): Likewise.
319 * maxq-dis.c (check_move, print_insn): Likewise.
320 * mep-dis.c (mep_examine_ivc2_insns): Likewise.
321 * msp430-dis.c (msp430_branchinstr): Likewise.
322 * bfin-dis.c (_print_insn_bfin): Avoid set but unused warning.
323 * cgen-asm.in (parse_insn_normal, _cgen_assemble_insn): Likewise.
324 * sparc-dis.c (print_insn_sparc): Likewise.
325 * fr30-asm.c: Regenerate.
326 * frv-asm.c: Regenerate.
327 * ip2k-asm.c: Regenerate.
328 * iq2000-asm.c: Regenerate.
329 * lm32-asm.c: Regenerate.
330 * m32c-asm.c: Regenerate.
331 * m32r-asm.c: Regenerate.
332 * mep-asm.c: Regenerate.
333 * mt-asm.c: Regenerate.
334 * openrisc-asm.c: Regenerate.
335 * xc16x-asm.c: Regenerate.
336 * xstormy16-asm.c: Regenerate.
337
6ffe3d99
NC		 3382010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
339
340 PR gas/11673
341 * m68k-opc.c (m68k_opcodes): Remove move.l for isab and later.
342
09ec0d17
NC		 3432010-06-16 Vincent Rivière <vincent.riviere@freesbee.fr>
344
345 PR binutils/11676
346 * m68k-dis.c (print_insn_arg): Prefix float constants with #0e.
347
e01d869a
AM		 3482010-06-14 Sebastian Andrzej Siewior <bigeasy@linutronix.de>
349
350 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_E500MC from e500 and
351 e500x2. Add PPC_OPCODE_E500 to e500 and e500x2
352 * ppc-opc.c (powerpc_opcodes): Deprecate all opcodes on EFS which
353 touch floating point regs and are enabled by COM, PPC or PPCCOM.
354 Treat sync as msync on e500. Treat eieio as mbar 1 on e500.
355 Treat lwsync as msync on e500.
356
1f4e4950
MGD		 3572010-06-07 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
358
359 * arm-dis.c (thumb-opcodes): Add disassembly for movs.
360
9d82ec38
MGD		 3612010-05-28 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
362
e01d869a 363 * arm-dis.c (print_insn_neon): Ensure disassembly of Neon
9d82ec38
MGD		 364 constants is the same on 32-bit and 64-bit hosts.
365
c3a6ea62 3662010-05-27 Jason Duerstock <jason.duerstock+binutils@gmail.com>
d8b24b95
NC		 367
368 * m68k-dis.c (print_insn_m68k): Emit undefined instructions as
369 .short directives so that they can be reassembled.
370
9db8dccb
CM		 3712010-05-26 Catherine Moore <clm@codesourcery.com>
372 David Ung <davidu@mips.com>
373
374 * mips-opc.c: Change membership to I1 for instructions ssnop and
375 ehb.
376
dfc8cf43
L		 3772010-05-26 H.J. Lu <hongjiu.lu@intel.com>
378
379 * i386-dis.c (sib): New.
380 (get_sib): Likewise.
381 (print_insn): Call get_sib.
382 OP_E_memory): Use sib.
383
f79e2745
CM		 3842010-05-26 Catherine Moore <clm@codesoourcery.com>
385
386 * mips-dis.c (mips_arch): Remove INSN_MIPS16.
387 * mips-opc.c (I16): Remove.
388 (mips_builtin_op): Reclassify jalx.
389
51b5d4a8
AM		 3902010-05-19 Alan Modra <amodra@gmail.com>
391
392 * ppc-opc.c (powerpc_opcodes): Enable divdeu, devweu, divde,
393 divwe, divdeuo, divweuo, divdeo, divweo for A2. Add icswepx.
394
85d4ac0b
AM		 3952010-05-13 Alan Modra <amodra@gmail.com>
396
397 * ppc-opc.c (powerpc_opcodes): Correct wclr encoding.
398
4547cb56
NC		 3992010-05-11 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
400
401 * arm-dis.c (thumb_opcodes): Update ldmia entry to use new %W
402 format.
403 (print_insn_thumb16): Add support for new %W format.
404
6540b386
TG		 4052010-05-07 Tristan Gingold <gingold@adacore.com>
406
407 * Makefile.in: Regenerate with automake 1.11.1.
408 * aclocal.m4: Ditto.
409
3e01a7fd
NC		 4102010-05-05 Nick Clifton <nickc@redhat.com>
411
412 * po/es.po: Updated Spanish translation.
413
9c9c98a5
NC		 4142010-04-22 Nick Clifton <nickc@redhat.com>
415
416 * po/opcodes.pot: Updated by the Translation project.
417 * po/vi.po: Updated Vietnamese translation.
418
f07af43e
L		 4192010-04-16 H.J. Lu <hongjiu.lu@intel.com>
420
421 * i386-dis.c (get_valid_dis386): Return bad_opcode on unknown
422 bits in opcode.
423
3d540e93
NC		 4242010-04-09 Nick Clifton <nickc@redhat.com>
425
426 * i386-dis.c (print_insn): Remove unused variable op.
427 (OP_sI): Remove unused variable mask.
428
397841b5
AM		 4292010-04-07 Alan Modra <amodra@gmail.com>
430
431 * configure: Regenerate.
432
cee62821
PB		 4332010-04-06 Peter Bergner <bergner@vnet.ibm.com>
434
435 * ppc-opc.c (RBOPT): New define.
436 ("dccci"): Enable for PPCA2. Make operands optional.
437 ("iccci"): Likewise. Do not deprecate for PPC476.
438
accf4463
NC		 4392010-04-02 Masaki Muranaka <monaka@monami-software.com>
440
441 * cr16-opc.c (cr16_instruction): Fix typo in comment.
442
40b36596
JM		 4432010-03-25 Joseph Myers <joseph@codesourcery.com>
444
445 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add tic6x-dis.c.
446 * Makefile.in: Regenerate.
447 * configure.in (bfd_tic6x_arch): New.
448 * configure: Regenerate.
449 * disassemble.c (ARCH_tic6x): Define if ARCH_all.
450 (disassembler): Handle TI C6X.
451 * tic6x-dis.c: New.
452
1985c81c
MF		 4532010-03-24 Mike Frysinger <vapier@gentoo.org>
454
455 * bfin-dis.c (decode_regs_hi): Change REG_LH2 typo to REG_MH2.
456
f66187fd
JM		 4572010-03-23 Joseph Myers <joseph@codesourcery.com>
458
459 * dis-buf.c (buffer_read_memory): Give error for reading just
460 before the start of memory.
461
ce7d077e
SP		 4622010-03-22 Sebastian Pop <sebastian.pop@amd.com>
463 Quentin Neill <quentin.neill@amd.com>
464
465 * i386-dis.c (OP_LWP_I): Removed.
466 (reg_table): Do not use OP_LWP_I, use Iq.
467 (OP_LWPCB_E): Remove use of names16.
468 (OP_LWP_E): Same.
469 * i386-opc.tbl: Removed 16bit LWP insns. 32bit LWP insns
470 should not set the Vex.length bit.
471 * i386-tbl.h: Regenerated.
472
63d0fa4e
AM		 4732010-02-25 Edmar Wienskoski <edmar@freescale.com>
474
475 * ppc-dis.c (ppc_opts): Add PPC_OPCODE_E500MC for "e500mc64".
476
c060226a
NC		 4772010-02-24 Nick Clifton <nickc@redhat.com>
478
479 PR binutils/6773
480 * arm-dis.c (arm_opcodes): Replace <prefix>addsubx with
481 <prefix>asx. Replace <prefix>subaddx with <prefix>sax.
482 (thumb32_opcodes): Likewise.
483
ab7875de
NC		 4842010-02-15 Nick Clifton <nickc@redhat.com>
485
486 * po/vi.po: Updated Vietnamese translation.
487
fee1d3e8
DE		 4882010-02-12 Doug Evans <dje@sebabeach.org>
489
490 * lm32-opinst.c: Regenerate.
491
37ec9240
DE		 4922010-02-11 Doug Evans <dje@sebabeach.org>
493
9468ae89
DE		 494 * cgen-dis.in (print_normal): Delete CGEN_PRINT_NORMAL.
495 (print_address): Delete CGEN_PRINT_ADDRESS.
496 * fr30-dis.c, * frv-dis.c, * ip2k-dis.c, * iq2000-dis.c,
497 * lm32-dis.c, * m32c-dis.c, * m32r-desc.c, * m32r-desc.h,
498 * m32r-dis.c, * mep-dis.c, * mt-dis.c, * openrisc-dis.c,
499 * xc16x-dis.c, * xstormy16-dis.c: Regenerate.
500
37ec9240
DE		 501 * fr30-desc.c, * fr30-desc.h, * fr30-opc.c,
502 * frv-desc.c, * frv-desc.h, * frv-opc.c,
503 * ip2k-desc.c, * ip2k-desc.h, * ip2k-opc.c,
504 * iq2000-desc.c, * iq2000-desc.h, * iq2000-opc.c,
505 * lm32-desc.c, * lm32-desc.h, * lm32-opc.c, * lm32-opinst.c,
506 * m32c-desc.c, * m32c-desc.h, * m32c-opc.c,
507 * m32r-desc.c, * m32r-desc.h, * m32r-opc.c, * m32r-opinst.c,
508 * mep-desc.c, * mep-desc.h, * mep-opc.c,
509 * mt-desc.c, * mt-desc.h, * mt-opc.c,
510 * openrisc-desc.c, * openrisc-desc.h, * openrisc-opc.c,
511 * xc16x-desc.c, * xc16x-desc.h, * xc16x-opc.c,
512 * xstormy16-desc.c, * xstormy16-desc.h, * xstormy16-opc.c: Regenerate.
513
c75ef631
L		 5142010-02-11 H.J. Lu <hongjiu.lu@intel.com>
515
516 * i386-dis.c: Update copyright.
517 * i386-gen.c: Likewise.
518 * i386-opc.h: Likewise.
519 * i386-opc.tbl: Likewise.
520
a683cc34
SP		 5212010-02-10 Quentin Neill <quentin.neill@amd.com>
522 Sebastian Pop <sebastian.pop@amd.com>
523
524 * i386-dis.c (OP_EX_VexImmW): Reintroduced
525 function to handle 5th imm8 operand.
526 (PREFIX_VEX_3A48): Added.
527 (PREFIX_VEX_3A49): Added.
528 (VEX_W_3A48_P_2): Added.
529 (VEX_W_3A49_P_2): Added.
530 (prefix table): Added entries for PREFIX_VEX_3A48
531 and PREFIX_VEX_3A49.
532 (vex table): Added entries for VEX_W_3A48_P_2 and
533 and VEX_W_3A49_P_2.
534 * i386-gen.c (operand_type_init): Added OPERAND_TYPE_VEC_IMM4
535 for Vec_Imm4 operands.
536 * i386-opc.h (enum): Added Vec_Imm4.
537 (i386_operand_type): Added vec_imm4.
538 * i386-opc.tbl: Add entries for vpermilp[ds].
539 * i386-init.h: Regenerated.
540 * i386-tbl.h: Regenerated.
541
cdc51b07
RS		 5422010-02-10 Richard Sandiford <r.sandiford@uk.ibm.com>
543
544 * ppc-dis.c (ppc_opts): Add "pwr4", "pwr5", "pwr5x", "pwr6"
545 and "pwr7". Move "a2" into alphabetical order.
546
ce3d2015
AM		 5472010-02-08 Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
548
549 * ppc-dis.c (ppc_opts): Add titan entry.
550 * ppc-opc.c (TITAN, MULHW): Define.
551 (powerpc_opcodes): Support AppliedMicro Titan core (APM83xxx).
552
68339fdf
SP		 5532010-02-03 Quentin Neill <quentin.neill@amd.com>
554
555 * i386-gen.c (cpu_flag_init): Rename CPU_AMDFAM15_FLAGS
556 to CPU_BDVER1_FLAGS
557 * i386-init.h: Regenerated.
558
f3d55a94
AG		 5592010-02-03 Anthony Green <green@moxielogic.com>
560
561 * moxie-opc.c (moxie_form1_opc_info): Move "nop" from 0x00 to
562 0x0f, and make 0x00 an illegal instruction.
563
b0e28b39
DJ		 5642010-01-29 Daniel Jacobowitz <dan@codesourcery.com>
565
566 * opcodes/arm-dis.c (struct arm_private_data): New.
567 (print_insn_coprocessor, print_insn_arm): Update to use struct
568 arm_private_data.
569 (is_mapping_symbol, get_map_sym_type): New functions.
570 (get_sym_code_type): Check the symbol's section. Do not check
571 mapping symbols.
572 (print_insn): Default to disassembling ARM mode code. Check
573 for mapping symbols separately from other symbols. Use
574 struct arm_private_data.
575
1c480963
L		 5762010-01-28 H.J. Lu <hongjiu.lu@intel.com>
577
578 * i386-dis.c (EXVexWdqScalar): New.
579 (vex_scalar_w_dq_mode): Likewise.
580 (prefix_table): Update entries for PREFIX_VEX_3899,
581 PREFIX_VEX_389B, PREFIX_VEX_389D, PREFIX_VEX_389F,
582 PREFIX_VEX_38A9, PREFIX_VEX_38AB, PREFIX_VEX_38AD,
583 PREFIX_VEX_38AF, PREFIX_VEX_38B9, PREFIX_VEX_38BB,
584 PREFIX_VEX_38BD and PREFIX_VEX_38BF.
585 (intel_operand_size): Handle vex_scalar_w_dq_mode.
586 (OP_EX): Likewise.
587
539f890d
L		 5882010-01-27 H.J. Lu <hongjiu.lu@intel.com>
589
590 * i386-dis.c (XMScalar): New.
591 (EXdScalar): Likewise.
592 (EXqScalar): Likewise.
593 (EXqScalarS): Likewise.
594 (VexScalar): Likewise.
595 (EXdVexScalarS): Likewise.
596 (EXqVexScalarS): Likewise.
597 (XMVexScalar): Likewise.
598 (scalar_mode): Likewise.
599 (d_scalar_mode): Likewise.
600 (d_scalar_swap_mode): Likewise.
601 (q_scalar_mode): Likewise.
602 (q_scalar_swap_mode): Likewise.
603 (vex_scalar_mode): Likewise.
604 (vex_len_table): Duplcate entries for VEX_LEN_10_P_1,
605 VEX_LEN_10_P_3, VEX_LEN_11_P_1, VEX_LEN_11_P_3, VEX_LEN_2A_P_1,
606 VEX_LEN_2A_P_3, VEX_LEN_2C_P_3, VEX_LEN_2D_P_1, VEX_LEN_2E_P_0,
607 VEX_LEN_2E_P_2, VEX_LEN_2F_P_2, VEX_LEN_51_P_1, VEX_LEN_51_P_3,
608 VEX_LEN_52_P_1, VEX_LEN_53_P_1, VEX_LEN_58_P_1, VEX_LEN_58_P_3,
609 VEX_LEN_59_P_1, VEX_LEN_5A_P_1, VEX_LEN_5A_P_3, VEX_LEN_5C_P_1,
610 VEX_LEN_5C_P_3, VEX_LEN_5D_P_1, VEX_LEN_5D_P_3, VEX_LEN_5E_P_1,
611 VEX_LEN_5E_P_3, VEX_LEN_5F_P_1, VEX_LEN_5F_P_3, VEX_LEN_6E_P_2,
612 VEX_LEN_7E_P_1, VEX_LEN_7E_P_2, VEX_LEN_D6_P_2, VEX_LEN_C2_P_1,
613 VEX_LEN_C2_P_3, VEX_LEN_3A0A_P_2 and VEX_LEN_3A0B_P_2.
614 (vex_w_table): Update entries for VEX_W_10_P_1, VEX_W_10_P_3,
615 VEX_W_11_P_1, VEX_W_11_P_3, VEX_W_2E_P_0, VEX_W_2E_P_2,
616 VEX_W_2F_P_0, VEX_W_2F_P_2, VEX_W_51_P_1, VEX_W_51_P_3,
617 VEX_W_52_P_1, VEX_W_53_P_1, VEX_W_58_P_1, VEX_W_58_P_3,
618 VEX_W_59_P_1, VEX_W_59_P_3, VEX_W_5A_P_1, VEX_W_5A_P_3,
619 VEX_W_5C_P_1, VEX_W_5C_P_3, VEX_W_5D_P_1, VEX_W_5D_P_3,
620 VEX_W_5E_P_1, VEX_W_5E_P_3, VEX_W_5F_P_1, VEX_W_5F_P_3,
621 VEX_W_7E_P_1, VEX_W_D6_P_2 VEX_W_C2_P_1, VEX_W_C2_P_3,
622 VEX_W_3A0A_P_2 and VEX_W_3A0B_P_2.
623 (intel_operand_size): Handle d_scalar_mode, d_scalar_swap_mode,
624 q_scalar_mode, q_scalar_swap_mode.
625 (OP_XMM): Handle scalar_mode.
626 (OP_EX): Handle d_scalar_mode, d_scalar_swap_mode, q_scalar_mode
627 and q_scalar_swap_mode.
628 (OP_VEX): Handle vex_scalar_mode.
629
208b4d78
L		 6302010-01-24 H.J. Lu <hongjiu.lu@intel.com>
631
632 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
633
448b213a
L		 6342010-01-24 H.J. Lu <hongjiu.lu@intel.com>
635
636 * i386-dis.c (vex_len_table): Remove trailing { Bad_Opcode }.
637
47cf8fa0
L		 6382010-01-24 H.J. Lu <hongjiu.lu@intel.com>
639
640 * i386-dis.c (prefix_table): Remove trailing { Bad_Opcode }.
641
592d1631
L		 6422010-01-24 H.J. Lu <hongjiu.lu@intel.com>
643
644 * i386-dis.c (Bad_Opcode): New.
645 (bad_opcode): Likewise.
646 (dis386): Replace { "(bad)", { XX } } with { Bad_Opcode }.
647 (dis386_twobyte): Likewise.
648 (reg_table): Likewise.
649 (prefix_table): Likewise.
650 (x86_64_table): Likewise.
651 (vex_len_table): Likewise.
652 (vex_w_table): Likewise.
653 (mod_table): Likewise.
654 (rm_table): Likewise.
655 (float_reg): Likewise.
656 (reg_table): Remove trailing "(bad)" entries.
657 (prefix_table): Likewise.
658 (x86_64_table): Likewise.
659 (vex_len_table): Likewise.
660 (vex_w_table): Likewise.
661 (mod_table): Likewise.
662 (rm_table): Likewise.
663 (get_valid_dis386): Handle bytemode 0.
664
712366da
L		 6652010-01-23 H.J. Lu <hongjiu.lu@intel.com>
666
667 * i386-opc.h (VEXScalar): New.
668
669 * i386-opc.tbl: Replace "Vex" with "Vex=3" on AVX scalar
670 instructions.
671 * i386-tbl.h: Regenerated.
672
706e8205 6732010-01-21 H.J. Lu <hongjiu.lu@intel.com>
73bb6729
L		 674
675 * i386-dis.c (mod_table): Use FXSAVE on xsave and xrstor.
676
677 * i386-opc.tbl: Add xsave64 and xrstor64.
678 * i386-tbl.h: Regenerated.
679
99ea83aa
NC		 6802010-01-20 Nick Clifton <nickc@redhat.com>
681
682 PR 11170
683 * arm-dis.c (print_arm_address): Do not ignore negative bit in PC
684 based post-indexed addressing.
685
a6461c02
SP		 6862010-01-15 Sebastian Pop <sebastian.pop@amd.com>
687
688 * i386-opc.tbl: Support all the possible aliases for VPCOM* insns.
689 * i386-tbl.h: Regenerated.
690
a2a7d12c
L		 6912010-01-14 H.J. Lu <hongjiu.lu@intel.com>
692
693 * i386-opc.h (VexVVVV): Replace VEX.DNS with VEX.NDS in
694 comments.
695
b9733481
L		 6962010-01-14 H.J. Lu <hongjiu.lu@intel.com>
697
698 * i386-dis.c (names_mm): New.
699 (intel_names_mm): Likewise.
700 (att_names_mm): Likewise.
701 (names_xmm): Likewise.
702 (intel_names_xmm): Likewise.
703 (att_names_xmm): Likewise.
704 (names_ymm): Likewise.
705 (intel_names_ymm): Likewise.
706 (att_names_ymm): Likewise.
707 (print_insn): Set names_mm, names_xmm and names_ymm.
708 (OP_MMX): Use names_mm, names_xmm and names_ymm.
709 (OP_XMM): Likewise.
710 (OP_EM): Likewise.
711 (OP_EMC): Likewise.
712 (OP_MXC): Likewise.
713 (OP_EX): Likewise.
714 (XMM_Fixup): Likewise.
715 (OP_VEX): Likewise.
716 (OP_EX_VexReg): Likewise.
717 (OP_Vex_2src): Likewise.
718 (OP_Vex_2src_1): Likewise.
719 (OP_Vex_2src_2): Likewise.
720 (OP_REG_VexI4): Likewise.
721
5e6718e4
L		 7222010-01-13 H.J. Lu <hongjiu.lu@intel.com>
723
724 * i386-dis.c (print_insn): Update comments.
725
d869730d
L		 7262010-01-12 H.J. Lu <hongjiu.lu@intel.com>
727
728 * i386-dis.c (rex_original): Removed.
729 (ckprefix): Remove rex_original.
730 (print_insn): Update comments.
731
3725885a
RW		 7322010-01-09 Ralf Wildenhues <Ralf.Wildenhues@gmx.de>
733
734 * Makefile.in: Regenerate.
735 * configure: Regenerate.
736
b7cd1872
DE		 7372010-01-07 Doug Evans <dje@sebabeach.org>
738
739 * cgen-ibld.in (insert_normal, extract_normal): Minor cleanup.
740 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
741 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
742 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
743 * xstormy16-ibld.c: Regenerate.
744
69dd9865
SP		 7452010-01-06 Quentin Neill <quentin.neill@amd.com>
746
747 * i386-gen.c (cpu_flag_init): Add new CPU_AMDFAM15_FLAGS.
748 * i386-init.h: Regenerated.
749
e3e535bc
NC		 7502010-01-06 Daniel Gutson <dgutson@codesourcery.com>
751
752 * arm-dis.c (print_insn): Fixed search for next symbol and data
753 dumping condition, and the initial mapping symbol state.
754
fe8afbc4
DE		 7552010-01-05 Doug Evans <dje@sebabeach.org>
756
757 * cgen-ibld.in: #include "cgen/basic-modes.h".
758 * fr30-ibld.c, * frv-ibld.c, * ip2k-ibld.c, * iq2000-ibld.c,
759 * lm32-ibld.c, * m32c-ibld.c, * m32r-ibld.c, * mep-ibld.c,
760 * mt-ibld.c, * openrisc-ibld.c, * xc16x-ibld.c,
761 * xstormy16-ibld.c: Regenerate.
762
2edcd244
NC		 7632010-01-04 Nick Clifton <nickc@redhat.com>
764
765 PR 11123
766 * arm-dis.c (print_insn_coprocessor): Initialise value.
767
0dc93057
AM		 7682010-01-04 Edmar Wienskoski <edmar@freescale.com>
769
770 * ppc-dis.c (ppc_opts): Add entry for "e500mc64".
771
05994f45
DE		 7722010-01-02 Doug Evans <dje@sebabeach.org>
773
774 * cgen-asm.in: Update copyright year.
775 * cgen-dis.in: Update copyright year.
776 * cgen-ibld.in: Update copyright year.
777 * fr30-asm.c, * fr30-desc.c, * fr30-desc.h, * fr30-dis.c,
778 * fr30-ibld.c, * fr30-opc.c, * fr30-opc.h, * frv-asm.c, * frv-desc.c,
779 * frv-desc.h, * frv-dis.c, * frv-ibld.c, * frv-opc.c, * frv-opc.h,
780 * ip2k-asm.c, * ip2k-desc.c, * ip2k-desc.h, * ip2k-dis.c,
781 * ip2k-ibld.c, * ip2k-opc.c, * ip2k-opc.h, * iq2000-asm.c,
782 * iq2000-desc.c, * iq2000-desc.h, * iq2000-dis.c, * iq2000-ibld.c,
783 * iq2000-opc.c, * iq2000-opc.h, * lm32-asm.c, * lm32-desc.c,
784 * lm32-desc.h, * lm32-dis.c, * lm32-ibld.c, * lm32-opc.c, * lm32-opc.h,
785 * lm32-opinst.c, * m32c-asm.c, * m32c-desc.c, * m32c-desc.h,
786 * m32c-dis.c, * m32c-ibld.c, * m32c-opc.c, * m32c-opc.h, * m32r-asm.c,
787 * m32r-desc.c, * m32r-desc.h, * m32r-dis.c, * m32r-ibld.c,
788 * m32r-opc.c, * m32r-opc.h, * m32r-opinst.c, * mep-asm.c, * mep-desc.c,
789 * mep-desc.h, * mep-dis.c, * mep-ibld.c, * mep-opc.c, * mep-opc.h,
790 * mt-asm.c, * mt-desc.c, * mt-desc.h, * mt-dis.c, * mt-ibld.c,
791 * mt-opc.c, * mt-opc.h, * openrisc-asm.c, * openrisc-desc.c,
792 * openrisc-desc.h, * openrisc-dis.c, * openrisc-ibld.c,
793 * openrisc-opc.c, * openrisc-opc.h, * xc16x-asm.c, * xc16x-desc.c,
794 * xc16x-desc.h, * xc16x-dis.c, * xc16x-ibld.c, * xc16x-opc.c,
795 * xc16x-opc.h, * xstormy16-asm.c, * xstormy16-desc.c,
796 * xstormy16-desc.h, * xstormy16-dis.c, * xstormy16-ibld.c,
797 * xstormy16-opc.c, * xstormy16-opc.h: Regenerate.
2426c15f 798
43ecc30f 799For older changes see ChangeLog-2009
252b5132
RH		 800\f
801Local Variables:
2f6d2f85
NC		 802mode: change-log
803left-margin: 8
804fill-column: 74
252b5132
RH		 805version-control: never
806End:
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