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[thirdparty/binutils-gdb.git] / opcodes / ChangeLog
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fc76e730
RS		 12013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
2
3 * mips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2, UDI):
4 New macros.
5 (WR_d, WR_t, WR_D, WR_T, WR_S, RD_s, RD_b, RD_t, RD_S, RD_T, RD_R)
6 (WR_z, WR_Z, RD_z, RD_Z, RD_d): Delete.
7 (mips_builtin_opcodes): Use the new position-based read-write flags
8 instead of field-based ones. Use UDI for "udi..." instructions.
9 * mips16-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
10 New macros.
11 (WR_x, WR_y, WR_z, WR_Y, RD_x, RD_y, RD_Z, RD_X): Delete.
12 (RD_T, WR_T, WR_31): Redefine using generic INSN_* flags.
13 (WR_SP, RD_16): New macros.
14 (RD_SP): Redefine as an INSN2_* flag.
15 (MOD_SP): Redefine in terms of RD_SP and WR_SP.
16 (mips16_opcodes): Use the new position-based read-write flags
17 instead of field-based ones. Use RD_16 for "nop". Move RD_SP to
18 pinfo2 field.
19 * micromips-opc.c (WR_1, WR_2, RD_1, RD_2, RD_3, RD_4, MOD_1, MOD_2):
20 New macros.
21 (WR_mb, RD_mc, RD_md, WR_md, RD_me, RD_mf, WR_mf, RD_mg, WR_mh, RD_mj)
22 (WR_mj, RD_ml, RD_mmn, RD_mp, WR_mp, RD_mq, RD_gp, WR_d, WR_t, WR_D)
23 (WR_T, WR_S, RD_s, RD_b, RD_t, RD_T, RD_S, RD_R, RD_D): Delete.
24 (RD_sp, WR_sp): Redefine to INSN2_READ_SP and INSN2_WRITE_SP.
25 (micromips_opcodes): Use the new position-based read-write flags
26 instead of field-based ones.
27 * mips-dis.c (print_insn_arg): Use mips_decode_reg_operand.
28 (print_insn_mips, print_insn_micromips): Use INSN_WRITE_1 instead
29 of field-based flags.
30
26545944
RS		 312013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
32
33 * mips16-opc.c (UBR, CBR, RD_31, RD_PC): Redefine as INSN2_* flags.
34 (WR_SP): Replace with...
35 (MOD_SP): ...this.
36 (mips16_opcodes): Update accordingly.
37 * mips-dis.c (print_insn_mips16): Likewise.
38
a8d92fc6
RS		 392013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
40
41 * mips16-opc.c (mips16_opcodes): Reformat.
42
6a819047
RS		 432013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
44
45 * mips-opc.c (mips_builtin_opcodes): Remove WR_* and RD_* flags
46 for operands that are hard-coded to $0.
47 * micromips-opc.c (micromips_opcodes): Likewise.
48
344c74a6
RS		 492013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
50
51 * mips-opc.c (mips_builtin_opcodes): Use WR_31 rather than WR_d
52 for the single-operand forms of JALR and JALR.HB.
53 * micromips-opc.c (micromips_opcodes): Likewise JALR, JALRS, JALR.HB
54 and JALRS.HB.
55
41989114
RS		 562013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
57
58 * mips-opc.c (mips_builtin_opcodes): Add FP_D to VR5400 vector
59 instructions. Fix them to use WR_MACC instead of WR_CC and
60 add missing RD_MACCs.
61
6d075bce
RS		 622013-08-01 Richard Sandiford <rdsandiford@googlemail.com>
63
64 * mips-dis.c (print_mips16_insn_arg): Include ISA bit in base address.
65
4f6ffcd3
PB		 662013-07-29 Peter Bergner <bergner@vnet.ibm.com>
67
68 * ppc-dis.c (powerpc_init_dialect): Use ppc_parse_cpu() to set dialect.
69
43234a1e
L		 702013-07-26 Sergey Guriev <sergey.s.guriev@intel.com>
71 Alexander Ivchenko <alexander.ivchenko@intel.com>
72 Maxim Kuznetsov <maxim.kuznetsov@intel.com>
73 Sergey Lega <sergey.s.lega@intel.com>
74 Anna Tikhonova <anna.tikhonova@intel.com>
75 Ilya Tocar <ilya.tocar@intel.com>
76 Andrey Turetskiy <andrey.turetskiy@intel.com>
77 Ilya Verbin <ilya.verbin@intel.com>
78 Kirill Yukhin <kirill.yukhin@intel.com>
79 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
80
81 * i386-dis-evex.h: New.
82 * i386-dis.c (OP_Rounding): New.
83 (VPCMP_Fixup): New.
84 (OP_Mask): New.
85 (Rdq): New.
86 (XMxmmq): New.
87 (EXdScalarS): New.
88 (EXymm): New.
89 (EXEvexHalfBcstXmmq): New.
90 (EXxmm_mdq): New.
91 (EXEvexXGscat): New.
92 (EXEvexXNoBcst): New.
93 (VPCMP): New.
94 (EXxEVexR): New.
95 (EXxEVexS): New.
96 (XMask): New.
97 (MaskG): New.
98 (MaskE): New.
99 (MaskR): New.
100 (MaskVex): New.
101 (modes enum): Add evex_x_gscat_mode, evex_x_nobcst_mode,
102 evex_half_bcst_xmmq_mode, xmm_mdq_mode, ymm_mode,
103 evex_rounding_mode, evex_sae_mode, mask_mode.
104 (USE_EVEX_TABLE): New.
105 (EVEX_TABLE): New.
106 (EVEX enum): New.
107 (REG enum): Add REG_EVEX_0F72, REG_EVEX_0F73, REG_EVEX_0F38C6,
108 REG_EVEX_0F38C7.
109 (MOD enum): Add MOD_EVEX_0F10_PREFIX_1, MOD_EVEX_0F10_PREFIX_3,
110 MOD_EVEX_0F11_PREFIX_1, MOD_EVEX_0F11_PREFIX_3,
111 MOD_EVEX_0F12_PREFIX_0, MOD_EVEX_0F16_PREFIX_0, MOD_EVEX_0F38C6_REG_1,
112 MOD_EVEX_0F38C6_REG_2, MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
113 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2, MOD_EVEX_0F38C7_REG_5,
114 MOD_EVEX_0F38C7_REG_6.
115 (PREFIX enum): Add PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
116 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47, PREFIX_VEX_0F4B,
117 PREFIX_VEX_0F90, PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
118 PREFIX_VEX_0F98, PREFIX_VEX_0F3A30, PREFIX_VEX_0F3A32,
119 PREFIX_VEX_0F3AF0, PREFIX_EVEX_0F10, PREFIX_EVEX_0F11,
120 PREFIX_EVEX_0F12, PREFIX_EVEX_0F13, PREFIX_EVEX_0F14,
121 PREFIX_EVEX_0F15, PREFIX_EVEX_0F16, PREFIX_EVEX_0F17,
122 PREFIX_EVEX_0F28, PREFIX_EVEX_0F29, PREFIX_EVEX_0F2A,
123 PREFIX_EVEX_0F2B, PREFIX_EVEX_0F2C, PREFIX_EVEX_0F2D,
124 PREFIX_EVEX_0F2E, PREFIX_EVEX_0F2F, PREFIX_EVEX_0F51,
125 PREFIX_EVEX_0F58, PREFIX_EVEX_0F59, PREFIX_EVEX_0F5A,
126 PREFIX_EVEX_0F5B, PREFIX_EVEX_0F5C, PREFIX_EVEX_0F5D,
127 PREFIX_EVEX_0F5E, PREFIX_EVEX_0F5F, PREFIX_EVEX_0F62,
128 PREFIX_EVEX_0F66, PREFIX_EVEX_0F6A, PREFIX_EVEX_0F6C,
129 PREFIX_EVEX_0F6D, PREFIX_EVEX_0F6E, PREFIX_EVEX_0F6F,
130 PREFIX_EVEX_0F70, PREFIX_EVEX_0F72_REG_0, PREFIX_EVEX_0F72_REG_1,
131 PREFIX_EVEX_0F72_REG_2, PREFIX_EVEX_0F72_REG_4,
132 PREFIX_EVEX_0F72_REG_6, PREFIX_EVEX_0F73_REG_2,
133 PREFIX_EVEX_0F73_REG_6, PREFIX_EVEX_0F76, PREFIX_EVEX_0F78,
134 PREFIX_EVEX_0F79, PREFIX_EVEX_0F7A, PREFIX_EVEX_0F7B,
135 PREFIX_EVEX_0F7E, PREFIX_EVEX_0F7F, PREFIX_EVEX_0FC2,
136 PREFIX_EVEX_0FC6, PREFIX_EVEX_0FD2, PREFIX_EVEX_0FD3,
137 PREFIX_EVEX_0FD4, PREFIX_EVEX_0FD6, PREFIX_EVEX_0FDB,
138 PREFIX_EVEX_0FDF, PREFIX_EVEX_0FE2, PREFIX_EVEX_0FE6 PREFIX_EVEX_0FE7,
139 PREFIX_EVEX_0FEB, PREFIX_EVEX_0FEF, PREFIX_EVEX_0FF2,
140 PREFIX_EVEX_0FF3, PREFIX_EVEX_0FF4, PREFIX_EVEX_0FFA, PREFIX_EVEX_0FFB,
141 PREFIX_EVEX_0FFE, PREFIX_EVEX_0F380C, PREFIX_EVEX_0F380D,
142 PREFIX_EVEX_0F3811, PREFIX_EVEX_0F3812, PREFIX_EVEX_0F3813,
143 PREFIX_EVEX_0F3814, PREFIX_EVEX_0F3815, PREFIX_EVEX_0F3816,
144 PREFIX_EVEX_0F3818, PREFIX_EVEX_0F3819, PREFIX_EVEX_0F381A,
145 PREFIX_EVEX_0F381B, PREFIX_EVEX_0F381E, PREFIX_EVEX_0F381F,
146 PREFIX_EVEX_0F3821, PREFIX_EVEX_0F3822, PREFIX_EVEX_0F3823,
147 PREFIX_EVEX_0F3824, PREFIX_EVEX_0F3825, PREFIX_EVEX_0F3827,
148 PREFIX_EVEX_0F3828, PREFIX_EVEX_0F3829, PREFIX_EVEX_0F382A,
149 PREFIX_EVEX_0F382C, PREFIX_EVEX_0F382D, PREFIX_EVEX_0F3831,
150 PREFIX_EVEX_0F3832, PREFIX_EVEX_0F3833, PREFIX_EVEX_0F3834,
151 PREFIX_EVEX_0F3835, PREFIX_EVEX_0F3836, PREFIX_EVEX_0F3837,
152 PREFIX_EVEX_0F3839, PREFIX_EVEX_0F383A, PREFIX_EVEX_0F383B,
153 PREFIX_EVEX_0F383D, PREFIX_EVEX_0F383F, PREFIX_EVEX_0F3840,
154 PREFIX_EVEX_0F3842, PREFIX_EVEX_0F3843, PREFIX_EVEX_0F3844,
155 PREFIX_EVEX_0F3845, PREFIX_EVEX_0F3846, PREFIX_EVEX_0F3847,
156 PREFIX_EVEX_0F384C, PREFIX_EVEX_0F384D, PREFIX_EVEX_0F384E,
157 PREFIX_EVEX_0F384F, PREFIX_EVEX_0F3858, PREFIX_EVEX_0F3859,
158 PREFIX_EVEX_0F385A, PREFIX_EVEX_0F385B, PREFIX_EVEX_0F3864,
159 PREFIX_EVEX_0F3865, PREFIX_EVEX_0F3876, PREFIX_EVEX_0F3877,
160 PREFIX_EVEX_0F387C, PREFIX_EVEX_0F387E, PREFIX_EVEX_0F387F,
161 PREFIX_EVEX_0F3888, PREFIX_EVEX_0F3889, PREFIX_EVEX_0F388A,
162 PREFIX_EVEX_0F388B, PREFIX_EVEX_0F3890, PREFIX_EVEX_0F3891,
163 PREFIX_EVEX_0F3892, PREFIX_EVEX_0F3893, PREFIX_EVEX_0F3896,
164 PREFIX_EVEX_0F3897, PREFIX_EVEX_0F3898, PREFIX_EVEX_0F3899,
165 PREFIX_EVEX_0F389A, PREFIX_EVEX_0F389B, PREFIX_EVEX_0F389C,
166 PREFIX_EVEX_0F389D, PREFIX_EVEX_0F389E, PREFIX_EVEX_0F389F,
167 PREFIX_EVEX_0F38A0, PREFIX_EVEX_0F38A1, PREFIX_EVEX_0F38A2,
168 PREFIX_EVEX_0F38A3, PREFIX_EVEX_0F38A6, PREFIX_EVEX_0F38A7,
169 PREFIX_EVEX_0F38A8, PREFIX_EVEX_0F38A9, PREFIX_EVEX_0F38AA,
170 PREFIX_EVEX_0F38AB, PREFIX_EVEX_0F38AC, PREFIX_EVEX_0F38AD,
171 PREFIX_EVEX_0F38AE, PREFIX_EVEX_0F38AF, PREFIX_EVEX_0F38B6,
172 PREFIX_EVEX_0F38B7, PREFIX_EVEX_0F38B8, PREFIX_EVEX_0F38B9,
173 PREFIX_EVEX_0F38BA, PREFIX_EVEX_0F38BB, PREFIX_EVEX_0F38BC,
174 PREFIX_EVEX_0F38BD, PREFIX_EVEX_0F38BE, PREFIX_EVEX_0F38BF,
175 PREFIX_EVEX_0F38C4, PREFIX_EVEX_0F38C6_REG_1,
176 PREFIX_EVEX_0F38C6_REG_2, PREFIX_EVEX_0F38C6_REG_5,
177 PREFIX_EVEX_0F38C6_REG_6, PREFIX_EVEX_0F38C7_REG_1,
178 PREFIX_EVEX_0F38C7_REG_2, PREFIX_EVEX_0F38C7_REG_5,
179 PREFIX_EVEX_0F38C7_REG_6, PREFIX_EVEX_0F38C8, PREFIX_EVEX_0F38CA,
180 PREFIX_EVEX_0F38CB, PREFIX_EVEX_0F38CC, PREFIX_EVEX_0F38CD,
181 PREFIX_EVEX_0F3A00, PREFIX_EVEX_0F3A01, PREFIX_EVEX_0F3A03,
182 PREFIX_EVEX_0F3A04, PREFIX_EVEX_0F3A05, PREFIX_EVEX_0F3A08,
183 PREFIX_EVEX_0F3A09, PREFIX_EVEX_0F3A0A, PREFIX_EVEX_0F3A0B,
184 PREFIX_EVEX_0F3A17, PREFIX_EVEX_0F3A18, PREFIX_EVEX_0F3A19,
185 PREFIX_EVEX_0F3A1A, PREFIX_EVEX_0F3A1B, PREFIX_EVEX_0F3A1D,
186 PREFIX_EVEX_0F3A1E, PREFIX_EVEX_0F3A1F, PREFIX_EVEX_0F3A21,
187 PREFIX_EVEX_0F3A23, PREFIX_EVEX_0F3A25, PREFIX_EVEX_0F3A26,
188 PREFIX_EVEX_0F3A27, PREFIX_EVEX_0F3A38, PREFIX_EVEX_0F3A39,
189 PREFIX_EVEX_0F3A3A, PREFIX_EVEX_0F3A3B, PREFIX_EVEX_0F3A3E,
190 PREFIX_EVEX_0F3A3F, PREFIX_EVEX_0F3A43, PREFIX_EVEX_0F3A54,
191 PREFIX_EVEX_0F3A55.
192 (VEX_LEN enum): Add VEX_LEN_0F41_P_0, VEX_LEN_0F42_P_0, VEX_LEN_0F44_P_0,
193 VEX_LEN_0F45_P_0, VEX_LEN_0F46_P_0, VEX_LEN_0F47_P_0,
194 VEX_LEN_0F4B_P_2, VEX_LEN_0F90_P_0, VEX_LEN_0F91_P_0,
195 VEX_LEN_0F92_P_0, VEX_LEN_0F93_P_0, VEX_LEN_0F98_P_0,
196 VEX_LEN_0F3A30_P_2, VEX_LEN_0F3A32_P_2, VEX_W_0F41_P_0_LEN_1,
197 VEX_W_0F42_P_0_LEN_1, VEX_W_0F44_P_0_LEN_0, VEX_W_0F45_P_0_LEN_1,
198 VEX_W_0F46_P_0_LEN_1, VEX_W_0F47_P_0_LEN_1, VEX_W_0F4B_P_2_LEN_1,
199 VEX_W_0F90_P_0_LEN_0, VEX_W_0F91_P_0_LEN_0, VEX_W_0F92_P_0_LEN_0,
200 VEX_W_0F93_P_0_LEN_0, VEX_W_0F98_P_0_LEN_0, VEX_W_0F3A30_P_2_LEN_0,
201 VEX_W_0F3A32_P_2_LEN_0.
202 (VEX_W enum): Add EVEX_W_0F10_P_0, EVEX_W_0F10_P_1_M_0,
203 EVEX_W_0F10_P_1_M_1, EVEX_W_0F10_P_2, EVEX_W_0F10_P_3_M_0,
204 EVEX_W_0F10_P_3_M_1, EVEX_W_0F11_P_0, EVEX_W_0F11_P_1_M_0,
205 EVEX_W_0F11_P_1_M_1, EVEX_W_0F11_P_2, EVEX_W_0F11_P_3_M_0,
206 EVEX_W_0F11_P_3_M_1, EVEX_W_0F12_P_0_M_0, EVEX_W_0F12_P_0_M_1,
207 EVEX_W_0F12_P_1, EVEX_W_0F12_P_2, EVEX_W_0F12_P_3, EVEX_W_0F13_P_0,
208 EVEX_W_0F13_P_2, EVEX_W_0F14_P_0, EVEX_W_0F14_P_2, EVEX_W_0F15_P_0,
209 EVEX_W_0F15_P_2, EVEX_W_0F16_P_0_M_0, EVEX_W_0F16_P_0_M_1,
210 EVEX_W_0F16_P_1, EVEX_W_0F16_P_2, EVEX_W_0F17_P_0, EVEX_W_0F17_P_2,
211 EVEX_W_0F28_P_0, EVEX_W_0F28_P_2, EVEX_W_0F29_P_0, EVEX_W_0F29_P_2,
212 EVEX_W_0F2A_P_1, EVEX_W_0F2A_P_3, EVEX_W_0F2B_P_0, EVEX_W_0F2B_P_2,
213 EVEX_W_0F2E_P_0, EVEX_W_0F2E_P_2, EVEX_W_0F2F_P_0, EVEX_W_0F2F_P_2,
214 EVEX_W_0F51_P_0, EVEX_W_0F51_P_1, EVEX_W_0F51_P_2, EVEX_W_0F51_P_3,
215 EVEX_W_0F58_P_0, EVEX_W_0F58_P_1, EVEX_W_0F58_P_2, EVEX_W_0F58_P_3,
216 EVEX_W_0F59_P_0, EVEX_W_0F59_P_1, EVEX_W_0F59_P_2, EVEX_W_0F59_P_3,
217 EVEX_W_0F5A_P_0, EVEX_W_0F5A_P_1, EVEX_W_0F5A_P_2, EVEX_W_0F5A_P_3,
218 EVEX_W_0F5B_P_0, EVEX_W_0F5B_P_1, EVEX_W_0F5B_P_2, EVEX_W_0F5C_P_0,
219 EVEX_W_0F5C_P_1, EVEX_W_0F5C_P_2, EVEX_W_0F5C_P_3, EVEX_W_0F5D_P_0,
220 EVEX_W_0F5D_P_1, EVEX_W_0F5D_P_2, EVEX_W_0F5D_P_3, EVEX_W_0F5E_P_0,
221 EVEX_W_0F5E_P_1, EVEX_W_0F5E_P_2, EVEX_W_0F5E_P_3, EVEX_W_0F5F_P_0,
222 EVEX_W_0F5F_P_1, EVEX_W_0F5F_P_2, EVEX_W_0F5F_P_3, EVEX_W_0F62_P_2,
223 EVEX_W_0F66_P_2, EVEX_W_0F6A_P_2, EVEX_W_0F6C_P_2, EVEX_W_0F6D_P_2,
224 EVEX_W_0F6E_P_2, EVEX_W_0F6F_P_1, EVEX_W_0F6F_P_2, EVEX_W_0F70_P_2,
225 EVEX_W_0F72_R_2_P_2, EVEX_W_0F72_R_6_P_2, EVEX_W_0F73_R_2_P_2,
226 EVEX_W_0F73_R_6_P_2, EVEX_W_0F76_P_2, EVEX_W_0F78_P_0,
227 EVEX_W_0F79_P_0, EVEX_W_0F7A_P_1, EVEX_W_0F7A_P_3, EVEX_W_0F7B_P_1,
228 EVEX_W_0F7B_P_3, EVEX_W_0F7E_P_1, EVEX_W_0F7E_P_2, EVEX_W_0F7F_P_1,
229 EVEX_W_0F7F_P_2, EVEX_W_0FC2_P_0, EVEX_W_0FC2_P_1, EVEX_W_0FC2_P_2,
230 EVEX_W_0FC2_P_3, EVEX_W_0FC6_P_0, EVEX_W_0FC6_P_2, EVEX_W_0FD2_P_2,
231 EVEX_W_0FD3_P_2, EVEX_W_0FD4_P_2, EVEX_W_0FD6_P_2, EVEX_W_0FE6_P_1,
232 EVEX_W_0FE6_P_2, EVEX_W_0FE6_P_3, EVEX_W_0FE7_P_2, EVEX_W_0FF2_P_2,
233 EVEX_W_0FF3_P_2, EVEX_W_0FF4_P_2, EVEX_W_0FFA_P_2, EVEX_W_0FFB_P_2,
234 EVEX_W_0FFE_P_2, EVEX_W_0F380C_P_2, EVEX_W_0F380D_P_2,
235 EVEX_W_0F3811_P_1, EVEX_W_0F3812_P_1, EVEX_W_0F3813_P_1,
236 EVEX_W_0F3813_P_2, EVEX_W_0F3814_P_1, EVEX_W_0F3815_P_1,
237 EVEX_W_0F3818_P_2, EVEX_W_0F3819_P_2, EVEX_W_0F381A_P_2,
238 EVEX_W_0F381B_P_2, EVEX_W_0F381E_P_2, EVEX_W_0F381F_P_2,
239 EVEX_W_0F3821_P_1, EVEX_W_0F3822_P_1, EVEX_W_0F3823_P_1,
240 EVEX_W_0F3824_P_1, EVEX_W_0F3825_P_1, EVEX_W_0F3825_P_2,
241 EVEX_W_0F3828_P_2, EVEX_W_0F3829_P_2, EVEX_W_0F382A_P_1,
242 EVEX_W_0F382A_P_2, EVEX_W_0F3831_P_1, EVEX_W_0F3832_P_1,
243 EVEX_W_0F3833_P_1, EVEX_W_0F3834_P_1, EVEX_W_0F3835_P_1,
244 EVEX_W_0F3835_P_2, EVEX_W_0F3837_P_2, EVEX_W_0F383A_P_1,
245 EVEX_W_0F3840_P_2, EVEX_W_0F3858_P_2, EVEX_W_0F3859_P_2,
246 EVEX_W_0F385A_P_2, EVEX_W_0F385B_P_2, EVEX_W_0F3891_P_2,
247 EVEX_W_0F3893_P_2, EVEX_W_0F38A1_P_2, EVEX_W_0F38A3_P_2,
248 EVEX_W_0F38C7_R_1_P_2, EVEX_W_0F38C7_R_2_P_2, EVEX_W_0F38C7_R_5_P_2,
249 EVEX_W_0F38C7_R_6_P_2, EVEX_W_0F3A00_P_2, EVEX_W_0F3A01_P_2,
250 EVEX_W_0F3A04_P_2, EVEX_W_0F3A05_P_2, EVEX_W_0F3A08_P_2,
251 EVEX_W_0F3A09_P_2, EVEX_W_0F3A0A_P_2, EVEX_W_0F3A0B_P_2,
252 EVEX_W_0F3A18_P_2, EVEX_W_0F3A19_P_2, EVEX_W_0F3A1A_P_2,
253 EVEX_W_0F3A1B_P_2, EVEX_W_0F3A1D_P_2, EVEX_W_0F3A21_P_2,
254 EVEX_W_0F3A23_P_2, EVEX_W_0F3A38_P_2, EVEX_W_0F3A39_P_2,
255 EVEX_W_0F3A3A_P_2, EVEX_W_0F3A3B_P_2, EVEX_W_0F3A43_P_2.
256 (struct vex): Add fields evex, r, v, mask_register_specifier,
257 zeroing, ll, b.
258 (intel_names_xmm): Add upper 16 registers.
259 (att_names_xmm): Ditto.
260 (intel_names_ymm): Ditto.
261 (att_names_ymm): Ditto.
262 (names_zmm): New.
263 (intel_names_zmm): Ditto.
264 (att_names_zmm): Ditto.
265 (names_mask): Ditto.
266 (intel_names_mask): Ditto.
267 (att_names_mask): Ditto.
268 (names_rounding): Ditto.
269 (names_broadcast): Ditto.
270 (x86_64_table): Add escape to evex-table.
271 (reg_table): Include reg_table evex-entries from
272 i386-dis-evex.h. Fix prefetchwt1 instruction.
273 (prefix_table): Add entries for new instructions.
274 (vex_table): Ditto.
275 (vex_len_table): Ditto.
276 (vex_w_table): Ditto.
277 (mod_table): Ditto.
278 (get_valid_dis386): Properly handle new instructions.
279 (print_insn): Handle zmm and mask registers, print mask operand.
280 (intel_operand_size): Support EVEX, new modes and sizes.
281 (OP_E_register): Handle new modes.
282 (OP_E_memory): Ditto.
283 (OP_G): Ditto.
284 (OP_XMM): Ditto.
285 (OP_EX): Ditto.
286 (OP_VEX): Ditto.
287 * i386-gen.c (cpu_flag_init): Update CPU_ANY_SSE_FLAGS and
288 CPU_ANY_AVX_FLAGS. Add CPU_AVX512F_FLAGS, CPU_AVX512CD_FLAGS,
289 CPU_AVX512ER_FLAGS and CPU_AVX512PF_FLAGS.
290 (cpu_flags): Add CpuAVX512F, CpuAVX512CD, CpuAVX512ER,
291 CpuAVX512PF and CpuVREX.
292 (operand_type_init): Add OPERAND_TYPE_REGZMM,
293 OPERAND_TYPE_REGMASK and OPERAND_TYPE_VEC_DISP8.
294 (opcode_modifiers): Add EVex, Masking, VecESize, Broadcast,
295 StaticRounding, SAE, Disp8MemShift, NoDefMask.
296 (operand_types): Add RegZMM, RegMask, Vec_Disp8, Zmmword.
297 * i386-init.h: Regenerate.
298 * i386-opc.h (CpuAVX512F): New.
299 (CpuAVX512CD): New.
300 (CpuAVX512ER): New.
301 (CpuAVX512PF): New.
302 (CpuVREX): New.
303 (i386_cpu_flags): Add cpuavx512f, cpuavx512cd, cpuavx512er,
304 cpuavx512pf and cpuvrex fields.
305 (VecSIB): Add VecSIB512.
306 (EVex): New.
307 (Masking): New.
308 (VecESize): New.
309 (Broadcast): New.
310 (StaticRounding): New.
311 (SAE): New.
312 (Disp8MemShift): New.
313 (NoDefMask): New.
314 (i386_opcode_modifier): Add evex, masking, vecesize, broadcast,
315 staticrounding, sae, disp8memshift and nodefmask.
316 (RegZMM): New.
317 (Zmmword): Ditto.
318 (Vec_Disp8): Ditto.
319 (i386_operand_type): Add regzmm, regmask, zmmword and vec_disp8
320 fields.
321 (RegVRex): New.
322 * i386-opc.tbl: Add AVX512 instructions.
323 * i386-reg.tbl: Add 16 upper XMM and YMM registers, 32 new ZMM
324 registers, mask registers.
325 * i386-tbl.h: Regenerate.
326
1d2db237
RS		 3272013-07-25 Aaro Koskinen <aaro.koskinen@iki.fi>
328
329 PR gas/15220
330 * mips-opc.c (mips_builtin_opcodes): Fix wrong opcodes for
331 Loongson 2F madd.ps, msub.ps, nmadd.ps and nmsub.ps.
332
a0046408
L		 3332013-07-25 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
334
335 * i386-dis.c (PREFIX enum): Add PREFIX_0F38C8, PREFIX_0F38C9,
336 PREFIX_0F38CA, PREFIX_0F38CB, PREFIX_0F38CC, PREFIX_0F38CD,
337 PREFIX_0F3ACC.
338 (prefix_table): Updated.
339 (three_byte_table): Likewise.
340 * i386-gen.c (cpu_flag_init): Add CPU_SHA_FLAGS.
341 (cpu_flags): Add CpuSHA.
342 (i386_cpu_flags): Add cpusha.
343 * i386-init.h: Regenerate.
344 * i386-opc.h (CpuSHA): New.
345 (CpuUnused): Restored.
346 (i386_cpu_flags): Add cpusha.
347 * i386-opc.tbl: Add SHA instructions.
348 * i386-tbl.h: Regenerate.
349
7e8b059b
L		 3502013-07-24 Anna Tikhonova <anna.tikhonova@intel.com>
351 Kirill Yukhin <kirill.yukhin@intel.com>
352 Michael Zolotukhin <michael.v.zolotukhin@intel.com>
353
354 * i386-dis.c (BND_Fixup): New.
355 (Ebnd): New.
356 (Ev_bnd): New.
357 (Gbnd): New.
358 (BND): New.
359 (v_bnd_mode): New.
360 (bnd_mode): New.
c623f86c
L		 361 (MOD enum): Add MOD_0F1A_PREFIX_0, MOD_0F1B_PREFIX_0,
362 MOD_0F1B_PREFIX_1.
363 (PREFIX enum): Add PREFIX_0F1A, PREFIX_0F1B.
7e8b059b
L		 364 (dis tables): Replace XX with BND for near branch and call
365 instructions.
366 (prefix_table): Add new entries.
367 (mod_table): Likewise.
368 (names_bnd): New.
369 (intel_names_bnd): New.
370 (att_names_bnd): New.
371 (BND_PREFIX): New.
372 (prefix_name): Handle BND_PREFIX.
373 (print_insn): Initialize names_bnd.
374 (intel_operand_size): Handle new modes.
375 (OP_E_register): Likewise.
376 (OP_E_memory): Likewise.
377 (OP_G): Likewise.
378 * i386-gen.c (cpu_flag_init): Add CpuMPX.
379 (cpu_flags): Add CpuMPX.
380 (operand_type_init): Add RegBND.
381 (opcode_modifiers): Add BNDPrefixOk.
382 (operand_types): Add RegBND.
383 * i386-init.h: Regenerate.
384 * i386-opc.h (CpuMPX): New.
385 (CpuUnused): Comment out.
386 (i386_cpu_flags): Add cpumpx.
387 (BNDPrefixOk): New.
388 (i386_opcode_modifier): Add bndprefixok.
389 (RegBND): New.
390 (i386_operand_type): Add regbnd.
391 * i386-opc.tbl: Add BNDPrefixOk to near jumps, calls and rets.
392 Add MPX instructions and bnd prefix.
393 * i386-reg.tbl: Add bnd0-bnd3 registers.
394 * i386-tbl.h: Regenerate.
395
b56e23fb
RS		 3962013-07-17 Richard Sandiford <rdsandiford@googlemail.com>
397
398 * mips-formats.h (MAPPED_INT, MAPPED_REG, REG_PAIR): Add
399 ATTRIBUTE_UNUSED.
400
e7ae278d
RS		 4012013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
402
403 * Makefile.am (mips-opc.lo, micromips-opc.lo, mips16-opc.lo): Remove
404 special rules.
405 * Makefile.in: Regenerate.
406 * mips-opc.c, micromips-opc.c, mips16-opc.c: Explicitly initialize
407 all fields. Reformat.
408
c3c07478
RS		 4092013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
410
411 * mips16-opc.c: Include mips-formats.h.
412 (reg_0_map, reg_29_map, reg_31_map, reg_m16_map, reg32r_map): New
413 static arrays.
414 (decode_mips16_operand): New function.
415 * mips-dis.c (mips16_to_32_reg_map, mips16_reg_names): Delete.
416 (print_insn_arg): Handle OP_ENTRY_EXIT list.
417 Abort for OP_SAVE_RESTORE_LIST.
418 (print_mips16_insn_arg): Change interface. Use mips_operand
419 structures. Delete GET_OP_S. Move GET_OP definition to...
420 (print_insn_mips16): ...here. Call init_print_arg_state.
421 Update the call to print_mips16_insn_arg.
422
ab902481
RS		 4232013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
424
425 * mips-formats.h: New file.
426 * mips-opc.c: Include mips-formats.h.
427 (reg_0_map): New static array.
428 (decode_mips_operand): New function.
429 * micromips-opc.c: Remove <stdio.h> include. Include mips-formats.h.
430 (reg_0_map, reg_28_map, reg_29_map, reg_31_map, reg_m16_map)
431 (reg_mn_map, reg_q_map, reg_h_map1, reg_h_map2, int_b_map)
432 (int_c_map): New static arrays.
433 (decode_micromips_operand): New function.
434 * mips-dis.c (micromips_to_32_reg_b_map, micromips_to_32_reg_c_map)
435 (micromips_to_32_reg_d_map, micromips_to_32_reg_e_map)
436 (micromips_to_32_reg_f_map, micromips_to_32_reg_g_map)
437 (micromips_to_32_reg_h_map1, micromips_to_32_reg_h_map2)
438 (micromips_to_32_reg_l_map, micromips_to_32_reg_m_map)
439 (micromips_to_32_reg_n_map, micromips_to_32_reg_q_map)
440 (micromips_imm_b_map, micromips_imm_c_map): Delete.
441 (print_reg): New function.
442 (mips_print_arg_state): New structure.
443 (init_print_arg_state, print_insn_arg): New functions.
444 (print_insn_args): Change interface and use mips_operand structures.
445 Delete GET_OP_S. Move GET_OP definition to...
446 (print_insn_mips): ...here. Update the call to print_insn_args.
447 (print_insn_micromips): Use print_insn_args.
448
cc537e56
RS		 4492013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
450
451 * mips16-opc.c (mips16_opcodes): Use "I" for immediate operands
452 in macros.
453
7a5f87ce
RS		 4542013-07-14 Richard Sandiford <rdsandiford@googlemail.com>
455
456 * mips-opc.c (mips_builtin_opcodes): Use "S,T" rather than "V,T" for
457 ADDA.S, MULA.S and SUBA.S.
458
41741fa4
L		 4592013-07-08 H.J. Lu <hongjiu.lu@intel.com>
460
461 PR gas/13572
462 * i386-opc.tbl: Replace Xmmword with Qword on cvttps2pi.
463 * i386-tbl.h: Regenerated.
464
f2ae14a1
RS		 4652013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
466
467 * mips-opc.c (mips_builtin_opcodes): Remove o(b) macros. Move LD
468 and SD A(B) macros up.
469 * micromips-opc.c (micromips_opcodes): Likewise.
470
04c9d415
RS		 4712013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
472
473 * mips16-opc.c: Add entries for argumentless "entry" and "exit"
474 instructions.
475
5c324c16
RS		 4762013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
477
478 * mips-opc.c (mips_builtin_opcodes): Use "Q" for the INSN_5400
479 MDMX-like instructions.
480 * mips-dis.c (print_insn_arg): Use "$f" rather than "$v" when
481 printing "Q" operands for INSN_5400 instructions.
482
23e69e47
RS		 4832013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
484
485 * mips-opc.c (mips_builtin_opcodes): Use "+s" for "cins32" and
486 "+S" for "cins".
487 * mips-dis.c (print_mips_arg): Update "+s" and "+S" comments.
488 Combine cases.
489
27c5c572
RS		 4902013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
491
492 * mips-opc.c (mips_builtin_opcodes): Use "+i" rather than "a" for
493 "jalx".
494 * mips16-opc.c (mips16_opcodes): Likewise.
495 * micromips-opc.c (micromips_opcodes): Likewise.
496 * mips-dis.c (print_insn_args, print_mips16_insn_arg)
497 (print_insn_mips16): Handle "+i".
498 (print_insn_micromips): Likewise. Conditionally preserve the
499 ISA bit for "a" but not for "+i".
500
e76ff5ab
RS		 5012013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
502
503 * micromips-opc.c (WR_mhi): Rename to..
504 (WR_mh): ...this.
505 (micromips_opcodes): Update "movep" entry accordingly. Replace
506 "mh,mi" with "mh".
507 * mips-dis.c (micromips_to_32_reg_h_map): Rename to...
508 (micromips_to_32_reg_h_map1): ...this.
509 (micromips_to_32_reg_i_map): Rename to...
510 (micromips_to_32_reg_h_map2): ...this.
511 (print_micromips_insn): Remove "mi" case. Print both registers
512 in the pair for "mh".
513
fa7616a4
RS		 5142013-07-07 Richard Sandiford <rdsandiford@googlemail.com>
515
516 * mips-opc.c (mips_builtin_opcodes): Remove "+D" and "+T" entries.
517 * micromips-opc.c (micromips_opcodes): Likewise.
518 * mips-dis.c (print_insn_args, print_insn_micromips): Remove "+D"
519 and "+T" handling. Check for a "0" suffix when deciding whether to
520 use coprocessor 0 names. In that case, also check for ",H" selectors.
521
fb798c50
AK		 5222013-07-05 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
523
524 * s390-opc.c (J12_12, J24_24): New macros.
525 (INSTR_MII_UPI): Rename to INSTR_MII_UPP.
526 (MASK_MII_UPI): Rename to MASK_MII_UPP.
527 * s390-opc.txt: Rename MII_UPI to MII_UPP for bprp instruction.
528
58ae08f2
AM		 5292013-07-04 Alan Modra <amodra@gmail.com>
530
531 * ppc-opc.c (powerpc_opcodes): Add tdui, twui, tdu, twu, tui, tu.
532
b5e04c2b
NC		 5332013-06-26 Nick Clifton <nickc@redhat.com>
534
535 * rx-decode.opc (rx_decode_opcode): Check sd field as well as ss
536 field when checking for type 2 nop.
537 * rx-decode.c: Regenerate.
538
833794fc
MR		 5392013-06-25 Maciej W. Rozycki <macro@codesourcery.com>
540
541 * micromips-opc.c (micromips_opcodes): Add "jraddiusp", "jrc"
542 and "movep" macros.
543
1bbce132
MR		 5442013-06-24 Maciej W. Rozycki <macro@codesourcery.com>
545
546 * mips-dis.c (is_mips16_plt_tail): New function.
547 (print_insn_mips16): Handle MIPS16 PLT entry's GOT slot address
548 word.
549 (is_compressed_mode_p): Handle MIPS16/microMIPS PLT entries.
550
34c911a4
NC		 5512013-06-21 DJ Delorie <dj@redhat.com>
552
553 * msp430-decode.opc: New.
554 * msp430-decode.c: New/generated.
555 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add msp430-decode.c.
556 (MAINTAINER_CLEANFILES): Likewise.
557 Add rule to build msp430-decode.c frommsp430decode.opc
558 using the opc2c program.
559 * Makefile.in: Regenerate.
560 * configure.in: Add msp430-decode.lo to msp430 architecture files.
561 * configure: Regenerate.
562
b9eead84
YZ		 5632013-06-20 Yufeng Zhang <yufeng.zhang@arm.com>
564
565 * aarch64-dis.c (EMBEDDED_ENV): Remove the check on it.
566 (SYMTAB_AVAILABLE): Removed.
567 (#include "elf/aarch64.h): Ditto.
568
7f3c4072
CM		 5692013-06-17 Catherine Moore <clm@codesourcery.com>
570 Maciej W. Rozycki <macro@codesourcery.com>
571 Chao-Ying Fu <fu@mips.com>
572
573 * micromips-opc.c (EVA): Define.
574 (TLBINV): Define.
575 (micromips_opcodes): Add EVA opcodes.
576 * mips-dis.c (mips_arch_choices): Update for ASE_EVA.
577 (print_insn_args): Handle EVA offsets.
578 (print_insn_micromips): Likewise.
579 * mips-opc.c (EVA): Define.
580 (TLBINV): Define.
581 (mips_builtin_opcodes): Add EVA opcodes.
582
de40ceb6
AM		 5832013-06-17 Alan Modra <amodra@gmail.com>
584
585 * Makefile.am (mips-opc.lo): Add rules to create automatic
586 dependency files. Pass archdefs.
587 (micromips-opc.lo, mips16-opc.lo): Likewise.
588 * Makefile.in: Regenerate.
589
3531d549
DD		 5902013-06-14 DJ Delorie <dj@redhat.com>
591
592 * rx-decode.opc (rx_decode_opcode): Bit operations on
593 registers are 32-bit operations, not 8-bit operations.
594 * rx-decode.c: Regenerate.
595
ba92f7fb
CF		 5962013-06-13 Chao-ying Fu <Chao-ying.Fu@imgtec.com>
597
598 * micromips-opc.c (IVIRT): New define.
599 (IVIRT64): New define.
600 (micromips_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
601 tlbginv, tlbginvf, tlbgp, tlbgr, tlbgwi, tlbgwr VIRT instructions.
602
603 * mips-dis.c (print_insn_micromips): Handle mfgc0, mtgc0, dmfgc0,
604 dmtgc0 to print cp0 names.
605
9daf7bab
SL		 6062013-06-09 Sandra Loosemore <sandra@codesourcery.com>
607
608 * nios2-opc.c (nios2_builtin_opcodes): Give "trap" a type-"b"
609 argument.
610
d301a56b
RS		 6112013-06-08 Catherine Moore <clm@codesourcery.com>
612 Richard Sandiford <rdsandiford@googlemail.com>
613
614 * micromips-opc.c (D32, D33, MC): Update definitions.
615 (micromips_opcodes): Initialize ase field.
616 * mips-dis.c (mips_arch_choice): Add ase field.
617 (mips_arch_choices): Initialize ase field.
618 (set_default_mips_dis_options): Declare and setup mips_ase.
619 * mips-opc.c (M3D, SMT, MX, IVIRT, IVIRT64, D32, D33, D64,
620 MT32, MC): Update definitions.
621 (mips_builtin_opcodes): Initialize ase field.
622
a3dcb6c5
RS		 6232013-05-24 Richard Sandiford <rsandifo@linux.vnet.ibm.com>
624
625 * s390-opc.txt (flogr): Require a register pair destination.
626
6cf1d90c
AK		 6272013-05-23 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
628
629 * s390-opc.c: Fix length operand in RSL_LRDFU and RSL_LRDFEU
630 instruction format.
631
c77c0862
RS		 6322013-05-22 Jürgen Urban <JuergenUrban@gmx.de>
633
634 * mips-opc.c (mips_builtin_opcodes): Add R5900 VU0 instructions.
635
c0637f3a
PB		 6362013-05-20 Peter Bergner <bergner@vnet.ibm.com>
637
638 * ppc-dis.c (powerpc_init_dialect): Set default dialect to power8.
639 * ppc-opc.c (BHRBE, ST, SIX, PS, SXL, VXPS_MASK, XX1RB_MASK,
640 XLS_MASK, PPCVSX2): New defines.
641 (powerpc_opcodes) <bcdadd., bcdsub., bctar, bctar, bctarl, clrbhrb,
642 fmrgew, fmrgow, lqarx, lxsiwax, lxsiwzx, lxsspx, mfbhrbe,
643 mffprd, mffprwz, mfvrd, mfvrwz, mfvsrd, mfvsrwz, msgclrp, msgsndp,
644 mtfprd, mtfprwa, mtfprwz, mtsle, mtvrd, mtvrwa, mtvrwz, mtvsrd,
645 mtvsrwa, mtvsrwz, pbt., rfebb, stqcx., stxsiwx, stxsspx,
646 vaddcuq, vaddecuq, vaddeuqm, vaddudm, vadduqm, vbpermq, vcipher,
647 vcipherlast, vclzb, vclzd, vclzh, vclzw, vcmpequd, vcmpequd.,
648 vcmpgtsd, vcmpgtsd., vcmpgtud, vcmpgtud., veqv, vgbbd, vmaxsd,
649 vmaxud, vminsd, vminud, vmrgew, vmrgow, vmulesw, vmuleuw, vmulosw,
650 vmulouw, vmuluwm, vnand, vncipher, vncipherlast, vorc, vpermxor,
651 vpksdss, vpksdus, vpkudum, vpkudus, vpmsumb, vpmsumd, vpmsumh,
652 vpmsumw, vpopcntb, vpopcntd, vpopcnth, vpopcntw, vrld, vsbox,
653 vshasigmad, vshasigmaw, vsld, vsrad, vsrd, vsubcuq, vsubecuq,
654 vsubeuqm, vsubudm, vsubuqm, vupkhsw, vupklsw, waitasec, xsaddsp,
655 xscvdpspn, xscvspdpn, xscvsxdsp, xscvuxdsp, xsdivsp, xsmaddasp,
656 xsmaddmsp, xsmsubasp, xsmsubmsp, xsmulsp, xsnmaddasp, xsnmaddmsp,
657 xsnmsubasp, xsnmsubmsp, xsresp, xsrsp, xsrsqrtesp, xssqrtsp,
658 xssubsp, xxleqv, xxlnand, xxlorc>: New instructions.
659 <lxvx, stxvx>: New extended mnemonics.
660
4934fdaf
AM		 6612013-05-17 Alan Modra <amodra@gmail.com>
662
663 * ia64-raw.tbl: Replace non-ASCII char.
664 * ia64-waw.tbl: Likewise.
665 * ia64-asmtab.c: Regenerate.
666
6091d651
SE		 6672013-05-15 Saravanan Ekanathan <saravanan.ekanathan@amd.com>
668
669 * i386-gen.c (cpu_flag_init): Add CpuFSGSBase in CPU_BDVER3_FLAGS.
670 * i386-init.h: Regenerated.
671
d2865ed3
YZ		 6722013-05-13 Yufeng Zhang <yufeng.zhang@arm.com>
673
674 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Remove assertion.
675 * aarch64-opc.c (operand_general_constraint_met_p): Relax the range
676 check from [0, 255] to [-128, 255].
677
b015e599
AP		 6782013-05-09 Andrew Pinski <apinski@cavium.com>
679
680 * mips-dis.c (mips_arch_choices): Add INSN_VIRT to mips32r2.
681 Add INSN_VIRT and INSN_VIRT64 to mips64r2.
682 (parse_mips_dis_option): Handle the virt option.
683 (print_insn_args): Handle "+J".
684 (print_mips_disassembler_options): Print out message about virt64.
685 * mips-opc.c (IVIRT): New define.
686 (IVIRT64): New define.
687 (mips_builtin_opcodes): Add dmfgc0, dmtgc0, hypcall, mfgc0, mtgc0,
688 tlbgr, tlbgwi, tlbginv, tlbginvf, tlbgwr, tlbgp VIRT instructions.
689 Move rfe to the bottom as it conflicts with tlbgp.
690
9f0682fe
AM		 6912013-05-09 Alan Modra <amodra@gmail.com>
692
693 * ppc-opc.c (extract_vlesi): Properly sign extend.
694 (extract_vlensi): Likewise. Comment reason for setting invalid.
695
13761a11
NC		 6962013-05-02 Nick Clifton <nickc@redhat.com>
697
698 * msp430-dis.c: Add support for MSP430X instructions.
699
e3031850
SL		 7002013-04-24 Sandra Loosemore <sandra@codesourcery.com>
701
702 * nios2-opc.c (nios2_builtin_reg): Rename "fstatus" control register
703 to "eccinj".
704
17310e56
NC		 7052013-04-17 Wei-chen Wang <cole945@gmail.com>
706
707 PR binutils/15369
708 * cgen-dis.c (hash_insn_array): Use CGEN_CPU_INSN_ENDIAN instead
709 of CGEN_CPU_ENDIAN.
710 (hash_insns_list): Likewise.
711
731df338
JK		 7122013-04-10 Jan Kratochvil <jan.kratochvil@redhat.com>
713
714 * rl78-dis.c (print_insn_rl78): Use alternative form as a GCC false
715 warning workaround.
716
5f77db52
JB		 7172013-04-08 Jan Beulich <jbeulich@suse.com>
718
719 * i386-opc.tbl: Fold 64-bit and non-64-bit jecxz entries.
720 * i386-tbl.h: Re-generate.
721
0afd1215
DM		 7222013-04-06 David S. Miller <davem@davemloft.net>
723
724 * sparc-dis.c (compare_opcodes): When encountering multiple aliases
725 of an opcode, prefer the one with F_PREFERRED set.
726 * sparc-opc.c (sparc_opcodes): Add ldtw, ldtwa, sttw, sttwa,
727 lzcnt, flush with '[address]' syntax, and missing cbcond pseudo
728 ops. Make 64-bit VIS logical ops have "d" suffix in their names,
729 mark existing mnenomics as aliases. Add "cc" suffix to edge
730 instructions generating condition codes, mark existing mnenomics
731 as aliases. Add "fp" prefix to VIS compare instructions, mark
732 existing mnenomics as aliases.
733
41702d50
NC		 7342013-04-03 Nick Clifton <nickc@redhat.com>
735
736 * v850-dis.c (print_value): With V850_INVERSE_PCREL compute the
737 destination address by subtracting the operand from the current
738 address.
739 * v850-opc.c (insert_u16_loop): Disallow negative offsets. Store
740 a positive value in the insn.
741 (extract_u16_loop): Do not negate the returned value.
742 (D16_LOOP): Add V850_INVERSE_PCREL flag.
743
744 (ceilf.sw): Remove duplicate entry.
745 (cvtf.hs): New entry.
746 (cvtf.sh): Likewise.
747 (fmaf.s): Likewise.
748 (fmsf.s): Likewise.
749 (fnmaf.s): Likewise.
750 (fnmsf.s): Likewise.
751 (maddf.s): Restrict to E3V5 architectures.
752 (msubf.s): Likewise.
753 (nmaddf.s): Likewise.
754 (nmsubf.s): Likewise.
755
55cf16e1
L		 7562013-03-27 H.J. Lu <hongjiu.lu@intel.com>
757
758 * i386-dis.c (get_sib): Add the sizeflag argument. Properly
759 check address mode.
760 (print_insn): Pass sizeflag to get_sib.
761
51dcdd4d
NC		 7622013-03-27 Alexis Deruelle <alexis.deruelle@gmail.com>
763
764 PR binutils/15068
765 * tic6x-dis.c: Add support for displaying 16-bit insns.
766
795b8e6b
NC		 7672013-03-20 Alexis Deruelle <alexis.deruelle@gmail.com>
768
769 PR gas/15095
770 * tic6x-dis.c (print_insn_tic6x): Decode opcodes that have
771 individual msb and lsb halves in src1 & src2 fields. Discard the
772 src1 (lsb) value and only use src2 (msb), discarding bit 0, to
773 follow what Ti SDK does in that case as any value in the src1
774 field yields the same output with SDK disassembler.
775
314d60dd
ME		 7762013-03-12 Michael Eager <eager@eagercon.com>
777
795b8e6b 778 * opcodes/mips-dis.c (print_insn_args): Modify def of reg.
314d60dd 779
dad60f8e
SL		 7802013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
781
782 * nios2-opc.c (nios2_builtin_opcodes): Add entry for wrprs.
783
f5cb796a
SL		 7842013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
785
786 * nios2-opc.c (nios2_builtin_opcodes): Add entry for rdprs.
787
21fde85c
SL		 7882013-03-11 Sebastian Huber <sebastian.huber@embedded-brains.de>
789
790 * nios2-opc.c (nios2_builtin_regs): Add sstatus alias for ba register.
791
dd5181d5
KT		 7922013-03-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
793
794 * arm-dis.c (arm_opcodes): Add entries for CRC instructions.
795 (thumb32_opcodes): Likewise.
796 (print_insn_thumb32): Handle 'S' control char.
797
87a8d6cb
NC		 7982013-03-08 Yann Sionneau <yann.sionneau@gmail.com>
799
800 * lm32-desc.c: Regenerate.
801
99dce992
L		 8022013-03-01 H.J. Lu <hongjiu.lu@intel.com>
803
804 * i386-reg.tbl (riz): Add RegRex64.
805 * i386-tbl.h: Regenerated.
806
e60bb1dd
YZ		 8072013-02-28 Yufeng Zhang <yufeng.zhang@arm.com>
808
809 * aarch64-tbl.h (QL_I3SAMEW, QL_I3WWX): New macros.
810 (aarch64_feature_crc): New static.
811 (CRC): New macro.
812 (aarch64_opcode_table): Add entries for the crc32b, crc32h, crc32w,
813 crc32x, crc32cb, crc32ch, crc32cw and crc32cx instructions.
814 * aarch64-asm-2.c: Re-generate.
815 * aarch64-dis-2.c: Ditto.
816 * aarch64-opc-2.c: Ditto.
817
c7570fcd
AM		 8182013-02-27 Alan Modra <amodra@gmail.com>
819
820 * rl78-decode.opc (rl78_decode_opcode): Fix typo.
821 * rl78-decode.c: Regenerate.
822
151fa98f
NC		 8232013-02-25 Kaushik Phatak <Kaushik.Phatak@kpitcummins.com>
824
825 * rl78-decode.opc: Fix encoding of DIVWU insn.
826 * rl78-decode.c: Regenerate.
827
5c111e37
L		 8282013-02-19 H.J. Lu <hongjiu.lu@intel.com>
829
830 PR gas/15159
831 * i386-dis.c (rm_table): Add clac and stac to RM_0F01_REG_1.
832
833 * i386-gen.c (cpu_flag_init): Add CPU_SMAP_FLAGS.
834 (cpu_flags): Add CpuSMAP.
835
836 * i386-opc.h (CpuSMAP): New.
837 (i386_cpu_flags): Add cpusmap.
838
839 * i386-opc.tbl: Add clac and stac.
840
841 * i386-init.h: Regenerated.
842 * i386-tbl.h: Likewise.
843
9d1df426
NC		 8442013-02-15 Markos Chandras <markos.chandras@imgtec.com>
845
846 * metag-dis.c: Initialize outf->bytes_per_chunk to 4
847 which also makes the disassembler output be in little
848 endian like it should be.
849
a1ccaec9
YZ		 8502013-02-14 Yufeng Zhang <yufeng.zhang@arm.com>
851
852 * aarch64-opc.c (aarch64_prfops): Change unnamed operation 'name'
853 fields to NULL.
854 (aarch64_print_operand): Adjust the printing for AARCH64_OPND_PRFOP.
855
ef068ef4 8562013-02-13 Maciej W. Rozycki <macro@codesourcery.com>
5417f71e
MR		 857
858 * mips-dis.c (is_compressed_mode_p): Only match symbols from the
859 section disassembled.
860
6fe6ded9
RE		 8612013-02-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
862
863 * arm-dis.c: Update strht pattern.
864
0aa27725
RS		 8652013-02-09 Jürgen Urban <JuergenUrban@gmx.de>
866
867 * mips-opc.c (mips_builtin_opcodes): Enable l.d and s.d macros for
868 single-float. Disable ll, lld, sc and scd for EE. Disable the
869 trunc.w.s macro for EE.
870
36591ba1
SL		 8712013-02-06 Sandra Loosemore <sandra@codesourcery.com>
872 Andrew Jenner <andrew@codesourcery.com>
873
874 Based on patches from Altera Corporation.
875
876 * Makefile.am (TARGET_LIBOPCODES_CFILES): Add nios2-dis.c and
877 nios2-opc.c.
878 * Makefile.in: Regenerated.
879 * configure.in: Add case for bfd_nios2_arch.
880 * configure: Regenerated.
881 * disassemble.c (ARCH_nios2): Define.
882 (disassembler): Add case for bfd_arch_nios2.
883 * nios2-dis.c: New file.
884 * nios2-opc.c: New file.
885
545093a4
AM		 8862013-02-04 Alan Modra <amodra@gmail.com>
887
888 * po/POTFILES.in: Regenerate.
889 * rl78-decode.c: Regenerate.
890 * rx-decode.c: Regenerate.
891
e30181a5
YZ		 8922013-01-30 Yufeng Zhang <yufeng.zhang@arm.com>
893
894 * aarch64-tbl.h (aarch64_opcode_table): Flag sshll, sshll2, ushll and
895 ushll2 with F_HAS_ALIAS. Add entries for sxtl, sxtl2, uxtl and uxtl2.
896 * aarch64-asm.c (convert_xtl_to_shll): New function.
897 (convert_to_real): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
898 calling convert_xtl_to_shll.
899 * aarch64-dis.c (convert_shll_to_xtl): New function.
900 (convert_to_alias): Handle OP_SXTL, OP_SXTL2, OP_UXTL and OP_UXTL2 by
901 calling convert_shll_to_xtl.
902 * aarch64-gen.c: Update copyright year.
903 * aarch64-asm-2.c: Re-generate.
904 * aarch64-dis-2.c: Re-generate.
905 * aarch64-opc-2.c: Re-generate.
906
78c8d46c
NC		 9072013-01-24 Nick Clifton <nickc@redhat.com>
908
909 * v850-dis.c: Add support for e3v5 architecture.
910 * v850-opc.c: Likewise.
911
f5555712
YZ		 9122013-01-17 Yufeng Zhang <yufeng.zhang@arm.com>
913
914 * aarch64-asm.c (aarch64_ins_advsimd_imm_modified): Handle 8-bit MOVI.
915 * aarch64-dis.c (aarch64_ext_advsimd_imm_modified): Likewise.
916 * aarch64-opc.c (operand_general_constraint_met_p): For
78c8d46c 917 AARCH64_MOD_LSL, move the range check on the shift amount before the
f5555712
YZ		 918 alignment check; change to call set_sft_amount_out_of_range_error
919 instead of set_imm_out_of_range_error.
920 * aarch64-tbl.h (QL_SIMD_IMM_B): Replace NIL with LSL.
921 (aarch64_opcode_table): Remove the OP enumerator from the asimdimm
922 8-bit MOVI entry; change the 2nd operand from SIMD_IMM to
923 SIMD_IMM_SFT.
924
2f81ff92
L		 9252013-01-16 H.J. Lu <hongjiu.lu@intel.com>
926
927 * i386-gen.c (operand_type_init): Add OPERAND_TYPE_IMM32_64.
928
929 * i386-init.h: Regenerated.
930 * i386-tbl.h: Likewise.
931
dd42f060
NC		 9322013-01-15 Nick Clifton <nickc@redhat.com>
933
934 * v850-dis.c (get_operand_value): Sign extend V850E_IMMEDIATE
935 values.
936 * v850-opc.c (IMM16LO): Add V850_OPERAND_SIGNED attribute.
937
a4533ed8
NC		 9382013-01-14 Will Newton <will.newton@imgtec.com>
939
940 * metag-dis.c (REG_WIDTH): Increase to 64.
941
5817ffd1
PB		 9422013-01-10 Peter Bergner <bergner@vnet.ibm.com>
943
944 * ppc-dis.c (ppc_opts): Add "power8", "pwr8" and "htm" entries.
945 * ppc-opc.c (HTM_R, HTM_SI, XRTRB_MASK, XRTRARB_MASK, XRTLRARB_MASK,
946 XRTARARB_MASK, XRTBFRARB_MASK, XRCL, POWER8, PPCHTM): New defines.
947 (SH6): Update.
948 <"tabort.", "tabortdc.", "tabortdci.", "tabortwc.",
949 "tabortwci.", "tbegin.", "tcheck", "tend.", "trechkpt.",
950 "treclaim.", "tsr.">: Add POWER8 HTM opcodes.
951 <"tendall.", "tresume.", "tsuspend.">: Add POWER8 HTM extended opcodes.
952
a3c62988
NC		 9532013-01-10 Will Newton <will.newton@imgtec.com>
954
955 * Makefile.am: Add Meta.
956 * configure.in: Add Meta.
957 * disassemble.c: Add Meta support.
958 * metag-dis.c: New file.
959 * Makefile.in: Regenerate.
960 * configure: Regenerate.
961
73335eae
NC		 9622013-01-07 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
963
964 * cr16-dis.c (make_instruction): Rename to cr16_make_instruction.
965 (match_opcode): Rename to cr16_match_opcode.
966
e407c74b
NC		 9672013-01-04 Juergen Urban <JuergenUrban@gmx.de>
968
969 * mips-dis.c: Add names for CP0 registers of r5900.
970 * mips-opc.c: Add M_SQ_AB and M_LQ_AB to support larger range for
971 instructions sq and lq.
972 Add support for MIPS r5900 CPU.
973 Add support for 128 bit MMI (Multimedia Instructions).
974 Add support for EE instructions (Emotion Engine).
975 Disable unsupported floating point instructions (64 bit and
976 undefined compare operations).
977 Enable instructions of MIPS ISA IV which are supported by r5900.
978 Disable 64 bit co processor instructions.
979 Disable 64 bit multiplication and division instructions.
980 Disable instructions for co-processor 2 and 3, because these are
981 not supported (preparation for later VU0 support (Vector Unit)).
982 Disable cvt.w.s because this behaves like trunc.w.s and the
983 correct execution can't be ensured on r5900.
984 Add trunc.w.s using the opcode encoding of cvt.w.s on r5900. This
985 will confuse less developers and compilers.
986
a32c3ff8
NC		 9872013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
988
fb098a1e
YZ		 989 * aarch64-opc.c (aarch64_print_operand): Change to print
990 AARCH64_OPND_IMM_MOV in hexadecimal in the instruction and in decimal
991 in comment.
992 * aarch64-tbl.h (aarch64_opcode_table): Remove the 'F_PSEUDO' flag
993 from the opcode entries of OP_MOV_IMM_LOG, OP_MOV_IMM_WIDEN and
994 OP_MOV_IMM_WIDE.
995
9962013-01-04 Yufeng Zhang <yufeng.zhang@arm.com>
997
998 * aarch64-opc.c (aarch64_prfops): Update to support PLIL1KEEP,
999 PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP and PLIL3STRM.
a32c3ff8 1000
62658407
L		 10012013-01-02 H.J. Lu <hongjiu.lu@intel.com>
1002
1003 * i386-gen.c (process_copyright): Update copyright year to 2013.
1004
bab4becb 10052013-01-02 Kaushik Phatak <kaushik.phatak@kpitcummins.com>
5bf135a7 1006
bab4becb
NC		 1007 * cr16-dis.c (match_opcode,make_instruction): Remove static
1008 declaration.
1009 (dwordU,wordU): Moved typedefs to opcode/cr16.h
1010 (cr16_words,cr16_allWords,cr16_currInsn): Added prefix 'cr16_'.
5bf135a7 1011
bab4becb 1012For older changes see ChangeLog-2012
252b5132 1013\f
bab4becb 1014Copyright (C) 2013 Free Software Foundation, Inc.
752937aa
NC		 1015
1016Copying and distribution of this file, with or without modification,
1017are permitted in any medium without royalty provided the copyright
1018notice and this notice are preserved.
1019
252b5132 1020Local Variables:
2f6d2f85
NC		 1021mode: change-log
1022left-margin: 8
1023fill-column: 74
252b5132
RH		 1024version-control: never
1025End:
A mirror of the official binutils-gdb repository