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[binutils][aarch64] New SVE_Zm3_11_INDEX operand.
[thirdparty/binutils-gdb.git] / opcodes / aarch64-opc.c
CommitLineData
a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
82704155 2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
2d5d5a8f 25#include "bfd_stdint.h"
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
116adc27
MM		 297 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
298 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
e950b345 299 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 300 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 301 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
302 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 303 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 304 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
305 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
306 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
307 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
308 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 309 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 310 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
311 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 312 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
313 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
adccc507 314 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
116b6019 315 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
3bd82c86 316 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
116b6019 317 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 318 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 319 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
320 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 321 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 322 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
323 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
324 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
325 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 326 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
6456d318 327 { 22, 1 }, /* sz: 1-bit element size select. */
a06ea964
NC		 328};
329
330enum aarch64_operand_class
331aarch64_get_operand_class (enum aarch64_opnd type)
332{
333 return aarch64_operands[type].op_class;
334}
335
336const char *
337aarch64_get_operand_name (enum aarch64_opnd type)
338{
339 return aarch64_operands[type].name;
340}
341
342/* Get operand description string.
343 This is usually for the diagnosis purpose. */
344const char *
345aarch64_get_operand_desc (enum aarch64_opnd type)
346{
347 return aarch64_operands[type].desc;
348}
349
350/* Table of all conditional affixes. */
351const aarch64_cond aarch64_conds[16] =
352{
bb7eff52
RS		 353 {{"eq", "none"}, 0x0},
354 {{"ne", "any"}, 0x1},
355 {{"cs", "hs", "nlast"}, 0x2},
356 {{"cc", "lo", "ul", "last"}, 0x3},
357 {{"mi", "first"}, 0x4},
358 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 359 {{"vs"}, 0x6},
360 {{"vc"}, 0x7},
bb7eff52
RS		 361 {{"hi", "pmore"}, 0x8},
362 {{"ls", "plast"}, 0x9},
363 {{"ge", "tcont"}, 0xa},
364 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 365 {{"gt"}, 0xc},
366 {{"le"}, 0xd},
367 {{"al"}, 0xe},
368 {{"nv"}, 0xf},
369};
370
371const aarch64_cond *
372get_cond_from_value (aarch64_insn value)
373{
374 assert (value < 16);
375 return &aarch64_conds[(unsigned int) value];
376}
377
378const aarch64_cond *
379get_inverted_cond (const aarch64_cond *cond)
380{
381 return &aarch64_conds[cond->value ^ 0x1];
382}
383
384/* Table describing the operand extension/shifting operators; indexed by
385 enum aarch64_modifier_kind.
386
387 The value column provides the most common values for encoding modifiers,
388 which enables table-driven encoding/decoding for the modifiers. */
389const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
390{
391 {"none", 0x0},
392 {"msl", 0x0},
393 {"ror", 0x3},
394 {"asr", 0x2},
395 {"lsr", 0x1},
396 {"lsl", 0x0},
397 {"uxtb", 0x0},
398 {"uxth", 0x1},
399 {"uxtw", 0x2},
400 {"uxtx", 0x3},
401 {"sxtb", 0x4},
402 {"sxth", 0x5},
403 {"sxtw", 0x6},
404 {"sxtx", 0x7},
2442d846 405 {"mul", 0x0},
98907a70 406 {"mul vl", 0x0},
a06ea964
NC		 407 {NULL, 0},
408};
409
410enum aarch64_modifier_kind
411aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
412{
413 return desc - aarch64_operand_modifiers;
414}
415
416aarch64_insn
417aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
418{
419 return aarch64_operand_modifiers[kind].value;
420}
421
422enum aarch64_modifier_kind
423aarch64_get_operand_modifier_from_value (aarch64_insn value,
424 bfd_boolean extend_p)
425{
426 if (extend_p == TRUE)
427 return AARCH64_MOD_UXTB + value;
428 else
429 return AARCH64_MOD_LSL - value;
430}
431
432bfd_boolean
433aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
434{
435 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
436 ? TRUE : FALSE;
437}
438
439static inline bfd_boolean
440aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
441{
442 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
443 ? TRUE : FALSE;
444}
445
446const struct aarch64_name_value_pair aarch64_barrier_options[16] =
447{
448 { "#0x00", 0x0 },
449 { "oshld", 0x1 },
450 { "oshst", 0x2 },
451 { "osh", 0x3 },
452 { "#0x04", 0x4 },
453 { "nshld", 0x5 },
454 { "nshst", 0x6 },
455 { "nsh", 0x7 },
456 { "#0x08", 0x8 },
457 { "ishld", 0x9 },
458 { "ishst", 0xa },
459 { "ish", 0xb },
460 { "#0x0c", 0xc },
461 { "ld", 0xd },
462 { "st", 0xe },
463 { "sy", 0xf },
464};
465
9ed608f9
MW		 466/* Table describing the operands supported by the aliases of the HINT
467 instruction.
468
469 The name column is the operand that is accepted for the alias. The value
470 column is the hint number of the alias. The list of operands is terminated
471 by NULL in the name column. */
472
473const struct aarch64_name_value_pair aarch64_hint_options[] =
474{
ff605452
SD		 475 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
476 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
477 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
478 { "c", HINT_OPD_C }, /* BTI C. */
479 { "j", HINT_OPD_J }, /* BTI J. */
480 { "jc", HINT_OPD_JC }, /* BTI JC. */
481 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 482};
483
a32c3ff8 484/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 485 l -> level: 1-3
486 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 487#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 488const struct aarch64_name_value_pair aarch64_prfops[32] =
489{
490 { "pldl1keep", B(0, 1, 0) },
491 { "pldl1strm", B(0, 1, 1) },
492 { "pldl2keep", B(0, 2, 0) },
493 { "pldl2strm", B(0, 2, 1) },
494 { "pldl3keep", B(0, 3, 0) },
495 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 496 { NULL, 0x06 },
497 { NULL, 0x07 },
a32c3ff8
NC		 498 { "plil1keep", B(1, 1, 0) },
499 { "plil1strm", B(1, 1, 1) },
500 { "plil2keep", B(1, 2, 0) },
501 { "plil2strm", B(1, 2, 1) },
502 { "plil3keep", B(1, 3, 0) },
503 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 504 { NULL, 0x0e },
505 { NULL, 0x0f },
a32c3ff8
NC		 506 { "pstl1keep", B(2, 1, 0) },
507 { "pstl1strm", B(2, 1, 1) },
508 { "pstl2keep", B(2, 2, 0) },
509 { "pstl2strm", B(2, 2, 1) },
510 { "pstl3keep", B(2, 3, 0) },
511 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 512 { NULL, 0x16 },
513 { NULL, 0x17 },
514 { NULL, 0x18 },
515 { NULL, 0x19 },
516 { NULL, 0x1a },
517 { NULL, 0x1b },
518 { NULL, 0x1c },
519 { NULL, 0x1d },
520 { NULL, 0x1e },
521 { NULL, 0x1f },
a06ea964
NC		 522};
523#undef B
524\f
525/* Utilities on value constraint. */
526
527static inline int
528value_in_range_p (int64_t value, int low, int high)
529{
530 return (value >= low && value <= high) ? 1 : 0;
531}
532
98907a70 533/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 534static inline int
535value_aligned_p (int64_t value, int align)
536{
98907a70 537 return (value % align) == 0;
a06ea964
NC		 538}
539
540/* A signed value fits in a field. */
541static inline int
542value_fit_signed_field_p (int64_t value, unsigned width)
543{
544 assert (width < 32);
545 if (width < sizeof (value) * 8)
546 {
547 int64_t lim = (int64_t)1 << (width - 1);
548 if (value >= -lim && value < lim)
549 return 1;
550 }
551 return 0;
552}
553
554/* An unsigned value fits in a field. */
555static inline int
556value_fit_unsigned_field_p (int64_t value, unsigned width)
557{
558 assert (width < 32);
559 if (width < sizeof (value) * 8)
560 {
561 int64_t lim = (int64_t)1 << width;
562 if (value >= 0 && value < lim)
563 return 1;
564 }
565 return 0;
566}
567
568/* Return 1 if OPERAND is SP or WSP. */
569int
570aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
571{
572 return ((aarch64_get_operand_class (operand->type)
573 == AARCH64_OPND_CLASS_INT_REG)
574 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
575 && operand->reg.regno == 31);
576}
577
578/* Return 1 if OPERAND is XZR or WZP. */
579int
580aarch64_zero_register_p (const aarch64_opnd_info *operand)
581{
582 return ((aarch64_get_operand_class (operand->type)
583 == AARCH64_OPND_CLASS_INT_REG)
584 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
585 && operand->reg.regno == 31);
586}
587
588/* Return true if the operand *OPERAND that has the operand code
589 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
590 qualified by the qualifier TARGET. */
591
592static inline int
593operand_also_qualified_p (const struct aarch64_opnd_info *operand,
594 aarch64_opnd_qualifier_t target)
595{
596 switch (operand->qualifier)
597 {
598 case AARCH64_OPND_QLF_W:
599 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
600 return 1;
601 break;
602 case AARCH64_OPND_QLF_X:
603 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
604 return 1;
605 break;
606 case AARCH64_OPND_QLF_WSP:
607 if (target == AARCH64_OPND_QLF_W
608 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
609 return 1;
610 break;
611 case AARCH64_OPND_QLF_SP:
612 if (target == AARCH64_OPND_QLF_X
613 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
614 return 1;
615 break;
616 default:
617 break;
618 }
619
620 return 0;
621}
622
623/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
624 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
625
626 Return NIL if more than one expected qualifiers are found. */
627
628aarch64_opnd_qualifier_t
629aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
630 int idx,
631 const aarch64_opnd_qualifier_t known_qlf,
632 int known_idx)
633{
634 int i, saved_i;
635
636 /* Special case.
637
638 When the known qualifier is NIL, we have to assume that there is only
639 one qualifier sequence in the *QSEQ_LIST and return the corresponding
640 qualifier directly. One scenario is that for instruction
641 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
642 which has only one possible valid qualifier sequence
643 NIL, S_D
644 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
645 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
646
647 Because the qualifier NIL has dual roles in the qualifier sequence:
648 it can mean no qualifier for the operand, or the qualifer sequence is
649 not in use (when all qualifiers in the sequence are NILs), we have to
650 handle this special case here. */
651 if (known_qlf == AARCH64_OPND_NIL)
652 {
653 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
654 return qseq_list[0][idx];
655 }
656
657 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
658 {
659 if (qseq_list[i][known_idx] == known_qlf)
660 {
661 if (saved_i != -1)
662 /* More than one sequences are found to have KNOWN_QLF at
663 KNOWN_IDX. */
664 return AARCH64_OPND_NIL;
665 saved_i = i;
666 }
667 }
668
669 return qseq_list[saved_i][idx];
670}
671
672enum operand_qualifier_kind
673{
674 OQK_NIL,
675 OQK_OPD_VARIANT,
676 OQK_VALUE_IN_RANGE,
677 OQK_MISC,
678};
679
680/* Operand qualifier description. */
681struct operand_qualifier_data
682{
683 /* The usage of the three data fields depends on the qualifier kind. */
684 int data0;
685 int data1;
686 int data2;
687 /* Description. */
688 const char *desc;
689 /* Kind. */
690 enum operand_qualifier_kind kind;
691};
692
693/* Indexed by the operand qualifier enumerators. */
694struct operand_qualifier_data aarch64_opnd_qualifiers[] =
695{
696 {0, 0, 0, "NIL", OQK_NIL},
697
698 /* Operand variant qualifiers.
699 First 3 fields:
700 element size, number of elements and common value for encoding. */
701
702 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
703 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
704 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
705 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
706
707 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
708 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
709 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
710 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
711 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 712 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964 713
a3b3345a 714 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 715 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
716 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 717 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 718 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
719 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
720 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
721 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
722 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
723 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
724 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
725
d50c751e
RS		 726 {0, 0, 0, "z", OQK_OPD_VARIANT},
727 {0, 0, 0, "m", OQK_OPD_VARIANT},
728
fb3265b3
SD		 729 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
730 {16, 0, 0, "tag", OQK_OPD_VARIANT},
731
a06ea964
NC		 732 /* Qualifiers constraining the value range.
733 First 3 fields:
734 Lower bound, higher bound, unused. */
735
a6a51754 736 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 737 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
738 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
739 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
740 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
741 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
742 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
743
744 /* Qualifiers for miscellaneous purpose.
745 First 3 fields:
746 unused, unused and unused. */
747
748 {0, 0, 0, "lsl", 0},
749 {0, 0, 0, "msl", 0},
750
751 {0, 0, 0, "retrieving", 0},
752};
753
754static inline bfd_boolean
755operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
756{
757 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
758 ? TRUE : FALSE;
759}
760
761static inline bfd_boolean
762qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
763{
764 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
765 ? TRUE : FALSE;
766}
767
768const char*
769aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
770{
771 return aarch64_opnd_qualifiers[qualifier].desc;
772}
773
774/* Given an operand qualifier, return the expected data element size
775 of a qualified operand. */
776unsigned char
777aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
778{
779 assert (operand_variant_qualifier_p (qualifier) == TRUE);
780 return aarch64_opnd_qualifiers[qualifier].data0;
781}
782
783unsigned char
784aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
785{
786 assert (operand_variant_qualifier_p (qualifier) == TRUE);
787 return aarch64_opnd_qualifiers[qualifier].data1;
788}
789
790aarch64_insn
791aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
792{
793 assert (operand_variant_qualifier_p (qualifier) == TRUE);
794 return aarch64_opnd_qualifiers[qualifier].data2;
795}
796
797static int
798get_lower_bound (aarch64_opnd_qualifier_t qualifier)
799{
800 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
801 return aarch64_opnd_qualifiers[qualifier].data0;
802}
803
804static int
805get_upper_bound (aarch64_opnd_qualifier_t qualifier)
806{
807 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
808 return aarch64_opnd_qualifiers[qualifier].data1;
809}
810
811#ifdef DEBUG_AARCH64
812void
813aarch64_verbose (const char *str, ...)
814{
815 va_list ap;
816 va_start (ap, str);
817 printf ("#### ");
818 vprintf (str, ap);
819 printf ("\n");
820 va_end (ap);
821}
822
823static inline void
824dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
825{
826 int i;
827 printf ("#### \t");
828 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
829 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
830 printf ("\n");
831}
832
833static void
834dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
835 const aarch64_opnd_qualifier_t *qualifier)
836{
837 int i;
838 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
839
840 aarch64_verbose ("dump_match_qualifiers:");
841 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
842 curr[i] = opnd[i].qualifier;
843 dump_qualifier_sequence (curr);
844 aarch64_verbose ("against");
845 dump_qualifier_sequence (qualifier);
846}
847#endif /* DEBUG_AARCH64 */
848
a68f4cd2
TC		 849/* This function checks if the given instruction INSN is a destructive
850 instruction based on the usage of the registers. It does not recognize
851 unary destructive instructions. */
852bfd_boolean
853aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
854{
855 int i = 0;
856 const enum aarch64_opnd *opnds = opcode->operands;
857
858 if (opnds[0] == AARCH64_OPND_NIL)
859 return FALSE;
860
861 while (opnds[++i] != AARCH64_OPND_NIL)
862 if (opnds[i] == opnds[0])
863 return TRUE;
864
865 return FALSE;
866}
867
a06ea964
NC		 868/* TODO improve this, we can have an extra field at the runtime to
869 store the number of operands rather than calculating it every time. */
870
871int
872aarch64_num_of_operands (const aarch64_opcode *opcode)
873{
874 int i = 0;
875 const enum aarch64_opnd *opnds = opcode->operands;
876 while (opnds[i++] != AARCH64_OPND_NIL)
877 ;
878 --i;
879 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
880 return i;
881}
882
883/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
884 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
885
886 N.B. on the entry, it is very likely that only some operands in *INST
887 have had their qualifiers been established.
888
889 If STOP_AT is not -1, the function will only try to match
890 the qualifier sequence for operands before and including the operand
891 of index STOP_AT; and on success *RET will only be filled with the first
892 (STOP_AT+1) qualifiers.
893
894 A couple examples of the matching algorithm:
895
896 X,W,NIL should match
897 X,W,NIL
898
899 NIL,NIL should match
900 X ,NIL
901
902 Apart from serving the main encoding routine, this can also be called
903 during or after the operand decoding. */
904
905int
906aarch64_find_best_match (const aarch64_inst *inst,
907 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
908 int stop_at, aarch64_opnd_qualifier_t *ret)
909{
910 int found = 0;
911 int i, num_opnds;
912 const aarch64_opnd_qualifier_t *qualifiers;
913
914 num_opnds = aarch64_num_of_operands (inst->opcode);
915 if (num_opnds == 0)
916 {
917 DEBUG_TRACE ("SUCCEED: no operand");
918 return 1;
919 }
920
921 if (stop_at < 0 || stop_at >= num_opnds)
922 stop_at = num_opnds - 1;
923
924 /* For each pattern. */
925 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
926 {
927 int j;
928 qualifiers = *qualifiers_list;
929
930 /* Start as positive. */
931 found = 1;
932
933 DEBUG_TRACE ("%d", i);
934#ifdef DEBUG_AARCH64
935 if (debug_dump)
936 dump_match_qualifiers (inst->operands, qualifiers);
937#endif
938
939 /* Most opcodes has much fewer patterns in the list.
940 First NIL qualifier indicates the end in the list. */
941 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
942 {
943 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
944 if (i)
945 found = 0;
946 break;
947 }
948
949 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
950 {
951 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
952 {
953 /* Either the operand does not have qualifier, or the qualifier
954 for the operand needs to be deduced from the qualifier
955 sequence.
956 In the latter case, any constraint checking related with
957 the obtained qualifier should be done later in
958 operand_general_constraint_met_p. */
959 continue;
960 }
961 else if (*qualifiers != inst->operands[j].qualifier)
962 {
963 /* Unless the target qualifier can also qualify the operand
964 (which has already had a non-nil qualifier), non-equal
965 qualifiers are generally un-matched. */
966 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
967 continue;
968 else
969 {
970 found = 0;
971 break;
972 }
973 }
974 else
975 continue; /* Equal qualifiers are certainly matched. */
976 }
977
978 /* Qualifiers established. */
979 if (found == 1)
980 break;
981 }
982
983 if (found == 1)
984 {
985 /* Fill the result in *RET. */
986 int j;
987 qualifiers = *qualifiers_list;
988
989 DEBUG_TRACE ("complete qualifiers using list %d", i);
990#ifdef DEBUG_AARCH64
991 if (debug_dump)
992 dump_qualifier_sequence (qualifiers);
993#endif
994
995 for (j = 0; j <= stop_at; ++j, ++qualifiers)
996 ret[j] = *qualifiers;
997 for (; j < AARCH64_MAX_OPND_NUM; ++j)
998 ret[j] = AARCH64_OPND_QLF_NIL;
999
1000 DEBUG_TRACE ("SUCCESS");
1001 return 1;
1002 }
1003
1004 DEBUG_TRACE ("FAIL");
1005 return 0;
1006}
1007
1008/* Operand qualifier matching and resolving.
1009
1010 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1011 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1012
1013 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1014 succeeds. */
1015
1016static int
1017match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1018{
4989adac 1019 int i, nops;
a06ea964
NC		 1020 aarch64_opnd_qualifier_seq_t qualifiers;
1021
1022 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1023 qualifiers))
1024 {
1025 DEBUG_TRACE ("matching FAIL");
1026 return 0;
1027 }
1028
4989adac
RS		 1029 if (inst->opcode->flags & F_STRICT)
1030 {
1031 /* Require an exact qualifier match, even for NIL qualifiers. */
1032 nops = aarch64_num_of_operands (inst->opcode);
1033 for (i = 0; i < nops; ++i)
1034 if (inst->operands[i].qualifier != qualifiers[i])
1035 return FALSE;
1036 }
1037
a06ea964
NC		 1038 /* Update the qualifiers. */
1039 if (update_p == TRUE)
1040 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1041 {
1042 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1043 break;
1044 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1045 "update %s with %s for operand %d",
1046 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1047 aarch64_get_qualifier_name (qualifiers[i]), i);
1048 inst->operands[i].qualifier = qualifiers[i];
1049 }
1050
1051 DEBUG_TRACE ("matching SUCCESS");
1052 return 1;
1053}
1054
1055/* Return TRUE if VALUE is a wide constant that can be moved into a general
1056 register by MOVZ.
1057
1058 IS32 indicates whether value is a 32-bit immediate or not.
1059 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1060 amount will be returned in *SHIFT_AMOUNT. */
1061
1062bfd_boolean
1063aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1064{
1065 int amount;
1066
1067 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1068
1069 if (is32)
1070 {
1071 /* Allow all zeros or all ones in top 32-bits, so that
1072 32-bit constant expressions like ~0x80000000 are
1073 permitted. */
1074 uint64_t ext = value;
1075 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1076 /* Immediate out of range. */
1077 return FALSE;
1078 value &= (int64_t) 0xffffffff;
1079 }
1080
1081 /* first, try movz then movn */
1082 amount = -1;
1083 if ((value & ((int64_t) 0xffff << 0)) == value)
1084 amount = 0;
1085 else if ((value & ((int64_t) 0xffff << 16)) == value)
1086 amount = 16;
1087 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1088 amount = 32;
1089 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1090 amount = 48;
1091
1092 if (amount == -1)
1093 {
1094 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1095 return FALSE;
1096 }
1097
1098 if (shift_amount != NULL)
1099 *shift_amount = amount;
1100
1101 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1102
1103 return TRUE;
1104}
1105
1106/* Build the accepted values for immediate logical SIMD instructions.
1107
1108 The standard encodings of the immediate value are:
1109 N imms immr SIMD size R S
1110 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1111 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1112 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1113 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1114 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1115 0 11110s 00000r 2 UInt(r) UInt(s)
1116 where all-ones value of S is reserved.
1117
1118 Let's call E the SIMD size.
1119
1120 The immediate value is: S+1 bits '1' rotated to the right by R.
1121
1122 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1123 (remember S != E - 1). */
1124
1125#define TOTAL_IMM_NB 5334
1126
1127typedef struct
1128{
1129 uint64_t imm;
1130 aarch64_insn encoding;
1131} simd_imm_encoding;
1132
1133static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1134
1135static int
1136simd_imm_encoding_cmp(const void *i1, const void *i2)
1137{
1138 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1139 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1140
1141 if (imm1->imm < imm2->imm)
1142 return -1;
1143 if (imm1->imm > imm2->imm)
1144 return +1;
1145 return 0;
1146}
1147
1148/* immediate bitfield standard encoding
1149 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1150 1 ssssss rrrrrr 64 rrrrrr ssssss
1151 0 0sssss 0rrrrr 32 rrrrr sssss
1152 0 10ssss 00rrrr 16 rrrr ssss
1153 0 110sss 000rrr 8 rrr sss
1154 0 1110ss 0000rr 4 rr ss
1155 0 11110s 00000r 2 r s */
1156static inline int
1157encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1158{
1159 return (is64 << 12) | (r << 6) | s;
1160}
1161
1162static void
1163build_immediate_table (void)
1164{
1165 uint32_t log_e, e, s, r, s_mask;
1166 uint64_t mask, imm;
1167 int nb_imms;
1168 int is64;
1169
1170 nb_imms = 0;
1171 for (log_e = 1; log_e <= 6; log_e++)
1172 {
1173 /* Get element size. */
1174 e = 1u << log_e;
1175 if (log_e == 6)
1176 {
1177 is64 = 1;
1178 mask = 0xffffffffffffffffull;
1179 s_mask = 0;
1180 }
1181 else
1182 {
1183 is64 = 0;
1184 mask = (1ull << e) - 1;
1185 /* log_e s_mask
1186 1 ((1 << 4) - 1) << 2 = 111100
1187 2 ((1 << 3) - 1) << 3 = 111000
1188 3 ((1 << 2) - 1) << 4 = 110000
1189 4 ((1 << 1) - 1) << 5 = 100000
1190 5 ((1 << 0) - 1) << 6 = 000000 */
1191 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1192 }
1193 for (s = 0; s < e - 1; s++)
1194 for (r = 0; r < e; r++)
1195 {
1196 /* s+1 consecutive bits to 1 (s < 63) */
1197 imm = (1ull << (s + 1)) - 1;
1198 /* rotate right by r */
1199 if (r != 0)
1200 imm = (imm >> r) | ((imm << (e - r)) & mask);
1201 /* replicate the constant depending on SIMD size */
1202 switch (log_e)
1203 {
1204 case 1: imm = (imm << 2) | imm;
1a0670f3 1205 /* Fall through. */
a06ea964 1206 case 2: imm = (imm << 4) | imm;
1a0670f3 1207 /* Fall through. */
a06ea964 1208 case 3: imm = (imm << 8) | imm;
1a0670f3 1209 /* Fall through. */
a06ea964 1210 case 4: imm = (imm << 16) | imm;
1a0670f3 1211 /* Fall through. */
a06ea964 1212 case 5: imm = (imm << 32) | imm;
1a0670f3 1213 /* Fall through. */
a06ea964
NC		 1214 case 6: break;
1215 default: abort ();
1216 }
1217 simd_immediates[nb_imms].imm = imm;
1218 simd_immediates[nb_imms].encoding =
1219 encode_immediate_bitfield(is64, s | s_mask, r);
1220 nb_imms++;
1221 }
1222 }
1223 assert (nb_imms == TOTAL_IMM_NB);
1224 qsort(simd_immediates, nb_imms,
1225 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1226}
1227
1228/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1229 be accepted by logical (immediate) instructions
1230 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1231
42408347 1232 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1233 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1234 VALUE will be returned in *ENCODING. */
1235
1236bfd_boolean
42408347 1237aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1238{
1239 simd_imm_encoding imm_enc;
1240 const simd_imm_encoding *imm_encoding;
1241 static bfd_boolean initialized = FALSE;
42408347
RS		 1242 uint64_t upper;
1243 int i;
a06ea964 1244
957f6b39
TC		 1245 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1246 value, esize);
a06ea964 1247
535b785f 1248 if (!initialized)
a06ea964
NC		 1249 {
1250 build_immediate_table ();
1251 initialized = TRUE;
1252 }
1253
42408347
RS		 1254 /* Allow all zeros or all ones in top bits, so that
1255 constant expressions like ~1 are permitted. */
1256 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1257 if ((value & ~upper) != value && (value | upper) != value)
1258 return FALSE;
7e105031 1259
42408347
RS		 1260 /* Replicate to a full 64-bit value. */
1261 value &= ~upper;
1262 for (i = esize * 8; i < 64; i *= 2)
1263 value |= (value << i);
a06ea964
NC		 1264
1265 imm_enc.imm = value;
1266 imm_encoding = (const simd_imm_encoding *)
1267 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1268 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1269 if (imm_encoding == NULL)
1270 {
1271 DEBUG_TRACE ("exit with FALSE");
1272 return FALSE;
1273 }
1274 if (encoding != NULL)
1275 *encoding = imm_encoding->encoding;
1276 DEBUG_TRACE ("exit with TRUE");
1277 return TRUE;
1278}
1279
1280/* If 64-bit immediate IMM is in the format of
1281 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1282 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1283 of value "abcdefgh". Otherwise return -1. */
1284int
1285aarch64_shrink_expanded_imm8 (uint64_t imm)
1286{
1287 int i, ret;
1288 uint32_t byte;
1289
1290 ret = 0;
1291 for (i = 0; i < 8; i++)
1292 {
1293 byte = (imm >> (8 * i)) & 0xff;
1294 if (byte == 0xff)
1295 ret |= 1 << i;
1296 else if (byte != 0x00)
1297 return -1;
1298 }
1299 return ret;
1300}
1301
1302/* Utility inline functions for operand_general_constraint_met_p. */
1303
1304static inline void
1305set_error (aarch64_operand_error *mismatch_detail,
1306 enum aarch64_operand_error_kind kind, int idx,
1307 const char* error)
1308{
1309 if (mismatch_detail == NULL)
1310 return;
1311 mismatch_detail->kind = kind;
1312 mismatch_detail->index = idx;
1313 mismatch_detail->error = error;
1314}
1315
4e50d5f8
YZ		 1316static inline void
1317set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1318 const char* error)
1319{
1320 if (mismatch_detail == NULL)
1321 return;
1322 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1323}
1324
a06ea964
NC		 1325static inline void
1326set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1327 int idx, int lower_bound, int upper_bound,
1328 const char* error)
1329{
1330 if (mismatch_detail == NULL)
1331 return;
1332 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1333 mismatch_detail->data[0] = lower_bound;
1334 mismatch_detail->data[1] = upper_bound;
1335}
1336
1337static inline void
1338set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1339 int idx, int lower_bound, int upper_bound)
1340{
1341 if (mismatch_detail == NULL)
1342 return;
1343 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1344 _("immediate value"));
1345}
1346
1347static inline void
1348set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1349 int idx, int lower_bound, int upper_bound)
1350{
1351 if (mismatch_detail == NULL)
1352 return;
1353 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1354 _("immediate offset"));
1355}
1356
1357static inline void
1358set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1359 int idx, int lower_bound, int upper_bound)
1360{
1361 if (mismatch_detail == NULL)
1362 return;
1363 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1364 _("register number"));
1365}
1366
1367static inline void
1368set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1369 int idx, int lower_bound, int upper_bound)
1370{
1371 if (mismatch_detail == NULL)
1372 return;
1373 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1374 _("register element index"));
1375}
1376
1377static inline void
1378set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1379 int idx, int lower_bound, int upper_bound)
1380{
1381 if (mismatch_detail == NULL)
1382 return;
1383 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1384 _("shift amount"));
1385}
1386
2442d846
RS		 1387/* Report that the MUL modifier in operand IDX should be in the range
1388 [LOWER_BOUND, UPPER_BOUND]. */
1389static inline void
1390set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1391 int idx, int lower_bound, int upper_bound)
1392{
1393 if (mismatch_detail == NULL)
1394 return;
1395 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1396 _("multiplier"));
1397}
1398
a06ea964
NC		 1399static inline void
1400set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1401 int alignment)
1402{
1403 if (mismatch_detail == NULL)
1404 return;
1405 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1406 mismatch_detail->data[0] = alignment;
1407}
1408
1409static inline void
1410set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1411 int expected_num)
1412{
1413 if (mismatch_detail == NULL)
1414 return;
1415 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1416 mismatch_detail->data[0] = expected_num;
1417}
1418
1419static inline void
1420set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1421 const char* error)
1422{
1423 if (mismatch_detail == NULL)
1424 return;
1425 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1426}
1427
1428/* General constraint checking based on operand code.
1429
1430 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1431 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1432
1433 This function has to be called after the qualifiers for all operands
1434 have been resolved.
1435
1436 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1437 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1438 of error message during the disassembling where error message is not
1439 wanted. We avoid the dynamic construction of strings of error messages
1440 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1441 use a combination of error code, static string and some integer data to
1442 represent an error. */
1443
1444static int
1445operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1446 enum aarch64_opnd type,
1447 const aarch64_opcode *opcode,
1448 aarch64_operand_error *mismatch_detail)
1449{
e950b345 1450 unsigned num, modifiers, shift;
a06ea964 1451 unsigned char size;
4df068de 1452 int64_t imm, min_value, max_value;
e950b345 1453 uint64_t uvalue, mask;
a06ea964
NC		 1454 const aarch64_opnd_info *opnd = opnds + idx;
1455 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1456
1457 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1458
1459 switch (aarch64_operands[type].op_class)
1460 {
1461 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1462 /* Check pair reg constraints for cas* instructions. */
1463 if (type == AARCH64_OPND_PAIRREG)
1464 {
1465 assert (idx == 1 || idx == 3);
1466 if (opnds[idx - 1].reg.regno % 2 != 0)
1467 {
1468 set_syntax_error (mismatch_detail, idx - 1,
1469 _("reg pair must start from even reg"));
1470 return 0;
1471 }
1472 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1473 {
1474 set_syntax_error (mismatch_detail, idx,
1475 _("reg pair must be contiguous"));
1476 return 0;
1477 }
1478 break;
1479 }
1480
a06ea964
NC		 1481 /* <Xt> may be optional in some IC and TLBI instructions. */
1482 if (type == AARCH64_OPND_Rt_SYS)
1483 {
1484 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1485 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1486 if (opnds[1].present
1487 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1488 {
1489 set_other_error (mismatch_detail, idx, _("extraneous register"));
1490 return 0;
1491 }
ea2deeec
MW		 1492 if (!opnds[1].present
1493 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1494 {
1495 set_other_error (mismatch_detail, idx, _("missing register"));
1496 return 0;
1497 }
1498 }
1499 switch (qualifier)
1500 {
1501 case AARCH64_OPND_QLF_WSP:
1502 case AARCH64_OPND_QLF_SP:
1503 if (!aarch64_stack_pointer_p (opnd))
1504 {
1505 set_other_error (mismatch_detail, idx,
1506 _("stack pointer register expected"));
1507 return 0;
1508 }
1509 break;
1510 default:
1511 break;
1512 }
1513 break;
1514
f11ad6bc
RS		 1515 case AARCH64_OPND_CLASS_SVE_REG:
1516 switch (type)
1517 {
582e12bf
RS		 1518 case AARCH64_OPND_SVE_Zm3_INDEX:
1519 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 1520 case AARCH64_OPND_SVE_Zm3_11_INDEX:
582e12bf
RS		 1521 case AARCH64_OPND_SVE_Zm4_INDEX:
1522 size = get_operand_fields_width (get_operand_from_code (type));
1523 shift = get_operand_specific_data (&aarch64_operands[type]);
1524 mask = (1 << shift) - 1;
1525 if (opnd->reg.regno > mask)
1526 {
1527 assert (mask == 7 || mask == 15);
1528 set_other_error (mismatch_detail, idx,
1529 mask == 15
1530 ? _("z0-z15 expected")
1531 : _("z0-z7 expected"));
1532 return 0;
1533 }
1534 mask = (1 << (size - shift)) - 1;
1535 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1536 {
1537 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1538 return 0;
1539 }
1540 break;
1541
f11ad6bc
RS		 1542 case AARCH64_OPND_SVE_Zn_INDEX:
1543 size = aarch64_get_qualifier_esize (opnd->qualifier);
1544 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1545 {
1546 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1547 0, 64 / size - 1);
1548 return 0;
1549 }
1550 break;
1551
1552 case AARCH64_OPND_SVE_ZnxN:
1553 case AARCH64_OPND_SVE_ZtxN:
1554 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1555 {
1556 set_other_error (mismatch_detail, idx,
1557 _("invalid register list"));
1558 return 0;
1559 }
1560 break;
1561
1562 default:
1563 break;
1564 }
1565 break;
1566
1567 case AARCH64_OPND_CLASS_PRED_REG:
1568 if (opnd->reg.regno >= 8
1569 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1570 {
1571 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1572 return 0;
1573 }
1574 break;
1575
68a64283
YZ		 1576 case AARCH64_OPND_CLASS_COND:
1577 if (type == AARCH64_OPND_COND1
1578 && (opnds[idx].cond->value & 0xe) == 0xe)
1579 {
1580 /* Not allow AL or NV. */
1581 set_syntax_error (mismatch_detail, idx, NULL);
1582 }
1583 break;
1584
a06ea964
NC		 1585 case AARCH64_OPND_CLASS_ADDRESS:
1586 /* Check writeback. */
1587 switch (opcode->iclass)
1588 {
1589 case ldst_pos:
1590 case ldst_unscaled:
1591 case ldstnapair_offs:
1592 case ldstpair_off:
1593 case ldst_unpriv:
1594 if (opnd->addr.writeback == 1)
1595 {
4e50d5f8
YZ		 1596 set_syntax_error (mismatch_detail, idx,
1597 _("unexpected address writeback"));
a06ea964
NC		 1598 return 0;
1599 }
1600 break;
3f06e550
SN		 1601 case ldst_imm10:
1602 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1603 {
1604 set_syntax_error (mismatch_detail, idx,
1605 _("unexpected address writeback"));
1606 return 0;
1607 }
1608 break;
a06ea964
NC		 1609 case ldst_imm9:
1610 case ldstpair_indexed:
1611 case asisdlsep:
1612 case asisdlsop:
1613 if (opnd->addr.writeback == 0)
1614 {
4e50d5f8
YZ		 1615 set_syntax_error (mismatch_detail, idx,
1616 _("address writeback expected"));
a06ea964
NC		 1617 return 0;
1618 }
1619 break;
1620 default:
1621 assert (opnd->addr.writeback == 0);
1622 break;
1623 }
1624 switch (type)
1625 {
1626 case AARCH64_OPND_ADDR_SIMM7:
1627 /* Scaled signed 7 bits immediate offset. */
1628 /* Get the size of the data element that is accessed, which may be
1629 different from that of the source register size,
1630 e.g. in strb/ldrb. */
1631 size = aarch64_get_qualifier_esize (opnd->qualifier);
1632 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1633 {
1634 set_offset_out_of_range_error (mismatch_detail, idx,
1635 -64 * size, 63 * size);
1636 return 0;
1637 }
1638 if (!value_aligned_p (opnd->addr.offset.imm, size))
1639 {
1640 set_unaligned_error (mismatch_detail, idx, size);
1641 return 0;
1642 }
1643 break;
f42f1a1d 1644 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1645 case AARCH64_OPND_ADDR_SIMM9:
1646 /* Unscaled signed 9 bits immediate offset. */
1647 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1648 {
1649 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1650 return 0;
1651 }
1652 break;
1653
1654 case AARCH64_OPND_ADDR_SIMM9_2:
1655 /* Unscaled signed 9 bits immediate offset, which has to be negative
1656 or unaligned. */
1657 size = aarch64_get_qualifier_esize (qualifier);
1658 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1659 && !value_aligned_p (opnd->addr.offset.imm, size))
1660 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1661 return 1;
1662 set_other_error (mismatch_detail, idx,
1663 _("negative or unaligned offset expected"));
1664 return 0;
1665
3f06e550
SN		 1666 case AARCH64_OPND_ADDR_SIMM10:
1667 /* Scaled signed 10 bits immediate offset. */
1668 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1669 {
1670 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1671 return 0;
1672 }
1673 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1674 {
1675 set_unaligned_error (mismatch_detail, idx, 8);
1676 return 0;
1677 }
1678 break;
1679
fb3265b3
SD		 1680 case AARCH64_OPND_ADDR_SIMM11:
1681 /* Signed 11 bits immediate offset (multiple of 16). */
1682 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1683 {
1684 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1685 return 0;
1686 }
1687
1688 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1689 {
1690 set_unaligned_error (mismatch_detail, idx, 16);
1691 return 0;
1692 }
1693 break;
1694
1695 case AARCH64_OPND_ADDR_SIMM13:
1696 /* Signed 13 bits immediate offset (multiple of 16). */
1697 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1698 {
1699 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1700 return 0;
1701 }
1702
1703 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1704 {
1705 set_unaligned_error (mismatch_detail, idx, 16);
1706 return 0;
1707 }
1708 break;
1709
a06ea964
NC		 1710 case AARCH64_OPND_SIMD_ADDR_POST:
1711 /* AdvSIMD load/store multiple structures, post-index. */
1712 assert (idx == 1);
1713 if (opnd->addr.offset.is_reg)
1714 {
1715 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1716 return 1;
1717 else
1718 {
1719 set_other_error (mismatch_detail, idx,
1720 _("invalid register offset"));
1721 return 0;
1722 }
1723 }
1724 else
1725 {
1726 const aarch64_opnd_info *prev = &opnds[idx-1];
1727 unsigned num_bytes; /* total number of bytes transferred. */
1728 /* The opcode dependent area stores the number of elements in
1729 each structure to be loaded/stored. */
1730 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1731 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1732 /* Special handling of loading single structure to all lane. */
1733 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1734 * aarch64_get_qualifier_esize (prev->qualifier);
1735 else
1736 num_bytes = prev->reglist.num_regs
1737 * aarch64_get_qualifier_esize (prev->qualifier)
1738 * aarch64_get_qualifier_nelem (prev->qualifier);
1739 if ((int) num_bytes != opnd->addr.offset.imm)
1740 {
1741 set_other_error (mismatch_detail, idx,
1742 _("invalid post-increment amount"));
1743 return 0;
1744 }
1745 }
1746 break;
1747
1748 case AARCH64_OPND_ADDR_REGOFF:
1749 /* Get the size of the data element that is accessed, which may be
1750 different from that of the source register size,
1751 e.g. in strb/ldrb. */
1752 size = aarch64_get_qualifier_esize (opnd->qualifier);
1753 /* It is either no shift or shift by the binary logarithm of SIZE. */
1754 if (opnd->shifter.amount != 0
1755 && opnd->shifter.amount != (int)get_logsz (size))
1756 {
1757 set_other_error (mismatch_detail, idx,
1758 _("invalid shift amount"));
1759 return 0;
1760 }
1761 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1762 operators. */
1763 switch (opnd->shifter.kind)
1764 {
1765 case AARCH64_MOD_UXTW:
1766 case AARCH64_MOD_LSL:
1767 case AARCH64_MOD_SXTW:
1768 case AARCH64_MOD_SXTX: break;
1769 default:
1770 set_other_error (mismatch_detail, idx,
1771 _("invalid extend/shift operator"));
1772 return 0;
1773 }
1774 break;
1775
1776 case AARCH64_OPND_ADDR_UIMM12:
1777 imm = opnd->addr.offset.imm;
1778 /* Get the size of the data element that is accessed, which may be
1779 different from that of the source register size,
1780 e.g. in strb/ldrb. */
1781 size = aarch64_get_qualifier_esize (qualifier);
1782 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1783 {
1784 set_offset_out_of_range_error (mismatch_detail, idx,
1785 0, 4095 * size);
1786 return 0;
1787 }
9de794e1 1788 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1789 {
1790 set_unaligned_error (mismatch_detail, idx, size);
1791 return 0;
1792 }
1793 break;
1794
1795 case AARCH64_OPND_ADDR_PCREL14:
1796 case AARCH64_OPND_ADDR_PCREL19:
1797 case AARCH64_OPND_ADDR_PCREL21:
1798 case AARCH64_OPND_ADDR_PCREL26:
1799 imm = opnd->imm.value;
1800 if (operand_need_shift_by_two (get_operand_from_code (type)))
1801 {
1802 /* The offset value in a PC-relative branch instruction is alway
1803 4-byte aligned and is encoded without the lowest 2 bits. */
1804 if (!value_aligned_p (imm, 4))
1805 {
1806 set_unaligned_error (mismatch_detail, idx, 4);
1807 return 0;
1808 }
1809 /* Right shift by 2 so that we can carry out the following check
1810 canonically. */
1811 imm >>= 2;
1812 }
1813 size = get_operand_fields_width (get_operand_from_code (type));
1814 if (!value_fit_signed_field_p (imm, size))
1815 {
1816 set_other_error (mismatch_detail, idx,
1817 _("immediate out of range"));
1818 return 0;
1819 }
1820 break;
1821
98907a70
RS		 1822 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1823 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1824 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1825 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1826 min_value = -8;
1827 max_value = 7;
1828 sve_imm_offset_vl:
1829 assert (!opnd->addr.offset.is_reg);
1830 assert (opnd->addr.preind);
1831 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1832 min_value *= num;
1833 max_value *= num;
1834 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1835 || (opnd->shifter.operator_present
1836 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1837 {
1838 set_other_error (mismatch_detail, idx,
1839 _("invalid addressing mode"));
1840 return 0;
1841 }
1842 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1843 {
1844 set_offset_out_of_range_error (mismatch_detail, idx,
1845 min_value, max_value);
1846 return 0;
1847 }
1848 if (!value_aligned_p (opnd->addr.offset.imm, num))
1849 {
1850 set_unaligned_error (mismatch_detail, idx, num);
1851 return 0;
1852 }
1853 break;
1854
1855 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1856 min_value = -32;
1857 max_value = 31;
1858 goto sve_imm_offset_vl;
1859
1860 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1861 min_value = -256;
1862 max_value = 255;
1863 goto sve_imm_offset_vl;
1864
4df068de
RS		 1865 case AARCH64_OPND_SVE_ADDR_RI_U6:
1866 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1867 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1868 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1869 min_value = 0;
1870 max_value = 63;
1871 sve_imm_offset:
1872 assert (!opnd->addr.offset.is_reg);
1873 assert (opnd->addr.preind);
1874 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1875 min_value *= num;
1876 max_value *= num;
1877 if (opnd->shifter.operator_present
1878 || opnd->shifter.amount_present)
1879 {
1880 set_other_error (mismatch_detail, idx,
1881 _("invalid addressing mode"));
1882 return 0;
1883 }
1884 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1885 {
1886 set_offset_out_of_range_error (mismatch_detail, idx,
1887 min_value, max_value);
1888 return 0;
1889 }
1890 if (!value_aligned_p (opnd->addr.offset.imm, num))
1891 {
1892 set_unaligned_error (mismatch_detail, idx, num);
1893 return 0;
1894 }
1895 break;
1896
582e12bf
RS		 1897 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
1898 min_value = -8;
1899 max_value = 7;
1900 goto sve_imm_offset;
1901
c8d59609 1902 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1903 case AARCH64_OPND_SVE_ADDR_RR:
1904 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1905 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1906 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1907 case AARCH64_OPND_SVE_ADDR_RX:
1908 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1909 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1910 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1911 case AARCH64_OPND_SVE_ADDR_RZ:
1912 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1913 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1914 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1915 modifiers = 1 << AARCH64_MOD_LSL;
1916 sve_rr_operand:
1917 assert (opnd->addr.offset.is_reg);
1918 assert (opnd->addr.preind);
1919 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1920 && opnd->addr.offset.regno == 31)
1921 {
1922 set_other_error (mismatch_detail, idx,
1923 _("index register xzr is not allowed"));
1924 return 0;
1925 }
1926 if (((1 << opnd->shifter.kind) & modifiers) == 0
1927 || (opnd->shifter.amount
1928 != get_operand_specific_data (&aarch64_operands[type])))
1929 {
1930 set_other_error (mismatch_detail, idx,
1931 _("invalid addressing mode"));
1932 return 0;
1933 }
1934 break;
1935
1936 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1937 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1938 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1939 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1940 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1941 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1942 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1943 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1944 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1945 goto sve_rr_operand;
1946
1947 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1948 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1949 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1950 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1951 min_value = 0;
1952 max_value = 31;
1953 goto sve_imm_offset;
1954
1955 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1956 modifiers = 1 << AARCH64_MOD_LSL;
1957 sve_zz_operand:
1958 assert (opnd->addr.offset.is_reg);
1959 assert (opnd->addr.preind);
1960 if (((1 << opnd->shifter.kind) & modifiers) == 0
1961 || opnd->shifter.amount < 0
1962 || opnd->shifter.amount > 3)
1963 {
1964 set_other_error (mismatch_detail, idx,
1965 _("invalid addressing mode"));
1966 return 0;
1967 }
1968 break;
1969
1970 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1971 modifiers = (1 << AARCH64_MOD_SXTW);
1972 goto sve_zz_operand;
1973
1974 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1975 modifiers = 1 << AARCH64_MOD_UXTW;
1976 goto sve_zz_operand;
1977
a06ea964
NC		 1978 default:
1979 break;
1980 }
1981 break;
1982
1983 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 1984 if (type == AARCH64_OPND_LEt)
1985 {
1986 /* Get the upper bound for the element index. */
1987 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
1988 if (!value_in_range_p (opnd->reglist.index, 0, num))
1989 {
1990 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
1991 return 0;
1992 }
1993 }
a06ea964
NC		 1994 /* The opcode dependent area stores the number of elements in
1995 each structure to be loaded/stored. */
1996 num = get_opcode_dependent_value (opcode);
1997 switch (type)
1998 {
1999 case AARCH64_OPND_LVt:
2000 assert (num >= 1 && num <= 4);
2001 /* Unless LD1/ST1, the number of registers should be equal to that
2002 of the structure elements. */
2003 if (num != 1 && opnd->reglist.num_regs != num)
2004 {
2005 set_reg_list_error (mismatch_detail, idx, num);
2006 return 0;
2007 }
2008 break;
2009 case AARCH64_OPND_LVt_AL:
2010 case AARCH64_OPND_LEt:
2011 assert (num >= 1 && num <= 4);
2012 /* The number of registers should be equal to that of the structure
2013 elements. */
2014 if (opnd->reglist.num_regs != num)
2015 {
2016 set_reg_list_error (mismatch_detail, idx, num);
2017 return 0;
2018 }
2019 break;
2020 default:
2021 break;
2022 }
2023 break;
2024
2025 case AARCH64_OPND_CLASS_IMMEDIATE:
2026 /* Constraint check on immediate operand. */
2027 imm = opnd->imm.value;
2028 /* E.g. imm_0_31 constrains value to be 0..31. */
2029 if (qualifier_value_in_range_constraint_p (qualifier)
2030 && !value_in_range_p (imm, get_lower_bound (qualifier),
2031 get_upper_bound (qualifier)))
2032 {
2033 set_imm_out_of_range_error (mismatch_detail, idx,
2034 get_lower_bound (qualifier),
2035 get_upper_bound (qualifier));
2036 return 0;
2037 }
2038
2039 switch (type)
2040 {
2041 case AARCH64_OPND_AIMM:
2042 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2043 {
2044 set_other_error (mismatch_detail, idx,
2045 _("invalid shift operator"));
2046 return 0;
2047 }
2048 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2049 {
2050 set_other_error (mismatch_detail, idx,
ab3b8fcf 2051 _("shift amount must be 0 or 12"));
a06ea964
NC		 2052 return 0;
2053 }
2054 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2055 {
2056 set_other_error (mismatch_detail, idx,
2057 _("immediate out of range"));
2058 return 0;
2059 }
2060 break;
2061
2062 case AARCH64_OPND_HALF:
2063 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2064 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2065 {
2066 set_other_error (mismatch_detail, idx,
2067 _("invalid shift operator"));
2068 return 0;
2069 }
2070 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2071 if (!value_aligned_p (opnd->shifter.amount, 16))
2072 {
2073 set_other_error (mismatch_detail, idx,
ab3b8fcf 2074 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2075 return 0;
2076 }
2077 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2078 {
2079 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2080 0, size * 8 - 16);
2081 return 0;
2082 }
2083 if (opnd->imm.value < 0)
2084 {
2085 set_other_error (mismatch_detail, idx,
2086 _("negative immediate value not allowed"));
2087 return 0;
2088 }
2089 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2090 {
2091 set_other_error (mismatch_detail, idx,
2092 _("immediate out of range"));
2093 return 0;
2094 }
2095 break;
2096
2097 case AARCH64_OPND_IMM_MOV:
2098 {
42408347 2099 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2100 imm = opnd->imm.value;
2101 assert (idx == 1);
2102 switch (opcode->op)
2103 {
2104 case OP_MOV_IMM_WIDEN:
2105 imm = ~imm;
1a0670f3 2106 /* Fall through. */
a06ea964 2107 case OP_MOV_IMM_WIDE:
42408347 2108 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2109 {
2110 set_other_error (mismatch_detail, idx,
2111 _("immediate out of range"));
2112 return 0;
2113 }
2114 break;
2115 case OP_MOV_IMM_LOG:
42408347 2116 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2117 {
2118 set_other_error (mismatch_detail, idx,
2119 _("immediate out of range"));
2120 return 0;
2121 }
2122 break;
2123 default:
2124 assert (0);
2125 return 0;
2126 }
2127 }
2128 break;
2129
2130 case AARCH64_OPND_NZCV:
2131 case AARCH64_OPND_CCMP_IMM:
2132 case AARCH64_OPND_EXCEPTION:
b83b4b13 2133 case AARCH64_OPND_TME_UIMM16:
a06ea964 2134 case AARCH64_OPND_UIMM4:
193614f2 2135 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2136 case AARCH64_OPND_UIMM7:
2137 case AARCH64_OPND_UIMM3_OP1:
2138 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2139 case AARCH64_OPND_SVE_UIMM3:
2140 case AARCH64_OPND_SVE_UIMM7:
2141 case AARCH64_OPND_SVE_UIMM8:
2142 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2143 size = get_operand_fields_width (get_operand_from_code (type));
2144 assert (size < 32);
2145 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2146 {
2147 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2148 (1 << size) - 1);
2149 return 0;
2150 }
2151 break;
2152
193614f2
SD		 2153 case AARCH64_OPND_UIMM10:
2154 /* Scaled unsigned 10 bits immediate offset. */
2155 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2156 {
2157 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2158 return 0;
2159 }
2160
2161 if (!value_aligned_p (opnd->imm.value, 16))
2162 {
2163 set_unaligned_error (mismatch_detail, idx, 16);
2164 return 0;
2165 }
2166 break;
2167
e950b345
RS		 2168 case AARCH64_OPND_SIMM5:
2169 case AARCH64_OPND_SVE_SIMM5:
2170 case AARCH64_OPND_SVE_SIMM5B:
2171 case AARCH64_OPND_SVE_SIMM6:
2172 case AARCH64_OPND_SVE_SIMM8:
2173 size = get_operand_fields_width (get_operand_from_code (type));
2174 assert (size < 32);
2175 if (!value_fit_signed_field_p (opnd->imm.value, size))
2176 {
2177 set_imm_out_of_range_error (mismatch_detail, idx,
2178 -(1 << (size - 1)),
2179 (1 << (size - 1)) - 1);
2180 return 0;
2181 }
2182 break;
2183
a06ea964 2184 case AARCH64_OPND_WIDTH:
d685192a 2185 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2186 && opnds[0].type == AARCH64_OPND_Rd);
2187 size = get_upper_bound (qualifier);
2188 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2189 /* lsb+width <= reg.size */
2190 {
2191 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2192 size - opnds[idx-1].imm.value);
2193 return 0;
2194 }
2195 break;
2196
2197 case AARCH64_OPND_LIMM:
e950b345 2198 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2199 {
2200 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2201 uint64_t uimm = opnd->imm.value;
2202 if (opcode->op == OP_BIC)
2203 uimm = ~uimm;
535b785f 2204 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2205 {
2206 set_other_error (mismatch_detail, idx,
2207 _("immediate out of range"));
2208 return 0;
2209 }
2210 }
a06ea964
NC		 2211 break;
2212
2213 case AARCH64_OPND_IMM0:
2214 case AARCH64_OPND_FPIMM0:
2215 if (opnd->imm.value != 0)
2216 {
2217 set_other_error (mismatch_detail, idx,
2218 _("immediate zero expected"));
2219 return 0;
2220 }
2221 break;
2222
c2c4ff8d
SN		 2223 case AARCH64_OPND_IMM_ROT1:
2224 case AARCH64_OPND_IMM_ROT2:
582e12bf 2225 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2226 if (opnd->imm.value != 0
2227 && opnd->imm.value != 90
2228 && opnd->imm.value != 180
2229 && opnd->imm.value != 270)
2230 {
2231 set_other_error (mismatch_detail, idx,
2232 _("rotate expected to be 0, 90, 180 or 270"));
2233 return 0;
2234 }
2235 break;
2236
2237 case AARCH64_OPND_IMM_ROT3:
582e12bf 2238 case AARCH64_OPND_SVE_IMM_ROT1:
adccc507 2239 case AARCH64_OPND_SVE_IMM_ROT3:
c2c4ff8d
SN		 2240 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2241 {
2242 set_other_error (mismatch_detail, idx,
2243 _("rotate expected to be 90 or 270"));
2244 return 0;
2245 }
2246 break;
2247
a06ea964
NC		 2248 case AARCH64_OPND_SHLL_IMM:
2249 assert (idx == 2);
2250 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2251 if (opnd->imm.value != size)
2252 {
2253 set_other_error (mismatch_detail, idx,
2254 _("invalid shift amount"));
2255 return 0;
2256 }
2257 break;
2258
2259 case AARCH64_OPND_IMM_VLSL:
2260 size = aarch64_get_qualifier_esize (qualifier);
2261 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2262 {
2263 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2264 size * 8 - 1);
2265 return 0;
2266 }
2267 break;
2268
2269 case AARCH64_OPND_IMM_VLSR:
2270 size = aarch64_get_qualifier_esize (qualifier);
2271 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2272 {
2273 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2274 return 0;
2275 }
2276 break;
2277
2278 case AARCH64_OPND_SIMD_IMM:
2279 case AARCH64_OPND_SIMD_IMM_SFT:
2280 /* Qualifier check. */
2281 switch (qualifier)
2282 {
2283 case AARCH64_OPND_QLF_LSL:
2284 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2285 {
2286 set_other_error (mismatch_detail, idx,
2287 _("invalid shift operator"));
2288 return 0;
2289 }
2290 break;
2291 case AARCH64_OPND_QLF_MSL:
2292 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2293 {
2294 set_other_error (mismatch_detail, idx,
2295 _("invalid shift operator"));
2296 return 0;
2297 }
2298 break;
2299 case AARCH64_OPND_QLF_NIL:
2300 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2301 {
2302 set_other_error (mismatch_detail, idx,
2303 _("shift is not permitted"));
2304 return 0;
2305 }
2306 break;
2307 default:
2308 assert (0);
2309 return 0;
2310 }
2311 /* Is the immediate valid? */
2312 assert (idx == 1);
2313 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2314 {
d2865ed3
YZ		 2315 /* uimm8 or simm8 */
2316 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2317 {
d2865ed3 2318 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2319 return 0;
2320 }
2321 }
2322 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2323 {
2324 /* uimm64 is not
2325 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2326 ffffffffgggggggghhhhhhhh'. */
2327 set_other_error (mismatch_detail, idx,
2328 _("invalid value for immediate"));
2329 return 0;
2330 }
2331 /* Is the shift amount valid? */
2332 switch (opnd->shifter.kind)
2333 {
2334 case AARCH64_MOD_LSL:
2335 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2336 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2337 {
f5555712
YZ		 2338 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2339 (size - 1) * 8);
a06ea964
NC		 2340 return 0;
2341 }
f5555712 2342 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2343 {
f5555712 2344 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2345 return 0;
2346 }
2347 break;
2348 case AARCH64_MOD_MSL:
2349 /* Only 8 and 16 are valid shift amount. */
2350 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2351 {
2352 set_other_error (mismatch_detail, idx,
ab3b8fcf 2353 _("shift amount must be 0 or 16"));
a06ea964
NC		 2354 return 0;
2355 }
2356 break;
2357 default:
2358 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2359 {
2360 set_other_error (mismatch_detail, idx,
2361 _("invalid shift operator"));
2362 return 0;
2363 }
2364 break;
2365 }
2366 break;
2367
2368 case AARCH64_OPND_FPIMM:
2369 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2370 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2371 if (opnd->imm.is_fp == 0)
2372 {
2373 set_other_error (mismatch_detail, idx,
2374 _("floating-point immediate expected"));
2375 return 0;
2376 }
2377 /* The value is expected to be an 8-bit floating-point constant with
2378 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2379 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2380 instruction). */
2381 if (!value_in_range_p (opnd->imm.value, 0, 255))
2382 {
2383 set_other_error (mismatch_detail, idx,
2384 _("immediate out of range"));
2385 return 0;
2386 }
2387 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2388 {
2389 set_other_error (mismatch_detail, idx,
2390 _("invalid shift operator"));
2391 return 0;
2392 }
2393 break;
2394
e950b345
RS		 2395 case AARCH64_OPND_SVE_AIMM:
2396 min_value = 0;
2397 sve_aimm:
2398 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2399 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2400 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2401 uvalue = opnd->imm.value;
2402 shift = opnd->shifter.amount;
2403 if (size == 1)
2404 {
2405 if (shift != 0)
2406 {
2407 set_other_error (mismatch_detail, idx,
2408 _("no shift amount allowed for"
2409 " 8-bit constants"));
2410 return 0;
2411 }
2412 }
2413 else
2414 {
2415 if (shift != 0 && shift != 8)
2416 {
2417 set_other_error (mismatch_detail, idx,
2418 _("shift amount must be 0 or 8"));
2419 return 0;
2420 }
2421 if (shift == 0 && (uvalue & 0xff) == 0)
2422 {
2423 shift = 8;
2424 uvalue = (int64_t) uvalue / 256;
2425 }
2426 }
2427 mask >>= shift;
2428 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2429 {
2430 set_other_error (mismatch_detail, idx,
2431 _("immediate too big for element size"));
2432 return 0;
2433 }
2434 uvalue = (uvalue - min_value) & mask;
2435 if (uvalue > 0xff)
2436 {
2437 set_other_error (mismatch_detail, idx,
2438 _("invalid arithmetic immediate"));
2439 return 0;
2440 }
2441 break;
2442
2443 case AARCH64_OPND_SVE_ASIMM:
2444 min_value = -128;
2445 goto sve_aimm;
2446
165d4950
RS		 2447 case AARCH64_OPND_SVE_I1_HALF_ONE:
2448 assert (opnd->imm.is_fp);
2449 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2450 {
2451 set_other_error (mismatch_detail, idx,
2452 _("floating-point value must be 0.5 or 1.0"));
2453 return 0;
2454 }
2455 break;
2456
2457 case AARCH64_OPND_SVE_I1_HALF_TWO:
2458 assert (opnd->imm.is_fp);
2459 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2460 {
2461 set_other_error (mismatch_detail, idx,
2462 _("floating-point value must be 0.5 or 2.0"));
2463 return 0;
2464 }
2465 break;
2466
2467 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2468 assert (opnd->imm.is_fp);
2469 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2470 {
2471 set_other_error (mismatch_detail, idx,
2472 _("floating-point value must be 0.0 or 1.0"));
2473 return 0;
2474 }
2475 break;
2476
e950b345
RS		 2477 case AARCH64_OPND_SVE_INV_LIMM:
2478 {
2479 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2480 uint64_t uimm = ~opnd->imm.value;
2481 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2482 {
2483 set_other_error (mismatch_detail, idx,
2484 _("immediate out of range"));
2485 return 0;
2486 }
2487 }
2488 break;
2489
2490 case AARCH64_OPND_SVE_LIMM_MOV:
2491 {
2492 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2493 uint64_t uimm = opnd->imm.value;
2494 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2495 {
2496 set_other_error (mismatch_detail, idx,
2497 _("immediate out of range"));
2498 return 0;
2499 }
2500 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2501 {
2502 set_other_error (mismatch_detail, idx,
2503 _("invalid replicated MOV immediate"));
2504 return 0;
2505 }
2506 }
2507 break;
2508
2442d846
RS		 2509 case AARCH64_OPND_SVE_PATTERN_SCALED:
2510 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2511 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2512 {
2513 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2514 return 0;
2515 }
2516 break;
2517
e950b345
RS		 2518 case AARCH64_OPND_SVE_SHLIMM_PRED:
2519 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
2520 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2521 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2522 {
2523 set_imm_out_of_range_error (mismatch_detail, idx,
2524 0, 8 * size - 1);
2525 return 0;
2526 }
2527 break;
2528
2529 case AARCH64_OPND_SVE_SHRIMM_PRED:
2530 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
2531 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2532 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2533 {
2534 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8 * size);
2535 return 0;
2536 }
2537 break;
2538
a06ea964
NC		 2539 default:
2540 break;
2541 }
2542 break;
2543
a06ea964
NC		 2544 case AARCH64_OPND_CLASS_SYSTEM:
2545 switch (type)
2546 {
2547 case AARCH64_OPND_PSTATEFIELD:
2548 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2549 /* MSR UAO, #uimm4
2550 MSR PAN, #uimm4
104fefee 2551 MSR SSBS,#uimm4
c2825638 2552 The immediate must be #0 or #1. */
0bff6e2d 2553 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2554 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2555 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2556 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2557 && opnds[1].imm.value > 1)
2558 {
2559 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2560 return 0;
2561 }
a06ea964
NC		 2562 /* MSR SPSel, #uimm4
2563 Uses uimm4 as a control value to select the stack pointer: if
2564 bit 0 is set it selects the current exception level's stack
2565 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2566 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2567 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2568 {
2569 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2570 return 0;
2571 }
2572 break;
2573 default:
2574 break;
2575 }
2576 break;
2577
2578 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2579 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2580 if (opcode->op == OP_FCMLA_ELEM)
2581 /* FCMLA index range depends on the vector size of other operands
2582 and is halfed because complex numbers take two elements. */
2583 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2584 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2585 else
2586 num = 16;
2587 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2588 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2589
a06ea964
NC		 2590 /* Index out-of-range. */
2591 if (!value_in_range_p (opnd->reglane.index, 0, num))
2592 {
2593 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2594 return 0;
2595 }
2596 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2597 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2598 number is encoded in "size:M:Rm":
2599 size <Vm>
2600 00 RESERVED
2601 01 0:Rm
2602 10 M:Rm
2603 11 RESERVED */
369c9167 2604 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2605 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2606 {
2607 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2608 return 0;
2609 }
2610 break;
2611
2612 case AARCH64_OPND_CLASS_MODIFIED_REG:
2613 assert (idx == 1 || idx == 2);
2614 switch (type)
2615 {
2616 case AARCH64_OPND_Rm_EXT:
535b785f 2617 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2618 && opnd->shifter.kind != AARCH64_MOD_LSL)
2619 {
2620 set_other_error (mismatch_detail, idx,
2621 _("extend operator expected"));
2622 return 0;
2623 }
2624 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2625 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2626 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2627 case. */
2628 if (!aarch64_stack_pointer_p (opnds + 0)
2629 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2630 {
2631 if (!opnd->shifter.operator_present)
2632 {
2633 set_other_error (mismatch_detail, idx,
2634 _("missing extend operator"));
2635 return 0;
2636 }
2637 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2638 {
2639 set_other_error (mismatch_detail, idx,
2640 _("'LSL' operator not allowed"));
2641 return 0;
2642 }
2643 }
2644 assert (opnd->shifter.operator_present /* Default to LSL. */
2645 || opnd->shifter.kind == AARCH64_MOD_LSL);
2646 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2647 {
2648 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2649 return 0;
2650 }
2651 /* In the 64-bit form, the final register operand is written as Wm
2652 for all but the (possibly omitted) UXTX/LSL and SXTX
2653 operators.
2654 N.B. GAS allows X register to be used with any operator as a
2655 programming convenience. */
2656 if (qualifier == AARCH64_OPND_QLF_X
2657 && opnd->shifter.kind != AARCH64_MOD_LSL
2658 && opnd->shifter.kind != AARCH64_MOD_UXTX
2659 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2660 {
2661 set_other_error (mismatch_detail, idx, _("W register expected"));
2662 return 0;
2663 }
2664 break;
2665
2666 case AARCH64_OPND_Rm_SFT:
2667 /* ROR is not available to the shifted register operand in
2668 arithmetic instructions. */
535b785f 2669 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2670 {
2671 set_other_error (mismatch_detail, idx,
2672 _("shift operator expected"));
2673 return 0;
2674 }
2675 if (opnd->shifter.kind == AARCH64_MOD_ROR
2676 && opcode->iclass != log_shift)
2677 {
2678 set_other_error (mismatch_detail, idx,
2679 _("'ROR' operator not allowed"));
2680 return 0;
2681 }
2682 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2683 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2684 {
2685 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2686 return 0;
2687 }
2688 break;
2689
2690 default:
2691 break;
2692 }
2693 break;
2694
2695 default:
2696 break;
2697 }
2698
2699 return 1;
2700}
2701
2702/* Main entrypoint for the operand constraint checking.
2703
2704 Return 1 if operands of *INST meet the constraint applied by the operand
2705 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2706 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2707 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2708 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2709 error kind when it is notified that an instruction does not pass the check).
2710
2711 Un-determined operand qualifiers may get established during the process. */
2712
2713int
2714aarch64_match_operands_constraint (aarch64_inst *inst,
2715 aarch64_operand_error *mismatch_detail)
2716{
2717 int i;
2718
2719 DEBUG_TRACE ("enter");
2720
0c608d6b
RS		 2721 /* Check for cases where a source register needs to be the same as the
2722 destination register. Do this before matching qualifiers since if
2723 an instruction has both invalid tying and invalid qualifiers,
2724 the error about qualifiers would suggest several alternative
2725 instructions that also have invalid tying. */
2726 i = inst->opcode->tied_operand;
2727 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2728 {
2729 if (mismatch_detail)
2730 {
2731 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2732 mismatch_detail->index = i;
2733 mismatch_detail->error = NULL;
2734 }
2735 return 0;
2736 }
2737
a06ea964
NC		 2738 /* Match operands' qualifier.
2739 *INST has already had qualifier establish for some, if not all, of
2740 its operands; we need to find out whether these established
2741 qualifiers match one of the qualifier sequence in
2742 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2743 with the corresponding qualifier in such a sequence.
2744 Only basic operand constraint checking is done here; the more thorough
2745 constraint checking will carried out by operand_general_constraint_met_p,
2746 which has be to called after this in order to get all of the operands'
2747 qualifiers established. */
2748 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2749 {
2750 DEBUG_TRACE ("FAIL on operand qualifier matching");
2751 if (mismatch_detail)
2752 {
2753 /* Return an error type to indicate that it is the qualifier
2754 matching failure; we don't care about which operand as there
2755 are enough information in the opcode table to reproduce it. */
2756 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2757 mismatch_detail->index = -1;
2758 mismatch_detail->error = NULL;
2759 }
2760 return 0;
2761 }
2762
2763 /* Match operands' constraint. */
2764 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2765 {
2766 enum aarch64_opnd type = inst->opcode->operands[i];
2767 if (type == AARCH64_OPND_NIL)
2768 break;
2769 if (inst->operands[i].skip)
2770 {
2771 DEBUG_TRACE ("skip the incomplete operand %d", i);
2772 continue;
2773 }
2774 if (operand_general_constraint_met_p (inst->operands, i, type,
2775 inst->opcode, mismatch_detail) == 0)
2776 {
2777 DEBUG_TRACE ("FAIL on operand %d", i);
2778 return 0;
2779 }
2780 }
2781
2782 DEBUG_TRACE ("PASS");
2783
2784 return 1;
2785}
2786
2787/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2788 Also updates the TYPE of each INST->OPERANDS with the corresponding
2789 value of OPCODE->OPERANDS.
2790
2791 Note that some operand qualifiers may need to be manually cleared by
2792 the caller before it further calls the aarch64_opcode_encode; by
2793 doing this, it helps the qualifier matching facilities work
2794 properly. */
2795
2796const aarch64_opcode*
2797aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2798{
2799 int i;
2800 const aarch64_opcode *old = inst->opcode;
2801
2802 inst->opcode = opcode;
2803
2804 /* Update the operand types. */
2805 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2806 {
2807 inst->operands[i].type = opcode->operands[i];
2808 if (opcode->operands[i] == AARCH64_OPND_NIL)
2809 break;
2810 }
2811
2812 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2813
2814 return old;
2815}
2816
2817int
2818aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2819{
2820 int i;
2821 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2822 if (operands[i] == operand)
2823 return i;
2824 else if (operands[i] == AARCH64_OPND_NIL)
2825 break;
2826 return -1;
2827}
2828\f
72e9f319
RS		 2829/* R0...R30, followed by FOR31. */
2830#define BANK(R, FOR31) \
2831 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2832 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2833 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2834 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2835/* [0][0] 32-bit integer regs with sp Wn
2836 [0][1] 64-bit integer regs with sp Xn sf=1
2837 [1][0] 32-bit integer regs with #0 Wn
2838 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2839static const char *int_reg[2][2][32] = {
72e9f319
RS		 2840#define R32(X) "w" #X
2841#define R64(X) "x" #X
2842 { BANK (R32, "wsp"), BANK (R64, "sp") },
2843 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2844#undef R64
2845#undef R32
2846};
4df068de
RS		 2847
2848/* Names of the SVE vector registers, first with .S suffixes,
2849 then with .D suffixes. */
2850
2851static const char *sve_reg[2][32] = {
2852#define ZS(X) "z" #X ".s"
2853#define ZD(X) "z" #X ".d"
2854 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2855#undef ZD
2856#undef ZS
2857};
72e9f319 2858#undef BANK
a06ea964
NC		 2859
2860/* Return the integer register name.
2861 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2862
2863static inline const char *
2864get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2865{
2866 const int has_zr = sp_reg_p ? 0 : 1;
2867 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2868 return int_reg[has_zr][is_64][regno];
2869}
2870
2871/* Like get_int_reg_name, but IS_64 is always 1. */
2872
2873static inline const char *
2874get_64bit_int_reg_name (int regno, int sp_reg_p)
2875{
2876 const int has_zr = sp_reg_p ? 0 : 1;
2877 return int_reg[has_zr][1][regno];
2878}
2879
01dbfe4c
RS		 2880/* Get the name of the integer offset register in OPND, using the shift type
2881 to decide whether it's a word or doubleword. */
2882
2883static inline const char *
2884get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2885{
2886 switch (opnd->shifter.kind)
2887 {
2888 case AARCH64_MOD_UXTW:
2889 case AARCH64_MOD_SXTW:
2890 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2891
2892 case AARCH64_MOD_LSL:
2893 case AARCH64_MOD_SXTX:
2894 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2895
2896 default:
2897 abort ();
2898 }
2899}
2900
4df068de
RS		 2901/* Get the name of the SVE vector offset register in OPND, using the operand
2902 qualifier to decide whether the suffix should be .S or .D. */
2903
2904static inline const char *
2905get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2906{
2907 assert (qualifier == AARCH64_OPND_QLF_S_S
2908 || qualifier == AARCH64_OPND_QLF_S_D);
2909 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2910}
2911
a06ea964
NC		 2912/* Types for expanding an encoded 8-bit value to a floating-point value. */
2913
2914typedef union
2915{
2916 uint64_t i;
2917 double d;
2918} double_conv_t;
2919
2920typedef union
2921{
2922 uint32_t i;
2923 float f;
2924} single_conv_t;
2925
cf86120b
MW		 2926typedef union
2927{
2928 uint32_t i;
2929 float f;
2930} half_conv_t;
2931
a06ea964
NC		 2932/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2933 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2934 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2935 single-precision floating-point value (SIZE == 4) or a double-precision
2936 floating-point value (SIZE == 8). A half-precision floating-point value
2937 (SIZE == 2) is expanded to a single-precision floating-point value. The
2938 expanded value is returned. */
a06ea964
NC		 2939
2940static uint64_t
cf86120b 2941expand_fp_imm (int size, uint32_t imm8)
a06ea964 2942{
57a024f4 2943 uint64_t imm = 0;
a06ea964
NC		 2944 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2945
2946 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2947 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2948 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2949 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2950 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2951 if (size == 8)
a06ea964
NC		 2952 {
2953 imm = (imm8_7 << (63-32)) /* imm8<7> */
2954 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2955 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2956 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2957 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2958 imm <<= 32;
2959 }
cf86120b 2960 else if (size == 4 || size == 2)
a06ea964
NC		 2961 {
2962 imm = (imm8_7 << 31) /* imm8<7> */
2963 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2964 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2965 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2966 }
cf86120b
MW		 2967 else
2968 {
2969 /* An unsupported size. */
2970 assert (0);
2971 }
a06ea964
NC		 2972
2973 return imm;
2974}
2975
2976/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2977 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
2978 the register name that comes before the register number, such as "v". */
a06ea964 2979static void
8a7f0c1b
RS		 2980print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
2981 const char *prefix)
a06ea964
NC		 2982{
2983 const int num_regs = opnd->reglist.num_regs;
2984 const int first_reg = opnd->reglist.first_regno;
2985 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
2986 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
2987 char tb[8]; /* Temporary buffer. */
2988
2989 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
2990 assert (num_regs >= 1 && num_regs <= 4);
2991
2992 /* Prepare the index if any. */
2993 if (opnd->reglist.has_index)
1b7e3d2f
NC		 2994 /* PR 21096: The %100 is to silence a warning about possible truncation. */
2995 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 2996 else
2997 tb[0] = '\0';
2998
2999 /* The hyphenated form is preferred for disassembly if there are
3000 more than two registers in the list, and the register numbers
3001 are monotonically increasing in increments of one. */
3002 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 3003 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3004 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 3005 else
3006 {
3007 const int reg0 = first_reg;
3008 const int reg1 = (first_reg + 1) & 0x1f;
3009 const int reg2 = (first_reg + 2) & 0x1f;
3010 const int reg3 = (first_reg + 3) & 0x1f;
3011
3012 switch (num_regs)
3013 {
3014 case 1:
8a7f0c1b 3015 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3016 break;
3017 case 2:
8a7f0c1b
RS		 3018 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3019 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3020 break;
3021 case 3:
8a7f0c1b
RS		 3022 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3023 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3024 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3025 break;
3026 case 4:
8a7f0c1b
RS		 3027 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3028 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3029 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3030 break;
3031 }
3032 }
3033}
3034
01dbfe4c
RS		 3035/* Print the register+immediate address in OPND to BUF, which has SIZE
3036 characters. BASE is the name of the base register. */
3037
3038static void
3039print_immediate_offset_address (char *buf, size_t size,
3040 const aarch64_opnd_info *opnd,
3041 const char *base)
3042{
3043 if (opnd->addr.writeback)
3044 {
3045 if (opnd->addr.preind)
ad43e107 3046 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
01dbfe4c 3047 else
ad43e107 3048 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3049 }
3050 else
3051 {
98907a70
RS		 3052 if (opnd->shifter.operator_present)
3053 {
3054 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3055 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3056 base, opnd->addr.offset.imm);
3057 }
3058 else if (opnd->addr.offset.imm)
ad43e107 3059 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3060 else
3061 snprintf (buf, size, "[%s]", base);
3062 }
3063}
3064
a06ea964 3065/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3066 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3067 the names of the base and offset registers. */
a06ea964
NC		 3068static void
3069print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3070 const aarch64_opnd_info *opnd,
3071 const char *base, const char *offset)
a06ea964 3072{
0d2f91fe 3073 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3074 bfd_boolean print_extend_p = TRUE;
3075 bfd_boolean print_amount_p = TRUE;
3076 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3077
a06ea964
NC		 3078 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3079 || !opnd->shifter.amount_present))
3080 {
3081 /* Not print the shift/extend amount when the amount is zero and
3082 when it is not the special case of 8-bit load/store instruction. */
3083 print_amount_p = FALSE;
3084 /* Likewise, no need to print the shift operator LSL in such a
3085 situation. */
01dbfe4c 3086 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3087 print_extend_p = FALSE;
3088 }
3089
3090 /* Prepare for the extend/shift. */
3091 if (print_extend_p)
3092 {
3093 if (print_amount_p)
ad43e107 3094 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3095 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3096 (opnd->shifter.amount % 100));
a06ea964 3097 else
ad43e107 3098 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3099 }
3100 else
3101 tb[0] = '\0';
3102
ad43e107 3103 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3104}
3105
3106/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3107 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3108 PC, PCREL_P and ADDRESS are used to pass in and return information about
3109 the PC-relative address calculation, where the PC value is passed in
3110 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3111 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3112 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3113
3114 The function serves both the disassembler and the assembler diagnostics
3115 issuer, which is the reason why it lives in this file. */
3116
3117void
3118aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3119 const aarch64_opcode *opcode,
3120 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3121 bfd_vma *address, char** notes)
a06ea964 3122{
bb7eff52 3123 unsigned int i, num_conds;
a06ea964
NC		 3124 const char *name = NULL;
3125 const aarch64_opnd_info *opnd = opnds + idx;
3126 enum aarch64_modifier_kind kind;
245d2e3f 3127 uint64_t addr, enum_value;
a06ea964
NC		 3128
3129 buf[0] = '\0';
3130 if (pcrel_p)
3131 *pcrel_p = 0;
3132
3133 switch (opnd->type)
3134 {
3135 case AARCH64_OPND_Rd:
3136 case AARCH64_OPND_Rn:
3137 case AARCH64_OPND_Rm:
3138 case AARCH64_OPND_Rt:
3139 case AARCH64_OPND_Rt2:
3140 case AARCH64_OPND_Rs:
3141 case AARCH64_OPND_Ra:
3142 case AARCH64_OPND_Rt_SYS:
ee804238 3143 case AARCH64_OPND_PAIRREG:
047cd301 3144 case AARCH64_OPND_SVE_Rm:
a06ea964 3145 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3146 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3147 generic optional-ness information. */
362c0c4d
JW		 3148 if (opnd->type == AARCH64_OPND_Rt_SYS)
3149 {
3150 if (!opnd->present)
3151 break;
3152 }
a06ea964 3153 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3154 else if (optional_operand_p (opcode, idx)
3155 && (opnd->reg.regno
3156 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3157 break;
3158 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3159 || opnd->qualifier == AARCH64_OPND_QLF_X);
3160 snprintf (buf, size, "%s",
3161 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3162 break;
3163
3164 case AARCH64_OPND_Rd_SP:
3165 case AARCH64_OPND_Rn_SP:
bd7ceb8d 3166 case AARCH64_OPND_Rt_SP:
047cd301 3167 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3168 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3169 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3170 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3171 || opnd->qualifier == AARCH64_OPND_QLF_X
3172 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3173 snprintf (buf, size, "%s",
3174 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3175 break;
3176
3177 case AARCH64_OPND_Rm_EXT:
3178 kind = opnd->shifter.kind;
3179 assert (idx == 1 || idx == 2);
3180 if ((aarch64_stack_pointer_p (opnds)
3181 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3182 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3183 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3184 && kind == AARCH64_MOD_UXTW)
3185 || (opnd->qualifier == AARCH64_OPND_QLF_X
3186 && kind == AARCH64_MOD_UXTX)))
3187 {
3188 /* 'LSL' is the preferred form in this case. */
3189 kind = AARCH64_MOD_LSL;
3190 if (opnd->shifter.amount == 0)
3191 {
3192 /* Shifter omitted. */
3193 snprintf (buf, size, "%s",
3194 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3195 break;
3196 }
3197 }
3198 if (opnd->shifter.amount)
2442d846 3199 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3200 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3201 aarch64_operand_modifiers[kind].name,
3202 opnd->shifter.amount);
3203 else
3204 snprintf (buf, size, "%s, %s",
3205 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3206 aarch64_operand_modifiers[kind].name);
3207 break;
3208
3209 case AARCH64_OPND_Rm_SFT:
3210 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3211 || opnd->qualifier == AARCH64_OPND_QLF_X);
3212 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3213 snprintf (buf, size, "%s",
3214 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3215 else
2442d846 3216 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3217 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3218 aarch64_operand_modifiers[opnd->shifter.kind].name,
3219 opnd->shifter.amount);
3220 break;
3221
3222 case AARCH64_OPND_Fd:
3223 case AARCH64_OPND_Fn:
3224 case AARCH64_OPND_Fm:
3225 case AARCH64_OPND_Fa:
3226 case AARCH64_OPND_Ft:
3227 case AARCH64_OPND_Ft2:
3228 case AARCH64_OPND_Sd:
3229 case AARCH64_OPND_Sn:
3230 case AARCH64_OPND_Sm:
047cd301
RS		 3231 case AARCH64_OPND_SVE_VZn:
3232 case AARCH64_OPND_SVE_Vd:
3233 case AARCH64_OPND_SVE_Vm:
3234 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3235 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3236 opnd->reg.regno);
3237 break;
3238
f42f1a1d 3239 case AARCH64_OPND_Va:
a06ea964
NC		 3240 case AARCH64_OPND_Vd:
3241 case AARCH64_OPND_Vn:
3242 case AARCH64_OPND_Vm:
3243 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3244 aarch64_get_qualifier_name (opnd->qualifier));
3245 break;
3246
3247 case AARCH64_OPND_Ed:
3248 case AARCH64_OPND_En:
3249 case AARCH64_OPND_Em:
369c9167 3250 case AARCH64_OPND_Em16:
f42f1a1d 3251 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3252 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3253 aarch64_get_qualifier_name (opnd->qualifier),
3254 opnd->reglane.index);
3255 break;
3256
3257 case AARCH64_OPND_VdD1:
3258 case AARCH64_OPND_VnD1:
3259 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3260 break;
3261
3262 case AARCH64_OPND_LVn:
3263 case AARCH64_OPND_LVt:
3264 case AARCH64_OPND_LVt_AL:
3265 case AARCH64_OPND_LEt:
8a7f0c1b 3266 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3267 break;
3268
f11ad6bc
RS		 3269 case AARCH64_OPND_SVE_Pd:
3270 case AARCH64_OPND_SVE_Pg3:
3271 case AARCH64_OPND_SVE_Pg4_5:
3272 case AARCH64_OPND_SVE_Pg4_10:
3273 case AARCH64_OPND_SVE_Pg4_16:
3274 case AARCH64_OPND_SVE_Pm:
3275 case AARCH64_OPND_SVE_Pn:
3276 case AARCH64_OPND_SVE_Pt:
3277 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3278 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3279 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3280 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3281 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3282 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3283 else
3284 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3285 aarch64_get_qualifier_name (opnd->qualifier));
3286 break;
3287
3288 case AARCH64_OPND_SVE_Za_5:
3289 case AARCH64_OPND_SVE_Za_16:
3290 case AARCH64_OPND_SVE_Zd:
3291 case AARCH64_OPND_SVE_Zm_5:
3292 case AARCH64_OPND_SVE_Zm_16:
3293 case AARCH64_OPND_SVE_Zn:
3294 case AARCH64_OPND_SVE_Zt:
3295 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3296 snprintf (buf, size, "z%d", opnd->reg.regno);
3297 else
3298 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3299 aarch64_get_qualifier_name (opnd->qualifier));
3300 break;
3301
3302 case AARCH64_OPND_SVE_ZnxN:
3303 case AARCH64_OPND_SVE_ZtxN:
3304 print_register_list (buf, size, opnd, "z");
3305 break;
3306
582e12bf
RS		 3307 case AARCH64_OPND_SVE_Zm3_INDEX:
3308 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 3309 case AARCH64_OPND_SVE_Zm3_11_INDEX:
582e12bf 3310 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3311 case AARCH64_OPND_SVE_Zn_INDEX:
3312 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3313 aarch64_get_qualifier_name (opnd->qualifier),
3314 opnd->reglane.index);
3315 break;
3316
a6a51754
RL		 3317 case AARCH64_OPND_CRn:
3318 case AARCH64_OPND_CRm:
3319 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3320 break;
3321
3322 case AARCH64_OPND_IDX:
f42f1a1d 3323 case AARCH64_OPND_MASK:
a06ea964 3324 case AARCH64_OPND_IMM:
f42f1a1d 3325 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3326 case AARCH64_OPND_WIDTH:
3327 case AARCH64_OPND_UIMM3_OP1:
3328 case AARCH64_OPND_UIMM3_OP2:
3329 case AARCH64_OPND_BIT_NUM:
3330 case AARCH64_OPND_IMM_VLSL:
3331 case AARCH64_OPND_IMM_VLSR:
3332 case AARCH64_OPND_SHLL_IMM:
3333 case AARCH64_OPND_IMM0:
3334 case AARCH64_OPND_IMMR:
3335 case AARCH64_OPND_IMMS:
3336 case AARCH64_OPND_FBITS:
b83b4b13 3337 case AARCH64_OPND_TME_UIMM16:
e950b345
RS		 3338 case AARCH64_OPND_SIMM5:
3339 case AARCH64_OPND_SVE_SHLIMM_PRED:
3340 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
3341 case AARCH64_OPND_SVE_SHRIMM_PRED:
3342 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3343 case AARCH64_OPND_SVE_SIMM5:
3344 case AARCH64_OPND_SVE_SIMM5B:
3345 case AARCH64_OPND_SVE_SIMM6:
3346 case AARCH64_OPND_SVE_SIMM8:
3347 case AARCH64_OPND_SVE_UIMM3:
3348 case AARCH64_OPND_SVE_UIMM7:
3349 case AARCH64_OPND_SVE_UIMM8:
3350 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3351 case AARCH64_OPND_IMM_ROT1:
3352 case AARCH64_OPND_IMM_ROT2:
3353 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3354 case AARCH64_OPND_SVE_IMM_ROT1:
3355 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 3356 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC		 3357 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3358 break;
3359
165d4950
RS		 3360 case AARCH64_OPND_SVE_I1_HALF_ONE:
3361 case AARCH64_OPND_SVE_I1_HALF_TWO:
3362 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3363 {
3364 single_conv_t c;
3365 c.i = opnd->imm.value;
3366 snprintf (buf, size, "#%.1f", c.f);
3367 break;
3368 }
3369
245d2e3f
RS		 3370 case AARCH64_OPND_SVE_PATTERN:
3371 if (optional_operand_p (opcode, idx)
3372 && opnd->imm.value == get_optional_operand_default_value (opcode))
3373 break;
3374 enum_value = opnd->imm.value;
3375 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3376 if (aarch64_sve_pattern_array[enum_value])
3377 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3378 else
3379 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3380 break;
3381
2442d846
RS		 3382 case AARCH64_OPND_SVE_PATTERN_SCALED:
3383 if (optional_operand_p (opcode, idx)
3384 && !opnd->shifter.operator_present
3385 && opnd->imm.value == get_optional_operand_default_value (opcode))
3386 break;
3387 enum_value = opnd->imm.value;
3388 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3389 if (aarch64_sve_pattern_array[opnd->imm.value])
3390 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3391 else
3392 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3393 if (opnd->shifter.operator_present)
3394 {
3395 size_t len = strlen (buf);
3396 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3397 aarch64_operand_modifiers[opnd->shifter.kind].name,
3398 opnd->shifter.amount);
3399 }
3400 break;
3401
245d2e3f
RS		 3402 case AARCH64_OPND_SVE_PRFOP:
3403 enum_value = opnd->imm.value;
3404 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3405 if (aarch64_sve_prfop_array[enum_value])
3406 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3407 else
3408 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3409 break;
3410
fb098a1e
YZ		 3411 case AARCH64_OPND_IMM_MOV:
3412 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3413 {
3414 case 4: /* e.g. MOV Wd, #<imm32>. */
3415 {
3416 int imm32 = opnd->imm.value;
3417 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3418 }
3419 break;
3420 case 8: /* e.g. MOV Xd, #<imm64>. */
3421 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3422 opnd->imm.value, opnd->imm.value);
3423 break;
3424 default: assert (0);
3425 }
3426 break;
3427
a06ea964
NC		 3428 case AARCH64_OPND_FPIMM0:
3429 snprintf (buf, size, "#0.0");
3430 break;
3431
3432 case AARCH64_OPND_LIMM:
3433 case AARCH64_OPND_AIMM:
3434 case AARCH64_OPND_HALF:
e950b345
RS		 3435 case AARCH64_OPND_SVE_INV_LIMM:
3436 case AARCH64_OPND_SVE_LIMM:
3437 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3438 if (opnd->shifter.amount)
2442d846 3439 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3440 opnd->shifter.amount);
3441 else
3442 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3443 break;
3444
3445 case AARCH64_OPND_SIMD_IMM:
3446 case AARCH64_OPND_SIMD_IMM_SFT:
3447 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3448 || opnd->shifter.kind == AARCH64_MOD_NONE)
3449 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3450 else
2442d846 3451 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3452 aarch64_operand_modifiers[opnd->shifter.kind].name,
3453 opnd->shifter.amount);
3454 break;
3455
e950b345
RS		 3456 case AARCH64_OPND_SVE_AIMM:
3457 case AARCH64_OPND_SVE_ASIMM:
3458 if (opnd->shifter.amount)
3459 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3460 opnd->shifter.amount);
3461 else
3462 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3463 break;
3464
a06ea964
NC		 3465 case AARCH64_OPND_FPIMM:
3466 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3467 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3468 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3469 {
cf86120b
MW		 3470 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3471 {
3472 half_conv_t c;
3473 c.i = expand_fp_imm (2, opnd->imm.value);
3474 snprintf (buf, size, "#%.18e", c.f);
3475 }
3476 break;
a06ea964
NC		 3477 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3478 {
3479 single_conv_t c;
cf86120b 3480 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3481 snprintf (buf, size, "#%.18e", c.f);
3482 }
3483 break;
3484 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3485 {
3486 double_conv_t c;
cf86120b 3487 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3488 snprintf (buf, size, "#%.18e", c.d);
3489 }
3490 break;
3491 default: assert (0);
3492 }
3493 break;
3494
3495 case AARCH64_OPND_CCMP_IMM:
3496 case AARCH64_OPND_NZCV:
3497 case AARCH64_OPND_EXCEPTION:
3498 case AARCH64_OPND_UIMM4:
193614f2 3499 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3500 case AARCH64_OPND_UIMM7:
193614f2 3501 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3502 if (optional_operand_p (opcode, idx) == TRUE
3503 && (opnd->imm.value ==
3504 (int64_t) get_optional_operand_default_value (opcode)))
3505 /* Omit the operand, e.g. DCPS1. */
3506 break;
3507 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3508 break;
3509
3510 case AARCH64_OPND_COND:
68a64283 3511 case AARCH64_OPND_COND1:
a06ea964 3512 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3513 num_conds = ARRAY_SIZE (opnd->cond->names);
3514 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3515 {
3516 size_t len = strlen (buf);
3517 if (i == 1)
3518 snprintf (buf + len, size - len, " // %s = %s",
3519 opnd->cond->names[0], opnd->cond->names[i]);
3520 else
3521 snprintf (buf + len, size - len, ", %s",
3522 opnd->cond->names[i]);
3523 }
a06ea964
NC		 3524 break;
3525
3526 case AARCH64_OPND_ADDR_ADRP:
3527 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3528 + opnd->imm.value;
3529 if (pcrel_p)
3530 *pcrel_p = 1;
3531 if (address)
3532 *address = addr;
3533 /* This is not necessary during the disassembling, as print_address_func
3534 in the disassemble_info will take care of the printing. But some
3535 other callers may be still interested in getting the string in *STR,
3536 so here we do snprintf regardless. */
3537 snprintf (buf, size, "#0x%" PRIx64, addr);
3538 break;
3539
3540 case AARCH64_OPND_ADDR_PCREL14:
3541 case AARCH64_OPND_ADDR_PCREL19:
3542 case AARCH64_OPND_ADDR_PCREL21:
3543 case AARCH64_OPND_ADDR_PCREL26:
3544 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3545 if (pcrel_p)
3546 *pcrel_p = 1;
3547 if (address)
3548 *address = addr;
3549 /* This is not necessary during the disassembling, as print_address_func
3550 in the disassemble_info will take care of the printing. But some
3551 other callers may be still interested in getting the string in *STR,
3552 so here we do snprintf regardless. */
3553 snprintf (buf, size, "#0x%" PRIx64, addr);
3554 break;
3555
3556 case AARCH64_OPND_ADDR_SIMPLE:
3557 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3558 case AARCH64_OPND_SIMD_ADDR_POST:
3559 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3560 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3561 {
3562 if (opnd->addr.offset.is_reg)
3563 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3564 else
3565 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3566 }
3567 else
3568 snprintf (buf, size, "[%s]", name);
3569 break;
3570
3571 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3572 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3573 case AARCH64_OPND_SVE_ADDR_RR:
3574 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3575 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3576 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3577 case AARCH64_OPND_SVE_ADDR_RX:
3578 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3579 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3580 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3581 print_register_offset_address
3582 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3583 get_offset_int_reg_name (opnd));
a06ea964
NC		 3584 break;
3585
4df068de
RS		 3586 case AARCH64_OPND_SVE_ADDR_RZ:
3587 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3588 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3589 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3590 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3591 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3592 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3593 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3594 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3595 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3596 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3597 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3598 print_register_offset_address
3599 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3600 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3601 break;
3602
a06ea964
NC		 3603 case AARCH64_OPND_ADDR_SIMM7:
3604 case AARCH64_OPND_ADDR_SIMM9:
3605 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3606 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3607 case AARCH64_OPND_ADDR_SIMM11:
3608 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3609 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3610 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
98907a70
RS		 3611 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3612 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3613 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3614 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3615 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3616 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3617 case AARCH64_OPND_SVE_ADDR_RI_U6:
3618 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3619 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3620 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3621 print_immediate_offset_address
3622 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3623 break;
3624
4df068de
RS		 3625 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3626 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3627 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3628 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3629 print_immediate_offset_address
3630 (buf, size, opnd,
3631 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3632 break;
3633
3634 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3635 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3636 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3637 print_register_offset_address
3638 (buf, size, opnd,
3639 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3640 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3641 break;
3642
a06ea964
NC		 3643 case AARCH64_OPND_ADDR_UIMM12:
3644 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3645 if (opnd->addr.offset.imm)
ad43e107 3646 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3647 else
3648 snprintf (buf, size, "[%s]", name);
3649 break;
3650
3651 case AARCH64_OPND_SYSREG:
3652 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3653 {
3654 bfd_boolean exact_match
3655 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3656 == opnd->sysreg.flags;
3657
3658 /* Try and find an exact match, But if that fails, return the first
3659 partial match that was found. */
3660 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3661 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3662 && (name == NULL || exact_match))
3663 {
3664 name = aarch64_sys_regs[i].name;
3665 if (exact_match)
3666 {
3667 if (notes)
3668 *notes = NULL;
3669 break;
3670 }
3671
3672 /* If we didn't match exactly, that means the presense of a flag
3673 indicates what we didn't want for this instruction. e.g. If
3674 F_REG_READ is there, that means we were looking for a write
3675 register. See aarch64_ext_sysreg. */
3676 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3677 *notes = _("reading from a write-only register");
f9830ec1 3678 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3679 *notes = _("writing to a read-only register");
f9830ec1
TC		 3680 }
3681 }
3682
3683 if (name)
3684 snprintf (buf, size, "%s", name);
a06ea964
NC		 3685 else
3686 {
3687 /* Implementation defined system register. */
561a72d4 3688 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3689 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3690 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3691 value & 0x7);
3692 }
3693 break;
3694
3695 case AARCH64_OPND_PSTATEFIELD:
3696 for (i = 0; aarch64_pstatefields[i].name; ++i)
3697 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3698 break;
3699 assert (aarch64_pstatefields[i].name);
3700 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3701 break;
3702
3703 case AARCH64_OPND_SYSREG_AT:
3704 case AARCH64_OPND_SYSREG_DC:
3705 case AARCH64_OPND_SYSREG_IC:
3706 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3707 case AARCH64_OPND_SYSREG_SR:
875880c6 3708 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3709 break;
3710
3711 case AARCH64_OPND_BARRIER:
3712 snprintf (buf, size, "%s", opnd->barrier->name);
3713 break;
3714
3715 case AARCH64_OPND_BARRIER_ISB:
3716 /* Operand can be omitted, e.g. in DCPS1. */
3717 if (! optional_operand_p (opcode, idx)
3718 || (opnd->barrier->value
3719 != get_optional_operand_default_value (opcode)))
3720 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3721 break;
3722
3723 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3724 if (opnd->prfop->name != NULL)
3725 snprintf (buf, size, "%s", opnd->prfop->name);
3726 else
3727 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3728 break;
3729
1e6f4800 3730 case AARCH64_OPND_BARRIER_PSB:
ff605452
SD		 3731 case AARCH64_OPND_BTI_TARGET:
3732 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3733 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3734 break;
3735
a06ea964
NC		 3736 default:
3737 assert (0);
3738 }
3739}
3740\f
3741#define CPENC(op0,op1,crn,crm,op2) \
3742 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3743 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3744#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3745 /* for 3.9.10 System Instructions */
3746#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3747
3748#define C0 0
3749#define C1 1
3750#define C2 2
3751#define C3 3
3752#define C4 4
3753#define C5 5
3754#define C6 6
3755#define C7 7
3756#define C8 8
3757#define C9 9
3758#define C10 10
3759#define C11 11
3760#define C12 12
3761#define C13 13
3762#define C14 14
3763#define C15 15
3764
f9830ec1
TC		 3765/* TODO there is one more issues need to be resolved
3766 1. handle cpu-implementation-defined system registers. */
49eec193
YZ		 3767const aarch64_sys_reg aarch64_sys_regs [] =
3768{
3769 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
250aafa4 3770 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
49eec193 3771 { "elr_el1", CPEN_(0,C0,1), 0 },
250aafa4 3772 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
49eec193
YZ		 3773 { "sp_el0", CPEN_(0,C1,0), 0 },
3774 { "spsel", CPEN_(0,C2,0), 0 },
3775 { "daif", CPEN_(3,C2,1), 0 },
f9830ec1 3776 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
f21cce2c 3777 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
6479e48e 3778 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
49eec193 3779 { "nzcv", CPEN_(3,C2,0), 0 },
104fefee 3780 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
49eec193
YZ		 3781 { "fpcr", CPEN_(3,C4,0), 0 },
3782 { "fpsr", CPEN_(3,C4,1), 0 },
3783 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3784 { "dlr_el0", CPEN_(3,C5,1), 0 },
3785 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3786 { "elr_el2", CPEN_(4,C0,1), 0 },
3787 { "sp_el1", CPEN_(4,C1,0), 0 },
3788 { "spsr_irq", CPEN_(4,C3,0), 0 },
3789 { "spsr_abt", CPEN_(4,C3,1), 0 },
3790 { "spsr_und", CPEN_(4,C3,2), 0 },
3791 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3792 { "spsr_el3", CPEN_(6,C0,0), 0 },
3793 { "elr_el3", CPEN_(6,C0,1), 0 },
3794 { "sp_el2", CPEN_(6,C1,0), 0 },
3795 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3796 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
f9830ec1
TC		 3797 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3798 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3799 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3800 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3801 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3802 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3803 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3804 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3805 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
a97330e7 3806 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
f9830ec1
TC		 3807 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3808 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3809 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3810 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3811 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3812 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3813 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3814 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3815 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3816 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3817 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3818 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3819 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3820 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3821 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3822 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3823 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3824 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3825 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3826 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3827 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3828 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3829 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3830 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3831 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3832 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3833 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3834 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3835 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
cba05feb 3836 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
49eec193
YZ		 3837 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3838 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3839 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3840 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3841 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
250aafa4 3842 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
49eec193
YZ		 3843 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3844 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3845 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3846 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
250aafa4 3847 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
49eec193
YZ		 3848 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3849 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3850 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3851 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3852 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3853 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3854 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3855 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
773fb663
RS		 3856 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3857 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3858 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3859 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3860 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
49eec193
YZ		 3861 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3862 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3863 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
250aafa4 3864 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
49eec193 3865 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
250aafa4
MW		 3866 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3867 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
49eec193
YZ		 3868 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3869 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3870 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3871 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
250aafa4 3872 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
49eec193 3873 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
b0bfa7b5
SN		 3874 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3875 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3876 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3877 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3878 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3879 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3880 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3881 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3882 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3883 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
49eec193
YZ		 3884 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3885 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3886 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3887 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3888 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
250aafa4 3889 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
49eec193 3890 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
250aafa4 3891 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
49eec193
YZ		 3892 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3893 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3894 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
250aafa4 3895 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
cba05feb 3896 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
49eec193 3897 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
f9830ec1 3898 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142 3899 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
f9830ec1 3900 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142
MW		 3901 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3902 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3903 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3904 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3905 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
49eec193
YZ		 3906 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3907 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3908 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
250aafa4 3909 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
49eec193
YZ		 3910 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3911 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3912 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3913 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3914 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
250aafa4 3915 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
49eec193
YZ		 3916 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3917 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3918 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
250aafa4 3919 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
49eec193
YZ		 3920 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3921 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3922 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
250aafa4 3923 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
f9830ec1
TC		 3924 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3925 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3926 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
49eec193
YZ		 3927 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3928 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3929 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
f9830ec1 3930 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
47f81142
MW		 3931 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3932 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
49eec193 3933 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
250aafa4
MW		 3934 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3935 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
af4bcb4c
SD		 3936 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3937 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
70f3d23a
SD		 3938 { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
3939 { "tfsre0_el1", CPENC(3,0,C6,C6,1), F_ARCHEXT },
3940 { "tfsr_el1", CPENC(3,0,C6,C5,0), F_ARCHEXT },
3941 { "tfsr_el2", CPENC(3,4,C6,C5,0), F_ARCHEXT },
3942 { "tfsr_el3", CPENC(3,6,C6,C6,0), F_ARCHEXT },
3943 { "tfsr_el12", CPENC(3,5,C6,C6,0), F_ARCHEXT },
3944 { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
3945 { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
49eec193 3946 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
f9830ec1 3947 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
49eec193
YZ		 3948 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3949 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3950 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
a97330e7
SD		 3951 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3952 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3953 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3954 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3955 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
49eec193 3956 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
f9830ec1
TC		 3957 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3958 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3959 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
49eec193
YZ		 3960 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
3961 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
250aafa4 3962 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
49eec193
YZ		 3963 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
3964 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
250aafa4 3965 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
49eec193 3966 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
250aafa4 3967 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
49eec193 3968 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
250aafa4 3969 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
49eec193 3970 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
250aafa4 3971 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
49eec193 3972 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
250aafa4 3973 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
49eec193 3974 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
250aafa4 3975 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 3976 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
3977 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
3978 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
3979 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
3980 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
3981 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
250aafa4
MW		 3982 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
3983 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
3984 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 3985 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
3986 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
3987 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
3988 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
3989 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
f9830ec1 3990 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
49eec193
YZ		 3991 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
3992 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
f9830ec1
TC		 3993 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
3994 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
cba05feb
TC		 3995 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
3996 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
49eec193
YZ		 3997 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
3998 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
3999 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
4000 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
4001 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
4002 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
4003 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
4004 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
4005 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
4006 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
4007 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
4008 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
4009 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
4010 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
4011 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
4012 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
4013 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4014 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4015 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4016 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4017 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4018 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4019 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4020 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4021 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4022 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4023 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4024 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4025 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4026 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4027 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4028 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4029 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4030 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4031 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4032 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4033 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4034 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4035 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4036 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4037 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4038 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4039 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4040 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4041 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4042 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4043 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4044 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4045 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4046 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4047 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4048 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4049 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4050 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4051 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4052 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4053 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4054 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4055 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4056 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4057 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4058 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4059 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4060 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4061 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4062 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
f9830ec1
TC		 4063 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4064 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4065 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
49eec193
YZ		 4066 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4067 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4068 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4069 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
f9830ec1 4070 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
55c144e6
MW		 4071 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4072 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4073 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
f9830ec1 4074 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
55c144e6
MW		 4075 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4076 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4077 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4078 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4079 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4080 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
cba05feb 4081 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
55c144e6
MW		 4082 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4083 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
49eec193
YZ		 4084 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4085 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4086 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4087 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
f9830ec1 4088 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
49eec193 4089 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
f9830ec1
TC		 4090 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4091 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
49eec193
YZ		 4092 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4093 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4094 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4095 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4096 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4097 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4098 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4099 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4100 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4101 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4102 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4103 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4104 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4105 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4106 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4107 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4108 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4109 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4110 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4111 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4112 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4113 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4114 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4115 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4116 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4117 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4118 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4119 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4120 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4121 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4122 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4123 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4124 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4125 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4126 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4127 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4128 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4129 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4130 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4131 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4132 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4133 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4134 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4135 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4136 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4137 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4138 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4139 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4140 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4141 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4142 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4143 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4144 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4145 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4146 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4147 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4148 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4149 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4150 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4151 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4152 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4153 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4154 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4155 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4156 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4157 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4158 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4159 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4160 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4161 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
793a1948
TC		 4162
4163 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4164 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4165 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4166 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4167 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4168 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4169 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4170 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4171 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4172 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4173 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
49eec193 4174 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4175};
4176
49eec193
YZ		 4177bfd_boolean
4178aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4179{
4180 return (reg->flags & F_DEPRECATED) != 0;
4181}
4182
f21cce2c
MW		 4183bfd_boolean
4184aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4185 const aarch64_sys_reg *reg)
4186{
4187 if (!(reg->flags & F_ARCHEXT))
4188 return TRUE;
4189
4190 /* PAN. Values are from aarch64_sys_regs. */
4191 if (reg->value == CPEN_(0,C2,3)
4192 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4193 return FALSE;
4194
a97330e7
SD		 4195 /* SCXTNUM_ELx registers. */
4196 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4197 || reg->value == CPENC (3, 0, C13, C0, 7)
4198 || reg->value == CPENC (3, 4, C13, C0, 7)
4199 || reg->value == CPENC (3, 6, C13, C0, 7)
4200 || reg->value == CPENC (3, 5, C13, C0, 7))
4201 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4202 return FALSE;
4203
4204 /* ID_PFR2_EL1 register. */
4205 if (reg->value == CPENC(3, 0, C0, C3, 4)
4206 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4207 return FALSE;
4208
104fefee
SD		 4209 /* SSBS. Values are from aarch64_sys_regs. */
4210 if (reg->value == CPEN_(3,C2,6)
4211 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4212 return FALSE;
4213
250aafa4
MW		 4214 /* Virtualization host extensions: system registers. */
4215 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4216 || reg->value == CPENC (3, 4, C13, C0, 1)
4217 || reg->value == CPENC (3, 4, C14, C3, 0)
4218 || reg->value == CPENC (3, 4, C14, C3, 1)
4219 || reg->value == CPENC (3, 4, C14, C3, 2))
4220 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4221 return FALSE;
4222
4223 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4224 if ((reg->value == CPEN_ (5, C0, 0)
4225 || reg->value == CPEN_ (5, C0, 1)
4226 || reg->value == CPENC (3, 5, C1, C0, 0)
4227 || reg->value == CPENC (3, 5, C1, C0, 2)
4228 || reg->value == CPENC (3, 5, C2, C0, 0)
4229 || reg->value == CPENC (3, 5, C2, C0, 1)
4230 || reg->value == CPENC (3, 5, C2, C0, 2)
4231 || reg->value == CPENC (3, 5, C5, C1, 0)
4232 || reg->value == CPENC (3, 5, C5, C1, 1)
4233 || reg->value == CPENC (3, 5, C5, C2, 0)
4234 || reg->value == CPENC (3, 5, C6, C0, 0)
4235 || reg->value == CPENC (3, 5, C10, C2, 0)
4236 || reg->value == CPENC (3, 5, C10, C3, 0)
4237 || reg->value == CPENC (3, 5, C12, C0, 0)
4238 || reg->value == CPENC (3, 5, C13, C0, 1)
4239 || reg->value == CPENC (3, 5, C14, C1, 0))
4240 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4241 return FALSE;
4242
4243 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4244 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4245 || reg->value == CPENC (3, 5, C14, C2, 1)
4246 || reg->value == CPENC (3, 5, C14, C2, 2)
4247 || reg->value == CPENC (3, 5, C14, C3, 0)
4248 || reg->value == CPENC (3, 5, C14, C3, 1)
4249 || reg->value == CPENC (3, 5, C14, C3, 2))
4250 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
63511907 4251 return FALSE;
1a04d1a7
MW		 4252
4253 /* ARMv8.2 features. */
6479e48e
MW		 4254
4255 /* ID_AA64MMFR2_EL1. */
1a04d1a7
MW		 4256 if (reg->value == CPENC (3, 0, C0, C7, 2)
4257 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
250aafa4
MW		 4258 return FALSE;
4259
6479e48e
MW		 4260 /* PSTATE.UAO. */
4261 if (reg->value == CPEN_ (0, C2, 4)
4262 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4263 return FALSE;
4264
47f81142
MW		 4265 /* RAS extension. */
4266
651657fa
MW		 4267 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4268 ERXMISC0_EL1 AND ERXMISC1_EL1. */
47f81142 4269 if ((reg->value == CPENC (3, 0, C5, C3, 0)
651657fa 4270 || reg->value == CPENC (3, 0, C5, C3, 1)
47f81142
MW		 4271 || reg->value == CPENC (3, 0, C5, C3, 2)
4272 || reg->value == CPENC (3, 0, C5, C3, 3)
651657fa
MW		 4273 || reg->value == CPENC (3, 0, C5, C4, 0)
4274 || reg->value == CPENC (3, 0, C5, C4, 1)
4275 || reg->value == CPENC (3, 0, C5, C4, 2)
4276 || reg->value == CPENC (3, 0, C5, C4, 3)
47f81142
MW		 4277 || reg->value == CPENC (3, 0, C5, C5, 0)
4278 || reg->value == CPENC (3, 0, C5, C5, 1))
4279 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4280 return FALSE;
4281
4282 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4283 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4284 || reg->value == CPENC (3, 0, C12, C1, 1)
4285 || reg->value == CPENC (3, 4, C12, C1, 1))
4286 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4287 return FALSE;
4288
55c144e6
MW		 4289 /* Statistical Profiling extension. */
4290 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4291 || reg->value == CPENC (3, 0, C9, C10, 1)
4292 || reg->value == CPENC (3, 0, C9, C10, 3)
4293 || reg->value == CPENC (3, 0, C9, C10, 7)
4294 || reg->value == CPENC (3, 0, C9, C9, 0)
4295 || reg->value == CPENC (3, 0, C9, C9, 2)
4296 || reg->value == CPENC (3, 0, C9, C9, 3)
4297 || reg->value == CPENC (3, 0, C9, C9, 4)
4298 || reg->value == CPENC (3, 0, C9, C9, 5)
4299 || reg->value == CPENC (3, 0, C9, C9, 6)
4300 || reg->value == CPENC (3, 0, C9, C9, 7)
4301 || reg->value == CPENC (3, 4, C9, C9, 0)
4302 || reg->value == CPENC (3, 5, C9, C9, 0))
4303 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4304 return FALSE;
4305
b0bfa7b5
SN		 4306 /* ARMv8.3 Pointer authentication keys. */
4307 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4308 || reg->value == CPENC (3, 0, C2, C1, 1)
4309 || reg->value == CPENC (3, 0, C2, C1, 2)
4310 || reg->value == CPENC (3, 0, C2, C1, 3)
4311 || reg->value == CPENC (3, 0, C2, C2, 0)
4312 || reg->value == CPENC (3, 0, C2, C2, 1)
4313 || reg->value == CPENC (3, 0, C2, C2, 2)
4314 || reg->value == CPENC (3, 0, C2, C2, 3)
4315 || reg->value == CPENC (3, 0, C2, C3, 0)
4316 || reg->value == CPENC (3, 0, C2, C3, 1))
4317 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4318 return FALSE;
4319
773fb663
RS		 4320 /* SVE. */
4321 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4322 || reg->value == CPENC (3, 0, C1, C2, 0)
4323 || reg->value == CPENC (3, 4, C1, C2, 0)
4324 || reg->value == CPENC (3, 6, C1, C2, 0)
4325 || reg->value == CPENC (3, 5, C1, C2, 0)
4326 || reg->value == CPENC (3, 0, C0, C0, 7))
4327 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4328 return FALSE;
4329
793a1948
TC		 4330 /* ARMv8.4 features. */
4331
4332 /* PSTATE.DIT. */
4333 if (reg->value == CPEN_ (3, C2, 5)
4334 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4335 return FALSE;
4336
4337 /* Virtualization extensions. */
4338 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4339 || reg->value == CPENC(3, 4, C2, C6, 0)
4340 || reg->value == CPENC(3, 4, C14, C4, 0)
4341 || reg->value == CPENC(3, 4, C14, C4, 2)
4342 || reg->value == CPENC(3, 4, C14, C4, 1)
4343 || reg->value == CPENC(3, 4, C14, C5, 0)
4344 || reg->value == CPENC(3, 4, C14, C5, 2)
4345 || reg->value == CPENC(3, 4, C14, C5, 1)
4346 || reg->value == CPENC(3, 4, C1, C3, 1)
4347 || reg->value == CPENC(3, 4, C2, C2, 0))
4348 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4349 return FALSE;
4350
4351 /* ARMv8.4 TLB instructions. */
4352 if ((reg->value == CPENS (0, C8, C1, 0)
4353 || reg->value == CPENS (0, C8, C1, 1)
4354 || reg->value == CPENS (0, C8, C1, 2)
4355 || reg->value == CPENS (0, C8, C1, 3)
4356 || reg->value == CPENS (0, C8, C1, 5)
4357 || reg->value == CPENS (0, C8, C1, 7)
4358 || reg->value == CPENS (4, C8, C4, 0)
4359 || reg->value == CPENS (4, C8, C4, 4)
4360 || reg->value == CPENS (4, C8, C1, 1)
4361 || reg->value == CPENS (4, C8, C1, 5)
4362 || reg->value == CPENS (4, C8, C1, 6)
4363 || reg->value == CPENS (6, C8, C1, 1)
4364 || reg->value == CPENS (6, C8, C1, 5)
4365 || reg->value == CPENS (4, C8, C1, 0)
4366 || reg->value == CPENS (4, C8, C1, 4)
4367 || reg->value == CPENS (6, C8, C1, 0)
4368 || reg->value == CPENS (0, C8, C6, 1)
4369 || reg->value == CPENS (0, C8, C6, 3)
4370 || reg->value == CPENS (0, C8, C6, 5)
4371 || reg->value == CPENS (0, C8, C6, 7)
4372 || reg->value == CPENS (0, C8, C2, 1)
4373 || reg->value == CPENS (0, C8, C2, 3)
4374 || reg->value == CPENS (0, C8, C2, 5)
4375 || reg->value == CPENS (0, C8, C2, 7)
4376 || reg->value == CPENS (0, C8, C5, 1)
4377 || reg->value == CPENS (0, C8, C5, 3)
4378 || reg->value == CPENS (0, C8, C5, 5)
4379 || reg->value == CPENS (0, C8, C5, 7)
4380 || reg->value == CPENS (4, C8, C0, 2)
4381 || reg->value == CPENS (4, C8, C0, 6)
4382 || reg->value == CPENS (4, C8, C4, 2)
4383 || reg->value == CPENS (4, C8, C4, 6)
4384 || reg->value == CPENS (4, C8, C4, 3)
4385 || reg->value == CPENS (4, C8, C4, 7)
4386 || reg->value == CPENS (4, C8, C6, 1)
4387 || reg->value == CPENS (4, C8, C6, 5)
4388 || reg->value == CPENS (4, C8, C2, 1)
4389 || reg->value == CPENS (4, C8, C2, 5)
4390 || reg->value == CPENS (4, C8, C5, 1)
4391 || reg->value == CPENS (4, C8, C5, 5)
4392 || reg->value == CPENS (6, C8, C6, 1)
4393 || reg->value == CPENS (6, C8, C6, 5)
4394 || reg->value == CPENS (6, C8, C2, 1)
4395 || reg->value == CPENS (6, C8, C2, 5)
4396 || reg->value == CPENS (6, C8, C5, 1)
4397 || reg->value == CPENS (6, C8, C5, 5))
4398 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4399 return FALSE;
4400
af4bcb4c
SD		 4401 /* Random Number Instructions. For now they are available
4402 (and optional) only with ARMv8.5-A. */
4403 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4404 || reg->value == CPENC (3, 3, C2, C4, 1))
4405 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4406 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4407 return FALSE;
4408
70f3d23a
SD		 4409 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4410 if ((reg->value == CPENC (3, 3, C4, C2, 7)
4411 || reg->value == CPENC (3, 0, C6, C6, 1)
4412 || reg->value == CPENC (3, 0, C6, C5, 0)
4413 || reg->value == CPENC (3, 4, C6, C5, 0)
4414 || reg->value == CPENC (3, 6, C6, C6, 0)
4415 || reg->value == CPENC (3, 5, C6, C6, 0)
4416 || reg->value == CPENC (3, 0, C1, C0, 5)
4417 || reg->value == CPENC (3, 0, C1, C0, 6))
4418 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
4419 return FALSE;
4420
f21cce2c
MW		 4421 return TRUE;
4422}
4423
793a1948
TC		 4424/* The CPENC below is fairly misleading, the fields
4425 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4426 by ins_pstatefield, which just shifts the value by the width of the fields
4427 in a loop. So if you CPENC them only the first value will be set, the rest
4428 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4429 value of 0b110000000001000000 (0x30040) while what you want is
4430 0b011010 (0x1a). */
87b8eed7 4431const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4432{
87b8eed7
YZ		 4433 { "spsel", 0x05, 0 },
4434 { "daifset", 0x1e, 0 },
4435 { "daifclr", 0x1f, 0 },
f21cce2c 4436 { "pan", 0x04, F_ARCHEXT },
6479e48e 4437 { "uao", 0x03, F_ARCHEXT },
104fefee 4438 { "ssbs", 0x19, F_ARCHEXT },
793a1948 4439 { "dit", 0x1a, F_ARCHEXT },
70f3d23a 4440 { "tco", 0x1c, F_ARCHEXT },
87b8eed7 4441 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4442};
4443
f21cce2c
MW		 4444bfd_boolean
4445aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4446 const aarch64_sys_reg *reg)
4447{
4448 if (!(reg->flags & F_ARCHEXT))
4449 return TRUE;
4450
4451 /* PAN. Values are from aarch64_pstatefields. */
4452 if (reg->value == 0x04
4453 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4454 return FALSE;
4455
6479e48e
MW		 4456 /* UAO. Values are from aarch64_pstatefields. */
4457 if (reg->value == 0x03
4458 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4459 return FALSE;
4460
104fefee
SD		 4461 /* SSBS. Values are from aarch64_pstatefields. */
4462 if (reg->value == 0x19
4463 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4464 return FALSE;
4465
793a1948
TC		 4466 /* DIT. Values are from aarch64_pstatefields. */
4467 if (reg->value == 0x1a
4468 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4469 return FALSE;
4470
70f3d23a
SD		 4471 /* TCO. Values are from aarch64_pstatefields. */
4472 if (reg->value == 0x1c
4473 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4474 return FALSE;
4475
f21cce2c
MW		 4476 return TRUE;
4477}
4478
a06ea964
NC		 4479const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4480{
4481 { "ialluis", CPENS(0,C7,C1,0), 0 },
4482 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4483 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4484 { 0, CPENS(0,0,0,0), 0 }
4485};
4486
4487const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4488{
ea2deeec 4489 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4490 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4491 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4492 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4493 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4494 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4495 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4496 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4497 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4498 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4499 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4500 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4501 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4502 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4503 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4504 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4505 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4506 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4507 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4508 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4509 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4510 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4511 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4512 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4513 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4514 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4515 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4516 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4517 { 0, CPENS(0,0,0,0), 0 }
4518};
4519
4520const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4521{
ea2deeec
MW		 4522 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4523 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4524 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4525 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4526 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4527 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4528 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4529 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4530 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4531 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4532 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4533 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4534 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4535 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4536 { 0, CPENS(0,0,0,0), 0 }
4537};
4538
4539const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4540{
4541 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4542 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4543 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4544 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4545 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4546 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4547 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4548 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4549 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4550 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4551 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4552 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4553 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4554 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4555 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4556 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4557 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4558 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4559 { "alle2", CPENS(4,C8,C7,0), 0 },
4560 { "alle2is", CPENS(4,C8,C3,0), 0 },
4561 { "alle1", CPENS(4,C8,C7,4), 0 },
4562 { "alle1is", CPENS(4,C8,C3,4), 0 },
4563 { "alle3", CPENS(6,C8,C7,0), 0 },
4564 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4565 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4566 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4567 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4568 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4569 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4570 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4571 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4572 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4573
4574 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4575 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4576 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4577 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4578 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4579 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4580 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4581 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4582 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4583 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4584 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4585 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4586 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4587 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4588 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4589 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4590
4591 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4592 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4593 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4594 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4595 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4596 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4597 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4598 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4599 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4600 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4601 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4602 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4603 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4604 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4605 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4606 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4607 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4608 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4609 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4610 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4611 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4612 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4613 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4614 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4615 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4616 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4617 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4618 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4619 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4620 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4621
a06ea964
NC		 4622 { 0, CPENS(0,0,0,0), 0 }
4623};
4624
2ac435d4
SD		 4625const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4626{
4627 /* RCTX is somewhat unique in a way that it has different values
4628 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4629 Thus op2 is masked out and instead encoded directly in the
4630 aarch64_opcode_table entries for the respective instructions. */
4631 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4632
4633 { 0, CPENS(0,0,0,0), 0 }
4634};
4635
ea2deeec
MW		 4636bfd_boolean
4637aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4638{
4639 return (sys_ins_reg->flags & F_HASXT) != 0;
4640}
4641
d6bf7ce6
MW		 4642extern bfd_boolean
4643aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4644 const aarch64_sys_ins_reg *reg)
4645{
4646 if (!(reg->flags & F_ARCHEXT))
4647 return TRUE;
4648
4649 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4650 if (reg->value == CPENS (3, C7, C12, 1)
4651 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4652 return FALSE;
4653
3fd229a4
SD		 4654 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4655 if (reg->value == CPENS (3, C7, C13, 1)
4656 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4657 return FALSE;
4658
3a0f69be
SD		 4659 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4660 if ((reg->value == CPENS (0, C7, C6, 3)
4661 || reg->value == CPENS (0, C7, C6, 4)
4662 || reg->value == CPENS (0, C7, C10, 4)
4663 || reg->value == CPENS (0, C7, C14, 4)
4664 || reg->value == CPENS (3, C7, C10, 3)
4665 || reg->value == CPENS (3, C7, C12, 3)
4666 || reg->value == CPENS (3, C7, C13, 3)
4667 || reg->value == CPENS (3, C7, C14, 3)
4668 || reg->value == CPENS (3, C7, C4, 3)
4669 || reg->value == CPENS (0, C7, C6, 5)
4670 || reg->value == CPENS (0, C7, C6, 6)
4671 || reg->value == CPENS (0, C7, C10, 6)
4672 || reg->value == CPENS (0, C7, C14, 6)
4673 || reg->value == CPENS (3, C7, C10, 5)
4674 || reg->value == CPENS (3, C7, C12, 5)
4675 || reg->value == CPENS (3, C7, C13, 5)
4676 || reg->value == CPENS (3, C7, C14, 5)
4677 || reg->value == CPENS (3, C7, C4, 4))
4678 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4679 return FALSE;
4680
63511907
MW		 4681 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4682 if ((reg->value == CPENS (0, C7, C9, 0)
4683 || reg->value == CPENS (0, C7, C9, 1))
4684 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4685 return FALSE;
4686
2ac435d4
SD		 4687 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4688 if (reg->value == CPENS (3, C7, C3, 0)
4689 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4690 return FALSE;
4691
d6bf7ce6
MW		 4692 return TRUE;
4693}
4694
a06ea964
NC		 4695#undef C0
4696#undef C1
4697#undef C2
4698#undef C3
4699#undef C4
4700#undef C5
4701#undef C6
4702#undef C7
4703#undef C8
4704#undef C9
4705#undef C10
4706#undef C11
4707#undef C12
4708#undef C13
4709#undef C14
4710#undef C15
4711
4bd13cde
NC		 4712#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4713#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4714
755b748f
TC		 4715static enum err_type
4716verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4717 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4718 bfd_boolean encoding ATTRIBUTE_UNUSED,
4719 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4720 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4721{
4722 int t = BITS (insn, 4, 0);
4723 int n = BITS (insn, 9, 5);
4724 int t2 = BITS (insn, 14, 10);
4725
4726 if (BIT (insn, 23))
4727 {
4728 /* Write back enabled. */
4729 if ((t == n || t2 == n) && n != 31)
755b748f 4730 return ERR_UND;
4bd13cde
NC		 4731 }
4732
4733 if (BIT (insn, 22))
4734 {
4735 /* Load */
4736 if (t == t2)
755b748f 4737 return ERR_UND;
4bd13cde
NC		 4738 }
4739
755b748f 4740 return ERR_OK;
4bd13cde
NC		 4741}
4742
6456d318
TC		 4743/* Verifier for vector by element 3 operands functions where the
4744 conditions `if sz:L == 11 then UNDEFINED` holds. */
4745
4746static enum err_type
4747verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
4748 bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
4749 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4750 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4751{
4752 const aarch64_insn undef_pattern = 0x3;
4753 aarch64_insn value;
4754
4755 assert (inst->opcode);
4756 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
4757 value = encoding ? inst->value : insn;
4758 assert (value);
4759
4760 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
4761 return ERR_UND;
4762
4763 return ERR_OK;
4764}
4765
a68f4cd2
TC		 4766/* Initialize an instruction sequence insn_sequence with the instruction INST.
4767 If INST is NULL the given insn_sequence is cleared and the sequence is left
4768 uninitialized. */
4769
4770void
4771init_insn_sequence (const struct aarch64_inst *inst,
4772 aarch64_instr_sequence *insn_sequence)
4773{
4774 int num_req_entries = 0;
4775 insn_sequence->next_insn = 0;
4776 insn_sequence->num_insns = num_req_entries;
4777 if (insn_sequence->instr)
4778 XDELETE (insn_sequence->instr);
4779 insn_sequence->instr = NULL;
4780
4781 if (inst)
4782 {
4783 insn_sequence->instr = XNEW (aarch64_inst);
4784 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4785 }
4786
4787 /* Handle all the cases here. May need to think of something smarter than
4788 a giant if/else chain if this grows. At that time, a lookup table may be
4789 best. */
4790 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4791 num_req_entries = 1;
4792
4793 if (insn_sequence->current_insns)
4794 XDELETEVEC (insn_sequence->current_insns);
4795 insn_sequence->current_insns = NULL;
4796
4797 if (num_req_entries != 0)
4798 {
4799 size_t size = num_req_entries * sizeof (aarch64_inst);
4800 insn_sequence->current_insns
4801 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4802 memset (insn_sequence->current_insns, 0, size);
4803 }
4804}
4805
4806
4807/* This function verifies that the instruction INST adheres to its specified
4808 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4809 returned and MISMATCH_DETAIL contains the reason why verification failed.
4810
4811 The function is called both during assembly and disassembly. If assembling
4812 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4813 and will contain the PC of the current instruction w.r.t to the section.
4814
4815 If ENCODING and PC=0 then you are at a start of a section. The constraints
4816 are verified against the given state insn_sequence which is updated as it
4817 transitions through the verification. */
4818
4819enum err_type
4820verify_constraints (const struct aarch64_inst *inst,
4821 const aarch64_insn insn ATTRIBUTE_UNUSED,
4822 bfd_vma pc,
4823 bfd_boolean encoding,
4824 aarch64_operand_error *mismatch_detail,
4825 aarch64_instr_sequence *insn_sequence)
4826{
4827 assert (inst);
4828 assert (inst->opcode);
4829
4830 const struct aarch64_opcode *opcode = inst->opcode;
4831 if (!opcode->constraints && !insn_sequence->instr)
4832 return ERR_OK;
4833
4834 assert (insn_sequence);
4835
4836 enum err_type res = ERR_OK;
4837
4838 /* This instruction puts a constraint on the insn_sequence. */
4839 if (opcode->flags & F_SCAN)
4840 {
4841 if (insn_sequence->instr)
4842 {
4843 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4844 mismatch_detail->error = _("instruction opens new dependency "
4845 "sequence without ending previous one");
4846 mismatch_detail->index = -1;
4847 mismatch_detail->non_fatal = TRUE;
4848 res = ERR_VFI;
4849 }
4850
4851 init_insn_sequence (inst, insn_sequence);
4852 return res;
4853 }
4854
4855 /* Verify constraints on an existing sequence. */
4856 if (insn_sequence->instr)
4857 {
4858 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4859 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4860 closed a previous one that we should have. */
4861 if (!encoding && pc == 0)
4862 {
4863 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4864 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4865 mismatch_detail->index = -1;
4866 mismatch_detail->non_fatal = TRUE;
4867 res = ERR_VFI;
4868 /* Reset the sequence. */
4869 init_insn_sequence (NULL, insn_sequence);
4870 return res;
4871 }
4872
4873 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4874 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4875 {
4876 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4877 instruction for better error messages. */
5cd99750
MM		 4878 if (!opcode->avariant
4879 || !(*opcode->avariant &
4880 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
a68f4cd2
TC		 4881 {
4882 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4883 mismatch_detail->error = _("SVE instruction expected after "
4884 "`movprfx'");
4885 mismatch_detail->index = -1;
4886 mismatch_detail->non_fatal = TRUE;
4887 res = ERR_VFI;
4888 goto done;
4889 }
4890
4891 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4892 instruction that is allowed to be used with a MOVPRFX. */
4893 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4894 {
4895 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4896 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4897 "expected");
4898 mismatch_detail->index = -1;
4899 mismatch_detail->non_fatal = TRUE;
4900 res = ERR_VFI;
4901 goto done;
4902 }
4903
4904 /* Next check for usage of the predicate register. */
4905 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4906 aarch64_opnd_info blk_pred, inst_pred;
4907 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4908 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4909 bfd_boolean predicated = FALSE;
4910 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4911
4912 /* Determine if the movprfx instruction used is predicated or not. */
4913 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4914 {
4915 predicated = TRUE;
4916 blk_pred = insn_sequence->instr->operands[1];
4917 }
4918
4919 unsigned char max_elem_size = 0;
4920 unsigned char current_elem_size;
4921 int num_op_used = 0, last_op_usage = 0;
4922 int i, inst_pred_idx = -1;
4923 int num_ops = aarch64_num_of_operands (opcode);
4924 for (i = 0; i < num_ops; i++)
4925 {
4926 aarch64_opnd_info inst_op = inst->operands[i];
4927 switch (inst_op.type)
4928 {
4929 case AARCH64_OPND_SVE_Zd:
4930 case AARCH64_OPND_SVE_Zm_5:
4931 case AARCH64_OPND_SVE_Zm_16:
4932 case AARCH64_OPND_SVE_Zn:
4933 case AARCH64_OPND_SVE_Zt:
4934 case AARCH64_OPND_SVE_Vm:
4935 case AARCH64_OPND_SVE_Vn:
4936 case AARCH64_OPND_Va:
4937 case AARCH64_OPND_Vn:
4938 case AARCH64_OPND_Vm:
4939 case AARCH64_OPND_Sn:
4940 case AARCH64_OPND_Sm:
4941 case AARCH64_OPND_Rn:
4942 case AARCH64_OPND_Rm:
4943 case AARCH64_OPND_Rn_SP:
bd7ceb8d 4944 case AARCH64_OPND_Rt_SP:
a68f4cd2
TC		 4945 case AARCH64_OPND_Rm_SP:
4946 if (inst_op.reg.regno == blk_dest.reg.regno)
4947 {
4948 num_op_used++;
4949 last_op_usage = i;
4950 }
4951 current_elem_size
4952 = aarch64_get_qualifier_esize (inst_op.qualifier);
4953 if (current_elem_size > max_elem_size)
4954 max_elem_size = current_elem_size;
4955 break;
4956 case AARCH64_OPND_SVE_Pd:
4957 case AARCH64_OPND_SVE_Pg3:
4958 case AARCH64_OPND_SVE_Pg4_5:
4959 case AARCH64_OPND_SVE_Pg4_10:
4960 case AARCH64_OPND_SVE_Pg4_16:
4961 case AARCH64_OPND_SVE_Pm:
4962 case AARCH64_OPND_SVE_Pn:
4963 case AARCH64_OPND_SVE_Pt:
4964 inst_pred = inst_op;
4965 inst_pred_idx = i;
4966 break;
4967 default:
4968 break;
4969 }
4970 }
4971
4972 assert (max_elem_size != 0);
4973 aarch64_opnd_info inst_dest = inst->operands[0];
4974 /* Determine the size that should be used to compare against the
4975 movprfx size. */
4976 current_elem_size
4977 = opcode->constraints & C_MAX_ELEM
4978 ? max_elem_size
4979 : aarch64_get_qualifier_esize (inst_dest.qualifier);
4980
4981 /* If movprfx is predicated do some extra checks. */
4982 if (predicated)
4983 {
4984 /* The instruction must be predicated. */
4985 if (inst_pred_idx < 0)
4986 {
4987 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4988 mismatch_detail->error = _("predicated instruction expected "
4989 "after `movprfx'");
4990 mismatch_detail->index = -1;
4991 mismatch_detail->non_fatal = TRUE;
4992 res = ERR_VFI;
4993 goto done;
4994 }
4995
4996 /* The instruction must have a merging predicate. */
4997 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
4998 {
4999 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5000 mismatch_detail->error = _("merging predicate expected due "
5001 "to preceding `movprfx'");
5002 mismatch_detail->index = inst_pred_idx;
5003 mismatch_detail->non_fatal = TRUE;
5004 res = ERR_VFI;
5005 goto done;
5006 }
5007
5008 /* The same register must be used in instruction. */
5009 if (blk_pred.reg.regno != inst_pred.reg.regno)
5010 {
5011 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5012 mismatch_detail->error = _("predicate register differs "
5013 "from that in preceding "
5014 "`movprfx'");
5015 mismatch_detail->index = inst_pred_idx;
5016 mismatch_detail->non_fatal = TRUE;
5017 res = ERR_VFI;
5018 goto done;
5019 }
5020 }
5021
5022 /* Destructive operations by definition must allow one usage of the
5023 same register. */
5024 int allowed_usage
5025 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
5026
5027 /* Operand is not used at all. */
5028 if (num_op_used == 0)
5029 {
5030 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5031 mismatch_detail->error = _("output register of preceding "
5032 "`movprfx' not used in current "
5033 "instruction");
5034 mismatch_detail->index = 0;
5035 mismatch_detail->non_fatal = TRUE;
5036 res = ERR_VFI;
5037 goto done;
5038 }
5039
5040 /* We now know it's used, now determine exactly where it's used. */
5041 if (blk_dest.reg.regno != inst_dest.reg.regno)
5042 {
5043 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5044 mismatch_detail->error = _("output register of preceding "
5045 "`movprfx' expected as output");
5046 mismatch_detail->index = 0;
5047 mismatch_detail->non_fatal = TRUE;
5048 res = ERR_VFI;
5049 goto done;
5050 }
5051
5052 /* Operand used more than allowed for the specific opcode type. */
5053 if (num_op_used > allowed_usage)
5054 {
5055 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5056 mismatch_detail->error = _("output register of preceding "
5057 "`movprfx' used as input");
5058 mismatch_detail->index = last_op_usage;
5059 mismatch_detail->non_fatal = TRUE;
5060 res = ERR_VFI;
5061 goto done;
5062 }
5063
5064 /* Now the only thing left is the qualifiers checks. The register
5065 must have the same maximum element size. */
5066 if (inst_dest.qualifier
5067 && blk_dest.qualifier
5068 && current_elem_size
5069 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5070 {
5071 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5072 mismatch_detail->error = _("register size not compatible with "
5073 "previous `movprfx'");
5074 mismatch_detail->index = 0;
5075 mismatch_detail->non_fatal = TRUE;
5076 res = ERR_VFI;
5077 goto done;
5078 }
5079 }
5080
5081done:
5082 /* Add the new instruction to the sequence. */
5083 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5084 inst, sizeof (aarch64_inst));
5085
5086 /* Check if sequence is now full. */
5087 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5088 {
5089 /* Sequence is full, but we don't have anything special to do for now,
5090 so clear and reset it. */
5091 init_insn_sequence (NULL, insn_sequence);
5092 }
5093 }
5094
5095 return res;
5096}
5097
5098
e950b345
RS		 5099/* Return true if VALUE cannot be moved into an SVE register using DUP
5100 (with any element size, not just ESIZE) and if using DUPM would
5101 therefore be OK. ESIZE is the number of bytes in the immediate. */
5102
5103bfd_boolean
5104aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5105{
5106 int64_t svalue = uvalue;
5107 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5108
5109 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5110 return FALSE;
5111 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5112 {
5113 svalue = (int32_t) uvalue;
5114 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5115 {
5116 svalue = (int16_t) uvalue;
5117 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5118 return FALSE;
5119 }
5120 }
5121 if ((svalue & 0xff) == 0)
5122 svalue /= 256;
5123 return svalue < -128 || svalue >= 128;
5124}
5125
a06ea964
NC		 5126/* Include the opcode description table as well as the operand description
5127 table. */
20f55f38 5128#define VERIFIER(x) verify_##x
a06ea964 5129#include "aarch64-tbl.h"
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