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Fix building the AArch64 assembler and disassembler when assertions are disabled.
[thirdparty/binutils-gdb.git] / opcodes / aarch64-opc.c
CommitLineData
a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
250d07de 2 Copyright (C) 2009-2021 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
3dfb1b6d 25#include <stdint.h>
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
78933a4a 35int debug_dump = false;
a06ea964
NC		 36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
78933a4a 105static inline bool
a06ea964
NC		 106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
63b4cc53
AM		 108 return (qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q);
a06ea964
NC		 110}
111
78933a4a 112static inline bool
a06ea964
NC		 113fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
114{
63b4cc53
AM		 115 return (qualifier >= AARCH64_OPND_QLF_S_B
116 && qualifier <= AARCH64_OPND_QLF_S_Q);
a06ea964
NC		 117}
118
119enum data_pattern
120{
121 DP_UNKNOWN,
122 DP_VECTOR_3SAME,
123 DP_VECTOR_LONG,
124 DP_VECTOR_WIDE,
125 DP_VECTOR_ACROSS_LANES,
126};
127
128static const char significant_operand_index [] =
129{
130 0, /* DP_UNKNOWN, by default using operand 0. */
131 0, /* DP_VECTOR_3SAME */
132 1, /* DP_VECTOR_LONG */
133 2, /* DP_VECTOR_WIDE */
134 1, /* DP_VECTOR_ACROSS_LANES */
135};
136
137/* Given a sequence of qualifiers in QUALIFIERS, determine and return
138 the data pattern.
139 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
140 corresponds to one of a sequence of operands. */
141
142static enum data_pattern
143get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
144{
63b4cc53 145 if (vector_qualifier_p (qualifiers[0]))
a06ea964
NC		 146 {
147 /* e.g. v.4s, v.4s, v.4s
148 or v.4h, v.4h, v.h[3]. */
149 if (qualifiers[0] == qualifiers[1]
63b4cc53 150 && vector_qualifier_p (qualifiers[2])
a06ea964
NC		 151 && (aarch64_get_qualifier_esize (qualifiers[0])
152 == aarch64_get_qualifier_esize (qualifiers[1]))
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[2])))
155 return DP_VECTOR_3SAME;
156 /* e.g. v.8h, v.8b, v.8b.
157 or v.4s, v.4h, v.h[2].
158 or v.8h, v.16b. */
63b4cc53 159 if (vector_qualifier_p (qualifiers[1])
a06ea964
NC		 160 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
161 && (aarch64_get_qualifier_esize (qualifiers[0])
162 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
163 return DP_VECTOR_LONG;
164 /* e.g. v.8h, v.8h, v.8b. */
165 if (qualifiers[0] == qualifiers[1]
63b4cc53 166 && vector_qualifier_p (qualifiers[2])
a06ea964
NC		 167 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
168 && (aarch64_get_qualifier_esize (qualifiers[0])
169 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[1])))
172 return DP_VECTOR_WIDE;
173 }
63b4cc53 174 else if (fp_qualifier_p (qualifiers[0]))
a06ea964
NC		 175 {
176 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
63b4cc53 177 if (vector_qualifier_p (qualifiers[1])
a06ea964
NC		 178 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
179 return DP_VECTOR_ACROSS_LANES;
180 }
181
182 return DP_UNKNOWN;
183}
184
185/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
186 the AdvSIMD instructions. */
187/* N.B. it is possible to do some optimization that doesn't call
188 get_data_pattern each time when we need to select an operand. We can
189 either buffer the caculated the result or statically generate the data,
190 however, it is not obvious that the optimization will bring significant
191 benefit. */
192
193int
194aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
195{
196 return
197 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
198}
199\f
01a4d082
PW		 200/* Instruction bit-fields.
201+ Keep synced with 'enum aarch64_field_kind'. */
a06ea964
NC		 202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
7bb5f07c 247 { 5, 4 }, /* imm4_5: in SME instructions. */
a06ea964
NC		 248 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
249 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
250 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
251 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
252 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
253 { 5, 14 }, /* imm14: in test bit and branch instructions. */
254 { 5, 16 }, /* imm16: in exception instructions. */
09c1e68a 255 { 0, 16 }, /* imm16_2: in udf instruction. */
a06ea964
NC		 256 { 0, 26 }, /* imm26: in unconditional branch instructions. */
257 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
258 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
259 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
260 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 261 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 262 { 22, 1 }, /* N: in logical (immediate) instructions. */
263 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
264 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
265 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 266 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 267 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
268 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
269 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
270 { 31, 1 }, /* b5: in the test bit and branch instructions. */
271 { 19, 5 }, /* b40: in the test bit and branch instructions. */
272 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 273 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
274 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
275 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 276 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 277 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
278 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
279 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
280 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
281 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
282 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
283 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
284 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 285 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
286 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
287 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
288 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
289 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 290 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
291 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
292 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
293 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
294 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
295 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
296 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 297 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 298 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
116adc27
MM		 299 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
300 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
31e36ab3 301 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
e950b345 302 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 303 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 304 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
305 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 306 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 307 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
308 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
309 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
310 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
311 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 312 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 313 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
314 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 315 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
316 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
adccc507 317 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
116b6019 318 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
3bd82c86 319 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
0a57e14f 320 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
116b6019 321 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 322 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 323 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
324 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 325 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d 326 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
971eda73
PW		 327 { 0, 2 }, /* SME ZAda tile ZA0-ZA3. */
328 { 0, 3 }, /* SME ZAda tile ZA0-ZA7. */
7bb5f07c
PW		 329 { 22, 2 }, /* SME_size_10: size<1>, size<0> class field, [23:22]. */
330 { 16, 1 }, /* SME_Q: Q class bit, bit 16. */
331 { 15, 1 }, /* SME_V: (horizontal / vertical tiles), bit 15. */
332 { 13, 2 }, /* SME_Rv: vector select register W12-W15, bits [14:13]. */
971eda73 333 { 13, 3 }, /* SME Pm second source scalable predicate register P0-P7. */
1cad938d 334 { 0, 8 }, /* SME_zero_mask: list of up to 8 tile names separated by commas [7:0]. */
d3de0860
PW		 335 { 16, 2 }, /* SME_Rm: index base register W12-W15 [17:16]. */
336 { 23, 1 }, /* SME_i1: immediate field, bit 23. */
337 { 22, 1 }, /* SME_tszh: immediate and qualifier field, bit 22. */
338 { 18, 3 }, /* SME_tshl: immediate and qualifier field, bits [20:18]. */
c2c4ff8d
SN		 339 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
340 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
341 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 342 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
6456d318 343 { 22, 1 }, /* sz: 1-bit element size select. */
fd195909 344 { 10, 2 }, /* CRm_dsb_nxs: 2-bit imm. encoded in CRm<3:2>. */
a06ea964
NC		 345};
346
347enum aarch64_operand_class
348aarch64_get_operand_class (enum aarch64_opnd type)
349{
350 return aarch64_operands[type].op_class;
351}
352
353const char *
354aarch64_get_operand_name (enum aarch64_opnd type)
355{
356 return aarch64_operands[type].name;
357}
358
359/* Get operand description string.
360 This is usually for the diagnosis purpose. */
361const char *
362aarch64_get_operand_desc (enum aarch64_opnd type)
363{
364 return aarch64_operands[type].desc;
365}
366
367/* Table of all conditional affixes. */
368const aarch64_cond aarch64_conds[16] =
369{
bb7eff52
RS		 370 {{"eq", "none"}, 0x0},
371 {{"ne", "any"}, 0x1},
372 {{"cs", "hs", "nlast"}, 0x2},
373 {{"cc", "lo", "ul", "last"}, 0x3},
374 {{"mi", "first"}, 0x4},
375 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 376 {{"vs"}, 0x6},
377 {{"vc"}, 0x7},
bb7eff52
RS		 378 {{"hi", "pmore"}, 0x8},
379 {{"ls", "plast"}, 0x9},
380 {{"ge", "tcont"}, 0xa},
381 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 382 {{"gt"}, 0xc},
383 {{"le"}, 0xd},
384 {{"al"}, 0xe},
385 {{"nv"}, 0xf},
386};
387
388const aarch64_cond *
389get_cond_from_value (aarch64_insn value)
390{
391 assert (value < 16);
392 return &aarch64_conds[(unsigned int) value];
393}
394
395const aarch64_cond *
396get_inverted_cond (const aarch64_cond *cond)
397{
398 return &aarch64_conds[cond->value ^ 0x1];
399}
400
401/* Table describing the operand extension/shifting operators; indexed by
402 enum aarch64_modifier_kind.
403
404 The value column provides the most common values for encoding modifiers,
405 which enables table-driven encoding/decoding for the modifiers. */
406const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
407{
408 {"none", 0x0},
409 {"msl", 0x0},
410 {"ror", 0x3},
411 {"asr", 0x2},
412 {"lsr", 0x1},
413 {"lsl", 0x0},
414 {"uxtb", 0x0},
415 {"uxth", 0x1},
416 {"uxtw", 0x2},
417 {"uxtx", 0x3},
418 {"sxtb", 0x4},
419 {"sxth", 0x5},
420 {"sxtw", 0x6},
421 {"sxtx", 0x7},
2442d846 422 {"mul", 0x0},
98907a70 423 {"mul vl", 0x0},
a06ea964
NC		 424 {NULL, 0},
425};
426
427enum aarch64_modifier_kind
428aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
429{
430 return desc - aarch64_operand_modifiers;
431}
432
433aarch64_insn
434aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
435{
436 return aarch64_operand_modifiers[kind].value;
437}
438
439enum aarch64_modifier_kind
440aarch64_get_operand_modifier_from_value (aarch64_insn value,
78933a4a 441 bool extend_p)
a06ea964 442{
63b4cc53 443 if (extend_p)
a06ea964
NC		 444 return AARCH64_MOD_UXTB + value;
445 else
446 return AARCH64_MOD_LSL - value;
447}
448
78933a4a 449bool
a06ea964
NC		 450aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
451{
63b4cc53 452 return kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX;
a06ea964
NC		 453}
454
78933a4a 455static inline bool
a06ea964
NC		 456aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
457{
63b4cc53 458 return kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL;
a06ea964
NC		 459}
460
461const struct aarch64_name_value_pair aarch64_barrier_options[16] =
462{
463 { "#0x00", 0x0 },
464 { "oshld", 0x1 },
465 { "oshst", 0x2 },
466 { "osh", 0x3 },
467 { "#0x04", 0x4 },
468 { "nshld", 0x5 },
469 { "nshst", 0x6 },
470 { "nsh", 0x7 },
471 { "#0x08", 0x8 },
472 { "ishld", 0x9 },
473 { "ishst", 0xa },
474 { "ish", 0xb },
475 { "#0x0c", 0xc },
476 { "ld", 0xd },
477 { "st", 0xe },
478 { "sy", 0xf },
479};
480
fd195909
PW		 481const struct aarch64_name_value_pair aarch64_barrier_dsb_nxs_options[4] =
482{ /* CRm<3:2> #imm */
483 { "oshnxs", 16 }, /* 00 16 */
484 { "nshnxs", 20 }, /* 01 20 */
485 { "ishnxs", 24 }, /* 10 24 */
486 { "synxs", 28 }, /* 11 28 */
487};
488
9ed608f9
MW		 489/* Table describing the operands supported by the aliases of the HINT
490 instruction.
491
492 The name column is the operand that is accepted for the alias. The value
493 column is the hint number of the alias. The list of operands is terminated
494 by NULL in the name column. */
495
496const struct aarch64_name_value_pair aarch64_hint_options[] =
497{
ff605452
SD		 498 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
499 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
500 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
501 { "c", HINT_OPD_C }, /* BTI C. */
502 { "j", HINT_OPD_J }, /* BTI J. */
503 { "jc", HINT_OPD_JC }, /* BTI JC. */
504 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 505};
506
a32c3ff8 507/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 508 l -> level: 1-3
509 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 510#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 511const struct aarch64_name_value_pair aarch64_prfops[32] =
512{
513 { "pldl1keep", B(0, 1, 0) },
514 { "pldl1strm", B(0, 1, 1) },
515 { "pldl2keep", B(0, 2, 0) },
516 { "pldl2strm", B(0, 2, 1) },
517 { "pldl3keep", B(0, 3, 0) },
518 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 519 { NULL, 0x06 },
520 { NULL, 0x07 },
a32c3ff8
NC		 521 { "plil1keep", B(1, 1, 0) },
522 { "plil1strm", B(1, 1, 1) },
523 { "plil2keep", B(1, 2, 0) },
524 { "plil2strm", B(1, 2, 1) },
525 { "plil3keep", B(1, 3, 0) },
526 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 527 { NULL, 0x0e },
528 { NULL, 0x0f },
a32c3ff8
NC		 529 { "pstl1keep", B(2, 1, 0) },
530 { "pstl1strm", B(2, 1, 1) },
531 { "pstl2keep", B(2, 2, 0) },
532 { "pstl2strm", B(2, 2, 1) },
533 { "pstl3keep", B(2, 3, 0) },
534 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 535 { NULL, 0x16 },
536 { NULL, 0x17 },
537 { NULL, 0x18 },
538 { NULL, 0x19 },
539 { NULL, 0x1a },
540 { NULL, 0x1b },
541 { NULL, 0x1c },
542 { NULL, 0x1d },
543 { NULL, 0x1e },
544 { NULL, 0x1f },
a06ea964
NC		 545};
546#undef B
547\f
548/* Utilities on value constraint. */
549
550static inline int
551value_in_range_p (int64_t value, int low, int high)
552{
553 return (value >= low && value <= high) ? 1 : 0;
554}
555
98907a70 556/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 557static inline int
558value_aligned_p (int64_t value, int align)
559{
98907a70 560 return (value % align) == 0;
a06ea964
NC		 561}
562
563/* A signed value fits in a field. */
564static inline int
565value_fit_signed_field_p (int64_t value, unsigned width)
566{
567 assert (width < 32);
568 if (width < sizeof (value) * 8)
569 {
29298bf6 570 int64_t lim = (uint64_t) 1 << (width - 1);
a06ea964
NC		 571 if (value >= -lim && value < lim)
572 return 1;
573 }
574 return 0;
575}
576
577/* An unsigned value fits in a field. */
578static inline int
579value_fit_unsigned_field_p (int64_t value, unsigned width)
580{
581 assert (width < 32);
582 if (width < sizeof (value) * 8)
583 {
29298bf6 584 int64_t lim = (uint64_t) 1 << width;
a06ea964
NC		 585 if (value >= 0 && value < lim)
586 return 1;
587 }
588 return 0;
589}
590
591/* Return 1 if OPERAND is SP or WSP. */
592int
593aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
594{
595 return ((aarch64_get_operand_class (operand->type)
596 == AARCH64_OPND_CLASS_INT_REG)
597 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
598 && operand->reg.regno == 31);
599}
600
601/* Return 1 if OPERAND is XZR or WZP. */
602int
603aarch64_zero_register_p (const aarch64_opnd_info *operand)
604{
605 return ((aarch64_get_operand_class (operand->type)
606 == AARCH64_OPND_CLASS_INT_REG)
607 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
608 && operand->reg.regno == 31);
609}
610
611/* Return true if the operand *OPERAND that has the operand code
612 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
613 qualified by the qualifier TARGET. */
614
615static inline int
616operand_also_qualified_p (const struct aarch64_opnd_info *operand,
617 aarch64_opnd_qualifier_t target)
618{
619 switch (operand->qualifier)
620 {
621 case AARCH64_OPND_QLF_W:
622 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
623 return 1;
624 break;
625 case AARCH64_OPND_QLF_X:
626 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
627 return 1;
628 break;
629 case AARCH64_OPND_QLF_WSP:
630 if (target == AARCH64_OPND_QLF_W
631 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
632 return 1;
633 break;
634 case AARCH64_OPND_QLF_SP:
635 if (target == AARCH64_OPND_QLF_X
636 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
637 return 1;
638 break;
639 default:
640 break;
641 }
642
643 return 0;
644}
645
646/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
647 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
648
649 Return NIL if more than one expected qualifiers are found. */
650
651aarch64_opnd_qualifier_t
652aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
653 int idx,
654 const aarch64_opnd_qualifier_t known_qlf,
655 int known_idx)
656{
657 int i, saved_i;
658
659 /* Special case.
660
661 When the known qualifier is NIL, we have to assume that there is only
662 one qualifier sequence in the *QSEQ_LIST and return the corresponding
663 qualifier directly. One scenario is that for instruction
664 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
665 which has only one possible valid qualifier sequence
666 NIL, S_D
667 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
668 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
669
670 Because the qualifier NIL has dual roles in the qualifier sequence:
671 it can mean no qualifier for the operand, or the qualifer sequence is
672 not in use (when all qualifiers in the sequence are NILs), we have to
673 handle this special case here. */
674 if (known_qlf == AARCH64_OPND_NIL)
675 {
676 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
677 return qseq_list[0][idx];
678 }
679
680 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
681 {
682 if (qseq_list[i][known_idx] == known_qlf)
683 {
684 if (saved_i != -1)
685 /* More than one sequences are found to have KNOWN_QLF at
686 KNOWN_IDX. */
687 return AARCH64_OPND_NIL;
688 saved_i = i;
689 }
690 }
691
692 return qseq_list[saved_i][idx];
693}
694
695enum operand_qualifier_kind
696{
697 OQK_NIL,
698 OQK_OPD_VARIANT,
699 OQK_VALUE_IN_RANGE,
700 OQK_MISC,
701};
702
703/* Operand qualifier description. */
704struct operand_qualifier_data
705{
706 /* The usage of the three data fields depends on the qualifier kind. */
707 int data0;
708 int data1;
709 int data2;
710 /* Description. */
711 const char *desc;
712 /* Kind. */
713 enum operand_qualifier_kind kind;
714};
715
716/* Indexed by the operand qualifier enumerators. */
717struct operand_qualifier_data aarch64_opnd_qualifiers[] =
718{
719 {0, 0, 0, "NIL", OQK_NIL},
720
721 /* Operand variant qualifiers.
722 First 3 fields:
723 element size, number of elements and common value for encoding. */
724
725 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
726 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
727 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
728 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
729
730 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
731 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
732 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
733 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
734 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 735 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
df678013 736 {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964 737
a3b3345a 738 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 739 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
740 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 741 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 742 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
743 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
744 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
745 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
746 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
747 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
748 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
749
d50c751e
RS		 750 {0, 0, 0, "z", OQK_OPD_VARIANT},
751 {0, 0, 0, "m", OQK_OPD_VARIANT},
752
fb3265b3
SD		 753 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
754 {16, 0, 0, "tag", OQK_OPD_VARIANT},
755
a06ea964
NC		 756 /* Qualifiers constraining the value range.
757 First 3 fields:
758 Lower bound, higher bound, unused. */
759
a6a51754 760 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 761 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
762 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
763 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
764 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
765 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
766 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
767
768 /* Qualifiers for miscellaneous purpose.
769 First 3 fields:
770 unused, unused and unused. */
771
772 {0, 0, 0, "lsl", 0},
773 {0, 0, 0, "msl", 0},
774
775 {0, 0, 0, "retrieving", 0},
776};
777
78933a4a 778static inline bool
a06ea964
NC		 779operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
780{
63b4cc53 781 return aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT;
a06ea964
NC		 782}
783
78933a4a 784static inline bool
a06ea964
NC		 785qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
786{
63b4cc53 787 return aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE;
a06ea964
NC		 788}
789
790const char*
791aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
792{
793 return aarch64_opnd_qualifiers[qualifier].desc;
794}
795
796/* Given an operand qualifier, return the expected data element size
797 of a qualified operand. */
798unsigned char
799aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
800{
63b4cc53 801 assert (operand_variant_qualifier_p (qualifier));
a06ea964
NC		 802 return aarch64_opnd_qualifiers[qualifier].data0;
803}
804
805unsigned char
806aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
807{
63b4cc53 808 assert (operand_variant_qualifier_p (qualifier));
a06ea964
NC		 809 return aarch64_opnd_qualifiers[qualifier].data1;
810}
811
812aarch64_insn
813aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
814{
63b4cc53 815 assert (operand_variant_qualifier_p (qualifier));
a06ea964
NC		 816 return aarch64_opnd_qualifiers[qualifier].data2;
817}
818
819static int
820get_lower_bound (aarch64_opnd_qualifier_t qualifier)
821{
63b4cc53 822 assert (qualifier_value_in_range_constraint_p (qualifier));
a06ea964
NC		 823 return aarch64_opnd_qualifiers[qualifier].data0;
824}
825
826static int
827get_upper_bound (aarch64_opnd_qualifier_t qualifier)
828{
63b4cc53 829 assert (qualifier_value_in_range_constraint_p (qualifier));
a06ea964
NC		 830 return aarch64_opnd_qualifiers[qualifier].data1;
831}
832
833#ifdef DEBUG_AARCH64
834void
835aarch64_verbose (const char *str, ...)
836{
837 va_list ap;
838 va_start (ap, str);
839 printf ("#### ");
840 vprintf (str, ap);
841 printf ("\n");
842 va_end (ap);
843}
844
845static inline void
846dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
847{
848 int i;
849 printf ("#### \t");
850 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
851 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
852 printf ("\n");
853}
854
855static void
856dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
857 const aarch64_opnd_qualifier_t *qualifier)
858{
859 int i;
860 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
861
862 aarch64_verbose ("dump_match_qualifiers:");
863 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
864 curr[i] = opnd[i].qualifier;
865 dump_qualifier_sequence (curr);
866 aarch64_verbose ("against");
867 dump_qualifier_sequence (qualifier);
868}
869#endif /* DEBUG_AARCH64 */
870
a68f4cd2
TC		 871/* This function checks if the given instruction INSN is a destructive
872 instruction based on the usage of the registers. It does not recognize
873 unary destructive instructions. */
78933a4a 874bool
a68f4cd2
TC		 875aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
876{
877 int i = 0;
878 const enum aarch64_opnd *opnds = opcode->operands;
879
880 if (opnds[0] == AARCH64_OPND_NIL)
78933a4a 881 return false;
a68f4cd2
TC		 882
883 while (opnds[++i] != AARCH64_OPND_NIL)
884 if (opnds[i] == opnds[0])
78933a4a 885 return true;
a68f4cd2 886
78933a4a 887 return false;
a68f4cd2
TC		 888}
889
a06ea964
NC		 890/* TODO improve this, we can have an extra field at the runtime to
891 store the number of operands rather than calculating it every time. */
892
893int
894aarch64_num_of_operands (const aarch64_opcode *opcode)
895{
896 int i = 0;
897 const enum aarch64_opnd *opnds = opcode->operands;
898 while (opnds[i++] != AARCH64_OPND_NIL)
899 ;
900 --i;
901 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
902 return i;
903}
904
905/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
906 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
907
908 N.B. on the entry, it is very likely that only some operands in *INST
909 have had their qualifiers been established.
910
911 If STOP_AT is not -1, the function will only try to match
912 the qualifier sequence for operands before and including the operand
913 of index STOP_AT; and on success *RET will only be filled with the first
914 (STOP_AT+1) qualifiers.
915
916 A couple examples of the matching algorithm:
917
918 X,W,NIL should match
919 X,W,NIL
920
921 NIL,NIL should match
922 X ,NIL
923
924 Apart from serving the main encoding routine, this can also be called
925 during or after the operand decoding. */
926
927int
928aarch64_find_best_match (const aarch64_inst *inst,
929 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
930 int stop_at, aarch64_opnd_qualifier_t *ret)
931{
932 int found = 0;
933 int i, num_opnds;
934 const aarch64_opnd_qualifier_t *qualifiers;
935
936 num_opnds = aarch64_num_of_operands (inst->opcode);
937 if (num_opnds == 0)
938 {
939 DEBUG_TRACE ("SUCCEED: no operand");
940 return 1;
941 }
942
943 if (stop_at < 0 || stop_at >= num_opnds)
944 stop_at = num_opnds - 1;
945
946 /* For each pattern. */
947 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
948 {
949 int j;
950 qualifiers = *qualifiers_list;
951
952 /* Start as positive. */
953 found = 1;
954
955 DEBUG_TRACE ("%d", i);
956#ifdef DEBUG_AARCH64
957 if (debug_dump)
958 dump_match_qualifiers (inst->operands, qualifiers);
959#endif
960
961 /* Most opcodes has much fewer patterns in the list.
962 First NIL qualifier indicates the end in the list. */
63b4cc53 963 if (empty_qualifier_sequence_p (qualifiers))
a06ea964
NC		 964 {
965 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
966 if (i)
967 found = 0;
968 break;
969 }
970
971 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
972 {
973 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
974 {
975 /* Either the operand does not have qualifier, or the qualifier
976 for the operand needs to be deduced from the qualifier
977 sequence.
978 In the latter case, any constraint checking related with
979 the obtained qualifier should be done later in
980 operand_general_constraint_met_p. */
981 continue;
982 }
983 else if (*qualifiers != inst->operands[j].qualifier)
984 {
985 /* Unless the target qualifier can also qualify the operand
986 (which has already had a non-nil qualifier), non-equal
987 qualifiers are generally un-matched. */
988 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
989 continue;
990 else
991 {
992 found = 0;
993 break;
994 }
995 }
996 else
997 continue; /* Equal qualifiers are certainly matched. */
998 }
999
1000 /* Qualifiers established. */
1001 if (found == 1)
1002 break;
1003 }
1004
1005 if (found == 1)
1006 {
1007 /* Fill the result in *RET. */
1008 int j;
1009 qualifiers = *qualifiers_list;
1010
1011 DEBUG_TRACE ("complete qualifiers using list %d", i);
1012#ifdef DEBUG_AARCH64
1013 if (debug_dump)
1014 dump_qualifier_sequence (qualifiers);
1015#endif
1016
1017 for (j = 0; j <= stop_at; ++j, ++qualifiers)
1018 ret[j] = *qualifiers;
1019 for (; j < AARCH64_MAX_OPND_NUM; ++j)
1020 ret[j] = AARCH64_OPND_QLF_NIL;
1021
1022 DEBUG_TRACE ("SUCCESS");
1023 return 1;
1024 }
1025
1026 DEBUG_TRACE ("FAIL");
1027 return 0;
1028}
1029
1030/* Operand qualifier matching and resolving.
1031
1032 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1033 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1034
63b4cc53 1035 if UPDATE_P, update the qualifier(s) in *INST after the matching
a06ea964
NC		 1036 succeeds. */
1037
1038static int
78933a4a 1039match_operands_qualifier (aarch64_inst *inst, bool update_p)
a06ea964 1040{
4989adac 1041 int i, nops;
a06ea964
NC		 1042 aarch64_opnd_qualifier_seq_t qualifiers;
1043
1044 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1045 qualifiers))
1046 {
1047 DEBUG_TRACE ("matching FAIL");
1048 return 0;
1049 }
1050
4989adac
RS		 1051 if (inst->opcode->flags & F_STRICT)
1052 {
1053 /* Require an exact qualifier match, even for NIL qualifiers. */
1054 nops = aarch64_num_of_operands (inst->opcode);
1055 for (i = 0; i < nops; ++i)
1056 if (inst->operands[i].qualifier != qualifiers[i])
78933a4a 1057 return false;
4989adac
RS		 1058 }
1059
a06ea964 1060 /* Update the qualifiers. */
63b4cc53 1061 if (update_p)
a06ea964
NC		 1062 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1063 {
1064 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1065 break;
1066 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1067 "update %s with %s for operand %d",
1068 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1069 aarch64_get_qualifier_name (qualifiers[i]), i);
1070 inst->operands[i].qualifier = qualifiers[i];
1071 }
1072
1073 DEBUG_TRACE ("matching SUCCESS");
1074 return 1;
1075}
1076
1077/* Return TRUE if VALUE is a wide constant that can be moved into a general
1078 register by MOVZ.
1079
1080 IS32 indicates whether value is a 32-bit immediate or not.
1081 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1082 amount will be returned in *SHIFT_AMOUNT. */
1083
78933a4a 1084bool
29298bf6 1085aarch64_wide_constant_p (uint64_t value, int is32, unsigned int *shift_amount)
a06ea964
NC		 1086{
1087 int amount;
1088
1089 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1090
1091 if (is32)
1092 {
1093 /* Allow all zeros or all ones in top 32-bits, so that
1094 32-bit constant expressions like ~0x80000000 are
1095 permitted. */
29298bf6 1096 if (value >> 32 != 0 && value >> 32 != 0xffffffff)
a06ea964 1097 /* Immediate out of range. */
78933a4a 1098 return false;
29298bf6 1099 value &= 0xffffffff;
a06ea964
NC		 1100 }
1101
1102 /* first, try movz then movn */
1103 amount = -1;
29298bf6 1104 if ((value & ((uint64_t) 0xffff << 0)) == value)
a06ea964 1105 amount = 0;
29298bf6 1106 else if ((value & ((uint64_t) 0xffff << 16)) == value)
a06ea964 1107 amount = 16;
29298bf6 1108 else if (!is32 && (value & ((uint64_t) 0xffff << 32)) == value)
a06ea964 1109 amount = 32;
29298bf6 1110 else if (!is32 && (value & ((uint64_t) 0xffff << 48)) == value)
a06ea964
NC		 1111 amount = 48;
1112
1113 if (amount == -1)
1114 {
78933a4a
AM		 1115 DEBUG_TRACE ("exit false with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1116 return false;
a06ea964
NC		 1117 }
1118
1119 if (shift_amount != NULL)
1120 *shift_amount = amount;
1121
78933a4a 1122 DEBUG_TRACE ("exit true with amount %d", amount);
a06ea964 1123
78933a4a 1124 return true;
a06ea964
NC		 1125}
1126
1127/* Build the accepted values for immediate logical SIMD instructions.
1128
1129 The standard encodings of the immediate value are:
1130 N imms immr SIMD size R S
1131 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1132 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1133 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1134 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1135 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1136 0 11110s 00000r 2 UInt(r) UInt(s)
1137 where all-ones value of S is reserved.
1138
1139 Let's call E the SIMD size.
1140
1141 The immediate value is: S+1 bits '1' rotated to the right by R.
1142
1143 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1144 (remember S != E - 1). */
1145
1146#define TOTAL_IMM_NB 5334
1147
1148typedef struct
1149{
1150 uint64_t imm;
1151 aarch64_insn encoding;
1152} simd_imm_encoding;
1153
1154static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1155
1156static int
1157simd_imm_encoding_cmp(const void *i1, const void *i2)
1158{
1159 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1160 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1161
1162 if (imm1->imm < imm2->imm)
1163 return -1;
1164 if (imm1->imm > imm2->imm)
1165 return +1;
1166 return 0;
1167}
1168
1169/* immediate bitfield standard encoding
1170 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1171 1 ssssss rrrrrr 64 rrrrrr ssssss
1172 0 0sssss 0rrrrr 32 rrrrr sssss
1173 0 10ssss 00rrrr 16 rrrr ssss
1174 0 110sss 000rrr 8 rrr sss
1175 0 1110ss 0000rr 4 rr ss
1176 0 11110s 00000r 2 r s */
1177static inline int
1178encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1179{
1180 return (is64 << 12) | (r << 6) | s;
1181}
1182
1183static void
1184build_immediate_table (void)
1185{
1186 uint32_t log_e, e, s, r, s_mask;
1187 uint64_t mask, imm;
1188 int nb_imms;
1189 int is64;
1190
1191 nb_imms = 0;
1192 for (log_e = 1; log_e <= 6; log_e++)
1193 {
1194 /* Get element size. */
1195 e = 1u << log_e;
1196 if (log_e == 6)
1197 {
1198 is64 = 1;
1199 mask = 0xffffffffffffffffull;
1200 s_mask = 0;
1201 }
1202 else
1203 {
1204 is64 = 0;
1205 mask = (1ull << e) - 1;
1206 /* log_e s_mask
1207 1 ((1 << 4) - 1) << 2 = 111100
1208 2 ((1 << 3) - 1) << 3 = 111000
1209 3 ((1 << 2) - 1) << 4 = 110000
1210 4 ((1 << 1) - 1) << 5 = 100000
1211 5 ((1 << 0) - 1) << 6 = 000000 */
1212 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1213 }
1214 for (s = 0; s < e - 1; s++)
1215 for (r = 0; r < e; r++)
1216 {
1217 /* s+1 consecutive bits to 1 (s < 63) */
1218 imm = (1ull << (s + 1)) - 1;
1219 /* rotate right by r */
1220 if (r != 0)
1221 imm = (imm >> r) | ((imm << (e - r)) & mask);
1222 /* replicate the constant depending on SIMD size */
1223 switch (log_e)
1224 {
1225 case 1: imm = (imm << 2) | imm;
1a0670f3 1226 /* Fall through. */
a06ea964 1227 case 2: imm = (imm << 4) | imm;
1a0670f3 1228 /* Fall through. */
a06ea964 1229 case 3: imm = (imm << 8) | imm;
1a0670f3 1230 /* Fall through. */
a06ea964 1231 case 4: imm = (imm << 16) | imm;
1a0670f3 1232 /* Fall through. */
a06ea964 1233 case 5: imm = (imm << 32) | imm;
1a0670f3 1234 /* Fall through. */
a06ea964
NC		 1235 case 6: break;
1236 default: abort ();
1237 }
1238 simd_immediates[nb_imms].imm = imm;
1239 simd_immediates[nb_imms].encoding =
1240 encode_immediate_bitfield(is64, s | s_mask, r);
1241 nb_imms++;
1242 }
1243 }
1244 assert (nb_imms == TOTAL_IMM_NB);
1245 qsort(simd_immediates, nb_imms,
1246 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1247}
1248
1249/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1250 be accepted by logical (immediate) instructions
1251 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1252
42408347 1253 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1254 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1255 VALUE will be returned in *ENCODING. */
1256
78933a4a 1257bool
42408347 1258aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1259{
1260 simd_imm_encoding imm_enc;
1261 const simd_imm_encoding *imm_encoding;
78933a4a 1262 static bool initialized = false;
42408347
RS		 1263 uint64_t upper;
1264 int i;
a06ea964 1265
957f6b39
TC		 1266 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1267 value, esize);
a06ea964 1268
535b785f 1269 if (!initialized)
a06ea964
NC		 1270 {
1271 build_immediate_table ();
78933a4a 1272 initialized = true;
a06ea964
NC		 1273 }
1274
42408347
RS		 1275 /* Allow all zeros or all ones in top bits, so that
1276 constant expressions like ~1 are permitted. */
1277 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1278 if ((value & ~upper) != value && (value | upper) != value)
78933a4a 1279 return false;
7e105031 1280
42408347
RS		 1281 /* Replicate to a full 64-bit value. */
1282 value &= ~upper;
1283 for (i = esize * 8; i < 64; i *= 2)
1284 value |= (value << i);
a06ea964
NC		 1285
1286 imm_enc.imm = value;
1287 imm_encoding = (const simd_imm_encoding *)
1288 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1289 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1290 if (imm_encoding == NULL)
1291 {
78933a4a
AM		 1292 DEBUG_TRACE ("exit with false");
1293 return false;
a06ea964
NC		 1294 }
1295 if (encoding != NULL)
1296 *encoding = imm_encoding->encoding;
78933a4a
AM		 1297 DEBUG_TRACE ("exit with true");
1298 return true;
a06ea964
NC		 1299}
1300
1301/* If 64-bit immediate IMM is in the format of
1302 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1303 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1304 of value "abcdefgh". Otherwise return -1. */
1305int
1306aarch64_shrink_expanded_imm8 (uint64_t imm)
1307{
1308 int i, ret;
1309 uint32_t byte;
1310
1311 ret = 0;
1312 for (i = 0; i < 8; i++)
1313 {
1314 byte = (imm >> (8 * i)) & 0xff;
1315 if (byte == 0xff)
1316 ret |= 1 << i;
1317 else if (byte != 0x00)
1318 return -1;
1319 }
1320 return ret;
1321}
1322
1323/* Utility inline functions for operand_general_constraint_met_p. */
1324
1325static inline void
1326set_error (aarch64_operand_error *mismatch_detail,
1327 enum aarch64_operand_error_kind kind, int idx,
1328 const char* error)
1329{
1330 if (mismatch_detail == NULL)
1331 return;
1332 mismatch_detail->kind = kind;
1333 mismatch_detail->index = idx;
1334 mismatch_detail->error = error;
1335}
1336
4e50d5f8
YZ		 1337static inline void
1338set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1339 const char* error)
1340{
1341 if (mismatch_detail == NULL)
1342 return;
1343 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1344}
1345
a06ea964
NC		 1346static inline void
1347set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1348 int idx, int lower_bound, int upper_bound,
1349 const char* error)
1350{
1351 if (mismatch_detail == NULL)
1352 return;
1353 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1354 mismatch_detail->data[0] = lower_bound;
1355 mismatch_detail->data[1] = upper_bound;
1356}
1357
1358static inline void
1359set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1360 int idx, int lower_bound, int upper_bound)
1361{
1362 if (mismatch_detail == NULL)
1363 return;
1364 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1365 _("immediate value"));
1366}
1367
1368static inline void
1369set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1370 int idx, int lower_bound, int upper_bound)
1371{
1372 if (mismatch_detail == NULL)
1373 return;
1374 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1375 _("immediate offset"));
1376}
1377
1378static inline void
1379set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1380 int idx, int lower_bound, int upper_bound)
1381{
1382 if (mismatch_detail == NULL)
1383 return;
1384 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1385 _("register number"));
1386}
1387
1388static inline void
1389set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1390 int idx, int lower_bound, int upper_bound)
1391{
1392 if (mismatch_detail == NULL)
1393 return;
1394 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1395 _("register element index"));
1396}
1397
1398static inline void
1399set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1400 int idx, int lower_bound, int upper_bound)
1401{
1402 if (mismatch_detail == NULL)
1403 return;
1404 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1405 _("shift amount"));
1406}
1407
2442d846
RS		 1408/* Report that the MUL modifier in operand IDX should be in the range
1409 [LOWER_BOUND, UPPER_BOUND]. */
1410static inline void
1411set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1412 int idx, int lower_bound, int upper_bound)
1413{
1414 if (mismatch_detail == NULL)
1415 return;
1416 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1417 _("multiplier"));
1418}
1419
a06ea964
NC		 1420static inline void
1421set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1422 int alignment)
1423{
1424 if (mismatch_detail == NULL)
1425 return;
1426 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1427 mismatch_detail->data[0] = alignment;
1428}
1429
1430static inline void
1431set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1432 int expected_num)
1433{
1434 if (mismatch_detail == NULL)
1435 return;
1436 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1437 mismatch_detail->data[0] = expected_num;
1438}
1439
1440static inline void
1441set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1442 const char* error)
1443{
1444 if (mismatch_detail == NULL)
1445 return;
1446 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1447}
1448
1449/* General constraint checking based on operand code.
1450
1451 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1452 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1453
1454 This function has to be called after the qualifiers for all operands
1455 have been resolved.
1456
1457 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1458 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1459 of error message during the disassembling where error message is not
1460 wanted. We avoid the dynamic construction of strings of error messages
1461 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1462 use a combination of error code, static string and some integer data to
1463 represent an error. */
1464
1465static int
1466operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1467 enum aarch64_opnd type,
1468 const aarch64_opcode *opcode,
1469 aarch64_operand_error *mismatch_detail)
1470{
e950b345 1471 unsigned num, modifiers, shift;
a06ea964 1472 unsigned char size;
4df068de 1473 int64_t imm, min_value, max_value;
e950b345 1474 uint64_t uvalue, mask;
a06ea964
NC		 1475 const aarch64_opnd_info *opnd = opnds + idx;
1476 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1477
1478 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1479
1480 switch (aarch64_operands[type].op_class)
1481 {
1482 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1483 /* Check pair reg constraints for cas* instructions. */
1484 if (type == AARCH64_OPND_PAIRREG)
1485 {
1486 assert (idx == 1 || idx == 3);
1487 if (opnds[idx - 1].reg.regno % 2 != 0)
1488 {
1489 set_syntax_error (mismatch_detail, idx - 1,
1490 _("reg pair must start from even reg"));
1491 return 0;
1492 }
1493 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1494 {
1495 set_syntax_error (mismatch_detail, idx,
1496 _("reg pair must be contiguous"));
1497 return 0;
1498 }
1499 break;
1500 }
1501
a06ea964
NC		 1502 /* <Xt> may be optional in some IC and TLBI instructions. */
1503 if (type == AARCH64_OPND_Rt_SYS)
1504 {
1505 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1506 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1507 if (opnds[1].present
1508 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1509 {
1510 set_other_error (mismatch_detail, idx, _("extraneous register"));
1511 return 0;
1512 }
ea2deeec
MW		 1513 if (!opnds[1].present
1514 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1515 {
1516 set_other_error (mismatch_detail, idx, _("missing register"));
1517 return 0;
1518 }
1519 }
1520 switch (qualifier)
1521 {
1522 case AARCH64_OPND_QLF_WSP:
1523 case AARCH64_OPND_QLF_SP:
1524 if (!aarch64_stack_pointer_p (opnd))
1525 {
1526 set_other_error (mismatch_detail, idx,
3dd032c5 1527 _("stack pointer register expected"));
a06ea964
NC		 1528 return 0;
1529 }
1530 break;
1531 default:
1532 break;
1533 }
1534 break;
1535
f11ad6bc
RS		 1536 case AARCH64_OPND_CLASS_SVE_REG:
1537 switch (type)
1538 {
582e12bf
RS		 1539 case AARCH64_OPND_SVE_Zm3_INDEX:
1540 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 1541 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 1542 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf
RS		 1543 case AARCH64_OPND_SVE_Zm4_INDEX:
1544 size = get_operand_fields_width (get_operand_from_code (type));
1545 shift = get_operand_specific_data (&aarch64_operands[type]);
1546 mask = (1 << shift) - 1;
1547 if (opnd->reg.regno > mask)
1548 {
1549 assert (mask == 7 || mask == 15);
1550 set_other_error (mismatch_detail, idx,
1551 mask == 15
1552 ? _("z0-z15 expected")
1553 : _("z0-z7 expected"));
1554 return 0;
1555 }
29298bf6 1556 mask = (1u << (size - shift)) - 1;
582e12bf
RS		 1557 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1558 {
1559 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1560 return 0;
1561 }
1562 break;
1563
f11ad6bc
RS		 1564 case AARCH64_OPND_SVE_Zn_INDEX:
1565 size = aarch64_get_qualifier_esize (opnd->qualifier);
1566 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1567 {
1568 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1569 0, 64 / size - 1);
1570 return 0;
1571 }
1572 break;
1573
1574 case AARCH64_OPND_SVE_ZnxN:
1575 case AARCH64_OPND_SVE_ZtxN:
1576 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1577 {
1578 set_other_error (mismatch_detail, idx,
1579 _("invalid register list"));
1580 return 0;
1581 }
1582 break;
1583
1584 default:
1585 break;
1586 }
1587 break;
1588
1589 case AARCH64_OPND_CLASS_PRED_REG:
1590 if (opnd->reg.regno >= 8
1591 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1592 {
1593 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1594 return 0;
1595 }
1596 break;
1597
68a64283
YZ		 1598 case AARCH64_OPND_CLASS_COND:
1599 if (type == AARCH64_OPND_COND1
1600 && (opnds[idx].cond->value & 0xe) == 0xe)
1601 {
1602 /* Not allow AL or NV. */
1603 set_syntax_error (mismatch_detail, idx, NULL);
1604 }
1605 break;
1606
a06ea964
NC		 1607 case AARCH64_OPND_CLASS_ADDRESS:
1608 /* Check writeback. */
1609 switch (opcode->iclass)
1610 {
1611 case ldst_pos:
1612 case ldst_unscaled:
1613 case ldstnapair_offs:
1614 case ldstpair_off:
1615 case ldst_unpriv:
1616 if (opnd->addr.writeback == 1)
1617 {
4e50d5f8
YZ		 1618 set_syntax_error (mismatch_detail, idx,
1619 _("unexpected address writeback"));
a06ea964
NC		 1620 return 0;
1621 }
1622 break;
3f06e550
SN		 1623 case ldst_imm10:
1624 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1625 {
1626 set_syntax_error (mismatch_detail, idx,
1627 _("unexpected address writeback"));
1628 return 0;
1629 }
1630 break;
a06ea964
NC		 1631 case ldst_imm9:
1632 case ldstpair_indexed:
1633 case asisdlsep:
1634 case asisdlsop:
1635 if (opnd->addr.writeback == 0)
1636 {
4e50d5f8
YZ		 1637 set_syntax_error (mismatch_detail, idx,
1638 _("address writeback expected"));
a06ea964
NC		 1639 return 0;
1640 }
1641 break;
1642 default:
1643 assert (opnd->addr.writeback == 0);
1644 break;
1645 }
1646 switch (type)
1647 {
1648 case AARCH64_OPND_ADDR_SIMM7:
1649 /* Scaled signed 7 bits immediate offset. */
1650 /* Get the size of the data element that is accessed, which may be
1651 different from that of the source register size,
1652 e.g. in strb/ldrb. */
1653 size = aarch64_get_qualifier_esize (opnd->qualifier);
1654 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1655 {
1656 set_offset_out_of_range_error (mismatch_detail, idx,
1657 -64 * size, 63 * size);
1658 return 0;
1659 }
1660 if (!value_aligned_p (opnd->addr.offset.imm, size))
1661 {
1662 set_unaligned_error (mismatch_detail, idx, size);
1663 return 0;
1664 }
1665 break;
f42f1a1d 1666 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1667 case AARCH64_OPND_ADDR_SIMM9:
1668 /* Unscaled signed 9 bits immediate offset. */
1669 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1670 {
1671 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1672 return 0;
1673 }
1674 break;
1675
1676 case AARCH64_OPND_ADDR_SIMM9_2:
1677 /* Unscaled signed 9 bits immediate offset, which has to be negative
1678 or unaligned. */
1679 size = aarch64_get_qualifier_esize (qualifier);
1680 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1681 && !value_aligned_p (opnd->addr.offset.imm, size))
1682 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1683 return 1;
1684 set_other_error (mismatch_detail, idx,
1685 _("negative or unaligned offset expected"));
1686 return 0;
1687
3f06e550
SN		 1688 case AARCH64_OPND_ADDR_SIMM10:
1689 /* Scaled signed 10 bits immediate offset. */
1690 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1691 {
1692 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1693 return 0;
1694 }
1695 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1696 {
1697 set_unaligned_error (mismatch_detail, idx, 8);
1698 return 0;
1699 }
1700 break;
1701
fb3265b3
SD		 1702 case AARCH64_OPND_ADDR_SIMM11:
1703 /* Signed 11 bits immediate offset (multiple of 16). */
1704 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1705 {
1706 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1707 return 0;
1708 }
1709
1710 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1711 {
1712 set_unaligned_error (mismatch_detail, idx, 16);
1713 return 0;
1714 }
1715 break;
1716
1717 case AARCH64_OPND_ADDR_SIMM13:
1718 /* Signed 13 bits immediate offset (multiple of 16). */
1719 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1720 {
1721 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1722 return 0;
1723 }
1724
1725 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1726 {
1727 set_unaligned_error (mismatch_detail, idx, 16);
1728 return 0;
1729 }
1730 break;
1731
a06ea964
NC		 1732 case AARCH64_OPND_SIMD_ADDR_POST:
1733 /* AdvSIMD load/store multiple structures, post-index. */
1734 assert (idx == 1);
1735 if (opnd->addr.offset.is_reg)
1736 {
1737 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1738 return 1;
1739 else
1740 {
1741 set_other_error (mismatch_detail, idx,
1742 _("invalid register offset"));
1743 return 0;
1744 }
1745 }
1746 else
1747 {
1748 const aarch64_opnd_info *prev = &opnds[idx-1];
1749 unsigned num_bytes; /* total number of bytes transferred. */
1750 /* The opcode dependent area stores the number of elements in
1751 each structure to be loaded/stored. */
1752 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1753 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1754 /* Special handling of loading single structure to all lane. */
1755 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1756 * aarch64_get_qualifier_esize (prev->qualifier);
1757 else
1758 num_bytes = prev->reglist.num_regs
1759 * aarch64_get_qualifier_esize (prev->qualifier)
1760 * aarch64_get_qualifier_nelem (prev->qualifier);
1761 if ((int) num_bytes != opnd->addr.offset.imm)
1762 {
1763 set_other_error (mismatch_detail, idx,
1764 _("invalid post-increment amount"));
1765 return 0;
1766 }
1767 }
1768 break;
1769
1770 case AARCH64_OPND_ADDR_REGOFF:
1771 /* Get the size of the data element that is accessed, which may be
1772 different from that of the source register size,
1773 e.g. in strb/ldrb. */
1774 size = aarch64_get_qualifier_esize (opnd->qualifier);
1775 /* It is either no shift or shift by the binary logarithm of SIZE. */
1776 if (opnd->shifter.amount != 0
1777 && opnd->shifter.amount != (int)get_logsz (size))
1778 {
1779 set_other_error (mismatch_detail, idx,
1780 _("invalid shift amount"));
1781 return 0;
1782 }
1783 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1784 operators. */
1785 switch (opnd->shifter.kind)
1786 {
1787 case AARCH64_MOD_UXTW:
1788 case AARCH64_MOD_LSL:
1789 case AARCH64_MOD_SXTW:
1790 case AARCH64_MOD_SXTX: break;
1791 default:
1792 set_other_error (mismatch_detail, idx,
1793 _("invalid extend/shift operator"));
1794 return 0;
1795 }
1796 break;
1797
1798 case AARCH64_OPND_ADDR_UIMM12:
1799 imm = opnd->addr.offset.imm;
1800 /* Get the size of the data element that is accessed, which may be
1801 different from that of the source register size,
1802 e.g. in strb/ldrb. */
1803 size = aarch64_get_qualifier_esize (qualifier);
1804 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1805 {
1806 set_offset_out_of_range_error (mismatch_detail, idx,
1807 0, 4095 * size);
1808 return 0;
1809 }
9de794e1 1810 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1811 {
1812 set_unaligned_error (mismatch_detail, idx, size);
1813 return 0;
1814 }
1815 break;
1816
1817 case AARCH64_OPND_ADDR_PCREL14:
1818 case AARCH64_OPND_ADDR_PCREL19:
1819 case AARCH64_OPND_ADDR_PCREL21:
1820 case AARCH64_OPND_ADDR_PCREL26:
1821 imm = opnd->imm.value;
1822 if (operand_need_shift_by_two (get_operand_from_code (type)))
1823 {
1824 /* The offset value in a PC-relative branch instruction is alway
1825 4-byte aligned and is encoded without the lowest 2 bits. */
1826 if (!value_aligned_p (imm, 4))
1827 {
1828 set_unaligned_error (mismatch_detail, idx, 4);
1829 return 0;
1830 }
1831 /* Right shift by 2 so that we can carry out the following check
1832 canonically. */
1833 imm >>= 2;
1834 }
1835 size = get_operand_fields_width (get_operand_from_code (type));
1836 if (!value_fit_signed_field_p (imm, size))
1837 {
1838 set_other_error (mismatch_detail, idx,
1839 _("immediate out of range"));
1840 return 0;
1841 }
1842 break;
1843
01a4d082
PW		 1844 case AARCH64_OPND_SME_ADDR_RI_U4xVL:
1845 if (!value_in_range_p (opnd->addr.offset.imm, 0, 15))
1846 {
1847 set_offset_out_of_range_error (mismatch_detail, idx, 0, 15);
1848 return 0;
1849 }
1850 break;
1851
98907a70
RS		 1852 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1853 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1854 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1855 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1856 min_value = -8;
1857 max_value = 7;
1858 sve_imm_offset_vl:
1859 assert (!opnd->addr.offset.is_reg);
1860 assert (opnd->addr.preind);
1861 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1862 min_value *= num;
1863 max_value *= num;
1864 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1865 || (opnd->shifter.operator_present
1866 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1867 {
1868 set_other_error (mismatch_detail, idx,
1869 _("invalid addressing mode"));
1870 return 0;
1871 }
1872 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1873 {
1874 set_offset_out_of_range_error (mismatch_detail, idx,
1875 min_value, max_value);
1876 return 0;
1877 }
1878 if (!value_aligned_p (opnd->addr.offset.imm, num))
1879 {
1880 set_unaligned_error (mismatch_detail, idx, num);
1881 return 0;
1882 }
1883 break;
1884
1885 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1886 min_value = -32;
1887 max_value = 31;
1888 goto sve_imm_offset_vl;
1889
1890 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1891 min_value = -256;
1892 max_value = 255;
1893 goto sve_imm_offset_vl;
1894
4df068de
RS		 1895 case AARCH64_OPND_SVE_ADDR_RI_U6:
1896 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1897 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1898 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1899 min_value = 0;
1900 max_value = 63;
1901 sve_imm_offset:
1902 assert (!opnd->addr.offset.is_reg);
1903 assert (opnd->addr.preind);
1904 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1905 min_value *= num;
1906 max_value *= num;
1907 if (opnd->shifter.operator_present
1908 || opnd->shifter.amount_present)
1909 {
1910 set_other_error (mismatch_detail, idx,
1911 _("invalid addressing mode"));
1912 return 0;
1913 }
1914 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1915 {
1916 set_offset_out_of_range_error (mismatch_detail, idx,
1917 min_value, max_value);
1918 return 0;
1919 }
1920 if (!value_aligned_p (opnd->addr.offset.imm, num))
1921 {
1922 set_unaligned_error (mismatch_detail, idx, num);
1923 return 0;
1924 }
1925 break;
1926
582e12bf 1927 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
8382113f 1928 case AARCH64_OPND_SVE_ADDR_RI_S4x32:
582e12bf
RS		 1929 min_value = -8;
1930 max_value = 7;
1931 goto sve_imm_offset;
1932
c469c864
MM		 1933 case AARCH64_OPND_SVE_ADDR_ZX:
1934 /* Everything is already ensured by parse_operands or
1935 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1936 argument type). */
1937 assert (opnd->addr.offset.is_reg);
1938 assert (opnd->addr.preind);
1939 assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
1940 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
1941 assert (opnd->shifter.operator_present == 0);
1942 break;
1943
c8d59609 1944 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1945 case AARCH64_OPND_SVE_ADDR_RR:
1946 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1947 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1948 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
01a4d082 1949 case AARCH64_OPND_SVE_ADDR_RR_LSL4:
4df068de
RS		 1950 case AARCH64_OPND_SVE_ADDR_RX:
1951 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1952 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1953 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1954 case AARCH64_OPND_SVE_ADDR_RZ:
1955 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1956 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1957 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1958 modifiers = 1 << AARCH64_MOD_LSL;
1959 sve_rr_operand:
1960 assert (opnd->addr.offset.is_reg);
1961 assert (opnd->addr.preind);
1962 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1963 && opnd->addr.offset.regno == 31)
1964 {
1965 set_other_error (mismatch_detail, idx,
1966 _("index register xzr is not allowed"));
1967 return 0;
1968 }
1969 if (((1 << opnd->shifter.kind) & modifiers) == 0
1970 || (opnd->shifter.amount
1971 != get_operand_specific_data (&aarch64_operands[type])))
1972 {
1973 set_other_error (mismatch_detail, idx,
1974 _("invalid addressing mode"));
1975 return 0;
1976 }
1977 break;
1978
1979 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1980 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1981 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1982 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1983 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1984 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1985 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1986 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1987 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1988 goto sve_rr_operand;
1989
1990 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1991 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1992 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1993 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1994 min_value = 0;
1995 max_value = 31;
1996 goto sve_imm_offset;
1997
1998 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1999 modifiers = 1 << AARCH64_MOD_LSL;
2000 sve_zz_operand:
2001 assert (opnd->addr.offset.is_reg);
2002 assert (opnd->addr.preind);
2003 if (((1 << opnd->shifter.kind) & modifiers) == 0
2004 || opnd->shifter.amount < 0
2005 || opnd->shifter.amount > 3)
2006 {
2007 set_other_error (mismatch_detail, idx,
2008 _("invalid addressing mode"));
2009 return 0;
2010 }
2011 break;
2012
2013 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
2014 modifiers = (1 << AARCH64_MOD_SXTW);
2015 goto sve_zz_operand;
2016
2017 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
2018 modifiers = 1 << AARCH64_MOD_UXTW;
2019 goto sve_zz_operand;
2020
a06ea964
NC		 2021 default:
2022 break;
2023 }
2024 break;
2025
2026 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 2027 if (type == AARCH64_OPND_LEt)
2028 {
2029 /* Get the upper bound for the element index. */
2030 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
2031 if (!value_in_range_p (opnd->reglist.index, 0, num))
2032 {
2033 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2034 return 0;
2035 }
2036 }
a06ea964
NC		 2037 /* The opcode dependent area stores the number of elements in
2038 each structure to be loaded/stored. */
2039 num = get_opcode_dependent_value (opcode);
2040 switch (type)
2041 {
2042 case AARCH64_OPND_LVt:
2043 assert (num >= 1 && num <= 4);
2044 /* Unless LD1/ST1, the number of registers should be equal to that
2045 of the structure elements. */
2046 if (num != 1 && opnd->reglist.num_regs != num)
2047 {
2048 set_reg_list_error (mismatch_detail, idx, num);
2049 return 0;
2050 }
2051 break;
2052 case AARCH64_OPND_LVt_AL:
2053 case AARCH64_OPND_LEt:
2054 assert (num >= 1 && num <= 4);
2055 /* The number of registers should be equal to that of the structure
2056 elements. */
2057 if (opnd->reglist.num_regs != num)
2058 {
2059 set_reg_list_error (mismatch_detail, idx, num);
2060 return 0;
2061 }
2062 break;
2063 default:
2064 break;
2065 }
2066 break;
2067
2068 case AARCH64_OPND_CLASS_IMMEDIATE:
2069 /* Constraint check on immediate operand. */
2070 imm = opnd->imm.value;
2071 /* E.g. imm_0_31 constrains value to be 0..31. */
2072 if (qualifier_value_in_range_constraint_p (qualifier)
2073 && !value_in_range_p (imm, get_lower_bound (qualifier),
2074 get_upper_bound (qualifier)))
2075 {
2076 set_imm_out_of_range_error (mismatch_detail, idx,
2077 get_lower_bound (qualifier),
2078 get_upper_bound (qualifier));
2079 return 0;
2080 }
2081
2082 switch (type)
2083 {
2084 case AARCH64_OPND_AIMM:
2085 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2086 {
2087 set_other_error (mismatch_detail, idx,
2088 _("invalid shift operator"));
2089 return 0;
2090 }
2091 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2092 {
2093 set_other_error (mismatch_detail, idx,
ab3b8fcf 2094 _("shift amount must be 0 or 12"));
a06ea964
NC		 2095 return 0;
2096 }
2097 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2098 {
2099 set_other_error (mismatch_detail, idx,
2100 _("immediate out of range"));
2101 return 0;
2102 }
2103 break;
2104
2105 case AARCH64_OPND_HALF:
2106 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2107 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2108 {
2109 set_other_error (mismatch_detail, idx,
2110 _("invalid shift operator"));
2111 return 0;
2112 }
2113 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2114 if (!value_aligned_p (opnd->shifter.amount, 16))
2115 {
2116 set_other_error (mismatch_detail, idx,
ab3b8fcf 2117 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2118 return 0;
2119 }
2120 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2121 {
2122 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2123 0, size * 8 - 16);
2124 return 0;
2125 }
2126 if (opnd->imm.value < 0)
2127 {
2128 set_other_error (mismatch_detail, idx,
2129 _("negative immediate value not allowed"));
2130 return 0;
2131 }
2132 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2133 {
2134 set_other_error (mismatch_detail, idx,
2135 _("immediate out of range"));
2136 return 0;
2137 }
2138 break;
2139
2140 case AARCH64_OPND_IMM_MOV:
2141 {
42408347 2142 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2143 imm = opnd->imm.value;
2144 assert (idx == 1);
2145 switch (opcode->op)
2146 {
2147 case OP_MOV_IMM_WIDEN:
2148 imm = ~imm;
1a0670f3 2149 /* Fall through. */
a06ea964 2150 case OP_MOV_IMM_WIDE:
42408347 2151 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2152 {
2153 set_other_error (mismatch_detail, idx,
2154 _("immediate out of range"));
2155 return 0;
2156 }
2157 break;
2158 case OP_MOV_IMM_LOG:
42408347 2159 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2160 {
2161 set_other_error (mismatch_detail, idx,
2162 _("immediate out of range"));
2163 return 0;
2164 }
2165 break;
2166 default:
2167 assert (0);
2168 return 0;
2169 }
2170 }
2171 break;
2172
2173 case AARCH64_OPND_NZCV:
2174 case AARCH64_OPND_CCMP_IMM:
2175 case AARCH64_OPND_EXCEPTION:
09c1e68a 2176 case AARCH64_OPND_UNDEFINED:
b83b4b13 2177 case AARCH64_OPND_TME_UIMM16:
a06ea964 2178 case AARCH64_OPND_UIMM4:
193614f2 2179 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2180 case AARCH64_OPND_UIMM7:
2181 case AARCH64_OPND_UIMM3_OP1:
2182 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2183 case AARCH64_OPND_SVE_UIMM3:
2184 case AARCH64_OPND_SVE_UIMM7:
2185 case AARCH64_OPND_SVE_UIMM8:
2186 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2187 size = get_operand_fields_width (get_operand_from_code (type));
2188 assert (size < 32);
2189 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2190 {
2191 set_imm_out_of_range_error (mismatch_detail, idx, 0,
29298bf6 2192 (1u << size) - 1);
a06ea964
NC		 2193 return 0;
2194 }
2195 break;
2196
193614f2
SD		 2197 case AARCH64_OPND_UIMM10:
2198 /* Scaled unsigned 10 bits immediate offset. */
2199 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2200 {
2201 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2202 return 0;
2203 }
2204
2205 if (!value_aligned_p (opnd->imm.value, 16))
2206 {
2207 set_unaligned_error (mismatch_detail, idx, 16);
2208 return 0;
2209 }
2210 break;
2211
e950b345
RS		 2212 case AARCH64_OPND_SIMM5:
2213 case AARCH64_OPND_SVE_SIMM5:
2214 case AARCH64_OPND_SVE_SIMM5B:
2215 case AARCH64_OPND_SVE_SIMM6:
2216 case AARCH64_OPND_SVE_SIMM8:
2217 size = get_operand_fields_width (get_operand_from_code (type));
2218 assert (size < 32);
2219 if (!value_fit_signed_field_p (opnd->imm.value, size))
2220 {
2221 set_imm_out_of_range_error (mismatch_detail, idx,
2222 -(1 << (size - 1)),
2223 (1 << (size - 1)) - 1);
2224 return 0;
2225 }
2226 break;
2227
a06ea964 2228 case AARCH64_OPND_WIDTH:
d685192a 2229 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2230 && opnds[0].type == AARCH64_OPND_Rd);
2231 size = get_upper_bound (qualifier);
2232 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2233 /* lsb+width <= reg.size */
2234 {
2235 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2236 size - opnds[idx-1].imm.value);
2237 return 0;
2238 }
2239 break;
2240
2241 case AARCH64_OPND_LIMM:
e950b345 2242 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2243 {
2244 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2245 uint64_t uimm = opnd->imm.value;
2246 if (opcode->op == OP_BIC)
2247 uimm = ~uimm;
535b785f 2248 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2249 {
2250 set_other_error (mismatch_detail, idx,
2251 _("immediate out of range"));
2252 return 0;
2253 }
2254 }
a06ea964
NC		 2255 break;
2256
2257 case AARCH64_OPND_IMM0:
2258 case AARCH64_OPND_FPIMM0:
2259 if (opnd->imm.value != 0)
2260 {
2261 set_other_error (mismatch_detail, idx,
2262 _("immediate zero expected"));
2263 return 0;
2264 }
2265 break;
2266
c2c4ff8d
SN		 2267 case AARCH64_OPND_IMM_ROT1:
2268 case AARCH64_OPND_IMM_ROT2:
582e12bf 2269 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2270 if (opnd->imm.value != 0
2271 && opnd->imm.value != 90
2272 && opnd->imm.value != 180
2273 && opnd->imm.value != 270)
2274 {
2275 set_other_error (mismatch_detail, idx,
2276 _("rotate expected to be 0, 90, 180 or 270"));
2277 return 0;
2278 }
2279 break;
2280
2281 case AARCH64_OPND_IMM_ROT3:
582e12bf 2282 case AARCH64_OPND_SVE_IMM_ROT1:
adccc507 2283 case AARCH64_OPND_SVE_IMM_ROT3:
c2c4ff8d
SN		 2284 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2285 {
2286 set_other_error (mismatch_detail, idx,
2287 _("rotate expected to be 90 or 270"));
2288 return 0;
2289 }
2290 break;
2291
a06ea964
NC		 2292 case AARCH64_OPND_SHLL_IMM:
2293 assert (idx == 2);
2294 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2295 if (opnd->imm.value != size)
2296 {
2297 set_other_error (mismatch_detail, idx,
2298 _("invalid shift amount"));
2299 return 0;
2300 }
2301 break;
2302
2303 case AARCH64_OPND_IMM_VLSL:
2304 size = aarch64_get_qualifier_esize (qualifier);
2305 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2306 {
2307 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2308 size * 8 - 1);
2309 return 0;
2310 }
2311 break;
2312
2313 case AARCH64_OPND_IMM_VLSR:
2314 size = aarch64_get_qualifier_esize (qualifier);
2315 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2316 {
2317 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2318 return 0;
2319 }
2320 break;
2321
2322 case AARCH64_OPND_SIMD_IMM:
2323 case AARCH64_OPND_SIMD_IMM_SFT:
2324 /* Qualifier check. */
2325 switch (qualifier)
2326 {
2327 case AARCH64_OPND_QLF_LSL:
2328 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2329 {
2330 set_other_error (mismatch_detail, idx,
2331 _("invalid shift operator"));
2332 return 0;
2333 }
2334 break;
2335 case AARCH64_OPND_QLF_MSL:
2336 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2337 {
2338 set_other_error (mismatch_detail, idx,
2339 _("invalid shift operator"));
2340 return 0;
2341 }
2342 break;
2343 case AARCH64_OPND_QLF_NIL:
2344 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2345 {
2346 set_other_error (mismatch_detail, idx,
2347 _("shift is not permitted"));
2348 return 0;
2349 }
2350 break;
2351 default:
2352 assert (0);
2353 return 0;
2354 }
2355 /* Is the immediate valid? */
2356 assert (idx == 1);
2357 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2358 {
d2865ed3
YZ		 2359 /* uimm8 or simm8 */
2360 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2361 {
d2865ed3 2362 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2363 return 0;
2364 }
2365 }
2366 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2367 {
2368 /* uimm64 is not
2369 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2370 ffffffffgggggggghhhhhhhh'. */
2371 set_other_error (mismatch_detail, idx,
2372 _("invalid value for immediate"));
2373 return 0;
2374 }
2375 /* Is the shift amount valid? */
2376 switch (opnd->shifter.kind)
2377 {
2378 case AARCH64_MOD_LSL:
2379 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2380 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2381 {
f5555712
YZ		 2382 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2383 (size - 1) * 8);
a06ea964
NC		 2384 return 0;
2385 }
f5555712 2386 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2387 {
f5555712 2388 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2389 return 0;
2390 }
2391 break;
2392 case AARCH64_MOD_MSL:
2393 /* Only 8 and 16 are valid shift amount. */
2394 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2395 {
2396 set_other_error (mismatch_detail, idx,
ab3b8fcf 2397 _("shift amount must be 0 or 16"));
a06ea964
NC		 2398 return 0;
2399 }
2400 break;
2401 default:
2402 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2403 {
2404 set_other_error (mismatch_detail, idx,
2405 _("invalid shift operator"));
2406 return 0;
2407 }
2408 break;
2409 }
2410 break;
2411
2412 case AARCH64_OPND_FPIMM:
2413 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2414 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2415 if (opnd->imm.is_fp == 0)
2416 {
2417 set_other_error (mismatch_detail, idx,
2418 _("floating-point immediate expected"));
2419 return 0;
2420 }
2421 /* The value is expected to be an 8-bit floating-point constant with
2422 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2423 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2424 instruction). */
2425 if (!value_in_range_p (opnd->imm.value, 0, 255))
2426 {
2427 set_other_error (mismatch_detail, idx,
2428 _("immediate out of range"));
2429 return 0;
2430 }
2431 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2432 {
2433 set_other_error (mismatch_detail, idx,
2434 _("invalid shift operator"));
2435 return 0;
2436 }
2437 break;
2438
e950b345
RS		 2439 case AARCH64_OPND_SVE_AIMM:
2440 min_value = 0;
2441 sve_aimm:
2442 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2443 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2444 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2445 uvalue = opnd->imm.value;
2446 shift = opnd->shifter.amount;
2447 if (size == 1)
2448 {
2449 if (shift != 0)
2450 {
2451 set_other_error (mismatch_detail, idx,
2452 _("no shift amount allowed for"
2453 " 8-bit constants"));
2454 return 0;
2455 }
2456 }
2457 else
2458 {
2459 if (shift != 0 && shift != 8)
2460 {
2461 set_other_error (mismatch_detail, idx,
2462 _("shift amount must be 0 or 8"));
2463 return 0;
2464 }
2465 if (shift == 0 && (uvalue & 0xff) == 0)
2466 {
2467 shift = 8;
2468 uvalue = (int64_t) uvalue / 256;
2469 }
2470 }
2471 mask >>= shift;
2472 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2473 {
2474 set_other_error (mismatch_detail, idx,
2475 _("immediate too big for element size"));
2476 return 0;
2477 }
2478 uvalue = (uvalue - min_value) & mask;
2479 if (uvalue > 0xff)
2480 {
2481 set_other_error (mismatch_detail, idx,
2482 _("invalid arithmetic immediate"));
2483 return 0;
2484 }
2485 break;
2486
2487 case AARCH64_OPND_SVE_ASIMM:
2488 min_value = -128;
2489 goto sve_aimm;
2490
165d4950
RS		 2491 case AARCH64_OPND_SVE_I1_HALF_ONE:
2492 assert (opnd->imm.is_fp);
2493 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2494 {
2495 set_other_error (mismatch_detail, idx,
2496 _("floating-point value must be 0.5 or 1.0"));
2497 return 0;
2498 }
2499 break;
2500
2501 case AARCH64_OPND_SVE_I1_HALF_TWO:
2502 assert (opnd->imm.is_fp);
2503 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2504 {
2505 set_other_error (mismatch_detail, idx,
2506 _("floating-point value must be 0.5 or 2.0"));
2507 return 0;
2508 }
2509 break;
2510
2511 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2512 assert (opnd->imm.is_fp);
2513 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2514 {
2515 set_other_error (mismatch_detail, idx,
2516 _("floating-point value must be 0.0 or 1.0"));
2517 return 0;
2518 }
2519 break;
2520
e950b345
RS		 2521 case AARCH64_OPND_SVE_INV_LIMM:
2522 {
2523 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2524 uint64_t uimm = ~opnd->imm.value;
2525 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2526 {
2527 set_other_error (mismatch_detail, idx,
2528 _("immediate out of range"));
2529 return 0;
2530 }
2531 }
2532 break;
2533
2534 case AARCH64_OPND_SVE_LIMM_MOV:
2535 {
2536 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2537 uint64_t uimm = opnd->imm.value;
2538 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2539 {
2540 set_other_error (mismatch_detail, idx,
2541 _("immediate out of range"));
2542 return 0;
2543 }
2544 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2545 {
2546 set_other_error (mismatch_detail, idx,
2547 _("invalid replicated MOV immediate"));
2548 return 0;
2549 }
2550 }
2551 break;
2552
2442d846
RS		 2553 case AARCH64_OPND_SVE_PATTERN_SCALED:
2554 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2555 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2556 {
2557 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2558 return 0;
2559 }
2560 break;
2561
e950b345
RS		 2562 case AARCH64_OPND_SVE_SHLIMM_PRED:
2563 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 2564 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 2565 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2566 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2567 {
2568 set_imm_out_of_range_error (mismatch_detail, idx,
2569 0, 8 * size - 1);
2570 return 0;
2571 }
2572 break;
2573
2574 case AARCH64_OPND_SVE_SHRIMM_PRED:
2575 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 2576 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
4f5fc85d
JB		 2577 num = (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
2578 size = aarch64_get_qualifier_esize (opnds[idx - num].qualifier);
2579 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
e950b345 2580 {
4f5fc85d
JB		 2581 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
2582 return 0;
2583 }
2584 break;
e950b345 2585
a06ea964
NC		 2586 default:
2587 break;
2588 }
2589 break;
2590
a06ea964
NC		 2591 case AARCH64_OPND_CLASS_SYSTEM:
2592 switch (type)
2593 {
2594 case AARCH64_OPND_PSTATEFIELD:
2595 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2596 /* MSR UAO, #uimm4
2597 MSR PAN, #uimm4
104fefee 2598 MSR SSBS,#uimm4
3dd032c5
PW		 2599 MSR SVCRSM, #uimm4
2600 MSR SVCRZA, #uimm4
2601 MSR SVCRSMZA, #uimm4
c2825638 2602 The immediate must be #0 or #1. */
0bff6e2d 2603 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2604 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2605 || opnd->pstatefield == 0x19 /* SSBS. */
3dd032c5
PW		 2606 || opnd->pstatefield == 0x1a /* DIT. */
2607 || opnd->pstatefield == 0x1b) /* SVCRSM, SVCRZA or SVCRSMZA. */
c2825638
MW		 2608 && opnds[1].imm.value > 1)
2609 {
2610 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2611 return 0;
2612 }
a06ea964
NC		 2613 /* MSR SPSel, #uimm4
2614 Uses uimm4 as a control value to select the stack pointer: if
2615 bit 0 is set it selects the current exception level's stack
2616 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2617 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2618 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2619 {
2620 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2621 return 0;
2622 }
2623 break;
2624 default:
2625 break;
2626 }
2627 break;
2628
2629 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2630 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2631 if (opcode->op == OP_FCMLA_ELEM)
2632 /* FCMLA index range depends on the vector size of other operands
2633 and is halfed because complex numbers take two elements. */
2634 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2635 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2636 else
2637 num = 16;
2638 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2639 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2640
a06ea964
NC		 2641 /* Index out-of-range. */
2642 if (!value_in_range_p (opnd->reglane.index, 0, num))
2643 {
2644 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2645 return 0;
2646 }
2647 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2648 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2649 number is encoded in "size:M:Rm":
2650 size <Vm>
2651 00 RESERVED
2652 01 0:Rm
2653 10 M:Rm
2654 11 RESERVED */
369c9167 2655 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2656 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2657 {
2658 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2659 return 0;
2660 }
2661 break;
2662
2663 case AARCH64_OPND_CLASS_MODIFIED_REG:
2664 assert (idx == 1 || idx == 2);
2665 switch (type)
2666 {
2667 case AARCH64_OPND_Rm_EXT:
535b785f 2668 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2669 && opnd->shifter.kind != AARCH64_MOD_LSL)
2670 {
2671 set_other_error (mismatch_detail, idx,
2672 _("extend operator expected"));
2673 return 0;
2674 }
2675 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2676 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2677 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2678 case. */
2679 if (!aarch64_stack_pointer_p (opnds + 0)
2680 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2681 {
2682 if (!opnd->shifter.operator_present)
2683 {
2684 set_other_error (mismatch_detail, idx,
2685 _("missing extend operator"));
2686 return 0;
2687 }
2688 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2689 {
2690 set_other_error (mismatch_detail, idx,
2691 _("'LSL' operator not allowed"));
2692 return 0;
2693 }
2694 }
2695 assert (opnd->shifter.operator_present /* Default to LSL. */
2696 || opnd->shifter.kind == AARCH64_MOD_LSL);
2697 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2698 {
2699 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2700 return 0;
2701 }
2702 /* In the 64-bit form, the final register operand is written as Wm
2703 for all but the (possibly omitted) UXTX/LSL and SXTX
2704 operators.
2705 N.B. GAS allows X register to be used with any operator as a
2706 programming convenience. */
2707 if (qualifier == AARCH64_OPND_QLF_X
2708 && opnd->shifter.kind != AARCH64_MOD_LSL
2709 && opnd->shifter.kind != AARCH64_MOD_UXTX
2710 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2711 {
2712 set_other_error (mismatch_detail, idx, _("W register expected"));
2713 return 0;
2714 }
2715 break;
2716
2717 case AARCH64_OPND_Rm_SFT:
2718 /* ROR is not available to the shifted register operand in
2719 arithmetic instructions. */
535b785f 2720 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2721 {
2722 set_other_error (mismatch_detail, idx,
2723 _("shift operator expected"));
2724 return 0;
2725 }
2726 if (opnd->shifter.kind == AARCH64_MOD_ROR
2727 && opcode->iclass != log_shift)
2728 {
2729 set_other_error (mismatch_detail, idx,
2730 _("'ROR' operator not allowed"));
2731 return 0;
2732 }
2733 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2734 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2735 {
2736 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2737 return 0;
2738 }
2739 break;
2740
2741 default:
2742 break;
2743 }
2744 break;
2745
2746 default:
2747 break;
2748 }
2749
2750 return 1;
2751}
2752
2753/* Main entrypoint for the operand constraint checking.
2754
2755 Return 1 if operands of *INST meet the constraint applied by the operand
2756 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2757 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2758 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2759 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2760 error kind when it is notified that an instruction does not pass the check).
2761
2762 Un-determined operand qualifiers may get established during the process. */
2763
2764int
2765aarch64_match_operands_constraint (aarch64_inst *inst,
2766 aarch64_operand_error *mismatch_detail)
2767{
2768 int i;
2769
2770 DEBUG_TRACE ("enter");
2771
0c608d6b 2772 i = inst->opcode->tied_operand;
01a4d082
PW		 2773
2774 if (i > 0)
0c608d6b 2775 {
01a4d082
PW		 2776 /* Check for tied_operands with specific opcode iclass. */
2777 switch (inst->opcode->iclass)
2778 {
2779 /* For SME LDR and STR instructions #imm must have the same numerical
2780 value for both operands.
2781 */
2782 case sme_ldr:
2783 case sme_str:
2784 assert (inst->operands[0].type == AARCH64_OPND_SME_ZA_array);
2785 assert (inst->operands[1].type == AARCH64_OPND_SME_ADDR_RI_U4xVL);
2786 if (inst->operands[0].za_tile_vector.index.imm
2787 != inst->operands[1].addr.offset.imm)
2788 {
2789 if (mismatch_detail)
2790 {
2791 mismatch_detail->kind = AARCH64_OPDE_UNTIED_IMMS;
2792 mismatch_detail->index = i;
2793 }
2794 return 0;
2795 }
2796 break;
2797
2798 default:
2799 /* Check for cases where a source register needs to be the same as the
2800 destination register. Do this before matching qualifiers since if
2801 an instruction has both invalid tying and invalid qualifiers,
2802 the error about qualifiers would suggest several alternative
2803 instructions that also have invalid tying. */
2804 if (inst->operands[0].reg.regno
2805 != inst->operands[i].reg.regno)
2806 {
2807 if (mismatch_detail)
2808 {
2809 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2810 mismatch_detail->index = i;
2811 mismatch_detail->error = NULL;
2812 }
2813 return 0;
2814 }
2815 break;
2816 }
0c608d6b
RS		 2817 }
2818
a06ea964
NC		 2819 /* Match operands' qualifier.
2820 *INST has already had qualifier establish for some, if not all, of
2821 its operands; we need to find out whether these established
2822 qualifiers match one of the qualifier sequence in
2823 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2824 with the corresponding qualifier in such a sequence.
2825 Only basic operand constraint checking is done here; the more thorough
2826 constraint checking will carried out by operand_general_constraint_met_p,
2827 which has be to called after this in order to get all of the operands'
2828 qualifiers established. */
78933a4a 2829 if (match_operands_qualifier (inst, true /* update_p */) == 0)
a06ea964
NC		 2830 {
2831 DEBUG_TRACE ("FAIL on operand qualifier matching");
2832 if (mismatch_detail)
2833 {
2834 /* Return an error type to indicate that it is the qualifier
2835 matching failure; we don't care about which operand as there
2836 are enough information in the opcode table to reproduce it. */
2837 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2838 mismatch_detail->index = -1;
2839 mismatch_detail->error = NULL;
2840 }
2841 return 0;
2842 }
2843
2844 /* Match operands' constraint. */
2845 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2846 {
2847 enum aarch64_opnd type = inst->opcode->operands[i];
2848 if (type == AARCH64_OPND_NIL)
2849 break;
2850 if (inst->operands[i].skip)
2851 {
2852 DEBUG_TRACE ("skip the incomplete operand %d", i);
2853 continue;
2854 }
2855 if (operand_general_constraint_met_p (inst->operands, i, type,
2856 inst->opcode, mismatch_detail) == 0)
2857 {
2858 DEBUG_TRACE ("FAIL on operand %d", i);
2859 return 0;
2860 }
2861 }
2862
2863 DEBUG_TRACE ("PASS");
2864
2865 return 1;
2866}
2867
2868/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2869 Also updates the TYPE of each INST->OPERANDS with the corresponding
2870 value of OPCODE->OPERANDS.
2871
2872 Note that some operand qualifiers may need to be manually cleared by
2873 the caller before it further calls the aarch64_opcode_encode; by
2874 doing this, it helps the qualifier matching facilities work
2875 properly. */
2876
2877const aarch64_opcode*
2878aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2879{
2880 int i;
2881 const aarch64_opcode *old = inst->opcode;
2882
2883 inst->opcode = opcode;
2884
2885 /* Update the operand types. */
2886 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2887 {
2888 inst->operands[i].type = opcode->operands[i];
2889 if (opcode->operands[i] == AARCH64_OPND_NIL)
2890 break;
2891 }
2892
2893 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2894
2895 return old;
2896}
2897
2898int
2899aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2900{
2901 int i;
2902 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2903 if (operands[i] == operand)
2904 return i;
2905 else if (operands[i] == AARCH64_OPND_NIL)
2906 break;
2907 return -1;
2908}
2909\f
72e9f319
RS		 2910/* R0...R30, followed by FOR31. */
2911#define BANK(R, FOR31) \
2912 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2913 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2914 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2915 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2916/* [0][0] 32-bit integer regs with sp Wn
2917 [0][1] 64-bit integer regs with sp Xn sf=1
2918 [1][0] 32-bit integer regs with #0 Wn
2919 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2920static const char *int_reg[2][2][32] = {
72e9f319
RS		 2921#define R32(X) "w" #X
2922#define R64(X) "x" #X
2923 { BANK (R32, "wsp"), BANK (R64, "sp") },
2924 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2925#undef R64
2926#undef R32
2927};
4df068de
RS		 2928
2929/* Names of the SVE vector registers, first with .S suffixes,
2930 then with .D suffixes. */
2931
2932static const char *sve_reg[2][32] = {
2933#define ZS(X) "z" #X ".s"
2934#define ZD(X) "z" #X ".d"
2935 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2936#undef ZD
2937#undef ZS
2938};
72e9f319 2939#undef BANK
a06ea964
NC		 2940
2941/* Return the integer register name.
2942 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2943
2944static inline const char *
2945get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2946{
2947 const int has_zr = sp_reg_p ? 0 : 1;
2948 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2949 return int_reg[has_zr][is_64][regno];
2950}
2951
2952/* Like get_int_reg_name, but IS_64 is always 1. */
2953
2954static inline const char *
2955get_64bit_int_reg_name (int regno, int sp_reg_p)
2956{
2957 const int has_zr = sp_reg_p ? 0 : 1;
2958 return int_reg[has_zr][1][regno];
2959}
2960
01dbfe4c
RS		 2961/* Get the name of the integer offset register in OPND, using the shift type
2962 to decide whether it's a word or doubleword. */
2963
2964static inline const char *
2965get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2966{
2967 switch (opnd->shifter.kind)
2968 {
2969 case AARCH64_MOD_UXTW:
2970 case AARCH64_MOD_SXTW:
2971 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2972
2973 case AARCH64_MOD_LSL:
2974 case AARCH64_MOD_SXTX:
2975 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2976
2977 default:
2978 abort ();
2979 }
2980}
2981
4df068de
RS		 2982/* Get the name of the SVE vector offset register in OPND, using the operand
2983 qualifier to decide whether the suffix should be .S or .D. */
2984
2985static inline const char *
2986get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2987{
2988 assert (qualifier == AARCH64_OPND_QLF_S_S
2989 || qualifier == AARCH64_OPND_QLF_S_D);
2990 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2991}
2992
a06ea964
NC		 2993/* Types for expanding an encoded 8-bit value to a floating-point value. */
2994
2995typedef union
2996{
2997 uint64_t i;
2998 double d;
2999} double_conv_t;
3000
3001typedef union
3002{
3003 uint32_t i;
3004 float f;
3005} single_conv_t;
3006
cf86120b
MW		 3007typedef union
3008{
3009 uint32_t i;
3010 float f;
3011} half_conv_t;
3012
a06ea964
NC		 3013/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
3014 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
3015 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 3016 single-precision floating-point value (SIZE == 4) or a double-precision
3017 floating-point value (SIZE == 8). A half-precision floating-point value
3018 (SIZE == 2) is expanded to a single-precision floating-point value. The
3019 expanded value is returned. */
a06ea964
NC		 3020
3021static uint64_t
cf86120b 3022expand_fp_imm (int size, uint32_t imm8)
a06ea964 3023{
57a024f4 3024 uint64_t imm = 0;
a06ea964
NC		 3025 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
3026
3027 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
3028 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
3029 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
3030 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
3031 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 3032 if (size == 8)
a06ea964
NC		 3033 {
3034 imm = (imm8_7 << (63-32)) /* imm8<7> */
3035 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
3036 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
3037 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
3038 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
3039 imm <<= 32;
3040 }
cf86120b 3041 else if (size == 4 || size == 2)
a06ea964
NC		 3042 {
3043 imm = (imm8_7 << 31) /* imm8<7> */
3044 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
3045 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
3046 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
3047 }
cf86120b
MW		 3048 else
3049 {
3050 /* An unsupported size. */
3051 assert (0);
3052 }
a06ea964
NC		 3053
3054 return imm;
3055}
3056
3057/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 3058 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
3059 the register name that comes before the register number, such as "v". */
a06ea964 3060static void
8a7f0c1b
RS		 3061print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3062 const char *prefix)
a06ea964
NC		 3063{
3064 const int num_regs = opnd->reglist.num_regs;
3065 const int first_reg = opnd->reglist.first_regno;
3066 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
3067 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3068 char tb[8]; /* Temporary buffer. */
3069
3070 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3071 assert (num_regs >= 1 && num_regs <= 4);
3072
3073 /* Prepare the index if any. */
3074 if (opnd->reglist.has_index)
1b7e3d2f
NC		 3075 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3076 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 3077 else
3078 tb[0] = '\0';
3079
3080 /* The hyphenated form is preferred for disassembly if there are
3081 more than two registers in the list, and the register numbers
3082 are monotonically increasing in increments of one. */
3083 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 3084 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3085 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 3086 else
3087 {
3088 const int reg0 = first_reg;
3089 const int reg1 = (first_reg + 1) & 0x1f;
3090 const int reg2 = (first_reg + 2) & 0x1f;
3091 const int reg3 = (first_reg + 3) & 0x1f;
3092
3093 switch (num_regs)
3094 {
3095 case 1:
8a7f0c1b 3096 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3097 break;
3098 case 2:
8a7f0c1b
RS		 3099 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3100 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3101 break;
3102 case 3:
8a7f0c1b
RS		 3103 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3104 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3105 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3106 break;
3107 case 4:
8a7f0c1b
RS		 3108 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3109 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3110 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3111 break;
3112 }
3113 }
3114}
3115
01dbfe4c
RS		 3116/* Print the register+immediate address in OPND to BUF, which has SIZE
3117 characters. BASE is the name of the base register. */
3118
3119static void
3120print_immediate_offset_address (char *buf, size_t size,
3121 const aarch64_opnd_info *opnd,
3122 const char *base)
3123{
3124 if (opnd->addr.writeback)
3125 {
3126 if (opnd->addr.preind)
1820262b
DB		 3127 {
3128 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3129 snprintf (buf, size, "[%s]!", base);
3130 else
3131 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
3132 }
01dbfe4c 3133 else
ad43e107 3134 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3135 }
3136 else
3137 {
98907a70
RS		 3138 if (opnd->shifter.operator_present)
3139 {
3140 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3141 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3142 base, opnd->addr.offset.imm);
3143 }
3144 else if (opnd->addr.offset.imm)
ad43e107 3145 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3146 else
3147 snprintf (buf, size, "[%s]", base);
3148 }
3149}
3150
a06ea964 3151/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3152 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3153 the names of the base and offset registers. */
a06ea964
NC		 3154static void
3155print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3156 const aarch64_opnd_info *opnd,
3157 const char *base, const char *offset)
a06ea964 3158{
0d2f91fe 3159 char tb[16]; /* Temporary buffer. */
78933a4a
AM		 3160 bool print_extend_p = true;
3161 bool print_amount_p = true;
a06ea964
NC		 3162 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3163
a06ea964
NC		 3164 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3165 || !opnd->shifter.amount_present))
3166 {
3167 /* Not print the shift/extend amount when the amount is zero and
3168 when it is not the special case of 8-bit load/store instruction. */
78933a4a 3169 print_amount_p = false;
a06ea964
NC		 3170 /* Likewise, no need to print the shift operator LSL in such a
3171 situation. */
01dbfe4c 3172 if (opnd->shifter.kind == AARCH64_MOD_LSL)
78933a4a 3173 print_extend_p = false;
a06ea964
NC		 3174 }
3175
3176 /* Prepare for the extend/shift. */
3177 if (print_extend_p)
3178 {
3179 if (print_amount_p)
ad43e107 3180 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3181 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3182 (opnd->shifter.amount % 100));
a06ea964 3183 else
ad43e107 3184 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3185 }
3186 else
3187 tb[0] = '\0';
3188
ad43e107 3189 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3190}
3191
1cad938d
PW		 3192/* Print ZA tiles from imm8 in ZERO instruction.
3193
3194 The preferred disassembly of this instruction uses the shortest list of tile
3195 names that represent the encoded immediate mask.
3196
3197 For example:
3198 * An all-ones immediate is disassembled as {ZA}.
3199 * An all-zeros immediate is disassembled as an empty list { }.
3200*/
3201static void
3202print_sme_za_list(char *buf, size_t size, int mask)
3203{
3204 const char* zan[] = { "za", "za0.h", "za1.h", "za0.s",
3205 "za1.s", "za2.s", "za3.s", "za0.d",
3206 "za1.d", "za2.d", "za3.d", "za4.d",
3207 "za5.d", "za6.d", "za7.d", " " };
3208 const int zan_v[] = { 0xff, 0x55, 0xaa, 0x11,
3209 0x22, 0x44, 0x88, 0x01,
3210 0x02, 0x04, 0x08, 0x10,
3211 0x20, 0x40, 0x80, 0x00 };
3212 int i, k;
3213 const int ZAN_SIZE = sizeof(zan) / sizeof(zan[0]);
3214
3215 k = snprintf (buf, size, "{");
3216 for (i = 0; i < ZAN_SIZE; i++)
3217 {
3218 if ((mask & zan_v[i]) == zan_v[i])
3219 {
3220 mask &= ~zan_v[i];
3221 if (k > 1)
3222 k += snprintf (buf + k, size - k, ", %s", zan[i]);
3223 else
3224 k += snprintf (buf + k, size - k, "%s", zan[i]);
3225 }
3226 if (mask == 0)
3227 break;
3228 }
3229 snprintf (buf + k, size - k, "}");
3230}
3231
a06ea964
NC		 3232/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3233 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3234 PC, PCREL_P and ADDRESS are used to pass in and return information about
3235 the PC-relative address calculation, where the PC value is passed in
3236 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3237 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3238 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3239
3240 The function serves both the disassembler and the assembler diagnostics
3241 issuer, which is the reason why it lives in this file. */
3242
3243void
3244aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3245 const aarch64_opcode *opcode,
3246 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
38cf07a6
AC		 3247 bfd_vma *address, char** notes,
3248 aarch64_feature_set features)
a06ea964 3249{
bb7eff52 3250 unsigned int i, num_conds;
a06ea964
NC		 3251 const char *name = NULL;
3252 const aarch64_opnd_info *opnd = opnds + idx;
3253 enum aarch64_modifier_kind kind;
245d2e3f 3254 uint64_t addr, enum_value;
a06ea964
NC		 3255
3256 buf[0] = '\0';
3257 if (pcrel_p)
3258 *pcrel_p = 0;
3259
3260 switch (opnd->type)
3261 {
3262 case AARCH64_OPND_Rd:
3263 case AARCH64_OPND_Rn:
3264 case AARCH64_OPND_Rm:
3265 case AARCH64_OPND_Rt:
3266 case AARCH64_OPND_Rt2:
3267 case AARCH64_OPND_Rs:
3268 case AARCH64_OPND_Ra:
8edca81e 3269 case AARCH64_OPND_Rt_LS64:
a06ea964 3270 case AARCH64_OPND_Rt_SYS:
ee804238 3271 case AARCH64_OPND_PAIRREG:
047cd301 3272 case AARCH64_OPND_SVE_Rm:
a06ea964 3273 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3274 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3275 generic optional-ness information. */
362c0c4d
JW		 3276 if (opnd->type == AARCH64_OPND_Rt_SYS)
3277 {
3278 if (!opnd->present)
3279 break;
3280 }
a06ea964 3281 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3282 else if (optional_operand_p (opcode, idx)
3283 && (opnd->reg.regno
3284 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3285 break;
3286 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3287 || opnd->qualifier == AARCH64_OPND_QLF_X);
3288 snprintf (buf, size, "%s",
3289 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3290 break;
3291
3292 case AARCH64_OPND_Rd_SP:
3293 case AARCH64_OPND_Rn_SP:
bd7ceb8d 3294 case AARCH64_OPND_Rt_SP:
047cd301 3295 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3296 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3297 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3298 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3299 || opnd->qualifier == AARCH64_OPND_QLF_X
3300 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3301 snprintf (buf, size, "%s",
3302 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3303 break;
3304
3305 case AARCH64_OPND_Rm_EXT:
3306 kind = opnd->shifter.kind;
3307 assert (idx == 1 || idx == 2);
3308 if ((aarch64_stack_pointer_p (opnds)
3309 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3310 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3311 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3312 && kind == AARCH64_MOD_UXTW)
3313 || (opnd->qualifier == AARCH64_OPND_QLF_X
3314 && kind == AARCH64_MOD_UXTX)))
3315 {
3316 /* 'LSL' is the preferred form in this case. */
3317 kind = AARCH64_MOD_LSL;
3318 if (opnd->shifter.amount == 0)
3319 {
3320 /* Shifter omitted. */
3321 snprintf (buf, size, "%s",
3322 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3323 break;
3324 }
3325 }
3326 if (opnd->shifter.amount)
2442d846 3327 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3328 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3329 aarch64_operand_modifiers[kind].name,
3330 opnd->shifter.amount);
3331 else
3332 snprintf (buf, size, "%s, %s",
3333 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3334 aarch64_operand_modifiers[kind].name);
3335 break;
3336
3337 case AARCH64_OPND_Rm_SFT:
3338 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3339 || opnd->qualifier == AARCH64_OPND_QLF_X);
3340 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3341 snprintf (buf, size, "%s",
3342 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3343 else
2442d846 3344 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3345 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3346 aarch64_operand_modifiers[opnd->shifter.kind].name,
3347 opnd->shifter.amount);
3348 break;
3349
3350 case AARCH64_OPND_Fd:
3351 case AARCH64_OPND_Fn:
3352 case AARCH64_OPND_Fm:
3353 case AARCH64_OPND_Fa:
3354 case AARCH64_OPND_Ft:
3355 case AARCH64_OPND_Ft2:
3356 case AARCH64_OPND_Sd:
3357 case AARCH64_OPND_Sn:
3358 case AARCH64_OPND_Sm:
047cd301
RS		 3359 case AARCH64_OPND_SVE_VZn:
3360 case AARCH64_OPND_SVE_Vd:
3361 case AARCH64_OPND_SVE_Vm:
3362 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3363 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3364 opnd->reg.regno);
3365 break;
3366
f42f1a1d 3367 case AARCH64_OPND_Va:
a06ea964
NC		 3368 case AARCH64_OPND_Vd:
3369 case AARCH64_OPND_Vn:
3370 case AARCH64_OPND_Vm:
3371 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3372 aarch64_get_qualifier_name (opnd->qualifier));
3373 break;
3374
3375 case AARCH64_OPND_Ed:
3376 case AARCH64_OPND_En:
3377 case AARCH64_OPND_Em:
369c9167 3378 case AARCH64_OPND_Em16:
f42f1a1d 3379 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3380 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3381 aarch64_get_qualifier_name (opnd->qualifier),
3382 opnd->reglane.index);
3383 break;
3384
3385 case AARCH64_OPND_VdD1:
3386 case AARCH64_OPND_VnD1:
3387 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3388 break;
3389
3390 case AARCH64_OPND_LVn:
3391 case AARCH64_OPND_LVt:
3392 case AARCH64_OPND_LVt_AL:
3393 case AARCH64_OPND_LEt:
8a7f0c1b 3394 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3395 break;
3396
f11ad6bc
RS		 3397 case AARCH64_OPND_SVE_Pd:
3398 case AARCH64_OPND_SVE_Pg3:
3399 case AARCH64_OPND_SVE_Pg4_5:
3400 case AARCH64_OPND_SVE_Pg4_10:
3401 case AARCH64_OPND_SVE_Pg4_16:
3402 case AARCH64_OPND_SVE_Pm:
3403 case AARCH64_OPND_SVE_Pn:
3404 case AARCH64_OPND_SVE_Pt:
971eda73 3405 case AARCH64_OPND_SME_Pm:
f11ad6bc
RS		 3406 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3407 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3408 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3409 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3410 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3411 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3412 else
3413 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3414 aarch64_get_qualifier_name (opnd->qualifier));
3415 break;
3416
3417 case AARCH64_OPND_SVE_Za_5:
3418 case AARCH64_OPND_SVE_Za_16:
3419 case AARCH64_OPND_SVE_Zd:
3420 case AARCH64_OPND_SVE_Zm_5:
3421 case AARCH64_OPND_SVE_Zm_16:
3422 case AARCH64_OPND_SVE_Zn:
3423 case AARCH64_OPND_SVE_Zt:
3424 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3425 snprintf (buf, size, "z%d", opnd->reg.regno);
3426 else
3427 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3428 aarch64_get_qualifier_name (opnd->qualifier));
3429 break;
3430
3431 case AARCH64_OPND_SVE_ZnxN:
3432 case AARCH64_OPND_SVE_ZtxN:
3433 print_register_list (buf, size, opnd, "z");
3434 break;
3435
582e12bf
RS		 3436 case AARCH64_OPND_SVE_Zm3_INDEX:
3437 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 3438 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 3439 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf 3440 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3441 case AARCH64_OPND_SVE_Zn_INDEX:
3442 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3443 aarch64_get_qualifier_name (opnd->qualifier),
3444 opnd->reglane.index);
3445 break;
3446
971eda73
PW		 3447 case AARCH64_OPND_SME_ZAda_2b:
3448 case AARCH64_OPND_SME_ZAda_3b:
3449 snprintf (buf, size, "za%d.%s", opnd->reg.regno,
3450 aarch64_get_qualifier_name (opnd->qualifier));
3451 break;
3452
7bb5f07c
PW		 3453 case AARCH64_OPND_SME_ZA_HV_idx_src:
3454 case AARCH64_OPND_SME_ZA_HV_idx_dest:
01a4d082
PW		 3455 case AARCH64_OPND_SME_ZA_HV_idx_ldstr:
3456 snprintf (buf, size, "%sza%d%c.%s[w%d, %d]%s",
3457 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "{" : "",
7bb5f07c
PW		 3458 opnd->za_tile_vector.regno,
3459 opnd->za_tile_vector.v == 1 ? 'v' : 'h',
3460 aarch64_get_qualifier_name (opnd->qualifier),
3461 opnd->za_tile_vector.index.regno,
01a4d082
PW		 3462 opnd->za_tile_vector.index.imm,
3463 opnd->type == AARCH64_OPND_SME_ZA_HV_idx_ldstr ? "}" : "");
7bb5f07c
PW		 3464 break;
3465
1cad938d
PW		 3466 case AARCH64_OPND_SME_list_of_64bit_tiles:
3467 print_sme_za_list (buf, size, opnd->reg.regno);
3468 break;
3469
01a4d082
PW		 3470 case AARCH64_OPND_SME_ZA_array:
3471 snprintf (buf, size, "za[w%d, %d]",
3472 opnd->za_tile_vector.index.regno,
3473 opnd->za_tile_vector.index.imm);
3474 break;
3475
3dd032c5
PW		 3476 case AARCH64_OPND_SME_SM_ZA:
3477 snprintf (buf, size, "%s", opnd->reg.regno == 's' ? "sm" : "za");
3478 break;
3479
d3de0860
PW		 3480 case AARCH64_OPND_SME_PnT_Wm_imm:
3481 snprintf (buf, size, "p%d.%s[w%d, %d]",
3482 opnd->za_tile_vector.regno,
3483 aarch64_get_qualifier_name (opnd->qualifier),
3484 opnd->za_tile_vector.index.regno,
3485 opnd->za_tile_vector.index.imm);
3486 break;
3487
a6a51754
RL		 3488 case AARCH64_OPND_CRn:
3489 case AARCH64_OPND_CRm:
3490 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3491 break;
3492
3493 case AARCH64_OPND_IDX:
f42f1a1d 3494 case AARCH64_OPND_MASK:
a06ea964 3495 case AARCH64_OPND_IMM:
f42f1a1d 3496 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3497 case AARCH64_OPND_WIDTH:
3498 case AARCH64_OPND_UIMM3_OP1:
3499 case AARCH64_OPND_UIMM3_OP2:
3500 case AARCH64_OPND_BIT_NUM:
3501 case AARCH64_OPND_IMM_VLSL:
3502 case AARCH64_OPND_IMM_VLSR:
3503 case AARCH64_OPND_SHLL_IMM:
3504 case AARCH64_OPND_IMM0:
3505 case AARCH64_OPND_IMMR:
3506 case AARCH64_OPND_IMMS:
09c1e68a 3507 case AARCH64_OPND_UNDEFINED:
a06ea964 3508 case AARCH64_OPND_FBITS:
b83b4b13 3509 case AARCH64_OPND_TME_UIMM16:
e950b345
RS		 3510 case AARCH64_OPND_SIMM5:
3511 case AARCH64_OPND_SVE_SHLIMM_PRED:
3512 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 3513 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 3514 case AARCH64_OPND_SVE_SHRIMM_PRED:
3515 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 3516 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345
RS		 3517 case AARCH64_OPND_SVE_SIMM5:
3518 case AARCH64_OPND_SVE_SIMM5B:
3519 case AARCH64_OPND_SVE_SIMM6:
3520 case AARCH64_OPND_SVE_SIMM8:
3521 case AARCH64_OPND_SVE_UIMM3:
3522 case AARCH64_OPND_SVE_UIMM7:
3523 case AARCH64_OPND_SVE_UIMM8:
3524 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3525 case AARCH64_OPND_IMM_ROT1:
3526 case AARCH64_OPND_IMM_ROT2:
3527 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3528 case AARCH64_OPND_SVE_IMM_ROT1:
3529 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 3530 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC		 3531 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3532 break;
3533
165d4950
RS		 3534 case AARCH64_OPND_SVE_I1_HALF_ONE:
3535 case AARCH64_OPND_SVE_I1_HALF_TWO:
3536 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3537 {
3538 single_conv_t c;
3539 c.i = opnd->imm.value;
3540 snprintf (buf, size, "#%.1f", c.f);
3541 break;
3542 }
3543
245d2e3f
RS		 3544 case AARCH64_OPND_SVE_PATTERN:
3545 if (optional_operand_p (opcode, idx)
3546 && opnd->imm.value == get_optional_operand_default_value (opcode))
3547 break;
3548 enum_value = opnd->imm.value;
3549 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3550 if (aarch64_sve_pattern_array[enum_value])
3551 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3552 else
3553 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3554 break;
3555
2442d846
RS		 3556 case AARCH64_OPND_SVE_PATTERN_SCALED:
3557 if (optional_operand_p (opcode, idx)
3558 && !opnd->shifter.operator_present
3559 && opnd->imm.value == get_optional_operand_default_value (opcode))
3560 break;
3561 enum_value = opnd->imm.value;
3562 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3563 if (aarch64_sve_pattern_array[opnd->imm.value])
3564 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3565 else
3566 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3567 if (opnd->shifter.operator_present)
3568 {
3569 size_t len = strlen (buf);
3570 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3571 aarch64_operand_modifiers[opnd->shifter.kind].name,
3572 opnd->shifter.amount);
3573 }
3574 break;
3575
245d2e3f
RS		 3576 case AARCH64_OPND_SVE_PRFOP:
3577 enum_value = opnd->imm.value;
3578 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3579 if (aarch64_sve_prfop_array[enum_value])
3580 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3581 else
3582 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3583 break;
3584
fb098a1e
YZ		 3585 case AARCH64_OPND_IMM_MOV:
3586 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3587 {
3588 case 4: /* e.g. MOV Wd, #<imm32>. */
3589 {
3590 int imm32 = opnd->imm.value;
3591 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3592 }
3593 break;
3594 case 8: /* e.g. MOV Xd, #<imm64>. */
3595 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3596 opnd->imm.value, opnd->imm.value);
3597 break;
7060c28e
NC		 3598 default:
3599 snprintf (buf, size, "<invalid>");
3600 break;
fb098a1e
YZ		 3601 }
3602 break;
3603
a06ea964
NC		 3604 case AARCH64_OPND_FPIMM0:
3605 snprintf (buf, size, "#0.0");
3606 break;
3607
3608 case AARCH64_OPND_LIMM:
3609 case AARCH64_OPND_AIMM:
3610 case AARCH64_OPND_HALF:
e950b345
RS		 3611 case AARCH64_OPND_SVE_INV_LIMM:
3612 case AARCH64_OPND_SVE_LIMM:
3613 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3614 if (opnd->shifter.amount)
2442d846 3615 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3616 opnd->shifter.amount);
3617 else
3618 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3619 break;
3620
3621 case AARCH64_OPND_SIMD_IMM:
3622 case AARCH64_OPND_SIMD_IMM_SFT:
3623 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3624 || opnd->shifter.kind == AARCH64_MOD_NONE)
3625 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3626 else
2442d846 3627 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3628 aarch64_operand_modifiers[opnd->shifter.kind].name,
3629 opnd->shifter.amount);
3630 break;
3631
e950b345
RS		 3632 case AARCH64_OPND_SVE_AIMM:
3633 case AARCH64_OPND_SVE_ASIMM:
3634 if (opnd->shifter.amount)
3635 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3636 opnd->shifter.amount);
3637 else
3638 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3639 break;
3640
a06ea964
NC		 3641 case AARCH64_OPND_FPIMM:
3642 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3643 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3644 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3645 {
cf86120b
MW		 3646 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3647 {
3648 half_conv_t c;
3649 c.i = expand_fp_imm (2, opnd->imm.value);
3650 snprintf (buf, size, "#%.18e", c.f);
3651 }
3652 break;
a06ea964
NC		 3653 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3654 {
3655 single_conv_t c;
cf86120b 3656 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3657 snprintf (buf, size, "#%.18e", c.f);
3658 }
3659 break;
3660 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3661 {
3662 double_conv_t c;
cf86120b 3663 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3664 snprintf (buf, size, "#%.18e", c.d);
3665 }
3666 break;
7060c28e
NC		 3667 default:
3668 snprintf (buf, size, "<invalid>");
3669 break;
a06ea964
NC		 3670 }
3671 break;
3672
3673 case AARCH64_OPND_CCMP_IMM:
3674 case AARCH64_OPND_NZCV:
3675 case AARCH64_OPND_EXCEPTION:
3676 case AARCH64_OPND_UIMM4:
193614f2 3677 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3678 case AARCH64_OPND_UIMM7:
193614f2 3679 case AARCH64_OPND_UIMM10:
63b4cc53 3680 if (optional_operand_p (opcode, idx)
a06ea964
NC		 3681 && (opnd->imm.value ==
3682 (int64_t) get_optional_operand_default_value (opcode)))
3683 /* Omit the operand, e.g. DCPS1. */
3684 break;
3685 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3686 break;
3687
3688 case AARCH64_OPND_COND:
68a64283 3689 case AARCH64_OPND_COND1:
a06ea964 3690 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3691 num_conds = ARRAY_SIZE (opnd->cond->names);
3692 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3693 {
3694 size_t len = strlen (buf);
3695 if (i == 1)
3696 snprintf (buf + len, size - len, " // %s = %s",
3697 opnd->cond->names[0], opnd->cond->names[i]);
3698 else
3699 snprintf (buf + len, size - len, ", %s",
3700 opnd->cond->names[i]);
3701 }
a06ea964
NC		 3702 break;
3703
3704 case AARCH64_OPND_ADDR_ADRP:
3705 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3706 + opnd->imm.value;
3707 if (pcrel_p)
3708 *pcrel_p = 1;
3709 if (address)
3710 *address = addr;
3711 /* This is not necessary during the disassembling, as print_address_func
3712 in the disassemble_info will take care of the printing. But some
3713 other callers may be still interested in getting the string in *STR,
3714 so here we do snprintf regardless. */
3715 snprintf (buf, size, "#0x%" PRIx64, addr);
3716 break;
3717
3718 case AARCH64_OPND_ADDR_PCREL14:
3719 case AARCH64_OPND_ADDR_PCREL19:
3720 case AARCH64_OPND_ADDR_PCREL21:
3721 case AARCH64_OPND_ADDR_PCREL26:
3722 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3723 if (pcrel_p)
3724 *pcrel_p = 1;
3725 if (address)
3726 *address = addr;
3727 /* This is not necessary during the disassembling, as print_address_func
3728 in the disassemble_info will take care of the printing. But some
3729 other callers may be still interested in getting the string in *STR,
3730 so here we do snprintf regardless. */
3731 snprintf (buf, size, "#0x%" PRIx64, addr);
3732 break;
3733
3734 case AARCH64_OPND_ADDR_SIMPLE:
3735 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3736 case AARCH64_OPND_SIMD_ADDR_POST:
3737 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3738 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3739 {
3740 if (opnd->addr.offset.is_reg)
3741 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3742 else
3743 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3744 }
3745 else
3746 snprintf (buf, size, "[%s]", name);
3747 break;
3748
3749 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3750 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3751 case AARCH64_OPND_SVE_ADDR_RR:
3752 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3753 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3754 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
01a4d082 3755 case AARCH64_OPND_SVE_ADDR_RR_LSL4:
4df068de
RS		 3756 case AARCH64_OPND_SVE_ADDR_RX:
3757 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3758 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3759 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3760 print_register_offset_address
3761 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3762 get_offset_int_reg_name (opnd));
a06ea964
NC		 3763 break;
3764
c469c864
MM		 3765 case AARCH64_OPND_SVE_ADDR_ZX:
3766 print_register_offset_address
3767 (buf, size, opnd,
3768 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3769 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
3770 break;
3771
4df068de
RS		 3772 case AARCH64_OPND_SVE_ADDR_RZ:
3773 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3774 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3775 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3776 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3777 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3778 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3779 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3780 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3781 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3782 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3783 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3784 print_register_offset_address
3785 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3786 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3787 break;
3788
a06ea964
NC		 3789 case AARCH64_OPND_ADDR_SIMM7:
3790 case AARCH64_OPND_ADDR_SIMM9:
3791 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3792 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3793 case AARCH64_OPND_ADDR_SIMM11:
3794 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3795 case AARCH64_OPND_ADDR_OFFSET:
01a4d082 3796 case AARCH64_OPND_SME_ADDR_RI_U4xVL:
582e12bf 3797 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
8382113f 3798 case AARCH64_OPND_SVE_ADDR_RI_S4x32:
98907a70
RS		 3799 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3800 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3801 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3802 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3803 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3804 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3805 case AARCH64_OPND_SVE_ADDR_RI_U6:
3806 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3807 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3808 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3809 print_immediate_offset_address
3810 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3811 break;
3812
4df068de
RS		 3813 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3814 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3815 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3816 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3817 print_immediate_offset_address
3818 (buf, size, opnd,
3819 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3820 break;
3821
3822 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3823 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3824 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3825 print_register_offset_address
3826 (buf, size, opnd,
3827 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3828 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3829 break;
3830
a06ea964
NC		 3831 case AARCH64_OPND_ADDR_UIMM12:
3832 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3833 if (opnd->addr.offset.imm)
ad43e107 3834 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3835 else
3836 snprintf (buf, size, "[%s]", name);
3837 break;
3838
3839 case AARCH64_OPND_SYSREG:
3840 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1 3841 {
38cf07a6
AC		 3842 const aarch64_sys_reg *sr = aarch64_sys_regs + i;
3843
78933a4a 3844 bool exact_match
38cf07a6
AC		 3845 = (!(sr->flags & (F_REG_READ | F_REG_WRITE))
3846 || (sr->flags & opnd->sysreg.flags) == opnd->sysreg.flags)
3847 && AARCH64_CPU_HAS_FEATURE (features, sr->features);
f9830ec1
TC		 3848
3849 /* Try and find an exact match, But if that fails, return the first
3850 partial match that was found. */
3851 if (aarch64_sys_regs[i].value == opnd->sysreg.value
f7cb161e 3852 && ! aarch64_sys_reg_deprecated_p (aarch64_sys_regs[i].flags)
f9830ec1
TC		 3853 && (name == NULL || exact_match))
3854 {
3855 name = aarch64_sys_regs[i].name;
3856 if (exact_match)
3857 {
3858 if (notes)
3859 *notes = NULL;
3860 break;
3861 }
3862
3863 /* If we didn't match exactly, that means the presense of a flag
3864 indicates what we didn't want for this instruction. e.g. If
3865 F_REG_READ is there, that means we were looking for a write
3866 register. See aarch64_ext_sysreg. */
3867 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3868 *notes = _("reading from a write-only register");
f9830ec1 3869 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3870 *notes = _("writing to a read-only register");
f9830ec1
TC		 3871 }
3872 }
3873
3874 if (name)
3875 snprintf (buf, size, "%s", name);
a06ea964
NC		 3876 else
3877 {
3878 /* Implementation defined system register. */
561a72d4 3879 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3880 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3881 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3882 value & 0x7);
3883 }
3884 break;
3885
3886 case AARCH64_OPND_PSTATEFIELD:
3887 for (i = 0; aarch64_pstatefields[i].name; ++i)
3dd032c5
PW		 3888 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3889 {
3890 /* PSTATEFIELD name is encoded partially in CRm[3:1] for SVCRSM,
3891 SVCRZA and SVCRSMZA. */
3892 uint32_t flags = aarch64_pstatefields[i].flags;
3893 if (flags & F_REG_IN_CRM
3894 && (PSTATE_DECODE_CRM (opnd->sysreg.flags)
3895 != PSTATE_DECODE_CRM (flags)))
3896 continue;
3897 break;
3898 }
a06ea964
NC		 3899 assert (aarch64_pstatefields[i].name);
3900 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3901 break;
3902
3903 case AARCH64_OPND_SYSREG_AT:
3904 case AARCH64_OPND_SYSREG_DC:
3905 case AARCH64_OPND_SYSREG_IC:
3906 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3907 case AARCH64_OPND_SYSREG_SR:
875880c6 3908 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3909 break;
3910
3911 case AARCH64_OPND_BARRIER:
fd195909 3912 case AARCH64_OPND_BARRIER_DSB_NXS:
a06ea964
NC		 3913 snprintf (buf, size, "%s", opnd->barrier->name);
3914 break;
3915
3916 case AARCH64_OPND_BARRIER_ISB:
3917 /* Operand can be omitted, e.g. in DCPS1. */
3918 if (! optional_operand_p (opcode, idx)
3919 || (opnd->barrier->value
3920 != get_optional_operand_default_value (opcode)))
3921 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3922 break;
3923
3924 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3925 if (opnd->prfop->name != NULL)
3926 snprintf (buf, size, "%s", opnd->prfop->name);
3927 else
3928 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3929 break;
3930
1e6f4800 3931 case AARCH64_OPND_BARRIER_PSB:
c2e5c986
SD		 3932 snprintf (buf, size, "csync");
3933 break;
3934
ff605452
SD		 3935 case AARCH64_OPND_BTI_TARGET:
3936 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3937 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3938 break;
3939
a06ea964 3940 default:
7060c28e
NC		 3941 snprintf (buf, size, "<invalid>");
3942 break;
a06ea964
NC		 3943 }
3944}
3945\f
3946#define CPENC(op0,op1,crn,crm,op2) \
3947 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3948 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3949#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3950 /* for 3.9.10 System Instructions */
3951#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3952
3953#define C0 0
3954#define C1 1
3955#define C2 2
3956#define C3 3
3957#define C4 4
3958#define C5 5
3959#define C6 6
3960#define C7 7
3961#define C8 8
3962#define C9 9
3963#define C10 10
3964#define C11 11
3965#define C12 12
3966#define C13 13
3967#define C14 14
3968#define C15 15
3969
14962256
AC		 3970#define SYSREG(name, encoding, flags, features) \
3971 { name, encoding, flags, features }
3972
3973#define SR_CORE(n,e,f) SYSREG (n,e,f,0)
3974
3975#define SR_FEAT(n,e,f,feat) \
3976 SYSREG ((n), (e), (f) | F_ARCHEXT, AARCH64_FEATURE_##feat)
3977
38cf07a6
AC		 3978#define SR_FEAT2(n,e,f,fe1,fe2) \
3979 SYSREG ((n), (e), (f) | F_ARCHEXT, \
3980 AARCH64_FEATURE_##fe1 | AARCH64_FEATURE_##fe2)
3981
3982#define SR_RNG(n,e,f) SR_FEAT2(n,e,f,RNG,V8_5)
3983#define SR_V8_1_A(n,e,f) SR_FEAT2(n,e,f,V8_A,V8_1)
3984#define SR_V8_4_A(n,e,f) SR_FEAT2(n,e,f,V8_A,V8_4)
14962256 3985
38cf07a6
AC		 3986#define SR_V8_A(n,e,f) SR_FEAT (n,e,f,V8_A)
3987#define SR_V8_R(n,e,f) SR_FEAT (n,e,f,V8_R)
14962256
AC		 3988#define SR_V8_1(n,e,f) SR_FEAT (n,e,f,V8_1)
3989#define SR_V8_2(n,e,f) SR_FEAT (n,e,f,V8_2)
3990#define SR_V8_3(n,e,f) SR_FEAT (n,e,f,V8_3)
3991#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
3992#define SR_V8_4(n,e,f) SR_FEAT (n,e,f,V8_4)
3993#define SR_PAN(n,e,f) SR_FEAT (n,e,f,PAN)
3994#define SR_RAS(n,e,f) SR_FEAT (n,e,f,RAS)
3dd032c5 3995#define SR_SME(n,e,f) SR_FEAT (n,e,f,SME)
14962256
AC		 3996#define SR_SSBS(n,e,f) SR_FEAT (n,e,f,SSBS)
3997#define SR_SVE(n,e,f) SR_FEAT (n,e,f,SVE)
3998#define SR_ID_PFR2(n,e,f) SR_FEAT (n,e,f,ID_PFR2)
3999#define SR_PROFILE(n,e,f) SR_FEAT (n,e,f,PROFILE)
4000#define SR_MEMTAG(n,e,f) SR_FEAT (n,e,f,MEMTAG)
4001#define SR_SCXTNUM(n,e,f) SR_FEAT (n,e,f,SCXTNUM)
4002
38cf07a6
AC		 4003#define SR_EXPAND_ELx(f,x) \
4004 f (x, 1), \
4005 f (x, 2), \
4006 f (x, 3), \
4007 f (x, 4), \
4008 f (x, 5), \
4009 f (x, 6), \
4010 f (x, 7), \
4011 f (x, 8), \
4012 f (x, 9), \
4013 f (x, 10), \
4014 f (x, 11), \
4015 f (x, 12), \
4016 f (x, 13), \
4017 f (x, 14), \
4018 f (x, 15),
4019
4020#define SR_EXPAND_EL12(f) \
4021 SR_EXPAND_ELx (f,1) \
4022 SR_EXPAND_ELx (f,2)
4023
f9830ec1 4024/* TODO there is one more issues need to be resolved
14962256
AC		 4025 1. handle cpu-implementation-defined system registers.
4026
4027 Note that the F_REG_{READ,WRITE} flags mean read-only and write-only
4028 respectively. If neither of these are set then the register is read-write. */
49eec193
YZ		 4029const aarch64_sys_reg aarch64_sys_regs [] =
4030{
14962256
AC		 4031 SR_CORE ("spsr_el1", CPEN_ (0,C0,0), 0), /* = spsr_svc. */
4032 SR_V8_1 ("spsr_el12", CPEN_ (5,C0,0), 0),
4033 SR_CORE ("elr_el1", CPEN_ (0,C0,1), 0),
4034 SR_V8_1 ("elr_el12", CPEN_ (5,C0,1), 0),
4035 SR_CORE ("sp_el0", CPEN_ (0,C1,0), 0),
4036 SR_CORE ("spsel", CPEN_ (0,C2,0), 0),
4037 SR_CORE ("daif", CPEN_ (3,C2,1), 0),
4038 SR_CORE ("currentel", CPEN_ (0,C2,2), F_REG_READ),
4039 SR_PAN ("pan", CPEN_ (0,C2,3), 0),
4040 SR_V8_2 ("uao", CPEN_ (0,C2,4), 0),
4041 SR_CORE ("nzcv", CPEN_ (3,C2,0), 0),
4042 SR_SSBS ("ssbs", CPEN_ (3,C2,6), 0),
4043 SR_CORE ("fpcr", CPEN_ (3,C4,0), 0),
4044 SR_CORE ("fpsr", CPEN_ (3,C4,1), 0),
4045 SR_CORE ("dspsr_el0", CPEN_ (3,C5,0), 0),
4046 SR_CORE ("dlr_el0", CPEN_ (3,C5,1), 0),
4047 SR_CORE ("spsr_el2", CPEN_ (4,C0,0), 0), /* = spsr_hyp. */
4048 SR_CORE ("elr_el2", CPEN_ (4,C0,1), 0),
4049 SR_CORE ("sp_el1", CPEN_ (4,C1,0), 0),
4050 SR_CORE ("spsr_irq", CPEN_ (4,C3,0), 0),
4051 SR_CORE ("spsr_abt", CPEN_ (4,C3,1), 0),
4052 SR_CORE ("spsr_und", CPEN_ (4,C3,2), 0),
4053 SR_CORE ("spsr_fiq", CPEN_ (4,C3,3), 0),
4054 SR_CORE ("spsr_el3", CPEN_ (6,C0,0), 0),
4055 SR_CORE ("elr_el3", CPEN_ (6,C0,1), 0),
4056 SR_CORE ("sp_el2", CPEN_ (6,C1,0), 0),
4057 SR_CORE ("spsr_svc", CPEN_ (0,C0,0), F_DEPRECATED), /* = spsr_el1. */
4058 SR_CORE ("spsr_hyp", CPEN_ (4,C0,0), F_DEPRECATED), /* = spsr_el2. */
4059 SR_CORE ("midr_el1", CPENC (3,0,C0,C0,0), F_REG_READ),
4060 SR_CORE ("ctr_el0", CPENC (3,3,C0,C0,1), F_REG_READ),
4061 SR_CORE ("mpidr_el1", CPENC (3,0,C0,C0,5), F_REG_READ),
4062 SR_CORE ("revidr_el1", CPENC (3,0,C0,C0,6), F_REG_READ),
4063 SR_CORE ("aidr_el1", CPENC (3,1,C0,C0,7), F_REG_READ),
4064 SR_CORE ("dczid_el0", CPENC (3,3,C0,C0,7), F_REG_READ),
4065 SR_CORE ("id_dfr0_el1", CPENC (3,0,C0,C1,2), F_REG_READ),
4066 SR_CORE ("id_pfr0_el1", CPENC (3,0,C0,C1,0), F_REG_READ),
4067 SR_CORE ("id_pfr1_el1", CPENC (3,0,C0,C1,1), F_REG_READ),
4068 SR_ID_PFR2 ("id_pfr2_el1", CPENC (3,0,C0,C3,4), F_REG_READ),
4069 SR_CORE ("id_afr0_el1", CPENC (3,0,C0,C1,3), F_REG_READ),
4070 SR_CORE ("id_mmfr0_el1", CPENC (3,0,C0,C1,4), F_REG_READ),
4071 SR_CORE ("id_mmfr1_el1", CPENC (3,0,C0,C1,5), F_REG_READ),
4072 SR_CORE ("id_mmfr2_el1", CPENC (3,0,C0,C1,6), F_REG_READ),
4073 SR_CORE ("id_mmfr3_el1", CPENC (3,0,C0,C1,7), F_REG_READ),
4074 SR_CORE ("id_mmfr4_el1", CPENC (3,0,C0,C2,6), F_REG_READ),
4075 SR_CORE ("id_isar0_el1", CPENC (3,0,C0,C2,0), F_REG_READ),
4076 SR_CORE ("id_isar1_el1", CPENC (3,0,C0,C2,1), F_REG_READ),
4077 SR_CORE ("id_isar2_el1", CPENC (3,0,C0,C2,2), F_REG_READ),
4078 SR_CORE ("id_isar3_el1", CPENC (3,0,C0,C2,3), F_REG_READ),
4079 SR_CORE ("id_isar4_el1", CPENC (3,0,C0,C2,4), F_REG_READ),
4080 SR_CORE ("id_isar5_el1", CPENC (3,0,C0,C2,5), F_REG_READ),
4081 SR_CORE ("mvfr0_el1", CPENC (3,0,C0,C3,0), F_REG_READ),
4082 SR_CORE ("mvfr1_el1", CPENC (3,0,C0,C3,1), F_REG_READ),
4083 SR_CORE ("mvfr2_el1", CPENC (3,0,C0,C3,2), F_REG_READ),
4084 SR_CORE ("ccsidr_el1", CPENC (3,1,C0,C0,0), F_REG_READ),
4085 SR_CORE ("id_aa64pfr0_el1", CPENC (3,0,C0,C4,0), F_REG_READ),
4086 SR_CORE ("id_aa64pfr1_el1", CPENC (3,0,C0,C4,1), F_REG_READ),
4087 SR_CORE ("id_aa64dfr0_el1", CPENC (3,0,C0,C5,0), F_REG_READ),
4088 SR_CORE ("id_aa64dfr1_el1", CPENC (3,0,C0,C5,1), F_REG_READ),
4089 SR_CORE ("id_aa64isar0_el1", CPENC (3,0,C0,C6,0), F_REG_READ),
4090 SR_CORE ("id_aa64isar1_el1", CPENC (3,0,C0,C6,1), F_REG_READ),
4091 SR_CORE ("id_aa64mmfr0_el1", CPENC (3,0,C0,C7,0), F_REG_READ),
4092 SR_CORE ("id_aa64mmfr1_el1", CPENC (3,0,C0,C7,1), F_REG_READ),
fb932b57 4093 SR_CORE ("id_aa64mmfr2_el1", CPENC (3,0,C0,C7,2), F_REG_READ),
14962256
AC		 4094 SR_CORE ("id_aa64afr0_el1", CPENC (3,0,C0,C5,4), F_REG_READ),
4095 SR_CORE ("id_aa64afr1_el1", CPENC (3,0,C0,C5,5), F_REG_READ),
4096 SR_SVE ("id_aa64zfr0_el1", CPENC (3,0,C0,C4,4), F_REG_READ),
4097 SR_CORE ("clidr_el1", CPENC (3,1,C0,C0,1), F_REG_READ),
4098 SR_CORE ("csselr_el1", CPENC (3,2,C0,C0,0), 0),
4099 SR_CORE ("vpidr_el2", CPENC (3,4,C0,C0,0), 0),
4100 SR_CORE ("vmpidr_el2", CPENC (3,4,C0,C0,5), 0),
4101 SR_CORE ("sctlr_el1", CPENC (3,0,C1,C0,0), 0),
4102 SR_CORE ("sctlr_el2", CPENC (3,4,C1,C0,0), 0),
4103 SR_CORE ("sctlr_el3", CPENC (3,6,C1,C0,0), 0),
4104 SR_V8_1 ("sctlr_el12", CPENC (3,5,C1,C0,0), 0),
4105 SR_CORE ("actlr_el1", CPENC (3,0,C1,C0,1), 0),
4106 SR_CORE ("actlr_el2", CPENC (3,4,C1,C0,1), 0),
4107 SR_CORE ("actlr_el3", CPENC (3,6,C1,C0,1), 0),
4108 SR_CORE ("cpacr_el1", CPENC (3,0,C1,C0,2), 0),
4109 SR_V8_1 ("cpacr_el12", CPENC (3,5,C1,C0,2), 0),
4110 SR_CORE ("cptr_el2", CPENC (3,4,C1,C1,2), 0),
4111 SR_CORE ("cptr_el3", CPENC (3,6,C1,C1,2), 0),
4112 SR_CORE ("scr_el3", CPENC (3,6,C1,C1,0), 0),
4113 SR_CORE ("hcr_el2", CPENC (3,4,C1,C1,0), 0),
4114 SR_CORE ("mdcr_el2", CPENC (3,4,C1,C1,1), 0),
4115 SR_CORE ("mdcr_el3", CPENC (3,6,C1,C3,1), 0),
4116 SR_CORE ("hstr_el2", CPENC (3,4,C1,C1,3), 0),
4117 SR_CORE ("hacr_el2", CPENC (3,4,C1,C1,7), 0),
4118 SR_SVE ("zcr_el1", CPENC (3,0,C1,C2,0), 0),
4119 SR_SVE ("zcr_el12", CPENC (3,5,C1,C2,0), 0),
4120 SR_SVE ("zcr_el2", CPENC (3,4,C1,C2,0), 0),
4121 SR_SVE ("zcr_el3", CPENC (3,6,C1,C2,0), 0),
4122 SR_SVE ("zidr_el1", CPENC (3,0,C0,C0,7), 0),
4123 SR_CORE ("ttbr0_el1", CPENC (3,0,C2,C0,0), 0),
4124 SR_CORE ("ttbr1_el1", CPENC (3,0,C2,C0,1), 0),
38cf07a6
AC		 4125 SR_V8_A ("ttbr0_el2", CPENC (3,4,C2,C0,0), 0),
4126 SR_V8_1_A ("ttbr1_el2", CPENC (3,4,C2,C0,1), 0),
14962256
AC		 4127 SR_CORE ("ttbr0_el3", CPENC (3,6,C2,C0,0), 0),
4128 SR_V8_1 ("ttbr0_el12", CPENC (3,5,C2,C0,0), 0),
4129 SR_V8_1 ("ttbr1_el12", CPENC (3,5,C2,C0,1), 0),
38cf07a6 4130 SR_V8_A ("vttbr_el2", CPENC (3,4,C2,C1,0), 0),
14962256
AC		 4131 SR_CORE ("tcr_el1", CPENC (3,0,C2,C0,2), 0),
4132 SR_CORE ("tcr_el2", CPENC (3,4,C2,C0,2), 0),
4133 SR_CORE ("tcr_el3", CPENC (3,6,C2,C0,2), 0),
4134 SR_V8_1 ("tcr_el12", CPENC (3,5,C2,C0,2), 0),
4135 SR_CORE ("vtcr_el2", CPENC (3,4,C2,C1,2), 0),
4136 SR_V8_3 ("apiakeylo_el1", CPENC (3,0,C2,C1,0), 0),
4137 SR_V8_3 ("apiakeyhi_el1", CPENC (3,0,C2,C1,1), 0),
4138 SR_V8_3 ("apibkeylo_el1", CPENC (3,0,C2,C1,2), 0),
4139 SR_V8_3 ("apibkeyhi_el1", CPENC (3,0,C2,C1,3), 0),
4140 SR_V8_3 ("apdakeylo_el1", CPENC (3,0,C2,C2,0), 0),
4141 SR_V8_3 ("apdakeyhi_el1", CPENC (3,0,C2,C2,1), 0),
4142 SR_V8_3 ("apdbkeylo_el1", CPENC (3,0,C2,C2,2), 0),
4143 SR_V8_3 ("apdbkeyhi_el1", CPENC (3,0,C2,C2,3), 0),
4144 SR_V8_3 ("apgakeylo_el1", CPENC (3,0,C2,C3,0), 0),
4145 SR_V8_3 ("apgakeyhi_el1", CPENC (3,0,C2,C3,1), 0),
4146 SR_CORE ("afsr0_el1", CPENC (3,0,C5,C1,0), 0),
4147 SR_CORE ("afsr1_el1", CPENC (3,0,C5,C1,1), 0),
4148 SR_CORE ("afsr0_el2", CPENC (3,4,C5,C1,0), 0),
4149 SR_CORE ("afsr1_el2", CPENC (3,4,C5,C1,1), 0),
4150 SR_CORE ("afsr0_el3", CPENC (3,6,C5,C1,0), 0),
4151 SR_V8_1 ("afsr0_el12", CPENC (3,5,C5,C1,0), 0),
4152 SR_CORE ("afsr1_el3", CPENC (3,6,C5,C1,1), 0),
4153 SR_V8_1 ("afsr1_el12", CPENC (3,5,C5,C1,1), 0),
4154 SR_CORE ("esr_el1", CPENC (3,0,C5,C2,0), 0),
4155 SR_CORE ("esr_el2", CPENC (3,4,C5,C2,0), 0),
4156 SR_CORE ("esr_el3", CPENC (3,6,C5,C2,0), 0),
4157 SR_V8_1 ("esr_el12", CPENC (3,5,C5,C2,0), 0),
4158 SR_RAS ("vsesr_el2", CPENC (3,4,C5,C2,3), 0),
4159 SR_CORE ("fpexc32_el2", CPENC (3,4,C5,C3,0), 0),
4160 SR_RAS ("erridr_el1", CPENC (3,0,C5,C3,0), F_REG_READ),
4161 SR_RAS ("errselr_el1", CPENC (3,0,C5,C3,1), 0),
4162 SR_RAS ("erxfr_el1", CPENC (3,0,C5,C4,0), F_REG_READ),
4163 SR_RAS ("erxctlr_el1", CPENC (3,0,C5,C4,1), 0),
4164 SR_RAS ("erxstatus_el1", CPENC (3,0,C5,C4,2), 0),
4165 SR_RAS ("erxaddr_el1", CPENC (3,0,C5,C4,3), 0),
4166 SR_RAS ("erxmisc0_el1", CPENC (3,0,C5,C5,0), 0),
4167 SR_RAS ("erxmisc1_el1", CPENC (3,0,C5,C5,1), 0),
55cc0128
PW		 4168 SR_RAS ("erxmisc2_el1", CPENC (3,0,C5,C5,2), 0),
4169 SR_RAS ("erxmisc3_el1", CPENC (3,0,C5,C5,3), 0),
4170 SR_RAS ("erxpfgcdn_el1", CPENC (3,0,C5,C4,6), 0),
4171 SR_RAS ("erxpfgctl_el1", CPENC (3,0,C5,C4,5), 0),
4172 SR_RAS ("erxpfgf_el1", CPENC (3,0,C5,C4,4), F_REG_READ),
14962256
AC		 4173 SR_CORE ("far_el1", CPENC (3,0,C6,C0,0), 0),
4174 SR_CORE ("far_el2", CPENC (3,4,C6,C0,0), 0),
4175 SR_CORE ("far_el3", CPENC (3,6,C6,C0,0), 0),
4176 SR_V8_1 ("far_el12", CPENC (3,5,C6,C0,0), 0),
4177 SR_CORE ("hpfar_el2", CPENC (3,4,C6,C0,4), 0),
4178 SR_CORE ("par_el1", CPENC (3,0,C7,C4,0), 0),
4179 SR_CORE ("mair_el1", CPENC (3,0,C10,C2,0), 0),
4180 SR_CORE ("mair_el2", CPENC (3,4,C10,C2,0), 0),
4181 SR_CORE ("mair_el3", CPENC (3,6,C10,C2,0), 0),
4182 SR_V8_1 ("mair_el12", CPENC (3,5,C10,C2,0), 0),
4183 SR_CORE ("amair_el1", CPENC (3,0,C10,C3,0), 0),
4184 SR_CORE ("amair_el2", CPENC (3,4,C10,C3,0), 0),
4185 SR_CORE ("amair_el3", CPENC (3,6,C10,C3,0), 0),
4186 SR_V8_1 ("amair_el12", CPENC (3,5,C10,C3,0), 0),
4187 SR_CORE ("vbar_el1", CPENC (3,0,C12,C0,0), 0),
4188 SR_CORE ("vbar_el2", CPENC (3,4,C12,C0,0), 0),
4189 SR_CORE ("vbar_el3", CPENC (3,6,C12,C0,0), 0),
4190 SR_V8_1 ("vbar_el12", CPENC (3,5,C12,C0,0), 0),
4191 SR_CORE ("rvbar_el1", CPENC (3,0,C12,C0,1), F_REG_READ),
4192 SR_CORE ("rvbar_el2", CPENC (3,4,C12,C0,1), F_REG_READ),
4193 SR_CORE ("rvbar_el3", CPENC (3,6,C12,C0,1), F_REG_READ),
4194 SR_CORE ("rmr_el1", CPENC (3,0,C12,C0,2), 0),
4195 SR_CORE ("rmr_el2", CPENC (3,4,C12,C0,2), 0),
4196 SR_CORE ("rmr_el3", CPENC (3,6,C12,C0,2), 0),
4197 SR_CORE ("isr_el1", CPENC (3,0,C12,C1,0), F_REG_READ),
4198 SR_RAS ("disr_el1", CPENC (3,0,C12,C1,1), 0),
4199 SR_RAS ("vdisr_el2", CPENC (3,4,C12,C1,1), 0),
4200 SR_CORE ("contextidr_el1", CPENC (3,0,C13,C0,1), 0),
4201 SR_V8_1 ("contextidr_el2", CPENC (3,4,C13,C0,1), 0),
4202 SR_V8_1 ("contextidr_el12", CPENC (3,5,C13,C0,1), 0),
4203 SR_RNG ("rndr", CPENC (3,3,C2,C4,0), F_REG_READ),
4204 SR_RNG ("rndrrs", CPENC (3,3,C2,C4,1), F_REG_READ),
4205 SR_MEMTAG ("tco", CPENC (3,3,C4,C2,7), 0),
4206 SR_MEMTAG ("tfsre0_el1", CPENC (3,0,C5,C6,1), 0),
4207 SR_MEMTAG ("tfsr_el1", CPENC (3,0,C5,C6,0), 0),
4208 SR_MEMTAG ("tfsr_el2", CPENC (3,4,C5,C6,0), 0),
4209 SR_MEMTAG ("tfsr_el3", CPENC (3,6,C5,C6,0), 0),
4210 SR_MEMTAG ("tfsr_el12", CPENC (3,5,C5,C6,0), 0),
4211 SR_MEMTAG ("rgsr_el1", CPENC (3,0,C1,C0,5), 0),
4212 SR_MEMTAG ("gcr_el1", CPENC (3,0,C1,C0,6), 0),
4213 SR_MEMTAG ("gmid_el1", CPENC (3,1,C0,C0,4), F_REG_READ),
4214 SR_CORE ("tpidr_el0", CPENC (3,3,C13,C0,2), 0),
4215 SR_CORE ("tpidrro_el0", CPENC (3,3,C13,C0,3), 0),
4216 SR_CORE ("tpidr_el1", CPENC (3,0,C13,C0,4), 0),
4217 SR_CORE ("tpidr_el2", CPENC (3,4,C13,C0,2), 0),
4218 SR_CORE ("tpidr_el3", CPENC (3,6,C13,C0,2), 0),
4219 SR_SCXTNUM ("scxtnum_el0", CPENC (3,3,C13,C0,7), 0),
4220 SR_SCXTNUM ("scxtnum_el1", CPENC (3,0,C13,C0,7), 0),
4221 SR_SCXTNUM ("scxtnum_el2", CPENC (3,4,C13,C0,7), 0),
4222 SR_SCXTNUM ("scxtnum_el12", CPENC (3,5,C13,C0,7), 0),
4223 SR_SCXTNUM ("scxtnum_el3", CPENC (3,6,C13,C0,7), 0),
4224 SR_CORE ("teecr32_el1", CPENC (2,2,C0, C0,0), 0), /* See section 3.9.7.1. */
4225 SR_CORE ("cntfrq_el0", CPENC (3,3,C14,C0,0), 0),
4226 SR_CORE ("cntpct_el0", CPENC (3,3,C14,C0,1), F_REG_READ),
4227 SR_CORE ("cntvct_el0", CPENC (3,3,C14,C0,2), F_REG_READ),
4228 SR_CORE ("cntvoff_el2", CPENC (3,4,C14,C0,3), 0),
4229 SR_CORE ("cntkctl_el1", CPENC (3,0,C14,C1,0), 0),
4230 SR_V8_1 ("cntkctl_el12", CPENC (3,5,C14,C1,0), 0),
4231 SR_CORE ("cnthctl_el2", CPENC (3,4,C14,C1,0), 0),
4232 SR_CORE ("cntp_tval_el0", CPENC (3,3,C14,C2,0), 0),
4233 SR_V8_1 ("cntp_tval_el02", CPENC (3,5,C14,C2,0), 0),
4234 SR_CORE ("cntp_ctl_el0", CPENC (3,3,C14,C2,1), 0),
4235 SR_V8_1 ("cntp_ctl_el02", CPENC (3,5,C14,C2,1), 0),
4236 SR_CORE ("cntp_cval_el0", CPENC (3,3,C14,C2,2), 0),
4237 SR_V8_1 ("cntp_cval_el02", CPENC (3,5,C14,C2,2), 0),
4238 SR_CORE ("cntv_tval_el0", CPENC (3,3,C14,C3,0), 0),
4239 SR_V8_1 ("cntv_tval_el02", CPENC (3,5,C14,C3,0), 0),
4240 SR_CORE ("cntv_ctl_el0", CPENC (3,3,C14,C3,1), 0),
4241 SR_V8_1 ("cntv_ctl_el02", CPENC (3,5,C14,C3,1), 0),
4242 SR_CORE ("cntv_cval_el0", CPENC (3,3,C14,C3,2), 0),
4243 SR_V8_1 ("cntv_cval_el02", CPENC (3,5,C14,C3,2), 0),
4244 SR_CORE ("cnthp_tval_el2", CPENC (3,4,C14,C2,0), 0),
4245 SR_CORE ("cnthp_ctl_el2", CPENC (3,4,C14,C2,1), 0),
4246 SR_CORE ("cnthp_cval_el2", CPENC (3,4,C14,C2,2), 0),
4247 SR_CORE ("cntps_tval_el1", CPENC (3,7,C14,C2,0), 0),
4248 SR_CORE ("cntps_ctl_el1", CPENC (3,7,C14,C2,1), 0),
4249 SR_CORE ("cntps_cval_el1", CPENC (3,7,C14,C2,2), 0),
4250 SR_V8_1 ("cnthv_tval_el2", CPENC (3,4,C14,C3,0), 0),
4251 SR_V8_1 ("cnthv_ctl_el2", CPENC (3,4,C14,C3,1), 0),
4252 SR_V8_1 ("cnthv_cval_el2", CPENC (3,4,C14,C3,2), 0),
4253 SR_CORE ("dacr32_el2", CPENC (3,4,C3,C0,0), 0),
4254 SR_CORE ("ifsr32_el2", CPENC (3,4,C5,C0,1), 0),
4255 SR_CORE ("teehbr32_el1", CPENC (2,2,C1,C0,0), 0),
4256 SR_CORE ("sder32_el3", CPENC (3,6,C1,C1,1), 0),
4257 SR_CORE ("mdscr_el1", CPENC (2,0,C0,C2,2), 0),
4258 SR_CORE ("mdccsr_el0", CPENC (2,3,C0,C1,0), F_REG_READ),
4259 SR_CORE ("mdccint_el1", CPENC (2,0,C0,C2,0), 0),
4260 SR_CORE ("dbgdtr_el0", CPENC (2,3,C0,C4,0), 0),
4261 SR_CORE ("dbgdtrrx_el0", CPENC (2,3,C0,C5,0), F_REG_READ),
4262 SR_CORE ("dbgdtrtx_el0", CPENC (2,3,C0,C5,0), F_REG_WRITE),
4263 SR_CORE ("osdtrrx_el1", CPENC (2,0,C0,C0,2), 0),
4264 SR_CORE ("osdtrtx_el1", CPENC (2,0,C0,C3,2), 0),
4265 SR_CORE ("oseccr_el1", CPENC (2,0,C0,C6,2), 0),
4266 SR_CORE ("dbgvcr32_el2", CPENC (2,4,C0,C7,0), 0),
4267 SR_CORE ("dbgbvr0_el1", CPENC (2,0,C0,C0,4), 0),
4268 SR_CORE ("dbgbvr1_el1", CPENC (2,0,C0,C1,4), 0),
4269 SR_CORE ("dbgbvr2_el1", CPENC (2,0,C0,C2,4), 0),
4270 SR_CORE ("dbgbvr3_el1", CPENC (2,0,C0,C3,4), 0),
4271 SR_CORE ("dbgbvr4_el1", CPENC (2,0,C0,C4,4), 0),
4272 SR_CORE ("dbgbvr5_el1", CPENC (2,0,C0,C5,4), 0),
4273 SR_CORE ("dbgbvr6_el1", CPENC (2,0,C0,C6,4), 0),
4274 SR_CORE ("dbgbvr7_el1", CPENC (2,0,C0,C7,4), 0),
4275 SR_CORE ("dbgbvr8_el1", CPENC (2,0,C0,C8,4), 0),
4276 SR_CORE ("dbgbvr9_el1", CPENC (2,0,C0,C9,4), 0),
4277 SR_CORE ("dbgbvr10_el1", CPENC (2,0,C0,C10,4), 0),
4278 SR_CORE ("dbgbvr11_el1", CPENC (2,0,C0,C11,4), 0),
4279 SR_CORE ("dbgbvr12_el1", CPENC (2,0,C0,C12,4), 0),
4280 SR_CORE ("dbgbvr13_el1", CPENC (2,0,C0,C13,4), 0),
4281 SR_CORE ("dbgbvr14_el1", CPENC (2,0,C0,C14,4), 0),
4282 SR_CORE ("dbgbvr15_el1", CPENC (2,0,C0,C15,4), 0),
4283 SR_CORE ("dbgbcr0_el1", CPENC (2,0,C0,C0,5), 0),
4284 SR_CORE ("dbgbcr1_el1", CPENC (2,0,C0,C1,5), 0),
4285 SR_CORE ("dbgbcr2_el1", CPENC (2,0,C0,C2,5), 0),
4286 SR_CORE ("dbgbcr3_el1", CPENC (2,0,C0,C3,5), 0),
4287 SR_CORE ("dbgbcr4_el1", CPENC (2,0,C0,C4,5), 0),
4288 SR_CORE ("dbgbcr5_el1", CPENC (2,0,C0,C5,5), 0),
4289 SR_CORE ("dbgbcr6_el1", CPENC (2,0,C0,C6,5), 0),
4290 SR_CORE ("dbgbcr7_el1", CPENC (2,0,C0,C7,5), 0),
4291 SR_CORE ("dbgbcr8_el1", CPENC (2,0,C0,C8,5), 0),
4292 SR_CORE ("dbgbcr9_el1", CPENC (2,0,C0,C9,5), 0),
4293 SR_CORE ("dbgbcr10_el1", CPENC (2,0,C0,C10,5), 0),
4294 SR_CORE ("dbgbcr11_el1", CPENC (2,0,C0,C11,5), 0),
4295 SR_CORE ("dbgbcr12_el1", CPENC (2,0,C0,C12,5), 0),
4296 SR_CORE ("dbgbcr13_el1", CPENC (2,0,C0,C13,5), 0),
4297 SR_CORE ("dbgbcr14_el1", CPENC (2,0,C0,C14,5), 0),
4298 SR_CORE ("dbgbcr15_el1", CPENC (2,0,C0,C15,5), 0),
4299 SR_CORE ("dbgwvr0_el1", CPENC (2,0,C0,C0,6), 0),
4300 SR_CORE ("dbgwvr1_el1", CPENC (2,0,C0,C1,6), 0),
4301 SR_CORE ("dbgwvr2_el1", CPENC (2,0,C0,C2,6), 0),
4302 SR_CORE ("dbgwvr3_el1", CPENC (2,0,C0,C3,6), 0),
4303 SR_CORE ("dbgwvr4_el1", CPENC (2,0,C0,C4,6), 0),
4304 SR_CORE ("dbgwvr5_el1", CPENC (2,0,C0,C5,6), 0),
4305 SR_CORE ("dbgwvr6_el1", CPENC (2,0,C0,C6,6), 0),
4306 SR_CORE ("dbgwvr7_el1", CPENC (2,0,C0,C7,6), 0),
4307 SR_CORE ("dbgwvr8_el1", CPENC (2,0,C0,C8,6), 0),
4308 SR_CORE ("dbgwvr9_el1", CPENC (2,0,C0,C9,6), 0),
4309 SR_CORE ("dbgwvr10_el1", CPENC (2,0,C0,C10,6), 0),
4310 SR_CORE ("dbgwvr11_el1", CPENC (2,0,C0,C11,6), 0),
4311 SR_CORE ("dbgwvr12_el1", CPENC (2,0,C0,C12,6), 0),
4312 SR_CORE ("dbgwvr13_el1", CPENC (2,0,C0,C13,6), 0),
4313 SR_CORE ("dbgwvr14_el1", CPENC (2,0,C0,C14,6), 0),
4314 SR_CORE ("dbgwvr15_el1", CPENC (2,0,C0,C15,6), 0),
4315 SR_CORE ("dbgwcr0_el1", CPENC (2,0,C0,C0,7), 0),
4316 SR_CORE ("dbgwcr1_el1", CPENC (2,0,C0,C1,7), 0),
4317 SR_CORE ("dbgwcr2_el1", CPENC (2,0,C0,C2,7), 0),
4318 SR_CORE ("dbgwcr3_el1", CPENC (2,0,C0,C3,7), 0),
4319 SR_CORE ("dbgwcr4_el1", CPENC (2,0,C0,C4,7), 0),
4320 SR_CORE ("dbgwcr5_el1", CPENC (2,0,C0,C5,7), 0),
4321 SR_CORE ("dbgwcr6_el1", CPENC (2,0,C0,C6,7), 0),
4322 SR_CORE ("dbgwcr7_el1", CPENC (2,0,C0,C7,7), 0),
4323 SR_CORE ("dbgwcr8_el1", CPENC (2,0,C0,C8,7), 0),
4324 SR_CORE ("dbgwcr9_el1", CPENC (2,0,C0,C9,7), 0),
4325 SR_CORE ("dbgwcr10_el1", CPENC (2,0,C0,C10,7), 0),
4326 SR_CORE ("dbgwcr11_el1", CPENC (2,0,C0,C11,7), 0),
4327 SR_CORE ("dbgwcr12_el1", CPENC (2,0,C0,C12,7), 0),
4328 SR_CORE ("dbgwcr13_el1", CPENC (2,0,C0,C13,7), 0),
4329 SR_CORE ("dbgwcr14_el1", CPENC (2,0,C0,C14,7), 0),
4330 SR_CORE ("dbgwcr15_el1", CPENC (2,0,C0,C15,7), 0),
4331 SR_CORE ("mdrar_el1", CPENC (2,0,C1,C0,0), F_REG_READ),
4332 SR_CORE ("oslar_el1", CPENC (2,0,C1,C0,4), F_REG_WRITE),
4333 SR_CORE ("oslsr_el1", CPENC (2,0,C1,C1,4), F_REG_READ),
4334 SR_CORE ("osdlr_el1", CPENC (2,0,C1,C3,4), 0),
4335 SR_CORE ("dbgprcr_el1", CPENC (2,0,C1,C4,4), 0),
4336 SR_CORE ("dbgclaimset_el1", CPENC (2,0,C7,C8,6), 0),
4337 SR_CORE ("dbgclaimclr_el1", CPENC (2,0,C7,C9,6), 0),
4338 SR_CORE ("dbgauthstatus_el1", CPENC (2,0,C7,C14,6), F_REG_READ),
4339 SR_PROFILE ("pmblimitr_el1", CPENC (3,0,C9,C10,0), 0),
4340 SR_PROFILE ("pmbptr_el1", CPENC (3,0,C9,C10,1), 0),
4341 SR_PROFILE ("pmbsr_el1", CPENC (3,0,C9,C10,3), 0),
4342 SR_PROFILE ("pmbidr_el1", CPENC (3,0,C9,C10,7), F_REG_READ),
4343 SR_PROFILE ("pmscr_el1", CPENC (3,0,C9,C9,0), 0),
4344 SR_PROFILE ("pmsicr_el1", CPENC (3,0,C9,C9,2), 0),
4345 SR_PROFILE ("pmsirr_el1", CPENC (3,0,C9,C9,3), 0),
4346 SR_PROFILE ("pmsfcr_el1", CPENC (3,0,C9,C9,4), 0),
4347 SR_PROFILE ("pmsevfr_el1", CPENC (3,0,C9,C9,5), 0),
4348 SR_PROFILE ("pmslatfr_el1", CPENC (3,0,C9,C9,6), 0),
4349 SR_PROFILE ("pmsidr_el1", CPENC (3,0,C9,C9,7), 0),
4350 SR_PROFILE ("pmscr_el2", CPENC (3,4,C9,C9,0), 0),
4351 SR_PROFILE ("pmscr_el12", CPENC (3,5,C9,C9,0), 0),
4352 SR_CORE ("pmcr_el0", CPENC (3,3,C9,C12,0), 0),
4353 SR_CORE ("pmcntenset_el0", CPENC (3,3,C9,C12,1), 0),
4354 SR_CORE ("pmcntenclr_el0", CPENC (3,3,C9,C12,2), 0),
4355 SR_CORE ("pmovsclr_el0", CPENC (3,3,C9,C12,3), 0),
4356 SR_CORE ("pmswinc_el0", CPENC (3,3,C9,C12,4), F_REG_WRITE),
4357 SR_CORE ("pmselr_el0", CPENC (3,3,C9,C12,5), 0),
4358 SR_CORE ("pmceid0_el0", CPENC (3,3,C9,C12,6), F_REG_READ),
4359 SR_CORE ("pmceid1_el0", CPENC (3,3,C9,C12,7), F_REG_READ),
4360 SR_CORE ("pmccntr_el0", CPENC (3,3,C9,C13,0), 0),
4361 SR_CORE ("pmxevtyper_el0", CPENC (3,3,C9,C13,1), 0),
4362 SR_CORE ("pmxevcntr_el0", CPENC (3,3,C9,C13,2), 0),
4363 SR_CORE ("pmuserenr_el0", CPENC (3,3,C9,C14,0), 0),
4364 SR_CORE ("pmintenset_el1", CPENC (3,0,C9,C14,1), 0),
4365 SR_CORE ("pmintenclr_el1", CPENC (3,0,C9,C14,2), 0),
4366 SR_CORE ("pmovsset_el0", CPENC (3,3,C9,C14,3), 0),
4367 SR_CORE ("pmevcntr0_el0", CPENC (3,3,C14,C8,0), 0),
4368 SR_CORE ("pmevcntr1_el0", CPENC (3,3,C14,C8,1), 0),
4369 SR_CORE ("pmevcntr2_el0", CPENC (3,3,C14,C8,2), 0),
4370 SR_CORE ("pmevcntr3_el0", CPENC (3,3,C14,C8,3), 0),
4371 SR_CORE ("pmevcntr4_el0", CPENC (3,3,C14,C8,4), 0),
4372 SR_CORE ("pmevcntr5_el0", CPENC (3,3,C14,C8,5), 0),
4373 SR_CORE ("pmevcntr6_el0", CPENC (3,3,C14,C8,6), 0),
4374 SR_CORE ("pmevcntr7_el0", CPENC (3,3,C14,C8,7), 0),
4375 SR_CORE ("pmevcntr8_el0", CPENC (3,3,C14,C9,0), 0),
4376 SR_CORE ("pmevcntr9_el0", CPENC (3,3,C14,C9,1), 0),
4377 SR_CORE ("pmevcntr10_el0", CPENC (3,3,C14,C9,2), 0),
4378 SR_CORE ("pmevcntr11_el0", CPENC (3,3,C14,C9,3), 0),
4379 SR_CORE ("pmevcntr12_el0", CPENC (3,3,C14,C9,4), 0),
4380 SR_CORE ("pmevcntr13_el0", CPENC (3,3,C14,C9,5), 0),
4381 SR_CORE ("pmevcntr14_el0", CPENC (3,3,C14,C9,6), 0),
4382 SR_CORE ("pmevcntr15_el0", CPENC (3,3,C14,C9,7), 0),
4383 SR_CORE ("pmevcntr16_el0", CPENC (3,3,C14,C10,0), 0),
4384 SR_CORE ("pmevcntr17_el0", CPENC (3,3,C14,C10,1), 0),
4385 SR_CORE ("pmevcntr18_el0", CPENC (3,3,C14,C10,2), 0),
4386 SR_CORE ("pmevcntr19_el0", CPENC (3,3,C14,C10,3), 0),
4387 SR_CORE ("pmevcntr20_el0", CPENC (3,3,C14,C10,4), 0),
4388 SR_CORE ("pmevcntr21_el0", CPENC (3,3,C14,C10,5), 0),
4389 SR_CORE ("pmevcntr22_el0", CPENC (3,3,C14,C10,6), 0),
4390 SR_CORE ("pmevcntr23_el0", CPENC (3,3,C14,C10,7), 0),
4391 SR_CORE ("pmevcntr24_el0", CPENC (3,3,C14,C11,0), 0),
4392 SR_CORE ("pmevcntr25_el0", CPENC (3,3,C14,C11,1), 0),
4393 SR_CORE ("pmevcntr26_el0", CPENC (3,3,C14,C11,2), 0),
4394 SR_CORE ("pmevcntr27_el0", CPENC (3,3,C14,C11,3), 0),
4395 SR_CORE ("pmevcntr28_el0", CPENC (3,3,C14,C11,4), 0),
4396 SR_CORE ("pmevcntr29_el0", CPENC (3,3,C14,C11,5), 0),
4397 SR_CORE ("pmevcntr30_el0", CPENC (3,3,C14,C11,6), 0),
4398 SR_CORE ("pmevtyper0_el0", CPENC (3,3,C14,C12,0), 0),
4399 SR_CORE ("pmevtyper1_el0", CPENC (3,3,C14,C12,1), 0),
4400 SR_CORE ("pmevtyper2_el0", CPENC (3,3,C14,C12,2), 0),
4401 SR_CORE ("pmevtyper3_el0", CPENC (3,3,C14,C12,3), 0),
4402 SR_CORE ("pmevtyper4_el0", CPENC (3,3,C14,C12,4), 0),
4403 SR_CORE ("pmevtyper5_el0", CPENC (3,3,C14,C12,5), 0),
4404 SR_CORE ("pmevtyper6_el0", CPENC (3,3,C14,C12,6), 0),
4405 SR_CORE ("pmevtyper7_el0", CPENC (3,3,C14,C12,7), 0),
4406 SR_CORE ("pmevtyper8_el0", CPENC (3,3,C14,C13,0), 0),
4407 SR_CORE ("pmevtyper9_el0", CPENC (3,3,C14,C13,1), 0),
4408 SR_CORE ("pmevtyper10_el0", CPENC (3,3,C14,C13,2), 0),
4409 SR_CORE ("pmevtyper11_el0", CPENC (3,3,C14,C13,3), 0),
4410 SR_CORE ("pmevtyper12_el0", CPENC (3,3,C14,C13,4), 0),
4411 SR_CORE ("pmevtyper13_el0", CPENC (3,3,C14,C13,5), 0),
4412 SR_CORE ("pmevtyper14_el0", CPENC (3,3,C14,C13,6), 0),
4413 SR_CORE ("pmevtyper15_el0", CPENC (3,3,C14,C13,7), 0),
4414 SR_CORE ("pmevtyper16_el0", CPENC (3,3,C14,C14,0), 0),
4415 SR_CORE ("pmevtyper17_el0", CPENC (3,3,C14,C14,1), 0),
4416 SR_CORE ("pmevtyper18_el0", CPENC (3,3,C14,C14,2), 0),
4417 SR_CORE ("pmevtyper19_el0", CPENC (3,3,C14,C14,3), 0),
4418 SR_CORE ("pmevtyper20_el0", CPENC (3,3,C14,C14,4), 0),
4419 SR_CORE ("pmevtyper21_el0", CPENC (3,3,C14,C14,5), 0),
4420 SR_CORE ("pmevtyper22_el0", CPENC (3,3,C14,C14,6), 0),
4421 SR_CORE ("pmevtyper23_el0", CPENC (3,3,C14,C14,7), 0),
4422 SR_CORE ("pmevtyper24_el0", CPENC (3,3,C14,C15,0), 0),
4423 SR_CORE ("pmevtyper25_el0", CPENC (3,3,C14,C15,1), 0),
4424 SR_CORE ("pmevtyper26_el0", CPENC (3,3,C14,C15,2), 0),
4425 SR_CORE ("pmevtyper27_el0", CPENC (3,3,C14,C15,3), 0),
4426 SR_CORE ("pmevtyper28_el0", CPENC (3,3,C14,C15,4), 0),
4427 SR_CORE ("pmevtyper29_el0", CPENC (3,3,C14,C15,5), 0),
4428 SR_CORE ("pmevtyper30_el0", CPENC (3,3,C14,C15,6), 0),
4429 SR_CORE ("pmccfiltr_el0", CPENC (3,3,C14,C15,7), 0),
4430
4431 SR_V8_4 ("dit", CPEN_ (3,C2,5), 0),
4432 SR_V8_4 ("vstcr_el2", CPENC (3,4,C2,C6,2), 0),
38cf07a6 4433 SR_V8_4_A ("vsttbr_el2", CPENC (3,4,C2,C6,0), 0),
14962256
AC		 4434 SR_V8_4 ("cnthvs_tval_el2", CPENC (3,4,C14,C4,0), 0),
4435 SR_V8_4 ("cnthvs_cval_el2", CPENC (3,4,C14,C4,2), 0),
4436 SR_V8_4 ("cnthvs_ctl_el2", CPENC (3,4,C14,C4,1), 0),
4437 SR_V8_4 ("cnthps_tval_el2", CPENC (3,4,C14,C5,0), 0),
4438 SR_V8_4 ("cnthps_cval_el2", CPENC (3,4,C14,C5,2), 0),
4439 SR_V8_4 ("cnthps_ctl_el2", CPENC (3,4,C14,C5,1), 0),
4440 SR_V8_4 ("sder32_el2", CPENC (3,4,C1,C3,1), 0),
4441 SR_V8_4 ("vncr_el2", CPENC (3,4,C2,C2,0), 0),
4442
2e49fd1e
AC		 4443 SR_CORE ("mpam0_el1", CPENC (3,0,C10,C5,1), 0),
4444 SR_CORE ("mpam1_el1", CPENC (3,0,C10,C5,0), 0),
4445 SR_CORE ("mpam1_el12", CPENC (3,5,C10,C5,0), 0),
4446 SR_CORE ("mpam2_el2", CPENC (3,4,C10,C5,0), 0),
4447 SR_CORE ("mpam3_el3", CPENC (3,6,C10,C5,0), 0),
4448 SR_CORE ("mpamhcr_el2", CPENC (3,4,C10,C4,0), 0),
4449 SR_CORE ("mpamidr_el1", CPENC (3,0,C10,C4,4), F_REG_READ),
4450 SR_CORE ("mpamvpm0_el2", CPENC (3,4,C10,C6,0), 0),
4451 SR_CORE ("mpamvpm1_el2", CPENC (3,4,C10,C6,1), 0),
4452 SR_CORE ("mpamvpm2_el2", CPENC (3,4,C10,C6,2), 0),
4453 SR_CORE ("mpamvpm3_el2", CPENC (3,4,C10,C6,3), 0),
4454 SR_CORE ("mpamvpm4_el2", CPENC (3,4,C10,C6,4), 0),
4455 SR_CORE ("mpamvpm5_el2", CPENC (3,4,C10,C6,5), 0),
4456 SR_CORE ("mpamvpm6_el2", CPENC (3,4,C10,C6,6), 0),
4457 SR_CORE ("mpamvpm7_el2", CPENC (3,4,C10,C6,7), 0),
4458 SR_CORE ("mpamvpmv_el2", CPENC (3,4,C10,C4,1), 0),
4459
38cf07a6
AC		 4460 SR_V8_R ("mpuir_el1", CPENC (3,0,C0,C0,4), F_REG_READ),
4461 SR_V8_R ("mpuir_el2", CPENC (3,4,C0,C0,4), F_REG_READ),
4462 SR_V8_R ("prbar_el1", CPENC (3,0,C6,C8,0), 0),
4463 SR_V8_R ("prbar_el2", CPENC (3,4,C6,C8,0), 0),
4464
4465#define ENC_BARLAR(x,n,lar) \
4466 CPENC (3, (x-1) << 2, C6, 8 | (n >> 1), ((n & 1) << 2) | lar)
4467
4468#define PRBARn_ELx(x,n) SR_V8_R ("prbar" #n "_el" #x, ENC_BARLAR (x,n,0), 0)
4469#define PRLARn_ELx(x,n) SR_V8_R ("prlar" #n "_el" #x, ENC_BARLAR (x,n,1), 0)
4470
4471 SR_EXPAND_EL12 (PRBARn_ELx)
4472 SR_V8_R ("prenr_el1", CPENC (3,0,C6,C1,1), 0),
4473 SR_V8_R ("prenr_el2", CPENC (3,4,C6,C1,1), 0),
4474 SR_V8_R ("prlar_el1", CPENC (3,0,C6,C8,1), 0),
4475 SR_V8_R ("prlar_el2", CPENC (3,4,C6,C8,1), 0),
4476 SR_EXPAND_EL12 (PRLARn_ELx)
4477 SR_V8_R ("prselr_el1", CPENC (3,0,C6,C2,1), 0),
4478 SR_V8_R ("prselr_el2", CPENC (3,4,C6,C2,1), 0),
4479 SR_V8_R ("vsctlr_el2", CPENC (3,4,C2,C0,0), 0),
4480
1ff8e401
PW		 4481 SR_CORE("trbbaser_el1", CPENC (3,0,C9,C11,2), 0),
4482 SR_CORE("trbidr_el1", CPENC (3,0,C9,C11,7), F_REG_READ),
4483 SR_CORE("trblimitr_el1", CPENC (3,0,C9,C11,0), 0),
4484 SR_CORE("trbmar_el1", CPENC (3,0,C9,C11,4), 0),
4485 SR_CORE("trbptr_el1", CPENC (3,0,C9,C11,1), 0),
4486 SR_CORE("trbsr_el1", CPENC (3,0,C9,C11,3), 0),
4487 SR_CORE("trbtrg_el1", CPENC (3,0,C9,C11,6), 0),
4488
3454861d
PW		 4489 SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0),
4490 SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0),
4491 SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
4492 SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
4493 SR_CORE ("trcrsr", CPENC (2,1,C0,C10,0), 0),
4494
12e35da6
PW		 4495 SR_CORE ("trcauthstatus", CPENC (2,1,C7,C14,6), F_REG_READ),
4496 SR_CORE ("trccidr0", CPENC (2,1,C7,C12,7), F_REG_READ),
4497 SR_CORE ("trccidr1", CPENC (2,1,C7,C13,7), F_REG_READ),
4498 SR_CORE ("trccidr2", CPENC (2,1,C7,C14,7), F_REG_READ),
4499 SR_CORE ("trccidr3", CPENC (2,1,C7,C15,7), F_REG_READ),
4500 SR_CORE ("trcdevaff0", CPENC (2,1,C7,C10,6), F_REG_READ),
4501 SR_CORE ("trcdevaff1", CPENC (2,1,C7,C11,6), F_REG_READ),
4502 SR_CORE ("trcdevarch", CPENC (2,1,C7,C15,6), F_REG_READ),
4503 SR_CORE ("trcdevid", CPENC (2,1,C7,C2,7), F_REG_READ),
4504 SR_CORE ("trcdevtype", CPENC (2,1,C7,C3,7), F_REG_READ),
4505 SR_CORE ("trcidr0", CPENC (2,1,C0,C8,7), F_REG_READ),
4506 SR_CORE ("trcidr1", CPENC (2,1,C0,C9,7), F_REG_READ),
4507 SR_CORE ("trcidr2", CPENC (2,1,C0,C10,7), F_REG_READ),
4508 SR_CORE ("trcidr3", CPENC (2,1,C0,C11,7), F_REG_READ),
4509 SR_CORE ("trcidr4", CPENC (2,1,C0,C12,7), F_REG_READ),
4510 SR_CORE ("trcidr5", CPENC (2,1,C0,C13,7), F_REG_READ),
4511 SR_CORE ("trcidr6", CPENC (2,1,C0,C14,7), F_REG_READ),
4512 SR_CORE ("trcidr7", CPENC (2,1,C0,C15,7), F_REG_READ),
4513 SR_CORE ("trcidr8", CPENC (2,1,C0,C0,6), F_REG_READ),
4514 SR_CORE ("trcidr9", CPENC (2,1,C0,C1,6), F_REG_READ),
4515 SR_CORE ("trcidr10", CPENC (2,1,C0,C2,6), F_REG_READ),
4516 SR_CORE ("trcidr11", CPENC (2,1,C0,C3,6), F_REG_READ),
4517 SR_CORE ("trcidr12", CPENC (2,1,C0,C4,6), F_REG_READ),
4518 SR_CORE ("trcidr13", CPENC (2,1,C0,C5,6), F_REG_READ),
4519 SR_CORE ("trclsr", CPENC (2,1,C7,C13,6), F_REG_READ),
4520 SR_CORE ("trcoslsr", CPENC (2,1,C1,C1,4), F_REG_READ),
4521 SR_CORE ("trcpdsr", CPENC (2,1,C1,C5,4), F_REG_READ),
4522 SR_CORE ("trcpidr0", CPENC (2,1,C7,C8,7), F_REG_READ),
4523 SR_CORE ("trcpidr1", CPENC (2,1,C7,C9,7), F_REG_READ),
4524 SR_CORE ("trcpidr2", CPENC (2,1,C7,C10,7), F_REG_READ),
4525 SR_CORE ("trcpidr3", CPENC (2,1,C7,C11,7), F_REG_READ),
4526 SR_CORE ("trcpidr4", CPENC (2,1,C7,C4,7), F_REG_READ),
4527 SR_CORE ("trcpidr5", CPENC (2,1,C7,C5,7), F_REG_READ),
4528 SR_CORE ("trcpidr6", CPENC (2,1,C7,C6,7), F_REG_READ),
4529 SR_CORE ("trcpidr7", CPENC (2,1,C7,C7,7), F_REG_READ),
4530 SR_CORE ("trcstatr", CPENC (2,1,C0,C3,0), F_REG_READ),
4531 SR_CORE ("trcacatr0", CPENC (2,1,C2,C0,2), 0),
4532 SR_CORE ("trcacatr1", CPENC (2,1,C2,C2,2), 0),
4533 SR_CORE ("trcacatr2", CPENC (2,1,C2,C4,2), 0),
4534 SR_CORE ("trcacatr3", CPENC (2,1,C2,C6,2), 0),
4535 SR_CORE ("trcacatr4", CPENC (2,1,C2,C8,2), 0),
4536 SR_CORE ("trcacatr5", CPENC (2,1,C2,C10,2), 0),
4537 SR_CORE ("trcacatr6", CPENC (2,1,C2,C12,2), 0),
4538 SR_CORE ("trcacatr7", CPENC (2,1,C2,C14,2), 0),
4539 SR_CORE ("trcacatr8", CPENC (2,1,C2,C0,3), 0),
4540 SR_CORE ("trcacatr9", CPENC (2,1,C2,C2,3), 0),
4541 SR_CORE ("trcacatr10", CPENC (2,1,C2,C4,3), 0),
4542 SR_CORE ("trcacatr11", CPENC (2,1,C2,C6,3), 0),
4543 SR_CORE ("trcacatr12", CPENC (2,1,C2,C8,3), 0),
4544 SR_CORE ("trcacatr13", CPENC (2,1,C2,C10,3), 0),
4545 SR_CORE ("trcacatr14", CPENC (2,1,C2,C12,3), 0),
4546 SR_CORE ("trcacatr15", CPENC (2,1,C2,C14,3), 0),
4547 SR_CORE ("trcacvr0", CPENC (2,1,C2,C0,0), 0),
4548 SR_CORE ("trcacvr1", CPENC (2,1,C2,C2,0), 0),
4549 SR_CORE ("trcacvr2", CPENC (2,1,C2,C4,0), 0),
4550 SR_CORE ("trcacvr3", CPENC (2,1,C2,C6,0), 0),
4551 SR_CORE ("trcacvr4", CPENC (2,1,C2,C8,0), 0),
4552 SR_CORE ("trcacvr5", CPENC (2,1,C2,C10,0), 0),
4553 SR_CORE ("trcacvr6", CPENC (2,1,C2,C12,0), 0),
4554 SR_CORE ("trcacvr7", CPENC (2,1,C2,C14,0), 0),
4555 SR_CORE ("trcacvr8", CPENC (2,1,C2,C0,1), 0),
4556 SR_CORE ("trcacvr9", CPENC (2,1,C2,C2,1), 0),
4557 SR_CORE ("trcacvr10", CPENC (2,1,C2,C4,1), 0),
4558 SR_CORE ("trcacvr11", CPENC (2,1,C2,C6,1), 0),
4559 SR_CORE ("trcacvr12", CPENC (2,1,C2,C8,1), 0),
4560 SR_CORE ("trcacvr13", CPENC (2,1,C2,C10,1), 0),
4561 SR_CORE ("trcacvr14", CPENC (2,1,C2,C12,1), 0),
4562 SR_CORE ("trcacvr15", CPENC (2,1,C2,C14,1), 0),
4563 SR_CORE ("trcauxctlr", CPENC (2,1,C0,C6,0), 0),
4564 SR_CORE ("trcbbctlr", CPENC (2,1,C0,C15,0), 0),
4565 SR_CORE ("trcccctlr", CPENC (2,1,C0,C14,0), 0),
4566 SR_CORE ("trccidcctlr0", CPENC (2,1,C3,C0,2), 0),
4567 SR_CORE ("trccidcctlr1", CPENC (2,1,C3,C1,2), 0),
4568 SR_CORE ("trccidcvr0", CPENC (2,1,C3,C0,0), 0),
4569 SR_CORE ("trccidcvr1", CPENC (2,1,C3,C2,0), 0),
4570 SR_CORE ("trccidcvr2", CPENC (2,1,C3,C4,0), 0),
4571 SR_CORE ("trccidcvr3", CPENC (2,1,C3,C6,0), 0),
4572 SR_CORE ("trccidcvr4", CPENC (2,1,C3,C8,0), 0),
4573 SR_CORE ("trccidcvr5", CPENC (2,1,C3,C10,0), 0),
4574 SR_CORE ("trccidcvr6", CPENC (2,1,C3,C12,0), 0),
4575 SR_CORE ("trccidcvr7", CPENC (2,1,C3,C14,0), 0),
4576 SR_CORE ("trcclaimclr", CPENC (2,1,C7,C9,6), 0),
4577 SR_CORE ("trcclaimset", CPENC (2,1,C7,C8,6), 0),
4578 SR_CORE ("trccntctlr0", CPENC (2,1,C0,C4,5), 0),
4579 SR_CORE ("trccntctlr1", CPENC (2,1,C0,C5,5), 0),
4580 SR_CORE ("trccntctlr2", CPENC (2,1,C0,C6,5), 0),
4581 SR_CORE ("trccntctlr3", CPENC (2,1,C0,C7,5), 0),
4582 SR_CORE ("trccntrldvr0", CPENC (2,1,C0,C0,5), 0),
4583 SR_CORE ("trccntrldvr1", CPENC (2,1,C0,C1,5), 0),
4584 SR_CORE ("trccntrldvr2", CPENC (2,1,C0,C2,5), 0),
4585 SR_CORE ("trccntrldvr3", CPENC (2,1,C0,C3,5), 0),
4586 SR_CORE ("trccntvr0", CPENC (2,1,C0,C8,5), 0),
4587 SR_CORE ("trccntvr1", CPENC (2,1,C0,C9,5), 0),
4588 SR_CORE ("trccntvr2", CPENC (2,1,C0,C10,5), 0),
4589 SR_CORE ("trccntvr3", CPENC (2,1,C0,C11,5), 0),
4590 SR_CORE ("trcconfigr", CPENC (2,1,C0,C4,0), 0),
4591 SR_CORE ("trcdvcmr0", CPENC (2,1,C2,C0,6), 0),
4592 SR_CORE ("trcdvcmr1", CPENC (2,1,C2,C4,6), 0),
4593 SR_CORE ("trcdvcmr2", CPENC (2,1,C2,C8,6), 0),
4594 SR_CORE ("trcdvcmr3", CPENC (2,1,C2,C12,6), 0),
4595 SR_CORE ("trcdvcmr4", CPENC (2,1,C2,C0,7), 0),
4596 SR_CORE ("trcdvcmr5", CPENC (2,1,C2,C4,7), 0),
4597 SR_CORE ("trcdvcmr6", CPENC (2,1,C2,C8,7), 0),
4598 SR_CORE ("trcdvcmr7", CPENC (2,1,C2,C12,7), 0),
4599 SR_CORE ("trcdvcvr0", CPENC (2,1,C2,C0,4), 0),
4600 SR_CORE ("trcdvcvr1", CPENC (2,1,C2,C4,4), 0),
4601 SR_CORE ("trcdvcvr2", CPENC (2,1,C2,C8,4), 0),
4602 SR_CORE ("trcdvcvr3", CPENC (2,1,C2,C12,4), 0),
4603 SR_CORE ("trcdvcvr4", CPENC (2,1,C2,C0,5), 0),
4604 SR_CORE ("trcdvcvr5", CPENC (2,1,C2,C4,5), 0),
4605 SR_CORE ("trcdvcvr6", CPENC (2,1,C2,C8,5), 0),
4606 SR_CORE ("trcdvcvr7", CPENC (2,1,C2,C12,5), 0),
4607 SR_CORE ("trceventctl0r", CPENC (2,1,C0,C8,0), 0),
4608 SR_CORE ("trceventctl1r", CPENC (2,1,C0,C9,0), 0),
4609 SR_CORE ("trcextinselr0", CPENC (2,1,C0,C8,4), 0),
4610 SR_CORE ("trcextinselr", CPENC (2,1,C0,C8,4), 0),
4611 SR_CORE ("trcextinselr1", CPENC (2,1,C0,C9,4), 0),
4612 SR_CORE ("trcextinselr2", CPENC (2,1,C0,C10,4), 0),
4613 SR_CORE ("trcextinselr3", CPENC (2,1,C0,C11,4), 0),
4614 SR_CORE ("trcimspec0", CPENC (2,1,C0,C0,7), 0),
4615 SR_CORE ("trcimspec0", CPENC (2,1,C0,C0,7), 0),
4616 SR_CORE ("trcimspec1", CPENC (2,1,C0,C1,7), 0),
4617 SR_CORE ("trcimspec2", CPENC (2,1,C0,C2,7), 0),
4618 SR_CORE ("trcimspec3", CPENC (2,1,C0,C3,7), 0),
4619 SR_CORE ("trcimspec4", CPENC (2,1,C0,C4,7), 0),
4620 SR_CORE ("trcimspec5", CPENC (2,1,C0,C5,7), 0),
4621 SR_CORE ("trcimspec6", CPENC (2,1,C0,C6,7), 0),
4622 SR_CORE ("trcimspec7", CPENC (2,1,C0,C7,7), 0),
4623 SR_CORE ("trcitctrl", CPENC (2,1,C7,C0,4), 0),
4624 SR_CORE ("trcpdcr", CPENC (2,1,C1,C4,4), 0),
4625 SR_CORE ("trcprgctlr", CPENC (2,1,C0,C1,0), 0),
4626 SR_CORE ("trcprocselr", CPENC (2,1,C0,C2,0), 0),
4627 SR_CORE ("trcqctlr", CPENC (2,1,C0,C1,1), 0),
4628 SR_CORE ("trcrsctlr2", CPENC (2,1,C1,C2,0), 0),
4629 SR_CORE ("trcrsctlr3", CPENC (2,1,C1,C3,0), 0),
4630 SR_CORE ("trcrsctlr4", CPENC (2,1,C1,C4,0), 0),
4631 SR_CORE ("trcrsctlr5", CPENC (2,1,C1,C5,0), 0),
4632 SR_CORE ("trcrsctlr6", CPENC (2,1,C1,C6,0), 0),
4633 SR_CORE ("trcrsctlr7", CPENC (2,1,C1,C7,0), 0),
4634 SR_CORE ("trcrsctlr8", CPENC (2,1,C1,C8,0), 0),
4635 SR_CORE ("trcrsctlr9", CPENC (2,1,C1,C9,0), 0),
4636 SR_CORE ("trcrsctlr10", CPENC (2,1,C1,C10,0), 0),
4637 SR_CORE ("trcrsctlr11", CPENC (2,1,C1,C11,0), 0),
4638 SR_CORE ("trcrsctlr12", CPENC (2,1,C1,C12,0), 0),
4639 SR_CORE ("trcrsctlr13", CPENC (2,1,C1,C13,0), 0),
4640 SR_CORE ("trcrsctlr14", CPENC (2,1,C1,C14,0), 0),
4641 SR_CORE ("trcrsctlr15", CPENC (2,1,C1,C15,0), 0),
4642 SR_CORE ("trcrsctlr16", CPENC (2,1,C1,C0,1), 0),
4643 SR_CORE ("trcrsctlr17", CPENC (2,1,C1,C1,1), 0),
4644 SR_CORE ("trcrsctlr18", CPENC (2,1,C1,C2,1), 0),
4645 SR_CORE ("trcrsctlr19", CPENC (2,1,C1,C3,1), 0),
4646 SR_CORE ("trcrsctlr20", CPENC (2,1,C1,C4,1), 0),
4647 SR_CORE ("trcrsctlr21", CPENC (2,1,C1,C5,1), 0),
4648 SR_CORE ("trcrsctlr22", CPENC (2,1,C1,C6,1), 0),
4649 SR_CORE ("trcrsctlr23", CPENC (2,1,C1,C7,1), 0),
4650 SR_CORE ("trcrsctlr24", CPENC (2,1,C1,C8,1), 0),
4651 SR_CORE ("trcrsctlr25", CPENC (2,1,C1,C9,1), 0),
4652 SR_CORE ("trcrsctlr26", CPENC (2,1,C1,C10,1), 0),
4653 SR_CORE ("trcrsctlr27", CPENC (2,1,C1,C11,1), 0),
4654 SR_CORE ("trcrsctlr28", CPENC (2,1,C1,C12,1), 0),
4655 SR_CORE ("trcrsctlr29", CPENC (2,1,C1,C13,1), 0),
4656 SR_CORE ("trcrsctlr30", CPENC (2,1,C1,C14,1), 0),
4657 SR_CORE ("trcrsctlr31", CPENC (2,1,C1,C15,1), 0),
4658 SR_CORE ("trcseqevr0", CPENC (2,1,C0,C0,4), 0),
4659 SR_CORE ("trcseqevr1", CPENC (2,1,C0,C1,4), 0),
4660 SR_CORE ("trcseqevr2", CPENC (2,1,C0,C2,4), 0),
4661 SR_CORE ("trcseqrstevr", CPENC (2,1,C0,C6,4), 0),
4662 SR_CORE ("trcseqstr", CPENC (2,1,C0,C7,4), 0),
4663 SR_CORE ("trcssccr0", CPENC (2,1,C1,C0,2), 0),
4664 SR_CORE ("trcssccr1", CPENC (2,1,C1,C1,2), 0),
4665 SR_CORE ("trcssccr2", CPENC (2,1,C1,C2,2), 0),
4666 SR_CORE ("trcssccr3", CPENC (2,1,C1,C3,2), 0),
4667 SR_CORE ("trcssccr4", CPENC (2,1,C1,C4,2), 0),
4668 SR_CORE ("trcssccr5", CPENC (2,1,C1,C5,2), 0),
4669 SR_CORE ("trcssccr6", CPENC (2,1,C1,C6,2), 0),
4670 SR_CORE ("trcssccr7", CPENC (2,1,C1,C7,2), 0),
4671 SR_CORE ("trcsscsr0", CPENC (2,1,C1,C8,2), 0),
4672 SR_CORE ("trcsscsr1", CPENC (2,1,C1,C9,2), 0),
4673 SR_CORE ("trcsscsr2", CPENC (2,1,C1,C10,2), 0),
4674 SR_CORE ("trcsscsr3", CPENC (2,1,C1,C11,2), 0),
4675 SR_CORE ("trcsscsr4", CPENC (2,1,C1,C12,2), 0),
4676 SR_CORE ("trcsscsr5", CPENC (2,1,C1,C13,2), 0),
4677 SR_CORE ("trcsscsr6", CPENC (2,1,C1,C14,2), 0),
4678 SR_CORE ("trcsscsr7", CPENC (2,1,C1,C15,2), 0),
4679 SR_CORE ("trcsspcicr0", CPENC (2,1,C1,C0,3), 0),
4680 SR_CORE ("trcsspcicr1", CPENC (2,1,C1,C1,3), 0),
4681 SR_CORE ("trcsspcicr2", CPENC (2,1,C1,C2,3), 0),
4682 SR_CORE ("trcsspcicr3", CPENC (2,1,C1,C3,3), 0),
4683 SR_CORE ("trcsspcicr4", CPENC (2,1,C1,C4,3), 0),
4684 SR_CORE ("trcsspcicr5", CPENC (2,1,C1,C5,3), 0),
4685 SR_CORE ("trcsspcicr6", CPENC (2,1,C1,C6,3), 0),
4686 SR_CORE ("trcsspcicr7", CPENC (2,1,C1,C7,3), 0),
4687 SR_CORE ("trcstallctlr", CPENC (2,1,C0,C11,0), 0),
4688 SR_CORE ("trcsyncpr", CPENC (2,1,C0,C13,0), 0),
4689 SR_CORE ("trctraceidr", CPENC (2,1,C0,C0,1), 0),
4690 SR_CORE ("trctsctlr", CPENC (2,1,C0,C12,0), 0),
4691 SR_CORE ("trcvdarcctlr", CPENC (2,1,C0,C10,2), 0),
4692 SR_CORE ("trcvdctlr", CPENC (2,1,C0,C8,2), 0),
4693 SR_CORE ("trcvdsacctlr", CPENC (2,1,C0,C9,2), 0),
4694 SR_CORE ("trcvictlr", CPENC (2,1,C0,C0,2), 0),
4695 SR_CORE ("trcviiectlr", CPENC (2,1,C0,C1,2), 0),
4696 SR_CORE ("trcvipcssctlr", CPENC (2,1,C0,C3,2), 0),
4697 SR_CORE ("trcvissctlr", CPENC (2,1,C0,C2,2), 0),
4698 SR_CORE ("trcvmidcctlr0", CPENC (2,1,C3,C2,2), 0),
4699 SR_CORE ("trcvmidcctlr1", CPENC (2,1,C3,C3,2), 0),
4700 SR_CORE ("trcvmidcvr0", CPENC (2,1,C3,C0,1), 0),
4701 SR_CORE ("trcvmidcvr1", CPENC (2,1,C3,C2,1), 0),
4702 SR_CORE ("trcvmidcvr2", CPENC (2,1,C3,C4,1), 0),
4703 SR_CORE ("trcvmidcvr3", CPENC (2,1,C3,C6,1), 0),
4704 SR_CORE ("trcvmidcvr4", CPENC (2,1,C3,C8,1), 0),
4705 SR_CORE ("trcvmidcvr5", CPENC (2,1,C3,C10,1), 0),
4706 SR_CORE ("trcvmidcvr6", CPENC (2,1,C3,C12,1), 0),
4707 SR_CORE ("trcvmidcvr7", CPENC (2,1,C3,C14,1), 0),
4708 SR_CORE ("trclar", CPENC (2,1,C7,C12,6), F_REG_WRITE),
4709 SR_CORE ("trcoslar", CPENC (2,1,C1,C0,4), F_REG_WRITE),
4710
5feaa09b
PW		 4711 SR_CORE ("csrcr_el0", CPENC (2,3,C8,C0,0), 0),
4712 SR_CORE ("csrptr_el0", CPENC (2,3,C8,C0,1), 0),
4713 SR_CORE ("csridr_el0", CPENC (2,3,C8,C0,2), F_REG_READ),
4714 SR_CORE ("csrptridx_el0", CPENC (2,3,C8,C0,3), F_REG_READ),
4715 SR_CORE ("csrcr_el1", CPENC (2,0,C8,C0,0), 0),
4716 SR_CORE ("csrcr_el12", CPENC (2,5,C8,C0,0), 0),
4717 SR_CORE ("csrptr_el1", CPENC (2,0,C8,C0,1), 0),
4718 SR_CORE ("csrptr_el12", CPENC (2,5,C8,C0,1), 0),
4719 SR_CORE ("csrptridx_el1", CPENC (2,0,C8,C0,3), F_REG_READ),
4720 SR_CORE ("csrcr_el2", CPENC (2,4,C8,C0,0), 0),
4721 SR_CORE ("csrptr_el2", CPENC (2,4,C8,C0,1), 0),
4722 SR_CORE ("csrptridx_el2", CPENC (2,4,C8,C0,3), F_REG_READ),
4723
7fce7ea9
PW		 4724 SR_CORE ("lorc_el1", CPENC (3,0,C10,C4,3), 0),
4725 SR_CORE ("lorea_el1", CPENC (3,0,C10,C4,1), 0),
4726 SR_CORE ("lorn_el1", CPENC (3,0,C10,C4,2), 0),
4727 SR_CORE ("lorsa_el1", CPENC (3,0,C10,C4,0), 0),
4728 SR_CORE ("icc_ctlr_el3", CPENC (3,6,C12,C12,4), 0),
4729 SR_CORE ("icc_sre_el1", CPENC (3,0,C12,C12,5), 0),
4730 SR_CORE ("icc_sre_el2", CPENC (3,4,C12,C9,5), 0),
4731 SR_CORE ("icc_sre_el3", CPENC (3,6,C12,C12,5), 0),
4732 SR_CORE ("ich_vtr_el2", CPENC (3,4,C12,C11,1), F_REG_READ),
4733
6278c6a6
PW		 4734 SR_CORE ("brbcr_el1", CPENC (2,1,C9,C0,0), 0),
4735 SR_CORE ("brbcr_el12", CPENC (2,5,C9,C0,0), 0),
4736 SR_CORE ("brbfcr_el1", CPENC (2,1,C9,C0,1), 0),
4737 SR_CORE ("brbts_el1", CPENC (2,1,C9,C0,2), 0),
4738 SR_CORE ("brbinfinj_el1", CPENC (2,1,C9,C1,0), 0),
4739 SR_CORE ("brbsrcinj_el1", CPENC (2,1,C9,C1,1), 0),
4740 SR_CORE ("brbtgtinj_el1", CPENC (2,1,C9,C1,2), 0),
4741 SR_CORE ("brbidr0_el1", CPENC (2,1,C9,C2,0), F_REG_READ),
4742 SR_CORE ("brbcr_el2", CPENC (2,4,C9,C0,0), 0),
4743 SR_CORE ("brbsrc0_el1", CPENC (2,1,C8,C0,1), F_REG_READ),
4744 SR_CORE ("brbsrc1_el1", CPENC (2,1,C8,C1,1), F_REG_READ),
4745 SR_CORE ("brbsrc2_el1", CPENC (2,1,C8,C2,1), F_REG_READ),
4746 SR_CORE ("brbsrc3_el1", CPENC (2,1,C8,C3,1), F_REG_READ),
4747 SR_CORE ("brbsrc4_el1", CPENC (2,1,C8,C4,1), F_REG_READ),
4748 SR_CORE ("brbsrc5_el1", CPENC (2,1,C8,C5,1), F_REG_READ),
4749 SR_CORE ("brbsrc6_el1", CPENC (2,1,C8,C6,1), F_REG_READ),
4750 SR_CORE ("brbsrc7_el1", CPENC (2,1,C8,C7,1), F_REG_READ),
4751 SR_CORE ("brbsrc8_el1", CPENC (2,1,C8,C8,1), F_REG_READ),
4752 SR_CORE ("brbsrc9_el1", CPENC (2,1,C8,C9,1), F_REG_READ),
4753 SR_CORE ("brbsrc10_el1", CPENC (2,1,C8,C10,1), F_REG_READ),
4754 SR_CORE ("brbsrc11_el1", CPENC (2,1,C8,C11,1), F_REG_READ),
4755 SR_CORE ("brbsrc12_el1", CPENC (2,1,C8,C12,1), F_REG_READ),
4756 SR_CORE ("brbsrc13_el1", CPENC (2,1,C8,C13,1), F_REG_READ),
4757 SR_CORE ("brbsrc14_el1", CPENC (2,1,C8,C14,1), F_REG_READ),
4758 SR_CORE ("brbsrc15_el1", CPENC (2,1,C8,C15,1), F_REG_READ),
4759 SR_CORE ("brbsrc16_el1", CPENC (2,1,C8,C0,5), F_REG_READ),
4760 SR_CORE ("brbsrc17_el1", CPENC (2,1,C8,C1,5), F_REG_READ),
4761 SR_CORE ("brbsrc18_el1", CPENC (2,1,C8,C2,5), F_REG_READ),
4762 SR_CORE ("brbsrc19_el1", CPENC (2,1,C8,C3,5), F_REG_READ),
4763 SR_CORE ("brbsrc20_el1", CPENC (2,1,C8,C4,5), F_REG_READ),
4764 SR_CORE ("brbsrc21_el1", CPENC (2,1,C8,C5,5), F_REG_READ),
4765 SR_CORE ("brbsrc22_el1", CPENC (2,1,C8,C6,5), F_REG_READ),
4766 SR_CORE ("brbsrc23_el1", CPENC (2,1,C8,C7,5), F_REG_READ),
4767 SR_CORE ("brbsrc24_el1", CPENC (2,1,C8,C8,5), F_REG_READ),
4768 SR_CORE ("brbsrc25_el1", CPENC (2,1,C8,C9,5), F_REG_READ),
4769 SR_CORE ("brbsrc26_el1", CPENC (2,1,C8,C10,5), F_REG_READ),
4770 SR_CORE ("brbsrc27_el1", CPENC (2,1,C8,C11,5), F_REG_READ),
4771 SR_CORE ("brbsrc28_el1", CPENC (2,1,C8,C12,5), F_REG_READ),
4772 SR_CORE ("brbsrc29_el1", CPENC (2,1,C8,C13,5), F_REG_READ),
4773 SR_CORE ("brbsrc30_el1", CPENC (2,1,C8,C14,5), F_REG_READ),
4774 SR_CORE ("brbsrc31_el1", CPENC (2,1,C8,C15,5), F_REG_READ),
4775 SR_CORE ("brbtgt0_el1", CPENC (2,1,C8,C0,2), F_REG_READ),
4776 SR_CORE ("brbtgt1_el1", CPENC (2,1,C8,C1,2), F_REG_READ),
4777 SR_CORE ("brbtgt2_el1", CPENC (2,1,C8,C2,2), F_REG_READ),
4778 SR_CORE ("brbtgt3_el1", CPENC (2,1,C8,C3,2), F_REG_READ),
4779 SR_CORE ("brbtgt4_el1", CPENC (2,1,C8,C4,2), F_REG_READ),
4780 SR_CORE ("brbtgt5_el1", CPENC (2,1,C8,C5,2), F_REG_READ),
4781 SR_CORE ("brbtgt6_el1", CPENC (2,1,C8,C6,2), F_REG_READ),
4782 SR_CORE ("brbtgt7_el1", CPENC (2,1,C8,C7,2), F_REG_READ),
4783 SR_CORE ("brbtgt8_el1", CPENC (2,1,C8,C8,2), F_REG_READ),
4784 SR_CORE ("brbtgt9_el1", CPENC (2,1,C8,C9,2), F_REG_READ),
4785 SR_CORE ("brbtgt10_el1", CPENC (2,1,C8,C10,2), F_REG_READ),
4786 SR_CORE ("brbtgt11_el1", CPENC (2,1,C8,C11,2), F_REG_READ),
4787 SR_CORE ("brbtgt12_el1", CPENC (2,1,C8,C12,2), F_REG_READ),
4788 SR_CORE ("brbtgt13_el1", CPENC (2,1,C8,C13,2), F_REG_READ),
4789 SR_CORE ("brbtgt14_el1", CPENC (2,1,C8,C14,2), F_REG_READ),
4790 SR_CORE ("brbtgt15_el1", CPENC (2,1,C8,C15,2), F_REG_READ),
4791 SR_CORE ("brbtgt16_el1", CPENC (2,1,C8,C0,6), F_REG_READ),
4792 SR_CORE ("brbtgt17_el1", CPENC (2,1,C8,C1,6), F_REG_READ),
4793 SR_CORE ("brbtgt18_el1", CPENC (2,1,C8,C2,6), F_REG_READ),
4794 SR_CORE ("brbtgt19_el1", CPENC (2,1,C8,C3,6), F_REG_READ),
4795 SR_CORE ("brbtgt20_el1", CPENC (2,1,C8,C4,6), F_REG_READ),
4796 SR_CORE ("brbtgt21_el1", CPENC (2,1,C8,C5,6), F_REG_READ),
4797 SR_CORE ("brbtgt22_el1", CPENC (2,1,C8,C6,6), F_REG_READ),
4798 SR_CORE ("brbtgt23_el1", CPENC (2,1,C8,C7,6), F_REG_READ),
4799 SR_CORE ("brbtgt24_el1", CPENC (2,1,C8,C8,6), F_REG_READ),
4800 SR_CORE ("brbtgt25_el1", CPENC (2,1,C8,C9,6), F_REG_READ),
4801 SR_CORE ("brbtgt26_el1", CPENC (2,1,C8,C10,6), F_REG_READ),
4802 SR_CORE ("brbtgt27_el1", CPENC (2,1,C8,C11,6), F_REG_READ),
4803 SR_CORE ("brbtgt28_el1", CPENC (2,1,C8,C12,6), F_REG_READ),
4804 SR_CORE ("brbtgt29_el1", CPENC (2,1,C8,C13,6), F_REG_READ),
4805 SR_CORE ("brbtgt30_el1", CPENC (2,1,C8,C14,6), F_REG_READ),
4806 SR_CORE ("brbtgt31_el1", CPENC (2,1,C8,C15,6), F_REG_READ),
4807 SR_CORE ("brbinf0_el1", CPENC (2,1,C8,C0,0), F_REG_READ),
4808 SR_CORE ("brbinf1_el1", CPENC (2,1,C8,C1,0), F_REG_READ),
4809 SR_CORE ("brbinf2_el1", CPENC (2,1,C8,C2,0), F_REG_READ),
4810 SR_CORE ("brbinf3_el1", CPENC (2,1,C8,C3,0), F_REG_READ),
4811 SR_CORE ("brbinf4_el1", CPENC (2,1,C8,C4,0), F_REG_READ),
4812 SR_CORE ("brbinf5_el1", CPENC (2,1,C8,C5,0), F_REG_READ),
4813 SR_CORE ("brbinf6_el1", CPENC (2,1,C8,C6,0), F_REG_READ),
4814 SR_CORE ("brbinf7_el1", CPENC (2,1,C8,C7,0), F_REG_READ),
4815 SR_CORE ("brbinf8_el1", CPENC (2,1,C8,C8,0), F_REG_READ),
4816 SR_CORE ("brbinf9_el1", CPENC (2,1,C8,C9,0), F_REG_READ),
4817 SR_CORE ("brbinf10_el1", CPENC (2,1,C8,C10,0), F_REG_READ),
4818 SR_CORE ("brbinf11_el1", CPENC (2,1,C8,C11,0), F_REG_READ),
4819 SR_CORE ("brbinf12_el1", CPENC (2,1,C8,C12,0), F_REG_READ),
4820 SR_CORE ("brbinf13_el1", CPENC (2,1,C8,C13,0), F_REG_READ),
4821 SR_CORE ("brbinf14_el1", CPENC (2,1,C8,C14,0), F_REG_READ),
4822 SR_CORE ("brbinf15_el1", CPENC (2,1,C8,C15,0), F_REG_READ),
4823 SR_CORE ("brbinf16_el1", CPENC (2,1,C8,C0,4), F_REG_READ),
4824 SR_CORE ("brbinf17_el1", CPENC (2,1,C8,C1,4), F_REG_READ),
4825 SR_CORE ("brbinf18_el1", CPENC (2,1,C8,C2,4), F_REG_READ),
4826 SR_CORE ("brbinf19_el1", CPENC (2,1,C8,C3,4), F_REG_READ),
4827 SR_CORE ("brbinf20_el1", CPENC (2,1,C8,C4,4), F_REG_READ),
4828 SR_CORE ("brbinf21_el1", CPENC (2,1,C8,C5,4), F_REG_READ),
4829 SR_CORE ("brbinf22_el1", CPENC (2,1,C8,C6,4), F_REG_READ),
4830 SR_CORE ("brbinf23_el1", CPENC (2,1,C8,C7,4), F_REG_READ),
4831 SR_CORE ("brbinf24_el1", CPENC (2,1,C8,C8,4), F_REG_READ),
4832 SR_CORE ("brbinf25_el1", CPENC (2,1,C8,C9,4), F_REG_READ),
4833 SR_CORE ("brbinf26_el1", CPENC (2,1,C8,C10,4), F_REG_READ),
4834 SR_CORE ("brbinf27_el1", CPENC (2,1,C8,C11,4), F_REG_READ),
4835 SR_CORE ("brbinf28_el1", CPENC (2,1,C8,C12,4), F_REG_READ),
4836 SR_CORE ("brbinf29_el1", CPENC (2,1,C8,C13,4), F_REG_READ),
4837 SR_CORE ("brbinf30_el1", CPENC (2,1,C8,C14,4), F_REG_READ),
4838 SR_CORE ("brbinf31_el1", CPENC (2,1,C8,C15,4), F_REG_READ),
4839
4a3e3e22
PW		 4840 SR_CORE ("accdata_el1", CPENC (3,0,C13,C0,5), 0),
4841
100e914d
PW		 4842 SR_CORE ("mfar_el3", CPENC (3,6,C6,C0,5), F_REG_READ),
4843 SR_CORE ("gpccr_el3", CPENC (3,6,C2,C1,6), 0),
4844 SR_CORE ("gptbr_el3", CPENC (3,6,C2,C1,4), 0),
4845
8f1bfdb4
PW		 4846 SR_SME ("svcr", CPENC (3,3,C4,C2,2), 0),
4847 SR_SME ("id_aa64smfr0_el1", CPENC (3,0,C0,C4,5), F_REG_READ),
4848 SR_SME ("smcr_el1", CPENC (3,0,C1,C2,6), 0),
4849 SR_SME ("smcr_el12", CPENC (3,5,C1,C2,6), 0),
4850 SR_SME ("smcr_el2", CPENC (3,4,C1,C2,6), 0),
4851 SR_SME ("smcr_el3", CPENC (3,6,C1,C2,6), 0),
4852 SR_SME ("smpri_el1", CPENC (3,0,C1,C2,4), 0),
4853 SR_SME ("smprimap_el2", CPENC (3,4,C1,C2,5), 0),
4854 SR_SME ("smidr_el1", CPENC (3,1,C0,C0,6), F_REG_READ),
4855 SR_SME ("tpidr2_el0", CPENC (3,3,C13,C0,5), 0),
4856 SR_SME ("mpamsm_el1", CPENC (3,0,C10,C5,3), 0),
3dd032c5 4857
14962256 4858 { 0, CPENC (0,0,0,0,0), 0, 0 }
a06ea964
NC		 4859};
4860
78933a4a 4861bool
f7cb161e 4862aarch64_sys_reg_deprecated_p (const uint32_t reg_flags)
49eec193 4863{
f7cb161e 4864 return (reg_flags & F_DEPRECATED) != 0;
f21cce2c
MW		 4865}
4866
793a1948
TC		 4867/* The CPENC below is fairly misleading, the fields
4868 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4869 by ins_pstatefield, which just shifts the value by the width of the fields
4870 in a loop. So if you CPENC them only the first value will be set, the rest
4871 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4872 value of 0b110000000001000000 (0x30040) while what you want is
4873 0b011010 (0x1a). */
87b8eed7 4874const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4875{
14962256
AC		 4876 SR_CORE ("spsel", 0x05, 0),
4877 SR_CORE ("daifset", 0x1e, 0),
4878 SR_CORE ("daifclr", 0x1f, 0),
4879 SR_PAN ("pan", 0x04, 0),
4880 SR_V8_2 ("uao", 0x03, 0),
4881 SR_SSBS ("ssbs", 0x19, 0),
4882 SR_V8_4 ("dit", 0x1a, 0),
4883 SR_MEMTAG ("tco", 0x1c, 0),
3dd032c5
PW		 4884 SR_SME ("svcrsm", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x2,0x1)),
4885 SR_SME ("svcrza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x4,0x1)),
4886 SR_SME ("svcrsmza", 0x1b, PSTATE_ENCODE_CRM_AND_IMM(0x6,0x1)),
14962256 4887 { 0, CPENC (0,0,0,0,0), 0, 0 },
a06ea964
NC		 4888};
4889
78933a4a 4890bool
f21cce2c
MW		 4891aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4892 const aarch64_sys_reg *reg)
4893{
4894 if (!(reg->flags & F_ARCHEXT))
78933a4a 4895 return true;
f21cce2c 4896
14962256 4897 return AARCH64_CPU_HAS_ALL_FEATURES (features, reg->features);
f21cce2c
MW		 4898}
4899
a06ea964
NC		 4900const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4901{
4902 { "ialluis", CPENS(0,C7,C1,0), 0 },
4903 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4904 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4905 { 0, CPENS(0,0,0,0), 0 }
4906};
4907
4908const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4909{
ea2deeec 4910 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4911 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4912 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4913 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4914 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4915 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4916 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4917 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4918 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4919 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4920 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4921 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4922 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4923 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4924 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4925 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4926 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4927 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4928 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4929 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4930 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4931 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4932 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4933 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4934 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4935 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4936 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4937 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
cd6608e4
PW		 4938 { "cipapa", CPENS (6, C7, C14, 1), F_HASXT },
4939 { "cigdpapa", CPENS (6, C7, C14, 5), F_HASXT },
a06ea964
NC		 4940 { 0, CPENS(0,0,0,0), 0 }
4941};
4942
4943const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4944{
ea2deeec
MW		 4945 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4946 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4947 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4948 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4949 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4950 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4951 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4952 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4953 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4954 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4955 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4956 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4957 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4958 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4959 { 0, CPENS(0,0,0,0), 0 }
4960};
4961
4962const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4963{
4964 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4965 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4966 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4967 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4968 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4969 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4970 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4971 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4972 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4973 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4974 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4975 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4976 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4977 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4978 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4979 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4980 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4981 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4982 { "alle2", CPENS(4,C8,C7,0), 0 },
4983 { "alle2is", CPENS(4,C8,C3,0), 0 },
4984 { "alle1", CPENS(4,C8,C7,4), 0 },
4985 { "alle1is", CPENS(4,C8,C3,4), 0 },
4986 { "alle3", CPENS(6,C8,C7,0), 0 },
4987 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4988 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4989 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4990 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4991 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4992 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4993 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4994 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4995 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4996
4997 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4998 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4999 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
5000 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
5001 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
5002 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
5003 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
5004 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
5005 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
5006 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
5007 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
5008 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
5009 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
5010 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
5011 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
5012 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
5013
5014 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
5015 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
5016 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
5017 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
5018 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
5019 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
5020 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
5021 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
5022 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
5023 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
5024 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
5025 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
5026 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
5027 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
5028 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
5029 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
5030 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
5031 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
5032 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
5033 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
5034 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
5035 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
5036 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
5037 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
5038 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
5039 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
5040 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
5041 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
5042 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
5043 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
5044
02202574
PW		 5045 { "rpaos", CPENS (6, C8, C4, 3), F_HASXT },
5046 { "rpalos", CPENS (6, C8, C4, 7), F_HASXT },
5047 { "paallos", CPENS (6, C8, C1, 4), 0},
5048 { "paall", CPENS (6, C8, C7, 4), 0},
5049
a06ea964
NC		 5050 { 0, CPENS(0,0,0,0), 0 }
5051};
5052
2ac435d4
SD		 5053const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
5054{
5055 /* RCTX is somewhat unique in a way that it has different values
5056 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
5057 Thus op2 is masked out and instead encoded directly in the
5058 aarch64_opcode_table entries for the respective instructions. */
5059 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
5060
5061 { 0, CPENS(0,0,0,0), 0 }
5062};
5063
78933a4a 5064bool
ea2deeec
MW		 5065aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
5066{
5067 return (sys_ins_reg->flags & F_HASXT) != 0;
5068}
5069
78933a4a 5070extern bool
d6bf7ce6 5071aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
38cf07a6 5072 const char *reg_name,
f7cb161e
PW		 5073 aarch64_insn reg_value,
5074 uint32_t reg_flags,
5075 aarch64_feature_set reg_features)
d6bf7ce6 5076{
38cf07a6
AC		 5077 /* Armv8-R has no EL3. */
5078 if (AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_R))
5079 {
5080 const char *suffix = strrchr (reg_name, '_');
5081 if (suffix && !strcmp (suffix, "_el3"))
78933a4a 5082 return false;
38cf07a6 5083 }
f7cb161e
PW		 5084
5085 if (!(reg_flags & F_ARCHEXT))
78933a4a 5086 return true;
f7cb161e
PW		 5087
5088 if (reg_features
5089 && AARCH64_CPU_HAS_ALL_FEATURES (features, reg_features))
78933a4a 5090 return true;
f7cb161e
PW		 5091
5092 /* ARMv8.4 TLB instructions. */
5093 if ((reg_value == CPENS (0, C8, C1, 0)
5094 || reg_value == CPENS (0, C8, C1, 1)
5095 || reg_value == CPENS (0, C8, C1, 2)
5096 || reg_value == CPENS (0, C8, C1, 3)
5097 || reg_value == CPENS (0, C8, C1, 5)
5098 || reg_value == CPENS (0, C8, C1, 7)
5099 || reg_value == CPENS (4, C8, C4, 0)
5100 || reg_value == CPENS (4, C8, C4, 4)
5101 || reg_value == CPENS (4, C8, C1, 1)
5102 || reg_value == CPENS (4, C8, C1, 5)
5103 || reg_value == CPENS (4, C8, C1, 6)
5104 || reg_value == CPENS (6, C8, C1, 1)
5105 || reg_value == CPENS (6, C8, C1, 5)
5106 || reg_value == CPENS (4, C8, C1, 0)
5107 || reg_value == CPENS (4, C8, C1, 4)
5108 || reg_value == CPENS (6, C8, C1, 0)
5109 || reg_value == CPENS (0, C8, C6, 1)
5110 || reg_value == CPENS (0, C8, C6, 3)
5111 || reg_value == CPENS (0, C8, C6, 5)
5112 || reg_value == CPENS (0, C8, C6, 7)
5113 || reg_value == CPENS (0, C8, C2, 1)
5114 || reg_value == CPENS (0, C8, C2, 3)
5115 || reg_value == CPENS (0, C8, C2, 5)
5116 || reg_value == CPENS (0, C8, C2, 7)
5117 || reg_value == CPENS (0, C8, C5, 1)
5118 || reg_value == CPENS (0, C8, C5, 3)
5119 || reg_value == CPENS (0, C8, C5, 5)
5120 || reg_value == CPENS (0, C8, C5, 7)
5121 || reg_value == CPENS (4, C8, C0, 2)
5122 || reg_value == CPENS (4, C8, C0, 6)
5123 || reg_value == CPENS (4, C8, C4, 2)
5124 || reg_value == CPENS (4, C8, C4, 6)
5125 || reg_value == CPENS (4, C8, C4, 3)
5126 || reg_value == CPENS (4, C8, C4, 7)
5127 || reg_value == CPENS (4, C8, C6, 1)
5128 || reg_value == CPENS (4, C8, C6, 5)
5129 || reg_value == CPENS (4, C8, C2, 1)
5130 || reg_value == CPENS (4, C8, C2, 5)
5131 || reg_value == CPENS (4, C8, C5, 1)
5132 || reg_value == CPENS (4, C8, C5, 5)
5133 || reg_value == CPENS (6, C8, C6, 1)
5134 || reg_value == CPENS (6, C8, C6, 5)
5135 || reg_value == CPENS (6, C8, C2, 1)
5136 || reg_value == CPENS (6, C8, C2, 5)
5137 || reg_value == CPENS (6, C8, C5, 1)
5138 || reg_value == CPENS (6, C8, C5, 5))
5139 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
78933a4a 5140 return true;
d6bf7ce6
MW		 5141
5142 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
f7cb161e
PW		 5143 if (reg_value == CPENS (3, C7, C12, 1)
5144 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
78933a4a 5145 return true;
d6bf7ce6 5146
3fd229a4 5147 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
f7cb161e
PW		 5148 if (reg_value == CPENS (3, C7, C13, 1)
5149 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
78933a4a 5150 return true;
3fd229a4 5151
3a0f69be 5152 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
f7cb161e
PW		 5153 if ((reg_value == CPENS (0, C7, C6, 3)
5154 || reg_value == CPENS (0, C7, C6, 4)
5155 || reg_value == CPENS (0, C7, C10, 4)
5156 || reg_value == CPENS (0, C7, C14, 4)
5157 || reg_value == CPENS (3, C7, C10, 3)
5158 || reg_value == CPENS (3, C7, C12, 3)
5159 || reg_value == CPENS (3, C7, C13, 3)
5160 || reg_value == CPENS (3, C7, C14, 3)
5161 || reg_value == CPENS (3, C7, C4, 3)
5162 || reg_value == CPENS (0, C7, C6, 5)
5163 || reg_value == CPENS (0, C7, C6, 6)
5164 || reg_value == CPENS (0, C7, C10, 6)
5165 || reg_value == CPENS (0, C7, C14, 6)
5166 || reg_value == CPENS (3, C7, C10, 5)
5167 || reg_value == CPENS (3, C7, C12, 5)
5168 || reg_value == CPENS (3, C7, C13, 5)
5169 || reg_value == CPENS (3, C7, C14, 5)
5170 || reg_value == CPENS (3, C7, C4, 4))
5171 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
78933a4a 5172 return true;
3a0f69be 5173
63511907 5174 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
f7cb161e
PW		 5175 if ((reg_value == CPENS (0, C7, C9, 0)
5176 || reg_value == CPENS (0, C7, C9, 1))
5177 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
78933a4a 5178 return true;
63511907 5179
2ac435d4 5180 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
f7cb161e
PW		 5181 if (reg_value == CPENS (3, C7, C3, 0)
5182 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
78933a4a 5183 return true;
2ac435d4 5184
78933a4a 5185 return false;
d6bf7ce6
MW		 5186}
5187
a06ea964
NC		 5188#undef C0
5189#undef C1
5190#undef C2
5191#undef C3
5192#undef C4
5193#undef C5
5194#undef C6
5195#undef C7
5196#undef C8
5197#undef C9
5198#undef C10
5199#undef C11
5200#undef C12
5201#undef C13
5202#undef C14
5203#undef C15
5204
4bd13cde
NC		 5205#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
5206#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
5207
755b748f
TC		 5208static enum err_type
5209verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
5210 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
78933a4a 5211 bool encoding ATTRIBUTE_UNUSED,
755b748f 5212 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 5213 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 5214{
5215 int t = BITS (insn, 4, 0);
5216 int n = BITS (insn, 9, 5);
5217 int t2 = BITS (insn, 14, 10);
5218
5219 if (BIT (insn, 23))
5220 {
5221 /* Write back enabled. */
5222 if ((t == n || t2 == n) && n != 31)
755b748f 5223 return ERR_UND;
4bd13cde
NC		 5224 }
5225
5226 if (BIT (insn, 22))
5227 {
5228 /* Load */
5229 if (t == t2)
755b748f 5230 return ERR_UND;
4bd13cde
NC		 5231 }
5232
755b748f 5233 return ERR_OK;
4bd13cde
NC		 5234}
5235
6456d318
TC		 5236/* Verifier for vector by element 3 operands functions where the
5237 conditions `if sz:L == 11 then UNDEFINED` holds. */
5238
5239static enum err_type
5240verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
78933a4a 5241 bfd_vma pc ATTRIBUTE_UNUSED, bool encoding,
6456d318
TC		 5242 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
5243 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
5244{
5245 const aarch64_insn undef_pattern = 0x3;
5246 aarch64_insn value;
5247
5248 assert (inst->opcode);
5249 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
5250 value = encoding ? inst->value : insn;
5251 assert (value);
5252
5253 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
5254 return ERR_UND;
5255
5256 return ERR_OK;
5257}
5258
a68f4cd2
TC		 5259/* Initialize an instruction sequence insn_sequence with the instruction INST.
5260 If INST is NULL the given insn_sequence is cleared and the sequence is left
5261 uninitialized. */
5262
5263void
5264init_insn_sequence (const struct aarch64_inst *inst,
5265 aarch64_instr_sequence *insn_sequence)
5266{
5267 int num_req_entries = 0;
5268 insn_sequence->next_insn = 0;
5269 insn_sequence->num_insns = num_req_entries;
5270 if (insn_sequence->instr)
5271 XDELETE (insn_sequence->instr);
5272 insn_sequence->instr = NULL;
5273
5274 if (inst)
5275 {
5276 insn_sequence->instr = XNEW (aarch64_inst);
5277 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
5278 }
5279
5280 /* Handle all the cases here. May need to think of something smarter than
5281 a giant if/else chain if this grows. At that time, a lookup table may be
5282 best. */
5283 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
5284 num_req_entries = 1;
5285
5286 if (insn_sequence->current_insns)
5287 XDELETEVEC (insn_sequence->current_insns);
5288 insn_sequence->current_insns = NULL;
5289
5290 if (num_req_entries != 0)
5291 {
5292 size_t size = num_req_entries * sizeof (aarch64_inst);
5293 insn_sequence->current_insns
5294 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
5295 memset (insn_sequence->current_insns, 0, size);
5296 }
5297}
5298
5299
5300/* This function verifies that the instruction INST adheres to its specified
5301 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
5302 returned and MISMATCH_DETAIL contains the reason why verification failed.
5303
5304 The function is called both during assembly and disassembly. If assembling
5305 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
5306 and will contain the PC of the current instruction w.r.t to the section.
5307
5308 If ENCODING and PC=0 then you are at a start of a section. The constraints
5309 are verified against the given state insn_sequence which is updated as it
5310 transitions through the verification. */
5311
5312enum err_type
5313verify_constraints (const struct aarch64_inst *inst,
5314 const aarch64_insn insn ATTRIBUTE_UNUSED,
5315 bfd_vma pc,
78933a4a 5316 bool encoding,
a68f4cd2
TC		 5317 aarch64_operand_error *mismatch_detail,
5318 aarch64_instr_sequence *insn_sequence)
5319{
5320 assert (inst);
5321 assert (inst->opcode);
5322
5323 const struct aarch64_opcode *opcode = inst->opcode;
5324 if (!opcode->constraints && !insn_sequence->instr)
5325 return ERR_OK;
5326
5327 assert (insn_sequence);
5328
5329 enum err_type res = ERR_OK;
5330
5331 /* This instruction puts a constraint on the insn_sequence. */
5332 if (opcode->flags & F_SCAN)
5333 {
5334 if (insn_sequence->instr)
5335 {
5336 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5337 mismatch_detail->error = _("instruction opens new dependency "
5338 "sequence without ending previous one");
5339 mismatch_detail->index = -1;
78933a4a 5340 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5341 res = ERR_VFI;
5342 }
5343
5344 init_insn_sequence (inst, insn_sequence);
5345 return res;
5346 }
5347
5348 /* Verify constraints on an existing sequence. */
5349 if (insn_sequence->instr)
5350 {
5351 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
5352 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
5353 closed a previous one that we should have. */
5354 if (!encoding && pc == 0)
5355 {
5356 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5357 mismatch_detail->error = _("previous `movprfx' sequence not closed");
5358 mismatch_detail->index = -1;
78933a4a 5359 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5360 res = ERR_VFI;
5361 /* Reset the sequence. */
5362 init_insn_sequence (NULL, insn_sequence);
5363 return res;
5364 }
5365
5366 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
5367 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
5368 {
5369 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
5370 instruction for better error messages. */
5cd99750
MM		 5371 if (!opcode->avariant
5372 || !(*opcode->avariant &
5373 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
a68f4cd2
TC		 5374 {
5375 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5376 mismatch_detail->error = _("SVE instruction expected after "
5377 "`movprfx'");
5378 mismatch_detail->index = -1;
78933a4a 5379 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5380 res = ERR_VFI;
5381 goto done;
5382 }
5383
5384 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
5385 instruction that is allowed to be used with a MOVPRFX. */
5386 if (!(opcode->constraints & C_SCAN_MOVPRFX))
5387 {
5388 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5389 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
5390 "expected");
5391 mismatch_detail->index = -1;
78933a4a 5392 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5393 res = ERR_VFI;
5394 goto done;
5395 }
5396
5397 /* Next check for usage of the predicate register. */
5398 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 5399 aarch64_opnd_info blk_pred, inst_pred;
5400 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
5401 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
78933a4a 5402 bool predicated = false;
a68f4cd2
TC		 5403 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
5404
5405 /* Determine if the movprfx instruction used is predicated or not. */
5406 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
5407 {
78933a4a 5408 predicated = true;
a68f4cd2
TC		 5409 blk_pred = insn_sequence->instr->operands[1];
5410 }
5411
5412 unsigned char max_elem_size = 0;
5413 unsigned char current_elem_size;
5414 int num_op_used = 0, last_op_usage = 0;
5415 int i, inst_pred_idx = -1;
5416 int num_ops = aarch64_num_of_operands (opcode);
5417 for (i = 0; i < num_ops; i++)
5418 {
5419 aarch64_opnd_info inst_op = inst->operands[i];
5420 switch (inst_op.type)
5421 {
5422 case AARCH64_OPND_SVE_Zd:
5423 case AARCH64_OPND_SVE_Zm_5:
5424 case AARCH64_OPND_SVE_Zm_16:
5425 case AARCH64_OPND_SVE_Zn:
5426 case AARCH64_OPND_SVE_Zt:
5427 case AARCH64_OPND_SVE_Vm:
5428 case AARCH64_OPND_SVE_Vn:
5429 case AARCH64_OPND_Va:
5430 case AARCH64_OPND_Vn:
5431 case AARCH64_OPND_Vm:
5432 case AARCH64_OPND_Sn:
5433 case AARCH64_OPND_Sm:
a68f4cd2
TC		 5434 if (inst_op.reg.regno == blk_dest.reg.regno)
5435 {
5436 num_op_used++;
5437 last_op_usage = i;
5438 }
5439 current_elem_size
5440 = aarch64_get_qualifier_esize (inst_op.qualifier);
5441 if (current_elem_size > max_elem_size)
5442 max_elem_size = current_elem_size;
5443 break;
5444 case AARCH64_OPND_SVE_Pd:
5445 case AARCH64_OPND_SVE_Pg3:
5446 case AARCH64_OPND_SVE_Pg4_5:
5447 case AARCH64_OPND_SVE_Pg4_10:
5448 case AARCH64_OPND_SVE_Pg4_16:
5449 case AARCH64_OPND_SVE_Pm:
5450 case AARCH64_OPND_SVE_Pn:
5451 case AARCH64_OPND_SVE_Pt:
971eda73 5452 case AARCH64_OPND_SME_Pm:
a68f4cd2
TC		 5453 inst_pred = inst_op;
5454 inst_pred_idx = i;
5455 break;
5456 default:
5457 break;
5458 }
5459 }
5460
5461 assert (max_elem_size != 0);
5462 aarch64_opnd_info inst_dest = inst->operands[0];
5463 /* Determine the size that should be used to compare against the
5464 movprfx size. */
5465 current_elem_size
5466 = opcode->constraints & C_MAX_ELEM
5467 ? max_elem_size
5468 : aarch64_get_qualifier_esize (inst_dest.qualifier);
5469
5470 /* If movprfx is predicated do some extra checks. */
5471 if (predicated)
5472 {
5473 /* The instruction must be predicated. */
5474 if (inst_pred_idx < 0)
5475 {
5476 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5477 mismatch_detail->error = _("predicated instruction expected "
5478 "after `movprfx'");
5479 mismatch_detail->index = -1;
78933a4a 5480 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5481 res = ERR_VFI;
5482 goto done;
5483 }
5484
5485 /* The instruction must have a merging predicate. */
5486 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
5487 {
5488 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5489 mismatch_detail->error = _("merging predicate expected due "
5490 "to preceding `movprfx'");
5491 mismatch_detail->index = inst_pred_idx;
78933a4a 5492 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5493 res = ERR_VFI;
5494 goto done;
5495 }
5496
5497 /* The same register must be used in instruction. */
5498 if (blk_pred.reg.regno != inst_pred.reg.regno)
5499 {
5500 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5501 mismatch_detail->error = _("predicate register differs "
5502 "from that in preceding "
5503 "`movprfx'");
5504 mismatch_detail->index = inst_pred_idx;
78933a4a 5505 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5506 res = ERR_VFI;
5507 goto done;
5508 }
5509 }
5510
5511 /* Destructive operations by definition must allow one usage of the
5512 same register. */
5513 int allowed_usage
5514 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
5515
5516 /* Operand is not used at all. */
5517 if (num_op_used == 0)
5518 {
5519 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5520 mismatch_detail->error = _("output register of preceding "
5521 "`movprfx' not used in current "
5522 "instruction");
5523 mismatch_detail->index = 0;
78933a4a 5524 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5525 res = ERR_VFI;
5526 goto done;
5527 }
5528
5529 /* We now know it's used, now determine exactly where it's used. */
5530 if (blk_dest.reg.regno != inst_dest.reg.regno)
5531 {
5532 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5533 mismatch_detail->error = _("output register of preceding "
5534 "`movprfx' expected as output");
5535 mismatch_detail->index = 0;
78933a4a 5536 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5537 res = ERR_VFI;
5538 goto done;
5539 }
5540
5541 /* Operand used more than allowed for the specific opcode type. */
5542 if (num_op_used > allowed_usage)
5543 {
5544 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5545 mismatch_detail->error = _("output register of preceding "
5546 "`movprfx' used as input");
5547 mismatch_detail->index = last_op_usage;
78933a4a 5548 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5549 res = ERR_VFI;
5550 goto done;
5551 }
5552
5553 /* Now the only thing left is the qualifiers checks. The register
5554 must have the same maximum element size. */
5555 if (inst_dest.qualifier
5556 && blk_dest.qualifier
5557 && current_elem_size
5558 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5559 {
5560 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5561 mismatch_detail->error = _("register size not compatible with "
5562 "previous `movprfx'");
5563 mismatch_detail->index = 0;
78933a4a 5564 mismatch_detail->non_fatal = true;
a68f4cd2
TC		 5565 res = ERR_VFI;
5566 goto done;
5567 }
5568 }
5569
dc1e8a47 5570 done:
a68f4cd2
TC		 5571 /* Add the new instruction to the sequence. */
5572 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5573 inst, sizeof (aarch64_inst));
5574
5575 /* Check if sequence is now full. */
5576 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5577 {
5578 /* Sequence is full, but we don't have anything special to do for now,
5579 so clear and reset it. */
5580 init_insn_sequence (NULL, insn_sequence);
5581 }
5582 }
5583
5584 return res;
5585}
5586
5587
e950b345
RS		 5588/* Return true if VALUE cannot be moved into an SVE register using DUP
5589 (with any element size, not just ESIZE) and if using DUPM would
5590 therefore be OK. ESIZE is the number of bytes in the immediate. */
5591
78933a4a 5592bool
e950b345
RS		 5593aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5594{
5595 int64_t svalue = uvalue;
5596 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5597
5598 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
78933a4a 5599 return false;
e950b345
RS		 5600 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5601 {
5602 svalue = (int32_t) uvalue;
5603 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5604 {
5605 svalue = (int16_t) uvalue;
5606 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
78933a4a 5607 return false;
e950b345
RS		 5608 }
5609 }
5610 if ((svalue & 0xff) == 0)
5611 svalue /= 256;
5612 return svalue < -128 || svalue >= 128;
5613}
5614
a06ea964
NC		 5615/* Include the opcode description table as well as the operand description
5616 table. */
20f55f38 5617#define VERIFIER(x) verify_##x
a06ea964 5618#include "aarch64-tbl.h"
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