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[binutils][aarch64] Matrix Multiply extension enablement [8/X]
[thirdparty/binutils-gdb.git] / opcodes / aarch64-opc.c
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a06ea964 1/* aarch64-opc.c -- AArch64 opcode support.
82704155 2 Copyright (C) 2009-2019 Free Software Foundation, Inc.
a06ea964
NC		 3 Contributed by ARM Ltd.
4
5 This file is part of the GNU opcodes library.
6
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
10 any later version.
11
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
20
21#include "sysdep.h"
22#include <assert.h>
23#include <stdlib.h>
24#include <stdio.h>
2d5d5a8f 25#include "bfd_stdint.h"
a06ea964
NC		 26#include <stdarg.h>
27#include <inttypes.h>
28
29#include "opintl.h"
245d2e3f 30#include "libiberty.h"
a06ea964
NC		 31
32#include "aarch64-opc.h"
33
34#ifdef DEBUG_AARCH64
35int debug_dump = FALSE;
36#endif /* DEBUG_AARCH64 */
37
245d2e3f
RS		 38/* The enumeration strings associated with each value of a 5-bit SVE
39 pattern operand. A null entry indicates a reserved meaning. */
40const char *const aarch64_sve_pattern_array[32] = {
41 /* 0-7. */
42 "pow2",
43 "vl1",
44 "vl2",
45 "vl3",
46 "vl4",
47 "vl5",
48 "vl6",
49 "vl7",
50 /* 8-15. */
51 "vl8",
52 "vl16",
53 "vl32",
54 "vl64",
55 "vl128",
56 "vl256",
57 0,
58 0,
59 /* 16-23. */
60 0,
61 0,
62 0,
63 0,
64 0,
65 0,
66 0,
67 0,
68 /* 24-31. */
69 0,
70 0,
71 0,
72 0,
73 0,
74 "mul4",
75 "mul3",
76 "all"
77};
78
79/* The enumeration strings associated with each value of a 4-bit SVE
80 prefetch operand. A null entry indicates a reserved meaning. */
81const char *const aarch64_sve_prfop_array[16] = {
82 /* 0-7. */
83 "pldl1keep",
84 "pldl1strm",
85 "pldl2keep",
86 "pldl2strm",
87 "pldl3keep",
88 "pldl3strm",
89 0,
90 0,
91 /* 8-15. */
92 "pstl1keep",
93 "pstl1strm",
94 "pstl2keep",
95 "pstl2strm",
96 "pstl3keep",
97 "pstl3strm",
98 0,
99 0
100};
101
a06ea964
NC		 102/* Helper functions to determine which operand to be used to encode/decode
103 the size:Q fields for AdvSIMD instructions. */
104
105static inline bfd_boolean
106vector_qualifier_p (enum aarch64_opnd_qualifier qualifier)
107{
108 return ((qualifier >= AARCH64_OPND_QLF_V_8B
109 && qualifier <= AARCH64_OPND_QLF_V_1Q) ? TRUE
110 : FALSE);
111}
112
113static inline bfd_boolean
114fp_qualifier_p (enum aarch64_opnd_qualifier qualifier)
115{
116 return ((qualifier >= AARCH64_OPND_QLF_S_B
117 && qualifier <= AARCH64_OPND_QLF_S_Q) ? TRUE
118 : FALSE);
119}
120
121enum data_pattern
122{
123 DP_UNKNOWN,
124 DP_VECTOR_3SAME,
125 DP_VECTOR_LONG,
126 DP_VECTOR_WIDE,
127 DP_VECTOR_ACROSS_LANES,
128};
129
130static const char significant_operand_index [] =
131{
132 0, /* DP_UNKNOWN, by default using operand 0. */
133 0, /* DP_VECTOR_3SAME */
134 1, /* DP_VECTOR_LONG */
135 2, /* DP_VECTOR_WIDE */
136 1, /* DP_VECTOR_ACROSS_LANES */
137};
138
139/* Given a sequence of qualifiers in QUALIFIERS, determine and return
140 the data pattern.
141 N.B. QUALIFIERS is a possible sequence of qualifiers each of which
142 corresponds to one of a sequence of operands. */
143
144static enum data_pattern
145get_data_pattern (const aarch64_opnd_qualifier_seq_t qualifiers)
146{
147 if (vector_qualifier_p (qualifiers[0]) == TRUE)
148 {
149 /* e.g. v.4s, v.4s, v.4s
150 or v.4h, v.4h, v.h[3]. */
151 if (qualifiers[0] == qualifiers[1]
152 && vector_qualifier_p (qualifiers[2]) == TRUE
153 && (aarch64_get_qualifier_esize (qualifiers[0])
154 == aarch64_get_qualifier_esize (qualifiers[1]))
155 && (aarch64_get_qualifier_esize (qualifiers[0])
156 == aarch64_get_qualifier_esize (qualifiers[2])))
157 return DP_VECTOR_3SAME;
158 /* e.g. v.8h, v.8b, v.8b.
159 or v.4s, v.4h, v.h[2].
160 or v.8h, v.16b. */
161 if (vector_qualifier_p (qualifiers[1]) == TRUE
162 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
163 && (aarch64_get_qualifier_esize (qualifiers[0])
164 == aarch64_get_qualifier_esize (qualifiers[1]) << 1))
165 return DP_VECTOR_LONG;
166 /* e.g. v.8h, v.8h, v.8b. */
167 if (qualifiers[0] == qualifiers[1]
168 && vector_qualifier_p (qualifiers[2]) == TRUE
169 && aarch64_get_qualifier_esize (qualifiers[0]) != 0
170 && (aarch64_get_qualifier_esize (qualifiers[0])
171 == aarch64_get_qualifier_esize (qualifiers[2]) << 1)
172 && (aarch64_get_qualifier_esize (qualifiers[0])
173 == aarch64_get_qualifier_esize (qualifiers[1])))
174 return DP_VECTOR_WIDE;
175 }
176 else if (fp_qualifier_p (qualifiers[0]) == TRUE)
177 {
178 /* e.g. SADDLV <V><d>, <Vn>.<T>. */
179 if (vector_qualifier_p (qualifiers[1]) == TRUE
180 && qualifiers[2] == AARCH64_OPND_QLF_NIL)
181 return DP_VECTOR_ACROSS_LANES;
182 }
183
184 return DP_UNKNOWN;
185}
186
187/* Select the operand to do the encoding/decoding of the 'size:Q' fields in
188 the AdvSIMD instructions. */
189/* N.B. it is possible to do some optimization that doesn't call
190 get_data_pattern each time when we need to select an operand. We can
191 either buffer the caculated the result or statically generate the data,
192 however, it is not obvious that the optimization will bring significant
193 benefit. */
194
195int
196aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *opcode)
197{
198 return
199 significant_operand_index [get_data_pattern (opcode->qualifiers_list[0])];
200}
201\f
202const aarch64_field fields[] =
203{
204 { 0, 0 }, /* NIL. */
205 { 0, 4 }, /* cond2: condition in truly conditional-executed inst. */
206 { 0, 4 }, /* nzcv: flag bit specifier, encoded in the "nzcv" field. */
207 { 5, 5 }, /* defgh: d:e:f:g:h bits in AdvSIMD modified immediate. */
208 { 16, 3 }, /* abc: a:b:c bits in AdvSIMD modified immediate. */
209 { 5, 19 }, /* imm19: e.g. in CBZ. */
210 { 5, 19 }, /* immhi: e.g. in ADRP. */
211 { 29, 2 }, /* immlo: e.g. in ADRP. */
212 { 22, 2 }, /* size: in most AdvSIMD and floating-point instructions. */
213 { 10, 2 }, /* vldst_size: size field in the AdvSIMD load/store inst. */
214 { 29, 1 }, /* op: in AdvSIMD modified immediate instructions. */
215 { 30, 1 }, /* Q: in most AdvSIMD instructions. */
216 { 0, 5 }, /* Rt: in load/store instructions. */
217 { 0, 5 }, /* Rd: in many integer instructions. */
218 { 5, 5 }, /* Rn: in many integer instructions. */
219 { 10, 5 }, /* Rt2: in load/store pair instructions. */
220 { 10, 5 }, /* Ra: in fp instructions. */
221 { 5, 3 }, /* op2: in the system instructions. */
222 { 8, 4 }, /* CRm: in the system instructions. */
223 { 12, 4 }, /* CRn: in the system instructions. */
224 { 16, 3 }, /* op1: in the system instructions. */
225 { 19, 2 }, /* op0: in the system instructions. */
226 { 10, 3 }, /* imm3: in add/sub extended reg instructions. */
227 { 12, 4 }, /* cond: condition flags as a source operand. */
228 { 12, 4 }, /* opcode: in advsimd load/store instructions. */
229 { 12, 4 }, /* cmode: in advsimd modified immediate instructions. */
230 { 13, 3 }, /* asisdlso_opcode: opcode in advsimd ld/st single element. */
231 { 13, 2 }, /* len: in advsimd tbl/tbx instructions. */
232 { 16, 5 }, /* Rm: in ld/st reg offset and some integer inst. */
233 { 16, 5 }, /* Rs: in load/store exclusive instructions. */
234 { 13, 3 }, /* option: in ld/st reg offset + add/sub extended reg inst. */
235 { 12, 1 }, /* S: in load/store reg offset instructions. */
236 { 21, 2 }, /* hw: in move wide constant instructions. */
237 { 22, 2 }, /* opc: in load/store reg offset instructions. */
238 { 23, 1 }, /* opc1: in load/store reg offset instructions. */
239 { 22, 2 }, /* shift: in add/sub reg/imm shifted instructions. */
240 { 22, 2 }, /* type: floating point type field in fp data inst. */
241 { 30, 2 }, /* ldst_size: size field in ld/st reg offset inst. */
242 { 10, 6 }, /* imm6: in add/sub reg shifted instructions. */
f42f1a1d 243 { 15, 6 }, /* imm6_2: in rmif instructions. */
a06ea964 244 { 11, 4 }, /* imm4: in advsimd ext and advsimd ins instructions. */
f42f1a1d 245 { 0, 4 }, /* imm4_2: in rmif instructions. */
193614f2 246 { 10, 4 }, /* imm4_3: in adddg/subg instructions. */
a06ea964
NC		 247 { 16, 5 }, /* imm5: in conditional compare (immediate) instructions. */
248 { 15, 7 }, /* imm7: in load/store pair pre/post index instructions. */
249 { 13, 8 }, /* imm8: in floating-point scalar move immediate inst. */
250 { 12, 9 }, /* imm9: in load/store pre/post index instructions. */
251 { 10, 12 }, /* imm12: in ld/st unsigned imm or add/sub shifted inst. */
252 { 5, 14 }, /* imm14: in test bit and branch instructions. */
253 { 5, 16 }, /* imm16: in exception instructions. */
254 { 0, 26 }, /* imm26: in unconditional branch instructions. */
255 { 10, 6 }, /* imms: in bitfield and logical immediate instructions. */
256 { 16, 6 }, /* immr: in bitfield and logical immediate instructions. */
257 { 16, 3 }, /* immb: in advsimd shift by immediate instructions. */
258 { 19, 4 }, /* immh: in advsimd shift by immediate instructions. */
3f06e550 259 { 22, 1 }, /* S: in LDRAA and LDRAB instructions. */
a06ea964
NC		 260 { 22, 1 }, /* N: in logical (immediate) instructions. */
261 { 11, 1 }, /* index: in ld/st inst deciding the pre/post-index. */
262 { 24, 1 }, /* index2: in ld/st pair inst deciding the pre/post-index. */
263 { 31, 1 }, /* sf: in integer data processing instructions. */
ee804238 264 { 30, 1 }, /* lse_size: in LSE extension atomic instructions. */
a06ea964
NC		 265 { 11, 1 }, /* H: in advsimd scalar x indexed element instructions. */
266 { 21, 1 }, /* L: in advsimd scalar x indexed element instructions. */
267 { 20, 1 }, /* M: in advsimd scalar x indexed element instructions. */
268 { 31, 1 }, /* b5: in the test bit and branch instructions. */
269 { 19, 5 }, /* b40: in the test bit and branch instructions. */
270 { 10, 6 }, /* scale: in the fixed-point scalar to fp converting inst. */
116b6019
RS		 271 { 4, 1 }, /* SVE_M_4: Merge/zero select, bit 4. */
272 { 14, 1 }, /* SVE_M_14: Merge/zero select, bit 14. */
273 { 16, 1 }, /* SVE_M_16: Merge/zero select, bit 16. */
e950b345 274 { 17, 1 }, /* SVE_N: SVE equivalent of N. */
f11ad6bc
RS		 275 { 0, 4 }, /* SVE_Pd: p0-p15, bits [3,0]. */
276 { 10, 3 }, /* SVE_Pg3: p0-p7, bits [12,10]. */
277 { 5, 4 }, /* SVE_Pg4_5: p0-p15, bits [8,5]. */
278 { 10, 4 }, /* SVE_Pg4_10: p0-p15, bits [13,10]. */
279 { 16, 4 }, /* SVE_Pg4_16: p0-p15, bits [19,16]. */
280 { 16, 4 }, /* SVE_Pm: p0-p15, bits [19,16]. */
281 { 5, 4 }, /* SVE_Pn: p0-p15, bits [8,5]. */
282 { 0, 4 }, /* SVE_Pt: p0-p15, bits [3,0]. */
047cd301
RS		 283 { 5, 5 }, /* SVE_Rm: SVE alternative position for Rm. */
284 { 16, 5 }, /* SVE_Rn: SVE alternative position for Rn. */
285 { 0, 5 }, /* SVE_Vd: Scalar SIMD&FP register, bits [4,0]. */
286 { 5, 5 }, /* SVE_Vm: Scalar SIMD&FP register, bits [9,5]. */
287 { 5, 5 }, /* SVE_Vn: Scalar SIMD&FP register, bits [9,5]. */
f11ad6bc
RS		 288 { 5, 5 }, /* SVE_Za_5: SVE vector register, bits [9,5]. */
289 { 16, 5 }, /* SVE_Za_16: SVE vector register, bits [20,16]. */
290 { 0, 5 }, /* SVE_Zd: SVE vector register. bits [4,0]. */
291 { 5, 5 }, /* SVE_Zm_5: SVE vector register, bits [9,5]. */
292 { 16, 5 }, /* SVE_Zm_16: SVE vector register, bits [20,16]. */
293 { 5, 5 }, /* SVE_Zn: SVE vector register, bits [9,5]. */
294 { 0, 5 }, /* SVE_Zt: SVE vector register, bits [4,0]. */
165d4950 295 { 5, 1 }, /* SVE_i1: single-bit immediate. */
582e12bf 296 { 22, 1 }, /* SVE_i3h: high bit of 3-bit immediate. */
116adc27
MM		 297 { 11, 1 }, /* SVE_i3l: low bit of 3-bit immediate. */
298 { 19, 2 }, /* SVE_i3h2: two high bits of 3bit immediate, bits [20,19]. */
31e36ab3 299 { 20, 1 }, /* SVE_i2h: high bit of 2bit immediate, bits. */
e950b345 300 { 16, 3 }, /* SVE_imm3: 3-bit immediate field. */
2442d846 301 { 16, 4 }, /* SVE_imm4: 4-bit immediate field. */
e950b345
RS		 302 { 5, 5 }, /* SVE_imm5: 5-bit immediate field. */
303 { 16, 5 }, /* SVE_imm5b: secondary 5-bit immediate field. */
4df068de 304 { 16, 6 }, /* SVE_imm6: 6-bit immediate field. */
e950b345
RS		 305 { 14, 7 }, /* SVE_imm7: 7-bit immediate field. */
306 { 5, 8 }, /* SVE_imm8: 8-bit immediate field. */
307 { 5, 9 }, /* SVE_imm9: 9-bit immediate field. */
308 { 11, 6 }, /* SVE_immr: SVE equivalent of immr. */
309 { 5, 6 }, /* SVE_imms: SVE equivalent of imms. */
4df068de 310 { 10, 2 }, /* SVE_msz: 2-bit shift amount for ADR. */
245d2e3f
RS		 311 { 5, 5 }, /* SVE_pattern: vector pattern enumeration. */
312 { 0, 4 }, /* SVE_prfop: prefetch operation for SVE PRF[BHWD]. */
582e12bf
RS		 313 { 16, 1 }, /* SVE_rot1: 1-bit rotation amount. */
314 { 10, 2 }, /* SVE_rot2: 2-bit rotation amount. */
adccc507 315 { 10, 1 }, /* SVE_rot3: 1-bit rotation amount at bit 10. */
116b6019 316 { 22, 1 }, /* SVE_sz: 1-bit element size select. */
3bd82c86 317 { 17, 2 }, /* SVE_size: 2-bit element size, bits [18,17]. */
0a57e14f 318 { 30, 1 }, /* SVE_sz2: 1-bit element size select. */
116b6019 319 { 16, 4 }, /* SVE_tsz: triangular size select. */
f11ad6bc 320 { 22, 2 }, /* SVE_tszh: triangular size select high, bits [23,22]. */
116b6019
RS		 321 { 8, 2 }, /* SVE_tszl_8: triangular size select low, bits [9,8]. */
322 { 19, 2 }, /* SVE_tszl_19: triangular size select low, bits [20,19]. */
4df068de 323 { 14, 1 }, /* SVE_xs_14: UXTW/SXTW select (bit 14). */
c2c4ff8d
SN		 324 { 22, 1 }, /* SVE_xs_22: UXTW/SXTW select (bit 22). */
325 { 11, 2 }, /* rotate1: FCMLA immediate rotate. */
326 { 13, 2 }, /* rotate2: Indexed element FCMLA immediate rotate. */
327 { 12, 1 }, /* rotate3: FCADD immediate rotate. */
f42f1a1d 328 { 12, 2 }, /* SM3: Indexed element SM3 2 bits index immediate. */
6456d318 329 { 22, 1 }, /* sz: 1-bit element size select. */
a06ea964
NC		 330};
331
332enum aarch64_operand_class
333aarch64_get_operand_class (enum aarch64_opnd type)
334{
335 return aarch64_operands[type].op_class;
336}
337
338const char *
339aarch64_get_operand_name (enum aarch64_opnd type)
340{
341 return aarch64_operands[type].name;
342}
343
344/* Get operand description string.
345 This is usually for the diagnosis purpose. */
346const char *
347aarch64_get_operand_desc (enum aarch64_opnd type)
348{
349 return aarch64_operands[type].desc;
350}
351
352/* Table of all conditional affixes. */
353const aarch64_cond aarch64_conds[16] =
354{
bb7eff52
RS		 355 {{"eq", "none"}, 0x0},
356 {{"ne", "any"}, 0x1},
357 {{"cs", "hs", "nlast"}, 0x2},
358 {{"cc", "lo", "ul", "last"}, 0x3},
359 {{"mi", "first"}, 0x4},
360 {{"pl", "nfrst"}, 0x5},
a06ea964
NC		 361 {{"vs"}, 0x6},
362 {{"vc"}, 0x7},
bb7eff52
RS		 363 {{"hi", "pmore"}, 0x8},
364 {{"ls", "plast"}, 0x9},
365 {{"ge", "tcont"}, 0xa},
366 {{"lt", "tstop"}, 0xb},
a06ea964
NC		 367 {{"gt"}, 0xc},
368 {{"le"}, 0xd},
369 {{"al"}, 0xe},
370 {{"nv"}, 0xf},
371};
372
373const aarch64_cond *
374get_cond_from_value (aarch64_insn value)
375{
376 assert (value < 16);
377 return &aarch64_conds[(unsigned int) value];
378}
379
380const aarch64_cond *
381get_inverted_cond (const aarch64_cond *cond)
382{
383 return &aarch64_conds[cond->value ^ 0x1];
384}
385
386/* Table describing the operand extension/shifting operators; indexed by
387 enum aarch64_modifier_kind.
388
389 The value column provides the most common values for encoding modifiers,
390 which enables table-driven encoding/decoding for the modifiers. */
391const struct aarch64_name_value_pair aarch64_operand_modifiers [] =
392{
393 {"none", 0x0},
394 {"msl", 0x0},
395 {"ror", 0x3},
396 {"asr", 0x2},
397 {"lsr", 0x1},
398 {"lsl", 0x0},
399 {"uxtb", 0x0},
400 {"uxth", 0x1},
401 {"uxtw", 0x2},
402 {"uxtx", 0x3},
403 {"sxtb", 0x4},
404 {"sxth", 0x5},
405 {"sxtw", 0x6},
406 {"sxtx", 0x7},
2442d846 407 {"mul", 0x0},
98907a70 408 {"mul vl", 0x0},
a06ea964
NC		 409 {NULL, 0},
410};
411
412enum aarch64_modifier_kind
413aarch64_get_operand_modifier (const struct aarch64_name_value_pair *desc)
414{
415 return desc - aarch64_operand_modifiers;
416}
417
418aarch64_insn
419aarch64_get_operand_modifier_value (enum aarch64_modifier_kind kind)
420{
421 return aarch64_operand_modifiers[kind].value;
422}
423
424enum aarch64_modifier_kind
425aarch64_get_operand_modifier_from_value (aarch64_insn value,
426 bfd_boolean extend_p)
427{
428 if (extend_p == TRUE)
429 return AARCH64_MOD_UXTB + value;
430 else
431 return AARCH64_MOD_LSL - value;
432}
433
434bfd_boolean
435aarch64_extend_operator_p (enum aarch64_modifier_kind kind)
436{
437 return (kind > AARCH64_MOD_LSL && kind <= AARCH64_MOD_SXTX)
438 ? TRUE : FALSE;
439}
440
441static inline bfd_boolean
442aarch64_shift_operator_p (enum aarch64_modifier_kind kind)
443{
444 return (kind >= AARCH64_MOD_ROR && kind <= AARCH64_MOD_LSL)
445 ? TRUE : FALSE;
446}
447
448const struct aarch64_name_value_pair aarch64_barrier_options[16] =
449{
450 { "#0x00", 0x0 },
451 { "oshld", 0x1 },
452 { "oshst", 0x2 },
453 { "osh", 0x3 },
454 { "#0x04", 0x4 },
455 { "nshld", 0x5 },
456 { "nshst", 0x6 },
457 { "nsh", 0x7 },
458 { "#0x08", 0x8 },
459 { "ishld", 0x9 },
460 { "ishst", 0xa },
461 { "ish", 0xb },
462 { "#0x0c", 0xc },
463 { "ld", 0xd },
464 { "st", 0xe },
465 { "sy", 0xf },
466};
467
9ed608f9
MW		 468/* Table describing the operands supported by the aliases of the HINT
469 instruction.
470
471 The name column is the operand that is accepted for the alias. The value
472 column is the hint number of the alias. The list of operands is terminated
473 by NULL in the name column. */
474
475const struct aarch64_name_value_pair aarch64_hint_options[] =
476{
ff605452
SD		 477 /* BTI. This is also the F_DEFAULT entry for AARCH64_OPND_BTI_TARGET. */
478 { " ", HINT_ENCODE (HINT_OPD_F_NOPRINT, 0x20) },
479 { "csync", HINT_OPD_CSYNC }, /* PSB CSYNC. */
480 { "c", HINT_OPD_C }, /* BTI C. */
481 { "j", HINT_OPD_J }, /* BTI J. */
482 { "jc", HINT_OPD_JC }, /* BTI JC. */
483 { NULL, HINT_OPD_NULL },
9ed608f9
MW		 484};
485
a32c3ff8 486/* op -> op: load = 0 instruction = 1 store = 2
a06ea964
NC		 487 l -> level: 1-3
488 t -> temporal: temporal (retained) = 0 non-temporal (streaming) = 1 */
a32c3ff8 489#define B(op,l,t) (((op) << 3) | (((l) - 1) << 1) | (t))
a06ea964
NC		 490const struct aarch64_name_value_pair aarch64_prfops[32] =
491{
492 { "pldl1keep", B(0, 1, 0) },
493 { "pldl1strm", B(0, 1, 1) },
494 { "pldl2keep", B(0, 2, 0) },
495 { "pldl2strm", B(0, 2, 1) },
496 { "pldl3keep", B(0, 3, 0) },
497 { "pldl3strm", B(0, 3, 1) },
a1ccaec9
YZ		 498 { NULL, 0x06 },
499 { NULL, 0x07 },
a32c3ff8
NC		 500 { "plil1keep", B(1, 1, 0) },
501 { "plil1strm", B(1, 1, 1) },
502 { "plil2keep", B(1, 2, 0) },
503 { "plil2strm", B(1, 2, 1) },
504 { "plil3keep", B(1, 3, 0) },
505 { "plil3strm", B(1, 3, 1) },
a1ccaec9
YZ		 506 { NULL, 0x0e },
507 { NULL, 0x0f },
a32c3ff8
NC		 508 { "pstl1keep", B(2, 1, 0) },
509 { "pstl1strm", B(2, 1, 1) },
510 { "pstl2keep", B(2, 2, 0) },
511 { "pstl2strm", B(2, 2, 1) },
512 { "pstl3keep", B(2, 3, 0) },
513 { "pstl3strm", B(2, 3, 1) },
a1ccaec9
YZ		 514 { NULL, 0x16 },
515 { NULL, 0x17 },
516 { NULL, 0x18 },
517 { NULL, 0x19 },
518 { NULL, 0x1a },
519 { NULL, 0x1b },
520 { NULL, 0x1c },
521 { NULL, 0x1d },
522 { NULL, 0x1e },
523 { NULL, 0x1f },
a06ea964
NC		 524};
525#undef B
526\f
527/* Utilities on value constraint. */
528
529static inline int
530value_in_range_p (int64_t value, int low, int high)
531{
532 return (value >= low && value <= high) ? 1 : 0;
533}
534
98907a70 535/* Return true if VALUE is a multiple of ALIGN. */
a06ea964
NC		 536static inline int
537value_aligned_p (int64_t value, int align)
538{
98907a70 539 return (value % align) == 0;
a06ea964
NC		 540}
541
542/* A signed value fits in a field. */
543static inline int
544value_fit_signed_field_p (int64_t value, unsigned width)
545{
546 assert (width < 32);
547 if (width < sizeof (value) * 8)
548 {
549 int64_t lim = (int64_t)1 << (width - 1);
550 if (value >= -lim && value < lim)
551 return 1;
552 }
553 return 0;
554}
555
556/* An unsigned value fits in a field. */
557static inline int
558value_fit_unsigned_field_p (int64_t value, unsigned width)
559{
560 assert (width < 32);
561 if (width < sizeof (value) * 8)
562 {
563 int64_t lim = (int64_t)1 << width;
564 if (value >= 0 && value < lim)
565 return 1;
566 }
567 return 0;
568}
569
570/* Return 1 if OPERAND is SP or WSP. */
571int
572aarch64_stack_pointer_p (const aarch64_opnd_info *operand)
573{
574 return ((aarch64_get_operand_class (operand->type)
575 == AARCH64_OPND_CLASS_INT_REG)
576 && operand_maybe_stack_pointer (aarch64_operands + operand->type)
577 && operand->reg.regno == 31);
578}
579
580/* Return 1 if OPERAND is XZR or WZP. */
581int
582aarch64_zero_register_p (const aarch64_opnd_info *operand)
583{
584 return ((aarch64_get_operand_class (operand->type)
585 == AARCH64_OPND_CLASS_INT_REG)
586 && !operand_maybe_stack_pointer (aarch64_operands + operand->type)
587 && operand->reg.regno == 31);
588}
589
590/* Return true if the operand *OPERAND that has the operand code
591 OPERAND->TYPE and been qualified by OPERAND->QUALIFIER can be also
592 qualified by the qualifier TARGET. */
593
594static inline int
595operand_also_qualified_p (const struct aarch64_opnd_info *operand,
596 aarch64_opnd_qualifier_t target)
597{
598 switch (operand->qualifier)
599 {
600 case AARCH64_OPND_QLF_W:
601 if (target == AARCH64_OPND_QLF_WSP && aarch64_stack_pointer_p (operand))
602 return 1;
603 break;
604 case AARCH64_OPND_QLF_X:
605 if (target == AARCH64_OPND_QLF_SP && aarch64_stack_pointer_p (operand))
606 return 1;
607 break;
608 case AARCH64_OPND_QLF_WSP:
609 if (target == AARCH64_OPND_QLF_W
610 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
611 return 1;
612 break;
613 case AARCH64_OPND_QLF_SP:
614 if (target == AARCH64_OPND_QLF_X
615 && operand_maybe_stack_pointer (aarch64_operands + operand->type))
616 return 1;
617 break;
618 default:
619 break;
620 }
621
622 return 0;
623}
624
625/* Given qualifier sequence list QSEQ_LIST and the known qualifier KNOWN_QLF
626 for operand KNOWN_IDX, return the expected qualifier for operand IDX.
627
628 Return NIL if more than one expected qualifiers are found. */
629
630aarch64_opnd_qualifier_t
631aarch64_get_expected_qualifier (const aarch64_opnd_qualifier_seq_t *qseq_list,
632 int idx,
633 const aarch64_opnd_qualifier_t known_qlf,
634 int known_idx)
635{
636 int i, saved_i;
637
638 /* Special case.
639
640 When the known qualifier is NIL, we have to assume that there is only
641 one qualifier sequence in the *QSEQ_LIST and return the corresponding
642 qualifier directly. One scenario is that for instruction
643 PRFM <prfop>, [<Xn|SP>, #:lo12:<symbol>]
644 which has only one possible valid qualifier sequence
645 NIL, S_D
646 the caller may pass NIL in KNOWN_QLF to obtain S_D so that it can
647 determine the correct relocation type (i.e. LDST64_LO12) for PRFM.
648
649 Because the qualifier NIL has dual roles in the qualifier sequence:
650 it can mean no qualifier for the operand, or the qualifer sequence is
651 not in use (when all qualifiers in the sequence are NILs), we have to
652 handle this special case here. */
653 if (known_qlf == AARCH64_OPND_NIL)
654 {
655 assert (qseq_list[0][known_idx] == AARCH64_OPND_NIL);
656 return qseq_list[0][idx];
657 }
658
659 for (i = 0, saved_i = -1; i < AARCH64_MAX_QLF_SEQ_NUM; ++i)
660 {
661 if (qseq_list[i][known_idx] == known_qlf)
662 {
663 if (saved_i != -1)
664 /* More than one sequences are found to have KNOWN_QLF at
665 KNOWN_IDX. */
666 return AARCH64_OPND_NIL;
667 saved_i = i;
668 }
669 }
670
671 return qseq_list[saved_i][idx];
672}
673
674enum operand_qualifier_kind
675{
676 OQK_NIL,
677 OQK_OPD_VARIANT,
678 OQK_VALUE_IN_RANGE,
679 OQK_MISC,
680};
681
682/* Operand qualifier description. */
683struct operand_qualifier_data
684{
685 /* The usage of the three data fields depends on the qualifier kind. */
686 int data0;
687 int data1;
688 int data2;
689 /* Description. */
690 const char *desc;
691 /* Kind. */
692 enum operand_qualifier_kind kind;
693};
694
695/* Indexed by the operand qualifier enumerators. */
696struct operand_qualifier_data aarch64_opnd_qualifiers[] =
697{
698 {0, 0, 0, "NIL", OQK_NIL},
699
700 /* Operand variant qualifiers.
701 First 3 fields:
702 element size, number of elements and common value for encoding. */
703
704 {4, 1, 0x0, "w", OQK_OPD_VARIANT},
705 {8, 1, 0x1, "x", OQK_OPD_VARIANT},
706 {4, 1, 0x0, "wsp", OQK_OPD_VARIANT},
707 {8, 1, 0x1, "sp", OQK_OPD_VARIANT},
708
709 {1, 1, 0x0, "b", OQK_OPD_VARIANT},
710 {2, 1, 0x1, "h", OQK_OPD_VARIANT},
711 {4, 1, 0x2, "s", OQK_OPD_VARIANT},
712 {8, 1, 0x3, "d", OQK_OPD_VARIANT},
713 {16, 1, 0x4, "q", OQK_OPD_VARIANT},
66e6f0b7 714 {4, 1, 0x0, "4b", OQK_OPD_VARIANT},
df678013 715 {4, 1, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964 716
a3b3345a 717 {1, 4, 0x0, "4b", OQK_OPD_VARIANT},
a06ea964
NC		 718 {1, 8, 0x0, "8b", OQK_OPD_VARIANT},
719 {1, 16, 0x1, "16b", OQK_OPD_VARIANT},
3067d3b9 720 {2, 2, 0x0, "2h", OQK_OPD_VARIANT},
a06ea964
NC		 721 {2, 4, 0x2, "4h", OQK_OPD_VARIANT},
722 {2, 8, 0x3, "8h", OQK_OPD_VARIANT},
723 {4, 2, 0x4, "2s", OQK_OPD_VARIANT},
724 {4, 4, 0x5, "4s", OQK_OPD_VARIANT},
725 {8, 1, 0x6, "1d", OQK_OPD_VARIANT},
726 {8, 2, 0x7, "2d", OQK_OPD_VARIANT},
727 {16, 1, 0x8, "1q", OQK_OPD_VARIANT},
728
d50c751e
RS		 729 {0, 0, 0, "z", OQK_OPD_VARIANT},
730 {0, 0, 0, "m", OQK_OPD_VARIANT},
731
fb3265b3
SD		 732 /* Qualifier for scaled immediate for Tag granule (stg,st2g,etc). */
733 {16, 0, 0, "tag", OQK_OPD_VARIANT},
734
a06ea964
NC		 735 /* Qualifiers constraining the value range.
736 First 3 fields:
737 Lower bound, higher bound, unused. */
738
a6a51754 739 {0, 15, 0, "CR", OQK_VALUE_IN_RANGE},
a06ea964
NC		 740 {0, 7, 0, "imm_0_7" , OQK_VALUE_IN_RANGE},
741 {0, 15, 0, "imm_0_15", OQK_VALUE_IN_RANGE},
742 {0, 31, 0, "imm_0_31", OQK_VALUE_IN_RANGE},
743 {0, 63, 0, "imm_0_63", OQK_VALUE_IN_RANGE},
744 {1, 32, 0, "imm_1_32", OQK_VALUE_IN_RANGE},
745 {1, 64, 0, "imm_1_64", OQK_VALUE_IN_RANGE},
746
747 /* Qualifiers for miscellaneous purpose.
748 First 3 fields:
749 unused, unused and unused. */
750
751 {0, 0, 0, "lsl", 0},
752 {0, 0, 0, "msl", 0},
753
754 {0, 0, 0, "retrieving", 0},
755};
756
757static inline bfd_boolean
758operand_variant_qualifier_p (aarch64_opnd_qualifier_t qualifier)
759{
760 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_OPD_VARIANT)
761 ? TRUE : FALSE;
762}
763
764static inline bfd_boolean
765qualifier_value_in_range_constraint_p (aarch64_opnd_qualifier_t qualifier)
766{
767 return (aarch64_opnd_qualifiers[qualifier].kind == OQK_VALUE_IN_RANGE)
768 ? TRUE : FALSE;
769}
770
771const char*
772aarch64_get_qualifier_name (aarch64_opnd_qualifier_t qualifier)
773{
774 return aarch64_opnd_qualifiers[qualifier].desc;
775}
776
777/* Given an operand qualifier, return the expected data element size
778 of a qualified operand. */
779unsigned char
780aarch64_get_qualifier_esize (aarch64_opnd_qualifier_t qualifier)
781{
782 assert (operand_variant_qualifier_p (qualifier) == TRUE);
783 return aarch64_opnd_qualifiers[qualifier].data0;
784}
785
786unsigned char
787aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t qualifier)
788{
789 assert (operand_variant_qualifier_p (qualifier) == TRUE);
790 return aarch64_opnd_qualifiers[qualifier].data1;
791}
792
793aarch64_insn
794aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t qualifier)
795{
796 assert (operand_variant_qualifier_p (qualifier) == TRUE);
797 return aarch64_opnd_qualifiers[qualifier].data2;
798}
799
800static int
801get_lower_bound (aarch64_opnd_qualifier_t qualifier)
802{
803 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
804 return aarch64_opnd_qualifiers[qualifier].data0;
805}
806
807static int
808get_upper_bound (aarch64_opnd_qualifier_t qualifier)
809{
810 assert (qualifier_value_in_range_constraint_p (qualifier) == TRUE);
811 return aarch64_opnd_qualifiers[qualifier].data1;
812}
813
814#ifdef DEBUG_AARCH64
815void
816aarch64_verbose (const char *str, ...)
817{
818 va_list ap;
819 va_start (ap, str);
820 printf ("#### ");
821 vprintf (str, ap);
822 printf ("\n");
823 va_end (ap);
824}
825
826static inline void
827dump_qualifier_sequence (const aarch64_opnd_qualifier_t *qualifier)
828{
829 int i;
830 printf ("#### \t");
831 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i, ++qualifier)
832 printf ("%s,", aarch64_get_qualifier_name (*qualifier));
833 printf ("\n");
834}
835
836static void
837dump_match_qualifiers (const struct aarch64_opnd_info *opnd,
838 const aarch64_opnd_qualifier_t *qualifier)
839{
840 int i;
841 aarch64_opnd_qualifier_t curr[AARCH64_MAX_OPND_NUM];
842
843 aarch64_verbose ("dump_match_qualifiers:");
844 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
845 curr[i] = opnd[i].qualifier;
846 dump_qualifier_sequence (curr);
847 aarch64_verbose ("against");
848 dump_qualifier_sequence (qualifier);
849}
850#endif /* DEBUG_AARCH64 */
851
a68f4cd2
TC		 852/* This function checks if the given instruction INSN is a destructive
853 instruction based on the usage of the registers. It does not recognize
854 unary destructive instructions. */
855bfd_boolean
856aarch64_is_destructive_by_operands (const aarch64_opcode *opcode)
857{
858 int i = 0;
859 const enum aarch64_opnd *opnds = opcode->operands;
860
861 if (opnds[0] == AARCH64_OPND_NIL)
862 return FALSE;
863
864 while (opnds[++i] != AARCH64_OPND_NIL)
865 if (opnds[i] == opnds[0])
866 return TRUE;
867
868 return FALSE;
869}
870
a06ea964
NC		 871/* TODO improve this, we can have an extra field at the runtime to
872 store the number of operands rather than calculating it every time. */
873
874int
875aarch64_num_of_operands (const aarch64_opcode *opcode)
876{
877 int i = 0;
878 const enum aarch64_opnd *opnds = opcode->operands;
879 while (opnds[i++] != AARCH64_OPND_NIL)
880 ;
881 --i;
882 assert (i >= 0 && i <= AARCH64_MAX_OPND_NUM);
883 return i;
884}
885
886/* Find the best matched qualifier sequence in *QUALIFIERS_LIST for INST.
887 If succeeds, fill the found sequence in *RET, return 1; otherwise return 0.
888
889 N.B. on the entry, it is very likely that only some operands in *INST
890 have had their qualifiers been established.
891
892 If STOP_AT is not -1, the function will only try to match
893 the qualifier sequence for operands before and including the operand
894 of index STOP_AT; and on success *RET will only be filled with the first
895 (STOP_AT+1) qualifiers.
896
897 A couple examples of the matching algorithm:
898
899 X,W,NIL should match
900 X,W,NIL
901
902 NIL,NIL should match
903 X ,NIL
904
905 Apart from serving the main encoding routine, this can also be called
906 during or after the operand decoding. */
907
908int
909aarch64_find_best_match (const aarch64_inst *inst,
910 const aarch64_opnd_qualifier_seq_t *qualifiers_list,
911 int stop_at, aarch64_opnd_qualifier_t *ret)
912{
913 int found = 0;
914 int i, num_opnds;
915 const aarch64_opnd_qualifier_t *qualifiers;
916
917 num_opnds = aarch64_num_of_operands (inst->opcode);
918 if (num_opnds == 0)
919 {
920 DEBUG_TRACE ("SUCCEED: no operand");
921 return 1;
922 }
923
924 if (stop_at < 0 || stop_at >= num_opnds)
925 stop_at = num_opnds - 1;
926
927 /* For each pattern. */
928 for (i = 0; i < AARCH64_MAX_QLF_SEQ_NUM; ++i, ++qualifiers_list)
929 {
930 int j;
931 qualifiers = *qualifiers_list;
932
933 /* Start as positive. */
934 found = 1;
935
936 DEBUG_TRACE ("%d", i);
937#ifdef DEBUG_AARCH64
938 if (debug_dump)
939 dump_match_qualifiers (inst->operands, qualifiers);
940#endif
941
942 /* Most opcodes has much fewer patterns in the list.
943 First NIL qualifier indicates the end in the list. */
944 if (empty_qualifier_sequence_p (qualifiers) == TRUE)
945 {
946 DEBUG_TRACE_IF (i == 0, "SUCCEED: empty qualifier list");
947 if (i)
948 found = 0;
949 break;
950 }
951
952 for (j = 0; j < num_opnds && j <= stop_at; ++j, ++qualifiers)
953 {
954 if (inst->operands[j].qualifier == AARCH64_OPND_QLF_NIL)
955 {
956 /* Either the operand does not have qualifier, or the qualifier
957 for the operand needs to be deduced from the qualifier
958 sequence.
959 In the latter case, any constraint checking related with
960 the obtained qualifier should be done later in
961 operand_general_constraint_met_p. */
962 continue;
963 }
964 else if (*qualifiers != inst->operands[j].qualifier)
965 {
966 /* Unless the target qualifier can also qualify the operand
967 (which has already had a non-nil qualifier), non-equal
968 qualifiers are generally un-matched. */
969 if (operand_also_qualified_p (inst->operands + j, *qualifiers))
970 continue;
971 else
972 {
973 found = 0;
974 break;
975 }
976 }
977 else
978 continue; /* Equal qualifiers are certainly matched. */
979 }
980
981 /* Qualifiers established. */
982 if (found == 1)
983 break;
984 }
985
986 if (found == 1)
987 {
988 /* Fill the result in *RET. */
989 int j;
990 qualifiers = *qualifiers_list;
991
992 DEBUG_TRACE ("complete qualifiers using list %d", i);
993#ifdef DEBUG_AARCH64
994 if (debug_dump)
995 dump_qualifier_sequence (qualifiers);
996#endif
997
998 for (j = 0; j <= stop_at; ++j, ++qualifiers)
999 ret[j] = *qualifiers;
1000 for (; j < AARCH64_MAX_OPND_NUM; ++j)
1001 ret[j] = AARCH64_OPND_QLF_NIL;
1002
1003 DEBUG_TRACE ("SUCCESS");
1004 return 1;
1005 }
1006
1007 DEBUG_TRACE ("FAIL");
1008 return 0;
1009}
1010
1011/* Operand qualifier matching and resolving.
1012
1013 Return 1 if the operand qualifier(s) in *INST match one of the qualifier
1014 sequences in INST->OPCODE->qualifiers_list; otherwise return 0.
1015
1016 if UPDATE_P == TRUE, update the qualifier(s) in *INST after the matching
1017 succeeds. */
1018
1019static int
1020match_operands_qualifier (aarch64_inst *inst, bfd_boolean update_p)
1021{
4989adac 1022 int i, nops;
a06ea964
NC		 1023 aarch64_opnd_qualifier_seq_t qualifiers;
1024
1025 if (!aarch64_find_best_match (inst, inst->opcode->qualifiers_list, -1,
1026 qualifiers))
1027 {
1028 DEBUG_TRACE ("matching FAIL");
1029 return 0;
1030 }
1031
4989adac
RS		 1032 if (inst->opcode->flags & F_STRICT)
1033 {
1034 /* Require an exact qualifier match, even for NIL qualifiers. */
1035 nops = aarch64_num_of_operands (inst->opcode);
1036 for (i = 0; i < nops; ++i)
1037 if (inst->operands[i].qualifier != qualifiers[i])
1038 return FALSE;
1039 }
1040
a06ea964
NC		 1041 /* Update the qualifiers. */
1042 if (update_p == TRUE)
1043 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
1044 {
1045 if (inst->opcode->operands[i] == AARCH64_OPND_NIL)
1046 break;
1047 DEBUG_TRACE_IF (inst->operands[i].qualifier != qualifiers[i],
1048 "update %s with %s for operand %d",
1049 aarch64_get_qualifier_name (inst->operands[i].qualifier),
1050 aarch64_get_qualifier_name (qualifiers[i]), i);
1051 inst->operands[i].qualifier = qualifiers[i];
1052 }
1053
1054 DEBUG_TRACE ("matching SUCCESS");
1055 return 1;
1056}
1057
1058/* Return TRUE if VALUE is a wide constant that can be moved into a general
1059 register by MOVZ.
1060
1061 IS32 indicates whether value is a 32-bit immediate or not.
1062 If SHIFT_AMOUNT is not NULL, on the return of TRUE, the logical left shift
1063 amount will be returned in *SHIFT_AMOUNT. */
1064
1065bfd_boolean
1066aarch64_wide_constant_p (int64_t value, int is32, unsigned int *shift_amount)
1067{
1068 int amount;
1069
1070 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1071
1072 if (is32)
1073 {
1074 /* Allow all zeros or all ones in top 32-bits, so that
1075 32-bit constant expressions like ~0x80000000 are
1076 permitted. */
1077 uint64_t ext = value;
1078 if (ext >> 32 != 0 && ext >> 32 != (uint64_t) 0xffffffff)
1079 /* Immediate out of range. */
1080 return FALSE;
1081 value &= (int64_t) 0xffffffff;
1082 }
1083
1084 /* first, try movz then movn */
1085 amount = -1;
1086 if ((value & ((int64_t) 0xffff << 0)) == value)
1087 amount = 0;
1088 else if ((value & ((int64_t) 0xffff << 16)) == value)
1089 amount = 16;
1090 else if (!is32 && (value & ((int64_t) 0xffff << 32)) == value)
1091 amount = 32;
1092 else if (!is32 && (value & ((int64_t) 0xffff << 48)) == value)
1093 amount = 48;
1094
1095 if (amount == -1)
1096 {
1097 DEBUG_TRACE ("exit FALSE with 0x%" PRIx64 "(%" PRIi64 ")", value, value);
1098 return FALSE;
1099 }
1100
1101 if (shift_amount != NULL)
1102 *shift_amount = amount;
1103
1104 DEBUG_TRACE ("exit TRUE with amount %d", amount);
1105
1106 return TRUE;
1107}
1108
1109/* Build the accepted values for immediate logical SIMD instructions.
1110
1111 The standard encodings of the immediate value are:
1112 N imms immr SIMD size R S
1113 1 ssssss rrrrrr 64 UInt(rrrrrr) UInt(ssssss)
1114 0 0sssss 0rrrrr 32 UInt(rrrrr) UInt(sssss)
1115 0 10ssss 00rrrr 16 UInt(rrrr) UInt(ssss)
1116 0 110sss 000rrr 8 UInt(rrr) UInt(sss)
1117 0 1110ss 0000rr 4 UInt(rr) UInt(ss)
1118 0 11110s 00000r 2 UInt(r) UInt(s)
1119 where all-ones value of S is reserved.
1120
1121 Let's call E the SIMD size.
1122
1123 The immediate value is: S+1 bits '1' rotated to the right by R.
1124
1125 The total of valid encodings is 64*63 + 32*31 + ... + 2*1 = 5334
1126 (remember S != E - 1). */
1127
1128#define TOTAL_IMM_NB 5334
1129
1130typedef struct
1131{
1132 uint64_t imm;
1133 aarch64_insn encoding;
1134} simd_imm_encoding;
1135
1136static simd_imm_encoding simd_immediates[TOTAL_IMM_NB];
1137
1138static int
1139simd_imm_encoding_cmp(const void *i1, const void *i2)
1140{
1141 const simd_imm_encoding *imm1 = (const simd_imm_encoding *)i1;
1142 const simd_imm_encoding *imm2 = (const simd_imm_encoding *)i2;
1143
1144 if (imm1->imm < imm2->imm)
1145 return -1;
1146 if (imm1->imm > imm2->imm)
1147 return +1;
1148 return 0;
1149}
1150
1151/* immediate bitfield standard encoding
1152 imm13<12> imm13<5:0> imm13<11:6> SIMD size R S
1153 1 ssssss rrrrrr 64 rrrrrr ssssss
1154 0 0sssss 0rrrrr 32 rrrrr sssss
1155 0 10ssss 00rrrr 16 rrrr ssss
1156 0 110sss 000rrr 8 rrr sss
1157 0 1110ss 0000rr 4 rr ss
1158 0 11110s 00000r 2 r s */
1159static inline int
1160encode_immediate_bitfield (int is64, uint32_t s, uint32_t r)
1161{
1162 return (is64 << 12) | (r << 6) | s;
1163}
1164
1165static void
1166build_immediate_table (void)
1167{
1168 uint32_t log_e, e, s, r, s_mask;
1169 uint64_t mask, imm;
1170 int nb_imms;
1171 int is64;
1172
1173 nb_imms = 0;
1174 for (log_e = 1; log_e <= 6; log_e++)
1175 {
1176 /* Get element size. */
1177 e = 1u << log_e;
1178 if (log_e == 6)
1179 {
1180 is64 = 1;
1181 mask = 0xffffffffffffffffull;
1182 s_mask = 0;
1183 }
1184 else
1185 {
1186 is64 = 0;
1187 mask = (1ull << e) - 1;
1188 /* log_e s_mask
1189 1 ((1 << 4) - 1) << 2 = 111100
1190 2 ((1 << 3) - 1) << 3 = 111000
1191 3 ((1 << 2) - 1) << 4 = 110000
1192 4 ((1 << 1) - 1) << 5 = 100000
1193 5 ((1 << 0) - 1) << 6 = 000000 */
1194 s_mask = ((1u << (5 - log_e)) - 1) << (log_e + 1);
1195 }
1196 for (s = 0; s < e - 1; s++)
1197 for (r = 0; r < e; r++)
1198 {
1199 /* s+1 consecutive bits to 1 (s < 63) */
1200 imm = (1ull << (s + 1)) - 1;
1201 /* rotate right by r */
1202 if (r != 0)
1203 imm = (imm >> r) | ((imm << (e - r)) & mask);
1204 /* replicate the constant depending on SIMD size */
1205 switch (log_e)
1206 {
1207 case 1: imm = (imm << 2) | imm;
1a0670f3 1208 /* Fall through. */
a06ea964 1209 case 2: imm = (imm << 4) | imm;
1a0670f3 1210 /* Fall through. */
a06ea964 1211 case 3: imm = (imm << 8) | imm;
1a0670f3 1212 /* Fall through. */
a06ea964 1213 case 4: imm = (imm << 16) | imm;
1a0670f3 1214 /* Fall through. */
a06ea964 1215 case 5: imm = (imm << 32) | imm;
1a0670f3 1216 /* Fall through. */
a06ea964
NC		 1217 case 6: break;
1218 default: abort ();
1219 }
1220 simd_immediates[nb_imms].imm = imm;
1221 simd_immediates[nb_imms].encoding =
1222 encode_immediate_bitfield(is64, s | s_mask, r);
1223 nb_imms++;
1224 }
1225 }
1226 assert (nb_imms == TOTAL_IMM_NB);
1227 qsort(simd_immediates, nb_imms,
1228 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1229}
1230
1231/* Return TRUE if VALUE is a valid logical immediate, i.e. bitmask, that can
1232 be accepted by logical (immediate) instructions
1233 e.g. ORR <Xd|SP>, <Xn>, #<imm>.
1234
42408347 1235 ESIZE is the number of bytes in the decoded immediate value.
a06ea964
NC		 1236 If ENCODING is not NULL, on the return of TRUE, the standard encoding for
1237 VALUE will be returned in *ENCODING. */
1238
1239bfd_boolean
42408347 1240aarch64_logical_immediate_p (uint64_t value, int esize, aarch64_insn *encoding)
a06ea964
NC		 1241{
1242 simd_imm_encoding imm_enc;
1243 const simd_imm_encoding *imm_encoding;
1244 static bfd_boolean initialized = FALSE;
42408347
RS		 1245 uint64_t upper;
1246 int i;
a06ea964 1247
957f6b39
TC		 1248 DEBUG_TRACE ("enter with 0x%" PRIx64 "(%" PRIi64 "), esize: %d", value,
1249 value, esize);
a06ea964 1250
535b785f 1251 if (!initialized)
a06ea964
NC		 1252 {
1253 build_immediate_table ();
1254 initialized = TRUE;
1255 }
1256
42408347
RS		 1257 /* Allow all zeros or all ones in top bits, so that
1258 constant expressions like ~1 are permitted. */
1259 upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
1260 if ((value & ~upper) != value && (value | upper) != value)
1261 return FALSE;
7e105031 1262
42408347
RS		 1263 /* Replicate to a full 64-bit value. */
1264 value &= ~upper;
1265 for (i = esize * 8; i < 64; i *= 2)
1266 value |= (value << i);
a06ea964
NC		 1267
1268 imm_enc.imm = value;
1269 imm_encoding = (const simd_imm_encoding *)
1270 bsearch(&imm_enc, simd_immediates, TOTAL_IMM_NB,
1271 sizeof(simd_immediates[0]), simd_imm_encoding_cmp);
1272 if (imm_encoding == NULL)
1273 {
1274 DEBUG_TRACE ("exit with FALSE");
1275 return FALSE;
1276 }
1277 if (encoding != NULL)
1278 *encoding = imm_encoding->encoding;
1279 DEBUG_TRACE ("exit with TRUE");
1280 return TRUE;
1281}
1282
1283/* If 64-bit immediate IMM is in the format of
1284 "aaaaaaaabbbbbbbbccccccccddddddddeeeeeeeeffffffffgggggggghhhhhhhh",
1285 where a, b, c, d, e, f, g and h are independently 0 or 1, return an integer
1286 of value "abcdefgh". Otherwise return -1. */
1287int
1288aarch64_shrink_expanded_imm8 (uint64_t imm)
1289{
1290 int i, ret;
1291 uint32_t byte;
1292
1293 ret = 0;
1294 for (i = 0; i < 8; i++)
1295 {
1296 byte = (imm >> (8 * i)) & 0xff;
1297 if (byte == 0xff)
1298 ret |= 1 << i;
1299 else if (byte != 0x00)
1300 return -1;
1301 }
1302 return ret;
1303}
1304
1305/* Utility inline functions for operand_general_constraint_met_p. */
1306
1307static inline void
1308set_error (aarch64_operand_error *mismatch_detail,
1309 enum aarch64_operand_error_kind kind, int idx,
1310 const char* error)
1311{
1312 if (mismatch_detail == NULL)
1313 return;
1314 mismatch_detail->kind = kind;
1315 mismatch_detail->index = idx;
1316 mismatch_detail->error = error;
1317}
1318
4e50d5f8
YZ		 1319static inline void
1320set_syntax_error (aarch64_operand_error *mismatch_detail, int idx,
1321 const char* error)
1322{
1323 if (mismatch_detail == NULL)
1324 return;
1325 set_error (mismatch_detail, AARCH64_OPDE_SYNTAX_ERROR, idx, error);
1326}
1327
a06ea964
NC		 1328static inline void
1329set_out_of_range_error (aarch64_operand_error *mismatch_detail,
1330 int idx, int lower_bound, int upper_bound,
1331 const char* error)
1332{
1333 if (mismatch_detail == NULL)
1334 return;
1335 set_error (mismatch_detail, AARCH64_OPDE_OUT_OF_RANGE, idx, error);
1336 mismatch_detail->data[0] = lower_bound;
1337 mismatch_detail->data[1] = upper_bound;
1338}
1339
1340static inline void
1341set_imm_out_of_range_error (aarch64_operand_error *mismatch_detail,
1342 int idx, int lower_bound, int upper_bound)
1343{
1344 if (mismatch_detail == NULL)
1345 return;
1346 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1347 _("immediate value"));
1348}
1349
1350static inline void
1351set_offset_out_of_range_error (aarch64_operand_error *mismatch_detail,
1352 int idx, int lower_bound, int upper_bound)
1353{
1354 if (mismatch_detail == NULL)
1355 return;
1356 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1357 _("immediate offset"));
1358}
1359
1360static inline void
1361set_regno_out_of_range_error (aarch64_operand_error *mismatch_detail,
1362 int idx, int lower_bound, int upper_bound)
1363{
1364 if (mismatch_detail == NULL)
1365 return;
1366 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1367 _("register number"));
1368}
1369
1370static inline void
1371set_elem_idx_out_of_range_error (aarch64_operand_error *mismatch_detail,
1372 int idx, int lower_bound, int upper_bound)
1373{
1374 if (mismatch_detail == NULL)
1375 return;
1376 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1377 _("register element index"));
1378}
1379
1380static inline void
1381set_sft_amount_out_of_range_error (aarch64_operand_error *mismatch_detail,
1382 int idx, int lower_bound, int upper_bound)
1383{
1384 if (mismatch_detail == NULL)
1385 return;
1386 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1387 _("shift amount"));
1388}
1389
2442d846
RS		 1390/* Report that the MUL modifier in operand IDX should be in the range
1391 [LOWER_BOUND, UPPER_BOUND]. */
1392static inline void
1393set_multiplier_out_of_range_error (aarch64_operand_error *mismatch_detail,
1394 int idx, int lower_bound, int upper_bound)
1395{
1396 if (mismatch_detail == NULL)
1397 return;
1398 set_out_of_range_error (mismatch_detail, idx, lower_bound, upper_bound,
1399 _("multiplier"));
1400}
1401
a06ea964
NC		 1402static inline void
1403set_unaligned_error (aarch64_operand_error *mismatch_detail, int idx,
1404 int alignment)
1405{
1406 if (mismatch_detail == NULL)
1407 return;
1408 set_error (mismatch_detail, AARCH64_OPDE_UNALIGNED, idx, NULL);
1409 mismatch_detail->data[0] = alignment;
1410}
1411
1412static inline void
1413set_reg_list_error (aarch64_operand_error *mismatch_detail, int idx,
1414 int expected_num)
1415{
1416 if (mismatch_detail == NULL)
1417 return;
1418 set_error (mismatch_detail, AARCH64_OPDE_REG_LIST, idx, NULL);
1419 mismatch_detail->data[0] = expected_num;
1420}
1421
1422static inline void
1423set_other_error (aarch64_operand_error *mismatch_detail, int idx,
1424 const char* error)
1425{
1426 if (mismatch_detail == NULL)
1427 return;
1428 set_error (mismatch_detail, AARCH64_OPDE_OTHER_ERROR, idx, error);
1429}
1430
1431/* General constraint checking based on operand code.
1432
1433 Return 1 if OPNDS[IDX] meets the general constraint of operand code TYPE
1434 as the IDXth operand of opcode OPCODE. Otherwise return 0.
1435
1436 This function has to be called after the qualifiers for all operands
1437 have been resolved.
1438
1439 Mismatching error message is returned in *MISMATCH_DETAIL upon request,
1440 i.e. when MISMATCH_DETAIL is non-NULL. This avoids the generation
1441 of error message during the disassembling where error message is not
1442 wanted. We avoid the dynamic construction of strings of error messages
1443 here (i.e. in libopcodes), as it is costly and complicated; instead, we
1444 use a combination of error code, static string and some integer data to
1445 represent an error. */
1446
1447static int
1448operand_general_constraint_met_p (const aarch64_opnd_info *opnds, int idx,
1449 enum aarch64_opnd type,
1450 const aarch64_opcode *opcode,
1451 aarch64_operand_error *mismatch_detail)
1452{
e950b345 1453 unsigned num, modifiers, shift;
a06ea964 1454 unsigned char size;
4df068de 1455 int64_t imm, min_value, max_value;
e950b345 1456 uint64_t uvalue, mask;
a06ea964
NC		 1457 const aarch64_opnd_info *opnd = opnds + idx;
1458 aarch64_opnd_qualifier_t qualifier = opnd->qualifier;
1459
1460 assert (opcode->operands[idx] == opnd->type && opnd->type == type);
1461
1462 switch (aarch64_operands[type].op_class)
1463 {
1464 case AARCH64_OPND_CLASS_INT_REG:
ee804238
JW		 1465 /* Check pair reg constraints for cas* instructions. */
1466 if (type == AARCH64_OPND_PAIRREG)
1467 {
1468 assert (idx == 1 || idx == 3);
1469 if (opnds[idx - 1].reg.regno % 2 != 0)
1470 {
1471 set_syntax_error (mismatch_detail, idx - 1,
1472 _("reg pair must start from even reg"));
1473 return 0;
1474 }
1475 if (opnds[idx].reg.regno != opnds[idx - 1].reg.regno + 1)
1476 {
1477 set_syntax_error (mismatch_detail, idx,
1478 _("reg pair must be contiguous"));
1479 return 0;
1480 }
1481 break;
1482 }
1483
a06ea964
NC		 1484 /* <Xt> may be optional in some IC and TLBI instructions. */
1485 if (type == AARCH64_OPND_Rt_SYS)
1486 {
1487 assert (idx == 1 && (aarch64_get_operand_class (opnds[0].type)
1488 == AARCH64_OPND_CLASS_SYSTEM));
ea2deeec
MW		 1489 if (opnds[1].present
1490 && !aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1491 {
1492 set_other_error (mismatch_detail, idx, _("extraneous register"));
1493 return 0;
1494 }
ea2deeec
MW		 1495 if (!opnds[1].present
1496 && aarch64_sys_ins_reg_has_xt (opnds[0].sysins_op))
a06ea964
NC		 1497 {
1498 set_other_error (mismatch_detail, idx, _("missing register"));
1499 return 0;
1500 }
1501 }
1502 switch (qualifier)
1503 {
1504 case AARCH64_OPND_QLF_WSP:
1505 case AARCH64_OPND_QLF_SP:
1506 if (!aarch64_stack_pointer_p (opnd))
1507 {
1508 set_other_error (mismatch_detail, idx,
1509 _("stack pointer register expected"));
1510 return 0;
1511 }
1512 break;
1513 default:
1514 break;
1515 }
1516 break;
1517
f11ad6bc
RS		 1518 case AARCH64_OPND_CLASS_SVE_REG:
1519 switch (type)
1520 {
582e12bf
RS		 1521 case AARCH64_OPND_SVE_Zm3_INDEX:
1522 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 1523 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 1524 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf
RS		 1525 case AARCH64_OPND_SVE_Zm4_INDEX:
1526 size = get_operand_fields_width (get_operand_from_code (type));
1527 shift = get_operand_specific_data (&aarch64_operands[type]);
1528 mask = (1 << shift) - 1;
1529 if (opnd->reg.regno > mask)
1530 {
1531 assert (mask == 7 || mask == 15);
1532 set_other_error (mismatch_detail, idx,
1533 mask == 15
1534 ? _("z0-z15 expected")
1535 : _("z0-z7 expected"));
1536 return 0;
1537 }
1538 mask = (1 << (size - shift)) - 1;
1539 if (!value_in_range_p (opnd->reglane.index, 0, mask))
1540 {
1541 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, mask);
1542 return 0;
1543 }
1544 break;
1545
f11ad6bc
RS		 1546 case AARCH64_OPND_SVE_Zn_INDEX:
1547 size = aarch64_get_qualifier_esize (opnd->qualifier);
1548 if (!value_in_range_p (opnd->reglane.index, 0, 64 / size - 1))
1549 {
1550 set_elem_idx_out_of_range_error (mismatch_detail, idx,
1551 0, 64 / size - 1);
1552 return 0;
1553 }
1554 break;
1555
1556 case AARCH64_OPND_SVE_ZnxN:
1557 case AARCH64_OPND_SVE_ZtxN:
1558 if (opnd->reglist.num_regs != get_opcode_dependent_value (opcode))
1559 {
1560 set_other_error (mismatch_detail, idx,
1561 _("invalid register list"));
1562 return 0;
1563 }
1564 break;
1565
1566 default:
1567 break;
1568 }
1569 break;
1570
1571 case AARCH64_OPND_CLASS_PRED_REG:
1572 if (opnd->reg.regno >= 8
1573 && get_operand_fields_width (get_operand_from_code (type)) == 3)
1574 {
1575 set_other_error (mismatch_detail, idx, _("p0-p7 expected"));
1576 return 0;
1577 }
1578 break;
1579
68a64283
YZ		 1580 case AARCH64_OPND_CLASS_COND:
1581 if (type == AARCH64_OPND_COND1
1582 && (opnds[idx].cond->value & 0xe) == 0xe)
1583 {
1584 /* Not allow AL or NV. */
1585 set_syntax_error (mismatch_detail, idx, NULL);
1586 }
1587 break;
1588
a06ea964
NC		 1589 case AARCH64_OPND_CLASS_ADDRESS:
1590 /* Check writeback. */
1591 switch (opcode->iclass)
1592 {
1593 case ldst_pos:
1594 case ldst_unscaled:
1595 case ldstnapair_offs:
1596 case ldstpair_off:
1597 case ldst_unpriv:
1598 if (opnd->addr.writeback == 1)
1599 {
4e50d5f8
YZ		 1600 set_syntax_error (mismatch_detail, idx,
1601 _("unexpected address writeback"));
a06ea964
NC		 1602 return 0;
1603 }
1604 break;
3f06e550
SN		 1605 case ldst_imm10:
1606 if (opnd->addr.writeback == 1 && opnd->addr.preind != 1)
1607 {
1608 set_syntax_error (mismatch_detail, idx,
1609 _("unexpected address writeback"));
1610 return 0;
1611 }
1612 break;
a06ea964
NC		 1613 case ldst_imm9:
1614 case ldstpair_indexed:
1615 case asisdlsep:
1616 case asisdlsop:
1617 if (opnd->addr.writeback == 0)
1618 {
4e50d5f8
YZ		 1619 set_syntax_error (mismatch_detail, idx,
1620 _("address writeback expected"));
a06ea964
NC		 1621 return 0;
1622 }
1623 break;
1624 default:
1625 assert (opnd->addr.writeback == 0);
1626 break;
1627 }
1628 switch (type)
1629 {
1630 case AARCH64_OPND_ADDR_SIMM7:
1631 /* Scaled signed 7 bits immediate offset. */
1632 /* Get the size of the data element that is accessed, which may be
1633 different from that of the source register size,
1634 e.g. in strb/ldrb. */
1635 size = aarch64_get_qualifier_esize (opnd->qualifier);
1636 if (!value_in_range_p (opnd->addr.offset.imm, -64 * size, 63 * size))
1637 {
1638 set_offset_out_of_range_error (mismatch_detail, idx,
1639 -64 * size, 63 * size);
1640 return 0;
1641 }
1642 if (!value_aligned_p (opnd->addr.offset.imm, size))
1643 {
1644 set_unaligned_error (mismatch_detail, idx, size);
1645 return 0;
1646 }
1647 break;
f42f1a1d 1648 case AARCH64_OPND_ADDR_OFFSET:
a06ea964
NC		 1649 case AARCH64_OPND_ADDR_SIMM9:
1650 /* Unscaled signed 9 bits immediate offset. */
1651 if (!value_in_range_p (opnd->addr.offset.imm, -256, 255))
1652 {
1653 set_offset_out_of_range_error (mismatch_detail, idx, -256, 255);
1654 return 0;
1655 }
1656 break;
1657
1658 case AARCH64_OPND_ADDR_SIMM9_2:
1659 /* Unscaled signed 9 bits immediate offset, which has to be negative
1660 or unaligned. */
1661 size = aarch64_get_qualifier_esize (qualifier);
1662 if ((value_in_range_p (opnd->addr.offset.imm, 0, 255)
1663 && !value_aligned_p (opnd->addr.offset.imm, size))
1664 || value_in_range_p (opnd->addr.offset.imm, -256, -1))
1665 return 1;
1666 set_other_error (mismatch_detail, idx,
1667 _("negative or unaligned offset expected"));
1668 return 0;
1669
3f06e550
SN		 1670 case AARCH64_OPND_ADDR_SIMM10:
1671 /* Scaled signed 10 bits immediate offset. */
1672 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4088))
1673 {
1674 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4088);
1675 return 0;
1676 }
1677 if (!value_aligned_p (opnd->addr.offset.imm, 8))
1678 {
1679 set_unaligned_error (mismatch_detail, idx, 8);
1680 return 0;
1681 }
1682 break;
1683
fb3265b3
SD		 1684 case AARCH64_OPND_ADDR_SIMM11:
1685 /* Signed 11 bits immediate offset (multiple of 16). */
1686 if (!value_in_range_p (opnd->addr.offset.imm, -1024, 1008))
1687 {
1688 set_offset_out_of_range_error (mismatch_detail, idx, -1024, 1008);
1689 return 0;
1690 }
1691
1692 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1693 {
1694 set_unaligned_error (mismatch_detail, idx, 16);
1695 return 0;
1696 }
1697 break;
1698
1699 case AARCH64_OPND_ADDR_SIMM13:
1700 /* Signed 13 bits immediate offset (multiple of 16). */
1701 if (!value_in_range_p (opnd->addr.offset.imm, -4096, 4080))
1702 {
1703 set_offset_out_of_range_error (mismatch_detail, idx, -4096, 4080);
1704 return 0;
1705 }
1706
1707 if (!value_aligned_p (opnd->addr.offset.imm, 16))
1708 {
1709 set_unaligned_error (mismatch_detail, idx, 16);
1710 return 0;
1711 }
1712 break;
1713
a06ea964
NC		 1714 case AARCH64_OPND_SIMD_ADDR_POST:
1715 /* AdvSIMD load/store multiple structures, post-index. */
1716 assert (idx == 1);
1717 if (opnd->addr.offset.is_reg)
1718 {
1719 if (value_in_range_p (opnd->addr.offset.regno, 0, 30))
1720 return 1;
1721 else
1722 {
1723 set_other_error (mismatch_detail, idx,
1724 _("invalid register offset"));
1725 return 0;
1726 }
1727 }
1728 else
1729 {
1730 const aarch64_opnd_info *prev = &opnds[idx-1];
1731 unsigned num_bytes; /* total number of bytes transferred. */
1732 /* The opcode dependent area stores the number of elements in
1733 each structure to be loaded/stored. */
1734 int is_ld1r = get_opcode_dependent_value (opcode) == 1;
1735 if (opcode->operands[0] == AARCH64_OPND_LVt_AL)
1736 /* Special handling of loading single structure to all lane. */
1737 num_bytes = (is_ld1r ? 1 : prev->reglist.num_regs)
1738 * aarch64_get_qualifier_esize (prev->qualifier);
1739 else
1740 num_bytes = prev->reglist.num_regs
1741 * aarch64_get_qualifier_esize (prev->qualifier)
1742 * aarch64_get_qualifier_nelem (prev->qualifier);
1743 if ((int) num_bytes != opnd->addr.offset.imm)
1744 {
1745 set_other_error (mismatch_detail, idx,
1746 _("invalid post-increment amount"));
1747 return 0;
1748 }
1749 }
1750 break;
1751
1752 case AARCH64_OPND_ADDR_REGOFF:
1753 /* Get the size of the data element that is accessed, which may be
1754 different from that of the source register size,
1755 e.g. in strb/ldrb. */
1756 size = aarch64_get_qualifier_esize (opnd->qualifier);
1757 /* It is either no shift or shift by the binary logarithm of SIZE. */
1758 if (opnd->shifter.amount != 0
1759 && opnd->shifter.amount != (int)get_logsz (size))
1760 {
1761 set_other_error (mismatch_detail, idx,
1762 _("invalid shift amount"));
1763 return 0;
1764 }
1765 /* Only UXTW, LSL, SXTW and SXTX are the accepted extending
1766 operators. */
1767 switch (opnd->shifter.kind)
1768 {
1769 case AARCH64_MOD_UXTW:
1770 case AARCH64_MOD_LSL:
1771 case AARCH64_MOD_SXTW:
1772 case AARCH64_MOD_SXTX: break;
1773 default:
1774 set_other_error (mismatch_detail, idx,
1775 _("invalid extend/shift operator"));
1776 return 0;
1777 }
1778 break;
1779
1780 case AARCH64_OPND_ADDR_UIMM12:
1781 imm = opnd->addr.offset.imm;
1782 /* Get the size of the data element that is accessed, which may be
1783 different from that of the source register size,
1784 e.g. in strb/ldrb. */
1785 size = aarch64_get_qualifier_esize (qualifier);
1786 if (!value_in_range_p (opnd->addr.offset.imm, 0, 4095 * size))
1787 {
1788 set_offset_out_of_range_error (mismatch_detail, idx,
1789 0, 4095 * size);
1790 return 0;
1791 }
9de794e1 1792 if (!value_aligned_p (opnd->addr.offset.imm, size))
a06ea964
NC		 1793 {
1794 set_unaligned_error (mismatch_detail, idx, size);
1795 return 0;
1796 }
1797 break;
1798
1799 case AARCH64_OPND_ADDR_PCREL14:
1800 case AARCH64_OPND_ADDR_PCREL19:
1801 case AARCH64_OPND_ADDR_PCREL21:
1802 case AARCH64_OPND_ADDR_PCREL26:
1803 imm = opnd->imm.value;
1804 if (operand_need_shift_by_two (get_operand_from_code (type)))
1805 {
1806 /* The offset value in a PC-relative branch instruction is alway
1807 4-byte aligned and is encoded without the lowest 2 bits. */
1808 if (!value_aligned_p (imm, 4))
1809 {
1810 set_unaligned_error (mismatch_detail, idx, 4);
1811 return 0;
1812 }
1813 /* Right shift by 2 so that we can carry out the following check
1814 canonically. */
1815 imm >>= 2;
1816 }
1817 size = get_operand_fields_width (get_operand_from_code (type));
1818 if (!value_fit_signed_field_p (imm, size))
1819 {
1820 set_other_error (mismatch_detail, idx,
1821 _("immediate out of range"));
1822 return 0;
1823 }
1824 break;
1825
98907a70
RS		 1826 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
1827 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
1828 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
1829 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
1830 min_value = -8;
1831 max_value = 7;
1832 sve_imm_offset_vl:
1833 assert (!opnd->addr.offset.is_reg);
1834 assert (opnd->addr.preind);
1835 num = 1 + get_operand_specific_data (&aarch64_operands[type]);
1836 min_value *= num;
1837 max_value *= num;
1838 if ((opnd->addr.offset.imm != 0 && !opnd->shifter.operator_present)
1839 || (opnd->shifter.operator_present
1840 && opnd->shifter.kind != AARCH64_MOD_MUL_VL))
1841 {
1842 set_other_error (mismatch_detail, idx,
1843 _("invalid addressing mode"));
1844 return 0;
1845 }
1846 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1847 {
1848 set_offset_out_of_range_error (mismatch_detail, idx,
1849 min_value, max_value);
1850 return 0;
1851 }
1852 if (!value_aligned_p (opnd->addr.offset.imm, num))
1853 {
1854 set_unaligned_error (mismatch_detail, idx, num);
1855 return 0;
1856 }
1857 break;
1858
1859 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
1860 min_value = -32;
1861 max_value = 31;
1862 goto sve_imm_offset_vl;
1863
1864 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
1865 min_value = -256;
1866 max_value = 255;
1867 goto sve_imm_offset_vl;
1868
4df068de
RS		 1869 case AARCH64_OPND_SVE_ADDR_RI_U6:
1870 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
1871 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
1872 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
1873 min_value = 0;
1874 max_value = 63;
1875 sve_imm_offset:
1876 assert (!opnd->addr.offset.is_reg);
1877 assert (opnd->addr.preind);
1878 num = 1 << get_operand_specific_data (&aarch64_operands[type]);
1879 min_value *= num;
1880 max_value *= num;
1881 if (opnd->shifter.operator_present
1882 || opnd->shifter.amount_present)
1883 {
1884 set_other_error (mismatch_detail, idx,
1885 _("invalid addressing mode"));
1886 return 0;
1887 }
1888 if (!value_in_range_p (opnd->addr.offset.imm, min_value, max_value))
1889 {
1890 set_offset_out_of_range_error (mismatch_detail, idx,
1891 min_value, max_value);
1892 return 0;
1893 }
1894 if (!value_aligned_p (opnd->addr.offset.imm, num))
1895 {
1896 set_unaligned_error (mismatch_detail, idx, num);
1897 return 0;
1898 }
1899 break;
1900
582e12bf 1901 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
8382113f 1902 case AARCH64_OPND_SVE_ADDR_RI_S4x32:
582e12bf
RS		 1903 min_value = -8;
1904 max_value = 7;
1905 goto sve_imm_offset;
1906
c469c864
MM		 1907 case AARCH64_OPND_SVE_ADDR_ZX:
1908 /* Everything is already ensured by parse_operands or
1909 aarch64_ext_sve_addr_rr_lsl (because this is a very specific
1910 argument type). */
1911 assert (opnd->addr.offset.is_reg);
1912 assert (opnd->addr.preind);
1913 assert ((aarch64_operands[type].flags & OPD_F_NO_ZR) == 0);
1914 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
1915 assert (opnd->shifter.operator_present == 0);
1916 break;
1917
c8d59609 1918 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 1919 case AARCH64_OPND_SVE_ADDR_RR:
1920 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
1921 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
1922 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
1923 case AARCH64_OPND_SVE_ADDR_RX:
1924 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
1925 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
1926 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
1927 case AARCH64_OPND_SVE_ADDR_RZ:
1928 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
1929 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
1930 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
1931 modifiers = 1 << AARCH64_MOD_LSL;
1932 sve_rr_operand:
1933 assert (opnd->addr.offset.is_reg);
1934 assert (opnd->addr.preind);
1935 if ((aarch64_operands[type].flags & OPD_F_NO_ZR) != 0
1936 && opnd->addr.offset.regno == 31)
1937 {
1938 set_other_error (mismatch_detail, idx,
1939 _("index register xzr is not allowed"));
1940 return 0;
1941 }
1942 if (((1 << opnd->shifter.kind) & modifiers) == 0
1943 || (opnd->shifter.amount
1944 != get_operand_specific_data (&aarch64_operands[type])))
1945 {
1946 set_other_error (mismatch_detail, idx,
1947 _("invalid addressing mode"));
1948 return 0;
1949 }
1950 break;
1951
1952 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
1953 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
1954 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
1955 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
1956 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
1957 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
1958 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
1959 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
1960 modifiers = (1 << AARCH64_MOD_SXTW) | (1 << AARCH64_MOD_UXTW);
1961 goto sve_rr_operand;
1962
1963 case AARCH64_OPND_SVE_ADDR_ZI_U5:
1964 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
1965 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
1966 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
1967 min_value = 0;
1968 max_value = 31;
1969 goto sve_imm_offset;
1970
1971 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
1972 modifiers = 1 << AARCH64_MOD_LSL;
1973 sve_zz_operand:
1974 assert (opnd->addr.offset.is_reg);
1975 assert (opnd->addr.preind);
1976 if (((1 << opnd->shifter.kind) & modifiers) == 0
1977 || opnd->shifter.amount < 0
1978 || opnd->shifter.amount > 3)
1979 {
1980 set_other_error (mismatch_detail, idx,
1981 _("invalid addressing mode"));
1982 return 0;
1983 }
1984 break;
1985
1986 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
1987 modifiers = (1 << AARCH64_MOD_SXTW);
1988 goto sve_zz_operand;
1989
1990 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
1991 modifiers = 1 << AARCH64_MOD_UXTW;
1992 goto sve_zz_operand;
1993
a06ea964
NC		 1994 default:
1995 break;
1996 }
1997 break;
1998
1999 case AARCH64_OPND_CLASS_SIMD_REGLIST:
dab26bf4
RS		 2000 if (type == AARCH64_OPND_LEt)
2001 {
2002 /* Get the upper bound for the element index. */
2003 num = 16 / aarch64_get_qualifier_esize (qualifier) - 1;
2004 if (!value_in_range_p (opnd->reglist.index, 0, num))
2005 {
2006 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2007 return 0;
2008 }
2009 }
a06ea964
NC		 2010 /* The opcode dependent area stores the number of elements in
2011 each structure to be loaded/stored. */
2012 num = get_opcode_dependent_value (opcode);
2013 switch (type)
2014 {
2015 case AARCH64_OPND_LVt:
2016 assert (num >= 1 && num <= 4);
2017 /* Unless LD1/ST1, the number of registers should be equal to that
2018 of the structure elements. */
2019 if (num != 1 && opnd->reglist.num_regs != num)
2020 {
2021 set_reg_list_error (mismatch_detail, idx, num);
2022 return 0;
2023 }
2024 break;
2025 case AARCH64_OPND_LVt_AL:
2026 case AARCH64_OPND_LEt:
2027 assert (num >= 1 && num <= 4);
2028 /* The number of registers should be equal to that of the structure
2029 elements. */
2030 if (opnd->reglist.num_regs != num)
2031 {
2032 set_reg_list_error (mismatch_detail, idx, num);
2033 return 0;
2034 }
2035 break;
2036 default:
2037 break;
2038 }
2039 break;
2040
2041 case AARCH64_OPND_CLASS_IMMEDIATE:
2042 /* Constraint check on immediate operand. */
2043 imm = opnd->imm.value;
2044 /* E.g. imm_0_31 constrains value to be 0..31. */
2045 if (qualifier_value_in_range_constraint_p (qualifier)
2046 && !value_in_range_p (imm, get_lower_bound (qualifier),
2047 get_upper_bound (qualifier)))
2048 {
2049 set_imm_out_of_range_error (mismatch_detail, idx,
2050 get_lower_bound (qualifier),
2051 get_upper_bound (qualifier));
2052 return 0;
2053 }
2054
2055 switch (type)
2056 {
2057 case AARCH64_OPND_AIMM:
2058 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2059 {
2060 set_other_error (mismatch_detail, idx,
2061 _("invalid shift operator"));
2062 return 0;
2063 }
2064 if (opnd->shifter.amount != 0 && opnd->shifter.amount != 12)
2065 {
2066 set_other_error (mismatch_detail, idx,
ab3b8fcf 2067 _("shift amount must be 0 or 12"));
a06ea964
NC		 2068 return 0;
2069 }
2070 if (!value_fit_unsigned_field_p (opnd->imm.value, 12))
2071 {
2072 set_other_error (mismatch_detail, idx,
2073 _("immediate out of range"));
2074 return 0;
2075 }
2076 break;
2077
2078 case AARCH64_OPND_HALF:
2079 assert (idx == 1 && opnds[0].type == AARCH64_OPND_Rd);
2080 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2081 {
2082 set_other_error (mismatch_detail, idx,
2083 _("invalid shift operator"));
2084 return 0;
2085 }
2086 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2087 if (!value_aligned_p (opnd->shifter.amount, 16))
2088 {
2089 set_other_error (mismatch_detail, idx,
ab3b8fcf 2090 _("shift amount must be a multiple of 16"));
a06ea964
NC		 2091 return 0;
2092 }
2093 if (!value_in_range_p (opnd->shifter.amount, 0, size * 8 - 16))
2094 {
2095 set_sft_amount_out_of_range_error (mismatch_detail, idx,
2096 0, size * 8 - 16);
2097 return 0;
2098 }
2099 if (opnd->imm.value < 0)
2100 {
2101 set_other_error (mismatch_detail, idx,
2102 _("negative immediate value not allowed"));
2103 return 0;
2104 }
2105 if (!value_fit_unsigned_field_p (opnd->imm.value, 16))
2106 {
2107 set_other_error (mismatch_detail, idx,
2108 _("immediate out of range"));
2109 return 0;
2110 }
2111 break;
2112
2113 case AARCH64_OPND_IMM_MOV:
2114 {
42408347 2115 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
a06ea964
NC		 2116 imm = opnd->imm.value;
2117 assert (idx == 1);
2118 switch (opcode->op)
2119 {
2120 case OP_MOV_IMM_WIDEN:
2121 imm = ~imm;
1a0670f3 2122 /* Fall through. */
a06ea964 2123 case OP_MOV_IMM_WIDE:
42408347 2124 if (!aarch64_wide_constant_p (imm, esize == 4, NULL))
a06ea964
NC		 2125 {
2126 set_other_error (mismatch_detail, idx,
2127 _("immediate out of range"));
2128 return 0;
2129 }
2130 break;
2131 case OP_MOV_IMM_LOG:
42408347 2132 if (!aarch64_logical_immediate_p (imm, esize, NULL))
a06ea964
NC		 2133 {
2134 set_other_error (mismatch_detail, idx,
2135 _("immediate out of range"));
2136 return 0;
2137 }
2138 break;
2139 default:
2140 assert (0);
2141 return 0;
2142 }
2143 }
2144 break;
2145
2146 case AARCH64_OPND_NZCV:
2147 case AARCH64_OPND_CCMP_IMM:
2148 case AARCH64_OPND_EXCEPTION:
b83b4b13 2149 case AARCH64_OPND_TME_UIMM16:
a06ea964 2150 case AARCH64_OPND_UIMM4:
193614f2 2151 case AARCH64_OPND_UIMM4_ADDG:
a06ea964
NC		 2152 case AARCH64_OPND_UIMM7:
2153 case AARCH64_OPND_UIMM3_OP1:
2154 case AARCH64_OPND_UIMM3_OP2:
e950b345
RS		 2155 case AARCH64_OPND_SVE_UIMM3:
2156 case AARCH64_OPND_SVE_UIMM7:
2157 case AARCH64_OPND_SVE_UIMM8:
2158 case AARCH64_OPND_SVE_UIMM8_53:
a06ea964
NC		 2159 size = get_operand_fields_width (get_operand_from_code (type));
2160 assert (size < 32);
2161 if (!value_fit_unsigned_field_p (opnd->imm.value, size))
2162 {
2163 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2164 (1 << size) - 1);
2165 return 0;
2166 }
2167 break;
2168
193614f2
SD		 2169 case AARCH64_OPND_UIMM10:
2170 /* Scaled unsigned 10 bits immediate offset. */
2171 if (!value_in_range_p (opnd->imm.value, 0, 1008))
2172 {
2173 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1008);
2174 return 0;
2175 }
2176
2177 if (!value_aligned_p (opnd->imm.value, 16))
2178 {
2179 set_unaligned_error (mismatch_detail, idx, 16);
2180 return 0;
2181 }
2182 break;
2183
e950b345
RS		 2184 case AARCH64_OPND_SIMM5:
2185 case AARCH64_OPND_SVE_SIMM5:
2186 case AARCH64_OPND_SVE_SIMM5B:
2187 case AARCH64_OPND_SVE_SIMM6:
2188 case AARCH64_OPND_SVE_SIMM8:
2189 size = get_operand_fields_width (get_operand_from_code (type));
2190 assert (size < 32);
2191 if (!value_fit_signed_field_p (opnd->imm.value, size))
2192 {
2193 set_imm_out_of_range_error (mismatch_detail, idx,
2194 -(1 << (size - 1)),
2195 (1 << (size - 1)) - 1);
2196 return 0;
2197 }
2198 break;
2199
a06ea964 2200 case AARCH64_OPND_WIDTH:
d685192a 2201 assert (idx > 1 && opnds[idx-1].type == AARCH64_OPND_IMM
a06ea964
NC		 2202 && opnds[0].type == AARCH64_OPND_Rd);
2203 size = get_upper_bound (qualifier);
2204 if (opnd->imm.value + opnds[idx-1].imm.value > size)
2205 /* lsb+width <= reg.size */
2206 {
2207 set_imm_out_of_range_error (mismatch_detail, idx, 1,
2208 size - opnds[idx-1].imm.value);
2209 return 0;
2210 }
2211 break;
2212
2213 case AARCH64_OPND_LIMM:
e950b345 2214 case AARCH64_OPND_SVE_LIMM:
42408347
RS		 2215 {
2216 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2217 uint64_t uimm = opnd->imm.value;
2218 if (opcode->op == OP_BIC)
2219 uimm = ~uimm;
535b785f 2220 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
42408347
RS		 2221 {
2222 set_other_error (mismatch_detail, idx,
2223 _("immediate out of range"));
2224 return 0;
2225 }
2226 }
a06ea964
NC		 2227 break;
2228
2229 case AARCH64_OPND_IMM0:
2230 case AARCH64_OPND_FPIMM0:
2231 if (opnd->imm.value != 0)
2232 {
2233 set_other_error (mismatch_detail, idx,
2234 _("immediate zero expected"));
2235 return 0;
2236 }
2237 break;
2238
c2c4ff8d
SN		 2239 case AARCH64_OPND_IMM_ROT1:
2240 case AARCH64_OPND_IMM_ROT2:
582e12bf 2241 case AARCH64_OPND_SVE_IMM_ROT2:
c2c4ff8d
SN		 2242 if (opnd->imm.value != 0
2243 && opnd->imm.value != 90
2244 && opnd->imm.value != 180
2245 && opnd->imm.value != 270)
2246 {
2247 set_other_error (mismatch_detail, idx,
2248 _("rotate expected to be 0, 90, 180 or 270"));
2249 return 0;
2250 }
2251 break;
2252
2253 case AARCH64_OPND_IMM_ROT3:
582e12bf 2254 case AARCH64_OPND_SVE_IMM_ROT1:
adccc507 2255 case AARCH64_OPND_SVE_IMM_ROT3:
c2c4ff8d
SN		 2256 if (opnd->imm.value != 90 && opnd->imm.value != 270)
2257 {
2258 set_other_error (mismatch_detail, idx,
2259 _("rotate expected to be 90 or 270"));
2260 return 0;
2261 }
2262 break;
2263
a06ea964
NC		 2264 case AARCH64_OPND_SHLL_IMM:
2265 assert (idx == 2);
2266 size = 8 * aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2267 if (opnd->imm.value != size)
2268 {
2269 set_other_error (mismatch_detail, idx,
2270 _("invalid shift amount"));
2271 return 0;
2272 }
2273 break;
2274
2275 case AARCH64_OPND_IMM_VLSL:
2276 size = aarch64_get_qualifier_esize (qualifier);
2277 if (!value_in_range_p (opnd->imm.value, 0, size * 8 - 1))
2278 {
2279 set_imm_out_of_range_error (mismatch_detail, idx, 0,
2280 size * 8 - 1);
2281 return 0;
2282 }
2283 break;
2284
2285 case AARCH64_OPND_IMM_VLSR:
2286 size = aarch64_get_qualifier_esize (qualifier);
2287 if (!value_in_range_p (opnd->imm.value, 1, size * 8))
2288 {
2289 set_imm_out_of_range_error (mismatch_detail, idx, 1, size * 8);
2290 return 0;
2291 }
2292 break;
2293
2294 case AARCH64_OPND_SIMD_IMM:
2295 case AARCH64_OPND_SIMD_IMM_SFT:
2296 /* Qualifier check. */
2297 switch (qualifier)
2298 {
2299 case AARCH64_OPND_QLF_LSL:
2300 if (opnd->shifter.kind != AARCH64_MOD_LSL)
2301 {
2302 set_other_error (mismatch_detail, idx,
2303 _("invalid shift operator"));
2304 return 0;
2305 }
2306 break;
2307 case AARCH64_OPND_QLF_MSL:
2308 if (opnd->shifter.kind != AARCH64_MOD_MSL)
2309 {
2310 set_other_error (mismatch_detail, idx,
2311 _("invalid shift operator"));
2312 return 0;
2313 }
2314 break;
2315 case AARCH64_OPND_QLF_NIL:
2316 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2317 {
2318 set_other_error (mismatch_detail, idx,
2319 _("shift is not permitted"));
2320 return 0;
2321 }
2322 break;
2323 default:
2324 assert (0);
2325 return 0;
2326 }
2327 /* Is the immediate valid? */
2328 assert (idx == 1);
2329 if (aarch64_get_qualifier_esize (opnds[0].qualifier) != 8)
2330 {
d2865ed3
YZ		 2331 /* uimm8 or simm8 */
2332 if (!value_in_range_p (opnd->imm.value, -128, 255))
a06ea964 2333 {
d2865ed3 2334 set_imm_out_of_range_error (mismatch_detail, idx, -128, 255);
a06ea964
NC		 2335 return 0;
2336 }
2337 }
2338 else if (aarch64_shrink_expanded_imm8 (opnd->imm.value) < 0)
2339 {
2340 /* uimm64 is not
2341 'aaaaaaaabbbbbbbbccccccccddddddddeeeeeeee
2342 ffffffffgggggggghhhhhhhh'. */
2343 set_other_error (mismatch_detail, idx,
2344 _("invalid value for immediate"));
2345 return 0;
2346 }
2347 /* Is the shift amount valid? */
2348 switch (opnd->shifter.kind)
2349 {
2350 case AARCH64_MOD_LSL:
2351 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
f5555712 2352 if (!value_in_range_p (opnd->shifter.amount, 0, (size - 1) * 8))
a06ea964 2353 {
f5555712
YZ		 2354 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0,
2355 (size - 1) * 8);
a06ea964
NC		 2356 return 0;
2357 }
f5555712 2358 if (!value_aligned_p (opnd->shifter.amount, 8))
a06ea964 2359 {
f5555712 2360 set_unaligned_error (mismatch_detail, idx, 8);
a06ea964
NC		 2361 return 0;
2362 }
2363 break;
2364 case AARCH64_MOD_MSL:
2365 /* Only 8 and 16 are valid shift amount. */
2366 if (opnd->shifter.amount != 8 && opnd->shifter.amount != 16)
2367 {
2368 set_other_error (mismatch_detail, idx,
ab3b8fcf 2369 _("shift amount must be 0 or 16"));
a06ea964
NC		 2370 return 0;
2371 }
2372 break;
2373 default:
2374 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2375 {
2376 set_other_error (mismatch_detail, idx,
2377 _("invalid shift operator"));
2378 return 0;
2379 }
2380 break;
2381 }
2382 break;
2383
2384 case AARCH64_OPND_FPIMM:
2385 case AARCH64_OPND_SIMD_FPIMM:
165d4950 2386 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 2387 if (opnd->imm.is_fp == 0)
2388 {
2389 set_other_error (mismatch_detail, idx,
2390 _("floating-point immediate expected"));
2391 return 0;
2392 }
2393 /* The value is expected to be an 8-bit floating-point constant with
2394 sign, 3-bit exponent and normalized 4 bits of precision, encoded
2395 in "a:b:c:d:e:f:g:h" or FLD_imm8 (depending on the type of the
2396 instruction). */
2397 if (!value_in_range_p (opnd->imm.value, 0, 255))
2398 {
2399 set_other_error (mismatch_detail, idx,
2400 _("immediate out of range"));
2401 return 0;
2402 }
2403 if (opnd->shifter.kind != AARCH64_MOD_NONE)
2404 {
2405 set_other_error (mismatch_detail, idx,
2406 _("invalid shift operator"));
2407 return 0;
2408 }
2409 break;
2410
e950b345
RS		 2411 case AARCH64_OPND_SVE_AIMM:
2412 min_value = 0;
2413 sve_aimm:
2414 assert (opnd->shifter.kind == AARCH64_MOD_LSL);
2415 size = aarch64_get_qualifier_esize (opnds[0].qualifier);
2416 mask = ~((uint64_t) -1 << (size * 4) << (size * 4));
2417 uvalue = opnd->imm.value;
2418 shift = opnd->shifter.amount;
2419 if (size == 1)
2420 {
2421 if (shift != 0)
2422 {
2423 set_other_error (mismatch_detail, idx,
2424 _("no shift amount allowed for"
2425 " 8-bit constants"));
2426 return 0;
2427 }
2428 }
2429 else
2430 {
2431 if (shift != 0 && shift != 8)
2432 {
2433 set_other_error (mismatch_detail, idx,
2434 _("shift amount must be 0 or 8"));
2435 return 0;
2436 }
2437 if (shift == 0 && (uvalue & 0xff) == 0)
2438 {
2439 shift = 8;
2440 uvalue = (int64_t) uvalue / 256;
2441 }
2442 }
2443 mask >>= shift;
2444 if ((uvalue & mask) != uvalue && (uvalue | ~mask) != uvalue)
2445 {
2446 set_other_error (mismatch_detail, idx,
2447 _("immediate too big for element size"));
2448 return 0;
2449 }
2450 uvalue = (uvalue - min_value) & mask;
2451 if (uvalue > 0xff)
2452 {
2453 set_other_error (mismatch_detail, idx,
2454 _("invalid arithmetic immediate"));
2455 return 0;
2456 }
2457 break;
2458
2459 case AARCH64_OPND_SVE_ASIMM:
2460 min_value = -128;
2461 goto sve_aimm;
2462
165d4950
RS		 2463 case AARCH64_OPND_SVE_I1_HALF_ONE:
2464 assert (opnd->imm.is_fp);
2465 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x3f800000)
2466 {
2467 set_other_error (mismatch_detail, idx,
2468 _("floating-point value must be 0.5 or 1.0"));
2469 return 0;
2470 }
2471 break;
2472
2473 case AARCH64_OPND_SVE_I1_HALF_TWO:
2474 assert (opnd->imm.is_fp);
2475 if (opnd->imm.value != 0x3f000000 && opnd->imm.value != 0x40000000)
2476 {
2477 set_other_error (mismatch_detail, idx,
2478 _("floating-point value must be 0.5 or 2.0"));
2479 return 0;
2480 }
2481 break;
2482
2483 case AARCH64_OPND_SVE_I1_ZERO_ONE:
2484 assert (opnd->imm.is_fp);
2485 if (opnd->imm.value != 0 && opnd->imm.value != 0x3f800000)
2486 {
2487 set_other_error (mismatch_detail, idx,
2488 _("floating-point value must be 0.0 or 1.0"));
2489 return 0;
2490 }
2491 break;
2492
e950b345
RS		 2493 case AARCH64_OPND_SVE_INV_LIMM:
2494 {
2495 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2496 uint64_t uimm = ~opnd->imm.value;
2497 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2498 {
2499 set_other_error (mismatch_detail, idx,
2500 _("immediate out of range"));
2501 return 0;
2502 }
2503 }
2504 break;
2505
2506 case AARCH64_OPND_SVE_LIMM_MOV:
2507 {
2508 int esize = aarch64_get_qualifier_esize (opnds[0].qualifier);
2509 uint64_t uimm = opnd->imm.value;
2510 if (!aarch64_logical_immediate_p (uimm, esize, NULL))
2511 {
2512 set_other_error (mismatch_detail, idx,
2513 _("immediate out of range"));
2514 return 0;
2515 }
2516 if (!aarch64_sve_dupm_mov_immediate_p (uimm, esize))
2517 {
2518 set_other_error (mismatch_detail, idx,
2519 _("invalid replicated MOV immediate"));
2520 return 0;
2521 }
2522 }
2523 break;
2524
2442d846
RS		 2525 case AARCH64_OPND_SVE_PATTERN_SCALED:
2526 assert (opnd->shifter.kind == AARCH64_MOD_MUL);
2527 if (!value_in_range_p (opnd->shifter.amount, 1, 16))
2528 {
2529 set_multiplier_out_of_range_error (mismatch_detail, idx, 1, 16);
2530 return 0;
2531 }
2532 break;
2533
e950b345
RS		 2534 case AARCH64_OPND_SVE_SHLIMM_PRED:
2535 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 2536 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 2537 size = aarch64_get_qualifier_esize (opnds[idx - 1].qualifier);
2538 if (!value_in_range_p (opnd->imm.value, 0, 8 * size - 1))
2539 {
2540 set_imm_out_of_range_error (mismatch_detail, idx,
2541 0, 8 * size - 1);
2542 return 0;
2543 }
2544 break;
2545
2546 case AARCH64_OPND_SVE_SHRIMM_PRED:
2547 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 2548 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345 2549 {
3c17238b
MM		 2550 unsigned int index =
2551 (type == AARCH64_OPND_SVE_SHRIMM_UNPRED_22) ? 2 : 1;
2552 size = aarch64_get_qualifier_esize (opnds[idx - index].qualifier);
2553 if (!value_in_range_p (opnd->imm.value, 1, 8 * size))
2554 {
2555 set_imm_out_of_range_error (mismatch_detail, idx, 1, 8*size);
2556 return 0;
2557 }
2558 break;
2559 }
e950b345 2560
a06ea964
NC		 2561 default:
2562 break;
2563 }
2564 break;
2565
a06ea964
NC		 2566 case AARCH64_OPND_CLASS_SYSTEM:
2567 switch (type)
2568 {
2569 case AARCH64_OPND_PSTATEFIELD:
2570 assert (idx == 0 && opnds[1].type == AARCH64_OPND_UIMM4);
0bff6e2d
MW		 2571 /* MSR UAO, #uimm4
2572 MSR PAN, #uimm4
104fefee 2573 MSR SSBS,#uimm4
c2825638 2574 The immediate must be #0 or #1. */
0bff6e2d 2575 if ((opnd->pstatefield == 0x03 /* UAO. */
793a1948 2576 || opnd->pstatefield == 0x04 /* PAN. */
104fefee 2577 || opnd->pstatefield == 0x19 /* SSBS. */
793a1948 2578 || opnd->pstatefield == 0x1a) /* DIT. */
c2825638
MW		 2579 && opnds[1].imm.value > 1)
2580 {
2581 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2582 return 0;
2583 }
a06ea964
NC		 2584 /* MSR SPSel, #uimm4
2585 Uses uimm4 as a control value to select the stack pointer: if
2586 bit 0 is set it selects the current exception level's stack
2587 pointer, if bit 0 is clear it selects shared EL0 stack pointer.
2588 Bits 1 to 3 of uimm4 are reserved and should be zero. */
2589 if (opnd->pstatefield == 0x05 /* spsel */ && opnds[1].imm.value > 1)
2590 {
2591 set_imm_out_of_range_error (mismatch_detail, idx, 0, 1);
2592 return 0;
2593 }
2594 break;
2595 default:
2596 break;
2597 }
2598 break;
2599
2600 case AARCH64_OPND_CLASS_SIMD_ELEMENT:
2601 /* Get the upper bound for the element index. */
c2c4ff8d
SN		 2602 if (opcode->op == OP_FCMLA_ELEM)
2603 /* FCMLA index range depends on the vector size of other operands
2604 and is halfed because complex numbers take two elements. */
2605 num = aarch64_get_qualifier_nelem (opnds[0].qualifier)
2606 * aarch64_get_qualifier_esize (opnds[0].qualifier) / 2;
2607 else
2608 num = 16;
2609 num = num / aarch64_get_qualifier_esize (qualifier) - 1;
66e6f0b7 2610 assert (aarch64_get_qualifier_nelem (qualifier) == 1);
c2c4ff8d 2611
a06ea964
NC		 2612 /* Index out-of-range. */
2613 if (!value_in_range_p (opnd->reglane.index, 0, num))
2614 {
2615 set_elem_idx_out_of_range_error (mismatch_detail, idx, 0, num);
2616 return 0;
2617 }
2618 /* SMLAL<Q> <Vd>.<Ta>, <Vn>.<Tb>, <Vm>.<Ts>[<index>].
2619 <Vm> Is the vector register (V0-V31) or (V0-V15), whose
2620 number is encoded in "size:M:Rm":
2621 size <Vm>
2622 00 RESERVED
2623 01 0:Rm
2624 10 M:Rm
2625 11 RESERVED */
369c9167 2626 if (type == AARCH64_OPND_Em16 && qualifier == AARCH64_OPND_QLF_S_H
a06ea964
NC		 2627 && !value_in_range_p (opnd->reglane.regno, 0, 15))
2628 {
2629 set_regno_out_of_range_error (mismatch_detail, idx, 0, 15);
2630 return 0;
2631 }
2632 break;
2633
2634 case AARCH64_OPND_CLASS_MODIFIED_REG:
2635 assert (idx == 1 || idx == 2);
2636 switch (type)
2637 {
2638 case AARCH64_OPND_Rm_EXT:
535b785f 2639 if (!aarch64_extend_operator_p (opnd->shifter.kind)
a06ea964
NC		 2640 && opnd->shifter.kind != AARCH64_MOD_LSL)
2641 {
2642 set_other_error (mismatch_detail, idx,
2643 _("extend operator expected"));
2644 return 0;
2645 }
2646 /* It is not optional unless at least one of "Rd" or "Rn" is '11111'
2647 (i.e. SP), in which case it defaults to LSL. The LSL alias is
2648 only valid when "Rd" or "Rn" is '11111', and is preferred in that
2649 case. */
2650 if (!aarch64_stack_pointer_p (opnds + 0)
2651 && (idx != 2 || !aarch64_stack_pointer_p (opnds + 1)))
2652 {
2653 if (!opnd->shifter.operator_present)
2654 {
2655 set_other_error (mismatch_detail, idx,
2656 _("missing extend operator"));
2657 return 0;
2658 }
2659 else if (opnd->shifter.kind == AARCH64_MOD_LSL)
2660 {
2661 set_other_error (mismatch_detail, idx,
2662 _("'LSL' operator not allowed"));
2663 return 0;
2664 }
2665 }
2666 assert (opnd->shifter.operator_present /* Default to LSL. */
2667 || opnd->shifter.kind == AARCH64_MOD_LSL);
2668 if (!value_in_range_p (opnd->shifter.amount, 0, 4))
2669 {
2670 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, 4);
2671 return 0;
2672 }
2673 /* In the 64-bit form, the final register operand is written as Wm
2674 for all but the (possibly omitted) UXTX/LSL and SXTX
2675 operators.
2676 N.B. GAS allows X register to be used with any operator as a
2677 programming convenience. */
2678 if (qualifier == AARCH64_OPND_QLF_X
2679 && opnd->shifter.kind != AARCH64_MOD_LSL
2680 && opnd->shifter.kind != AARCH64_MOD_UXTX
2681 && opnd->shifter.kind != AARCH64_MOD_SXTX)
2682 {
2683 set_other_error (mismatch_detail, idx, _("W register expected"));
2684 return 0;
2685 }
2686 break;
2687
2688 case AARCH64_OPND_Rm_SFT:
2689 /* ROR is not available to the shifted register operand in
2690 arithmetic instructions. */
535b785f 2691 if (!aarch64_shift_operator_p (opnd->shifter.kind))
a06ea964
NC		 2692 {
2693 set_other_error (mismatch_detail, idx,
2694 _("shift operator expected"));
2695 return 0;
2696 }
2697 if (opnd->shifter.kind == AARCH64_MOD_ROR
2698 && opcode->iclass != log_shift)
2699 {
2700 set_other_error (mismatch_detail, idx,
2701 _("'ROR' operator not allowed"));
2702 return 0;
2703 }
2704 num = qualifier == AARCH64_OPND_QLF_W ? 31 : 63;
2705 if (!value_in_range_p (opnd->shifter.amount, 0, num))
2706 {
2707 set_sft_amount_out_of_range_error (mismatch_detail, idx, 0, num);
2708 return 0;
2709 }
2710 break;
2711
2712 default:
2713 break;
2714 }
2715 break;
2716
2717 default:
2718 break;
2719 }
2720
2721 return 1;
2722}
2723
2724/* Main entrypoint for the operand constraint checking.
2725
2726 Return 1 if operands of *INST meet the constraint applied by the operand
2727 codes and operand qualifiers; otherwise return 0 and if MISMATCH_DETAIL is
2728 not NULL, return the detail of the error in *MISMATCH_DETAIL. N.B. when
2729 adding more constraint checking, make sure MISMATCH_DETAIL->KIND is set
2730 with a proper error kind rather than AARCH64_OPDE_NIL (GAS asserts non-NIL
2731 error kind when it is notified that an instruction does not pass the check).
2732
2733 Un-determined operand qualifiers may get established during the process. */
2734
2735int
2736aarch64_match_operands_constraint (aarch64_inst *inst,
2737 aarch64_operand_error *mismatch_detail)
2738{
2739 int i;
2740
2741 DEBUG_TRACE ("enter");
2742
0c608d6b
RS		 2743 /* Check for cases where a source register needs to be the same as the
2744 destination register. Do this before matching qualifiers since if
2745 an instruction has both invalid tying and invalid qualifiers,
2746 the error about qualifiers would suggest several alternative
2747 instructions that also have invalid tying. */
2748 i = inst->opcode->tied_operand;
2749 if (i > 0 && (inst->operands[0].reg.regno != inst->operands[i].reg.regno))
2750 {
2751 if (mismatch_detail)
2752 {
2753 mismatch_detail->kind = AARCH64_OPDE_UNTIED_OPERAND;
2754 mismatch_detail->index = i;
2755 mismatch_detail->error = NULL;
2756 }
2757 return 0;
2758 }
2759
a06ea964
NC		 2760 /* Match operands' qualifier.
2761 *INST has already had qualifier establish for some, if not all, of
2762 its operands; we need to find out whether these established
2763 qualifiers match one of the qualifier sequence in
2764 INST->OPCODE->QUALIFIERS_LIST. If yes, we will assign each operand
2765 with the corresponding qualifier in such a sequence.
2766 Only basic operand constraint checking is done here; the more thorough
2767 constraint checking will carried out by operand_general_constraint_met_p,
2768 which has be to called after this in order to get all of the operands'
2769 qualifiers established. */
2770 if (match_operands_qualifier (inst, TRUE /* update_p */) == 0)
2771 {
2772 DEBUG_TRACE ("FAIL on operand qualifier matching");
2773 if (mismatch_detail)
2774 {
2775 /* Return an error type to indicate that it is the qualifier
2776 matching failure; we don't care about which operand as there
2777 are enough information in the opcode table to reproduce it. */
2778 mismatch_detail->kind = AARCH64_OPDE_INVALID_VARIANT;
2779 mismatch_detail->index = -1;
2780 mismatch_detail->error = NULL;
2781 }
2782 return 0;
2783 }
2784
2785 /* Match operands' constraint. */
2786 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2787 {
2788 enum aarch64_opnd type = inst->opcode->operands[i];
2789 if (type == AARCH64_OPND_NIL)
2790 break;
2791 if (inst->operands[i].skip)
2792 {
2793 DEBUG_TRACE ("skip the incomplete operand %d", i);
2794 continue;
2795 }
2796 if (operand_general_constraint_met_p (inst->operands, i, type,
2797 inst->opcode, mismatch_detail) == 0)
2798 {
2799 DEBUG_TRACE ("FAIL on operand %d", i);
2800 return 0;
2801 }
2802 }
2803
2804 DEBUG_TRACE ("PASS");
2805
2806 return 1;
2807}
2808
2809/* Replace INST->OPCODE with OPCODE and return the replaced OPCODE.
2810 Also updates the TYPE of each INST->OPERANDS with the corresponding
2811 value of OPCODE->OPERANDS.
2812
2813 Note that some operand qualifiers may need to be manually cleared by
2814 the caller before it further calls the aarch64_opcode_encode; by
2815 doing this, it helps the qualifier matching facilities work
2816 properly. */
2817
2818const aarch64_opcode*
2819aarch64_replace_opcode (aarch64_inst *inst, const aarch64_opcode *opcode)
2820{
2821 int i;
2822 const aarch64_opcode *old = inst->opcode;
2823
2824 inst->opcode = opcode;
2825
2826 /* Update the operand types. */
2827 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2828 {
2829 inst->operands[i].type = opcode->operands[i];
2830 if (opcode->operands[i] == AARCH64_OPND_NIL)
2831 break;
2832 }
2833
2834 DEBUG_TRACE ("replace %s with %s", old->name, opcode->name);
2835
2836 return old;
2837}
2838
2839int
2840aarch64_operand_index (const enum aarch64_opnd *operands, enum aarch64_opnd operand)
2841{
2842 int i;
2843 for (i = 0; i < AARCH64_MAX_OPND_NUM; ++i)
2844 if (operands[i] == operand)
2845 return i;
2846 else if (operands[i] == AARCH64_OPND_NIL)
2847 break;
2848 return -1;
2849}
2850\f
72e9f319
RS		 2851/* R0...R30, followed by FOR31. */
2852#define BANK(R, FOR31) \
2853 { R (0), R (1), R (2), R (3), R (4), R (5), R (6), R (7), \
2854 R (8), R (9), R (10), R (11), R (12), R (13), R (14), R (15), \
2855 R (16), R (17), R (18), R (19), R (20), R (21), R (22), R (23), \
2856 R (24), R (25), R (26), R (27), R (28), R (29), R (30), FOR31 }
a06ea964
NC		 2857/* [0][0] 32-bit integer regs with sp Wn
2858 [0][1] 64-bit integer regs with sp Xn sf=1
2859 [1][0] 32-bit integer regs with #0 Wn
2860 [1][1] 64-bit integer regs with #0 Xn sf=1 */
2861static const char *int_reg[2][2][32] = {
72e9f319
RS		 2862#define R32(X) "w" #X
2863#define R64(X) "x" #X
2864 { BANK (R32, "wsp"), BANK (R64, "sp") },
2865 { BANK (R32, "wzr"), BANK (R64, "xzr") }
a06ea964
NC		 2866#undef R64
2867#undef R32
2868};
4df068de
RS		 2869
2870/* Names of the SVE vector registers, first with .S suffixes,
2871 then with .D suffixes. */
2872
2873static const char *sve_reg[2][32] = {
2874#define ZS(X) "z" #X ".s"
2875#define ZD(X) "z" #X ".d"
2876 BANK (ZS, ZS (31)), BANK (ZD, ZD (31))
2877#undef ZD
2878#undef ZS
2879};
72e9f319 2880#undef BANK
a06ea964
NC		 2881
2882/* Return the integer register name.
2883 if SP_REG_P is not 0, R31 is an SP reg, other R31 is the zero reg. */
2884
2885static inline const char *
2886get_int_reg_name (int regno, aarch64_opnd_qualifier_t qualifier, int sp_reg_p)
2887{
2888 const int has_zr = sp_reg_p ? 0 : 1;
2889 const int is_64 = aarch64_get_qualifier_esize (qualifier) == 4 ? 0 : 1;
2890 return int_reg[has_zr][is_64][regno];
2891}
2892
2893/* Like get_int_reg_name, but IS_64 is always 1. */
2894
2895static inline const char *
2896get_64bit_int_reg_name (int regno, int sp_reg_p)
2897{
2898 const int has_zr = sp_reg_p ? 0 : 1;
2899 return int_reg[has_zr][1][regno];
2900}
2901
01dbfe4c
RS		 2902/* Get the name of the integer offset register in OPND, using the shift type
2903 to decide whether it's a word or doubleword. */
2904
2905static inline const char *
2906get_offset_int_reg_name (const aarch64_opnd_info *opnd)
2907{
2908 switch (opnd->shifter.kind)
2909 {
2910 case AARCH64_MOD_UXTW:
2911 case AARCH64_MOD_SXTW:
2912 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_W, 0);
2913
2914 case AARCH64_MOD_LSL:
2915 case AARCH64_MOD_SXTX:
2916 return get_int_reg_name (opnd->addr.offset.regno, AARCH64_OPND_QLF_X, 0);
2917
2918 default:
2919 abort ();
2920 }
2921}
2922
4df068de
RS		 2923/* Get the name of the SVE vector offset register in OPND, using the operand
2924 qualifier to decide whether the suffix should be .S or .D. */
2925
2926static inline const char *
2927get_addr_sve_reg_name (int regno, aarch64_opnd_qualifier_t qualifier)
2928{
2929 assert (qualifier == AARCH64_OPND_QLF_S_S
2930 || qualifier == AARCH64_OPND_QLF_S_D);
2931 return sve_reg[qualifier == AARCH64_OPND_QLF_S_D][regno];
2932}
2933
a06ea964
NC		 2934/* Types for expanding an encoded 8-bit value to a floating-point value. */
2935
2936typedef union
2937{
2938 uint64_t i;
2939 double d;
2940} double_conv_t;
2941
2942typedef union
2943{
2944 uint32_t i;
2945 float f;
2946} single_conv_t;
2947
cf86120b
MW		 2948typedef union
2949{
2950 uint32_t i;
2951 float f;
2952} half_conv_t;
2953
a06ea964
NC		 2954/* IMM8 is an 8-bit floating-point constant with sign, 3-bit exponent and
2955 normalized 4 bits of precision, encoded in "a:b:c:d:e:f:g:h" or FLD_imm8
2956 (depending on the type of the instruction). IMM8 will be expanded to a
cf86120b
MW		 2957 single-precision floating-point value (SIZE == 4) or a double-precision
2958 floating-point value (SIZE == 8). A half-precision floating-point value
2959 (SIZE == 2) is expanded to a single-precision floating-point value. The
2960 expanded value is returned. */
a06ea964
NC		 2961
2962static uint64_t
cf86120b 2963expand_fp_imm (int size, uint32_t imm8)
a06ea964 2964{
57a024f4 2965 uint64_t imm = 0;
a06ea964
NC		 2966 uint32_t imm8_7, imm8_6_0, imm8_6, imm8_6_repl4;
2967
2968 imm8_7 = (imm8 >> 7) & 0x01; /* imm8<7> */
2969 imm8_6_0 = imm8 & 0x7f; /* imm8<6:0> */
2970 imm8_6 = imm8_6_0 >> 6; /* imm8<6> */
2971 imm8_6_repl4 = (imm8_6 << 3) | (imm8_6 << 2)
2972 | (imm8_6 << 1) | imm8_6; /* Replicate(imm8<6>,4) */
cf86120b 2973 if (size == 8)
a06ea964
NC		 2974 {
2975 imm = (imm8_7 << (63-32)) /* imm8<7> */
2976 | ((imm8_6 ^ 1) << (62-32)) /* NOT(imm8<6) */
2977 | (imm8_6_repl4 << (58-32)) | (imm8_6 << (57-32))
2978 | (imm8_6 << (56-32)) | (imm8_6 << (55-32)) /* Replicate(imm8<6>,7) */
2979 | (imm8_6_0 << (48-32)); /* imm8<6>:imm8<5:0> */
2980 imm <<= 32;
2981 }
cf86120b 2982 else if (size == 4 || size == 2)
a06ea964
NC		 2983 {
2984 imm = (imm8_7 << 31) /* imm8<7> */
2985 | ((imm8_6 ^ 1) << 30) /* NOT(imm8<6>) */
2986 | (imm8_6_repl4 << 26) /* Replicate(imm8<6>,4) */
2987 | (imm8_6_0 << 19); /* imm8<6>:imm8<5:0> */
2988 }
cf86120b
MW		 2989 else
2990 {
2991 /* An unsupported size. */
2992 assert (0);
2993 }
a06ea964
NC		 2994
2995 return imm;
2996}
2997
2998/* Produce the string representation of the register list operand *OPND
8a7f0c1b
RS		 2999 in the buffer pointed by BUF of size SIZE. PREFIX is the part of
3000 the register name that comes before the register number, such as "v". */
a06ea964 3001static void
8a7f0c1b
RS		 3002print_register_list (char *buf, size_t size, const aarch64_opnd_info *opnd,
3003 const char *prefix)
a06ea964
NC		 3004{
3005 const int num_regs = opnd->reglist.num_regs;
3006 const int first_reg = opnd->reglist.first_regno;
3007 const int last_reg = (first_reg + num_regs - 1) & 0x1f;
3008 const char *qlf_name = aarch64_get_qualifier_name (opnd->qualifier);
3009 char tb[8]; /* Temporary buffer. */
3010
3011 assert (opnd->type != AARCH64_OPND_LEt || opnd->reglist.has_index);
3012 assert (num_regs >= 1 && num_regs <= 4);
3013
3014 /* Prepare the index if any. */
3015 if (opnd->reglist.has_index)
1b7e3d2f
NC		 3016 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3017 snprintf (tb, 8, "[%" PRIi64 "]", (opnd->reglist.index % 100));
a06ea964
NC		 3018 else
3019 tb[0] = '\0';
3020
3021 /* The hyphenated form is preferred for disassembly if there are
3022 more than two registers in the list, and the register numbers
3023 are monotonically increasing in increments of one. */
3024 if (num_regs > 2 && last_reg > first_reg)
8a7f0c1b
RS		 3025 snprintf (buf, size, "{%s%d.%s-%s%d.%s}%s", prefix, first_reg, qlf_name,
3026 prefix, last_reg, qlf_name, tb);
a06ea964
NC		 3027 else
3028 {
3029 const int reg0 = first_reg;
3030 const int reg1 = (first_reg + 1) & 0x1f;
3031 const int reg2 = (first_reg + 2) & 0x1f;
3032 const int reg3 = (first_reg + 3) & 0x1f;
3033
3034 switch (num_regs)
3035 {
3036 case 1:
8a7f0c1b 3037 snprintf (buf, size, "{%s%d.%s}%s", prefix, reg0, qlf_name, tb);
a06ea964
NC		 3038 break;
3039 case 2:
8a7f0c1b
RS		 3040 snprintf (buf, size, "{%s%d.%s, %s%d.%s}%s", prefix, reg0, qlf_name,
3041 prefix, reg1, qlf_name, tb);
a06ea964
NC		 3042 break;
3043 case 3:
8a7f0c1b
RS		 3044 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s}%s",
3045 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3046 prefix, reg2, qlf_name, tb);
a06ea964
NC		 3047 break;
3048 case 4:
8a7f0c1b
RS		 3049 snprintf (buf, size, "{%s%d.%s, %s%d.%s, %s%d.%s, %s%d.%s}%s",
3050 prefix, reg0, qlf_name, prefix, reg1, qlf_name,
3051 prefix, reg2, qlf_name, prefix, reg3, qlf_name, tb);
a06ea964
NC		 3052 break;
3053 }
3054 }
3055}
3056
01dbfe4c
RS		 3057/* Print the register+immediate address in OPND to BUF, which has SIZE
3058 characters. BASE is the name of the base register. */
3059
3060static void
3061print_immediate_offset_address (char *buf, size_t size,
3062 const aarch64_opnd_info *opnd,
3063 const char *base)
3064{
3065 if (opnd->addr.writeback)
3066 {
3067 if (opnd->addr.preind)
1820262b
DB		 3068 {
3069 if (opnd->type == AARCH64_OPND_ADDR_SIMM10 && !opnd->addr.offset.imm)
3070 snprintf (buf, size, "[%s]!", base);
3071 else
3072 snprintf (buf, size, "[%s, #%d]!", base, opnd->addr.offset.imm);
3073 }
01dbfe4c 3074 else
ad43e107 3075 snprintf (buf, size, "[%s], #%d", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3076 }
3077 else
3078 {
98907a70
RS		 3079 if (opnd->shifter.operator_present)
3080 {
3081 assert (opnd->shifter.kind == AARCH64_MOD_MUL_VL);
ad43e107 3082 snprintf (buf, size, "[%s, #%d, mul vl]",
98907a70
RS		 3083 base, opnd->addr.offset.imm);
3084 }
3085 else if (opnd->addr.offset.imm)
ad43e107 3086 snprintf (buf, size, "[%s, #%d]", base, opnd->addr.offset.imm);
01dbfe4c
RS		 3087 else
3088 snprintf (buf, size, "[%s]", base);
3089 }
3090}
3091
a06ea964 3092/* Produce the string representation of the register offset address operand
01dbfe4c
RS		 3093 *OPND in the buffer pointed by BUF of size SIZE. BASE and OFFSET are
3094 the names of the base and offset registers. */
a06ea964
NC		 3095static void
3096print_register_offset_address (char *buf, size_t size,
01dbfe4c
RS		 3097 const aarch64_opnd_info *opnd,
3098 const char *base, const char *offset)
a06ea964 3099{
0d2f91fe 3100 char tb[16]; /* Temporary buffer. */
a06ea964
NC		 3101 bfd_boolean print_extend_p = TRUE;
3102 bfd_boolean print_amount_p = TRUE;
3103 const char *shift_name = aarch64_operand_modifiers[opnd->shifter.kind].name;
3104
a06ea964
NC		 3105 if (!opnd->shifter.amount && (opnd->qualifier != AARCH64_OPND_QLF_S_B
3106 || !opnd->shifter.amount_present))
3107 {
3108 /* Not print the shift/extend amount when the amount is zero and
3109 when it is not the special case of 8-bit load/store instruction. */
3110 print_amount_p = FALSE;
3111 /* Likewise, no need to print the shift operator LSL in such a
3112 situation. */
01dbfe4c 3113 if (opnd->shifter.kind == AARCH64_MOD_LSL)
a06ea964
NC		 3114 print_extend_p = FALSE;
3115 }
3116
3117 /* Prepare for the extend/shift. */
3118 if (print_extend_p)
3119 {
3120 if (print_amount_p)
ad43e107 3121 snprintf (tb, sizeof (tb), ", %s #%" PRIi64, shift_name,
1b7e3d2f
NC		 3122 /* PR 21096: The %100 is to silence a warning about possible truncation. */
3123 (opnd->shifter.amount % 100));
a06ea964 3124 else
ad43e107 3125 snprintf (tb, sizeof (tb), ", %s", shift_name);
a06ea964
NC		 3126 }
3127 else
3128 tb[0] = '\0';
3129
ad43e107 3130 snprintf (buf, size, "[%s, %s%s]", base, offset, tb);
a06ea964
NC		 3131}
3132
3133/* Generate the string representation of the operand OPNDS[IDX] for OPCODE
3134 in *BUF. The caller should pass in the maximum size of *BUF in SIZE.
3135 PC, PCREL_P and ADDRESS are used to pass in and return information about
3136 the PC-relative address calculation, where the PC value is passed in
3137 PC. If the operand is pc-relative related, *PCREL_P (if PCREL_P non-NULL)
3138 will return 1 and *ADDRESS (if ADDRESS non-NULL) will return the
3139 calculated address; otherwise, *PCREL_P (if PCREL_P non-NULL) returns 0.
3140
3141 The function serves both the disassembler and the assembler diagnostics
3142 issuer, which is the reason why it lives in this file. */
3143
3144void
3145aarch64_print_operand (char *buf, size_t size, bfd_vma pc,
3146 const aarch64_opcode *opcode,
3147 const aarch64_opnd_info *opnds, int idx, int *pcrel_p,
bde90be2 3148 bfd_vma *address, char** notes)
a06ea964 3149{
bb7eff52 3150 unsigned int i, num_conds;
a06ea964
NC		 3151 const char *name = NULL;
3152 const aarch64_opnd_info *opnd = opnds + idx;
3153 enum aarch64_modifier_kind kind;
245d2e3f 3154 uint64_t addr, enum_value;
a06ea964
NC		 3155
3156 buf[0] = '\0';
3157 if (pcrel_p)
3158 *pcrel_p = 0;
3159
3160 switch (opnd->type)
3161 {
3162 case AARCH64_OPND_Rd:
3163 case AARCH64_OPND_Rn:
3164 case AARCH64_OPND_Rm:
3165 case AARCH64_OPND_Rt:
3166 case AARCH64_OPND_Rt2:
3167 case AARCH64_OPND_Rs:
3168 case AARCH64_OPND_Ra:
3169 case AARCH64_OPND_Rt_SYS:
ee804238 3170 case AARCH64_OPND_PAIRREG:
047cd301 3171 case AARCH64_OPND_SVE_Rm:
a06ea964 3172 /* The optional-ness of <Xt> in e.g. IC <ic_op>{, <Xt>} is determined by
de194d85 3173 the <ic_op>, therefore we use opnd->present to override the
a06ea964 3174 generic optional-ness information. */
362c0c4d
JW		 3175 if (opnd->type == AARCH64_OPND_Rt_SYS)
3176 {
3177 if (!opnd->present)
3178 break;
3179 }
a06ea964 3180 /* Omit the operand, e.g. RET. */
362c0c4d
JW		 3181 else if (optional_operand_p (opcode, idx)
3182 && (opnd->reg.regno
3183 == get_optional_operand_default_value (opcode)))
a06ea964
NC		 3184 break;
3185 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3186 || opnd->qualifier == AARCH64_OPND_QLF_X);
3187 snprintf (buf, size, "%s",
3188 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3189 break;
3190
3191 case AARCH64_OPND_Rd_SP:
3192 case AARCH64_OPND_Rn_SP:
bd7ceb8d 3193 case AARCH64_OPND_Rt_SP:
047cd301 3194 case AARCH64_OPND_SVE_Rn_SP:
c84364ec 3195 case AARCH64_OPND_Rm_SP:
a06ea964
NC		 3196 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3197 || opnd->qualifier == AARCH64_OPND_QLF_WSP
3198 || opnd->qualifier == AARCH64_OPND_QLF_X
3199 || opnd->qualifier == AARCH64_OPND_QLF_SP);
3200 snprintf (buf, size, "%s",
3201 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 1));
3202 break;
3203
3204 case AARCH64_OPND_Rm_EXT:
3205 kind = opnd->shifter.kind;
3206 assert (idx == 1 || idx == 2);
3207 if ((aarch64_stack_pointer_p (opnds)
3208 || (idx == 2 && aarch64_stack_pointer_p (opnds + 1)))
3209 && ((opnd->qualifier == AARCH64_OPND_QLF_W
3210 && opnds[0].qualifier == AARCH64_OPND_QLF_W
3211 && kind == AARCH64_MOD_UXTW)
3212 || (opnd->qualifier == AARCH64_OPND_QLF_X
3213 && kind == AARCH64_MOD_UXTX)))
3214 {
3215 /* 'LSL' is the preferred form in this case. */
3216 kind = AARCH64_MOD_LSL;
3217 if (opnd->shifter.amount == 0)
3218 {
3219 /* Shifter omitted. */
3220 snprintf (buf, size, "%s",
3221 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3222 break;
3223 }
3224 }
3225 if (opnd->shifter.amount)
2442d846 3226 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3227 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3228 aarch64_operand_modifiers[kind].name,
3229 opnd->shifter.amount);
3230 else
3231 snprintf (buf, size, "%s, %s",
3232 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3233 aarch64_operand_modifiers[kind].name);
3234 break;
3235
3236 case AARCH64_OPND_Rm_SFT:
3237 assert (opnd->qualifier == AARCH64_OPND_QLF_W
3238 || opnd->qualifier == AARCH64_OPND_QLF_X);
3239 if (opnd->shifter.amount == 0 && opnd->shifter.kind == AARCH64_MOD_LSL)
3240 snprintf (buf, size, "%s",
3241 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0));
3242 else
2442d846 3243 snprintf (buf, size, "%s, %s #%" PRIi64,
a06ea964
NC		 3244 get_int_reg_name (opnd->reg.regno, opnd->qualifier, 0),
3245 aarch64_operand_modifiers[opnd->shifter.kind].name,
3246 opnd->shifter.amount);
3247 break;
3248
3249 case AARCH64_OPND_Fd:
3250 case AARCH64_OPND_Fn:
3251 case AARCH64_OPND_Fm:
3252 case AARCH64_OPND_Fa:
3253 case AARCH64_OPND_Ft:
3254 case AARCH64_OPND_Ft2:
3255 case AARCH64_OPND_Sd:
3256 case AARCH64_OPND_Sn:
3257 case AARCH64_OPND_Sm:
047cd301
RS		 3258 case AARCH64_OPND_SVE_VZn:
3259 case AARCH64_OPND_SVE_Vd:
3260 case AARCH64_OPND_SVE_Vm:
3261 case AARCH64_OPND_SVE_Vn:
a06ea964
NC		 3262 snprintf (buf, size, "%s%d", aarch64_get_qualifier_name (opnd->qualifier),
3263 opnd->reg.regno);
3264 break;
3265
f42f1a1d 3266 case AARCH64_OPND_Va:
a06ea964
NC		 3267 case AARCH64_OPND_Vd:
3268 case AARCH64_OPND_Vn:
3269 case AARCH64_OPND_Vm:
3270 snprintf (buf, size, "v%d.%s", opnd->reg.regno,
3271 aarch64_get_qualifier_name (opnd->qualifier));
3272 break;
3273
3274 case AARCH64_OPND_Ed:
3275 case AARCH64_OPND_En:
3276 case AARCH64_OPND_Em:
369c9167 3277 case AARCH64_OPND_Em16:
f42f1a1d 3278 case AARCH64_OPND_SM3_IMM2:
dab26bf4 3279 snprintf (buf, size, "v%d.%s[%" PRIi64 "]", opnd->reglane.regno,
a06ea964
NC		 3280 aarch64_get_qualifier_name (opnd->qualifier),
3281 opnd->reglane.index);
3282 break;
3283
3284 case AARCH64_OPND_VdD1:
3285 case AARCH64_OPND_VnD1:
3286 snprintf (buf, size, "v%d.d[1]", opnd->reg.regno);
3287 break;
3288
3289 case AARCH64_OPND_LVn:
3290 case AARCH64_OPND_LVt:
3291 case AARCH64_OPND_LVt_AL:
3292 case AARCH64_OPND_LEt:
8a7f0c1b 3293 print_register_list (buf, size, opnd, "v");
a06ea964
NC		 3294 break;
3295
f11ad6bc
RS		 3296 case AARCH64_OPND_SVE_Pd:
3297 case AARCH64_OPND_SVE_Pg3:
3298 case AARCH64_OPND_SVE_Pg4_5:
3299 case AARCH64_OPND_SVE_Pg4_10:
3300 case AARCH64_OPND_SVE_Pg4_16:
3301 case AARCH64_OPND_SVE_Pm:
3302 case AARCH64_OPND_SVE_Pn:
3303 case AARCH64_OPND_SVE_Pt:
3304 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3305 snprintf (buf, size, "p%d", opnd->reg.regno);
d50c751e
RS		 3306 else if (opnd->qualifier == AARCH64_OPND_QLF_P_Z
3307 || opnd->qualifier == AARCH64_OPND_QLF_P_M)
3308 snprintf (buf, size, "p%d/%s", opnd->reg.regno,
3309 aarch64_get_qualifier_name (opnd->qualifier));
f11ad6bc
RS		 3310 else
3311 snprintf (buf, size, "p%d.%s", opnd->reg.regno,
3312 aarch64_get_qualifier_name (opnd->qualifier));
3313 break;
3314
3315 case AARCH64_OPND_SVE_Za_5:
3316 case AARCH64_OPND_SVE_Za_16:
3317 case AARCH64_OPND_SVE_Zd:
3318 case AARCH64_OPND_SVE_Zm_5:
3319 case AARCH64_OPND_SVE_Zm_16:
3320 case AARCH64_OPND_SVE_Zn:
3321 case AARCH64_OPND_SVE_Zt:
3322 if (opnd->qualifier == AARCH64_OPND_QLF_NIL)
3323 snprintf (buf, size, "z%d", opnd->reg.regno);
3324 else
3325 snprintf (buf, size, "z%d.%s", opnd->reg.regno,
3326 aarch64_get_qualifier_name (opnd->qualifier));
3327 break;
3328
3329 case AARCH64_OPND_SVE_ZnxN:
3330 case AARCH64_OPND_SVE_ZtxN:
3331 print_register_list (buf, size, opnd, "z");
3332 break;
3333
582e12bf
RS		 3334 case AARCH64_OPND_SVE_Zm3_INDEX:
3335 case AARCH64_OPND_SVE_Zm3_22_INDEX:
116adc27 3336 case AARCH64_OPND_SVE_Zm3_11_INDEX:
31e36ab3 3337 case AARCH64_OPND_SVE_Zm4_11_INDEX:
582e12bf 3338 case AARCH64_OPND_SVE_Zm4_INDEX:
f11ad6bc
RS		 3339 case AARCH64_OPND_SVE_Zn_INDEX:
3340 snprintf (buf, size, "z%d.%s[%" PRIi64 "]", opnd->reglane.regno,
3341 aarch64_get_qualifier_name (opnd->qualifier),
3342 opnd->reglane.index);
3343 break;
3344
a6a51754
RL		 3345 case AARCH64_OPND_CRn:
3346 case AARCH64_OPND_CRm:
3347 snprintf (buf, size, "C%" PRIi64, opnd->imm.value);
a06ea964
NC		 3348 break;
3349
3350 case AARCH64_OPND_IDX:
f42f1a1d 3351 case AARCH64_OPND_MASK:
a06ea964 3352 case AARCH64_OPND_IMM:
f42f1a1d 3353 case AARCH64_OPND_IMM_2:
a06ea964
NC		 3354 case AARCH64_OPND_WIDTH:
3355 case AARCH64_OPND_UIMM3_OP1:
3356 case AARCH64_OPND_UIMM3_OP2:
3357 case AARCH64_OPND_BIT_NUM:
3358 case AARCH64_OPND_IMM_VLSL:
3359 case AARCH64_OPND_IMM_VLSR:
3360 case AARCH64_OPND_SHLL_IMM:
3361 case AARCH64_OPND_IMM0:
3362 case AARCH64_OPND_IMMR:
3363 case AARCH64_OPND_IMMS:
3364 case AARCH64_OPND_FBITS:
b83b4b13 3365 case AARCH64_OPND_TME_UIMM16:
e950b345
RS		 3366 case AARCH64_OPND_SIMM5:
3367 case AARCH64_OPND_SVE_SHLIMM_PRED:
3368 case AARCH64_OPND_SVE_SHLIMM_UNPRED:
28ed815a 3369 case AARCH64_OPND_SVE_SHLIMM_UNPRED_22:
e950b345
RS		 3370 case AARCH64_OPND_SVE_SHRIMM_PRED:
3371 case AARCH64_OPND_SVE_SHRIMM_UNPRED:
3c17238b 3372 case AARCH64_OPND_SVE_SHRIMM_UNPRED_22:
e950b345
RS		 3373 case AARCH64_OPND_SVE_SIMM5:
3374 case AARCH64_OPND_SVE_SIMM5B:
3375 case AARCH64_OPND_SVE_SIMM6:
3376 case AARCH64_OPND_SVE_SIMM8:
3377 case AARCH64_OPND_SVE_UIMM3:
3378 case AARCH64_OPND_SVE_UIMM7:
3379 case AARCH64_OPND_SVE_UIMM8:
3380 case AARCH64_OPND_SVE_UIMM8_53:
c2c4ff8d
SN		 3381 case AARCH64_OPND_IMM_ROT1:
3382 case AARCH64_OPND_IMM_ROT2:
3383 case AARCH64_OPND_IMM_ROT3:
582e12bf
RS		 3384 case AARCH64_OPND_SVE_IMM_ROT1:
3385 case AARCH64_OPND_SVE_IMM_ROT2:
adccc507 3386 case AARCH64_OPND_SVE_IMM_ROT3:
a06ea964
NC		 3387 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3388 break;
3389
165d4950
RS		 3390 case AARCH64_OPND_SVE_I1_HALF_ONE:
3391 case AARCH64_OPND_SVE_I1_HALF_TWO:
3392 case AARCH64_OPND_SVE_I1_ZERO_ONE:
3393 {
3394 single_conv_t c;
3395 c.i = opnd->imm.value;
3396 snprintf (buf, size, "#%.1f", c.f);
3397 break;
3398 }
3399
245d2e3f
RS		 3400 case AARCH64_OPND_SVE_PATTERN:
3401 if (optional_operand_p (opcode, idx)
3402 && opnd->imm.value == get_optional_operand_default_value (opcode))
3403 break;
3404 enum_value = opnd->imm.value;
3405 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3406 if (aarch64_sve_pattern_array[enum_value])
3407 snprintf (buf, size, "%s", aarch64_sve_pattern_array[enum_value]);
3408 else
3409 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3410 break;
3411
2442d846
RS		 3412 case AARCH64_OPND_SVE_PATTERN_SCALED:
3413 if (optional_operand_p (opcode, idx)
3414 && !opnd->shifter.operator_present
3415 && opnd->imm.value == get_optional_operand_default_value (opcode))
3416 break;
3417 enum_value = opnd->imm.value;
3418 assert (enum_value < ARRAY_SIZE (aarch64_sve_pattern_array));
3419 if (aarch64_sve_pattern_array[opnd->imm.value])
3420 snprintf (buf, size, "%s", aarch64_sve_pattern_array[opnd->imm.value]);
3421 else
3422 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3423 if (opnd->shifter.operator_present)
3424 {
3425 size_t len = strlen (buf);
3426 snprintf (buf + len, size - len, ", %s #%" PRIi64,
3427 aarch64_operand_modifiers[opnd->shifter.kind].name,
3428 opnd->shifter.amount);
3429 }
3430 break;
3431
245d2e3f
RS		 3432 case AARCH64_OPND_SVE_PRFOP:
3433 enum_value = opnd->imm.value;
3434 assert (enum_value < ARRAY_SIZE (aarch64_sve_prfop_array));
3435 if (aarch64_sve_prfop_array[enum_value])
3436 snprintf (buf, size, "%s", aarch64_sve_prfop_array[enum_value]);
3437 else
3438 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3439 break;
3440
fb098a1e
YZ		 3441 case AARCH64_OPND_IMM_MOV:
3442 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3443 {
3444 case 4: /* e.g. MOV Wd, #<imm32>. */
3445 {
3446 int imm32 = opnd->imm.value;
3447 snprintf (buf, size, "#0x%-20x\t// #%d", imm32, imm32);
3448 }
3449 break;
3450 case 8: /* e.g. MOV Xd, #<imm64>. */
3451 snprintf (buf, size, "#0x%-20" PRIx64 "\t// #%" PRIi64,
3452 opnd->imm.value, opnd->imm.value);
3453 break;
3454 default: assert (0);
3455 }
3456 break;
3457
a06ea964
NC		 3458 case AARCH64_OPND_FPIMM0:
3459 snprintf (buf, size, "#0.0");
3460 break;
3461
3462 case AARCH64_OPND_LIMM:
3463 case AARCH64_OPND_AIMM:
3464 case AARCH64_OPND_HALF:
e950b345
RS		 3465 case AARCH64_OPND_SVE_INV_LIMM:
3466 case AARCH64_OPND_SVE_LIMM:
3467 case AARCH64_OPND_SVE_LIMM_MOV:
a06ea964 3468 if (opnd->shifter.amount)
2442d846 3469 snprintf (buf, size, "#0x%" PRIx64 ", lsl #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3470 opnd->shifter.amount);
3471 else
3472 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3473 break;
3474
3475 case AARCH64_OPND_SIMD_IMM:
3476 case AARCH64_OPND_SIMD_IMM_SFT:
3477 if ((! opnd->shifter.amount && opnd->shifter.kind == AARCH64_MOD_LSL)
3478 || opnd->shifter.kind == AARCH64_MOD_NONE)
3479 snprintf (buf, size, "#0x%" PRIx64, opnd->imm.value);
3480 else
2442d846 3481 snprintf (buf, size, "#0x%" PRIx64 ", %s #%" PRIi64, opnd->imm.value,
a06ea964
NC		 3482 aarch64_operand_modifiers[opnd->shifter.kind].name,
3483 opnd->shifter.amount);
3484 break;
3485
e950b345
RS		 3486 case AARCH64_OPND_SVE_AIMM:
3487 case AARCH64_OPND_SVE_ASIMM:
3488 if (opnd->shifter.amount)
3489 snprintf (buf, size, "#%" PRIi64 ", lsl #%" PRIi64, opnd->imm.value,
3490 opnd->shifter.amount);
3491 else
3492 snprintf (buf, size, "#%" PRIi64, opnd->imm.value);
3493 break;
3494
a06ea964
NC		 3495 case AARCH64_OPND_FPIMM:
3496 case AARCH64_OPND_SIMD_FPIMM:
165d4950 3497 case AARCH64_OPND_SVE_FPIMM8:
a06ea964
NC		 3498 switch (aarch64_get_qualifier_esize (opnds[0].qualifier))
3499 {
cf86120b
MW		 3500 case 2: /* e.g. FMOV <Hd>, #<imm>. */
3501 {
3502 half_conv_t c;
3503 c.i = expand_fp_imm (2, opnd->imm.value);
3504 snprintf (buf, size, "#%.18e", c.f);
3505 }
3506 break;
a06ea964
NC		 3507 case 4: /* e.g. FMOV <Vd>.4S, #<imm>. */
3508 {
3509 single_conv_t c;
cf86120b 3510 c.i = expand_fp_imm (4, opnd->imm.value);
a06ea964
NC		 3511 snprintf (buf, size, "#%.18e", c.f);
3512 }
3513 break;
3514 case 8: /* e.g. FMOV <Sd>, #<imm>. */
3515 {
3516 double_conv_t c;
cf86120b 3517 c.i = expand_fp_imm (8, opnd->imm.value);
a06ea964
NC		 3518 snprintf (buf, size, "#%.18e", c.d);
3519 }
3520 break;
3521 default: assert (0);
3522 }
3523 break;
3524
3525 case AARCH64_OPND_CCMP_IMM:
3526 case AARCH64_OPND_NZCV:
3527 case AARCH64_OPND_EXCEPTION:
3528 case AARCH64_OPND_UIMM4:
193614f2 3529 case AARCH64_OPND_UIMM4_ADDG:
a06ea964 3530 case AARCH64_OPND_UIMM7:
193614f2 3531 case AARCH64_OPND_UIMM10:
a06ea964
NC		 3532 if (optional_operand_p (opcode, idx) == TRUE
3533 && (opnd->imm.value ==
3534 (int64_t) get_optional_operand_default_value (opcode)))
3535 /* Omit the operand, e.g. DCPS1. */
3536 break;
3537 snprintf (buf, size, "#0x%x", (unsigned int)opnd->imm.value);
3538 break;
3539
3540 case AARCH64_OPND_COND:
68a64283 3541 case AARCH64_OPND_COND1:
a06ea964 3542 snprintf (buf, size, "%s", opnd->cond->names[0]);
bb7eff52
RS		 3543 num_conds = ARRAY_SIZE (opnd->cond->names);
3544 for (i = 1; i < num_conds && opnd->cond->names[i]; ++i)
3545 {
3546 size_t len = strlen (buf);
3547 if (i == 1)
3548 snprintf (buf + len, size - len, " // %s = %s",
3549 opnd->cond->names[0], opnd->cond->names[i]);
3550 else
3551 snprintf (buf + len, size - len, ", %s",
3552 opnd->cond->names[i]);
3553 }
a06ea964
NC		 3554 break;
3555
3556 case AARCH64_OPND_ADDR_ADRP:
3557 addr = ((pc + AARCH64_PCREL_OFFSET) & ~(uint64_t)0xfff)
3558 + opnd->imm.value;
3559 if (pcrel_p)
3560 *pcrel_p = 1;
3561 if (address)
3562 *address = addr;
3563 /* This is not necessary during the disassembling, as print_address_func
3564 in the disassemble_info will take care of the printing. But some
3565 other callers may be still interested in getting the string in *STR,
3566 so here we do snprintf regardless. */
3567 snprintf (buf, size, "#0x%" PRIx64, addr);
3568 break;
3569
3570 case AARCH64_OPND_ADDR_PCREL14:
3571 case AARCH64_OPND_ADDR_PCREL19:
3572 case AARCH64_OPND_ADDR_PCREL21:
3573 case AARCH64_OPND_ADDR_PCREL26:
3574 addr = pc + AARCH64_PCREL_OFFSET + opnd->imm.value;
3575 if (pcrel_p)
3576 *pcrel_p = 1;
3577 if (address)
3578 *address = addr;
3579 /* This is not necessary during the disassembling, as print_address_func
3580 in the disassemble_info will take care of the printing. But some
3581 other callers may be still interested in getting the string in *STR,
3582 so here we do snprintf regardless. */
3583 snprintf (buf, size, "#0x%" PRIx64, addr);
3584 break;
3585
3586 case AARCH64_OPND_ADDR_SIMPLE:
3587 case AARCH64_OPND_SIMD_ADDR_SIMPLE:
3588 case AARCH64_OPND_SIMD_ADDR_POST:
3589 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3590 if (opnd->type == AARCH64_OPND_SIMD_ADDR_POST)
3591 {
3592 if (opnd->addr.offset.is_reg)
3593 snprintf (buf, size, "[%s], x%d", name, opnd->addr.offset.regno);
3594 else
3595 snprintf (buf, size, "[%s], #%d", name, opnd->addr.offset.imm);
3596 }
3597 else
3598 snprintf (buf, size, "[%s]", name);
3599 break;
3600
3601 case AARCH64_OPND_ADDR_REGOFF:
c8d59609 3602 case AARCH64_OPND_SVE_ADDR_R:
4df068de
RS		 3603 case AARCH64_OPND_SVE_ADDR_RR:
3604 case AARCH64_OPND_SVE_ADDR_RR_LSL1:
3605 case AARCH64_OPND_SVE_ADDR_RR_LSL2:
3606 case AARCH64_OPND_SVE_ADDR_RR_LSL3:
3607 case AARCH64_OPND_SVE_ADDR_RX:
3608 case AARCH64_OPND_SVE_ADDR_RX_LSL1:
3609 case AARCH64_OPND_SVE_ADDR_RX_LSL2:
3610 case AARCH64_OPND_SVE_ADDR_RX_LSL3:
01dbfe4c
RS		 3611 print_register_offset_address
3612 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3613 get_offset_int_reg_name (opnd));
a06ea964
NC		 3614 break;
3615
c469c864
MM		 3616 case AARCH64_OPND_SVE_ADDR_ZX:
3617 print_register_offset_address
3618 (buf, size, opnd,
3619 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3620 get_64bit_int_reg_name (opnd->addr.offset.regno, 0));
3621 break;
3622
4df068de
RS		 3623 case AARCH64_OPND_SVE_ADDR_RZ:
3624 case AARCH64_OPND_SVE_ADDR_RZ_LSL1:
3625 case AARCH64_OPND_SVE_ADDR_RZ_LSL2:
3626 case AARCH64_OPND_SVE_ADDR_RZ_LSL3:
3627 case AARCH64_OPND_SVE_ADDR_RZ_XTW_14:
3628 case AARCH64_OPND_SVE_ADDR_RZ_XTW_22:
3629 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_14:
3630 case AARCH64_OPND_SVE_ADDR_RZ_XTW1_22:
3631 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_14:
3632 case AARCH64_OPND_SVE_ADDR_RZ_XTW2_22:
3633 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_14:
3634 case AARCH64_OPND_SVE_ADDR_RZ_XTW3_22:
3635 print_register_offset_address
3636 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1),
3637 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3638 break;
3639
a06ea964
NC		 3640 case AARCH64_OPND_ADDR_SIMM7:
3641 case AARCH64_OPND_ADDR_SIMM9:
3642 case AARCH64_OPND_ADDR_SIMM9_2:
3f06e550 3643 case AARCH64_OPND_ADDR_SIMM10:
fb3265b3
SD		 3644 case AARCH64_OPND_ADDR_SIMM11:
3645 case AARCH64_OPND_ADDR_SIMM13:
f42f1a1d 3646 case AARCH64_OPND_ADDR_OFFSET:
582e12bf 3647 case AARCH64_OPND_SVE_ADDR_RI_S4x16:
8382113f 3648 case AARCH64_OPND_SVE_ADDR_RI_S4x32:
98907a70
RS		 3649 case AARCH64_OPND_SVE_ADDR_RI_S4xVL:
3650 case AARCH64_OPND_SVE_ADDR_RI_S4x2xVL:
3651 case AARCH64_OPND_SVE_ADDR_RI_S4x3xVL:
3652 case AARCH64_OPND_SVE_ADDR_RI_S4x4xVL:
3653 case AARCH64_OPND_SVE_ADDR_RI_S6xVL:
3654 case AARCH64_OPND_SVE_ADDR_RI_S9xVL:
4df068de
RS		 3655 case AARCH64_OPND_SVE_ADDR_RI_U6:
3656 case AARCH64_OPND_SVE_ADDR_RI_U6x2:
3657 case AARCH64_OPND_SVE_ADDR_RI_U6x4:
3658 case AARCH64_OPND_SVE_ADDR_RI_U6x8:
01dbfe4c
RS		 3659 print_immediate_offset_address
3660 (buf, size, opnd, get_64bit_int_reg_name (opnd->addr.base_regno, 1));
a06ea964
NC		 3661 break;
3662
4df068de
RS		 3663 case AARCH64_OPND_SVE_ADDR_ZI_U5:
3664 case AARCH64_OPND_SVE_ADDR_ZI_U5x2:
3665 case AARCH64_OPND_SVE_ADDR_ZI_U5x4:
3666 case AARCH64_OPND_SVE_ADDR_ZI_U5x8:
3667 print_immediate_offset_address
3668 (buf, size, opnd,
3669 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier));
3670 break;
3671
3672 case AARCH64_OPND_SVE_ADDR_ZZ_LSL:
3673 case AARCH64_OPND_SVE_ADDR_ZZ_SXTW:
3674 case AARCH64_OPND_SVE_ADDR_ZZ_UXTW:
3675 print_register_offset_address
3676 (buf, size, opnd,
3677 get_addr_sve_reg_name (opnd->addr.base_regno, opnd->qualifier),
3678 get_addr_sve_reg_name (opnd->addr.offset.regno, opnd->qualifier));
3679 break;
3680
a06ea964
NC		 3681 case AARCH64_OPND_ADDR_UIMM12:
3682 name = get_64bit_int_reg_name (opnd->addr.base_regno, 1);
3683 if (opnd->addr.offset.imm)
ad43e107 3684 snprintf (buf, size, "[%s, #%d]", name, opnd->addr.offset.imm);
a06ea964
NC		 3685 else
3686 snprintf (buf, size, "[%s]", name);
3687 break;
3688
3689 case AARCH64_OPND_SYSREG:
3690 for (i = 0; aarch64_sys_regs[i].name; ++i)
f9830ec1
TC		 3691 {
3692 bfd_boolean exact_match
3693 = (aarch64_sys_regs[i].flags & opnd->sysreg.flags)
3694 == opnd->sysreg.flags;
3695
3696 /* Try and find an exact match, But if that fails, return the first
3697 partial match that was found. */
3698 if (aarch64_sys_regs[i].value == opnd->sysreg.value
3699 && ! aarch64_sys_reg_deprecated_p (&aarch64_sys_regs[i])
3700 && (name == NULL || exact_match))
3701 {
3702 name = aarch64_sys_regs[i].name;
3703 if (exact_match)
3704 {
3705 if (notes)
3706 *notes = NULL;
3707 break;
3708 }
3709
3710 /* If we didn't match exactly, that means the presense of a flag
3711 indicates what we didn't want for this instruction. e.g. If
3712 F_REG_READ is there, that means we were looking for a write
3713 register. See aarch64_ext_sysreg. */
3714 if (aarch64_sys_regs[i].flags & F_REG_WRITE)
bde90be2 3715 *notes = _("reading from a write-only register");
f9830ec1 3716 else if (aarch64_sys_regs[i].flags & F_REG_READ)
bde90be2 3717 *notes = _("writing to a read-only register");
f9830ec1
TC		 3718 }
3719 }
3720
3721 if (name)
3722 snprintf (buf, size, "%s", name);
a06ea964
NC		 3723 else
3724 {
3725 /* Implementation defined system register. */
561a72d4 3726 unsigned int value = opnd->sysreg.value;
a06ea964
NC		 3727 snprintf (buf, size, "s%u_%u_c%u_c%u_%u", (value >> 14) & 0x3,
3728 (value >> 11) & 0x7, (value >> 7) & 0xf, (value >> 3) & 0xf,
3729 value & 0x7);
3730 }
3731 break;
3732
3733 case AARCH64_OPND_PSTATEFIELD:
3734 for (i = 0; aarch64_pstatefields[i].name; ++i)
3735 if (aarch64_pstatefields[i].value == opnd->pstatefield)
3736 break;
3737 assert (aarch64_pstatefields[i].name);
3738 snprintf (buf, size, "%s", aarch64_pstatefields[i].name);
3739 break;
3740
3741 case AARCH64_OPND_SYSREG_AT:
3742 case AARCH64_OPND_SYSREG_DC:
3743 case AARCH64_OPND_SYSREG_IC:
3744 case AARCH64_OPND_SYSREG_TLBI:
2ac435d4 3745 case AARCH64_OPND_SYSREG_SR:
875880c6 3746 snprintf (buf, size, "%s", opnd->sysins_op->name);
a06ea964
NC		 3747 break;
3748
3749 case AARCH64_OPND_BARRIER:
3750 snprintf (buf, size, "%s", opnd->barrier->name);
3751 break;
3752
3753 case AARCH64_OPND_BARRIER_ISB:
3754 /* Operand can be omitted, e.g. in DCPS1. */
3755 if (! optional_operand_p (opcode, idx)
3756 || (opnd->barrier->value
3757 != get_optional_operand_default_value (opcode)))
3758 snprintf (buf, size, "#0x%x", opnd->barrier->value);
3759 break;
3760
3761 case AARCH64_OPND_PRFOP:
a1ccaec9
YZ		 3762 if (opnd->prfop->name != NULL)
3763 snprintf (buf, size, "%s", opnd->prfop->name);
3764 else
3765 snprintf (buf, size, "#0x%02x", opnd->prfop->value);
a06ea964
NC		 3766 break;
3767
1e6f4800 3768 case AARCH64_OPND_BARRIER_PSB:
ff605452
SD		 3769 case AARCH64_OPND_BTI_TARGET:
3770 if ((HINT_FLAG (opnd->hint_option->value) & HINT_OPD_F_NOPRINT) == 0)
3771 snprintf (buf, size, "%s", opnd->hint_option->name);
1e6f4800
MW		 3772 break;
3773
a06ea964
NC		 3774 default:
3775 assert (0);
3776 }
3777}
3778\f
3779#define CPENC(op0,op1,crn,crm,op2) \
3780 ((((op0) << 19) | ((op1) << 16) | ((crn) << 12) | ((crm) << 8) | ((op2) << 5)) >> 5)
3781 /* for 3.9.3 Instructions for Accessing Special Purpose Registers */
3782#define CPEN_(op1,crm,op2) CPENC(3,(op1),4,(crm),(op2))
3783 /* for 3.9.10 System Instructions */
3784#define CPENS(op1,crn,crm,op2) CPENC(1,(op1),(crn),(crm),(op2))
3785
3786#define C0 0
3787#define C1 1
3788#define C2 2
3789#define C3 3
3790#define C4 4
3791#define C5 5
3792#define C6 6
3793#define C7 7
3794#define C8 8
3795#define C9 9
3796#define C10 10
3797#define C11 11
3798#define C12 12
3799#define C13 13
3800#define C14 14
3801#define C15 15
3802
f9830ec1
TC		 3803/* TODO there is one more issues need to be resolved
3804 1. handle cpu-implementation-defined system registers. */
49eec193
YZ		 3805const aarch64_sys_reg aarch64_sys_regs [] =
3806{
3807 { "spsr_el1", CPEN_(0,C0,0), 0 }, /* = spsr_svc */
250aafa4 3808 { "spsr_el12", CPEN_ (5, C0, 0), F_ARCHEXT },
49eec193 3809 { "elr_el1", CPEN_(0,C0,1), 0 },
250aafa4 3810 { "elr_el12", CPEN_ (5, C0, 1), F_ARCHEXT },
49eec193
YZ		 3811 { "sp_el0", CPEN_(0,C1,0), 0 },
3812 { "spsel", CPEN_(0,C2,0), 0 },
3813 { "daif", CPEN_(3,C2,1), 0 },
f9830ec1 3814 { "currentel", CPEN_(0,C2,2), F_REG_READ }, /* RO */
f21cce2c 3815 { "pan", CPEN_(0,C2,3), F_ARCHEXT },
6479e48e 3816 { "uao", CPEN_ (0, C2, 4), F_ARCHEXT },
49eec193 3817 { "nzcv", CPEN_(3,C2,0), 0 },
104fefee 3818 { "ssbs", CPEN_(3,C2,6), F_ARCHEXT },
49eec193
YZ		 3819 { "fpcr", CPEN_(3,C4,0), 0 },
3820 { "fpsr", CPEN_(3,C4,1), 0 },
3821 { "dspsr_el0", CPEN_(3,C5,0), 0 },
3822 { "dlr_el0", CPEN_(3,C5,1), 0 },
3823 { "spsr_el2", CPEN_(4,C0,0), 0 }, /* = spsr_hyp */
3824 { "elr_el2", CPEN_(4,C0,1), 0 },
3825 { "sp_el1", CPEN_(4,C1,0), 0 },
3826 { "spsr_irq", CPEN_(4,C3,0), 0 },
3827 { "spsr_abt", CPEN_(4,C3,1), 0 },
3828 { "spsr_und", CPEN_(4,C3,2), 0 },
3829 { "spsr_fiq", CPEN_(4,C3,3), 0 },
3830 { "spsr_el3", CPEN_(6,C0,0), 0 },
3831 { "elr_el3", CPEN_(6,C0,1), 0 },
3832 { "sp_el2", CPEN_(6,C1,0), 0 },
3833 { "spsr_svc", CPEN_(0,C0,0), F_DEPRECATED }, /* = spsr_el1 */
3834 { "spsr_hyp", CPEN_(4,C0,0), F_DEPRECATED }, /* = spsr_el2 */
f9830ec1
TC		 3835 { "midr_el1", CPENC(3,0,C0,C0,0), F_REG_READ }, /* RO */
3836 { "ctr_el0", CPENC(3,3,C0,C0,1), F_REG_READ }, /* RO */
3837 { "mpidr_el1", CPENC(3,0,C0,C0,5), F_REG_READ }, /* RO */
3838 { "revidr_el1", CPENC(3,0,C0,C0,6), F_REG_READ }, /* RO */
3839 { "aidr_el1", CPENC(3,1,C0,C0,7), F_REG_READ }, /* RO */
3840 { "dczid_el0", CPENC(3,3,C0,C0,7), F_REG_READ }, /* RO */
3841 { "id_dfr0_el1", CPENC(3,0,C0,C1,2), F_REG_READ }, /* RO */
3842 { "id_pfr0_el1", CPENC(3,0,C0,C1,0), F_REG_READ }, /* RO */
3843 { "id_pfr1_el1", CPENC(3,0,C0,C1,1), F_REG_READ }, /* RO */
a97330e7 3844 { "id_pfr2_el1", CPENC(3,0,C0,C3,4), F_ARCHEXT | F_REG_READ}, /* RO */
f9830ec1
TC		 3845 { "id_afr0_el1", CPENC(3,0,C0,C1,3), F_REG_READ }, /* RO */
3846 { "id_mmfr0_el1", CPENC(3,0,C0,C1,4), F_REG_READ }, /* RO */
3847 { "id_mmfr1_el1", CPENC(3,0,C0,C1,5), F_REG_READ }, /* RO */
3848 { "id_mmfr2_el1", CPENC(3,0,C0,C1,6), F_REG_READ }, /* RO */
3849 { "id_mmfr3_el1", CPENC(3,0,C0,C1,7), F_REG_READ }, /* RO */
3850 { "id_mmfr4_el1", CPENC(3,0,C0,C2,6), F_REG_READ }, /* RO */
3851 { "id_isar0_el1", CPENC(3,0,C0,C2,0), F_REG_READ }, /* RO */
3852 { "id_isar1_el1", CPENC(3,0,C0,C2,1), F_REG_READ }, /* RO */
3853 { "id_isar2_el1", CPENC(3,0,C0,C2,2), F_REG_READ }, /* RO */
3854 { "id_isar3_el1", CPENC(3,0,C0,C2,3), F_REG_READ }, /* RO */
3855 { "id_isar4_el1", CPENC(3,0,C0,C2,4), F_REG_READ }, /* RO */
3856 { "id_isar5_el1", CPENC(3,0,C0,C2,5), F_REG_READ }, /* RO */
3857 { "mvfr0_el1", CPENC(3,0,C0,C3,0), F_REG_READ }, /* RO */
3858 { "mvfr1_el1", CPENC(3,0,C0,C3,1), F_REG_READ }, /* RO */
3859 { "mvfr2_el1", CPENC(3,0,C0,C3,2), F_REG_READ }, /* RO */
3860 { "ccsidr_el1", CPENC(3,1,C0,C0,0), F_REG_READ }, /* RO */
3861 { "id_aa64pfr0_el1", CPENC(3,0,C0,C4,0), F_REG_READ }, /* RO */
3862 { "id_aa64pfr1_el1", CPENC(3,0,C0,C4,1), F_REG_READ }, /* RO */
3863 { "id_aa64dfr0_el1", CPENC(3,0,C0,C5,0), F_REG_READ }, /* RO */
3864 { "id_aa64dfr1_el1", CPENC(3,0,C0,C5,1), F_REG_READ }, /* RO */
3865 { "id_aa64isar0_el1", CPENC(3,0,C0,C6,0), F_REG_READ }, /* RO */
3866 { "id_aa64isar1_el1", CPENC(3,0,C0,C6,1), F_REG_READ }, /* RO */
3867 { "id_aa64mmfr0_el1", CPENC(3,0,C0,C7,0), F_REG_READ }, /* RO */
3868 { "id_aa64mmfr1_el1", CPENC(3,0,C0,C7,1), F_REG_READ }, /* RO */
3869 { "id_aa64mmfr2_el1", CPENC (3, 0, C0, C7, 2), F_ARCHEXT | F_REG_READ }, /* RO */
3870 { "id_aa64afr0_el1", CPENC(3,0,C0,C5,4), F_REG_READ }, /* RO */
3871 { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */
3872 { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */
3873 { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */
cba05feb 3874 { "csselr_el1", CPENC(3,2,C0,C0,0), 0 },
49eec193
YZ		 3875 { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 },
3876 { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 },
3877 { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 },
3878 { "sctlr_el2", CPENC(3,4,C1,C0,0), 0 },
3879 { "sctlr_el3", CPENC(3,6,C1,C0,0), 0 },
250aafa4 3880 { "sctlr_el12", CPENC (3, 5, C1, C0, 0), F_ARCHEXT },
49eec193
YZ		 3881 { "actlr_el1", CPENC(3,0,C1,C0,1), 0 },
3882 { "actlr_el2", CPENC(3,4,C1,C0,1), 0 },
3883 { "actlr_el3", CPENC(3,6,C1,C0,1), 0 },
3884 { "cpacr_el1", CPENC(3,0,C1,C0,2), 0 },
250aafa4 3885 { "cpacr_el12", CPENC (3, 5, C1, C0, 2), F_ARCHEXT },
49eec193
YZ		 3886 { "cptr_el2", CPENC(3,4,C1,C1,2), 0 },
3887 { "cptr_el3", CPENC(3,6,C1,C1,2), 0 },
3888 { "scr_el3", CPENC(3,6,C1,C1,0), 0 },
3889 { "hcr_el2", CPENC(3,4,C1,C1,0), 0 },
3890 { "mdcr_el2", CPENC(3,4,C1,C1,1), 0 },
3891 { "mdcr_el3", CPENC(3,6,C1,C3,1), 0 },
3892 { "hstr_el2", CPENC(3,4,C1,C1,3), 0 },
3893 { "hacr_el2", CPENC(3,4,C1,C1,7), 0 },
773fb663
RS		 3894 { "zcr_el1", CPENC (3, 0, C1, C2, 0), F_ARCHEXT },
3895 { "zcr_el12", CPENC (3, 5, C1, C2, 0), F_ARCHEXT },
3896 { "zcr_el2", CPENC (3, 4, C1, C2, 0), F_ARCHEXT },
3897 { "zcr_el3", CPENC (3, 6, C1, C2, 0), F_ARCHEXT },
3898 { "zidr_el1", CPENC (3, 0, C0, C0, 7), F_ARCHEXT },
49eec193
YZ		 3899 { "ttbr0_el1", CPENC(3,0,C2,C0,0), 0 },
3900 { "ttbr1_el1", CPENC(3,0,C2,C0,1), 0 },
3901 { "ttbr0_el2", CPENC(3,4,C2,C0,0), 0 },
250aafa4 3902 { "ttbr1_el2", CPENC (3, 4, C2, C0, 1), F_ARCHEXT },
49eec193 3903 { "ttbr0_el3", CPENC(3,6,C2,C0,0), 0 },
250aafa4
MW		 3904 { "ttbr0_el12", CPENC (3, 5, C2, C0, 0), F_ARCHEXT },
3905 { "ttbr1_el12", CPENC (3, 5, C2, C0, 1), F_ARCHEXT },
49eec193
YZ		 3906 { "vttbr_el2", CPENC(3,4,C2,C1,0), 0 },
3907 { "tcr_el1", CPENC(3,0,C2,C0,2), 0 },
3908 { "tcr_el2", CPENC(3,4,C2,C0,2), 0 },
3909 { "tcr_el3", CPENC(3,6,C2,C0,2), 0 },
250aafa4 3910 { "tcr_el12", CPENC (3, 5, C2, C0, 2), F_ARCHEXT },
49eec193 3911 { "vtcr_el2", CPENC(3,4,C2,C1,2), 0 },
b0bfa7b5
SN		 3912 { "apiakeylo_el1", CPENC (3, 0, C2, C1, 0), F_ARCHEXT },
3913 { "apiakeyhi_el1", CPENC (3, 0, C2, C1, 1), F_ARCHEXT },
3914 { "apibkeylo_el1", CPENC (3, 0, C2, C1, 2), F_ARCHEXT },
3915 { "apibkeyhi_el1", CPENC (3, 0, C2, C1, 3), F_ARCHEXT },
3916 { "apdakeylo_el1", CPENC (3, 0, C2, C2, 0), F_ARCHEXT },
3917 { "apdakeyhi_el1", CPENC (3, 0, C2, C2, 1), F_ARCHEXT },
3918 { "apdbkeylo_el1", CPENC (3, 0, C2, C2, 2), F_ARCHEXT },
3919 { "apdbkeyhi_el1", CPENC (3, 0, C2, C2, 3), F_ARCHEXT },
3920 { "apgakeylo_el1", CPENC (3, 0, C2, C3, 0), F_ARCHEXT },
3921 { "apgakeyhi_el1", CPENC (3, 0, C2, C3, 1), F_ARCHEXT },
49eec193
YZ		 3922 { "afsr0_el1", CPENC(3,0,C5,C1,0), 0 },
3923 { "afsr1_el1", CPENC(3,0,C5,C1,1), 0 },
3924 { "afsr0_el2", CPENC(3,4,C5,C1,0), 0 },
3925 { "afsr1_el2", CPENC(3,4,C5,C1,1), 0 },
3926 { "afsr0_el3", CPENC(3,6,C5,C1,0), 0 },
250aafa4 3927 { "afsr0_el12", CPENC (3, 5, C5, C1, 0), F_ARCHEXT },
49eec193 3928 { "afsr1_el3", CPENC(3,6,C5,C1,1), 0 },
250aafa4 3929 { "afsr1_el12", CPENC (3, 5, C5, C1, 1), F_ARCHEXT },
49eec193
YZ		 3930 { "esr_el1", CPENC(3,0,C5,C2,0), 0 },
3931 { "esr_el2", CPENC(3,4,C5,C2,0), 0 },
3932 { "esr_el3", CPENC(3,6,C5,C2,0), 0 },
250aafa4 3933 { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT },
cba05feb 3934 { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT },
49eec193 3935 { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 },
f9830ec1 3936 { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142 3937 { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT },
f9830ec1 3938 { "erxfr_el1", CPENC (3, 0, C5, C4, 0), F_ARCHEXT | F_REG_READ }, /* RO */
47f81142
MW		 3939 { "erxctlr_el1", CPENC (3, 0, C5, C4, 1), F_ARCHEXT },
3940 { "erxstatus_el1", CPENC (3, 0, C5, C4, 2), F_ARCHEXT },
3941 { "erxaddr_el1", CPENC (3, 0, C5, C4, 3), F_ARCHEXT },
3942 { "erxmisc0_el1", CPENC (3, 0, C5, C5, 0), F_ARCHEXT },
3943 { "erxmisc1_el1", CPENC (3, 0, C5, C5, 1), F_ARCHEXT },
49eec193
YZ		 3944 { "far_el1", CPENC(3,0,C6,C0,0), 0 },
3945 { "far_el2", CPENC(3,4,C6,C0,0), 0 },
3946 { "far_el3", CPENC(3,6,C6,C0,0), 0 },
250aafa4 3947 { "far_el12", CPENC (3, 5, C6, C0, 0), F_ARCHEXT },
49eec193
YZ		 3948 { "hpfar_el2", CPENC(3,4,C6,C0,4), 0 },
3949 { "par_el1", CPENC(3,0,C7,C4,0), 0 },
3950 { "mair_el1", CPENC(3,0,C10,C2,0), 0 },
3951 { "mair_el2", CPENC(3,4,C10,C2,0), 0 },
3952 { "mair_el3", CPENC(3,6,C10,C2,0), 0 },
250aafa4 3953 { "mair_el12", CPENC (3, 5, C10, C2, 0), F_ARCHEXT },
49eec193
YZ		 3954 { "amair_el1", CPENC(3,0,C10,C3,0), 0 },
3955 { "amair_el2", CPENC(3,4,C10,C3,0), 0 },
3956 { "amair_el3", CPENC(3,6,C10,C3,0), 0 },
250aafa4 3957 { "amair_el12", CPENC (3, 5, C10, C3, 0), F_ARCHEXT },
49eec193
YZ		 3958 { "vbar_el1", CPENC(3,0,C12,C0,0), 0 },
3959 { "vbar_el2", CPENC(3,4,C12,C0,0), 0 },
3960 { "vbar_el3", CPENC(3,6,C12,C0,0), 0 },
250aafa4 3961 { "vbar_el12", CPENC (3, 5, C12, C0, 0), F_ARCHEXT },
f9830ec1
TC		 3962 { "rvbar_el1", CPENC(3,0,C12,C0,1), F_REG_READ }, /* RO */
3963 { "rvbar_el2", CPENC(3,4,C12,C0,1), F_REG_READ }, /* RO */
3964 { "rvbar_el3", CPENC(3,6,C12,C0,1), F_REG_READ }, /* RO */
49eec193
YZ		 3965 { "rmr_el1", CPENC(3,0,C12,C0,2), 0 },
3966 { "rmr_el2", CPENC(3,4,C12,C0,2), 0 },
3967 { "rmr_el3", CPENC(3,6,C12,C0,2), 0 },
f9830ec1 3968 { "isr_el1", CPENC(3,0,C12,C1,0), F_REG_READ }, /* RO */
47f81142
MW		 3969 { "disr_el1", CPENC (3, 0, C12, C1, 1), F_ARCHEXT },
3970 { "vdisr_el2", CPENC (3, 4, C12, C1, 1), F_ARCHEXT },
49eec193 3971 { "contextidr_el1", CPENC(3,0,C13,C0,1), 0 },
250aafa4
MW		 3972 { "contextidr_el2", CPENC (3, 4, C13, C0, 1), F_ARCHEXT },
3973 { "contextidr_el12", CPENC (3, 5, C13, C0, 1), F_ARCHEXT },
af4bcb4c
SD		 3974 { "rndr", CPENC(3,3,C2,C4,0), F_ARCHEXT | F_REG_READ }, /* RO */
3975 { "rndrrs", CPENC(3,3,C2,C4,1), F_ARCHEXT | F_REG_READ }, /* RO */
70f3d23a 3976 { "tco", CPENC(3,3,C4,C2,7), F_ARCHEXT },
a051e2f3
KT		 3977 { "tfsre0_el1", CPENC(3,0,C5,C6,1), F_ARCHEXT },
3978 { "tfsr_el1", CPENC(3,0,C5,C6,0), F_ARCHEXT },
3979 { "tfsr_el2", CPENC(3,4,C5,C6,0), F_ARCHEXT },
3980 { "tfsr_el3", CPENC(3,6,C5,C6,0), F_ARCHEXT },
3981 { "tfsr_el12", CPENC(3,5,C5,C6,0), F_ARCHEXT },
70f3d23a
SD		 3982 { "rgsr_el1", CPENC(3,0,C1,C0,5), F_ARCHEXT },
3983 { "gcr_el1", CPENC(3,0,C1,C0,6), F_ARCHEXT },
a028026d 3984 { "gmid_el1", CPENC(3,1,C0,C0,4), F_ARCHEXT | F_REG_READ }, /* RO */
49eec193 3985 { "tpidr_el0", CPENC(3,3,C13,C0,2), 0 },
f9830ec1 3986 { "tpidrro_el0", CPENC(3,3,C13,C0,3), 0 }, /* RW */
49eec193
YZ		 3987 { "tpidr_el1", CPENC(3,0,C13,C0,4), 0 },
3988 { "tpidr_el2", CPENC(3,4,C13,C0,2), 0 },
3989 { "tpidr_el3", CPENC(3,6,C13,C0,2), 0 },
a97330e7
SD		 3990 { "scxtnum_el0", CPENC(3,3,C13,C0,7), F_ARCHEXT },
3991 { "scxtnum_el1", CPENC(3,0,C13,C0,7), F_ARCHEXT },
3992 { "scxtnum_el2", CPENC(3,4,C13,C0,7), F_ARCHEXT },
3993 { "scxtnum_el12", CPENC(3,5,C13,C0,7), F_ARCHEXT },
3994 { "scxtnum_el3", CPENC(3,6,C13,C0,7), F_ARCHEXT },
49eec193 3995 { "teecr32_el1", CPENC(2,2,C0, C0,0), 0 }, /* See section 3.9.7.1 */
f9830ec1
TC		 3996 { "cntfrq_el0", CPENC(3,3,C14,C0,0), 0 }, /* RW */
3997 { "cntpct_el0", CPENC(3,3,C14,C0,1), F_REG_READ }, /* RO */
3998 { "cntvct_el0", CPENC(3,3,C14,C0,2), F_REG_READ }, /* RO */
49eec193
YZ		 3999 { "cntvoff_el2", CPENC(3,4,C14,C0,3), 0 },
4000 { "cntkctl_el1", CPENC(3,0,C14,C1,0), 0 },
250aafa4 4001 { "cntkctl_el12", CPENC (3, 5, C14, C1, 0), F_ARCHEXT },
49eec193
YZ		 4002 { "cnthctl_el2", CPENC(3,4,C14,C1,0), 0 },
4003 { "cntp_tval_el0", CPENC(3,3,C14,C2,0), 0 },
250aafa4 4004 { "cntp_tval_el02", CPENC (3, 5, C14, C2, 0), F_ARCHEXT },
49eec193 4005 { "cntp_ctl_el0", CPENC(3,3,C14,C2,1), 0 },
250aafa4 4006 { "cntp_ctl_el02", CPENC (3, 5, C14, C2, 1), F_ARCHEXT },
49eec193 4007 { "cntp_cval_el0", CPENC(3,3,C14,C2,2), 0 },
250aafa4 4008 { "cntp_cval_el02", CPENC (3, 5, C14, C2, 2), F_ARCHEXT },
49eec193 4009 { "cntv_tval_el0", CPENC(3,3,C14,C3,0), 0 },
250aafa4 4010 { "cntv_tval_el02", CPENC (3, 5, C14, C3, 0), F_ARCHEXT },
49eec193 4011 { "cntv_ctl_el0", CPENC(3,3,C14,C3,1), 0 },
250aafa4 4012 { "cntv_ctl_el02", CPENC (3, 5, C14, C3, 1), F_ARCHEXT },
49eec193 4013 { "cntv_cval_el0", CPENC(3,3,C14,C3,2), 0 },
250aafa4 4014 { "cntv_cval_el02", CPENC (3, 5, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 4015 { "cnthp_tval_el2", CPENC(3,4,C14,C2,0), 0 },
4016 { "cnthp_ctl_el2", CPENC(3,4,C14,C2,1), 0 },
4017 { "cnthp_cval_el2", CPENC(3,4,C14,C2,2), 0 },
4018 { "cntps_tval_el1", CPENC(3,7,C14,C2,0), 0 },
4019 { "cntps_ctl_el1", CPENC(3,7,C14,C2,1), 0 },
4020 { "cntps_cval_el1", CPENC(3,7,C14,C2,2), 0 },
250aafa4
MW		 4021 { "cnthv_tval_el2", CPENC (3, 4, C14, C3, 0), F_ARCHEXT },
4022 { "cnthv_ctl_el2", CPENC (3, 4, C14, C3, 1), F_ARCHEXT },
4023 { "cnthv_cval_el2", CPENC (3, 4, C14, C3, 2), F_ARCHEXT },
49eec193
YZ		 4024 { "dacr32_el2", CPENC(3,4,C3,C0,0), 0 },
4025 { "ifsr32_el2", CPENC(3,4,C5,C0,1), 0 },
4026 { "teehbr32_el1", CPENC(2,2,C1,C0,0), 0 },
4027 { "sder32_el3", CPENC(3,6,C1,C1,1), 0 },
4028 { "mdscr_el1", CPENC(2,0,C0, C2, 2), 0 },
f9830ec1 4029 { "mdccsr_el0", CPENC(2,3,C0, C1, 0), F_REG_READ }, /* r */
49eec193
YZ		 4030 { "mdccint_el1", CPENC(2,0,C0, C2, 0), 0 },
4031 { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 },
f9830ec1
TC		 4032 { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */
4033 { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */
cba05feb
TC		 4034 { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 },
4035 { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 },
49eec193
YZ		 4036 { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 },
4037 { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 },
4038 { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 },
4039 { "dbgbvr1_el1", CPENC(2,0,C0, C1, 4), 0 },
4040 { "dbgbvr2_el1", CPENC(2,0,C0, C2, 4), 0 },
4041 { "dbgbvr3_el1", CPENC(2,0,C0, C3, 4), 0 },
4042 { "dbgbvr4_el1", CPENC(2,0,C0, C4, 4), 0 },
4043 { "dbgbvr5_el1", CPENC(2,0,C0, C5, 4), 0 },
4044 { "dbgbvr6_el1", CPENC(2,0,C0, C6, 4), 0 },
4045 { "dbgbvr7_el1", CPENC(2,0,C0, C7, 4), 0 },
4046 { "dbgbvr8_el1", CPENC(2,0,C0, C8, 4), 0 },
4047 { "dbgbvr9_el1", CPENC(2,0,C0, C9, 4), 0 },
4048 { "dbgbvr10_el1", CPENC(2,0,C0, C10,4), 0 },
4049 { "dbgbvr11_el1", CPENC(2,0,C0, C11,4), 0 },
4050 { "dbgbvr12_el1", CPENC(2,0,C0, C12,4), 0 },
4051 { "dbgbvr13_el1", CPENC(2,0,C0, C13,4), 0 },
4052 { "dbgbvr14_el1", CPENC(2,0,C0, C14,4), 0 },
4053 { "dbgbvr15_el1", CPENC(2,0,C0, C15,4), 0 },
4054 { "dbgbcr0_el1", CPENC(2,0,C0, C0, 5), 0 },
4055 { "dbgbcr1_el1", CPENC(2,0,C0, C1, 5), 0 },
4056 { "dbgbcr2_el1", CPENC(2,0,C0, C2, 5), 0 },
4057 { "dbgbcr3_el1", CPENC(2,0,C0, C3, 5), 0 },
4058 { "dbgbcr4_el1", CPENC(2,0,C0, C4, 5), 0 },
4059 { "dbgbcr5_el1", CPENC(2,0,C0, C5, 5), 0 },
4060 { "dbgbcr6_el1", CPENC(2,0,C0, C6, 5), 0 },
4061 { "dbgbcr7_el1", CPENC(2,0,C0, C7, 5), 0 },
4062 { "dbgbcr8_el1", CPENC(2,0,C0, C8, 5), 0 },
4063 { "dbgbcr9_el1", CPENC(2,0,C0, C9, 5), 0 },
4064 { "dbgbcr10_el1", CPENC(2,0,C0, C10,5), 0 },
4065 { "dbgbcr11_el1", CPENC(2,0,C0, C11,5), 0 },
4066 { "dbgbcr12_el1", CPENC(2,0,C0, C12,5), 0 },
4067 { "dbgbcr13_el1", CPENC(2,0,C0, C13,5), 0 },
4068 { "dbgbcr14_el1", CPENC(2,0,C0, C14,5), 0 },
4069 { "dbgbcr15_el1", CPENC(2,0,C0, C15,5), 0 },
4070 { "dbgwvr0_el1", CPENC(2,0,C0, C0, 6), 0 },
4071 { "dbgwvr1_el1", CPENC(2,0,C0, C1, 6), 0 },
4072 { "dbgwvr2_el1", CPENC(2,0,C0, C2, 6), 0 },
4073 { "dbgwvr3_el1", CPENC(2,0,C0, C3, 6), 0 },
4074 { "dbgwvr4_el1", CPENC(2,0,C0, C4, 6), 0 },
4075 { "dbgwvr5_el1", CPENC(2,0,C0, C5, 6), 0 },
4076 { "dbgwvr6_el1", CPENC(2,0,C0, C6, 6), 0 },
4077 { "dbgwvr7_el1", CPENC(2,0,C0, C7, 6), 0 },
4078 { "dbgwvr8_el1", CPENC(2,0,C0, C8, 6), 0 },
4079 { "dbgwvr9_el1", CPENC(2,0,C0, C9, 6), 0 },
4080 { "dbgwvr10_el1", CPENC(2,0,C0, C10,6), 0 },
4081 { "dbgwvr11_el1", CPENC(2,0,C0, C11,6), 0 },
4082 { "dbgwvr12_el1", CPENC(2,0,C0, C12,6), 0 },
4083 { "dbgwvr13_el1", CPENC(2,0,C0, C13,6), 0 },
4084 { "dbgwvr14_el1", CPENC(2,0,C0, C14,6), 0 },
4085 { "dbgwvr15_el1", CPENC(2,0,C0, C15,6), 0 },
4086 { "dbgwcr0_el1", CPENC(2,0,C0, C0, 7), 0 },
4087 { "dbgwcr1_el1", CPENC(2,0,C0, C1, 7), 0 },
4088 { "dbgwcr2_el1", CPENC(2,0,C0, C2, 7), 0 },
4089 { "dbgwcr3_el1", CPENC(2,0,C0, C3, 7), 0 },
4090 { "dbgwcr4_el1", CPENC(2,0,C0, C4, 7), 0 },
4091 { "dbgwcr5_el1", CPENC(2,0,C0, C5, 7), 0 },
4092 { "dbgwcr6_el1", CPENC(2,0,C0, C6, 7), 0 },
4093 { "dbgwcr7_el1", CPENC(2,0,C0, C7, 7), 0 },
4094 { "dbgwcr8_el1", CPENC(2,0,C0, C8, 7), 0 },
4095 { "dbgwcr9_el1", CPENC(2,0,C0, C9, 7), 0 },
4096 { "dbgwcr10_el1", CPENC(2,0,C0, C10,7), 0 },
4097 { "dbgwcr11_el1", CPENC(2,0,C0, C11,7), 0 },
4098 { "dbgwcr12_el1", CPENC(2,0,C0, C12,7), 0 },
4099 { "dbgwcr13_el1", CPENC(2,0,C0, C13,7), 0 },
4100 { "dbgwcr14_el1", CPENC(2,0,C0, C14,7), 0 },
4101 { "dbgwcr15_el1", CPENC(2,0,C0, C15,7), 0 },
f9830ec1
TC		 4102 { "mdrar_el1", CPENC(2,0,C1, C0, 0), F_REG_READ }, /* r */
4103 { "oslar_el1", CPENC(2,0,C1, C0, 4), F_REG_WRITE }, /* w */
4104 { "oslsr_el1", CPENC(2,0,C1, C1, 4), F_REG_READ }, /* r */
49eec193
YZ		 4105 { "osdlr_el1", CPENC(2,0,C1, C3, 4), 0 },
4106 { "dbgprcr_el1", CPENC(2,0,C1, C4, 4), 0 },
4107 { "dbgclaimset_el1", CPENC(2,0,C7, C8, 6), 0 },
4108 { "dbgclaimclr_el1", CPENC(2,0,C7, C9, 6), 0 },
f9830ec1 4109 { "dbgauthstatus_el1", CPENC(2,0,C7, C14,6), F_REG_READ }, /* r */
55c144e6
MW		 4110 { "pmblimitr_el1", CPENC (3, 0, C9, C10, 0), F_ARCHEXT }, /* rw */
4111 { "pmbptr_el1", CPENC (3, 0, C9, C10, 1), F_ARCHEXT }, /* rw */
4112 { "pmbsr_el1", CPENC (3, 0, C9, C10, 3), F_ARCHEXT }, /* rw */
f9830ec1 4113 { "pmbidr_el1", CPENC (3, 0, C9, C10, 7), F_ARCHEXT | F_REG_READ }, /* ro */
55c144e6
MW		 4114 { "pmscr_el1", CPENC (3, 0, C9, C9, 0), F_ARCHEXT }, /* rw */
4115 { "pmsicr_el1", CPENC (3, 0, C9, C9, 2), F_ARCHEXT }, /* rw */
4116 { "pmsirr_el1", CPENC (3, 0, C9, C9, 3), F_ARCHEXT }, /* rw */
4117 { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */
4118 { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */
4119 { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */
cba05feb 4120 { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */
55c144e6
MW		 4121 { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */
4122 { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */
49eec193
YZ		 4123 { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 },
4124 { "pmcntenset_el0", CPENC(3,3,C9,C12, 1), 0 },
4125 { "pmcntenclr_el0", CPENC(3,3,C9,C12, 2), 0 },
4126 { "pmovsclr_el0", CPENC(3,3,C9,C12, 3), 0 },
f9830ec1 4127 { "pmswinc_el0", CPENC(3,3,C9,C12, 4), F_REG_WRITE }, /* w */
49eec193 4128 { "pmselr_el0", CPENC(3,3,C9,C12, 5), 0 },
f9830ec1
TC		 4129 { "pmceid0_el0", CPENC(3,3,C9,C12, 6), F_REG_READ }, /* r */
4130 { "pmceid1_el0", CPENC(3,3,C9,C12, 7), F_REG_READ }, /* r */
49eec193
YZ		 4131 { "pmccntr_el0", CPENC(3,3,C9,C13, 0), 0 },
4132 { "pmxevtyper_el0", CPENC(3,3,C9,C13, 1), 0 },
4133 { "pmxevcntr_el0", CPENC(3,3,C9,C13, 2), 0 },
4134 { "pmuserenr_el0", CPENC(3,3,C9,C14, 0), 0 },
4135 { "pmintenset_el1", CPENC(3,0,C9,C14, 1), 0 },
4136 { "pmintenclr_el1", CPENC(3,0,C9,C14, 2), 0 },
4137 { "pmovsset_el0", CPENC(3,3,C9,C14, 3), 0 },
4138 { "pmevcntr0_el0", CPENC(3,3,C14,C8, 0), 0 },
4139 { "pmevcntr1_el0", CPENC(3,3,C14,C8, 1), 0 },
4140 { "pmevcntr2_el0", CPENC(3,3,C14,C8, 2), 0 },
4141 { "pmevcntr3_el0", CPENC(3,3,C14,C8, 3), 0 },
4142 { "pmevcntr4_el0", CPENC(3,3,C14,C8, 4), 0 },
4143 { "pmevcntr5_el0", CPENC(3,3,C14,C8, 5), 0 },
4144 { "pmevcntr6_el0", CPENC(3,3,C14,C8, 6), 0 },
4145 { "pmevcntr7_el0", CPENC(3,3,C14,C8, 7), 0 },
4146 { "pmevcntr8_el0", CPENC(3,3,C14,C9, 0), 0 },
4147 { "pmevcntr9_el0", CPENC(3,3,C14,C9, 1), 0 },
4148 { "pmevcntr10_el0", CPENC(3,3,C14,C9, 2), 0 },
4149 { "pmevcntr11_el0", CPENC(3,3,C14,C9, 3), 0 },
4150 { "pmevcntr12_el0", CPENC(3,3,C14,C9, 4), 0 },
4151 { "pmevcntr13_el0", CPENC(3,3,C14,C9, 5), 0 },
4152 { "pmevcntr14_el0", CPENC(3,3,C14,C9, 6), 0 },
4153 { "pmevcntr15_el0", CPENC(3,3,C14,C9, 7), 0 },
4154 { "pmevcntr16_el0", CPENC(3,3,C14,C10,0), 0 },
4155 { "pmevcntr17_el0", CPENC(3,3,C14,C10,1), 0 },
4156 { "pmevcntr18_el0", CPENC(3,3,C14,C10,2), 0 },
4157 { "pmevcntr19_el0", CPENC(3,3,C14,C10,3), 0 },
4158 { "pmevcntr20_el0", CPENC(3,3,C14,C10,4), 0 },
4159 { "pmevcntr21_el0", CPENC(3,3,C14,C10,5), 0 },
4160 { "pmevcntr22_el0", CPENC(3,3,C14,C10,6), 0 },
4161 { "pmevcntr23_el0", CPENC(3,3,C14,C10,7), 0 },
4162 { "pmevcntr24_el0", CPENC(3,3,C14,C11,0), 0 },
4163 { "pmevcntr25_el0", CPENC(3,3,C14,C11,1), 0 },
4164 { "pmevcntr26_el0", CPENC(3,3,C14,C11,2), 0 },
4165 { "pmevcntr27_el0", CPENC(3,3,C14,C11,3), 0 },
4166 { "pmevcntr28_el0", CPENC(3,3,C14,C11,4), 0 },
4167 { "pmevcntr29_el0", CPENC(3,3,C14,C11,5), 0 },
4168 { "pmevcntr30_el0", CPENC(3,3,C14,C11,6), 0 },
4169 { "pmevtyper0_el0", CPENC(3,3,C14,C12,0), 0 },
4170 { "pmevtyper1_el0", CPENC(3,3,C14,C12,1), 0 },
4171 { "pmevtyper2_el0", CPENC(3,3,C14,C12,2), 0 },
4172 { "pmevtyper3_el0", CPENC(3,3,C14,C12,3), 0 },
4173 { "pmevtyper4_el0", CPENC(3,3,C14,C12,4), 0 },
4174 { "pmevtyper5_el0", CPENC(3,3,C14,C12,5), 0 },
4175 { "pmevtyper6_el0", CPENC(3,3,C14,C12,6), 0 },
4176 { "pmevtyper7_el0", CPENC(3,3,C14,C12,7), 0 },
4177 { "pmevtyper8_el0", CPENC(3,3,C14,C13,0), 0 },
4178 { "pmevtyper9_el0", CPENC(3,3,C14,C13,1), 0 },
4179 { "pmevtyper10_el0", CPENC(3,3,C14,C13,2), 0 },
4180 { "pmevtyper11_el0", CPENC(3,3,C14,C13,3), 0 },
4181 { "pmevtyper12_el0", CPENC(3,3,C14,C13,4), 0 },
4182 { "pmevtyper13_el0", CPENC(3,3,C14,C13,5), 0 },
4183 { "pmevtyper14_el0", CPENC(3,3,C14,C13,6), 0 },
4184 { "pmevtyper15_el0", CPENC(3,3,C14,C13,7), 0 },
4185 { "pmevtyper16_el0", CPENC(3,3,C14,C14,0), 0 },
4186 { "pmevtyper17_el0", CPENC(3,3,C14,C14,1), 0 },
4187 { "pmevtyper18_el0", CPENC(3,3,C14,C14,2), 0 },
4188 { "pmevtyper19_el0", CPENC(3,3,C14,C14,3), 0 },
4189 { "pmevtyper20_el0", CPENC(3,3,C14,C14,4), 0 },
4190 { "pmevtyper21_el0", CPENC(3,3,C14,C14,5), 0 },
4191 { "pmevtyper22_el0", CPENC(3,3,C14,C14,6), 0 },
4192 { "pmevtyper23_el0", CPENC(3,3,C14,C14,7), 0 },
4193 { "pmevtyper24_el0", CPENC(3,3,C14,C15,0), 0 },
4194 { "pmevtyper25_el0", CPENC(3,3,C14,C15,1), 0 },
4195 { "pmevtyper26_el0", CPENC(3,3,C14,C15,2), 0 },
4196 { "pmevtyper27_el0", CPENC(3,3,C14,C15,3), 0 },
4197 { "pmevtyper28_el0", CPENC(3,3,C14,C15,4), 0 },
4198 { "pmevtyper29_el0", CPENC(3,3,C14,C15,5), 0 },
4199 { "pmevtyper30_el0", CPENC(3,3,C14,C15,6), 0 },
4200 { "pmccfiltr_el0", CPENC(3,3,C14,C15,7), 0 },
793a1948
TC		 4201
4202 { "dit", CPEN_ (3, C2, 5), F_ARCHEXT },
4203 { "vstcr_el2", CPENC(3, 4, C2, C6, 2), F_ARCHEXT },
4204 { "vsttbr_el2", CPENC(3, 4, C2, C6, 0), F_ARCHEXT },
4205 { "cnthvs_tval_el2", CPENC(3, 4, C14, C4, 0), F_ARCHEXT },
4206 { "cnthvs_cval_el2", CPENC(3, 4, C14, C4, 2), F_ARCHEXT },
4207 { "cnthvs_ctl_el2", CPENC(3, 4, C14, C4, 1), F_ARCHEXT },
4208 { "cnthps_tval_el2", CPENC(3, 4, C14, C5, 0), F_ARCHEXT },
4209 { "cnthps_cval_el2", CPENC(3, 4, C14, C5, 2), F_ARCHEXT },
4210 { "cnthps_ctl_el2", CPENC(3, 4, C14, C5, 1), F_ARCHEXT },
4211 { "sder32_el2", CPENC(3, 4, C1, C3, 1), F_ARCHEXT },
4212 { "vncr_el2", CPENC(3, 4, C2, C2, 0), F_ARCHEXT },
49eec193 4213 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4214};
4215
49eec193
YZ		 4216bfd_boolean
4217aarch64_sys_reg_deprecated_p (const aarch64_sys_reg *reg)
4218{
4219 return (reg->flags & F_DEPRECATED) != 0;
4220}
4221
f21cce2c
MW		 4222bfd_boolean
4223aarch64_sys_reg_supported_p (const aarch64_feature_set features,
4224 const aarch64_sys_reg *reg)
4225{
4226 if (!(reg->flags & F_ARCHEXT))
4227 return TRUE;
4228
4229 /* PAN. Values are from aarch64_sys_regs. */
4230 if (reg->value == CPEN_(0,C2,3)
4231 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4232 return FALSE;
4233
a97330e7
SD		 4234 /* SCXTNUM_ELx registers. */
4235 if ((reg->value == CPENC (3, 3, C13, C0, 7)
4236 || reg->value == CPENC (3, 0, C13, C0, 7)
4237 || reg->value == CPENC (3, 4, C13, C0, 7)
4238 || reg->value == CPENC (3, 6, C13, C0, 7)
4239 || reg->value == CPENC (3, 5, C13, C0, 7))
4240 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SCXTNUM))
4241 return FALSE;
4242
4243 /* ID_PFR2_EL1 register. */
4244 if (reg->value == CPENC(3, 0, C0, C3, 4)
4245 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_ID_PFR2))
4246 return FALSE;
4247
104fefee
SD		 4248 /* SSBS. Values are from aarch64_sys_regs. */
4249 if (reg->value == CPEN_(3,C2,6)
4250 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4251 return FALSE;
4252
250aafa4
MW		 4253 /* Virtualization host extensions: system registers. */
4254 if ((reg->value == CPENC (3, 4, C2, C0, 1)
4255 || reg->value == CPENC (3, 4, C13, C0, 1)
4256 || reg->value == CPENC (3, 4, C14, C3, 0)
4257 || reg->value == CPENC (3, 4, C14, C3, 1)
4258 || reg->value == CPENC (3, 4, C14, C3, 2))
4259 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4260 return FALSE;
4261
4262 /* Virtualization host extensions: *_el12 names of *_el1 registers. */
4263 if ((reg->value == CPEN_ (5, C0, 0)
4264 || reg->value == CPEN_ (5, C0, 1)
4265 || reg->value == CPENC (3, 5, C1, C0, 0)
4266 || reg->value == CPENC (3, 5, C1, C0, 2)
4267 || reg->value == CPENC (3, 5, C2, C0, 0)
4268 || reg->value == CPENC (3, 5, C2, C0, 1)
4269 || reg->value == CPENC (3, 5, C2, C0, 2)
4270 || reg->value == CPENC (3, 5, C5, C1, 0)
4271 || reg->value == CPENC (3, 5, C5, C1, 1)
4272 || reg->value == CPENC (3, 5, C5, C2, 0)
4273 || reg->value == CPENC (3, 5, C6, C0, 0)
4274 || reg->value == CPENC (3, 5, C10, C2, 0)
4275 || reg->value == CPENC (3, 5, C10, C3, 0)
4276 || reg->value == CPENC (3, 5, C12, C0, 0)
4277 || reg->value == CPENC (3, 5, C13, C0, 1)
4278 || reg->value == CPENC (3, 5, C14, C1, 0))
4279 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
4280 return FALSE;
4281
4282 /* Virtualization host extensions: *_el02 names of *_el0 registers. */
4283 if ((reg->value == CPENC (3, 5, C14, C2, 0)
4284 || reg->value == CPENC (3, 5, C14, C2, 1)
4285 || reg->value == CPENC (3, 5, C14, C2, 2)
4286 || reg->value == CPENC (3, 5, C14, C3, 0)
4287 || reg->value == CPENC (3, 5, C14, C3, 1)
4288 || reg->value == CPENC (3, 5, C14, C3, 2))
4289 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_1))
63511907 4290 return FALSE;
1a04d1a7
MW		 4291
4292 /* ARMv8.2 features. */
6479e48e
MW		 4293
4294 /* ID_AA64MMFR2_EL1. */
1a04d1a7
MW		 4295 if (reg->value == CPENC (3, 0, C0, C7, 2)
4296 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
250aafa4
MW		 4297 return FALSE;
4298
6479e48e
MW		 4299 /* PSTATE.UAO. */
4300 if (reg->value == CPEN_ (0, C2, 4)
4301 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4302 return FALSE;
4303
47f81142
MW		 4304 /* RAS extension. */
4305
651657fa
MW		 4306 /* ERRIDR_EL1, ERRSELR_EL1, ERXFR_EL1, ERXCTLR_EL1, ERXSTATUS_EL, ERXADDR_EL1,
4307 ERXMISC0_EL1 AND ERXMISC1_EL1. */
47f81142 4308 if ((reg->value == CPENC (3, 0, C5, C3, 0)
651657fa 4309 || reg->value == CPENC (3, 0, C5, C3, 1)
47f81142
MW		 4310 || reg->value == CPENC (3, 0, C5, C3, 2)
4311 || reg->value == CPENC (3, 0, C5, C3, 3)
651657fa
MW		 4312 || reg->value == CPENC (3, 0, C5, C4, 0)
4313 || reg->value == CPENC (3, 0, C5, C4, 1)
4314 || reg->value == CPENC (3, 0, C5, C4, 2)
4315 || reg->value == CPENC (3, 0, C5, C4, 3)
47f81142
MW		 4316 || reg->value == CPENC (3, 0, C5, C5, 0)
4317 || reg->value == CPENC (3, 0, C5, C5, 1))
4318 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4319 return FALSE;
4320
4321 /* VSESR_EL2, DISR_EL1 and VDISR_EL2. */
4322 if ((reg->value == CPENC (3, 4, C5, C2, 3)
4323 || reg->value == CPENC (3, 0, C12, C1, 1)
4324 || reg->value == CPENC (3, 4, C12, C1, 1))
4325 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RAS))
4326 return FALSE;
4327
55c144e6
MW		 4328 /* Statistical Profiling extension. */
4329 if ((reg->value == CPENC (3, 0, C9, C10, 0)
4330 || reg->value == CPENC (3, 0, C9, C10, 1)
4331 || reg->value == CPENC (3, 0, C9, C10, 3)
4332 || reg->value == CPENC (3, 0, C9, C10, 7)
4333 || reg->value == CPENC (3, 0, C9, C9, 0)
4334 || reg->value == CPENC (3, 0, C9, C9, 2)
4335 || reg->value == CPENC (3, 0, C9, C9, 3)
4336 || reg->value == CPENC (3, 0, C9, C9, 4)
4337 || reg->value == CPENC (3, 0, C9, C9, 5)
4338 || reg->value == CPENC (3, 0, C9, C9, 6)
4339 || reg->value == CPENC (3, 0, C9, C9, 7)
4340 || reg->value == CPENC (3, 4, C9, C9, 0)
4341 || reg->value == CPENC (3, 5, C9, C9, 0))
4342 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PROFILE))
4343 return FALSE;
4344
b0bfa7b5
SN		 4345 /* ARMv8.3 Pointer authentication keys. */
4346 if ((reg->value == CPENC (3, 0, C2, C1, 0)
4347 || reg->value == CPENC (3, 0, C2, C1, 1)
4348 || reg->value == CPENC (3, 0, C2, C1, 2)
4349 || reg->value == CPENC (3, 0, C2, C1, 3)
4350 || reg->value == CPENC (3, 0, C2, C2, 0)
4351 || reg->value == CPENC (3, 0, C2, C2, 1)
4352 || reg->value == CPENC (3, 0, C2, C2, 2)
4353 || reg->value == CPENC (3, 0, C2, C2, 3)
4354 || reg->value == CPENC (3, 0, C2, C3, 0)
4355 || reg->value == CPENC (3, 0, C2, C3, 1))
4356 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_3))
4357 return FALSE;
4358
773fb663
RS		 4359 /* SVE. */
4360 if ((reg->value == CPENC (3, 0, C0, C4, 4)
4361 || reg->value == CPENC (3, 0, C1, C2, 0)
4362 || reg->value == CPENC (3, 4, C1, C2, 0)
4363 || reg->value == CPENC (3, 6, C1, C2, 0)
4364 || reg->value == CPENC (3, 5, C1, C2, 0)
4365 || reg->value == CPENC (3, 0, C0, C0, 7))
4366 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SVE))
4367 return FALSE;
4368
793a1948
TC		 4369 /* ARMv8.4 features. */
4370
4371 /* PSTATE.DIT. */
4372 if (reg->value == CPEN_ (3, C2, 5)
4373 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4374 return FALSE;
4375
4376 /* Virtualization extensions. */
4377 if ((reg->value == CPENC(3, 4, C2, C6, 2)
4378 || reg->value == CPENC(3, 4, C2, C6, 0)
4379 || reg->value == CPENC(3, 4, C14, C4, 0)
4380 || reg->value == CPENC(3, 4, C14, C4, 2)
4381 || reg->value == CPENC(3, 4, C14, C4, 1)
4382 || reg->value == CPENC(3, 4, C14, C5, 0)
4383 || reg->value == CPENC(3, 4, C14, C5, 2)
4384 || reg->value == CPENC(3, 4, C14, C5, 1)
4385 || reg->value == CPENC(3, 4, C1, C3, 1)
4386 || reg->value == CPENC(3, 4, C2, C2, 0))
4387 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4388 return FALSE;
4389
4390 /* ARMv8.4 TLB instructions. */
4391 if ((reg->value == CPENS (0, C8, C1, 0)
4392 || reg->value == CPENS (0, C8, C1, 1)
4393 || reg->value == CPENS (0, C8, C1, 2)
4394 || reg->value == CPENS (0, C8, C1, 3)
4395 || reg->value == CPENS (0, C8, C1, 5)
4396 || reg->value == CPENS (0, C8, C1, 7)
4397 || reg->value == CPENS (4, C8, C4, 0)
4398 || reg->value == CPENS (4, C8, C4, 4)
4399 || reg->value == CPENS (4, C8, C1, 1)
4400 || reg->value == CPENS (4, C8, C1, 5)
4401 || reg->value == CPENS (4, C8, C1, 6)
4402 || reg->value == CPENS (6, C8, C1, 1)
4403 || reg->value == CPENS (6, C8, C1, 5)
4404 || reg->value == CPENS (4, C8, C1, 0)
4405 || reg->value == CPENS (4, C8, C1, 4)
4406 || reg->value == CPENS (6, C8, C1, 0)
4407 || reg->value == CPENS (0, C8, C6, 1)
4408 || reg->value == CPENS (0, C8, C6, 3)
4409 || reg->value == CPENS (0, C8, C6, 5)
4410 || reg->value == CPENS (0, C8, C6, 7)
4411 || reg->value == CPENS (0, C8, C2, 1)
4412 || reg->value == CPENS (0, C8, C2, 3)
4413 || reg->value == CPENS (0, C8, C2, 5)
4414 || reg->value == CPENS (0, C8, C2, 7)
4415 || reg->value == CPENS (0, C8, C5, 1)
4416 || reg->value == CPENS (0, C8, C5, 3)
4417 || reg->value == CPENS (0, C8, C5, 5)
4418 || reg->value == CPENS (0, C8, C5, 7)
4419 || reg->value == CPENS (4, C8, C0, 2)
4420 || reg->value == CPENS (4, C8, C0, 6)
4421 || reg->value == CPENS (4, C8, C4, 2)
4422 || reg->value == CPENS (4, C8, C4, 6)
4423 || reg->value == CPENS (4, C8, C4, 3)
4424 || reg->value == CPENS (4, C8, C4, 7)
4425 || reg->value == CPENS (4, C8, C6, 1)
4426 || reg->value == CPENS (4, C8, C6, 5)
4427 || reg->value == CPENS (4, C8, C2, 1)
4428 || reg->value == CPENS (4, C8, C2, 5)
4429 || reg->value == CPENS (4, C8, C5, 1)
4430 || reg->value == CPENS (4, C8, C5, 5)
4431 || reg->value == CPENS (6, C8, C6, 1)
4432 || reg->value == CPENS (6, C8, C6, 5)
4433 || reg->value == CPENS (6, C8, C2, 1)
4434 || reg->value == CPENS (6, C8, C2, 5)
4435 || reg->value == CPENS (6, C8, C5, 1)
4436 || reg->value == CPENS (6, C8, C5, 5))
4437 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4438 return FALSE;
4439
af4bcb4c
SD		 4440 /* Random Number Instructions. For now they are available
4441 (and optional) only with ARMv8.5-A. */
4442 if ((reg->value == CPENC (3, 3, C2, C4, 0)
4443 || reg->value == CPENC (3, 3, C2, C4, 1))
4444 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_RNG)
4445 && AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_5)))
4446 return FALSE;
4447
70f3d23a
SD		 4448 /* System Registers in ARMv8.5-A with AARCH64_FEATURE_MEMTAG. */
4449 if ((reg->value == CPENC (3, 3, C4, C2, 7)
a051e2f3
KT		 4450 || reg->value == CPENC (3, 0, C5, C6, 1)
4451 || reg->value == CPENC (3, 0, C5, C6, 0)
4452 || reg->value == CPENC (3, 4, C5, C6, 0)
4453 || reg->value == CPENC (3, 6, C5, C6, 0)
4454 || reg->value == CPENC (3, 5, C5, C6, 0)
70f3d23a 4455 || reg->value == CPENC (3, 0, C1, C0, 5)
a028026d
KT		 4456 || reg->value == CPENC (3, 0, C1, C0, 6)
4457 || reg->value == CPENC (3, 1, C0, C0, 4))
70f3d23a
SD		 4458 && !(AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG)))
4459 return FALSE;
4460
f21cce2c
MW		 4461 return TRUE;
4462}
4463
793a1948
TC		 4464/* The CPENC below is fairly misleading, the fields
4465 here are not in CPENC form. They are in op2op1 form. The fields are encoded
4466 by ins_pstatefield, which just shifts the value by the width of the fields
4467 in a loop. So if you CPENC them only the first value will be set, the rest
4468 are masked out to 0. As an example. op2 = 3, op1=2. CPENC would produce a
4469 value of 0b110000000001000000 (0x30040) while what you want is
4470 0b011010 (0x1a). */
87b8eed7 4471const aarch64_sys_reg aarch64_pstatefields [] =
a06ea964 4472{
87b8eed7
YZ		 4473 { "spsel", 0x05, 0 },
4474 { "daifset", 0x1e, 0 },
4475 { "daifclr", 0x1f, 0 },
f21cce2c 4476 { "pan", 0x04, F_ARCHEXT },
6479e48e 4477 { "uao", 0x03, F_ARCHEXT },
104fefee 4478 { "ssbs", 0x19, F_ARCHEXT },
793a1948 4479 { "dit", 0x1a, F_ARCHEXT },
70f3d23a 4480 { "tco", 0x1c, F_ARCHEXT },
87b8eed7 4481 { 0, CPENC(0,0,0,0,0), 0 },
a06ea964
NC		 4482};
4483
f21cce2c
MW		 4484bfd_boolean
4485aarch64_pstatefield_supported_p (const aarch64_feature_set features,
4486 const aarch64_sys_reg *reg)
4487{
4488 if (!(reg->flags & F_ARCHEXT))
4489 return TRUE;
4490
4491 /* PAN. Values are from aarch64_pstatefields. */
4492 if (reg->value == 0x04
4493 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PAN))
4494 return FALSE;
4495
6479e48e
MW		 4496 /* UAO. Values are from aarch64_pstatefields. */
4497 if (reg->value == 0x03
4498 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4499 return FALSE;
4500
104fefee
SD		 4501 /* SSBS. Values are from aarch64_pstatefields. */
4502 if (reg->value == 0x19
4503 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_SSBS))
4504 return FALSE;
4505
793a1948
TC		 4506 /* DIT. Values are from aarch64_pstatefields. */
4507 if (reg->value == 0x1a
4508 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_4))
4509 return FALSE;
4510
70f3d23a
SD		 4511 /* TCO. Values are from aarch64_pstatefields. */
4512 if (reg->value == 0x1c
4513 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4514 return FALSE;
4515
f21cce2c
MW		 4516 return TRUE;
4517}
4518
a06ea964
NC		 4519const aarch64_sys_ins_reg aarch64_sys_regs_ic[] =
4520{
4521 { "ialluis", CPENS(0,C7,C1,0), 0 },
4522 { "iallu", CPENS(0,C7,C5,0), 0 },
ea2deeec 4523 { "ivau", CPENS (3, C7, C5, 1), F_HASXT },
a06ea964
NC		 4524 { 0, CPENS(0,0,0,0), 0 }
4525};
4526
4527const aarch64_sys_ins_reg aarch64_sys_regs_dc[] =
4528{
ea2deeec 4529 { "zva", CPENS (3, C7, C4, 1), F_HASXT },
3a0f69be
SD		 4530 { "gva", CPENS (3, C7, C4, 3), F_HASXT | F_ARCHEXT },
4531 { "gzva", CPENS (3, C7, C4, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4532 { "ivac", CPENS (0, C7, C6, 1), F_HASXT },
3a0f69be
SD		 4533 { "igvac", CPENS (0, C7, C6, 3), F_HASXT | F_ARCHEXT },
4534 { "igsw", CPENS (0, C7, C6, 4), F_HASXT | F_ARCHEXT },
ea2deeec 4535 { "isw", CPENS (0, C7, C6, 2), F_HASXT },
3a0f69be
SD		 4536 { "igdvac", CPENS (0, C7, C6, 5), F_HASXT | F_ARCHEXT },
4537 { "igdsw", CPENS (0, C7, C6, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4538 { "cvac", CPENS (3, C7, C10, 1), F_HASXT },
3a0f69be
SD		 4539 { "cgvac", CPENS (3, C7, C10, 3), F_HASXT | F_ARCHEXT },
4540 { "cgdvac", CPENS (3, C7, C10, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4541 { "csw", CPENS (0, C7, C10, 2), F_HASXT },
3a0f69be
SD		 4542 { "cgsw", CPENS (0, C7, C10, 4), F_HASXT | F_ARCHEXT },
4543 { "cgdsw", CPENS (0, C7, C10, 6), F_HASXT | F_ARCHEXT },
ea2deeec 4544 { "cvau", CPENS (3, C7, C11, 1), F_HASXT },
d6bf7ce6 4545 { "cvap", CPENS (3, C7, C12, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4546 { "cgvap", CPENS (3, C7, C12, 3), F_HASXT | F_ARCHEXT },
4547 { "cgdvap", CPENS (3, C7, C12, 5), F_HASXT | F_ARCHEXT },
3fd229a4 4548 { "cvadp", CPENS (3, C7, C13, 1), F_HASXT | F_ARCHEXT },
3a0f69be
SD		 4549 { "cgvadp", CPENS (3, C7, C13, 3), F_HASXT | F_ARCHEXT },
4550 { "cgdvadp", CPENS (3, C7, C13, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4551 { "civac", CPENS (3, C7, C14, 1), F_HASXT },
3a0f69be
SD		 4552 { "cigvac", CPENS (3, C7, C14, 3), F_HASXT | F_ARCHEXT },
4553 { "cigdvac", CPENS (3, C7, C14, 5), F_HASXT | F_ARCHEXT },
ea2deeec 4554 { "cisw", CPENS (0, C7, C14, 2), F_HASXT },
3a0f69be
SD		 4555 { "cigsw", CPENS (0, C7, C14, 4), F_HASXT | F_ARCHEXT },
4556 { "cigdsw", CPENS (0, C7, C14, 6), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4557 { 0, CPENS(0,0,0,0), 0 }
4558};
4559
4560const aarch64_sys_ins_reg aarch64_sys_regs_at[] =
4561{
ea2deeec
MW		 4562 { "s1e1r", CPENS (0, C7, C8, 0), F_HASXT },
4563 { "s1e1w", CPENS (0, C7, C8, 1), F_HASXT },
4564 { "s1e0r", CPENS (0, C7, C8, 2), F_HASXT },
4565 { "s1e0w", CPENS (0, C7, C8, 3), F_HASXT },
4566 { "s12e1r", CPENS (4, C7, C8, 4), F_HASXT },
4567 { "s12e1w", CPENS (4, C7, C8, 5), F_HASXT },
4568 { "s12e0r", CPENS (4, C7, C8, 6), F_HASXT },
4569 { "s12e0w", CPENS (4, C7, C8, 7), F_HASXT },
4570 { "s1e2r", CPENS (4, C7, C8, 0), F_HASXT },
4571 { "s1e2w", CPENS (4, C7, C8, 1), F_HASXT },
4572 { "s1e3r", CPENS (6, C7, C8, 0), F_HASXT },
4573 { "s1e3w", CPENS (6, C7, C8, 1), F_HASXT },
22a5455c
MW		 4574 { "s1e1rp", CPENS (0, C7, C9, 0), F_HASXT | F_ARCHEXT },
4575 { "s1e1wp", CPENS (0, C7, C9, 1), F_HASXT | F_ARCHEXT },
a06ea964
NC		 4576 { 0, CPENS(0,0,0,0), 0 }
4577};
4578
4579const aarch64_sys_ins_reg aarch64_sys_regs_tlbi[] =
4580{
4581 { "vmalle1", CPENS(0,C8,C7,0), 0 },
ea2deeec
MW		 4582 { "vae1", CPENS (0, C8, C7, 1), F_HASXT },
4583 { "aside1", CPENS (0, C8, C7, 2), F_HASXT },
4584 { "vaae1", CPENS (0, C8, C7, 3), F_HASXT },
a06ea964 4585 { "vmalle1is", CPENS(0,C8,C3,0), 0 },
ea2deeec
MW		 4586 { "vae1is", CPENS (0, C8, C3, 1), F_HASXT },
4587 { "aside1is", CPENS (0, C8, C3, 2), F_HASXT },
4588 { "vaae1is", CPENS (0, C8, C3, 3), F_HASXT },
4589 { "ipas2e1is", CPENS (4, C8, C0, 1), F_HASXT },
4590 { "ipas2le1is",CPENS (4, C8, C0, 5), F_HASXT },
4591 { "ipas2e1", CPENS (4, C8, C4, 1), F_HASXT },
4592 { "ipas2le1", CPENS (4, C8, C4, 5), F_HASXT },
4593 { "vae2", CPENS (4, C8, C7, 1), F_HASXT },
4594 { "vae2is", CPENS (4, C8, C3, 1), F_HASXT },
a06ea964
NC		 4595 { "vmalls12e1",CPENS(4,C8,C7,6), 0 },
4596 { "vmalls12e1is",CPENS(4,C8,C3,6), 0 },
ea2deeec
MW		 4597 { "vae3", CPENS (6, C8, C7, 1), F_HASXT },
4598 { "vae3is", CPENS (6, C8, C3, 1), F_HASXT },
a06ea964
NC		 4599 { "alle2", CPENS(4,C8,C7,0), 0 },
4600 { "alle2is", CPENS(4,C8,C3,0), 0 },
4601 { "alle1", CPENS(4,C8,C7,4), 0 },
4602 { "alle1is", CPENS(4,C8,C3,4), 0 },
4603 { "alle3", CPENS(6,C8,C7,0), 0 },
4604 { "alle3is", CPENS(6,C8,C3,0), 0 },
ea2deeec
MW		 4605 { "vale1is", CPENS (0, C8, C3, 5), F_HASXT },
4606 { "vale2is", CPENS (4, C8, C3, 5), F_HASXT },
4607 { "vale3is", CPENS (6, C8, C3, 5), F_HASXT },
4608 { "vaale1is", CPENS (0, C8, C3, 7), F_HASXT },
4609 { "vale1", CPENS (0, C8, C7, 5), F_HASXT },
4610 { "vale2", CPENS (4, C8, C7, 5), F_HASXT },
4611 { "vale3", CPENS (6, C8, C7, 5), F_HASXT },
4612 { "vaale1", CPENS (0, C8, C7, 7), F_HASXT },
793a1948
TC		 4613
4614 { "vmalle1os", CPENS (0, C8, C1, 0), F_ARCHEXT },
4615 { "vae1os", CPENS (0, C8, C1, 1), F_HASXT | F_ARCHEXT },
4616 { "aside1os", CPENS (0, C8, C1, 2), F_HASXT | F_ARCHEXT },
4617 { "vaae1os", CPENS (0, C8, C1, 3), F_HASXT | F_ARCHEXT },
4618 { "vale1os", CPENS (0, C8, C1, 5), F_HASXT | F_ARCHEXT },
4619 { "vaale1os", CPENS (0, C8, C1, 7), F_HASXT | F_ARCHEXT },
4620 { "ipas2e1os", CPENS (4, C8, C4, 0), F_HASXT | F_ARCHEXT },
4621 { "ipas2le1os", CPENS (4, C8, C4, 4), F_HASXT | F_ARCHEXT },
4622 { "vae2os", CPENS (4, C8, C1, 1), F_HASXT | F_ARCHEXT },
4623 { "vale2os", CPENS (4, C8, C1, 5), F_HASXT | F_ARCHEXT },
4624 { "vmalls12e1os", CPENS (4, C8, C1, 6), F_ARCHEXT },
4625 { "vae3os", CPENS (6, C8, C1, 1), F_HASXT | F_ARCHEXT },
4626 { "vale3os", CPENS (6, C8, C1, 5), F_HASXT | F_ARCHEXT },
4627 { "alle2os", CPENS (4, C8, C1, 0), F_ARCHEXT },
4628 { "alle1os", CPENS (4, C8, C1, 4), F_ARCHEXT },
4629 { "alle3os", CPENS (6, C8, C1, 0), F_ARCHEXT },
4630
4631 { "rvae1", CPENS (0, C8, C6, 1), F_HASXT | F_ARCHEXT },
4632 { "rvaae1", CPENS (0, C8, C6, 3), F_HASXT | F_ARCHEXT },
4633 { "rvale1", CPENS (0, C8, C6, 5), F_HASXT | F_ARCHEXT },
4634 { "rvaale1", CPENS (0, C8, C6, 7), F_HASXT | F_ARCHEXT },
4635 { "rvae1is", CPENS (0, C8, C2, 1), F_HASXT | F_ARCHEXT },
4636 { "rvaae1is", CPENS (0, C8, C2, 3), F_HASXT | F_ARCHEXT },
4637 { "rvale1is", CPENS (0, C8, C2, 5), F_HASXT | F_ARCHEXT },
4638 { "rvaale1is", CPENS (0, C8, C2, 7), F_HASXT | F_ARCHEXT },
4639 { "rvae1os", CPENS (0, C8, C5, 1), F_HASXT | F_ARCHEXT },
4640 { "rvaae1os", CPENS (0, C8, C5, 3), F_HASXT | F_ARCHEXT },
4641 { "rvale1os", CPENS (0, C8, C5, 5), F_HASXT | F_ARCHEXT },
4642 { "rvaale1os", CPENS (0, C8, C5, 7), F_HASXT | F_ARCHEXT },
4643 { "ripas2e1is", CPENS (4, C8, C0, 2), F_HASXT | F_ARCHEXT },
4644 { "ripas2le1is",CPENS (4, C8, C0, 6), F_HASXT | F_ARCHEXT },
4645 { "ripas2e1", CPENS (4, C8, C4, 2), F_HASXT | F_ARCHEXT },
4646 { "ripas2le1", CPENS (4, C8, C4, 6), F_HASXT | F_ARCHEXT },
4647 { "ripas2e1os", CPENS (4, C8, C4, 3), F_HASXT | F_ARCHEXT },
4648 { "ripas2le1os",CPENS (4, C8, C4, 7), F_HASXT | F_ARCHEXT },
4649 { "rvae2", CPENS (4, C8, C6, 1), F_HASXT | F_ARCHEXT },
4650 { "rvale2", CPENS (4, C8, C6, 5), F_HASXT | F_ARCHEXT },
4651 { "rvae2is", CPENS (4, C8, C2, 1), F_HASXT | F_ARCHEXT },
4652 { "rvale2is", CPENS (4, C8, C2, 5), F_HASXT | F_ARCHEXT },
4653 { "rvae2os", CPENS (4, C8, C5, 1), F_HASXT | F_ARCHEXT },
4654 { "rvale2os", CPENS (4, C8, C5, 5), F_HASXT | F_ARCHEXT },
4655 { "rvae3", CPENS (6, C8, C6, 1), F_HASXT | F_ARCHEXT },
4656 { "rvale3", CPENS (6, C8, C6, 5), F_HASXT | F_ARCHEXT },
4657 { "rvae3is", CPENS (6, C8, C2, 1), F_HASXT | F_ARCHEXT },
4658 { "rvale3is", CPENS (6, C8, C2, 5), F_HASXT | F_ARCHEXT },
4659 { "rvae3os", CPENS (6, C8, C5, 1), F_HASXT | F_ARCHEXT },
4660 { "rvale3os", CPENS (6, C8, C5, 5), F_HASXT | F_ARCHEXT },
4661
a06ea964
NC		 4662 { 0, CPENS(0,0,0,0), 0 }
4663};
4664
2ac435d4
SD		 4665const aarch64_sys_ins_reg aarch64_sys_regs_sr[] =
4666{
4667 /* RCTX is somewhat unique in a way that it has different values
4668 (op2) based on the instruction in which it is used (cfp/dvp/cpp).
4669 Thus op2 is masked out and instead encoded directly in the
4670 aarch64_opcode_table entries for the respective instructions. */
4671 { "rctx", CPENS(3,C7,C3,0), F_HASXT | F_ARCHEXT | F_REG_WRITE}, /* WO */
4672
4673 { 0, CPENS(0,0,0,0), 0 }
4674};
4675
ea2deeec
MW		 4676bfd_boolean
4677aarch64_sys_ins_reg_has_xt (const aarch64_sys_ins_reg *sys_ins_reg)
4678{
4679 return (sys_ins_reg->flags & F_HASXT) != 0;
4680}
4681
d6bf7ce6
MW		 4682extern bfd_boolean
4683aarch64_sys_ins_reg_supported_p (const aarch64_feature_set features,
4684 const aarch64_sys_ins_reg *reg)
4685{
4686 if (!(reg->flags & F_ARCHEXT))
4687 return TRUE;
4688
4689 /* DC CVAP. Values are from aarch64_sys_regs_dc. */
4690 if (reg->value == CPENS (3, C7, C12, 1)
4691 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4692 return FALSE;
4693
3fd229a4
SD		 4694 /* DC CVADP. Values are from aarch64_sys_regs_dc. */
4695 if (reg->value == CPENS (3, C7, C13, 1)
4696 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_CVADP))
4697 return FALSE;
4698
3a0f69be
SD		 4699 /* DC <dc_op> for ARMv8.5-A Memory Tagging Extension. */
4700 if ((reg->value == CPENS (0, C7, C6, 3)
4701 || reg->value == CPENS (0, C7, C6, 4)
4702 || reg->value == CPENS (0, C7, C10, 4)
4703 || reg->value == CPENS (0, C7, C14, 4)
4704 || reg->value == CPENS (3, C7, C10, 3)
4705 || reg->value == CPENS (3, C7, C12, 3)
4706 || reg->value == CPENS (3, C7, C13, 3)
4707 || reg->value == CPENS (3, C7, C14, 3)
4708 || reg->value == CPENS (3, C7, C4, 3)
4709 || reg->value == CPENS (0, C7, C6, 5)
4710 || reg->value == CPENS (0, C7, C6, 6)
4711 || reg->value == CPENS (0, C7, C10, 6)
4712 || reg->value == CPENS (0, C7, C14, 6)
4713 || reg->value == CPENS (3, C7, C10, 5)
4714 || reg->value == CPENS (3, C7, C12, 5)
4715 || reg->value == CPENS (3, C7, C13, 5)
4716 || reg->value == CPENS (3, C7, C14, 5)
4717 || reg->value == CPENS (3, C7, C4, 4))
4718 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_MEMTAG))
4719 return FALSE;
4720
63511907
MW		 4721 /* AT S1E1RP, AT S1E1WP. Values are from aarch64_sys_regs_at. */
4722 if ((reg->value == CPENS (0, C7, C9, 0)
4723 || reg->value == CPENS (0, C7, C9, 1))
4724 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_V8_2))
4725 return FALSE;
4726
2ac435d4
SD		 4727 /* CFP/DVP/CPP RCTX : Value are from aarch64_sys_regs_sr. */
4728 if (reg->value == CPENS (3, C7, C3, 0)
4729 && !AARCH64_CPU_HAS_FEATURE (features, AARCH64_FEATURE_PREDRES))
4730 return FALSE;
4731
d6bf7ce6
MW		 4732 return TRUE;
4733}
4734
a06ea964
NC		 4735#undef C0
4736#undef C1
4737#undef C2
4738#undef C3
4739#undef C4
4740#undef C5
4741#undef C6
4742#undef C7
4743#undef C8
4744#undef C9
4745#undef C10
4746#undef C11
4747#undef C12
4748#undef C13
4749#undef C14
4750#undef C15
4751
4bd13cde
NC		 4752#define BIT(INSN,BT) (((INSN) >> (BT)) & 1)
4753#define BITS(INSN,HI,LO) (((INSN) >> (LO)) & ((1 << (((HI) - (LO)) + 1)) - 1))
4754
755b748f
TC		 4755static enum err_type
4756verify_ldpsw (const struct aarch64_inst *inst ATTRIBUTE_UNUSED,
4757 const aarch64_insn insn, bfd_vma pc ATTRIBUTE_UNUSED,
4758 bfd_boolean encoding ATTRIBUTE_UNUSED,
4759 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
a68f4cd2 4760 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4bd13cde
NC		 4761{
4762 int t = BITS (insn, 4, 0);
4763 int n = BITS (insn, 9, 5);
4764 int t2 = BITS (insn, 14, 10);
4765
4766 if (BIT (insn, 23))
4767 {
4768 /* Write back enabled. */
4769 if ((t == n || t2 == n) && n != 31)
755b748f 4770 return ERR_UND;
4bd13cde
NC		 4771 }
4772
4773 if (BIT (insn, 22))
4774 {
4775 /* Load */
4776 if (t == t2)
755b748f 4777 return ERR_UND;
4bd13cde
NC		 4778 }
4779
755b748f 4780 return ERR_OK;
4bd13cde
NC		 4781}
4782
6456d318
TC		 4783/* Verifier for vector by element 3 operands functions where the
4784 conditions `if sz:L == 11 then UNDEFINED` holds. */
4785
4786static enum err_type
4787verify_elem_sd (const struct aarch64_inst *inst, const aarch64_insn insn,
4788 bfd_vma pc ATTRIBUTE_UNUSED, bfd_boolean encoding,
4789 aarch64_operand_error *mismatch_detail ATTRIBUTE_UNUSED,
4790 aarch64_instr_sequence *insn_sequence ATTRIBUTE_UNUSED)
4791{
4792 const aarch64_insn undef_pattern = 0x3;
4793 aarch64_insn value;
4794
4795 assert (inst->opcode);
4796 assert (inst->opcode->operands[2] == AARCH64_OPND_Em);
4797 value = encoding ? inst->value : insn;
4798 assert (value);
4799
4800 if (undef_pattern == extract_fields (value, 0, 2, FLD_sz, FLD_L))
4801 return ERR_UND;
4802
4803 return ERR_OK;
4804}
4805
a68f4cd2
TC		 4806/* Initialize an instruction sequence insn_sequence with the instruction INST.
4807 If INST is NULL the given insn_sequence is cleared and the sequence is left
4808 uninitialized. */
4809
4810void
4811init_insn_sequence (const struct aarch64_inst *inst,
4812 aarch64_instr_sequence *insn_sequence)
4813{
4814 int num_req_entries = 0;
4815 insn_sequence->next_insn = 0;
4816 insn_sequence->num_insns = num_req_entries;
4817 if (insn_sequence->instr)
4818 XDELETE (insn_sequence->instr);
4819 insn_sequence->instr = NULL;
4820
4821 if (inst)
4822 {
4823 insn_sequence->instr = XNEW (aarch64_inst);
4824 memcpy (insn_sequence->instr, inst, sizeof (aarch64_inst));
4825 }
4826
4827 /* Handle all the cases here. May need to think of something smarter than
4828 a giant if/else chain if this grows. At that time, a lookup table may be
4829 best. */
4830 if (inst && inst->opcode->constraints & C_SCAN_MOVPRFX)
4831 num_req_entries = 1;
4832
4833 if (insn_sequence->current_insns)
4834 XDELETEVEC (insn_sequence->current_insns);
4835 insn_sequence->current_insns = NULL;
4836
4837 if (num_req_entries != 0)
4838 {
4839 size_t size = num_req_entries * sizeof (aarch64_inst);
4840 insn_sequence->current_insns
4841 = (aarch64_inst**) XNEWVEC (aarch64_inst, num_req_entries);
4842 memset (insn_sequence->current_insns, 0, size);
4843 }
4844}
4845
4846
4847/* This function verifies that the instruction INST adheres to its specified
4848 constraints. If it does then ERR_OK is returned, if not then ERR_VFI is
4849 returned and MISMATCH_DETAIL contains the reason why verification failed.
4850
4851 The function is called both during assembly and disassembly. If assembling
4852 then ENCODING will be TRUE, else FALSE. If dissassembling PC will be set
4853 and will contain the PC of the current instruction w.r.t to the section.
4854
4855 If ENCODING and PC=0 then you are at a start of a section. The constraints
4856 are verified against the given state insn_sequence which is updated as it
4857 transitions through the verification. */
4858
4859enum err_type
4860verify_constraints (const struct aarch64_inst *inst,
4861 const aarch64_insn insn ATTRIBUTE_UNUSED,
4862 bfd_vma pc,
4863 bfd_boolean encoding,
4864 aarch64_operand_error *mismatch_detail,
4865 aarch64_instr_sequence *insn_sequence)
4866{
4867 assert (inst);
4868 assert (inst->opcode);
4869
4870 const struct aarch64_opcode *opcode = inst->opcode;
4871 if (!opcode->constraints && !insn_sequence->instr)
4872 return ERR_OK;
4873
4874 assert (insn_sequence);
4875
4876 enum err_type res = ERR_OK;
4877
4878 /* This instruction puts a constraint on the insn_sequence. */
4879 if (opcode->flags & F_SCAN)
4880 {
4881 if (insn_sequence->instr)
4882 {
4883 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4884 mismatch_detail->error = _("instruction opens new dependency "
4885 "sequence without ending previous one");
4886 mismatch_detail->index = -1;
4887 mismatch_detail->non_fatal = TRUE;
4888 res = ERR_VFI;
4889 }
4890
4891 init_insn_sequence (inst, insn_sequence);
4892 return res;
4893 }
4894
4895 /* Verify constraints on an existing sequence. */
4896 if (insn_sequence->instr)
4897 {
4898 const struct aarch64_opcode* inst_opcode = insn_sequence->instr->opcode;
4899 /* If we're decoding and we hit PC=0 with an open sequence then we haven't
4900 closed a previous one that we should have. */
4901 if (!encoding && pc == 0)
4902 {
4903 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4904 mismatch_detail->error = _("previous `movprfx' sequence not closed");
4905 mismatch_detail->index = -1;
4906 mismatch_detail->non_fatal = TRUE;
4907 res = ERR_VFI;
4908 /* Reset the sequence. */
4909 init_insn_sequence (NULL, insn_sequence);
4910 return res;
4911 }
4912
4913 /* Validate C_SCAN_MOVPRFX constraints. Move this to a lookup table. */
4914 if (inst_opcode->constraints & C_SCAN_MOVPRFX)
4915 {
4916 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4917 instruction for better error messages. */
5cd99750
MM		 4918 if (!opcode->avariant
4919 || !(*opcode->avariant &
4920 (AARCH64_FEATURE_SVE | AARCH64_FEATURE_SVE2)))
a68f4cd2
TC		 4921 {
4922 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4923 mismatch_detail->error = _("SVE instruction expected after "
4924 "`movprfx'");
4925 mismatch_detail->index = -1;
4926 mismatch_detail->non_fatal = TRUE;
4927 res = ERR_VFI;
4928 goto done;
4929 }
4930
4931 /* Check to see if the MOVPRFX SVE instruction is followed by an SVE
4932 instruction that is allowed to be used with a MOVPRFX. */
4933 if (!(opcode->constraints & C_SCAN_MOVPRFX))
4934 {
4935 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
4936 mismatch_detail->error = _("SVE `movprfx' compatible instruction "
4937 "expected");
4938 mismatch_detail->index = -1;
4939 mismatch_detail->non_fatal = TRUE;
4940 res = ERR_VFI;
4941 goto done;
4942 }
4943
4944 /* Next check for usage of the predicate register. */
4945 aarch64_opnd_info blk_dest = insn_sequence->instr->operands[0];
780f601c
TC		 4946 aarch64_opnd_info blk_pred, inst_pred;
4947 memset (&blk_pred, 0, sizeof (aarch64_opnd_info));
4948 memset (&inst_pred, 0, sizeof (aarch64_opnd_info));
a68f4cd2
TC		 4949 bfd_boolean predicated = FALSE;
4950 assert (blk_dest.type == AARCH64_OPND_SVE_Zd);
4951
4952 /* Determine if the movprfx instruction used is predicated or not. */
4953 if (insn_sequence->instr->operands[1].type == AARCH64_OPND_SVE_Pg3)
4954 {
4955 predicated = TRUE;
4956 blk_pred = insn_sequence->instr->operands[1];
4957 }
4958
4959 unsigned char max_elem_size = 0;
4960 unsigned char current_elem_size;
4961 int num_op_used = 0, last_op_usage = 0;
4962 int i, inst_pred_idx = -1;
4963 int num_ops = aarch64_num_of_operands (opcode);
4964 for (i = 0; i < num_ops; i++)
4965 {
4966 aarch64_opnd_info inst_op = inst->operands[i];
4967 switch (inst_op.type)
4968 {
4969 case AARCH64_OPND_SVE_Zd:
4970 case AARCH64_OPND_SVE_Zm_5:
4971 case AARCH64_OPND_SVE_Zm_16:
4972 case AARCH64_OPND_SVE_Zn:
4973 case AARCH64_OPND_SVE_Zt:
4974 case AARCH64_OPND_SVE_Vm:
4975 case AARCH64_OPND_SVE_Vn:
4976 case AARCH64_OPND_Va:
4977 case AARCH64_OPND_Vn:
4978 case AARCH64_OPND_Vm:
4979 case AARCH64_OPND_Sn:
4980 case AARCH64_OPND_Sm:
a68f4cd2
TC		 4981 if (inst_op.reg.regno == blk_dest.reg.regno)
4982 {
4983 num_op_used++;
4984 last_op_usage = i;
4985 }
4986 current_elem_size
4987 = aarch64_get_qualifier_esize (inst_op.qualifier);
4988 if (current_elem_size > max_elem_size)
4989 max_elem_size = current_elem_size;
4990 break;
4991 case AARCH64_OPND_SVE_Pd:
4992 case AARCH64_OPND_SVE_Pg3:
4993 case AARCH64_OPND_SVE_Pg4_5:
4994 case AARCH64_OPND_SVE_Pg4_10:
4995 case AARCH64_OPND_SVE_Pg4_16:
4996 case AARCH64_OPND_SVE_Pm:
4997 case AARCH64_OPND_SVE_Pn:
4998 case AARCH64_OPND_SVE_Pt:
4999 inst_pred = inst_op;
5000 inst_pred_idx = i;
5001 break;
5002 default:
5003 break;
5004 }
5005 }
5006
5007 assert (max_elem_size != 0);
5008 aarch64_opnd_info inst_dest = inst->operands[0];
5009 /* Determine the size that should be used to compare against the
5010 movprfx size. */
5011 current_elem_size
5012 = opcode->constraints & C_MAX_ELEM
5013 ? max_elem_size
5014 : aarch64_get_qualifier_esize (inst_dest.qualifier);
5015
5016 /* If movprfx is predicated do some extra checks. */
5017 if (predicated)
5018 {
5019 /* The instruction must be predicated. */
5020 if (inst_pred_idx < 0)
5021 {
5022 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5023 mismatch_detail->error = _("predicated instruction expected "
5024 "after `movprfx'");
5025 mismatch_detail->index = -1;
5026 mismatch_detail->non_fatal = TRUE;
5027 res = ERR_VFI;
5028 goto done;
5029 }
5030
5031 /* The instruction must have a merging predicate. */
5032 if (inst_pred.qualifier != AARCH64_OPND_QLF_P_M)
5033 {
5034 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5035 mismatch_detail->error = _("merging predicate expected due "
5036 "to preceding `movprfx'");
5037 mismatch_detail->index = inst_pred_idx;
5038 mismatch_detail->non_fatal = TRUE;
5039 res = ERR_VFI;
5040 goto done;
5041 }
5042
5043 /* The same register must be used in instruction. */
5044 if (blk_pred.reg.regno != inst_pred.reg.regno)
5045 {
5046 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5047 mismatch_detail->error = _("predicate register differs "
5048 "from that in preceding "
5049 "`movprfx'");
5050 mismatch_detail->index = inst_pred_idx;
5051 mismatch_detail->non_fatal = TRUE;
5052 res = ERR_VFI;
5053 goto done;
5054 }
5055 }
5056
5057 /* Destructive operations by definition must allow one usage of the
5058 same register. */
5059 int allowed_usage
5060 = aarch64_is_destructive_by_operands (opcode) ? 2 : 1;
5061
5062 /* Operand is not used at all. */
5063 if (num_op_used == 0)
5064 {
5065 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5066 mismatch_detail->error = _("output register of preceding "
5067 "`movprfx' not used in current "
5068 "instruction");
5069 mismatch_detail->index = 0;
5070 mismatch_detail->non_fatal = TRUE;
5071 res = ERR_VFI;
5072 goto done;
5073 }
5074
5075 /* We now know it's used, now determine exactly where it's used. */
5076 if (blk_dest.reg.regno != inst_dest.reg.regno)
5077 {
5078 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5079 mismatch_detail->error = _("output register of preceding "
5080 "`movprfx' expected as output");
5081 mismatch_detail->index = 0;
5082 mismatch_detail->non_fatal = TRUE;
5083 res = ERR_VFI;
5084 goto done;
5085 }
5086
5087 /* Operand used more than allowed for the specific opcode type. */
5088 if (num_op_used > allowed_usage)
5089 {
5090 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5091 mismatch_detail->error = _("output register of preceding "
5092 "`movprfx' used as input");
5093 mismatch_detail->index = last_op_usage;
5094 mismatch_detail->non_fatal = TRUE;
5095 res = ERR_VFI;
5096 goto done;
5097 }
5098
5099 /* Now the only thing left is the qualifiers checks. The register
5100 must have the same maximum element size. */
5101 if (inst_dest.qualifier
5102 && blk_dest.qualifier
5103 && current_elem_size
5104 != aarch64_get_qualifier_esize (blk_dest.qualifier))
5105 {
5106 mismatch_detail->kind = AARCH64_OPDE_SYNTAX_ERROR;
5107 mismatch_detail->error = _("register size not compatible with "
5108 "previous `movprfx'");
5109 mismatch_detail->index = 0;
5110 mismatch_detail->non_fatal = TRUE;
5111 res = ERR_VFI;
5112 goto done;
5113 }
5114 }
5115
5116done:
5117 /* Add the new instruction to the sequence. */
5118 memcpy (insn_sequence->current_insns + insn_sequence->next_insn++,
5119 inst, sizeof (aarch64_inst));
5120
5121 /* Check if sequence is now full. */
5122 if (insn_sequence->next_insn >= insn_sequence->num_insns)
5123 {
5124 /* Sequence is full, but we don't have anything special to do for now,
5125 so clear and reset it. */
5126 init_insn_sequence (NULL, insn_sequence);
5127 }
5128 }
5129
5130 return res;
5131}
5132
5133
e950b345
RS		 5134/* Return true if VALUE cannot be moved into an SVE register using DUP
5135 (with any element size, not just ESIZE) and if using DUPM would
5136 therefore be OK. ESIZE is the number of bytes in the immediate. */
5137
5138bfd_boolean
5139aarch64_sve_dupm_mov_immediate_p (uint64_t uvalue, int esize)
5140{
5141 int64_t svalue = uvalue;
5142 uint64_t upper = (uint64_t) -1 << (esize * 4) << (esize * 4);
5143
5144 if ((uvalue & ~upper) != uvalue && (uvalue | upper) != uvalue)
5145 return FALSE;
5146 if (esize <= 4 || (uint32_t) uvalue == (uint32_t) (uvalue >> 32))
5147 {
5148 svalue = (int32_t) uvalue;
5149 if (esize <= 2 || (uint16_t) uvalue == (uint16_t) (uvalue >> 16))
5150 {
5151 svalue = (int16_t) uvalue;
5152 if (esize == 1 || (uint8_t) uvalue == (uint8_t) (uvalue >> 8))
5153 return FALSE;
5154 }
5155 }
5156 if ((svalue & 0xff) == 0)
5157 svalue /= 256;
5158 return svalue < -128 || svalue >= 128;
5159}
5160
a06ea964
NC		 5161/* Include the opcode description table as well as the operand description
5162 table. */
20f55f38 5163#define VERIFIER(x) verify_##x
a06ea964 5164#include "aarch64-tbl.h"
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