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Update the simplified Chinese translation of the messages in the opcodes library.
[thirdparty/binutils-gdb.git] / opcodes / arc-opc.c
CommitLineData
252b5132 1/* Opcode table for the ARC.
2571583a 2 Copyright (C) 1994-2017 Free Software Foundation, Inc.
886a2506
NC		 3
4 Contributed by Claudiu Zissulescu (claziss@synopsys.com)
bcee8eb8 5
9b201bb5
NC		 6 This file is part of libopcodes.
7
8 This library is free software; you can redistribute it and/or modify
252b5132 9 it under the terms of the GNU General Public License as published by
9b201bb5 10 the Free Software Foundation; either version 3, or (at your option)
252b5132
RH		 11 any later version.
12
9b201bb5
NC		 13 It is distributed in the hope that it will be useful, but WITHOUT
14 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
15 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
16 License for more details.
252b5132
RH		 17
18 You should have received a copy of the GNU General Public License
0d2bcfaf 19 along with this program; if not, write to the Free Software Foundation,
f4321104 20 Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */
252b5132 21
5bd67f35 22#include "sysdep.h"
252b5132 23#include <stdio.h>
d943fe33 24#include "bfd.h"
252b5132 25#include "opcode/arc.h"
47b0e7ad 26#include "opintl.h"
886a2506 27#include "libiberty.h"
252b5132 28
e23e8ebe 29/* ARC NPS400 Support: The ARC NPS400 core is an ARC700 with some custom
ce440d63 30 instructions. All NPS400 features are built into all ARC target builds as
e23e8ebe
AB		 31 this reduces the chances that regressions might creep in. */
32
abe7c33b 33/* Insert RA register into a 32-bit opcode, with checks. */
c0c31e91 34
abe7c33b 35static unsigned long long
c0c31e91
RZ		 36insert_ra_chk (unsigned long long insn,
37 long long value,
38 const char ** errmsg)
abe7c33b
CZ		 39{
40 if (value == 60)
41 *errmsg = _("LP_COUNT register cannot be used as destination register");
42
43 return insn | (value & 0x3F);
44}
c0c31e91 45
886a2506 46/* Insert RB register into a 32-bit opcode. */
c0c31e91 47
bdfe53e3 48static unsigned long long
c0c31e91
RZ		 49insert_rb (unsigned long long insn,
50 long long value,
51 const char ** errmsg ATTRIBUTE_UNUSED)
252b5132 52{
886a2506
NC		 53 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
54}
0d2bcfaf 55
abe7c33b 56/* Insert RB register with checks. */
c0c31e91 57
abe7c33b 58static unsigned long long
c0c31e91
RZ		 59insert_rb_chk (unsigned long long insn,
60 long long value,
61 const char ** errmsg)
abe7c33b
CZ		 62{
63 if (value == 60)
64 *errmsg = _("LP_COUNT register cannot be used as destination register");
65
66 return insn | ((value & 0x07) << 24) | (((value >> 3) & 0x07) << 12);
67}
68
c0c31e91
RZ		 69static long long
70extract_rb (unsigned long long insn,
71 bfd_boolean * invalid)
886a2506
NC		 72{
73 int value = (((insn >> 12) & 0x07) << 3) | ((insn >> 24) & 0x07);
0d2bcfaf 74
886a2506
NC		 75 if (value == 0x3e && invalid)
76 *invalid = TRUE; /* A limm operand, it should be extracted in a
77 different way. */
252b5132 78
886a2506
NC		 79 return value;
80}
252b5132 81
bdfe53e3 82static unsigned long long
c0c31e91
RZ		 83insert_rad (unsigned long long insn,
84 long long value,
85 const char ** errmsg)
886a2506
NC		 86{
87 if (value & 0x01)
abe7c33b
CZ		 88 *errmsg = _("cannot use odd number destination register");
89 if (value == 60)
90 *errmsg = _("LP_COUNT register cannot be used as destination register");
0d2bcfaf 91
886a2506
NC		 92 return insn | (value & 0x3F);
93}
0d2bcfaf 94
bdfe53e3 95static unsigned long long
c0c31e91
RZ		 96insert_rcd (unsigned long long insn,
97 long long value,
98 const char ** errmsg)
886a2506
NC		 99{
100 if (value & 0x01)
abe7c33b 101 *errmsg = _("cannot use odd number source register");
0d2bcfaf 102
886a2506
NC		 103 return insn | ((value & 0x3F) << 6);
104}
252b5132 105
886a2506 106/* Dummy insert ZERO operand function. */
252b5132 107
bdfe53e3 108static unsigned long long
c0c31e91
RZ		 109insert_za (unsigned long long insn,
110 long long value,
111 const char ** errmsg)
886a2506
NC		 112{
113 if (value)
114 *errmsg = _("operand is not zero");
115 return insn;
116}
252b5132 117
886a2506
NC		 118/* Insert Y-bit in bbit/br instructions. This function is called only
119 when solving fixups. */
252b5132 120
bdfe53e3 121static unsigned long long
c0c31e91
RZ		 122insert_Ybit (unsigned long long insn,
123 long long value,
124 const char ** errmsg ATTRIBUTE_UNUSED)
886a2506
NC		 125{
126 if (value > 0)
127 insn |= 0x08;
252b5132 128
886a2506
NC		 129 return insn;
130}
252b5132 131
886a2506
NC		 132/* Insert Y-bit in bbit/br instructions. This function is called only
133 when solving fixups. */
252b5132 134
bdfe53e3 135static unsigned long long
c0c31e91
RZ		 136insert_NYbit (unsigned long long insn,
137 long long value,
138 const char ** errmsg ATTRIBUTE_UNUSED)
886a2506
NC		 139{
140 if (value < 0)
141 insn |= 0x08;
0d2bcfaf 142
886a2506
NC		 143 return insn;
144}
252b5132 145
886a2506 146/* Insert H register into a 16-bit opcode. */
252b5132 147
bdfe53e3 148static unsigned long long
c0c31e91
RZ		 149insert_rhv1 (unsigned long long insn,
150 long long value,
151 const char ** errmsg ATTRIBUTE_UNUSED)
886a2506
NC		 152{
153 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x07);
154}
252b5132 155
c0c31e91
RZ		 156static long long
157extract_rhv1 (unsigned long long insn,
158 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506 159{
02f3be19 160 int value = ((insn & 0x7) << 3) | ((insn >> 5) & 0x7);
252b5132 161
886a2506
NC		 162 return value;
163}
252b5132 164
886a2506 165/* Insert H register into a 16-bit opcode. */
252b5132 166
bdfe53e3 167static unsigned long long
c0c31e91
RZ		 168insert_rhv2 (unsigned long long insn,
169 long long value,
170 const char ** errmsg)
0d2bcfaf 171{
886a2506 172 if (value == 0x1E)
7cbc739c 173 *errmsg = _("register R30 is a limm indicator");
dc958481 174 else if (value < 0 || value > 31)
175 *errmsg = _("register out of range");
886a2506
NC		 176 return insn |= ((value & 0x07) << 5) | ((value >> 3) & 0x03);
177}
252b5132 178
c0c31e91
RZ		 179static long long
180extract_rhv2 (unsigned long long insn,
181 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 182{
183 int value = ((insn >> 5) & 0x07) | ((insn & 0x03) << 3);
0d2bcfaf 184
886a2506
NC		 185 return value;
186}
0d2bcfaf 187
bdfe53e3 188static unsigned long long
c0c31e91
RZ		 189insert_r0 (unsigned long long insn,
190 long long value,
191 const char ** errmsg)
886a2506
NC		 192{
193 if (value != 0)
7cbc739c 194 *errmsg = _("register must be R0");
47b0e7ad
NC		 195 return insn;
196}
252b5132 197
c0c31e91 198static long long
bdfe53e3 199extract_r0 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 200 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 201{
886a2506 202 return 0;
47b0e7ad 203}
252b5132 204
252b5132 205
bdfe53e3 206static unsigned long long
c0c31e91
RZ		 207insert_r1 (unsigned long long insn,
208 long long value,
209 const char ** errmsg)
252b5132 210{
886a2506 211 if (value != 1)
7cbc739c 212 *errmsg = _("register must be R1");
47b0e7ad 213 return insn;
252b5132
RH		 214}
215
c0c31e91 216static long long
bdfe53e3 217extract_r1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 218 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 219{
886a2506 220 return 1;
252b5132
RH		 221}
222
bdfe53e3 223static unsigned long long
c0c31e91
RZ		 224insert_r2 (unsigned long long insn,
225 long long value,
226 const char ** errmsg)
252b5132 227{
886a2506 228 if (value != 2)
7cbc739c 229 *errmsg = _("register must be R2");
47b0e7ad 230 return insn;
252b5132
RH		 231}
232
c0c31e91 233static long long
bdfe53e3 234extract_r2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 235 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 236{
886a2506 237 return 2;
252b5132
RH		 238}
239
bdfe53e3 240static unsigned long long
c0c31e91
RZ		 241insert_r3 (unsigned long long insn,
242 long long value,
243 const char ** errmsg)
252b5132 244{
886a2506 245 if (value != 3)
7cbc739c 246 *errmsg = _("register must be R3");
47b0e7ad 247 return insn;
0d2bcfaf
NC		 248}
249
c0c31e91 250static long long
bdfe53e3 251extract_r3 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 252 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 253{
886a2506 254 return 3;
0d2bcfaf
NC		 255}
256
bdfe53e3 257static unsigned long long
c0c31e91
RZ		 258insert_sp (unsigned long long insn,
259 long long value,
260 const char ** errmsg)
252b5132 261{
886a2506 262 if (value != 28)
7cbc739c 263 *errmsg = _("register must be SP");
252b5132
RH		 264 return insn;
265}
266
c0c31e91 267static long long
bdfe53e3 268extract_sp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 269 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 270{
886a2506 271 return 28;
0d2bcfaf
NC		 272}
273
bdfe53e3 274static unsigned long long
c0c31e91
RZ		 275insert_gp (unsigned long long insn,
276 long long value,
277 const char ** errmsg)
0d2bcfaf 278{
886a2506 279 if (value != 26)
7cbc739c 280 *errmsg = _("register must be GP");
886a2506 281 return insn;
0d2bcfaf
NC		 282}
283
c0c31e91 284static long long
bdfe53e3 285extract_gp (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 286 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 287{
886a2506 288 return 26;
0d2bcfaf
NC		 289}
290
bdfe53e3 291static unsigned long long
c0c31e91
RZ		 292insert_pcl (unsigned long long insn,
293 long long value,
294 const char ** errmsg)
252b5132 295{
886a2506 296 if (value != 63)
7cbc739c 297 *errmsg = _("register must be PCL");
252b5132
RH		 298 return insn;
299}
300
c0c31e91 301static long long
bdfe53e3 302extract_pcl (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 303 bfd_boolean * invalid ATTRIBUTE_UNUSED)
0d2bcfaf 304{
886a2506 305 return 63;
0d2bcfaf
NC		 306}
307
bdfe53e3 308static unsigned long long
c0c31e91
RZ		 309insert_blink (unsigned long long insn,
310 long long value,
311 const char ** errmsg)
252b5132 312{
886a2506 313 if (value != 31)
7cbc739c 314 *errmsg = _("register must be BLINK");
252b5132
RH		 315 return insn;
316}
317
c0c31e91 318static long long
bdfe53e3 319extract_blink (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 320 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 321{
886a2506 322 return 31;
0d2bcfaf
NC		 323}
324
bdfe53e3 325static unsigned long long
c0c31e91
RZ		 326insert_ilink1 (unsigned long long insn,
327 long long value,
328 const char ** errmsg)
0d2bcfaf 329{
886a2506 330 if (value != 29)
7cbc739c 331 *errmsg = _("register must be ILINK1");
252b5132
RH		 332 return insn;
333}
334
c0c31e91 335static long long
bdfe53e3 336extract_ilink1 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506 337 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 338{
886a2506 339 return 29;
252b5132
RH		 340}
341
bdfe53e3 342static unsigned long long
c0c31e91
RZ		 343insert_ilink2 (unsigned long long insn,
344 long long value,
345 const char ** errmsg)
252b5132 346{
886a2506 347 if (value != 30)
7cbc739c 348 *errmsg = _("register must be ILINK2");
252b5132
RH		 349 return insn;
350}
351
c0c31e91 352static long long
bdfe53e3 353extract_ilink2 (unsigned long long insn ATTRIBUTE_UNUSED,
886a2506
NC		 354 bfd_boolean * invalid ATTRIBUTE_UNUSED)
355{
356 return 30;
357}
252b5132 358
bdfe53e3 359static unsigned long long
c0c31e91
RZ		 360insert_ras (unsigned long long insn,
361 long long value,
362 const char ** errmsg)
252b5132 363{
886a2506 364 switch (value)
0d2bcfaf 365 {
886a2506
NC		 366 case 0:
367 case 1:
368 case 2:
369 case 3:
370 insn |= value;
371 break;
372 case 12:
373 case 13:
374 case 14:
375 case 15:
376 insn |= (value - 8);
377 break;
378 default:
7cbc739c 379 *errmsg = _("register must be either r0-r3 or r12-r15");
886a2506 380 break;
0d2bcfaf 381 }
252b5132
RH		 382 return insn;
383}
252b5132 384
c0c31e91
RZ		 385static long long
386extract_ras (unsigned long long insn,
387 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 388{
886a2506 389 int value = insn & 0x07;
c0c31e91 390
886a2506
NC		 391 if (value > 3)
392 return (value + 8);
393 else
394 return value;
47b0e7ad
NC		 395}
396
bdfe53e3 397static unsigned long long
c0c31e91
RZ		 398insert_rbs (unsigned long long insn,
399 long long value,
400 const char ** errmsg)
252b5132 401{
886a2506 402 switch (value)
47b0e7ad 403 {
886a2506
NC		 404 case 0:
405 case 1:
406 case 2:
407 case 3:
408 insn |= value << 8;
409 break;
410 case 12:
411 case 13:
412 case 14:
413 case 15:
414 insn |= ((value - 8)) << 8;
415 break;
416 default:
7cbc739c 417 *errmsg = _("register must be either r0-r3 or r12-r15");
886a2506 418 break;
47b0e7ad 419 }
886a2506 420 return insn;
252b5132
RH		 421}
422
c0c31e91
RZ		 423static long long
424extract_rbs (unsigned long long insn,
425 bfd_boolean * invalid ATTRIBUTE_UNUSED)
252b5132 426{
886a2506 427 int value = (insn >> 8) & 0x07;
c0c31e91 428
886a2506
NC		 429 if (value > 3)
430 return (value + 8);
431 else
432 return value;
433}
252b5132 434
bdfe53e3 435static unsigned long long
c0c31e91
RZ		 436insert_rcs (unsigned long long insn,
437 long long value,
438 const char ** errmsg)
886a2506
NC		 439{
440 switch (value)
252b5132 441 {
886a2506
NC		 442 case 0:
443 case 1:
444 case 2:
445 case 3:
446 insn |= value << 5;
447 break;
448 case 12:
449 case 13:
450 case 14:
451 case 15:
452 insn |= ((value - 8)) << 5;
453 break;
454 default:
7cbc739c 455 *errmsg = _("register must be either r0-r3 or r12-r15");
886a2506 456 break;
252b5132 457 }
886a2506
NC		 458 return insn;
459}
47b0e7ad 460
c0c31e91
RZ		 461static long long
462extract_rcs (unsigned long long insn,
463 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 464{
465 int value = (insn >> 5) & 0x07;
c0c31e91 466
886a2506
NC		 467 if (value > 3)
468 return (value + 8);
252b5132 469 else
886a2506
NC		 470 return value;
471}
47b0e7ad 472
bdfe53e3 473static unsigned long long
c0c31e91
RZ		 474insert_simm3s (unsigned long long insn,
475 long long value,
476 const char ** errmsg)
886a2506
NC		 477{
478 int tmp = 0;
479 switch (value)
47b0e7ad 480 {
886a2506
NC		 481 case -1:
482 tmp = 0x07;
47b0e7ad 483 break;
886a2506
NC		 484 case 0:
485 tmp = 0x00;
486 break;
487 case 1:
488 tmp = 0x01;
47b0e7ad 489 break;
886a2506
NC		 490 case 2:
491 tmp = 0x02;
47b0e7ad 492 break;
886a2506
NC		 493 case 3:
494 tmp = 0x03;
495 break;
496 case 4:
497 tmp = 0x04;
498 break;
499 case 5:
500 tmp = 0x05;
501 break;
502 case 6:
503 tmp = 0x06;
504 break;
505 default:
7cbc739c 506 *errmsg = _("accepted values are from -1 to 6");
47b0e7ad
NC		 507 break;
508 }
509
886a2506
NC		 510 insn |= tmp << 8;
511 return insn;
47b0e7ad
NC		 512}
513
c0c31e91
RZ		 514static long long
515extract_simm3s (unsigned long long insn,
516 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 517{
886a2506 518 int value = (insn >> 8) & 0x07;
c0c31e91 519
886a2506
NC		 520 if (value == 7)
521 return -1;
47b0e7ad 522 else
886a2506 523 return value;
47b0e7ad
NC		 524}
525
bdfe53e3 526static unsigned long long
c0c31e91
RZ		 527insert_rrange (unsigned long long insn,
528 long long value,
529 const char ** errmsg)
47b0e7ad 530{
886a2506
NC		 531 int reg1 = (value >> 16) & 0xFFFF;
532 int reg2 = value & 0xFFFF;
c0c31e91 533
886a2506 534 if (reg1 != 13)
7cbc739c 535 *errmsg = _("first register of the range should be r13");
c0c31e91 536 else if (reg2 < 13 || reg2 > 26)
7cbc739c 537 *errmsg = _("last register of the range doesn't fit");
c0c31e91
RZ		 538 else
539 insn |= ((reg2 - 12) & 0x0F) << 1;
886a2506 540 return insn;
47b0e7ad
NC		 541}
542
c0c31e91
RZ		 543static long long
544extract_rrange (unsigned long long insn,
545 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 546{
547 return (insn >> 1) & 0x0F;
548}
47b0e7ad 549
126124cc
CZ		 550static unsigned long long
551insert_r13el (unsigned long long insn,
552 long long int value,
553 const char **errmsg)
554{
555 if (value != 13)
556 {
7cbc739c 557 *errmsg = _("invalid register number, should be fp");
126124cc
CZ		 558 return insn;
559 }
560
561 insn |= 0x02;
562 return insn;
563}
564
bdfe53e3 565static unsigned long long
c0c31e91
RZ		 566insert_fpel (unsigned long long insn,
567 long long value,
568 const char ** errmsg)
47b0e7ad 569{
886a2506
NC		 570 if (value != 27)
571 {
7cbc739c 572 *errmsg = _("invalid register number, should be fp");
886a2506
NC		 573 return insn;
574 }
47b0e7ad 575
886a2506
NC		 576 insn |= 0x0100;
577 return insn;
47b0e7ad
NC		 578}
579
c0c31e91
RZ		 580static long long
581extract_fpel (unsigned long long insn,
582 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 583{
886a2506 584 return (insn & 0x0100) ? 27 : -1;
47b0e7ad
NC		 585}
586
bdfe53e3 587static unsigned long long
c0c31e91
RZ		 588insert_blinkel (unsigned long long insn,
589 long long value,
590 const char ** errmsg)
47b0e7ad 591{
886a2506 592 if (value != 31)
47b0e7ad 593 {
7cbc739c 594 *errmsg = _("invalid register number, should be blink");
886a2506 595 return insn;
47b0e7ad 596 }
47b0e7ad 597
886a2506
NC		 598 insn |= 0x0200;
599 return insn;
47b0e7ad
NC		 600}
601
c0c31e91
RZ		 602static long long
603extract_blinkel (unsigned long long insn,
604 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 605{
886a2506
NC		 606 return (insn & 0x0200) ? 31 : -1;
607}
47b0e7ad 608
bdfe53e3 609static unsigned long long
c0c31e91
RZ		 610insert_pclel (unsigned long long insn,
611 long long value,
612 const char ** errmsg)
886a2506
NC		 613{
614 if (value != 63)
47b0e7ad 615 {
7cbc739c 616 *errmsg = _("invalid register number, should be pcl");
886a2506 617 return insn;
47b0e7ad 618 }
47b0e7ad 619
886a2506
NC		 620 insn |= 0x0400;
621 return insn;
622}
47b0e7ad 623
c0c31e91
RZ		 624static long long
625extract_pclel (unsigned long long insn,
626 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 627{
886a2506 628 return (insn & 0x0400) ? 63 : -1;
47b0e7ad 629}
47b0e7ad 630
886a2506 631#define INSERT_W6
c0c31e91 632
886a2506
NC		 633/* mask = 00000000000000000000111111000000
634 insn = 00011bbb000000000BBBwwwwwwDaaZZ1. */
c0c31e91 635
bdfe53e3 636static unsigned long long
c0c31e91
RZ		 637insert_w6 (unsigned long long insn,
638 long long value,
639 const char ** errmsg ATTRIBUTE_UNUSED)
47b0e7ad 640{
886a2506 641 insn |= ((value >> 0) & 0x003f) << 6;
47b0e7ad 642
886a2506
NC		 643 return insn;
644}
47b0e7ad 645
886a2506 646#define EXTRACT_W6
c0c31e91 647
886a2506 648/* mask = 00000000000000000000111111000000. */
c0c31e91
RZ		 649
650static long long
651extract_w6 (unsigned long long insn,
652 bfd_boolean * invalid ATTRIBUTE_UNUSED)
47b0e7ad 653{
886a2506 654 unsigned value = 0;
47b0e7ad 655
886a2506 656 value |= ((insn >> 6) & 0x003f) << 0;
47b0e7ad 657
886a2506
NC		 658 return value;
659}
47b0e7ad 660
886a2506 661#define INSERT_G_S
c0c31e91 662
886a2506
NC		 663/* mask = 0000011100022000
664 insn = 01000ggghhhGG0HH. */
c0c31e91 665
bdfe53e3 666static unsigned long long
c0c31e91
RZ		 667insert_g_s (unsigned long long insn,
668 long long value,
669 const char ** errmsg ATTRIBUTE_UNUSED)
47b0e7ad 670{
886a2506
NC		 671 insn |= ((value >> 0) & 0x0007) << 8;
672 insn |= ((value >> 3) & 0x0003) << 3;
252b5132 673
886a2506
NC		 674 return insn;
675}
252b5132 676
886a2506 677#define EXTRACT_G_S
c0c31e91 678
886a2506 679/* mask = 0000011100022000. */
c0c31e91
RZ		 680
681static long long
682extract_g_s (unsigned long long insn,
683 bfd_boolean * invalid ATTRIBUTE_UNUSED)
886a2506
NC		 684{
685 int value = 0;
c0c31e91 686 int signbit = 1 << (6 - 1);
252b5132 687
886a2506
NC		 688 value |= ((insn >> 8) & 0x0007) << 0;
689 value |= ((insn >> 3) & 0x0003) << 3;
252b5132 690
886a2506 691 /* Extend the sign. */
886a2506 692 value = (value ^ signbit) - signbit;
252b5132 693
886a2506 694 return value;
252b5132
RH		 695}
696
e23e8ebe 697/* ARC NPS400 Support: See comment near head of file. */
bdfe53e3
AB		 698#define MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(NAME,OFFSET) \
699static unsigned long long \
700insert_nps_3bit_reg_at_##OFFSET##_##NAME \
c0c31e91
RZ		 701 (unsigned long long insn, \
702 long long value, \
703 const char ** errmsg) \
bdfe53e3
AB		 704{ \
705 switch (value) \
706 { \
707 case 0: \
708 case 1: \
709 case 2: \
710 case 3: \
711 insn |= value << (OFFSET); \
712 break; \
713 case 12: \
714 case 13: \
715 case 14: \
716 case 15: \
717 insn |= (value - 8) << (OFFSET); \
718 break; \
719 default: \
7cbc739c 720 *errmsg = _("register must be either r0-r3 or r12-r15"); \
bdfe53e3
AB		 721 break; \
722 } \
723 return insn; \
724} \
725 \
c0c31e91 726static long long \
bdfe53e3 727extract_nps_3bit_reg_at_##OFFSET##_##NAME \
c0c31e91
RZ		 728 (unsigned long long insn, \
729 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
bdfe53e3
AB		 730{ \
731 int value = (insn >> (OFFSET)) & 0x07; \
732 if (value > 3) \
733 value += 8; \
734 return value; \
735} \
736
737MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,8)
738MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,24)
739MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,40)
740MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(dst,56)
741
742MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,5)
743MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,21)
744MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,37)
745MAKE_3BIT_REG_INSERT_EXTRACT_FUNCS(src2,53)
746
747static unsigned long long
c0c31e91
RZ		 748insert_nps_bitop_size_2b (unsigned long long insn,
749 long long value,
750 const char ** errmsg)
820f03ff
AB		 751{
752 switch (value)
753 {
754 case 1:
755 value = 0;
756 break;
757 case 2:
758 value = 1;
759 break;
760 case 4:
761 value = 2;
762 break;
763 case 8:
764 value = 3;
765 break;
766 default:
767 value = 0;
7cbc739c 768 *errmsg = _("invalid size, should be 1, 2, 4, or 8");
820f03ff
AB		 769 break;
770 }
771
772 insn |= value << 10;
773 return insn;
774}
775
c0c31e91
RZ		 776static long long
777extract_nps_bitop_size_2b (unsigned long long insn,
778 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 779{
780 return 1 << ((insn >> 10) & 0x3);
781}
782
bdfe53e3 783static unsigned long long
c0c31e91
RZ		 784insert_nps_bitop_uimm8 (unsigned long long insn,
785 long long value,
786 const char ** errmsg ATTRIBUTE_UNUSED)
820f03ff
AB		 787{
788 insn |= ((value >> 5) & 7) << 12;
789 insn |= (value & 0x1f);
790 return insn;
791}
792
c0c31e91
RZ		 793static long long
794extract_nps_bitop_uimm8 (unsigned long long insn,
795 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 796{
797 return (((insn >> 12) & 0x7) << 5) | (insn & 0x1f);
798}
799
bdfe53e3 800static unsigned long long
c0c31e91
RZ		 801insert_nps_rflt_uimm6 (unsigned long long insn,
802 long long value,
803 const char ** errmsg)
820f03ff
AB		 804{
805 switch (value)
806 {
807 case 1:
808 case 2:
809 case 4:
810 break;
811
812 default:
813 *errmsg = _("invalid immediate, must be 1, 2, or 4");
814 value = 0;
815 }
816
817 insn |= (value << 6);
818 return insn;
819}
820
c0c31e91
RZ		 821static long long
822extract_nps_rflt_uimm6 (unsigned long long insn,
823 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 824{
825 return (insn >> 6) & 0x3f;
826}
827
bdfe53e3 828static unsigned long long
c0c31e91
RZ		 829insert_nps_dst_pos_and_size (unsigned long long insn,
830 long long value,
831 const char ** errmsg ATTRIBUTE_UNUSED)
820f03ff
AB		 832{
833 insn |= ((value & 0x1f) | (((32 - value - 1) & 0x1f) << 10));
834 return insn;
835}
836
c0c31e91
RZ		 837static long long
838extract_nps_dst_pos_and_size (unsigned long long insn,
839 bfd_boolean * invalid ATTRIBUTE_UNUSED)
820f03ff
AB		 840{
841 return (insn & 0x1f);
842}
843
bdfe53e3 844static unsigned long long
c0c31e91
RZ		 845insert_nps_cmem_uimm16 (unsigned long long insn,
846 long long value,
847 const char ** errmsg)
4b0c052e
AB		 848{
849 int top = (value >> 16) & 0xffff;
c0c31e91 850
4b0c052e
AB		 851 if (top != 0x0 && top != NPS_CMEM_HIGH_VALUE)
852 *errmsg = _("invalid value for CMEM ld/st immediate");
853 insn |= (value & 0xffff);
854 return insn;
855}
856
c0c31e91
RZ		 857static long long
858extract_nps_cmem_uimm16 (unsigned long long insn,
859 bfd_boolean * invalid ATTRIBUTE_UNUSED)
4b0c052e
AB		 860{
861 return (NPS_CMEM_HIGH_VALUE << 16) | (insn & 0xffff);
862}
863
c0c31e91
RZ		 864static unsigned long long
865insert_nps_imm_offset (unsigned long long insn,
866 long long value,
867 const char ** errmsg)
645d3342
RZ		 868{
869 switch (value)
870 {
871 case 0:
872 case 16:
873 case 32:
874 case 48:
875 case 64:
876 value = value >> 4;
877 break;
878 default:
7cbc739c 879 *errmsg = _("invalid position, should be 0, 16, 32, 48 or 64.");
645d3342
RZ		 880 value = 0;
881 }
882 insn |= (value << 10);
883 return insn;
884}
885
c0c31e91
RZ		 886static long long
887extract_nps_imm_offset (unsigned long long insn,
888 bfd_boolean * invalid ATTRIBUTE_UNUSED)
645d3342
RZ		 889{
890 return ((insn >> 10) & 0x7) * 16;
891}
892
893static unsigned long long
c0c31e91
RZ		 894insert_nps_imm_entry (unsigned long long insn,
895 long long value,
896 const char ** errmsg)
645d3342
RZ		 897{
898 switch (value)
899 {
900 case 16:
901 value = 0;
902 break;
903 case 32:
904 value = 1;
905 break;
906 case 64:
907 value = 2;
908 break;
909 case 128:
910 value = 3;
911 break;
912 default:
7cbc739c 913 *errmsg = _("invalid position, should be 16, 32, 64 or 128.");
645d3342
RZ		 914 value = 0;
915 }
916 insn |= (value << 2);
917 return insn;
918}
919
c0c31e91
RZ		 920static long long
921extract_nps_imm_entry (unsigned long long insn,
922 bfd_boolean * invalid ATTRIBUTE_UNUSED)
645d3342
RZ		 923{
924 int imm_entry = ((insn >> 2) & 0x7);
925 return (1 << (imm_entry + 4));
926}
927
c0c31e91
RZ		 928static unsigned long long
929insert_nps_size_16bit (unsigned long long insn,
930 long long value,
931 const char ** errmsg)
932{
933 if ((value < 1) || (value > 64))
934 {
7cbc739c 935 *errmsg = _("invalid size value must be on range 1-64.");
c0c31e91
RZ		 936 value = 0;
937 }
938 value = value & 0x3f;
939 insn |= (value << 6);
940 return insn;
941}
942
943static long long
944extract_nps_size_16bit (unsigned long long insn,
945 bfd_boolean * invalid ATTRIBUTE_UNUSED)
946{
947 return ((insn & 0xfc0) >> 6) ? ((insn & 0xfc0) >> 6) : 64;
948}
949
950
951#define MAKE_SRC_POS_INSERT_EXTRACT_FUNCS(NAME,SHIFT) \
952static unsigned long long \
953insert_nps_##NAME##_pos (unsigned long long insn, \
954 long long value, \
955 const char ** errmsg) \
537aefaf
AB		 956{ \
957 switch (value) \
958 { \
959 case 0: \
960 case 8: \
961 case 16: \
962 case 24: \
963 value = value / 8; \
964 break; \
965 default: \
7cbc739c 966 *errmsg = _("invalid position, should be 0, 8, 16, or 24"); \
537aefaf
AB		 967 value = 0; \
968 } \
c0c31e91 969 insn |= (value << SHIFT); \
537aefaf
AB		 970 return insn; \
971} \
972 \
c0c31e91
RZ		 973static long long \
974extract_nps_##NAME##_pos (unsigned long long insn, \
975 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
976{ \
977 return ((insn >> SHIFT) & 0x3) * 8; \
537aefaf
AB		 978}
979
980MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src2, 12)
981MAKE_SRC_POS_INSERT_EXTRACT_FUNCS (src1, 10)
982
c0c31e91
RZ		 983#define MAKE_BIAS_INSERT_EXTRACT_FUNCS(NAME,LOWER,UPPER,BITS,BIAS,SHIFT) \
984static unsigned long long \
985insert_nps_##NAME (unsigned long long insn, \
986 long long value, \
987 const char ** errmsg) \
537aefaf 988 { \
9ba75c88 989 if (value < LOWER || value > UPPER) \
537aefaf 990 { \
7cbc739c 991 *errmsg = _("invalid size, value must be " \
537aefaf
AB		 992 #LOWER " to " #UPPER "."); \
993 return insn; \
994 } \
995 value -= BIAS; \
996 insn |= (value << SHIFT); \
997 return insn; \
998 } \
999 \
c0c31e91
RZ		 1000static long long \
1001extract_nps_##NAME (unsigned long long insn, \
1002 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
537aefaf
AB		 1003{ \
1004 return ((insn >> SHIFT) & ((1 << BITS) - 1)) + BIAS; \
1005}
1006
db18dbab
GM		 1007MAKE_BIAS_INSERT_EXTRACT_FUNCS (addb_size,2,32,5,1,5)
1008MAKE_BIAS_INSERT_EXTRACT_FUNCS (andb_size,1,32,5,1,5)
1009MAKE_BIAS_INSERT_EXTRACT_FUNCS (fxorb_size,8,32,5,8,5)
1010MAKE_BIAS_INSERT_EXTRACT_FUNCS (wxorb_size,16,32,5,16,5)
1011MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop_size,1,32,5,1,10)
1012MAKE_BIAS_INSERT_EXTRACT_FUNCS (qcmp_size,1,8,3,1,9)
1013MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop1_size,1,32,5,1,20)
1014MAKE_BIAS_INSERT_EXTRACT_FUNCS (bitop2_size,1,32,5,1,25)
1015MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_width,1,32,5,1,6)
1016MAKE_BIAS_INSERT_EXTRACT_FUNCS (hash_len,1,8,3,1,2)
1017MAKE_BIAS_INSERT_EXTRACT_FUNCS (index3,4,7,2,4,0)
537aefaf 1018
c0c31e91
RZ		 1019static long long
1020extract_nps_qcmp_m3 (unsigned long long insn,
1021 bfd_boolean * invalid)
537aefaf
AB		 1022{
1023 int m3 = (insn >> 5) & 0xf;
1024 if (m3 == 0xf)
1025 *invalid = TRUE;
1026 return m3;
1027}
1028
c0c31e91
RZ		 1029static long long
1030extract_nps_qcmp_m2 (unsigned long long insn,
1031 bfd_boolean * invalid)
537aefaf
AB		 1032{
1033 bfd_boolean tmp_invalid = FALSE;
1034 int m2 = (insn >> 15) & 0x1;
1035 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1036
1037 if (m2 == 0 && m3 == 0xf)
1038 *invalid = TRUE;
1039 return m2;
1040}
1041
c0c31e91
RZ		 1042static long long
1043extract_nps_qcmp_m1 (unsigned long long insn,
1044 bfd_boolean * invalid)
537aefaf
AB		 1045{
1046 bfd_boolean tmp_invalid = FALSE;
1047 int m1 = (insn >> 14) & 0x1;
1048 int m2 = extract_nps_qcmp_m2 (insn, &tmp_invalid);
1049 int m3 = extract_nps_qcmp_m3 (insn, &tmp_invalid);
1050
1051 if (m1 == 0 && m2 == 0 && m3 == 0xf)
1052 *invalid = TRUE;
1053 return m1;
1054}
1055
bdfe53e3 1056static unsigned long long
c0c31e91
RZ		 1057insert_nps_calc_entry_size (unsigned long long insn,
1058 long long value,
1059 const char ** errmsg)
537aefaf
AB		 1060{
1061 unsigned pwr;
1062
1063 if (value < 1 || value > 256)
1064 {
1065 *errmsg = _("value out of range 1 - 256");
1066 return 0;
1067 }
1068
1069 for (pwr = 0; (value & 1) == 0; value >>= 1)
1070 ++pwr;
1071
1072 if (value != 1)
1073 {
1074 *errmsg = _("value must be power of 2");
1075 return 0;
1076 }
1077
1078 return insn | (pwr << 8);
1079}
1080
c0c31e91
RZ		 1081static long long
1082extract_nps_calc_entry_size (unsigned long long insn,
1083 bfd_boolean * invalid ATTRIBUTE_UNUSED)
537aefaf
AB		 1084{
1085 unsigned entry_size = (insn >> 8) & 0xf;
1086 return 1 << entry_size;
1087}
1088
bdfe53e3 1089static unsigned long long
c0c31e91
RZ		 1090insert_nps_bitop_mod4 (unsigned long long insn,
1091 long long value,
1092 const char ** errmsg ATTRIBUTE_UNUSED)
4eb6f892 1093{
bdfe53e3 1094 return insn | ((value & 0x2) << 30) | ((value & 0x1) << 47);
4eb6f892
AB		 1095}
1096
c0c31e91
RZ		 1097static long long
1098extract_nps_bitop_mod4 (unsigned long long insn,
1099 bfd_boolean * invalid ATTRIBUTE_UNUSED)
4eb6f892 1100{
bdfe53e3 1101 return ((insn >> 30) & 0x2) | ((insn >> 47) & 0x1);
4eb6f892
AB		 1102}
1103
bdfe53e3 1104static unsigned long long
c0c31e91
RZ		 1105insert_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1106 long long value,
1107 const char ** errmsg ATTRIBUTE_UNUSED)
4eb6f892 1108{
bdfe53e3 1109 return insn | (value << 42) | (value << 37);
4eb6f892
AB		 1110}
1111
c0c31e91
RZ		 1112static long long
1113extract_nps_bitop_dst_pos3_pos4 (unsigned long long insn,
1114 bfd_boolean * invalid)
4eb6f892 1115{
bdfe53e3 1116 if (((insn >> 42) & 0x1f) != ((insn >> 37) & 0x1f))
4eb6f892 1117 *invalid = TRUE;
bdfe53e3 1118 return ((insn >> 37) & 0x1f);
4eb6f892
AB		 1119}
1120
bdfe53e3 1121static unsigned long long
c0c31e91
RZ		 1122insert_nps_bitop_ins_ext (unsigned long long insn,
1123 long long value,
1124 const char ** errmsg)
4eb6f892
AB		 1125{
1126 if (value < 0 || value > 28)
7cbc739c 1127 *errmsg = _("value must be in the range 0 to 28");
4eb6f892
AB		 1128 return insn | (value << 20);
1129}
1130
c0c31e91
RZ		 1131static long long
1132extract_nps_bitop_ins_ext (unsigned long long insn,
1133 bfd_boolean * invalid)
4eb6f892
AB		 1134{
1135 int value = (insn >> 20) & 0x1f;
c0c31e91 1136
4eb6f892
AB		 1137 if (value > 28)
1138 *invalid = TRUE;
1139 return value;
1140}
1141
14053c19 1142#define MAKE_1BASED_INSERT_EXTRACT_FUNCS(NAME,SHIFT,UPPER,BITS) \
c0c31e91
RZ		 1143static unsigned long long \
1144insert_nps_##NAME (unsigned long long insn, \
1145 long long value, \
1146 const char ** errmsg) \
14053c19
GM		 1147{ \
1148 if (value < 1 || value > UPPER) \
7cbc739c 1149 *errmsg = _("value must be in the range 1 to " #UPPER); \
14053c19
GM		 1150 if (value == UPPER) \
1151 value = 0; \
1152 return insn | (value << SHIFT); \
1153} \
1154 \
c0c31e91
RZ		 1155static long long \
1156extract_nps_##NAME (unsigned long long insn, \
1157 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
14053c19
GM		 1158{ \
1159 int value = (insn >> SHIFT) & ((1 << BITS) - 1); \
1160 if (value == 0) \
1161 value = UPPER; \
1162 return value; \
1163}
1164
db18dbab
GM		 1165MAKE_1BASED_INSERT_EXTRACT_FUNCS (field_size, 6, 8, 3)
1166MAKE_1BASED_INSERT_EXTRACT_FUNCS (shift_factor, 9, 8, 3)
1167MAKE_1BASED_INSERT_EXTRACT_FUNCS (bits_to_scramble, 12, 8, 3)
1168MAKE_1BASED_INSERT_EXTRACT_FUNCS (bdlen_max_len, 5, 256, 8)
1169MAKE_1BASED_INSERT_EXTRACT_FUNCS (bd_num_buff, 6, 8, 3)
1170MAKE_1BASED_INSERT_EXTRACT_FUNCS (pmu_num_job, 6, 4, 2)
5a736821 1171MAKE_1BASED_INSERT_EXTRACT_FUNCS (proto_size, 16, 64, 6)
14053c19 1172
bdfe53e3 1173static unsigned long long
c0c31e91
RZ		 1174insert_nps_min_hofs (unsigned long long insn,
1175 long long value,
1176 const char ** errmsg)
14053c19
GM		 1177{
1178 if (value < 0 || value > 240)
7cbc739c 1179 *errmsg = _("value must be in the range 0 to 240");
14053c19 1180 if ((value % 16) != 0)
7cbc739c 1181 *errmsg = _("value must be a multiple of 16");
14053c19
GM		 1182 value = value / 16;
1183 return insn | (value << 6);
1184}
1185
c0c31e91
RZ		 1186static long long
1187extract_nps_min_hofs (unsigned long long insn,
1188 bfd_boolean * invalid ATTRIBUTE_UNUSED)
14053c19
GM		 1189{
1190 int value = (insn >> 6) & 0xF;
1191 return value * 16;
1192}
1193
c0c31e91 1194#define MAKE_INSERT_NPS_ADDRTYPE(NAME, VALUE) \
bdfe53e3 1195static unsigned long long \
c0c31e91
RZ		 1196insert_nps_##NAME (unsigned long long insn, \
1197 long long value, \
1198 const char ** errmsg) \
db18dbab
GM		 1199{ \
1200 if (value != ARC_NPS400_ADDRTYPE_##VALUE) \
7cbc739c 1201 *errmsg = _("invalid address type for operand"); \
db18dbab
GM		 1202 return insn; \
1203} \
1204 \
c0c31e91
RZ		 1205static long long \
1206extract_nps_##NAME (unsigned long long insn ATTRIBUTE_UNUSED, \
1207 bfd_boolean * invalid ATTRIBUTE_UNUSED) \
db18dbab
GM		 1208{ \
1209 return ARC_NPS400_ADDRTYPE_##VALUE; \
1210}
1211
1212MAKE_INSERT_NPS_ADDRTYPE (bd, BD)
1213MAKE_INSERT_NPS_ADDRTYPE (jid, JID)
1214MAKE_INSERT_NPS_ADDRTYPE (lbd, LBD)
1215MAKE_INSERT_NPS_ADDRTYPE (mbd, MBD)
1216MAKE_INSERT_NPS_ADDRTYPE (sd, SD)
1217MAKE_INSERT_NPS_ADDRTYPE (sm, SM)
1218MAKE_INSERT_NPS_ADDRTYPE (xa, XA)
1219MAKE_INSERT_NPS_ADDRTYPE (xd, XD)
1220MAKE_INSERT_NPS_ADDRTYPE (cd, CD)
1221MAKE_INSERT_NPS_ADDRTYPE (cbd, CBD)
1222MAKE_INSERT_NPS_ADDRTYPE (cjid, CJID)
1223MAKE_INSERT_NPS_ADDRTYPE (clbd, CLBD)
1224MAKE_INSERT_NPS_ADDRTYPE (cm, CM)
1225MAKE_INSERT_NPS_ADDRTYPE (csd, CSD)
1226MAKE_INSERT_NPS_ADDRTYPE (cxa, CXA)
1227MAKE_INSERT_NPS_ADDRTYPE (cxd, CXD)
1228
5a736821 1229static unsigned long long
c0c31e91
RZ		 1230insert_nps_rbdouble_64 (unsigned long long insn,
1231 long long value,
1232 const char ** errmsg)
5a736821
GM		 1233{
1234 if (value < 0 || value > 31)
7cbc739c 1235 *errmsg = _("value must be in the range 0 to 31");
5a736821
GM		 1236 return insn | (value << 43) | (value << 48);
1237}
1238
1239
c0c31e91
RZ		 1240static long long
1241extract_nps_rbdouble_64 (unsigned long long insn,
1242 bfd_boolean * invalid)
5a736821
GM		 1243{
1244 int value1 = (insn >> 43) & 0x1F;
1245 int value2 = (insn >> 48) & 0x1F;
1246
1247 if (value1 != value2)
1248 *invalid = TRUE;
1249
1250 return value1;
1251}
1252
c0c31e91
RZ		 1253static unsigned long long
1254insert_nps_misc_imm_offset (unsigned long long insn,
1255 long long value,
1256 const char ** errmsg)
1257{
1258 if (value & 0x3)
1259 {
7cbc739c 1260 *errmsg = _("invalid position, should be one of: 0,4,8,...124.");
c0c31e91
RZ		 1261 value = 0;
1262 }
1263 insn |= (value << 6);
1264 return insn;
1265}
1266
1267static long long int
1268extract_nps_misc_imm_offset (unsigned long long insn,
1269 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1270{
1271 return ((insn >> 8) & 0x1f) * 4;
1272}
1273
7179e0e6
CZ		 1274static long long int
1275extract_uimm12_20 (unsigned long long insn ATTRIBUTE_UNUSED,
1276 bfd_boolean * invalid ATTRIBUTE_UNUSED)
1277{
1278 int value = 0;
1279
1280 value |= ((insn >> 6) & 0x003f) << 0;
1281 value |= ((insn >> 0) & 0x003f) << 6;
1282
1283 return value;
1284}
1285
886a2506
NC		 1286/* Include the generic extract/insert functions. Order is important
1287 as some of the functions present in the .h may be disabled via
1288 defines. */
1289#include "arc-fxi.h"
252b5132 1290
886a2506 1291/* The flag operands table.
252b5132 1292
886a2506
NC		 1293 The format of the table is
1294 NAME CODE BITS SHIFT FAVAIL. */
1295const struct arc_flag_operand arc_flag_operands[] =
1296{
1297#define F_NULL 0
1298 { 0, 0, 0, 0, 0},
1299#define F_ALWAYS (F_NULL + 1)
1300 { "al", 0, 0, 0, 0 },
1301#define F_RA (F_ALWAYS + 1)
1302 { "ra", 0, 0, 0, 0 },
1303#define F_EQUAL (F_RA + 1)
1304 { "eq", 1, 5, 0, 1 },
1305#define F_ZERO (F_EQUAL + 1)
1306 { "z", 1, 5, 0, 0 },
1307#define F_NOTEQUAL (F_ZERO + 1)
1308 { "ne", 2, 5, 0, 1 },
1309#define F_NOTZERO (F_NOTEQUAL + 1)
1310 { "nz", 2, 5, 0, 0 },
1311#define F_POZITIVE (F_NOTZERO + 1)
1312 { "p", 3, 5, 0, 1 },
1313#define F_PL (F_POZITIVE + 1)
1314 { "pl", 3, 5, 0, 0 },
1315#define F_NEGATIVE (F_PL + 1)
1316 { "n", 4, 5, 0, 1 },
1317#define F_MINUS (F_NEGATIVE + 1)
1318 { "mi", 4, 5, 0, 0 },
1319#define F_CARRY (F_MINUS + 1)
1320 { "c", 5, 5, 0, 1 },
1321#define F_CARRYSET (F_CARRY + 1)
1322 { "cs", 5, 5, 0, 0 },
1323#define F_LOWER (F_CARRYSET + 1)
1324 { "lo", 5, 5, 0, 0 },
1325#define F_CARRYCLR (F_LOWER + 1)
1326 { "cc", 6, 5, 0, 0 },
1327#define F_NOTCARRY (F_CARRYCLR + 1)
1328 { "nc", 6, 5, 0, 1 },
1329#define F_HIGHER (F_NOTCARRY + 1)
1330 { "hs", 6, 5, 0, 0 },
1331#define F_OVERFLOWSET (F_HIGHER + 1)
1332 { "vs", 7, 5, 0, 0 },
1333#define F_OVERFLOW (F_OVERFLOWSET + 1)
1334 { "v", 7, 5, 0, 1 },
1335#define F_NOTOVERFLOW (F_OVERFLOW + 1)
1336 { "nv", 8, 5, 0, 1 },
1337#define F_OVERFLOWCLR (F_NOTOVERFLOW + 1)
1338 { "vc", 8, 5, 0, 0 },
1339#define F_GT (F_OVERFLOWCLR + 1)
1340 { "gt", 9, 5, 0, 1 },
1341#define F_GE (F_GT + 1)
1342 { "ge", 10, 5, 0, 1 },
1343#define F_LT (F_GE + 1)
1344 { "lt", 11, 5, 0, 1 },
1345#define F_LE (F_LT + 1)
1346 { "le", 12, 5, 0, 1 },
1347#define F_HI (F_LE + 1)
1348 { "hi", 13, 5, 0, 1 },
1349#define F_LS (F_HI + 1)
1350 { "ls", 14, 5, 0, 1 },
1351#define F_PNZ (F_LS + 1)
1352 { "pnz", 15, 5, 0, 1 },
c0c31e91
RZ		 1353#define F_NJ (F_PNZ + 1)
1354 { "nj", 21, 5, 0, 1 },
1355#define F_NM (F_NJ + 1)
1356 { "nm", 23, 5, 0, 1 },
1357#define F_NO_T (F_NM + 1)
1358 { "nt", 24, 5, 0, 1 },
886a2506
NC		 1359
1360 /* FLAG. */
c0c31e91 1361#define F_FLAG (F_NO_T + 1)
886a2506
NC		 1362 { "f", 1, 1, 15, 1 },
1363#define F_FFAKE (F_FLAG + 1)
1364 { "f", 0, 0, 0, 1 },
1365
1366 /* Delay slot. */
1367#define F_ND (F_FFAKE + 1)
1368 { "nd", 0, 1, 5, 0 },
1369#define F_D (F_ND + 1)
1370 { "d", 1, 1, 5, 1 },
1371#define F_DFAKE (F_D + 1)
1372 { "d", 0, 0, 0, 1 },
2b848ebd
CZ		 1373#define F_DNZ_ND (F_DFAKE + 1)
1374 { "nd", 0, 1, 16, 0 },
1375#define F_DNZ_D (F_DNZ_ND + 1)
1376 { "d", 1, 1, 16, 1 },
886a2506
NC		 1377
1378 /* Data size. */
2b848ebd 1379#define F_SIZEB1 (F_DNZ_D + 1)
886a2506
NC		 1380 { "b", 1, 2, 1, 1 },
1381#define F_SIZEB7 (F_SIZEB1 + 1)
1382 { "b", 1, 2, 7, 1 },
1383#define F_SIZEB17 (F_SIZEB7 + 1)
1384 { "b", 1, 2, 17, 1 },
1385#define F_SIZEW1 (F_SIZEB17 + 1)
1386 { "w", 2, 2, 1, 0 },
1387#define F_SIZEW7 (F_SIZEW1 + 1)
1388 { "w", 2, 2, 7, 0 },
1389#define F_SIZEW17 (F_SIZEW7 + 1)
1390 { "w", 2, 2, 17, 0 },
1391
1392 /* Sign extension. */
1393#define F_SIGN6 (F_SIZEW17 + 1)
1394 { "x", 1, 1, 6, 1 },
1395#define F_SIGN16 (F_SIGN6 + 1)
1396 { "x", 1, 1, 16, 1 },
1397#define F_SIGNX (F_SIGN16 + 1)
1398 { "x", 0, 0, 0, 1 },
1399
1400 /* Address write-back modes. */
1401#define F_A3 (F_SIGNX + 1)
1402 { "a", 1, 2, 3, 0 },
1403#define F_A9 (F_A3 + 1)
1404 { "a", 1, 2, 9, 0 },
1405#define F_A22 (F_A9 + 1)
1406 { "a", 1, 2, 22, 0 },
1407#define F_AW3 (F_A22 + 1)
1408 { "aw", 1, 2, 3, 1 },
1409#define F_AW9 (F_AW3 + 1)
1410 { "aw", 1, 2, 9, 1 },
1411#define F_AW22 (F_AW9 + 1)
1412 { "aw", 1, 2, 22, 1 },
1413#define F_AB3 (F_AW22 + 1)
1414 { "ab", 2, 2, 3, 1 },
1415#define F_AB9 (F_AB3 + 1)
1416 { "ab", 2, 2, 9, 1 },
1417#define F_AB22 (F_AB9 + 1)
1418 { "ab", 2, 2, 22, 1 },
1419#define F_AS3 (F_AB22 + 1)
1420 { "as", 3, 2, 3, 1 },
1421#define F_AS9 (F_AS3 + 1)
1422 { "as", 3, 2, 9, 1 },
1423#define F_AS22 (F_AS9 + 1)
1424 { "as", 3, 2, 22, 1 },
1425#define F_ASFAKE (F_AS22 + 1)
1426 { "as", 0, 0, 0, 1 },
1427
1428 /* Cache bypass. */
1429#define F_DI5 (F_ASFAKE + 1)
1430 { "di", 1, 1, 5, 1 },
1431#define F_DI11 (F_DI5 + 1)
1432 { "di", 1, 1, 11, 1 },
b437d035
AB		 1433#define F_DI14 (F_DI11 + 1)
1434 { "di", 1, 1, 14, 1 },
1435#define F_DI15 (F_DI14 + 1)
886a2506
NC		 1436 { "di", 1, 1, 15, 1 },
1437
1438 /* ARCv2 specific. */
1439#define F_NT (F_DI15 + 1)
1440 { "nt", 0, 1, 3, 1},
1441#define F_T (F_NT + 1)
1442 { "t", 1, 1, 3, 1},
1443#define F_H1 (F_T + 1)
1444 { "h", 2, 2, 1, 1 },
1445#define F_H7 (F_H1 + 1)
1446 { "h", 2, 2, 7, 1 },
1447#define F_H17 (F_H7 + 1)
1448 { "h", 2, 2, 17, 1 },
6ec7c1ae
CZ		 1449#define F_SIZED (F_H17 + 1)
1450 { "dd", 8, 0, 0, 0 }, /* Fake. */
886a2506
NC		 1451
1452 /* Fake Flags. */
6ec7c1ae 1453#define F_NE (F_SIZED + 1)
886a2506 1454 { "ne", 0, 0, 0, 1 },
e23e8ebe
AB		 1455
1456 /* ARC NPS400 Support: See comment near head of file. */
1457#define F_NPS_CL (F_NE + 1)
1458 { "cl", 0, 0, 0, 1 },
1459
645d3342
RZ		 1460#define F_NPS_NA (F_NPS_CL + 1)
1461 { "na", 1, 1, 9, 1 },
1462
c0c31e91
RZ		 1463#define F_NPS_SR (F_NPS_NA + 1)
1464 { "s", 1, 1, 13, 1 },
1465
1466#define F_NPS_M (F_NPS_SR + 1)
1467 { "m", 1, 1, 7, 1 },
1468
1469#define F_NPS_FLAG (F_NPS_M + 1)
e23e8ebe 1470 { "f", 1, 1, 20, 1 },
820f03ff
AB		 1471
1472#define F_NPS_R (F_NPS_FLAG + 1)
1473 { "r", 1, 1, 15, 1 },
a42a4f84
AB		 1474
1475#define F_NPS_RW (F_NPS_R + 1)
1476 { "rw", 0, 1, 7, 1 },
1477
1478#define F_NPS_RD (F_NPS_RW + 1)
1479 { "rd", 1, 1, 7, 1 },
1480
1481#define F_NPS_WFT (F_NPS_RD + 1)
1482 { "wft", 0, 0, 0, 1 },
1483
1484#define F_NPS_IE1 (F_NPS_WFT + 1)
1485 { "ie1", 1, 2, 8, 1 },
1486
1487#define F_NPS_IE2 (F_NPS_IE1 + 1)
1488 { "ie2", 2, 2, 8, 1 },
1489
1490#define F_NPS_IE12 (F_NPS_IE2 + 1)
1491 { "ie12", 3, 2, 8, 1 },
1492
1493#define F_NPS_SYNC_RD (F_NPS_IE12 + 1)
1494 { "rd", 0, 1, 6, 1 },
1495
1496#define F_NPS_SYNC_WR (F_NPS_SYNC_RD + 1)
1497 { "wr", 1, 1, 6, 1 },
1498
1499#define F_NPS_HWS_OFF (F_NPS_SYNC_WR + 1)
1500 { "off", 0, 0, 0, 1 },
1501
1502#define F_NPS_HWS_RESTORE (F_NPS_HWS_OFF + 1)
1503 { "restore", 0, 0, 0, 1 },
1504
537aefaf
AB		 1505#define F_NPS_SX (F_NPS_HWS_RESTORE + 1)
1506 { "sx", 1, 1, 14, 1 },
1507
1508#define F_NPS_AR (F_NPS_SX + 1)
1509 { "ar", 0, 1, 0, 1 },
1510
1511#define F_NPS_AL (F_NPS_AR + 1)
1512 { "al", 1, 1, 0, 1 },
14053c19
GM		 1513
1514#define F_NPS_S (F_NPS_AL + 1)
1515 { "s", 0, 0, 0, 1 },
1516
1517#define F_NPS_ZNCV_RD (F_NPS_S + 1)
1518 { "rd", 0, 1, 15, 1 },
1519
1520#define F_NPS_ZNCV_WR (F_NPS_ZNCV_RD + 1)
1521 { "wr", 1, 1, 15, 1 },
9ba75c88
GM		 1522
1523#define F_NPS_P0 (F_NPS_ZNCV_WR + 1)
1524 { "p0", 0, 0, 0, 1 },
1525
1526#define F_NPS_P1 (F_NPS_P0 + 1)
1527 { "p1", 0, 0, 0, 1 },
1528
1529#define F_NPS_P2 (F_NPS_P1 + 1)
1530 { "p2", 0, 0, 0, 1 },
1531
1532#define F_NPS_P3 (F_NPS_P2 + 1)
1533 { "p3", 0, 0, 0, 1 },
28215275
GM		 1534
1535#define F_NPS_LDBIT_DI (F_NPS_P3 + 1)
1536 { "di", 0, 0, 0, 1 },
1537
1538#define F_NPS_LDBIT_CL1 (F_NPS_LDBIT_DI + 1)
1539 { "cl", 1, 1, 6, 1 },
1540
1541#define F_NPS_LDBIT_CL2 (F_NPS_LDBIT_CL1 + 1)
1542 { "cl", 1, 1, 16, 1 },
1543
1544#define F_NPS_LDBIT_X2_1 (F_NPS_LDBIT_CL2 + 1)
1545 { "x2", 1, 2, 9, 1 },
1546
1547#define F_NPS_LDBIT_X2_2 (F_NPS_LDBIT_X2_1 + 1)
1548 { "x2", 1, 2, 22, 1 },
1549
1550#define F_NPS_LDBIT_X4_1 (F_NPS_LDBIT_X2_2 + 1)
1551 { "x4", 2, 2, 9, 1 },
1552
1553#define F_NPS_LDBIT_X4_2 (F_NPS_LDBIT_X4_1 + 1)
1554 { "x4", 2, 2, 22, 1 },
c0c31e91
RZ		 1555
1556#define F_NPS_CORE (F_NPS_LDBIT_X4_2 + 1)
1557 { "core", 1, 3, 6, 1 },
1558
1559#define F_NPS_CLSR (F_NPS_CORE + 1)
1560 { "clsr", 2, 3, 6, 1 },
1561
1562#define F_NPS_ALL (F_NPS_CLSR + 1)
1563 { "all", 3, 3, 6, 1 },
1564
1565#define F_NPS_GIC (F_NPS_ALL + 1)
1566 { "gic", 4, 3, 6, 1 },
1567
1568#define F_NPS_RSPI_GIC (F_NPS_GIC + 1)
1569 { "gic", 5, 3, 6, 1 },
886a2506 1570};
252b5132 1571
886a2506 1572const unsigned arc_num_flag_operands = ARRAY_SIZE (arc_flag_operands);
252b5132 1573
886a2506 1574/* Table of the flag classes.
252b5132 1575
886a2506
NC		 1576 The format of the table is
1577 CLASS {FLAG_CODE}. */
1578const struct arc_flag_class arc_flag_classes[] =
1579{
1580#define C_EMPTY 0
1ae8ab47 1581 { F_CLASS_NONE, { F_NULL } },
886a2506 1582
6ec7c1ae
CZ		 1583#define C_CC_EQ (C_EMPTY + 1)
1584 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_EQUAL, F_NULL} },
1585
1586#define C_CC_GE (C_CC_EQ + 1)
1587 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GE, F_NULL} },
1588
1589#define C_CC_GT (C_CC_GE + 1)
1590 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_GT, F_NULL} },
1591
1592#define C_CC_HI (C_CC_GT + 1)
1593 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_HI, F_NULL} },
1594
1595#define C_CC_HS (C_CC_HI + 1)
1596 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTCARRY, F_NULL} },
1597
1598#define C_CC_LE (C_CC_HS + 1)
1599 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LE, F_NULL} },
1600
1601#define C_CC_LO (C_CC_LE + 1)
1602 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_CARRY, F_NULL} },
1603
1604#define C_CC_LS (C_CC_LO + 1)
1605 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LS, F_NULL} },
1606
1607#define C_CC_LT (C_CC_LS + 1)
1608 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_LT, F_NULL} },
1609
1610#define C_CC_NE (C_CC_LT + 1)
1611 {F_CLASS_IMPLICIT | F_CLASS_COND, {F_NOTEQUAL, F_NULL} },
1612
1613#define C_AA_AB (C_CC_NE + 1)
1614 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AB3, F_NULL} },
1615
1616#define C_AA_AW (C_AA_AB + 1)
1617 {F_CLASS_IMPLICIT | F_CLASS_WB, {F_AW3, F_NULL} },
1618
1619#define C_ZZ_D (C_AA_AW + 1)
1620 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZED, F_NULL} },
1621
1622#define C_ZZ_H (C_ZZ_D + 1)
1623 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_H1, F_NULL} },
1624
1625#define C_ZZ_B (C_ZZ_H + 1)
1626 {F_CLASS_IMPLICIT | F_CLASS_ZZ, {F_SIZEB1, F_NULL} },
1627
1628#define C_CC (C_ZZ_B + 1)
d9eca1df 1629 { F_CLASS_OPTIONAL | F_CLASS_EXTEND | F_CLASS_COND,
f36e33da
CZ		 1630 { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL,
1631 F_NOTZERO, F_POZITIVE, F_PL, F_NEGATIVE, F_MINUS,
1632 F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
1633 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW,
1634 F_NOTOVERFLOW, F_OVERFLOWCLR, F_GT, F_GE, F_LT,
c0c31e91 1635 F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM, F_NO_T, F_NULL } },
886a2506
NC		 1636
1637#define C_AA_ADDR3 (C_CC + 1)
1638#define C_AA27 (C_CC + 1)
6ec7c1ae 1639 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A3, F_AW3, F_AB3, F_AS3, F_NULL } },
886a2506
NC		 1640#define C_AA_ADDR9 (C_AA_ADDR3 + 1)
1641#define C_AA21 (C_AA_ADDR3 + 1)
6ec7c1ae 1642 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A9, F_AW9, F_AB9, F_AS9, F_NULL } },
886a2506
NC		 1643#define C_AA_ADDR22 (C_AA_ADDR9 + 1)
1644#define C_AA8 (C_AA_ADDR9 + 1)
6ec7c1ae 1645 { F_CLASS_OPTIONAL | F_CLASS_WB, { F_A22, F_AW22, F_AB22, F_AS22, F_NULL } },
886a2506
NC		 1646
1647#define C_F (C_AA_ADDR22 + 1)
1ae8ab47 1648 { F_CLASS_OPTIONAL, { F_FLAG, F_NULL } },
886a2506 1649#define C_FHARD (C_F + 1)
1ae8ab47 1650 { F_CLASS_OPTIONAL, { F_FFAKE, F_NULL } },
886a2506
NC		 1651
1652#define C_T (C_FHARD + 1)
1ae8ab47 1653 { F_CLASS_OPTIONAL, { F_NT, F_T, F_NULL } },
886a2506 1654#define C_D (C_T + 1)
1ae8ab47 1655 { F_CLASS_OPTIONAL, { F_ND, F_D, F_NULL } },
2b848ebd
CZ		 1656#define C_DNZ_D (C_D + 1)
1657 { F_CLASS_OPTIONAL, { F_DNZ_ND, F_DNZ_D, F_NULL } },
886a2506 1658
2b848ebd 1659#define C_DHARD (C_DNZ_D + 1)
1ae8ab47 1660 { F_CLASS_OPTIONAL, { F_DFAKE, F_NULL } },
886a2506
NC		 1661
1662#define C_DI20 (C_DHARD + 1)
1ae8ab47 1663 { F_CLASS_OPTIONAL, { F_DI11, F_NULL }},
b437d035
AB		 1664#define C_DI14 (C_DI20 + 1)
1665 { F_CLASS_OPTIONAL, { F_DI14, F_NULL }},
1666#define C_DI16 (C_DI14 + 1)
1ae8ab47 1667 { F_CLASS_OPTIONAL, { F_DI15, F_NULL }},
886a2506 1668#define C_DI26 (C_DI16 + 1)
1ae8ab47 1669 { F_CLASS_OPTIONAL, { F_DI5, F_NULL }},
886a2506
NC		 1670
1671#define C_X25 (C_DI26 + 1)
1ae8ab47 1672 { F_CLASS_OPTIONAL, { F_SIGN6, F_NULL }},
886a2506 1673#define C_X15 (C_X25 + 1)
1ae8ab47 1674 { F_CLASS_OPTIONAL, { F_SIGN16, F_NULL }},
886a2506
NC		 1675#define C_XHARD (C_X15 + 1)
1676#define C_X (C_X15 + 1)
1ae8ab47 1677 { F_CLASS_OPTIONAL, { F_SIGNX, F_NULL }},
886a2506
NC		 1678
1679#define C_ZZ13 (C_X + 1)
1ae8ab47 1680 { F_CLASS_OPTIONAL, { F_SIZEB17, F_SIZEW17, F_H17, F_NULL}},
886a2506 1681#define C_ZZ23 (C_ZZ13 + 1)
1ae8ab47 1682 { F_CLASS_OPTIONAL, { F_SIZEB7, F_SIZEW7, F_H7, F_NULL}},
886a2506 1683#define C_ZZ29 (C_ZZ23 + 1)
1ae8ab47 1684 { F_CLASS_OPTIONAL, { F_SIZEB1, F_SIZEW1, F_H1, F_NULL}},
886a2506
NC		 1685
1686#define C_AS (C_ZZ29 + 1)
1ae8ab47 1687 { F_CLASS_OPTIONAL, { F_ASFAKE, F_NULL}},
886a2506
NC		 1688
1689#define C_NE (C_AS + 1)
1ae8ab47 1690 { F_CLASS_OPTIONAL, { F_NE, F_NULL}},
e23e8ebe
AB		 1691
1692 /* ARC NPS400 Support: See comment near head of file. */
1693#define C_NPS_CL (C_NE + 1)
1694 { F_CLASS_REQUIRED, { F_NPS_CL, F_NULL}},
1695
645d3342
RZ		 1696#define C_NPS_NA (C_NPS_CL + 1)
1697 { F_CLASS_OPTIONAL, { F_NPS_NA, F_NULL}},
1698
c0c31e91
RZ		 1699#define C_NPS_SR (C_NPS_NA + 1)
1700 { F_CLASS_OPTIONAL, { F_NPS_SR, F_NULL}},
1701
1702#define C_NPS_M (C_NPS_SR + 1)
1703 { F_CLASS_OPTIONAL, { F_NPS_M, F_NULL}},
1704
1705#define C_NPS_F (C_NPS_M + 1)
e23e8ebe 1706 { F_CLASS_OPTIONAL, { F_NPS_FLAG, F_NULL}},
820f03ff
AB		 1707
1708#define C_NPS_R (C_NPS_F + 1)
1709 { F_CLASS_OPTIONAL, { F_NPS_R, F_NULL}},
a42a4f84
AB		 1710
1711#define C_NPS_SCHD_RW (C_NPS_R + 1)
1712 { F_CLASS_REQUIRED, { F_NPS_RW, F_NPS_RD, F_NULL}},
1713
1714#define C_NPS_SCHD_TRIG (C_NPS_SCHD_RW + 1)
1715 { F_CLASS_REQUIRED, { F_NPS_WFT, F_NULL}},
1716
1717#define C_NPS_SCHD_IE (C_NPS_SCHD_TRIG + 1)
1718 { F_CLASS_OPTIONAL, { F_NPS_IE1, F_NPS_IE2, F_NPS_IE12, F_NULL}},
1719
1720#define C_NPS_SYNC (C_NPS_SCHD_IE + 1)
1721 { F_CLASS_REQUIRED, { F_NPS_SYNC_RD, F_NPS_SYNC_WR, F_NULL}},
1722
1723#define C_NPS_HWS_OFF (C_NPS_SYNC + 1)
1724 { F_CLASS_REQUIRED, { F_NPS_HWS_OFF, F_NULL}},
1725
1726#define C_NPS_HWS_RESTORE (C_NPS_HWS_OFF + 1)
1727 { F_CLASS_REQUIRED, { F_NPS_HWS_RESTORE, F_NULL}},
1728
537aefaf
AB		 1729#define C_NPS_SX (C_NPS_HWS_RESTORE + 1)
1730 { F_CLASS_OPTIONAL, { F_NPS_SX, F_NULL}},
1731
1732#define C_NPS_AR_AL (C_NPS_SX + 1)
1733 { F_CLASS_REQUIRED, { F_NPS_AR, F_NPS_AL, F_NULL}},
14053c19
GM		 1734
1735#define C_NPS_S (C_NPS_AR_AL + 1)
1736 { F_CLASS_REQUIRED, { F_NPS_S, F_NULL}},
1737
1738#define C_NPS_ZNCV (C_NPS_S + 1)
1739 { F_CLASS_REQUIRED, { F_NPS_ZNCV_RD, F_NPS_ZNCV_WR, F_NULL}},
9ba75c88
GM		 1740
1741#define C_NPS_P0 (C_NPS_ZNCV + 1)
1742 { F_CLASS_REQUIRED, { F_NPS_P0, F_NULL }},
1743
1744#define C_NPS_P1 (C_NPS_P0 + 1)
1745 { F_CLASS_REQUIRED, { F_NPS_P1, F_NULL }},
1746
1747#define C_NPS_P2 (C_NPS_P1 + 1)
1748 { F_CLASS_REQUIRED, { F_NPS_P2, F_NULL }},
1749
1750#define C_NPS_P3 (C_NPS_P2 + 1)
1751 { F_CLASS_REQUIRED, { F_NPS_P3, F_NULL }},
28215275
GM		 1752
1753#define C_NPS_LDBIT_DI (C_NPS_P3 + 1)
1754 { F_CLASS_REQUIRED, { F_NPS_LDBIT_DI, F_NULL }},
1755
1756#define C_NPS_LDBIT_CL1 (C_NPS_LDBIT_DI + 1)
1757 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL1, F_NULL }},
1758
1759#define C_NPS_LDBIT_CL2 (C_NPS_LDBIT_CL1 + 1)
1760 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_CL2, F_NULL }},
1761
1762#define C_NPS_LDBIT_X_1 (C_NPS_LDBIT_CL2 + 1)
1763 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_1, F_NPS_LDBIT_X4_1, F_NULL }},
1764
1765#define C_NPS_LDBIT_X_2 (C_NPS_LDBIT_X_1 + 1)
1766 { F_CLASS_OPTIONAL, { F_NPS_LDBIT_X2_2, F_NPS_LDBIT_X4_2, F_NULL }},
c0c31e91
RZ		 1767
1768#define C_NPS_CORE (C_NPS_LDBIT_X_2 + 1)
1769 { F_CLASS_REQUIRED, { F_NPS_CORE, F_NULL}},
1770
1771#define C_NPS_CLSR (C_NPS_CORE + 1)
1772 { F_CLASS_REQUIRED, { F_NPS_CLSR, F_NULL}},
1773
1774#define C_NPS_ALL (C_NPS_CLSR + 1)
1775 { F_CLASS_REQUIRED, { F_NPS_ALL, F_NULL}},
1776
1777#define C_NPS_GIC (C_NPS_ALL + 1)
1778 { F_CLASS_REQUIRED, { F_NPS_GIC, F_NULL}},
1779
1780#define C_NPS_RSPI_GIC (C_NPS_GIC + 1)
1781 { F_CLASS_REQUIRED, { F_NPS_RSPI_GIC, F_NULL}},
886a2506 1782};
252b5132 1783
b99747ae
CZ		 1784const unsigned char flags_none[] = { 0 };
1785const unsigned char flags_f[] = { C_F };
1786const unsigned char flags_cc[] = { C_CC };
1787const unsigned char flags_ccf[] = { C_CC, C_F };
1788
886a2506 1789/* The operands table.
252b5132 1790
886a2506 1791 The format of the operands table is:
47b0e7ad 1792
886a2506
NC		 1793 BITS SHIFT DEFAULT_RELOC FLAGS INSERT_FUN EXTRACT_FUN. */
1794const struct arc_operand arc_operands[] =
0d2bcfaf 1795{
886a2506
NC		 1796 /* The fields are bits, shift, insert, extract, flags. The zero
1797 index is used to indicate end-of-list. */
1798#define UNUSED 0
1799 { 0, 0, 0, 0, 0, 0 },
4eb6f892
AB		 1800
1801#define IGNORED (UNUSED + 1)
1802 { 0, 0, 0, ARC_OPERAND_IGNORE | ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK, 0, 0 },
1803
886a2506
NC		 1804 /* The plain integer register fields. Used by 32 bit
1805 instructions. */
4eb6f892 1806#define RA (IGNORED + 1)
886a2506 1807 { 6, 0, 0, ARC_OPERAND_IR, 0, 0 },
abe7c33b
CZ		 1808#define RA_CHK (RA + 1)
1809 { 6, 0, 0, ARC_OPERAND_IR, insert_ra_chk, 0 },
1810#define RB (RA_CHK + 1)
886a2506 1811 { 6, 12, 0, ARC_OPERAND_IR, insert_rb, extract_rb },
abe7c33b
CZ		 1812#define RB_CHK (RB + 1)
1813 { 6, 12, 0, ARC_OPERAND_IR, insert_rb_chk, extract_rb },
1814#define RC (RB_CHK + 1)
886a2506
NC		 1815 { 6, 6, 0, ARC_OPERAND_IR, 0, 0 },
1816#define RBdup (RC + 1)
1817 { 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rb, extract_rb },
1818
1819#define RAD (RBdup + 1)
1820 { 6, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rad, 0 },
1821#define RCD (RAD + 1)
1822 { 6, 6, 0, ARC_OPERAND_IR | ARC_OPERAND_TRUNCATE, insert_rcd, 0 },
1823
1824 /* The plain integer register fields. Used by short
1825 instructions. */
1826#define RA16 (RCD + 1)
1827#define RA_S (RCD + 1)
1828 { 4, 0, 0, ARC_OPERAND_IR, insert_ras, extract_ras },
1829#define RB16 (RA16 + 1)
1830#define RB_S (RA16 + 1)
1831 { 4, 8, 0, ARC_OPERAND_IR, insert_rbs, extract_rbs },
1832#define RB16dup (RB16 + 1)
1833#define RB_Sdup (RB16 + 1)
1834 { 4, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_rbs, extract_rbs },
1835#define RC16 (RB16dup + 1)
1836#define RC_S (RB16dup + 1)
1837 { 4, 5, 0, ARC_OPERAND_IR, insert_rcs, extract_rcs },
1838#define R6H (RC16 + 1) /* 6bit register field 'h' used
1839 by V1 cpus. */
1840 { 6, 5, 0, ARC_OPERAND_IR, insert_rhv1, extract_rhv1 },
1841#define R5H (R6H + 1) /* 5bit register field 'h' used
1842 by V2 cpus. */
1843#define RH_S (R6H + 1) /* 5bit register field 'h' used
1844 by V2 cpus. */
1845 { 5, 5, 0, ARC_OPERAND_IR, insert_rhv2, extract_rhv2 },
1846#define R5Hdup (R5H + 1)
1847#define RH_Sdup (R5H + 1)
1848 { 5, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE,
1849 insert_rhv2, extract_rhv2 },
1850
1851#define RG (R5Hdup + 1)
1852#define G_S (R5Hdup + 1)
1853 { 5, 5, 0, ARC_OPERAND_IR, insert_g_s, extract_g_s },
1854
1855 /* Fix registers. */
1856#define R0 (RG + 1)
1857#define R0_S (RG + 1)
1858 { 0, 0, 0, ARC_OPERAND_IR, insert_r0, extract_r0 },
1859#define R1 (R0 + 1)
1860#define R1_S (R0 + 1)
1861 { 1, 0, 0, ARC_OPERAND_IR, insert_r1, extract_r1 },
1862#define R2 (R1 + 1)
1863#define R2_S (R1 + 1)
1864 { 2, 0, 0, ARC_OPERAND_IR, insert_r2, extract_r2 },
1865#define R3 (R2 + 1)
1866#define R3_S (R2 + 1)
1867 { 2, 0, 0, ARC_OPERAND_IR, insert_r3, extract_r3 },
8ddf6b2a 1868#define RSP (R3 + 1)
886a2506
NC		 1869#define SP_S (R3 + 1)
1870 { 5, 0, 0, ARC_OPERAND_IR, insert_sp, extract_sp },
8ddf6b2a
CZ		 1871#define SPdup (RSP + 1)
1872#define SP_Sdup (RSP + 1)
886a2506
NC		 1873 { 5, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, insert_sp, extract_sp },
1874#define GP (SPdup + 1)
1875#define GP_S (SPdup + 1)
1876 { 5, 0, 0, ARC_OPERAND_IR, insert_gp, extract_gp },
1877
1878#define PCL_S (GP + 1)
1879 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK, insert_pcl, extract_pcl },
1880
1881#define BLINK (PCL_S + 1)
1882#define BLINK_S (PCL_S + 1)
1883 { 5, 0, 0, ARC_OPERAND_IR, insert_blink, extract_blink },
1884
1885#define ILINK1 (BLINK + 1)
1886 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink1, extract_ilink1 },
1887#define ILINK2 (ILINK1 + 1)
1888 { 5, 0, 0, ARC_OPERAND_IR, insert_ilink2, extract_ilink2 },
1889
1890 /* Long immediate. */
1891#define LIMM (ILINK2 + 1)
1892#define LIMM_S (ILINK2 + 1)
1893 { 32, 0, BFD_RELOC_ARC_32_ME, ARC_OPERAND_LIMM, insert_limm, 0 },
1894#define LIMMdup (LIMM + 1)
1895 { 32, 0, 0, ARC_OPERAND_LIMM | ARC_OPERAND_DUPLICATE, insert_limm, 0 },
1896
1897 /* Special operands. */
1898#define ZA (LIMMdup + 1)
1899#define ZB (LIMMdup + 1)
1900#define ZA_S (LIMMdup + 1)
1901#define ZB_S (LIMMdup + 1)
1902#define ZC_S (LIMMdup + 1)
1903 { 0, 0, 0, ARC_OPERAND_UNSIGNED, insert_za, 0 },
1904
1905#define RRANGE_EL (ZA + 1)
1906 { 4, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK | ARC_OPERAND_TRUNCATE,
1907 insert_rrange, extract_rrange},
126124cc
CZ		 1908#define R13_EL (RRANGE_EL + 1)
1909 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1910 insert_r13el, extract_rrange },
1911#define FP_EL (R13_EL + 1)
886a2506
NC		 1912 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1913 insert_fpel, extract_fpel },
1914#define BLINK_EL (FP_EL + 1)
1915 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1916 insert_blinkel, extract_blinkel },
1917#define PCL_EL (BLINK_EL + 1)
1918 { 1, 0, 0, ARC_OPERAND_IR | ARC_OPERAND_IGNORE | ARC_OPERAND_NCHK,
1919 insert_pclel, extract_pclel },
1920
1921 /* Fake operand to handle the T flag. */
1922#define BRAKET (PCL_EL + 1)
1923#define BRAKETdup (PCL_EL + 1)
1924 { 0, 0, 0, ARC_OPERAND_FAKE | ARC_OPERAND_BRAKET, 0, 0 },
1925
1926 /* Fake operand to handle the T flag. */
1927#define FKT_T (BRAKET + 1)
1928 { 1, 3, 0, ARC_OPERAND_FAKE, insert_Ybit, 0 },
1929 /* Fake operand to handle the T flag. */
1930#define FKT_NT (FKT_T + 1)
1931 { 1, 3, 0, ARC_OPERAND_FAKE, insert_NYbit, 0 },
1932
1933 /* UIMM6_20 mask = 00000000000000000000111111000000. */
1934#define UIMM6_20 (FKT_NT + 1)
1935 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_20, extract_uimm6_20},
1936
cc07cda6
CZ		 1937 /* Exactly like the above but used by relaxation. */
1938#define UIMM6_20R (UIMM6_20 + 1)
1939 {6, 0, -UIMM6_20R, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1940 insert_uimm6_20, extract_uimm6_20},
1941
886a2506 1942 /* SIMM12_20 mask = 00000000000000000000111111222222. */
cc07cda6 1943#define SIMM12_20 (UIMM6_20R + 1)
886a2506
NC		 1944 {12, 0, 0, ARC_OPERAND_SIGNED, insert_simm12_20, extract_simm12_20},
1945
cc07cda6
CZ		 1946 /* Exactly like the above but used by relaxation. */
1947#define SIMM12_20R (SIMM12_20 + 1)
1948 {12, 0, -SIMM12_20R, ARC_OPERAND_SIGNED | ARC_OPERAND_PCREL,
1949 insert_simm12_20, extract_simm12_20},
1950
7179e0e6
CZ		 1951 /* UIMM12_20 mask = 00000000000000000000111111222222. */
1952#define UIMM12_20 (SIMM12_20R + 1)
1953 {12, 0, 0, ARC_OPERAND_UNSIGNED, insert_simm12_20, extract_uimm12_20},
1954
886a2506 1955 /* SIMM3_5_S mask = 0000011100000000. */
7179e0e6 1956#define SIMM3_5_S (UIMM12_20 + 1)
886a2506
NC		 1957 {3, 0, 0, ARC_OPERAND_SIGNED | ARC_OPERAND_NCHK,
1958 insert_simm3s, extract_simm3s},
1959
1960 /* UIMM7_A32_11_S mask = 0000000000011111. */
1961#define UIMM7_A32_11_S (SIMM3_5_S + 1)
1962 {7, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1963 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm7_a32_11_s,
1964 extract_uimm7_a32_11_s},
1965
cc07cda6
CZ		 1966 /* The same as above but used by relaxation. */
1967#define UIMM7_A32_11R_S (UIMM7_A32_11_S + 1)
1968 {7, 0, -UIMM7_A32_11R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
1969 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE | ARC_OPERAND_PCREL,
1970 insert_uimm7_a32_11_s, extract_uimm7_a32_11_s},
1971
886a2506 1972 /* UIMM7_9_S mask = 0000000001111111. */
cc07cda6 1973#define UIMM7_9_S (UIMM7_A32_11R_S + 1)
886a2506
NC		 1974 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_9_s, extract_uimm7_9_s},
1975
1976 /* UIMM3_13_S mask = 0000000000000111. */
1977#define UIMM3_13_S (UIMM7_9_S + 1)
1978 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_13_s, extract_uimm3_13_s},
1979
cc07cda6
CZ		 1980 /* Exactly like the above but used for relaxation. */
1981#define UIMM3_13R_S (UIMM3_13_S + 1)
1982 {3, 0, -UIMM3_13R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
1983 insert_uimm3_13_s, extract_uimm3_13_s},
1984
886a2506 1985 /* SIMM11_A32_7_S mask = 0000000111111111. */
cc07cda6 1986#define SIMM11_A32_7_S (UIMM3_13R_S + 1)
886a2506
NC		 1987 {11, 0, BFD_RELOC_ARC_SDA16_LD2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
1988 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_7_s, extract_simm11_a32_7_s},
1989
1990 /* UIMM6_13_S mask = 0000000002220111. */
1991#define UIMM6_13_S (SIMM11_A32_7_S + 1)
1992 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_13_s, extract_uimm6_13_s},
1993 /* UIMM5_11_S mask = 0000000000011111. */
1994#define UIMM5_11_S (UIMM6_13_S + 1)
1995 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_IGNORE, insert_uimm5_11_s,
1996 extract_uimm5_11_s},
1997
1998 /* SIMM9_A16_8 mask = 00000000111111102000000000000000. */
1999#define SIMM9_A16_8 (UIMM5_11_S + 1)
2000 {9, 0, -SIMM9_A16_8, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2001 | ARC_OPERAND_PCREL | ARC_OPERAND_TRUNCATE, insert_simm9_a16_8,
2002 extract_simm9_a16_8},
2003
2004 /* UIMM6_8 mask = 00000000000000000000111111000000. */
2005#define UIMM6_8 (SIMM9_A16_8 + 1)
2006 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_8, extract_uimm6_8},
2007
2008 /* SIMM21_A16_5 mask = 00000111111111102222222222000000. */
2009#define SIMM21_A16_5 (UIMM6_8 + 1)
2010 {21, 0, BFD_RELOC_ARC_S21H_PCREL, ARC_OPERAND_SIGNED
50d2740d 2011 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
886a2506
NC		 2012 insert_simm21_a16_5, extract_simm21_a16_5},
2013
2014 /* SIMM25_A16_5 mask = 00000111111111102222222222003333. */
2015#define SIMM25_A16_5 (SIMM21_A16_5 + 1)
2016 {25, 0, BFD_RELOC_ARC_S25H_PCREL, ARC_OPERAND_SIGNED
2017 | ARC_OPERAND_ALIGNED16 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL,
2018 insert_simm25_a16_5, extract_simm25_a16_5},
2019
2020 /* SIMM10_A16_7_S mask = 0000000111111111. */
2021#define SIMM10_A16_7_S (SIMM25_A16_5 + 1)
2022 {10, 0, -SIMM10_A16_7_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2023 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm10_a16_7_s,
2024 extract_simm10_a16_7_s},
2025
2026#define SIMM10_A16_7_Sbis (SIMM10_A16_7_S + 1)
2027 {10, 0, -SIMM10_A16_7_Sbis, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2028 | ARC_OPERAND_TRUNCATE, insert_simm10_a16_7_s, extract_simm10_a16_7_s},
2029
2030 /* SIMM7_A16_10_S mask = 0000000000111111. */
2031#define SIMM7_A16_10_S (SIMM10_A16_7_Sbis + 1)
2032 {7, 0, -SIMM7_A16_10_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2033 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm7_a16_10_s,
2034 extract_simm7_a16_10_s},
2035
2036 /* SIMM21_A32_5 mask = 00000111111111002222222222000000. */
2037#define SIMM21_A32_5 (SIMM7_A16_10_S + 1)
2038 {21, 0, BFD_RELOC_ARC_S21W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2039 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm21_a32_5,
2040 extract_simm21_a32_5},
2041
2042 /* SIMM25_A32_5 mask = 00000111111111002222222222003333. */
2043#define SIMM25_A32_5 (SIMM21_A32_5 + 1)
2044 {25, 0, BFD_RELOC_ARC_S25W_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2045 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm25_a32_5,
2046 extract_simm25_a32_5},
2047
2048 /* SIMM13_A32_5_S mask = 0000011111111111. */
2049#define SIMM13_A32_5_S (SIMM25_A32_5 + 1)
2050 {13, 0, BFD_RELOC_ARC_S13_PCREL, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2051 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a32_5_s,
2052 extract_simm13_a32_5_s},
2053
2054 /* SIMM8_A16_9_S mask = 0000000001111111. */
2055#define SIMM8_A16_9_S (SIMM13_A32_5_S + 1)
2056 {8, 0, -SIMM8_A16_9_S, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2057 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm8_a16_9_s,
2058 extract_simm8_a16_9_s},
2059
684d5a10
JEM		 2060/* UIMM10_6_S_JLIOFF mask = 0000001111111111. */
2061#define UIMM10_6_S_JLIOFF (SIMM8_A16_9_S + 1)
2062 {12, 0, BFD_RELOC_ARC_JLI_SECTOFF, ARC_OPERAND_UNSIGNED
2063 | ARC_OPERAND_ALIGNED32 | ARC_OPERAND_TRUNCATE, insert_uimm10_6_s,
2064 extract_uimm10_6_s},
2065
886a2506 2066 /* UIMM3_23 mask = 00000000000000000000000111000000. */
684d5a10 2067#define UIMM3_23 (UIMM10_6_S_JLIOFF + 1)
886a2506
NC		 2068 {3, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm3_23, extract_uimm3_23},
2069
2070 /* UIMM10_6_S mask = 0000001111111111. */
2071#define UIMM10_6_S (UIMM3_23 + 1)
2072 {10, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm10_6_s, extract_uimm10_6_s},
2073
2074 /* UIMM6_11_S mask = 0000002200011110. */
2075#define UIMM6_11_S (UIMM10_6_S + 1)
2076 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_11_s, extract_uimm6_11_s},
2077
2078 /* SIMM9_8 mask = 00000000111111112000000000000000. */
2079#define SIMM9_8 (UIMM6_11_S + 1)
2080 {9, 0, BFD_RELOC_ARC_SDA_LDST, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE,
2081 insert_simm9_8, extract_simm9_8},
2082
cc07cda6
CZ		 2083 /* The same as above but used by relaxation. */
2084#define SIMM9_8R (SIMM9_8 + 1)
2085 {9, 0, -SIMM9_8R, ARC_OPERAND_SIGNED | ARC_OPERAND_IGNORE
2086 | ARC_OPERAND_PCREL, insert_simm9_8, extract_simm9_8},
2087
886a2506 2088 /* UIMM10_A32_8_S mask = 0000000011111111. */
cc07cda6 2089#define UIMM10_A32_8_S (SIMM9_8R + 1)
886a2506
NC		 2090 {10, 0, -UIMM10_A32_8_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2091 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm10_a32_8_s,
2092 extract_uimm10_a32_8_s},
2093
2094 /* SIMM9_7_S mask = 0000000111111111. */
2095#define SIMM9_7_S (UIMM10_A32_8_S + 1)
2096 {9, 0, BFD_RELOC_ARC_SDA16_LD, ARC_OPERAND_SIGNED, insert_simm9_7_s,
2097 extract_simm9_7_s},
2098
2099 /* UIMM6_A16_11_S mask = 0000000000011111. */
2100#define UIMM6_A16_11_S (SIMM9_7_S + 1)
2101 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2102 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm6_a16_11_s,
2103 extract_uimm6_a16_11_s},
2104
2105 /* UIMM5_A32_11_S mask = 0000020000011000. */
2106#define UIMM5_A32_11_S (UIMM6_A16_11_S + 1)
2107 {5, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED32
2108 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_IGNORE, insert_uimm5_a32_11_s,
2109 extract_uimm5_a32_11_s},
2110
2111 /* SIMM11_A32_13_S mask = 0000022222200111. */
2112#define SIMM11_A32_13_S (UIMM5_A32_11_S + 1)
2113 {11, 0, BFD_RELOC_ARC_SDA16_ST2, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED32
2114 | ARC_OPERAND_TRUNCATE, insert_simm11_a32_13_s, extract_simm11_a32_13_s},
2115
2116 /* UIMM7_13_S mask = 0000000022220111. */
2117#define UIMM7_13_S (SIMM11_A32_13_S + 1)
2118 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_13_s, extract_uimm7_13_s},
2119
2120 /* UIMM6_A16_21 mask = 00000000000000000000011111000000. */
2121#define UIMM6_A16_21 (UIMM7_13_S + 1)
2122 {6, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2123 | ARC_OPERAND_TRUNCATE, insert_uimm6_a16_21, extract_uimm6_a16_21},
2124
2125 /* UIMM7_11_S mask = 0000022200011110. */
2126#define UIMM7_11_S (UIMM6_A16_21 + 1)
2127 {7, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm7_11_s, extract_uimm7_11_s},
2128
2129 /* UIMM7_A16_20 mask = 00000000000000000000111111000000. */
2130#define UIMM7_A16_20 (UIMM7_11_S + 1)
2131 {7, 0, -UIMM7_A16_20, ARC_OPERAND_UNSIGNED | ARC_OPERAND_ALIGNED16
2132 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_uimm7_a16_20,
2133 extract_uimm7_a16_20},
2134
2135 /* SIMM13_A16_20 mask = 00000000000000000000111111222222. */
2136#define SIMM13_A16_20 (UIMM7_A16_20 + 1)
2137 {13, 0, -SIMM13_A16_20, ARC_OPERAND_SIGNED | ARC_OPERAND_ALIGNED16
2138 | ARC_OPERAND_TRUNCATE | ARC_OPERAND_PCREL, insert_simm13_a16_20,
2139 extract_simm13_a16_20},
2140
2141 /* UIMM8_8_S mask = 0000000011111111. */
2142#define UIMM8_8_S (SIMM13_A16_20 + 1)
2143 {8, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm8_8_s, extract_uimm8_8_s},
2144
cc07cda6
CZ		 2145 /* The same as above but used for relaxation. */
2146#define UIMM8_8R_S (UIMM8_8_S + 1)
2147 {8, 0, -UIMM8_8R_S, ARC_OPERAND_UNSIGNED | ARC_OPERAND_PCREL,
2148 insert_uimm8_8_s, extract_uimm8_8_s},
2149
886a2506 2150 /* W6 mask = 00000000000000000000111111000000. */
cc07cda6 2151#define W6 (UIMM8_8R_S + 1)
886a2506
NC		 2152 {6, 0, 0, ARC_OPERAND_SIGNED, insert_w6, extract_w6},
2153
2154 /* UIMM6_5_S mask = 0000011111100000. */
2155#define UIMM6_5_S (W6 + 1)
2156 {6, 0, 0, ARC_OPERAND_UNSIGNED, insert_uimm6_5_s, extract_uimm6_5_s},
e23e8ebe
AB		 2157
2158 /* ARC NPS400 Support: See comment near head of file. */
2159#define NPS_R_DST_3B (UIMM6_5_S + 1)
c0c31e91
RZ		 2160 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2161 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 2162
2163#define NPS_R_SRC1_3B (NPS_R_DST_3B + 1)
c0c31e91
RZ		 2164 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2165 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
e23e8ebe
AB		 2166
2167#define NPS_R_SRC2_3B (NPS_R_SRC1_3B + 1)
c0c31e91
RZ		 2168 { 3, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2169 insert_nps_3bit_reg_at_21_src2, extract_nps_3bit_reg_at_21_src2 },
e23e8ebe
AB		 2170
2171#define NPS_R_DST (NPS_R_SRC2_3B + 1)
2cce10e7 2172 { 6, 21, 0, ARC_OPERAND_IR, NULL, NULL },
e23e8ebe
AB		 2173
2174#define NPS_R_SRC1 (NPS_R_DST + 1)
2cce10e7 2175 { 6, 21, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
e23e8ebe
AB		 2176
2177#define NPS_BITOP_DST_POS (NPS_R_SRC1 + 1)
2178 { 5, 5, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2179
2180#define NPS_BITOP_SRC_POS (NPS_BITOP_DST_POS + 1)
2181 { 5, 0, 0, ARC_OPERAND_UNSIGNED, 0, 0 },
2182
2183#define NPS_BITOP_SIZE (NPS_BITOP_SRC_POS + 1)
c0c31e91
RZ		 2184 { 5, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2185 insert_nps_bitop_size, extract_nps_bitop_size },
e23e8ebe 2186
820f03ff 2187#define NPS_BITOP_DST_POS_SZ (NPS_BITOP_SIZE + 1)
c0c31e91
RZ		 2188 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2189 insert_nps_dst_pos_and_size, extract_nps_dst_pos_and_size },
820f03ff
AB		 2190
2191#define NPS_BITOP_SIZE_2B (NPS_BITOP_DST_POS_SZ + 1)
c0c31e91
RZ		 2192 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2193 insert_nps_bitop_size_2b, extract_nps_bitop_size_2b },
820f03ff
AB		 2194
2195#define NPS_BITOP_UIMM8 (NPS_BITOP_SIZE_2B + 1)
c0c31e91
RZ		 2196 { 8, 0, 0, ARC_OPERAND_UNSIGNED,
2197 insert_nps_bitop_uimm8, extract_nps_bitop_uimm8 },
820f03ff
AB		 2198
2199#define NPS_UIMM16 (NPS_BITOP_UIMM8 + 1)
e23e8ebe 2200 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
820f03ff 2201
14053c19
GM		 2202#define NPS_SIMM16 (NPS_UIMM16 + 1)
2203 { 16, 0, 0, ARC_OPERAND_SIGNED, NULL, NULL },
2204
2205#define NPS_RFLT_UIMM6 (NPS_SIMM16 + 1)
c0c31e91
RZ		 2206 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2207 insert_nps_rflt_uimm6, extract_nps_rflt_uimm6 },
4b0c052e
AB		 2208
2209#define NPS_XLDST_UIMM16 (NPS_RFLT_UIMM6 + 1)
c0c31e91
RZ		 2210 { 16, 0, BFD_RELOC_ARC_NPS_CMEM16, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2211 insert_nps_cmem_uimm16, extract_nps_cmem_uimm16 },
537aefaf
AB		 2212
2213#define NPS_SRC2_POS (NPS_XLDST_UIMM16 + 1)
c0c31e91
RZ		 2214 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2215 insert_nps_src2_pos, extract_nps_src2_pos },
537aefaf
AB		 2216
2217#define NPS_SRC1_POS (NPS_SRC2_POS + 1)
c0c31e91
RZ		 2218 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2219 insert_nps_src1_pos, extract_nps_src1_pos },
537aefaf
AB		 2220
2221#define NPS_ADDB_SIZE (NPS_SRC1_POS + 1)
c0c31e91
RZ		 2222 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2223 insert_nps_addb_size, extract_nps_addb_size },
537aefaf
AB		 2224
2225#define NPS_ANDB_SIZE (NPS_ADDB_SIZE + 1)
c0c31e91
RZ		 2226 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2227 insert_nps_andb_size, extract_nps_andb_size },
537aefaf
AB		 2228
2229#define NPS_FXORB_SIZE (NPS_ANDB_SIZE + 1)
c0c31e91
RZ		 2230 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2231 insert_nps_fxorb_size, extract_nps_fxorb_size },
537aefaf
AB		 2232
2233#define NPS_WXORB_SIZE (NPS_FXORB_SIZE + 1)
c0c31e91
RZ		 2234 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2235 insert_nps_wxorb_size, extract_nps_wxorb_size },
537aefaf
AB		 2236
2237#define NPS_R_XLDST (NPS_WXORB_SIZE + 1)
2238 { 6, 5, 0, ARC_OPERAND_IR, NULL, NULL },
2239
2240#define NPS_DIV_UIMM4 (NPS_R_XLDST + 1)
2241 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2242
2243#define NPS_QCMP_SIZE (NPS_DIV_UIMM4 + 1)
c0c31e91
RZ		 2244 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2245 insert_nps_qcmp_size, extract_nps_qcmp_size },
537aefaf
AB		 2246
2247#define NPS_QCMP_M1 (NPS_QCMP_SIZE + 1)
2248 { 1, 14, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m1 },
2249
2250#define NPS_QCMP_M2 (NPS_QCMP_M1 + 1)
2251 { 1, 15, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m2 },
2252
2253#define NPS_QCMP_M3 (NPS_QCMP_M2 + 1)
2254 { 4, 5, 0, ARC_OPERAND_UNSIGNED, NULL, extract_nps_qcmp_m3 },
2255
2256#define NPS_CALC_ENTRY_SIZE (NPS_QCMP_M3 + 1)
c0c31e91
RZ		 2257 { 0, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2258 insert_nps_calc_entry_size, extract_nps_calc_entry_size },
4eb6f892
AB		 2259
2260#define NPS_R_DST_3B_SHORT (NPS_CALC_ENTRY_SIZE + 1)
c0c31e91
RZ		 2261 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2262 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 2263
2264#define NPS_R_SRC1_3B_SHORT (NPS_R_DST_3B_SHORT + 1)
c0c31e91
RZ		 2265 { 3, 8, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2266 insert_nps_3bit_reg_at_8_dst, extract_nps_3bit_reg_at_8_dst },
4eb6f892
AB		 2267
2268#define NPS_R_SRC2_3B_SHORT (NPS_R_SRC1_3B_SHORT + 1)
c0c31e91
RZ		 2269 { 3, 5, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2270 insert_nps_3bit_reg_at_5_src2, extract_nps_3bit_reg_at_5_src2 },
4eb6f892
AB		 2271
2272#define NPS_BITOP_SIZE2 (NPS_R_SRC2_3B_SHORT + 1)
c0c31e91
RZ		 2273 { 5, 25, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2274 insert_nps_bitop2_size, extract_nps_bitop2_size },
4eb6f892
AB		 2275
2276#define NPS_BITOP_SIZE1 (NPS_BITOP_SIZE2 + 1)
c0c31e91
RZ		 2277 { 5, 20, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2278 insert_nps_bitop1_size, extract_nps_bitop1_size },
4eb6f892
AB		 2279
2280#define NPS_BITOP_DST_POS3_POS4 (NPS_BITOP_SIZE1 + 1)
c0c31e91
RZ		 2281 { 5, 0, 0, ARC_OPERAND_UNSIGNED,
2282 insert_nps_bitop_dst_pos3_pos4, extract_nps_bitop_dst_pos3_pos4 },
4eb6f892
AB		 2283
2284#define NPS_BITOP_DST_POS4 (NPS_BITOP_DST_POS3_POS4 + 1)
bdfe53e3 2285 { 5, 42, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2286
2287#define NPS_BITOP_DST_POS3 (NPS_BITOP_DST_POS4 + 1)
bdfe53e3 2288 { 5, 37, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2289
2290#define NPS_BITOP_DST_POS2 (NPS_BITOP_DST_POS3 + 1)
2291 { 5, 15, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2292
2293#define NPS_BITOP_DST_POS1 (NPS_BITOP_DST_POS2 + 1)
2294 { 5, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2295
2296#define NPS_BITOP_SRC_POS4 (NPS_BITOP_DST_POS1 + 1)
bdfe53e3 2297 { 5, 32, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
4eb6f892
AB		 2298
2299#define NPS_BITOP_SRC_POS3 (NPS_BITOP_SRC_POS4 + 1)
2300 { 5, 20, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2301
2302#define NPS_BITOP_SRC_POS2 (NPS_BITOP_SRC_POS3 + 1)
2303 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2304
2305#define NPS_BITOP_SRC_POS1 (NPS_BITOP_SRC_POS2 + 1)
2306 { 5, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2307
bdfe53e3 2308#define NPS_BITOP_MOD4 (NPS_BITOP_SRC_POS1 + 1)
c0c31e91
RZ		 2309 { 2, 0, 0, ARC_OPERAND_UNSIGNED,
2310 insert_nps_bitop_mod4, extract_nps_bitop_mod4 },
4eb6f892 2311
bdfe53e3 2312#define NPS_BITOP_MOD3 (NPS_BITOP_MOD4 + 1)
4eb6f892
AB		 2313 { 2, 29, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2314
2315#define NPS_BITOP_MOD2 (NPS_BITOP_MOD3 + 1)
2316 { 2, 27, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2317
2318#define NPS_BITOP_MOD1 (NPS_BITOP_MOD2 + 1)
2319 { 2, 25, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2320
2321#define NPS_BITOP_INS_EXT (NPS_BITOP_MOD1 + 1)
c0c31e91
RZ		 2322 { 5, 20, 0, ARC_OPERAND_UNSIGNED,
2323 insert_nps_bitop_ins_ext, extract_nps_bitop_ins_ext },
14053c19
GM		 2324
2325#define NPS_FIELD_START_POS (NPS_BITOP_INS_EXT + 1)
2326 { 3, 3, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2327
2328#define NPS_FIELD_SIZE (NPS_FIELD_START_POS + 1)
c0c31e91
RZ		 2329 { 3, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2330 insert_nps_field_size, extract_nps_field_size },
14053c19
GM		 2331
2332#define NPS_SHIFT_FACTOR (NPS_FIELD_SIZE + 1)
c0c31e91
RZ		 2333 { 3, 9, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2334 insert_nps_shift_factor, extract_nps_shift_factor },
14053c19
GM		 2335
2336#define NPS_BITS_TO_SCRAMBLE (NPS_SHIFT_FACTOR + 1)
c0c31e91
RZ		 2337 { 3, 12, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2338 insert_nps_bits_to_scramble, extract_nps_bits_to_scramble },
14053c19
GM		 2339
2340#define NPS_SRC2_POS_5B (NPS_BITS_TO_SCRAMBLE + 1)
2341 { 5, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2342
2343#define NPS_BDLEN_MAX_LEN (NPS_SRC2_POS_5B + 1)
c0c31e91
RZ		 2344 { 8, 5, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2345 insert_nps_bdlen_max_len, extract_nps_bdlen_max_len },
14053c19
GM		 2346
2347#define NPS_MIN_HOFS (NPS_BDLEN_MAX_LEN + 1)
c0c31e91
RZ		 2348 { 4, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2349 insert_nps_min_hofs, extract_nps_min_hofs },
14053c19
GM		 2350
2351#define NPS_PSBC (NPS_MIN_HOFS + 1)
2352 { 1, 11, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
9ba75c88
GM		 2353
2354#define NPS_DPI_DST (NPS_PSBC + 1)
2355 { 5, 11, 0, ARC_OPERAND_IR, NULL, NULL },
2356
c0c31e91
RZ		 2357 /* NPS_DPI_SRC1_3B is similar to NPS_R_SRC1_3B
2358 but doesn't duplicate an operand. */
9ba75c88 2359#define NPS_DPI_SRC1_3B (NPS_DPI_DST + 1)
c0c31e91
RZ		 2360 { 3, 24, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2361 insert_nps_3bit_reg_at_24_dst, extract_nps_3bit_reg_at_24_dst },
9ba75c88
GM		 2362
2363#define NPS_HASH_WIDTH (NPS_DPI_SRC1_3B + 1)
c0c31e91
RZ		 2364 { 5, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2365 insert_nps_hash_width, extract_nps_hash_width },
9ba75c88
GM		 2366
2367#define NPS_HASH_PERM (NPS_HASH_WIDTH + 1)
2368 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2369
2370#define NPS_HASH_NONLINEAR (NPS_HASH_PERM + 1)
2371 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2372
2373#define NPS_HASH_BASEMAT (NPS_HASH_NONLINEAR + 1)
2374 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2375
2376#define NPS_HASH_LEN (NPS_HASH_BASEMAT + 1)
c0c31e91
RZ		 2377 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2378 insert_nps_hash_len, extract_nps_hash_len },
9ba75c88
GM		 2379
2380#define NPS_HASH_OFS (NPS_HASH_LEN + 1)
2381 { 2, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2382
2383#define NPS_HASH_BASEMAT2 (NPS_HASH_OFS + 1)
2384 { 1, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2385
2386#define NPS_E4BY_INDEX0 (NPS_HASH_BASEMAT2 + 1)
2387 { 3, 8, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2388
2389#define NPS_E4BY_INDEX1 (NPS_E4BY_INDEX0 + 1)
2390 { 3, 5, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2391
2392#define NPS_E4BY_INDEX2 (NPS_E4BY_INDEX1 + 1)
2393 { 3, 2, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2394
2395#define NPS_E4BY_INDEX3 (NPS_E4BY_INDEX2 + 1)
c0c31e91
RZ		 2396 { 2, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2397 insert_nps_index3, extract_nps_index3 },
db18dbab
GM		 2398
2399#define COLON (NPS_E4BY_INDEX3 + 1)
2400 { 0, 0, 0, ARC_OPERAND_COLON | ARC_OPERAND_FAKE, NULL, NULL },
2401
2402#define NPS_BD (COLON + 1)
c0c31e91
RZ		 2403 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2404 insert_nps_bd, extract_nps_bd },
db18dbab
GM		 2405
2406#define NPS_JID (NPS_BD + 1)
c0c31e91
RZ		 2407 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2408 insert_nps_jid, extract_nps_jid },
db18dbab
GM		 2409
2410#define NPS_LBD (NPS_JID + 1)
c0c31e91
RZ		 2411 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2412 insert_nps_lbd, extract_nps_lbd },
db18dbab
GM		 2413
2414#define NPS_MBD (NPS_LBD + 1)
c0c31e91
RZ		 2415 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2416 insert_nps_mbd, extract_nps_mbd },
db18dbab
GM		 2417
2418#define NPS_SD (NPS_MBD + 1)
c0c31e91
RZ		 2419 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2420 insert_nps_sd, extract_nps_sd },
db18dbab
GM		 2421
2422#define NPS_SM (NPS_SD + 1)
c0c31e91
RZ		 2423 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2424 insert_nps_sm, extract_nps_sm },
db18dbab
GM		 2425
2426#define NPS_XA (NPS_SM + 1)
c0c31e91
RZ		 2427 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2428 insert_nps_xa, extract_nps_xa },
db18dbab
GM		 2429
2430#define NPS_XD (NPS_XA + 1)
c0c31e91
RZ		 2431 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2432 insert_nps_xd, extract_nps_xd },
db18dbab
GM		 2433
2434#define NPS_CD (NPS_XD + 1)
c0c31e91
RZ		 2435 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2436 insert_nps_cd, extract_nps_cd },
db18dbab
GM		 2437
2438#define NPS_CBD (NPS_CD + 1)
c0c31e91
RZ		 2439 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2440 insert_nps_cbd, extract_nps_cbd },
db18dbab
GM		 2441
2442#define NPS_CJID (NPS_CBD + 1)
c0c31e91
RZ		 2443 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2444 insert_nps_cjid, extract_nps_cjid },
db18dbab
GM		 2445
2446#define NPS_CLBD (NPS_CJID + 1)
c0c31e91
RZ		 2447 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2448 insert_nps_clbd, extract_nps_clbd },
db18dbab
GM		 2449
2450#define NPS_CM (NPS_CLBD + 1)
c0c31e91
RZ		 2451 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2452 insert_nps_cm, extract_nps_cm },
db18dbab
GM		 2453
2454#define NPS_CSD (NPS_CM + 1)
c0c31e91
RZ		 2455 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2456 insert_nps_csd, extract_nps_csd },
db18dbab
GM		 2457
2458#define NPS_CXA (NPS_CSD + 1)
c0c31e91
RZ		 2459 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2460 insert_nps_cxa, extract_nps_cxa },
db18dbab
GM		 2461
2462#define NPS_CXD (NPS_CXA + 1)
c0c31e91
RZ		 2463 { 0, 0, 0, ARC_OPERAND_ADDRTYPE | ARC_OPERAND_NCHK,
2464 insert_nps_cxd, extract_nps_cxd },
db18dbab
GM		 2465
2466#define NPS_BD_TYPE (NPS_CXD + 1)
2467 { 1, 10, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2468
2469#define NPS_BMU_NUM (NPS_BD_TYPE + 1)
c0c31e91
RZ		 2470 { 3, 0, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2471 insert_nps_bd_num_buff, extract_nps_bd_num_buff },
db18dbab
GM		 2472
2473#define NPS_PMU_NXT_DST (NPS_BMU_NUM + 1)
2474 { 4, 6, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2475
c0c31e91
RZ		 2476#define NPS_WHASH_SIZE (NPS_PMU_NXT_DST + 1)
2477 { 6, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2478 insert_nps_size_16bit, extract_nps_size_16bit },
2479
2480#define NPS_PMU_NUM_JOB (NPS_WHASH_SIZE + 1)
2481 { 2, 6, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2482 insert_nps_pmu_num_job, extract_nps_pmu_num_job },
bdfe53e3 2483
645d3342 2484#define NPS_DMA_IMM_ENTRY (NPS_PMU_NUM_JOB + 1)
c0c31e91
RZ		 2485 { 3, 2, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2486 insert_nps_imm_entry, extract_nps_imm_entry },
645d3342
RZ		 2487
2488#define NPS_DMA_IMM_OFFSET (NPS_DMA_IMM_ENTRY + 1)
c0c31e91
RZ		 2489 { 4, 10, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2490 insert_nps_imm_offset, extract_nps_imm_offset },
2491
2492#define NPS_MISC_IMM_SIZE (NPS_DMA_IMM_OFFSET + 1)
2493 { 7, 0, 0, ARC_OPERAND_UNSIGNED , NULL, NULL },
2494
2495#define NPS_MISC_IMM_OFFSET (NPS_MISC_IMM_SIZE + 1)
2496 { 5, 8, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2497 insert_nps_misc_imm_offset, extract_nps_misc_imm_offset },
645d3342 2498
c0c31e91
RZ		 2499#define NPS_R_DST_3B_48 (NPS_MISC_IMM_OFFSET + 1)
2500 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2501 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
bdfe53e3
AB		 2502
2503#define NPS_R_SRC1_3B_48 (NPS_R_DST_3B_48 + 1)
c0c31e91
RZ		 2504 { 3, 40, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2505 insert_nps_3bit_reg_at_40_dst, extract_nps_3bit_reg_at_40_dst },
bdfe53e3
AB		 2506
2507#define NPS_R_SRC2_3B_48 (NPS_R_SRC1_3B_48 + 1)
c0c31e91
RZ		 2508 { 3, 37, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2509 insert_nps_3bit_reg_at_37_src2, extract_nps_3bit_reg_at_37_src2 },
bdfe53e3
AB		 2510
2511#define NPS_R_DST_3B_64 (NPS_R_SRC2_3B_48 + 1)
c0c31e91
RZ		 2512 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2513 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
bdfe53e3
AB		 2514
2515#define NPS_R_SRC1_3B_64 (NPS_R_DST_3B_64 + 1)
c0c31e91
RZ		 2516 { 3, 56, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE | ARC_OPERAND_NCHK,
2517 insert_nps_3bit_reg_at_56_dst, extract_nps_3bit_reg_at_56_dst },
bdfe53e3
AB		 2518
2519#define NPS_R_SRC2_3B_64 (NPS_R_SRC1_3B_64 + 1)
c0c31e91
RZ		 2520 { 3, 53, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2521 insert_nps_3bit_reg_at_53_src2, extract_nps_3bit_reg_at_53_src2 },
0d2bcfaf 2522
5a736821
GM		 2523#define NPS_RA_64 (NPS_R_SRC2_3B_64 + 1)
2524 { 6, 53, 0, ARC_OPERAND_IR, NULL, NULL },
2525
2526#define NPS_RB_64 (NPS_RA_64 + 1)
2527 { 5, 48, 0, ARC_OPERAND_IR, NULL, NULL },
2528
2529#define NPS_RBdup_64 (NPS_RB_64 + 1)
2530 { 5, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, NULL, NULL },
2531
2532#define NPS_RBdouble_64 (NPS_RBdup_64 + 1)
c0c31e91
RZ		 2533 { 10, 43, 0, ARC_OPERAND_IR | ARC_OPERAND_NCHK,
2534 insert_nps_rbdouble_64, extract_nps_rbdouble_64 },
5a736821
GM		 2535
2536#define NPS_RC_64 (NPS_RBdouble_64 + 1)
2537 { 5, 43, 0, ARC_OPERAND_IR, NULL, NULL },
2538
2539#define NPS_UIMM16_0_64 (NPS_RC_64 + 1)
2540 { 16, 0, 0, ARC_OPERAND_UNSIGNED, NULL, NULL },
2541
2542#define NPS_PROTO_SIZE (NPS_UIMM16_0_64 + 1)
c0c31e91
RZ		 2543 { 6, 16, 0, ARC_OPERAND_UNSIGNED | ARC_OPERAND_NCHK,
2544 insert_nps_proto_size, extract_nps_proto_size }
5a736821 2545};
886a2506 2546const unsigned arc_num_operands = ARRAY_SIZE (arc_operands);
0d2bcfaf 2547
886a2506
NC		 2548const unsigned arc_Toperand = FKT_T;
2549const unsigned arc_NToperand = FKT_NT;
47b0e7ad 2550
b99747ae
CZ		 2551const unsigned char arg_none[] = { 0 };
2552const unsigned char arg_32bit_rarbrc[] = { RA, RB, RC };
2553const unsigned char arg_32bit_zarbrc[] = { ZA, RB, RC };
2554const unsigned char arg_32bit_rbrbrc[] = { RB, RBdup, RC };
2555const unsigned char arg_32bit_rarbu6[] = { RA, RB, UIMM6_20 };
2556const unsigned char arg_32bit_zarbu6[] = { ZA, RB, UIMM6_20 };
2557const unsigned char arg_32bit_rbrbu6[] = { RB, RBdup, UIMM6_20 };
2558const unsigned char arg_32bit_rbrbs12[] = { RB, RBdup, SIMM12_20 };
2559const unsigned char arg_32bit_ralimmrc[] = { RA, LIMM, RC };
2560const unsigned char arg_32bit_rarblimm[] = { RA, RB, LIMM };
2561const unsigned char arg_32bit_zalimmrc[] = { ZA, LIMM, RC };
2562const unsigned char arg_32bit_zarblimm[] = { ZA, RB, LIMM };
2563
2564const unsigned char arg_32bit_rbrblimm[] = { RB, RBdup, LIMM };
2565const unsigned char arg_32bit_ralimmu6[] = { RA, LIMM, UIMM6_20 };
2566const unsigned char arg_32bit_zalimmu6[] = { ZA, LIMM, UIMM6_20 };
2567
2568const unsigned char arg_32bit_zalimms12[] = { ZA, LIMM, SIMM12_20 };
2569const unsigned char arg_32bit_ralimmlimm[] = { RA, LIMM, LIMMdup };
2570const unsigned char arg_32bit_zalimmlimm[] = { ZA, LIMM, LIMMdup };
2571
2572const unsigned char arg_32bit_rbrc[] = { RB, RC };
2573const unsigned char arg_32bit_zarc[] = { ZA, RC };
2574const unsigned char arg_32bit_rbu6[] = { RB, UIMM6_20 };
2575const unsigned char arg_32bit_zau6[] = { ZA, UIMM6_20 };
2576const unsigned char arg_32bit_rblimm[] = { RB, LIMM };
2577const unsigned char arg_32bit_zalimm[] = { ZA, LIMM };
2578
2579const unsigned char arg_32bit_limmrc[] = { LIMM, RC };
2580const unsigned char arg_32bit_limmu6[] = { LIMM, UIMM6_20 };
2581const unsigned char arg_32bit_limms12[] = { LIMM, SIMM12_20 };
2582const unsigned char arg_32bit_limmlimm[] = { LIMM, LIMMdup };
2583
945e0f82
CZ		 2584const unsigned char arg_32bit_rc[] = { RC };
2585const unsigned char arg_32bit_u6[] = { UIMM6_20 };
2586const unsigned char arg_32bit_limm[] = { LIMM };
2587
886a2506 2588/* The opcode table.
0d2bcfaf 2589
886a2506 2590 The format of the opcode table is:
0d2bcfaf 2591
1328504b
AB		 2592 NAME OPCODE MASK CPU CLASS SUBCLASS { OPERANDS } { FLAGS }.
2593
2594 The table is organised such that, where possible, all instructions with
2595 the same mnemonic are together in a block. When the assembler searches
2596 for a suitable instruction the entries are checked in table order, so
2597 more specific, or specialised cases should appear earlier in the table.
2598
2599 As an example, consider two instructions 'add a,b,u6' and 'add
2600 a,b,limm'. The first takes a 6-bit immediate that is encoded within the
2601 32-bit instruction, while the second takes a 32-bit immediate that is
2602 encoded in a follow-on 32-bit, making the total instruction length
2603 64-bits. In this case the u6 variant must appear first in the table, as
2604 all u6 immediates could also be encoded using the 'limm' extension,
2605 however, we want to use the shorter instruction wherever possible.
2606
2607 It is possible though to split instructions with the same mnemonic into
2608 multiple groups. However, the instructions are still checked in table
2609 order, even across groups. The only time that instructions with the
2610 same mnemonic should be split into different groups is when different
2611 variants of the instruction appear in different architectures, in which
2612 case, grouping all instructions from a particular architecture together
2613 might be preferable to merging the instruction into the main instruction
2614 table.
2615
2616 An example of this split instruction groups can be found with the 'sync'
2617 instruction. The core arc architecture provides a 'sync' instruction,
2618 while the nps instruction set extension provides 'sync.rd' and
2619 'sync.wr'. The rd/wr flags are instruction flags, not part of the
2620 mnemonic, so we end up with two groups for the sync instruction, the
2621 first within the core arc instruction table, and the second within the
2622 nps extension instructions. */
886a2506 2623const struct arc_opcode arc_opcodes[] =
0d2bcfaf 2624{
886a2506 2625#include "arc-tbl.h"
e23e8ebe 2626#include "arc-nps400-tbl.h"
f2dd8838 2627#include "arc-ext-tbl.h"
0d2bcfaf 2628
b99747ae
CZ		 2629 { NULL, 0, 0, 0, 0, 0, { 0 }, { 0 } }
2630};
252b5132 2631
886a2506
NC		 2632/* List with special cases instructions and the applicable flags. */
2633const struct arc_flag_special arc_flag_special_cases[] =
252b5132 2634{
886a2506
NC		 2635 { "b", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2636 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2637 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
c0c31e91
RZ		 2638 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NJ, F_NM,
2639 F_NO_T, F_NULL } },
886a2506
NC		 2640 { "bl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2641 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2642 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2643 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2644 { "br", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2645 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2646 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2647 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2648 { "j", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2649 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2650 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2651 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2652 { "jl", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2653 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2654 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2655 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2656 { "lp", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2657 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2658 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2659 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2660 { "set", { F_ALWAYS, F_RA, F_EQUAL, F_ZERO, F_NOTEQUAL, F_NOTZERO, F_POZITIVE,
2661 F_PL, F_NEGATIVE, F_MINUS, F_CARRY, F_CARRYSET, F_LOWER, F_CARRYCLR,
2662 F_NOTCARRY, F_HIGHER, F_OVERFLOWSET, F_OVERFLOW, F_NOTOVERFLOW,
2663 F_OVERFLOWCLR, F_GT, F_GE, F_LT, F_LE, F_HI, F_LS, F_PNZ, F_NULL } },
2664 { "ld", { F_SIZEB17, F_SIZEW17, F_H17, F_NULL } },
2665 { "st", { F_SIZEB1, F_SIZEW1, F_H1, F_NULL } }
2666};
252b5132 2667
886a2506 2668const unsigned arc_num_flag_special = ARRAY_SIZE (arc_flag_special_cases);
252b5132 2669
886a2506 2670/* Relocations. */
886a2506
NC		 2671const struct arc_reloc_equiv_tab arc_reloc_equiv[] =
2672{
24b368f8
CZ		 2673 { "sda", "ld", { F_ASFAKE, F_H1, F_NULL },
2674 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2675 { "sda", "st", { F_ASFAKE, F_H1, F_NULL },
2676 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2677 { "sda", "ld", { F_ASFAKE, F_SIZEW7, F_NULL },
2678 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2679 { "sda", "st", { F_ASFAKE, F_SIZEW7, F_NULL },
2680 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST1 },
2681
2682 /* Next two entries will cover the undefined behavior ldb/stb with
2683 address scaling. */
2684 { "sda", "ld", { F_ASFAKE, F_SIZEB7, F_NULL },
2685 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2686 { "sda", "st", { F_ASFAKE, F_SIZEB7, F_NULL },
2687 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST},
2688
2689 { "sda", "ld", { F_ASFAKE, F_NULL },
2690 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2691 { "sda", "st", { F_ASFAKE, F_NULL },
2692 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
2693 { "sda", "ldd", { F_ASFAKE, F_NULL },
2694 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2 },
2695 { "sda", "std", { F_ASFAKE, F_NULL },
2696 BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST2},
886a2506
NC		 2697
2698 /* Short instructions. */
24b368f8
CZ		 2699 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD, BFD_RELOC_ARC_SDA16_LD },
2700 { "sda", 0, { F_NULL }, -SIMM10_A16_7_Sbis, BFD_RELOC_ARC_SDA16_LD1 },
2701 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_LD2, BFD_RELOC_ARC_SDA16_LD2 },
2702 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA16_ST2, BFD_RELOC_ARC_SDA16_ST2 },
2703
2704 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_SDA32_ME },
2705 { "sda", 0, { F_NULL }, BFD_RELOC_ARC_SDA_LDST, BFD_RELOC_ARC_SDA_LDST },
2706
2707 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25H_PCREL,
2708 BFD_RELOC_ARC_S25H_PCREL_PLT },
2709 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21H_PCREL,
2710 BFD_RELOC_ARC_S21H_PCREL_PLT },
2711 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S25W_PCREL,
2712 BFD_RELOC_ARC_S25W_PCREL_PLT },
2713 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_S21W_PCREL,
2714 BFD_RELOC_ARC_S21W_PCREL_PLT },
2715
2716 { "plt", 0, { F_NULL }, BFD_RELOC_ARC_32_ME, BFD_RELOC_ARC_PLT32 }
886a2506 2717};
252b5132 2718
886a2506 2719const unsigned arc_num_equiv_tab = ARRAY_SIZE (arc_reloc_equiv);
252b5132 2720
886a2506 2721const struct arc_pseudo_insn arc_pseudo_insns[] =
0d2bcfaf 2722{
886a2506
NC		 2723 { "push", "st", ".aw", 5, { { RC, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2724 { RB, 1, 28, 2 }, { SIMM9_8, 1, -4, 3 },
2725 { BRAKETdup, 1, 0, 4} } },
2726 { "pop", "ld", ".ab", 5, { { RA, 0, 0, 0 }, { BRAKET, 1, 0, 1 },
2727 { RB, 1, 28, 2 }, { SIMM9_8, 1, 4, 3 },
2728 { BRAKETdup, 1, 0, 4} } },
2729
2730 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2731 { SIMM9_A16_8, 0, 0, 2 } } },
2732 { "brgt", "brge", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2733 { SIMM9_A16_8, 0, 0, 2 } } },
2734 { "brgt", "brlt", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2735 { SIMM9_A16_8, 0, 0, 2 } } },
2736 { "brgt", "brlt", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2737 { SIMM9_A16_8, 0, 0, 2 } } },
2738 { "brgt", "brge", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2739 { SIMM9_A16_8, 0, 0, 2 } } },
2740
2741 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2742 { SIMM9_A16_8, 0, 0, 2 } } },
2743 { "brhi", "brhs", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2744 { SIMM9_A16_8, 0, 0, 2 } } },
2745 { "brhi", "brlo", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2746 { SIMM9_A16_8, 0, 0, 2 } } },
2747 { "brhi", "brlo", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2748 { SIMM9_A16_8, 0, 0, 2 } } },
2749 { "brhi", "brhs", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2750 { SIMM9_A16_8, 0, 0, 2 } } },
2751
2752 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2753 { SIMM9_A16_8, 0, 0, 2 } } },
2754 { "brle", "brlt", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2755 { SIMM9_A16_8, 0, 0, 2 } } },
2756 { "brle", "brge", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2757 { SIMM9_A16_8, 0, 0, 2 } } },
2758 { "brle", "brge", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2759 { SIMM9_A16_8, 0, 0, 2 } } },
2760 { "brle", "brlt", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2761 { SIMM9_A16_8, 0, 0, 2 } } },
2762
2763 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { RC, 0, 0, 0 },
2764 { SIMM9_A16_8, 0, 0, 2 } } },
2765 { "brls", "brlo", NULL, 3, { { RB, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2766 { SIMM9_A16_8, 0, 0, 2 } } },
2767 { "brls", "brhs", NULL, 3, { { RB, 0, 0, 1 }, { LIMM, 0, 0, 0 },
2768 { SIMM9_A16_8, 0, 0, 2 } } },
2769 { "brls", "brhs", NULL, 3, { { LIMM, 0, 0, 1 }, { RC, 0, 0, 0 },
2770 { SIMM9_A16_8, 0, 0, 2 } } },
2771 { "brls", "brlo", NULL, 3, { { LIMM, 0, 0, 0 }, { UIMM6_8, 0, 1, 1 },
2772 { SIMM9_A16_8, 0, 0, 2 } } },
2773};
0d2bcfaf 2774
886a2506
NC		 2775const unsigned arc_num_pseudo_insn =
2776 sizeof (arc_pseudo_insns) / sizeof (*arc_pseudo_insns);
0d2bcfaf 2777
886a2506 2778const struct arc_aux_reg arc_aux_regs[] =
0d2bcfaf 2779{
886a2506 2780#undef DEF
f36e33da
CZ		 2781#define DEF(ADDR, CPU, SUBCLASS, NAME) \
2782 { ADDR, CPU, SUBCLASS, #NAME, sizeof (#NAME)-1 },
0d2bcfaf 2783
886a2506 2784#include "arc-regs.h"
0d2bcfaf 2785
886a2506
NC		 2786#undef DEF
2787};
0d2bcfaf 2788
886a2506 2789const unsigned arc_num_aux_regs = ARRAY_SIZE (arc_aux_regs);
4670103e
CZ		 2790
2791/* NOTE: The order of this array MUST be consistent with 'enum
2792 arc_rlx_types' located in tc-arc.h! */
2793const struct arc_opcode arc_relax_opcodes[] =
2794{
2795 { NULL, 0x0, 0x0, 0x0, ARITH, NONE, { UNUSED }, { 0 } },
2796
2797 /* bl_s s13 11111sssssssssss. */
2798 { "bl_s", 0x0000F800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2799 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2800 { SIMM13_A32_5_S }, { 0 }},
2801
2802 /* bl<.d> s25 00001sssssssss10SSSSSSSSSSNRtttt. */
2803 { "bl", 0x08020000, 0xF8030000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2804 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2805 { SIMM25_A32_5 }, { C_D }},
2806
2807 /* b_s s10 1111000sssssssss. */
2808 { "b_s", 0x0000F000, 0x0000FE00, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2809 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2810 { SIMM10_A16_7_S }, { 0 }},
2811
2812 /* b<.d> s25 00000ssssssssss1SSSSSSSSSSNRtttt. */
2813 { "b", 0x00010000, 0xF8010000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2814 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, BRANCH, NONE,
2815 { SIMM25_A16_5 }, { C_D }},
2816
cc07cda6 2817 /* add_s c,b,u3 01101bbbccc00uuu. */
4670103e
CZ		 2818 { "add_s", 0x00006800, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2819 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2820 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
4670103e 2821
cc07cda6 2822 /* add<.f> a,b,u6 00100bbb01000000FBBBuuuuuuAAAAAA. */
4670103e
CZ		 2823 { "add", 0x20400000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2824 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2825 { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2826
2827 /* add<.f> a,b,limm 00100bbb00000000FBBB111110AAAAAA. */
2828 { "add", 0x20000F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2829 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2830 { RA, RB, LIMM }, { C_F }},
2831
cc07cda6 2832 /* ld_s c,b,u7 10000bbbcccuuuuu. */
4670103e
CZ		 2833 { "ld_s", 0x00008000, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2834 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2835 { RC_S, BRAKET, RB_S, UIMM7_A32_11R_S, BRAKETdup }, { 0 }},
4670103e
CZ		 2836
2837 /* ld<.di><.aa><.x><zz> a,b,s9
cc07cda6 2838 00010bbbssssssssSBBBDaaZZXAAAAAA. */
4670103e
CZ		 2839 { "ld", 0x10000000, 0xF8000000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2840 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2841 { RA, BRAKET, RB, SIMM9_8R, BRAKETdup },
4670103e
CZ		 2842 { C_ZZ23, C_DI20, C_AA21, C_X25 }},
2843
2844 /* ld<.di><.aa><.x><zz> a,b,limm 00100bbbaa110ZZXDBBB111110AAAAAA. */
2845 { "ld", 0x20300F80, 0xF8380FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2846 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2847 { RA, BRAKET, RB, LIMM, BRAKETdup },
2848 { C_ZZ13, C_DI16, C_AA8, C_X15 }},
2849
cc07cda6 2850 /* mov_s b,u8 11011bbbuuuuuuuu. */
4670103e
CZ		 2851 { "mov_s", 0x0000D800, 0x0000F800, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2852 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2853 { RB_S, UIMM8_8R_S }, { 0 }},
4670103e 2854
cc07cda6 2855 /* mov<.f> b,s12 00100bbb10001010FBBBssssssSSSSSS. */
4670103e
CZ		 2856 { "mov", 0x208A0000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2857 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2858 { RB, SIMM12_20R }, { C_F }},
4670103e
CZ		 2859
2860 /* mov<.f> b,limm 00100bbb00001010FBBB111110RRRRRR. */
2861 { "mov", 0x200A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2862 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2863 { RB, LIMM }, { C_F }},
2864
cc07cda6 2865 /* sub_s c,b,u3 01101bbbccc01uuu. */
4670103e
CZ		 2866 { "sub_s", 0x00006808, 0x0000F818, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2867 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2868 { RC_S, RB_S, UIMM3_13R_S }, { 0 }},
4670103e 2869
cc07cda6 2870 /* sub<.f> a,b,u6 00100bbb01000010FBBBuuuuuuAAAAAA. */
4670103e
CZ		 2871 { "sub", 0x20420000, 0xF8FF0000, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2872 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2873 { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2874
2875 /* sub<.f> a,b,limm 00100bbb00000010FBBB111110AAAAAA. */
2876 { "sub", 0x20020F80, 0xF8FF0FC0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2877 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2878 { RA, RB, LIMM }, { C_F }},
2879
cc07cda6 2880 /* mpy<.f> a,b,u6 00100bbb01011010FBBBuuuuuuAAAAAA. */
4670103e 2881 { "mpy", 0x205A0000, 0xF8FF0000, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
cc07cda6 2882 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, UIMM6_20R }, { C_F }},
4670103e
CZ		 2883
2884 /* mpy<.f> a,b,limm 00100bbb00011010FBBB111110AAAAAA. */
2885 { "mpy", 0x201A0F80, 0xF8FF0FC0, ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM
2886 | ARC_OPCODE_ARCv2HS, ARITH, MPY6E, { RA, RB, LIMM }, { C_F }},
2887
cc07cda6 2888 /* mov<.f><.cc> b,u6 00100bbb11001010FBBBuuuuuu1QQQQQ. */
4670103e
CZ		 2889 { "mov", 0x20CA0020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2890 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
cc07cda6 2891 { RB, UIMM6_20R }, { C_F, C_CC }},
4670103e
CZ		 2892
2893 /* mov<.f><.cc> b,limm 00100bbb11001010FBBB1111100QQQQQ. */
2894 { "mov", 0x20CA0F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2895 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, MEMORY, NONE,
2896 { RB, LIMM }, { C_F, C_CC }},
2897
cc07cda6 2898 /* add<.f><.cc> b,b,u6 00100bbb11000000FBBBuuuuuu1QQQQQ. */
4670103e
CZ		 2899 { "add", 0x20C00020, 0xF8FF0020, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2900 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
cc07cda6 2901 { RB, RBdup, UIMM6_20R }, { C_F, C_CC }},
4670103e
CZ		 2902
2903 /* add<.f><.cc> b,b,limm 00100bbb11000000FBBB1111100QQQQQ. */
2904 { "add", 0x20C00F80, 0xF8FF0FE0, ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700
2905 | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS, ARITH, NONE,
2906 { RB, RBdup, LIMM }, { C_F, C_CC }}
2907};
2908
2909const unsigned arc_num_relax_opcodes = ARRAY_SIZE (arc_relax_opcodes);
4eb6f892 2910
bdfe53e3 2911/* Return length of an opcode in bytes. */
06fe285f
GM		 2912
2913int
2914arc_opcode_len (const struct arc_opcode *opcode)
2915{
2916 if (opcode->mask < 0x10000ull)
2917 return 2;
bdfe53e3
AB		 2918
2919 if (opcode->mask < 0x100000000ull)
2920 return 4;
2921
2922 if (opcode->mask < 0x1000000000000ull)
2923 return 6;
2924
2925 return 8;
06fe285f 2926}
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