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b8891f8d | 1 | /* Declarations for C-SKY opcode table |
b3adc24a | 2 | Copyright (C) 2007-2020 Free Software Foundation, Inc. |
b8891f8d AJ |
3 | Contributed by C-SKY Microsystems and Mentor Graphics. |
4 | ||
5 | This file is part of the GNU opcodes library. | |
6 | ||
7 | This library is free software; you can redistribute it and/or modify | |
8 | it under the terms of the GNU General Public License as published by | |
9 | the Free Software Foundation; either version 3, or (at your option) | |
10 | any later version. | |
11 | ||
12 | It is distributed in the hope that it will be useful, but WITHOUT | |
13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
15 | License for more details. | |
16 | ||
17 | You should have received a copy of the GNU General Public License | |
18 | along with GAS; see the file COPYING. If not, write to the Free | |
19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
20 | 02110-1301, USA. */ | |
21 | ||
22 | #include "opcode/csky.h" | |
23 | ||
24 | #define OP_TABLE_NUM 2 | |
0c0577f6 | 25 | #define MAX_OPRND_NUM 5 |
b8891f8d AJ |
26 | |
27 | enum operand_type | |
28 | { | |
29 | OPRND_TYPE_NONE = 0, | |
30 | /* Control register. */ | |
31 | OPRND_TYPE_CTRLREG, | |
32 | /* r0 - r7. */ | |
33 | OPRND_TYPE_GREG0_7, | |
34 | /* r0 - r15. */ | |
35 | OPRND_TYPE_GREG0_15, | |
36 | /* r16 - r31. */ | |
37 | OPRND_TYPE_GREG16_31, | |
38 | /* r0 - r31. */ | |
39 | OPRND_TYPE_AREG, | |
40 | /* (rx). */ | |
41 | OPRND_TYPE_AREG_WITH_BRACKET, | |
42 | OPRND_TYPE_AREG_WITH_LSHIFT, | |
43 | OPRND_TYPE_AREG_WITH_LSHIFT_FPU, | |
44 | ||
45 | OPRND_TYPE_FREG_WITH_INDEX, | |
46 | /* r1 only, for xtrb0(1)(2)(3) in csky v1 ISA. */ | |
47 | OPRND_TYPE_REG_r1a, | |
48 | /* r1 only, for divs/divu in csky v1 ISA. */ | |
49 | OPRND_TYPE_REG_r1b, | |
50 | /* r28. */ | |
51 | OPRND_TYPE_REG_r28, | |
52 | OPRND_TYPE_REGr4_r7, | |
53 | /* sp register with bracket. */ | |
54 | OPRND_TYPE_REGbsp, | |
55 | /* sp register. */ | |
56 | OPRND_TYPE_REGsp, | |
57 | /* Register with bracket. */ | |
58 | OPRND_TYPE_REGnr4_r7, | |
59 | /* Not sp register. */ | |
60 | OPRND_TYPE_REGnsp, | |
61 | /* Not lr register. */ | |
62 | OPRND_TYPE_REGnlr, | |
63 | /* Not sp/lr register. */ | |
64 | OPRND_TYPE_REGnsplr, | |
65 | /* hi/lo register. */ | |
66 | OPRND_TYPE_REGhilo, | |
67 | /* VDSP register. */ | |
68 | OPRND_TYPE_VREG, | |
69 | ||
70 | /* cp index. */ | |
71 | OPRND_TYPE_CPIDX, | |
72 | /* cp regs. */ | |
73 | OPRND_TYPE_CPREG, | |
74 | /* cp cregs. */ | |
75 | OPRND_TYPE_CPCREG, | |
76 | /* fpu regs. */ | |
77 | OPRND_TYPE_FREG, | |
78 | /* fpu even regs. */ | |
79 | OPRND_TYPE_FEREG, | |
80 | /* Float round mode. */ | |
81 | OPRND_TYPE_RM, | |
82 | /* PSR bits. */ | |
83 | OPRND_TYPE_PSR_BITS_LIST, | |
84 | ||
85 | /* Constant. */ | |
86 | OPRND_TYPE_CONSTANT, | |
87 | /* Floating Constant. */ | |
88 | OPRND_TYPE_FCONSTANT, | |
89 | /* Extern lrw constant. */ | |
90 | OPRND_TYPE_ELRW_CONSTANT, | |
91 | /* [label]. */ | |
92 | OPRND_TYPE_LABEL_WITH_BRACKET, | |
93 | /* The operand is the same as first reg. It is a dummy reg that doesn't | |
94 | appear in the binary code of the instruction. It is also used by | |
95 | the disassembler. | |
96 | For example: bclri rz, rz, imm5 -> bclri rz, imm5. */ | |
97 | OPRND_TYPE_DUMMY_REG, | |
98 | /* The type of the operand is same as the first operand. If the value | |
99 | of the operand is same as the first operand, we can use a 16-bit | |
100 | instruction to represent the opcode. | |
101 | For example: addc r1, r1, r2 -> addc16 r1, r2. */ | |
102 | OPRND_TYPE_2IN1_DUMMY, | |
103 | /* Output a reg same as the first reg. | |
104 | For example: addc r17, r1 -> addc32 r17, r17, r1. | |
105 | The old "addc" cannot be represented by a 16-bit instruction because | |
106 | 16-bit "addc" only supports regs from r0 to r15. So we use "addc32" | |
107 | which has 3 operands, and duplicate the first operand to the second. */ | |
108 | OPRND_TYPE_DUP_GREG0_7, | |
109 | OPRND_TYPE_DUP_GREG0_15, | |
110 | OPRND_TYPE_DUP_AREG, | |
111 | /* Immediate. */ | |
112 | OPRND_TYPE_IMM1b, | |
113 | OPRND_TYPE_IMM2b, | |
114 | OPRND_TYPE_IMM3b, | |
115 | OPRND_TYPE_IMM4b, | |
116 | OPRND_TYPE_IMM5b, | |
117 | OPRND_TYPE_IMM7b, | |
118 | OPRND_TYPE_IMM8b, | |
1feede9b | 119 | OPRND_TYPE_IMM9b, |
b8891f8d AJ |
120 | OPRND_TYPE_IMM12b, |
121 | OPRND_TYPE_IMM15b, | |
122 | OPRND_TYPE_IMM16b, | |
123 | OPRND_TYPE_IMM18b, | |
124 | OPRND_TYPE_IMM32b, | |
125 | /* Immediate left shift 2 bits. */ | |
126 | OPRND_TYPE_IMM7b_LS2, | |
127 | OPRND_TYPE_IMM8b_LS2, | |
128 | /* OPRND_TYPE_IMM5b_a_b means: Immediate in (a, b). */ | |
129 | OPRND_TYPE_IMM5b_1_31, | |
130 | OPRND_TYPE_IMM5b_7_31, | |
131 | /* Operand type for rori and rotri. */ | |
132 | OPRND_TYPE_IMM5b_RORI, | |
133 | OPRND_TYPE_IMM5b_POWER, | |
134 | OPRND_TYPE_IMM5b_7_31_POWER, | |
135 | OPRND_TYPE_IMM5b_BMASKI, | |
136 | OPRND_TYPE_IMM8b_BMASKI, | |
137 | /* For v2 movih. */ | |
138 | OPRND_TYPE_IMM16b_MOVIH, | |
139 | /* For v2 ori. */ | |
140 | OPRND_TYPE_IMM16b_ORI, | |
141 | /* For v2 ld/st. */ | |
142 | OPRND_TYPE_IMM_LDST, | |
143 | OPRND_TYPE_IMM_FLDST, | |
144 | OPRND_TYPE_IMM2b_JMPIX, | |
145 | /* Offset for bloop. */ | |
146 | OPRND_TYPE_BLOOP_OFF4b, | |
147 | OPRND_TYPE_BLOOP_OFF12b, | |
148 | /* Offset for jump. */ | |
149 | OPRND_TYPE_OFF8b, | |
150 | OPRND_TYPE_OFF10b, | |
151 | OPRND_TYPE_OFF11b, | |
152 | OPRND_TYPE_OFF16b, | |
153 | OPRND_TYPE_OFF16b_LSL1, | |
154 | OPRND_TYPE_OFF26b, | |
155 | /* An immediate or label. */ | |
156 | OPRND_TYPE_IMM_OFF18b, | |
157 | /* Offset immediate. */ | |
158 | OPRND_TYPE_OIMM3b, | |
159 | OPRND_TYPE_OIMM4b, | |
160 | OPRND_TYPE_OIMM5b, | |
161 | OPRND_TYPE_OIMM8b, | |
162 | OPRND_TYPE_OIMM12b, | |
163 | OPRND_TYPE_OIMM16b, | |
164 | OPRND_TYPE_OIMM18b, | |
165 | /* For csky v2 idly. */ | |
166 | OPRND_TYPE_OIMM5b_IDLY, | |
167 | /* For v2 bmaski. */ | |
168 | OPRND_TYPE_OIMM5b_BMASKI, | |
169 | /* Constants. */ | |
170 | OPRND_TYPE_CONST1, | |
171 | /* PC relative offset. */ | |
172 | OPRND_TYPE_PCR_OFFSET_16K, | |
173 | OPRND_TYPE_PCR_OFFSET_64K, | |
174 | OPRND_TYPE_PCR_OFFSET_64M, | |
175 | OPRND_TYPE_CPFUNC, | |
176 | OPRND_TYPE_GOT_PLT, | |
177 | OPRND_TYPE_REGLIST_LDM, | |
178 | OPRND_TYPE_REGLIST_DASH, | |
179 | OPRND_TYPE_FREGLIST_DASH, | |
180 | OPRND_TYPE_REGLIST_COMMA, | |
181 | OPRND_TYPE_REGLIST_DASH_COMMA, | |
182 | OPRND_TYPE_BRACKET, | |
183 | OPRND_TYPE_ABRACKET, | |
184 | OPRND_TYPE_JBTF, | |
185 | OPRND_TYPE_JBR, | |
186 | OPRND_TYPE_JBSR, | |
187 | OPRND_TYPE_UNCOND10b, | |
188 | OPRND_TYPE_UNCOND16b, | |
189 | OPRND_TYPE_COND10b, | |
190 | OPRND_TYPE_COND16b, | |
191 | OPRND_TYPE_JCOMPZ, | |
192 | OPRND_TYPE_LSB2SIZE, | |
193 | OPRND_TYPE_MSB2SIZE, | |
194 | OPRND_TYPE_LSB, | |
195 | OPRND_TYPE_MSB, | |
196 | /* Single float and double float. */ | |
197 | OPRND_TYPE_SFLOAT, | |
198 | OPRND_TYPE_DFLOAT, | |
1feede9b CQ |
199 | OPRND_TYPE_HFLOAT_FMOVI, |
200 | OPRND_TYPE_SFLOAT_FMOVI, | |
201 | OPRND_TYPE_DFLOAT_FMOVI, | |
b8891f8d AJ |
202 | }; |
203 | ||
204 | /* Operand descriptors. */ | |
205 | struct operand | |
206 | { | |
207 | /* Mask for suboperand. */ | |
208 | unsigned int mask; | |
209 | /* Suboperand type. */ | |
210 | enum operand_type type; | |
211 | /* Operand shift. */ | |
212 | int shift; | |
213 | }; | |
214 | ||
215 | struct soperand | |
216 | { | |
217 | /* Mask for operand. */ | |
218 | unsigned int mask; | |
219 | /* Operand type. */ | |
220 | enum operand_type type; | |
221 | /* Operand shift. */ | |
222 | int shift; | |
223 | /* Suboperand. */ | |
224 | struct operand subs[3]; | |
225 | }; | |
226 | ||
227 | union csky_operand | |
228 | { | |
0c0577f6 | 229 | struct operand oprnds[MAX_OPRND_NUM]; |
b8891f8d AJ |
230 | struct suboperand1 |
231 | { | |
232 | struct operand oprnd; | |
233 | struct soperand soprnd; | |
234 | } soprnd1; | |
235 | struct suboperand2 | |
236 | { | |
237 | struct soperand soprnd; | |
238 | struct operand oprnd; | |
239 | } soprnd2; | |
240 | }; | |
241 | ||
242 | /* Describe a single instruction encoding. */ | |
243 | struct csky_opcode_info | |
244 | { | |
245 | /* How many operands. */ | |
246 | long operand_num; | |
247 | /* The instruction opcode. */ | |
248 | unsigned int opcode; | |
249 | /* Operand information. */ | |
250 | union csky_operand oprnd; | |
251 | }; | |
252 | ||
253 | /* C-SKY instruction description. Each mnemonic can have multiple | |
254 | 16-bit and 32-bit encodings. */ | |
255 | struct csky_opcode | |
256 | { | |
257 | /* The instruction name. */ | |
258 | const char *mnemonic; | |
259 | /* Whether this is an unconditional control transfer instruction, | |
260 | for the purposes of placing literal pools after it. | |
261 | 0 = no, 1 = within function, 2 = end of function. | |
262 | See check_literals in gas/config/tc-csky.c. */ | |
263 | int transfer; | |
264 | /* Encodings for 16-bit opcodes. */ | |
265 | struct csky_opcode_info op16[OP_TABLE_NUM]; | |
266 | /* Encodings for 32-bit opcodes. */ | |
267 | struct csky_opcode_info op32[OP_TABLE_NUM]; | |
268 | /* Instruction set flag. */ | |
0861f561 CQ |
269 | BFD_HOST_U_64_BIT isa_flag16; |
270 | BFD_HOST_U_64_BIT isa_flag32; | |
b8891f8d AJ |
271 | /* Whether this insn needs relocation, 0: no, !=0: yes. */ |
272 | signed int reloc16; | |
273 | signed int reloc32; | |
274 | /* Whether this insn needs relaxation, 0: no, != 0: yes. */ | |
275 | signed int relax; | |
276 | /* Worker function to call when this instruction needs special assembler | |
277 | handling. */ | |
278 | bfd_boolean (*work)(void); | |
279 | }; | |
280 | ||
281 | /* The following are the opcodes used in relax/fix process. */ | |
282 | #define CSKYV1_INST_JMPI 0x7000 | |
283 | #define CSKYV1_INST_ADDI 0x2000 | |
284 | #define CSKYV1_INST_SUBI 0x2400 | |
285 | #define CSKYV1_INST_LDW 0x8000 | |
286 | #define CSKYV1_INST_STW 0x9000 | |
287 | #define CSKYV1_INST_BSR 0xf800 | |
288 | #define CSKYV1_INST_LRW 0x7000 | |
289 | #define CSKYV1_INST_ADDU 0x1c00 | |
290 | #define CSKYV1_INST_JMP 0x00c0 | |
291 | #define CSKYV1_INST_MOV_R1_RX 0x1201 | |
292 | #define CSKYV1_INST_MOV_RX_R1 0x1210 | |
293 | ||
294 | #define CSKYV2_INST_BT16 0x0800 | |
295 | #define CSKYV2_INST_BF16 0x0c00 | |
296 | #define CSKYV2_INST_BT32 0xe8600000 | |
297 | #define CSKYV2_INST_BF32 0xe8400000 | |
298 | #define CSKYV2_INST_BR32 0xe8000000 | |
299 | #define CSKYV2_INST_NOP 0x6c03 | |
300 | #define CSKYV2_INST_MOVI16 0x3000 | |
301 | #define CSKYV2_INST_MOVI32 0xea000000 | |
302 | #define CSKYV2_INST_MOVIH 0xea200000 | |
303 | #define CSKYV2_INST_LRW16 0x1000 | |
304 | #define CSKYV2_INST_LRW32 0xea800000 | |
305 | #define CSKYV2_INST_BSR32 0xe0000000 | |
306 | #define CSKYV2_INST_BR32 0xe8000000 | |
307 | #define CSKYV2_INST_FLRW 0xf4003800 | |
308 | #define CSKYV2_INST_JMPI32 0xeac00000 | |
309 | #define CSKYV2_INST_JSRI32 0xeae00000 | |
310 | #define CSKYV2_INST_JSRI_TO_LRW 0xea9a0000 | |
311 | #define CSKYV2_INST_JSR_R26 0xe8fa0000 | |
312 | #define CSKYV2_INST_MOV_R0_R0 0xc4004820 | |
313 | ||
314 | #define OPRND_SHIFT_0_BIT 0 | |
315 | #define OPRND_SHIFT_1_BIT 1 | |
316 | #define OPRND_SHIFT_2_BIT 2 | |
317 | #define OPRND_SHIFT_3_BIT 3 | |
318 | #define OPRND_SHIFT_4_BIT 4 | |
319 | ||
320 | #define OPRND_MASK_NONE 0x0 | |
321 | #define OPRND_MASK_0_1 0x3 | |
322 | #define OPRND_MASK_0_2 0x7 | |
323 | #define OPRND_MASK_0_3 0xf | |
324 | #define OPRND_MASK_0_4 0x1f | |
325 | #define OPRND_MASK_0_7 0xff | |
326 | #define OPRND_MASK_0_8 0x1ff | |
327 | #define OPRND_MASK_0_9 0x3ff | |
328 | #define OPRND_MASK_0_10 0x7ff | |
329 | #define OPRND_MASK_0_11 0xfff | |
330 | #define OPRND_MASK_0_14 0x7fff | |
331 | #define OPRND_MASK_0_15 0xffff | |
332 | #define OPRND_MASK_0_17 0x3ffff | |
333 | #define OPRND_MASK_0_25 0x3ffffff | |
334 | #define OPRND_MASK_2_4 0x1c | |
335 | #define OPRND_MASK_2_5 0x3c | |
336 | #define OPRND_MASK_3_7 0xf8 | |
337 | #define OPRND_MASK_4 0x10 | |
1feede9b | 338 | #define OPRND_MASK_4_5 0x30 |
b8891f8d AJ |
339 | #define OPRND_MASK_4_6 0x70 |
340 | #define OPRND_MASK_4_7 0xf0 | |
341 | #define OPRND_MASK_4_8 0x1f0 | |
342 | #define OPRND_MASK_4_10 0x7f0 | |
343 | #define OPRND_MASK_5 0x20 | |
344 | #define OPRND_MASK_5_6 0x60 | |
345 | #define OPRND_MASK_5_7 0xe0 | |
346 | #define OPRND_MASK_5_8 0x1e0 | |
347 | #define OPRND_MASK_5_9 0x3e0 | |
1feede9b CQ |
348 | #define OPRND_MASK_6 0x40 |
349 | #define OPRND_MASK_6_7 0xc0 | |
350 | #define OPRND_MASK_6_8 0x1c0 | |
b8891f8d AJ |
351 | #define OPRND_MASK_6_9 0x3c0 |
352 | #define OPRND_MASK_6_10 0x7c0 | |
1feede9b CQ |
353 | #define OPRND_MASK_7 0x80 |
354 | #define OPRND_MASK_7_8 0x180 | |
b8891f8d AJ |
355 | #define OPRND_MASK_8_9 0x300 |
356 | #define OPRND_MASK_8_10 0x700 | |
357 | #define OPRND_MASK_8_11 0xf00 | |
358 | #define OPRND_MASK_9_10 0x600 | |
359 | #define OPRND_MASK_9_12 0x1e00 | |
360 | #define OPRND_MASK_10_11 0xc00 | |
361 | #define OPRND_MASK_10_14 0x7c00 | |
362 | #define OPRND_MASK_12_15 0xf000 | |
363 | #define OPRND_MASK_13_17 0x3e000 | |
364 | #define OPRND_MASK_16_19 0xf0000 | |
365 | #define OPRND_MASK_16_20 0x1f0000 | |
366 | #define OPRND_MASK_16_25 0x3ff0000 | |
1feede9b CQ |
367 | #define OPRND_MASK_17_24 0x1fe0000 |
368 | #define OPRND_MASK_20 0x0100000 | |
369 | #define OPRND_MASK_20_21 0x0300000 | |
370 | #define OPRND_MASK_20_22 0x0700000 | |
371 | #define OPRND_MASK_20_23 0x0f00000 | |
372 | #define OPRND_MASK_20_24 0x1f00000 | |
373 | #define OPRND_MASK_20_25 0x3f00000 | |
b8891f8d AJ |
374 | #define OPRND_MASK_21_24 0x1e00000 |
375 | #define OPRND_MASK_21_25 0x3e00000 | |
376 | #define OPRND_MASK_25 0x2000000 | |
377 | #define OPRND_MASK_RSV 0xffffffff | |
1feede9b CQ |
378 | #define OPRND_MASK_0_3or5_8 OPRND_MASK_0_3 | OPRND_MASK_5_8 |
379 | #define OPRND_MASK_0_3or6_7 OPRND_MASK_0_3 | OPRND_MASK_6_7 | |
b8891f8d | 380 | #define OPRND_MASK_0_3or21_24 OPRND_MASK_0_3 | OPRND_MASK_21_24 |
1feede9b CQ |
381 | #define OPRND_MASK_0_3or25 OPRND_MASK_0_3 | OPRND_MASK_25 |
382 | #define OPRND_MASK_0_4or21_24 OPRND_MASK_0_4 | OPRND_MASK_21_24 | |
b8891f8d AJ |
383 | #define OPRND_MASK_0_4or21_25 OPRND_MASK_0_4 | OPRND_MASK_21_25 |
384 | #define OPRND_MASK_0_4or16_20 OPRND_MASK_0_4 | OPRND_MASK_16_20 | |
385 | #define OPRND_MASK_0_4or8_10 OPRND_MASK_0_4 | OPRND_MASK_8_10 | |
386 | #define OPRND_MASK_0_4or8_9 OPRND_MASK_0_4 | OPRND_MASK_8_9 | |
387 | #define OPRND_MASK_0_14or16_20 OPRND_MASK_0_14 | OPRND_MASK_16_20 | |
388 | #define OPRND_MASK_4or5_8 OPRND_MASK_4 | OPRND_MASK_5_8 | |
1feede9b CQ |
389 | #define OPRND_MASK_5or20_21 OPRND_MASK_5 | OPRND_MASK_20_21 |
390 | #define OPRND_MASK_5or20_22 OPRND_MASK_5 | OPRND_MASK_20_22 | |
391 | #define OPRND_MASK_5or20_23 OPRND_MASK_5 | OPRND_MASK_20_23 | |
392 | #define OPRND_MASK_5or20_24 OPRND_MASK_5 | OPRND_MASK_20_24 | |
393 | #define OPRND_MASK_5or20_25 OPRND_MASK_5 | OPRND_MASK_20_25 | |
b8891f8d AJ |
394 | #define OPRND_MASK_5or21_24 OPRND_MASK_5 | OPRND_MASK_21_24 |
395 | #define OPRND_MASK_2_5or6_9 OPRND_MASK_2_5 | OPRND_MASK_6_9 | |
396 | #define OPRND_MASK_4_6or21_25 OPRND_MASK_4_6 | OPRND_MASK_21_25 | |
397 | #define OPRND_MASK_4_7or21_24 OPRND_MASK_4_7 | OPRND_MASK_21_24 | |
398 | #define OPRND_MASK_5_6or21_25 OPRND_MASK_5_6 | OPRND_MASK_21_25 | |
399 | #define OPRND_MASK_5_7or8_10 OPRND_MASK_5_7 | OPRND_MASK_8_10 | |
400 | #define OPRND_MASK_5_9or21_25 OPRND_MASK_5_9 | OPRND_MASK_21_25 | |
1feede9b CQ |
401 | #define OPRND_MASK_8_9or21_25 OPRND_MASK_8_9 | OPRND_MASK_21_25 |
402 | #define OPRND_MASK_8_9or16_25 OPRND_MASK_8_9 | OPRND_MASK_16_20 | OPRND_MASK_21_25 | |
b8891f8d AJ |
403 | #define OPRND_MASK_16_19or21_24 OPRND_MASK_16_19 | OPRND_MASK_21_24 |
404 | #define OPRND_MASK_16_20or21_25 OPRND_MASK_16_20 | OPRND_MASK_21_25 | |
405 | #define OPRND_MASK_4or9_10or25 OPRND_MASK_4 | OPRND_MASK_9_10 | OPRND_MASK_25 | |
406 | #define OPRND_MASK_4_7or16_24 OPRND_MASK_4_7 | OPRND_MASK_16_20 | OPRND_MASK_21_24 | |
1feede9b CQ |
407 | #define OPRND_MASK_4_6or20 OPRND_MASK_4_6 | OPRND_MASK_20 |
408 | #define OPRND_MASK_5_7or20 OPRND_MASK_5_7 | OPRND_MASK_20 | |
409 | #define OPRND_MASK_4_5or20or25 OPRND_MASK_4 | OPRND_MASK_5 | OPRND_MASK_20 | OPRND_MASK_25 | |
410 | #define OPRND_MASK_4_6or20or25 OPRND_MASK_4_6 | OPRND_MASK_20 | OPRND_MASK_25 | |
411 | #define OPRND_MASK_4_7or20or25 OPRND_MASK_4_7 | OPRND_MASK_20 | OPRND_MASK_25 | |
412 | #define OPRND_MASK_6_9or17_24 OPRND_MASK_6_9 | OPRND_MASK_17_24 | |
413 | #define OPRND_MASK_6_7or20 OPRND_MASK_6_7 | OPRND_MASK_20 | |
414 | #define OPRND_MASK_6or20 OPRND_MASK_6 | OPRND_MASK_20 | |
415 | #define OPRND_MASK_7or20 OPRND_MASK_7 | OPRND_MASK_20 | |
416 | #define OPRND_MASK_5or8_9or16_25 OPRND_MASK_5 | OPRND_MASK_8_9or16_25 | |
417 | #define OPRND_MASK_5or8_9or20_25 OPRND_MASK_5 | OPRND_MASK_8_9 | OPRND_MASK_20_25 | |
b8891f8d AJ |
418 | |
419 | #define OPERAND_INFO(mask, type, shift) \ | |
420 | {OPRND_MASK_##mask, OPRND_TYPE_##type, shift} | |
421 | ||
422 | #define OPCODE_INFO_NONE() \ | |
423 | {-2, 0, \ | |
424 | {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
425 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
426 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
427 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
428 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
429 | ||
430 | /* Here and in subsequent macros, the "oprnd" arguments are the | |
431 | parenthesized arglist to the OPERAND_INFO macro above. */ | |
432 | #define OPCODE_INFO(num, op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ | |
433 | {num, op, \ | |
434 | {OPERAND_INFO oprnd1, OPERAND_INFO oprnd2, OPERAND_INFO oprnd3, \ | |
435 | OPERAND_INFO oprnd4, OPERAND_INFO oprnd5}} | |
436 | ||
437 | #define OPCODE_INFO0(op) \ | |
438 | {0, op, \ | |
439 | {{OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
440 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
441 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
442 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
443 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
444 | #define OPCODE_INFO1(op, oprnd) \ | |
445 | {1, op, \ | |
446 | {{OPERAND_INFO oprnd, \ | |
447 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
448 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
449 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
450 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
451 | #define OPCODE_INFO2(op, oprnd1, oprnd2) \ | |
452 | {2, op, \ | |
453 | {{OPERAND_INFO oprnd1, \ | |
454 | OPERAND_INFO oprnd2, \ | |
455 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
456 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
457 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
458 | #define OPCODE_INFO3(op, oprnd1, oprnd2, oprnd3) \ | |
459 | {3, op, \ | |
460 | {{OPERAND_INFO oprnd1, \ | |
461 | OPERAND_INFO oprnd2, \ | |
462 | OPERAND_INFO oprnd3, \ | |
463 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
464 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
465 | #define OPCODE_INFO4(op, oprnd1, oprnd2, oprnd3, oprnd4) \ | |
466 | {4, op, \ | |
467 | {{OPERAND_INFO oprnd1, \ | |
468 | OPERAND_INFO oprnd2, \ | |
469 | OPERAND_INFO oprnd3, \ | |
470 | OPERAND_INFO oprnd4, \ | |
471 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
472 | #define OPCODE_INFO_LIST(op, oprnd) \ | |
473 | {-1, op, \ | |
474 | {{OPERAND_INFO oprnd, \ | |
475 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
476 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) , \ | |
477 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT), \ | |
478 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
479 | #define OPCODE_INFO5(op, oprnd1, oprnd2, oprnd3, oprnd4, oprnd5) \ | |
480 | {5, op, \ | |
481 | {{OPERAND_INFO oprnd1, \ | |
482 | OPERAND_INFO oprnd2, \ | |
483 | OPERAND_INFO oprnd3, \ | |
484 | OPERAND_INFO oprnd4, \ | |
485 | OPERAND_INFO oprnd5}}} | |
486 | ||
487 | #define BRACKET_OPRND(oprnd1, oprnd2) \ | |
488 | OPERAND_INFO (RSV, BRACKET, OPRND_SHIFT_0_BIT), \ | |
489 | OPERAND_INFO oprnd1, \ | |
490 | OPERAND_INFO oprnd2, \ | |
491 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) | |
492 | #define ABRACKET_OPRND(oprnd1, oprnd2) \ | |
493 | OPERAND_INFO (RSV, ABRACKET, OPRND_SHIFT_0_BIT), \ | |
494 | OPERAND_INFO oprnd1, \ | |
495 | OPERAND_INFO oprnd2, \ | |
496 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT) | |
497 | ||
498 | #define SOPCODE_INFO1(op, soprnd) \ | |
499 | {1, op, \ | |
500 | {{soprnd, \ | |
501 | OPERAND_INFO (NONE, NONE, OPRND_SHIFT_0_BIT)}}} | |
502 | #define SOPCODE_INFO2(op, oprnd, soprnd) \ | |
503 | {2, op, \ | |
504 | {{OPERAND_INFO oprnd, soprnd}}} | |
505 | ||
506 | ||
507 | /* Before using the opcode-defining macros, there need to be | |
508 | #defines for _TRANSFER, _RELOC16, _RELOC32, and _RELAX. See | |
509 | below. */ | |
510 | /* FIXME: it is a wart that these parameters are not explicit. */ | |
511 | ||
512 | #define OP16(mnem, opcode16, isa) \ | |
513 | {mnem, _TRANSFER, \ | |
514 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
515 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
516 | isa, 0, _RELOC16, 0, _RELAX, NULL} | |
517 | ||
518 | #ifdef BUILD_AS | |
519 | ||
520 | #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ | |
521 | {mnem, _TRANSFER, \ | |
522 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
523 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
524 | isa, 0, _RELOC16, 0, _RELAX, work} | |
525 | #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ | |
526 | {mnem, _TRANSFER, \ | |
527 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
528 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
529 | 0, isa, 0, _RELOC32, _RELAX, work} | |
530 | #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ | |
531 | {mnem, _TRANSFER, \ | |
532 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
533 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
534 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} | |
535 | #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ | |
536 | {mnem, _TRANSFER, \ | |
537 | {opcode16a, opcode16b}, \ | |
538 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
539 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} | |
540 | #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ | |
541 | {mnem, _TRANSFER, \ | |
542 | {opcode16a, opcode16b}, \ | |
543 | {opcode32a, opcode32b}, \ | |
544 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, work} | |
545 | #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ | |
546 | {mnem, _TRANSFER, \ | |
547 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
548 | {opcode32a, opcode32b}, \ | |
549 | 0, isa, 0, _RELOC32, _RELAX, work} | |
550 | ||
551 | #else /* ifdef BUILD_AS */ | |
552 | ||
553 | #define OP16_WITH_WORK(mnem, opcode16, isa, work) \ | |
554 | {mnem, _TRANSFER, \ | |
555 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
556 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
557 | isa, 0, _RELOC16, 0, _RELAX, NULL} | |
558 | #define OP32_WITH_WORK(mnem, opcode32, isa, work) \ | |
559 | {mnem, _TRANSFER, \ | |
560 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
561 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
562 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
563 | #define OP16_OP32_WITH_WORK(mnem, opcode16, isa16, opcode32, isa32, work) \ | |
564 | {mnem, _TRANSFER, \ | |
565 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
566 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
567 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
568 | #define DOP16_OP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32, isa32, work) \ | |
569 | {mnem, _TRANSFER, \ | |
570 | {opcode16a, opcode16b}, \ | |
571 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
572 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
573 | #define DOP16_DOP32_WITH_WORK(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32, work) \ | |
574 | {mnem, _TRANSFER, \ | |
575 | {opcode16a, opcode16b}, \ | |
576 | {opcode32a, opcode32b}, \ | |
577 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
578 | #define DOP32_WITH_WORK(mnem, opcode32a, opcode32b, isa, work) \ | |
579 | {mnem, _TRANSFER, \ | |
580 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
581 | {opcode32a, opcode32b}, \ | |
582 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
583 | ||
584 | #endif /* ifdef BUILD_AS */ | |
585 | ||
586 | #define DOP16(mnem, opcode16_1, opcode16_2, isa) \ | |
587 | {mnem, _TRANSFER, \ | |
588 | {opcode16_1, opcode16_2}, \ | |
589 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
590 | isa, 0, _RELOC16, 0, _RELAX, NULL} | |
591 | #define OP32(mnem, opcode32, isa) \ | |
592 | {mnem, _TRANSFER, \ | |
593 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
594 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
595 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
596 | #define DOP32(mnem, opcode32a, opcode32b, isa) \ | |
597 | {mnem, _TRANSFER, \ | |
598 | {OPCODE_INFO_NONE (), OPCODE_INFO_NONE ()}, \ | |
599 | {opcode32a, opcode32b}, \ | |
600 | 0, isa, 0, _RELOC32, _RELAX, NULL} | |
601 | #define OP16_OP32(mnem, opcode16, isa16, opcode32, isa32) \ | |
602 | {mnem, _TRANSFER, \ | |
603 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
604 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
605 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
606 | #define DOP16_OP32(mnem, opcode16a, opcode16b, isa16, opcode32, isa32) \ | |
607 | {mnem, _TRANSFER, \ | |
608 | {opcode16a, opcode16b}, \ | |
609 | {opcode32, OPCODE_INFO_NONE ()}, \ | |
610 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
611 | #define OP16_DOP32(mnem, opcode16, isa16, opcode32a, opcode32b, isa32) \ | |
612 | {mnem, _TRANSFER, \ | |
613 | {opcode16, OPCODE_INFO_NONE ()}, \ | |
614 | {opcode32a, opcode32b}, \ | |
615 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
616 | #define DOP16_DOP32(mnem, opcode16a, opcode16b, isa16, opcode32a, opcode32b, isa32) \ | |
617 | {mnem, _TRANSFER, \ | |
618 | {opcode16a, opcode16b}, \ | |
619 | {opcode32a, opcode32b}, \ | |
620 | isa16, isa32, _RELOC16, _RELOC32, _RELAX, NULL} | |
621 | ||
622 | ||
623 | /* Register names and numbers. */ | |
624 | #define V1_REG_SP 0 | |
625 | #define V1_REG_LR 15 | |
626 | ||
627 | struct csky_reg | |
628 | { | |
629 | const char *name; | |
630 | int index; | |
631 | int flag; | |
632 | }; | |
633 | ||
634 | const char *csky_general_reg[] = | |
635 | { | |
636 | "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7", | |
637 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15", | |
638 | "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23", | |
639 | "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31", | |
640 | NULL, | |
641 | }; | |
642 | ||
643 | /* TODO: optimize. */ | |
644 | const char *cskyv2_general_alias_reg[] = | |
645 | { | |
646 | "a0", "a1", "a2", "a3", "l0", "l1", "l2", "l3", | |
647 | "l4", "l5", "l6", "l7", "t0", "t1", "sp", "lr", | |
648 | "l8", "l9", "t2", "t3", "t4", "t5", "t6", "t7", | |
649 | "t8", "t9", "r26", "r27", "rdb", "gb", "r30", "r31", | |
650 | NULL, | |
651 | }; | |
652 | ||
653 | /* TODO: optimize. */ | |
654 | const char *cskyv1_general_alias_reg[] = | |
655 | { | |
656 | "sp", "r1", "a0", "a1", "a2", "a3", "a4", "a5", | |
657 | "fp", "l0", "l1", "l2", "l3", "l4", "gb", "lr", | |
658 | NULL, | |
659 | }; | |
660 | ||
661 | /* TODO: optimize. */ | |
662 | const char *csky_fpu_reg[] = | |
663 | { | |
664 | "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7", | |
665 | "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15", | |
666 | "fr16", "fr17", "fr18", "fr19", "fr20", "fr21", "fr22", "fr23", | |
667 | "fr24", "fr25", "fr26", "fr27", "fr28", "fr29", "fr30", "fr31", | |
668 | NULL, | |
669 | }; | |
670 | ||
671 | /* Control Registers. */ | |
672 | struct csky_reg csky_ctrl_regs[] = | |
673 | { | |
674 | {"psr", 0, 0}, {"vbr", 1, 0}, {"epsr", 2, 0}, {"fpsr", 3, 0}, | |
675 | {"epc", 4, 0}, {"fpc", 5, 0}, {"ss0", 6, 0}, {"ss1", 7, 0}, | |
676 | {"ss2", 8, 0}, {"ss3", 9, 0}, {"ss4", 10, 0}, {"gcr", 11, 0}, | |
677 | {"gsr", 12, 0}, {"cpuidr", 13, 0}, {"dcsr", 14, 0}, {"cwr", 15, 0}, | |
678 | {"cfr", 16, 0}, {"ccr", 17, 0}, {"capr", 19, 0}, {"pacr", 20, 0}, | |
679 | {"rid", 21, 0}, {"sedcr", 8, CSKY_ISA_TRUST}, {"sepcr", 9, CSKY_ISA_TRUST}, | |
680 | {NULL, 0, 0} | |
681 | }; | |
682 | ||
683 | const char *csky_cp_idx[] = | |
684 | { | |
685 | "cp0", "cp1", "cp2", "cp3", "cp4", "cp5", "cp6", "cp7", | |
686 | "cp8", "cp9", "cp10", "cp11", "cp12", "cp13", "cp14", "cp15", | |
687 | "cp16", "cp17", "cp18", "cp19", "cp20", | |
688 | NULL, | |
689 | }; | |
690 | ||
691 | const char *csky_cp_reg[] = | |
692 | { | |
693 | "cpr0", "cpr1", "cpr2", "cpr3", "cpr4", "cpr5", "cpr6", "cpr7", | |
694 | "cpr8", "cpr9", "cpr10", "cpr11", "cpr12", "cpr13", "cpr14", "cpr15", | |
695 | "cpr16", "cpr17", "cpr18", "cpr19", "cpr20", "cpr21", "cpr22", "cpr23", | |
696 | "cpr24", "cpr25", "cpr26", "cpr27", "cpr28", "cpr29", "cpr30", "cpr31", | |
697 | "cpr32", "cpr33", "cpr34", "cpr35", "cpr36", "cpr37", "cpr38", "cpr39", | |
698 | "cpr40", "cpr41", "cpr42", "cpr43", "cpr44", "cpr45", "cpr46", "cpr47", | |
699 | "cpr48", "cpr49", "cpr50", "cpr51", "cpr52", "cpr53", "cpr54", "cpr55", | |
700 | "cpr56", "cpr57", "cpr58", "cpr59", "cpr60", "cpr61", "cpr62", "cpr63", | |
701 | NULL, | |
702 | }; | |
703 | ||
704 | const char *csky_cp_creg[] = | |
705 | { | |
706 | "cpcr0", "cpcr1", "cpcr2", "cpcr3", | |
707 | "cpcr4", "cpcr5", "cpcr6", "cpcr7", | |
708 | "cpcr8", "cpcr9", "cpcr10", "cpcr11", | |
709 | "cpcr12", "cpcr13", "cpcr14", "cpcr15", | |
710 | "cpcr16", "cpcr17", "cpcr18", "cpcr19", | |
711 | "cpcr20", "cpcr21", "cpcr22", "cpcr23", | |
712 | "cpcr24", "cpcr25", "cpcr26", "cpcr27", | |
713 | "cpcr28", "cpcr29", "cpcr30", "cpcr31", | |
714 | "cpcr32", "cpcr33", "cpcr34", "cpcr35", | |
715 | "cpcr36", "cpcr37", "cpcr38", "cpcr39", | |
716 | "cpcr40", "cpcr41", "cpcr42", "cpcr43", | |
717 | "cpcr44", "cpcr45", "cpcr46", "cpcr47", | |
718 | "cpcr48", "cpcr49", "cpcr50", "cpcr51", | |
719 | "cpcr52", "cpcr53", "cpcr54", "cpcr55", | |
720 | "cpcr56", "cpcr57", "cpcr58", "cpcr59", | |
721 | "cpcr60", "cpcr61", "cpcr62", "cpcr63", | |
722 | NULL, | |
723 | }; | |
724 | ||
725 | struct psrbit | |
726 | { | |
727 | int value; | |
728 | int isa; | |
729 | const char *name; | |
730 | }; | |
731 | const struct psrbit cskyv1_psr_bits[] = | |
732 | { | |
733 | {1, 0, "ie"}, | |
734 | {2, 0, "fe"}, | |
735 | {4, 0, "ee"}, | |
736 | {8, 0, "af"}, | |
737 | {0, 0, NULL}, | |
738 | }; | |
739 | const struct psrbit cskyv2_psr_bits[] = | |
740 | { | |
741 | {8, 0, "ee"}, | |
742 | {4, 0, "ie"}, | |
743 | {2, 0, "fe"}, | |
744 | {1, 0, "af"}, | |
745 | {0x10, CSKY_ISA_TRUST, "sie"}, | |
746 | {0, 0, NULL}, | |
747 | }; | |
748 | ||
749 | ||
750 | /* C-SKY V1 opcodes. */ | |
751 | const struct csky_opcode csky_v1_opcodes[] = | |
752 | { | |
753 | #define _TRANSFER 0 | |
754 | #define _RELOC16 0 | |
755 | #define _RELOC32 0 | |
756 | #define _RELAX 0 | |
757 | OP16 ("bkpt", | |
758 | OPCODE_INFO0 (0x0000), | |
759 | CSKYV1_ISA_E1), | |
760 | OP16 ("sync", | |
761 | OPCODE_INFO0 (0x0001), | |
762 | CSKYV1_ISA_E1), | |
763 | #undef _TRANSFER | |
764 | #define _TRANSFER 2 | |
765 | OP16 ("rfi", | |
766 | OPCODE_INFO0 (0x0003), | |
767 | CSKYV1_ISA_E1), | |
768 | #undef _TRANSFER | |
769 | #define _TRANSFER 0 | |
770 | OP16 ("stop", | |
771 | OPCODE_INFO0 (0x0004), | |
772 | CSKYV1_ISA_E1), | |
773 | OP16 ("wait", | |
774 | OPCODE_INFO0 (0x0005), | |
775 | CSKYV1_ISA_E1), | |
776 | OP16 ("doze", | |
777 | OPCODE_INFO0 (0x0006), | |
778 | CSKYV1_ISA_E1), | |
779 | OP16 ("idly4", | |
780 | OPCODE_INFO0 (0x0007), | |
781 | CSKYV1_ISA_E1), | |
782 | OP16 ("trap", | |
783 | OPCODE_INFO1 (0x0008, | |
784 | (0_1, IMM2b, OPRND_SHIFT_0_BIT)), | |
785 | CSKYV1_ISA_E1), | |
786 | OP16 ("mvtc", | |
787 | OPCODE_INFO0 (0x000c), | |
788 | CSKY_ISA_DSP), | |
789 | OP16 ("cprc", | |
790 | OPCODE_INFO0 (0x000d), | |
791 | CSKY_ISA_CP), | |
792 | OP16 ("cpseti", | |
793 | OPCODE_INFO1 (0x0010, | |
794 | (0_3, CPIDX, OPRND_SHIFT_0_BIT)), | |
795 | CSKY_ISA_CP), | |
796 | OP16 ("mvc", | |
797 | OPCODE_INFO1 (0x0020, | |
798 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
799 | CSKYV1_ISA_E1), | |
800 | OP16 ("mvcv", | |
801 | OPCODE_INFO1 (0x0030, | |
802 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
803 | CSKYV1_ISA_E1), | |
804 | OP16 ("ldq", | |
805 | OPCODE_INFO2 (0x0040, | |
806 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
807 | (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), | |
808 | CSKYV1_ISA_E1), | |
809 | OP16 ("stq", | |
810 | OPCODE_INFO2 (0x0050, | |
811 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
812 | (0_3, REGnr4_r7, OPRND_SHIFT_0_BIT)), | |
813 | CSKYV1_ISA_E1), | |
814 | OP16 ("ldm", | |
815 | OPCODE_INFO2 (0x0060, | |
816 | (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
817 | (NONE, REGbsp, OPRND_SHIFT_0_BIT)), | |
818 | CSKYV1_ISA_E1), | |
819 | OP16 ("stm", | |
820 | OPCODE_INFO2 (0x0070, | |
821 | (0_3, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
822 | (NONE, REGbsp, OPRND_SHIFT_0_BIT)), | |
823 | CSKYV1_ISA_E1), | |
824 | DOP16 ("dect", | |
825 | OPCODE_INFO3 (0x0080, | |
826 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
827 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
828 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
829 | OPCODE_INFO1 (0x0080, | |
830 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
831 | CSKYV1_ISA_E1), | |
832 | DOP16 ("decf", | |
833 | OPCODE_INFO3 (0x0090, | |
834 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
835 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
836 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
837 | OPCODE_INFO1 (0x0090, | |
838 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
839 | CSKYV1_ISA_E1), | |
840 | DOP16 ("inct", | |
841 | OPCODE_INFO3 (0x00a0, | |
842 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
843 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
844 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
845 | OPCODE_INFO1 (0x00a0, | |
846 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
847 | CSKYV1_ISA_E1), | |
848 | DOP16 ("incf", | |
849 | OPCODE_INFO3 (0x00b0, | |
850 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
851 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
852 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
853 | OPCODE_INFO1 (0x00b0, | |
854 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
855 | CSKYV1_ISA_E1), | |
856 | #undef _TRANSFER | |
857 | #define _TRANSFER 2 | |
858 | OP16 ("jmp", | |
859 | OPCODE_INFO1 (0x00c0, | |
860 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
861 | CSKYV1_ISA_E1), | |
862 | #undef _TRANSFER | |
863 | #define _TRANSFER 0 | |
864 | OP16 ("jsr", | |
865 | OPCODE_INFO1 (0x00d0, | |
866 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
867 | CSKYV1_ISA_E1), | |
868 | DOP16 ("ff1", | |
869 | OPCODE_INFO2 (0x00e0, | |
870 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
871 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
872 | OPCODE_INFO1 (0x00e0, | |
873 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
874 | CSKYV1_ISA_E1), | |
875 | DOP16 ("brev", | |
876 | OPCODE_INFO2 (0x00f0, | |
877 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
878 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
879 | OPCODE_INFO1 (0x00f0, | |
880 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
881 | CSKYV1_ISA_E1), | |
882 | DOP16 ("xtrb3", | |
883 | OPCODE_INFO2 (0x0100, | |
884 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
885 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
886 | OPCODE_INFO1 (0x0100, | |
887 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
888 | CSKYV1_ISA_E1), | |
889 | DOP16 ("xtrb2", | |
890 | OPCODE_INFO2 (0x0110, | |
891 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
892 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
893 | OPCODE_INFO1 (0x0110, | |
894 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
895 | CSKYV1_ISA_E1), | |
896 | DOP16 ("xtrb1", | |
897 | OPCODE_INFO2 (0x0120, | |
898 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
899 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
900 | OPCODE_INFO1 (0x0120, | |
901 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
902 | CSKYV1_ISA_E1), | |
903 | DOP16 ("xtrb0", | |
904 | OPCODE_INFO2 (0x0130, | |
905 | (NONE, REG_r1a, OPRND_SHIFT_0_BIT), | |
906 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
907 | OPCODE_INFO1 (0x0130, | |
908 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
909 | CSKYV1_ISA_E1), | |
910 | DOP16 ("zextb", | |
911 | OPCODE_INFO2 (0x0140, | |
912 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
913 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
914 | OPCODE_INFO1 (0x0140, | |
915 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
916 | CSKYV1_ISA_E1), | |
917 | DOP16 ("sextb", | |
918 | OPCODE_INFO2 (0x0150, | |
919 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
920 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
921 | OPCODE_INFO1 (0x0150, | |
922 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
923 | CSKYV1_ISA_E1), | |
924 | DOP16 ("zexth", | |
925 | OPCODE_INFO2 (0x0160, | |
926 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
927 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
928 | OPCODE_INFO1 (0x0160, | |
929 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
930 | CSKYV1_ISA_E1), | |
931 | DOP16 ("sexth", | |
932 | OPCODE_INFO2 (0x0170, | |
933 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
934 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
935 | OPCODE_INFO1 (0x0170, | |
936 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
937 | CSKYV1_ISA_E1), | |
938 | DOP16 ("declt", | |
939 | OPCODE_INFO3 (0x0180, | |
940 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
941 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
942 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
943 | OPCODE_INFO1 (0x0180, | |
944 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
945 | CSKYV1_ISA_E1), | |
946 | OP16 ("tstnbz", | |
947 | OPCODE_INFO1 (0x0190, | |
948 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
949 | CSKYV1_ISA_E1), | |
950 | DOP16 ("decgt", | |
951 | OPCODE_INFO3 (0x01a0, | |
952 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
953 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
954 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
955 | OPCODE_INFO1 (0x01a0, | |
956 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
957 | CSKYV1_ISA_E1), | |
958 | DOP16 ("decne", | |
959 | OPCODE_INFO3 (0x01b0, | |
960 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
961 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
962 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
963 | OPCODE_INFO1 (0x01b0, | |
964 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
965 | CSKYV1_ISA_E1), | |
966 | OP16 ("clrt", | |
967 | OPCODE_INFO1 (0x01c0, | |
968 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
969 | CSKYV1_ISA_E1), | |
970 | OP16 ("clrf", | |
971 | OPCODE_INFO1 (0x01d0, | |
972 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
973 | CSKYV1_ISA_E1), | |
974 | DOP16 ("abs", | |
975 | OPCODE_INFO2 (0x01e0, | |
976 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
977 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
978 | OPCODE_INFO1 (0x01e0, | |
979 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
980 | CSKYV1_ISA_E1), | |
981 | DOP16 ("not", | |
982 | OPCODE_INFO2 (0x01f0, | |
983 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
984 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT)), | |
985 | OPCODE_INFO1 (0x01f0, | |
986 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
987 | CSKYV1_ISA_E1), | |
988 | OP16 ("movt", | |
989 | OPCODE_INFO2 (0x0200, | |
990 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
991 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
992 | CSKYV1_ISA_E1), | |
993 | DOP16 ("mult", | |
994 | OPCODE_INFO3 (0x0300, | |
995 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
996 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
997 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
998 | OPCODE_INFO2 (0x0300, | |
999 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1000 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1001 | CSKYV1_ISA_E1), | |
1002 | OP16 ("mac", | |
1003 | OPCODE_INFO2 (0x0400, | |
1004 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1005 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1006 | CSKY_ISA_MAC), | |
1007 | DOP16 ("subu", | |
1008 | OPCODE_INFO3 (0x0500, | |
1009 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1010 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1011 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1012 | OPCODE_INFO2 (0x0500, | |
1013 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1014 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1015 | CSKYV1_ISA_E1), | |
1016 | DOP16 ("sub", | |
1017 | OPCODE_INFO3 (0x0500, | |
1018 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1019 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1020 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1021 | OPCODE_INFO2 (0x0500, | |
1022 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1023 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1024 | CSKYV1_ISA_E1), | |
1025 | DOP16 ("addc", | |
1026 | OPCODE_INFO3 (0x0600, | |
1027 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1028 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1029 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1030 | OPCODE_INFO2 (0x0600, | |
1031 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1032 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1033 | CSKYV1_ISA_E1), | |
1034 | DOP16 ("subc", | |
1035 | OPCODE_INFO3 (0x0700, | |
1036 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1037 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1038 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1039 | OPCODE_INFO2 (0x0700, | |
1040 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1041 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1042 | CSKYV1_ISA_E1), | |
1043 | OP16 ("cprgr", | |
1044 | OPCODE_INFO2 (0x0800, | |
1045 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1046 | (4_8, CPREG, OPRND_SHIFT_0_BIT)), | |
1047 | CSKY_ISA_CP), | |
1048 | OP16 ("movf", | |
1049 | OPCODE_INFO2 (0x0a00, | |
1050 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1051 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1052 | CSKYV1_ISA_E1), | |
1053 | DOP16 ("lsr", | |
1054 | OPCODE_INFO3 (0x0b00, | |
1055 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1056 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1057 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1058 | OPCODE_INFO2 (0x0b00, | |
1059 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1060 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1061 | CSKYV1_ISA_E1), | |
1062 | OP16 ("cmphs", | |
1063 | OPCODE_INFO2 (0x0c00, | |
1064 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1065 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1066 | CSKYV1_ISA_E1), | |
1067 | OP16 ("cmplt", | |
1068 | OPCODE_INFO2 (0x0d00, | |
1069 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1070 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1071 | CSKYV1_ISA_E1), | |
1072 | OP16 ("tst", | |
1073 | OPCODE_INFO2 (0x0e00, | |
1074 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1075 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1076 | CSKYV1_ISA_E1), | |
1077 | OP16 ("cmpne", | |
1078 | OPCODE_INFO2 (0x0f00, | |
1079 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1080 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1081 | CSKYV1_ISA_E1), | |
1082 | OP16 ("mfcr", | |
1083 | OPCODE_INFO2 (0x1000, | |
1084 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1085 | (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), | |
1086 | CSKYV1_ISA_E1), | |
1087 | OP16 ("psrclr", | |
1088 | OPCODE_INFO_LIST (0x11f0, | |
1089 | (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
1090 | CSKYV1_ISA_E1), | |
1091 | OP16 ("psrset", | |
1092 | OPCODE_INFO_LIST (0x11f8, | |
1093 | (0_2, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
1094 | CSKYV1_ISA_E1), | |
1095 | OP16 ("mov", | |
1096 | OPCODE_INFO2 (0x1200, | |
1097 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1098 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1099 | CSKYV1_ISA_E1), | |
1100 | OP16 ("bgenr", | |
1101 | OPCODE_INFO2 (0x1300, | |
1102 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1103 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1104 | CSKYV1_ISA_E1), | |
1105 | DOP16 ("rsub", | |
1106 | OPCODE_INFO3 (0x1400, | |
1107 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1108 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1109 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1110 | OPCODE_INFO2 (0x1400, | |
1111 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1112 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1113 | CSKYV1_ISA_E1), | |
1114 | DOP16 ("ixw", | |
1115 | OPCODE_INFO3 (0x1500, | |
1116 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1117 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1118 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1119 | OPCODE_INFO2 (0x1500, | |
1120 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1121 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1122 | CSKYV1_ISA_E1), | |
1123 | DOP16 ("and", | |
1124 | OPCODE_INFO3 (0x1600, | |
1125 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1126 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1127 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1128 | OPCODE_INFO2 (0x1600, | |
1129 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1130 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1131 | CSKYV1_ISA_E1), | |
1132 | DOP16 ("xor", | |
1133 | OPCODE_INFO3 (0x1700, | |
1134 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1135 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1136 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1137 | OPCODE_INFO2 (0x1700, | |
1138 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1139 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1140 | CSKYV1_ISA_E1), | |
1141 | OP16 ("mtcr", | |
1142 | OPCODE_INFO2 (0x1800, | |
1143 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1144 | (4_8, CTRLREG, OPRND_SHIFT_0_BIT)), | |
1145 | CSKYV1_ISA_E1), | |
1146 | DOP16 ("asr", | |
1147 | OPCODE_INFO3 (0x1a00, | |
1148 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1149 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1150 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1151 | OPCODE_INFO2 (0x1a00, | |
1152 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1153 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1154 | CSKYV1_ISA_E1), | |
1155 | DOP16 ("lsl", | |
1156 | OPCODE_INFO3 (0x1b00, | |
1157 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1158 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1159 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1160 | OPCODE_INFO2 (0x1b00, | |
1161 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1162 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1163 | CSKYV1_ISA_E1), | |
1164 | DOP16 ("addu", | |
1165 | OPCODE_INFO3 (0x1c00, | |
1166 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1167 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1168 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1169 | OPCODE_INFO2 (0x1c00, | |
1170 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1171 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1172 | CSKYV1_ISA_E1), | |
1173 | OP16 ("add", | |
1174 | OPCODE_INFO2 (0x1c00, | |
1175 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1176 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1177 | CSKYV1_ISA_E1), | |
1178 | DOP16 ("ixh", | |
1179 | OPCODE_INFO3 (0x1d00, | |
1180 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1181 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1182 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1183 | OPCODE_INFO2 (0x1d00, | |
1184 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1185 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1186 | CSKYV1_ISA_E1), | |
1187 | DOP16 ("or", | |
1188 | OPCODE_INFO3 (0x1e00, | |
1189 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1190 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1191 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1192 | OPCODE_INFO2 (0x1e00, | |
1193 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1194 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1195 | CSKYV1_ISA_E1), | |
1196 | DOP16 ("andn", | |
1197 | OPCODE_INFO3 (0x1f00, | |
1198 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1199 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1200 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1201 | OPCODE_INFO2 (0x1f00, | |
1202 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1203 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1204 | CSKYV1_ISA_E1), | |
1205 | DOP16 ("addi", | |
1206 | OPCODE_INFO3 (0x2000, | |
1207 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1208 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1209 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
1210 | OPCODE_INFO2 (0x2000, | |
1211 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1212 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
1213 | CSKYV1_ISA_E1), | |
1214 | OP16 ("cmplti", | |
1215 | OPCODE_INFO2 (0x2200, | |
1216 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1217 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
1218 | CSKYV1_ISA_E1), | |
1219 | DOP16 ("subi", | |
1220 | OPCODE_INFO3 (0x2400, | |
1221 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1222 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1223 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
1224 | OPCODE_INFO2 (0x2400, | |
1225 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1226 | (4_8, OIMM5b, OPRND_SHIFT_0_BIT)), | |
1227 | CSKYV1_ISA_E1), | |
1228 | OP16 ("cpwgr", | |
1229 | OPCODE_INFO2 (0x2600, | |
1230 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1231 | (4_8, CPREG, OPRND_SHIFT_0_BIT)), | |
1232 | CSKY_ISA_CP), | |
1233 | DOP16 ("rsubi", | |
1234 | OPCODE_INFO3 (0x2800, | |
1235 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1236 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1237 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1238 | OPCODE_INFO2 (0x2800, | |
1239 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1240 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1241 | CSKYV1_ISA_E1), | |
1242 | OP16 ("cmpnei", | |
1243 | OPCODE_INFO2 (0x2a00, | |
1244 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1245 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1246 | CSKYV1_ISA_E1), | |
1247 | OP16 ("bmaski", | |
1248 | OPCODE_INFO2 (0x2c00, | |
1249 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1250 | (4_8, IMM5b_BMASKI, OPRND_SHIFT_0_BIT)), | |
1251 | CSKYV1_ISA_E1), | |
1252 | DOP16 ("divu", | |
1253 | OPCODE_INFO3 (0x2c10, | |
1254 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1255 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1256 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
1257 | OPCODE_INFO2 (0x2c10, | |
1258 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1259 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
1260 | CSKYV1_ISA_E1), | |
1261 | OP16 ("mflos", | |
1262 | OPCODE_INFO1 (0x2c20, | |
1263 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1264 | CSKY_ISA_MAC_DSP), | |
1265 | OP16 ("mfhis", | |
1266 | OPCODE_INFO1 (0x2c30, | |
1267 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1268 | CSKY_ISA_MAC_DSP), | |
1269 | OP16 ("mtlo", | |
1270 | OPCODE_INFO1 (0x2c40, | |
1271 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1272 | CSKY_ISA_MAC_DSP), | |
1273 | OP16 ("mthi", | |
1274 | OPCODE_INFO1 (0x2c50, | |
1275 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1276 | CSKY_ISA_MAC_DSP), | |
1277 | OP16 ("mflo", | |
1278 | OPCODE_INFO1 (0x2c60, | |
1279 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1280 | CSKY_ISA_MAC_DSP), | |
1281 | OP16 ("mfhi", | |
1282 | OPCODE_INFO1 (0x2c70, | |
1283 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1284 | CSKY_ISA_MAC_DSP), | |
1285 | DOP16 ("andi", | |
1286 | OPCODE_INFO3 (0x2e00, | |
1287 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1288 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1289 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1290 | OPCODE_INFO2 (0x2e00, | |
1291 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1292 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1293 | CSKYV1_ISA_E1), | |
1294 | DOP16 ("bclri", | |
1295 | OPCODE_INFO3 (0x3000, | |
1296 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1297 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1298 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1299 | OPCODE_INFO2 (0x3000, | |
1300 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1301 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1302 | CSKYV1_ISA_E1), | |
1303 | OP16 ("bgeni", | |
1304 | OPCODE_INFO2 (0x3200, | |
1305 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1306 | (4_8, IMM5b_7_31, OPRND_SHIFT_0_BIT)), | |
1307 | CSKYV1_ISA_E1), | |
1308 | OP16 ("cpwir", | |
1309 | OPCODE_INFO1 (0x3200, | |
1310 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1311 | CSKY_ISA_CP), | |
1312 | DOP16 ("divs", | |
1313 | OPCODE_INFO3 (0x3210, | |
1314 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1315 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1316 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
1317 | OPCODE_INFO2 (0x3210, | |
1318 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1319 | (NONE, REG_r1b, OPRND_SHIFT_0_BIT)), | |
1320 | CSKYV1_ISA_E1), | |
1321 | OP16 ("cprsr", | |
1322 | OPCODE_INFO1 (0x3220, | |
1323 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1324 | CSKY_ISA_CP), | |
1325 | OP16 ("cpwsr", | |
1326 | OPCODE_INFO1 (0x3230, | |
1327 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1328 | CSKY_ISA_CP), | |
1329 | DOP16 ("bseti", | |
1330 | OPCODE_INFO3 (0x3400, | |
1331 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1332 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1333 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1334 | OPCODE_INFO2 (0x3400, | |
1335 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1336 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1337 | CSKYV1_ISA_E1), | |
1338 | OP16 ("btsti", | |
1339 | OPCODE_INFO2 (0x3600, | |
1340 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1341 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1342 | CSKYV1_ISA_E1), | |
1343 | DOP16 ("rotli", | |
1344 | OPCODE_INFO3 (0x3800, | |
1345 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1346 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1347 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1348 | OPCODE_INFO2 (0x3800, | |
1349 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1350 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1351 | CSKYV1_ISA_E1), | |
1352 | DOP16 ("xsr", | |
1353 | OPCODE_INFO3 (0x3800, | |
1354 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1355 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1356 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
1357 | OPCODE_INFO1 (0x3800, | |
1358 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1359 | CSKYV1_ISA_E1), | |
1360 | DOP16 ("asrc", | |
1361 | OPCODE_INFO3 (0x3a00, | |
1362 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1363 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1364 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
1365 | OPCODE_INFO1 (0x3a00, | |
1366 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1367 | CSKYV1_ISA_E1), | |
1368 | DOP16 ("asri", | |
1369 | OPCODE_INFO3 (0x3a00, | |
1370 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1371 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1372 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1373 | OPCODE_INFO2 (0x3a00, | |
1374 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1375 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1376 | CSKYV1_ISA_E1), | |
1377 | DOP16 ("lslc", | |
1378 | OPCODE_INFO3 (0x3c00, | |
1379 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1380 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1381 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
1382 | OPCODE_INFO1 (0x3c00, | |
1383 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1384 | CSKYV1_ISA_E1), | |
1385 | DOP16 ("lsli", | |
1386 | OPCODE_INFO3 (0x3c00, | |
1387 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1388 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1389 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1390 | OPCODE_INFO2 (0x3c00, | |
1391 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1392 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1393 | CSKYV1_ISA_E1), | |
1394 | DOP16 ("lsrc", | |
1395 | OPCODE_INFO3 (0x3e00, | |
1396 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1397 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1398 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
1399 | OPCODE_INFO1 (0x3e00, | |
1400 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1401 | CSKYV1_ISA_E1), | |
1402 | DOP16 ("lsri", | |
1403 | OPCODE_INFO3 (0x3e00, | |
1404 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1405 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1406 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1407 | OPCODE_INFO2 (0x3e00, | |
1408 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1409 | (4_8, IMM5b_1_31, OPRND_SHIFT_0_BIT)), | |
1410 | CSKYV1_ISA_E1), | |
1411 | OP16 ("ldex", | |
1412 | SOPCODE_INFO2 (0x4000, | |
1413 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1414 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1415 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1416 | CSKY_ISA_MP), | |
1417 | OP16 ("ldex.w", | |
1418 | SOPCODE_INFO2 (0x4000, | |
1419 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1420 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1421 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1422 | CSKY_ISA_MP), | |
1423 | OP16 ("ldwex", | |
1424 | SOPCODE_INFO2 (0x4000, | |
1425 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1426 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1427 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1428 | CSKY_ISA_MP), | |
1429 | OP16 ("stex", | |
1430 | SOPCODE_INFO2 (0x5000, | |
1431 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1432 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1433 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1434 | CSKY_ISA_MP), | |
1435 | OP16 ("stex.w", | |
1436 | SOPCODE_INFO2 (0x5000, | |
1437 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1438 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1439 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1440 | CSKY_ISA_MP), | |
1441 | OP16 ("stwex", | |
1442 | SOPCODE_INFO2 (0x5000, | |
1443 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1444 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1445 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1446 | CSKY_ISA_MP), | |
1447 | OP16 ("omflip0", | |
1448 | OPCODE_INFO2 (0x4000, | |
1449 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1450 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1451 | CSKY_ISA_MAC), | |
1452 | OP16 ("omflip1", | |
1453 | OPCODE_INFO2 (0x4100, | |
1454 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1455 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1456 | CSKY_ISA_MAC), | |
1457 | OP16 ("omflip2", | |
1458 | OPCODE_INFO2 (0x4200, | |
1459 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1460 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1461 | CSKY_ISA_MAC), | |
1462 | OP16 ("omflip3", | |
1463 | OPCODE_INFO2 (0x4300, | |
1464 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1465 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1466 | CSKY_ISA_MAC), | |
1467 | OP16 ("muls", | |
1468 | OPCODE_INFO2 (0x5000, | |
1469 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1470 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1471 | CSKY_ISA_DSP), | |
1472 | OP16 ("mulsa", | |
1473 | OPCODE_INFO2 (0x5100, | |
1474 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1475 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1476 | CSKY_ISA_DSP), | |
1477 | OP16 ("mulss", | |
1478 | OPCODE_INFO2 (0x5200, | |
1479 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1480 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1481 | CSKY_ISA_DSP), | |
1482 | OP16 ("mulu", | |
1483 | OPCODE_INFO2 (0x5400, | |
1484 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1485 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1486 | CSKY_ISA_DSP), | |
1487 | OP16 ("mulua", | |
1488 | OPCODE_INFO2 (0x5500, | |
1489 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1490 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1491 | CSKY_ISA_DSP), | |
1492 | OP16 ("mulus", | |
1493 | OPCODE_INFO2 (0x5600, | |
1494 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1495 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1496 | CSKY_ISA_DSP), | |
1497 | OP16 ("vmulsh", | |
1498 | OPCODE_INFO2 (0x5800, | |
1499 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1500 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1501 | CSKY_ISA_DSP), | |
1502 | OP16 ("vmulsha", | |
1503 | OPCODE_INFO2 (0x5900, | |
1504 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1505 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1506 | CSKY_ISA_DSP), | |
1507 | OP16 ("vmulshs", | |
1508 | OPCODE_INFO2 (0x5a00, | |
1509 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1510 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1511 | CSKY_ISA_DSP), | |
1512 | OP16 ("vmulsw", | |
1513 | OPCODE_INFO2 (0x5c00, | |
1514 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1515 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1516 | CSKY_ISA_DSP), | |
1517 | OP16 ("vmulswa", | |
1518 | OPCODE_INFO2 (0x5d00, | |
1519 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1520 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1521 | CSKY_ISA_DSP), | |
1522 | OP16 ("vmulsws", | |
1523 | OPCODE_INFO2 (0x5e00, | |
1524 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1525 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1526 | CSKY_ISA_DSP), | |
1527 | OP16 ("movi", | |
1528 | OPCODE_INFO2 (0x6000, | |
1529 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1530 | (4_10, IMM7b, OPRND_SHIFT_0_BIT)), | |
1531 | CSKYV1_ISA_E1), | |
1532 | DOP16 ("mulsh", | |
1533 | OPCODE_INFO3 (0x6800, | |
1534 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1535 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1536 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1537 | OPCODE_INFO2 (0x6800, | |
1538 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1539 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1540 | CSKYV1_ISA_E1), | |
1541 | DOP16 ("mulsh.h", | |
1542 | OPCODE_INFO3 (0x6800, | |
1543 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1544 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
1545 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1546 | OPCODE_INFO2 (0x6800, | |
1547 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1548 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1549 | CSKYV1_ISA_E1), | |
1550 | OP16 ("mulsha", | |
1551 | OPCODE_INFO2 (0x6900, | |
1552 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1553 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1554 | CSKY_ISA_DSP), | |
1555 | OP16 ("mulshs", | |
1556 | OPCODE_INFO2 (0x6a00, | |
1557 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1558 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1559 | CSKY_ISA_DSP), | |
1560 | OP16 ("cprcr", | |
1561 | OPCODE_INFO2 (0x6b00, | |
1562 | (0_2, GREG0_7, OPRND_SHIFT_0_BIT), | |
1563 | (3_7, CPCREG, OPRND_SHIFT_0_BIT)), | |
1564 | CSKY_ISA_CP), | |
1565 | OP16 ("mulsw", | |
1566 | OPCODE_INFO2 (0x6c00, | |
1567 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1568 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1569 | CSKY_ISA_DSP), | |
1570 | OP16 ("mulswa", | |
1571 | OPCODE_INFO2 (0x6d00, | |
1572 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1573 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1574 | CSKY_ISA_DSP), | |
1575 | OP16 ("mulsws", | |
1576 | OPCODE_INFO2 (0x6e00, | |
1577 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1578 | (4_7, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1579 | CSKY_ISA_DSP), | |
1580 | OP16 ("cpwcr", | |
1581 | OPCODE_INFO2 (0x6f00, | |
1582 | (0_2, GREG0_7, OPRND_SHIFT_0_BIT), | |
1583 | (3_7, CPCREG, OPRND_SHIFT_0_BIT)), | |
1584 | CSKY_ISA_CP), | |
1585 | #undef _RELOC16 | |
1586 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM8BY4 | |
1587 | #undef _TRANSFER | |
1588 | #define _TRANSFER 1 | |
1589 | OP16 ("jmpi", | |
1590 | OPCODE_INFO1 (0x7000, | |
1591 | (0_7, OFF8b, OPRND_SHIFT_2_BIT)), | |
1592 | CSKYV1_ISA_E1), | |
1593 | #undef _TRANSFER | |
1594 | #define _TRANSFER 0 | |
1595 | OP16 ("jsri", | |
1596 | OPCODE_INFO1 (0x7f00, | |
1597 | (0_7, OFF8b, OPRND_SHIFT_2_BIT)), | |
1598 | CSKYV1_ISA_E1), | |
1599 | OP16_WITH_WORK ("lrw", | |
1600 | OPCODE_INFO2 (0x7000, | |
1601 | (8_11, REGnsplr, OPRND_SHIFT_0_BIT), | |
1602 | (0_7, CONSTANT, OPRND_SHIFT_2_BIT)), | |
1603 | CSKYV1_ISA_E1, | |
1604 | v1_work_lrw), | |
1605 | #undef _RELOC16 | |
1606 | #define _RELOC16 0 | |
1607 | DOP16 ("ld.w", | |
1608 | SOPCODE_INFO2 (0x8000, | |
1609 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1610 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1611 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
1612 | OPCODE_INFO2 (0x8000, | |
1613 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1614 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1615 | CSKYV1_ISA_E1), | |
1616 | DOP16 ("ldw", | |
1617 | SOPCODE_INFO2 (0x8000, | |
1618 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1619 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1620 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
1621 | OPCODE_INFO2 (0x8000, | |
1622 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1623 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1624 | CSKYV1_ISA_E1), | |
1625 | DOP16 ("ld", | |
1626 | SOPCODE_INFO2 (0x8000, | |
1627 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1628 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1629 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
1630 | OPCODE_INFO2 (0x8000, | |
1631 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1632 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1633 | CSKYV1_ISA_E1), | |
1634 | DOP16 ("st.w", | |
1635 | SOPCODE_INFO2 (0x9000, | |
1636 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1637 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1638 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
1639 | OPCODE_INFO2 (0x9000, | |
1640 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1641 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1642 | CSKYV1_ISA_E1), | |
1643 | DOP16 ("stw", | |
1644 | SOPCODE_INFO2 (0x9000, | |
1645 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1646 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1647 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
1648 | OPCODE_INFO2 (0x9000, | |
1649 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1650 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1651 | CSKYV1_ISA_E1), | |
1652 | DOP16 ("st", | |
1653 | SOPCODE_INFO2 (0x9000, | |
1654 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1655 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1656 | (4_7, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
1657 | OPCODE_INFO2 (0x9000, | |
1658 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1659 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1660 | CSKYV1_ISA_E1), | |
1661 | DOP16 ("ld.b", | |
1662 | SOPCODE_INFO2 (0xa000, | |
1663 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1664 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1665 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1666 | OPCODE_INFO2 (0xa000, | |
1667 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1668 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1669 | CSKYV1_ISA_E1), | |
1670 | DOP16 ("ldb", | |
1671 | SOPCODE_INFO2 (0xa000, | |
1672 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1673 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1674 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1675 | OPCODE_INFO2 (0xa000, | |
1676 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1677 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1678 | CSKYV1_ISA_E1), | |
1679 | DOP16 ("st.b", | |
1680 | SOPCODE_INFO2 (0xb000, | |
1681 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1682 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1683 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1684 | OPCODE_INFO2 (0xb000, | |
1685 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1686 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1687 | CSKYV1_ISA_E1), | |
1688 | DOP16 ("stb", | |
1689 | SOPCODE_INFO2 (0xb000, | |
1690 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1691 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1692 | (4_7, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
1693 | OPCODE_INFO2 (0xb000, | |
1694 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1695 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1696 | CSKYV1_ISA_E1), | |
1697 | DOP16 ("ld.h", | |
1698 | SOPCODE_INFO2 (0xc000, | |
1699 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1700 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1701 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
1702 | OPCODE_INFO2 (0xc000, | |
1703 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1704 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1705 | CSKYV1_ISA_E1), | |
1706 | DOP16 ("ldh", | |
1707 | SOPCODE_INFO2 (0xc000, | |
1708 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1709 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1710 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
1711 | OPCODE_INFO2 (0xc000, | |
1712 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1713 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1714 | CSKYV1_ISA_E1), | |
1715 | DOP16 ("st.h", | |
1716 | SOPCODE_INFO2 (0xd000, | |
1717 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1718 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1719 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
1720 | OPCODE_INFO2 (0xd000, | |
1721 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1722 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1723 | CSKYV1_ISA_E1), | |
1724 | DOP16 ("sth", | |
1725 | SOPCODE_INFO2 (0xd000, | |
1726 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1727 | BRACKET_OPRND ((0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1728 | (4_7, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
1729 | OPCODE_INFO2 (0xd000, | |
1730 | (8_11, GREG0_15, OPRND_SHIFT_0_BIT), | |
1731 | (0_3, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
1732 | CSKYV1_ISA_E1), | |
1733 | ||
1734 | #undef _RELOC16 | |
1735 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM11BY2 | |
1736 | OP16 ("bt", | |
1737 | OPCODE_INFO1 (0xe000, | |
1738 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
1739 | CSKYV1_ISA_E1), | |
1740 | OP16 ("bf", | |
1741 | OPCODE_INFO1 (0xe800, | |
1742 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
1743 | CSKYV1_ISA_E1), | |
1744 | #undef _TRANSFER | |
1745 | #define _TRANSFER 1 | |
1746 | OP16 ("br", | |
1747 | OPCODE_INFO1 (0xf000, | |
1748 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
1749 | CSKYV1_ISA_E1), | |
1750 | #undef _TRANSFER | |
1751 | #define _TRANSFER 0 | |
1752 | OP16 ("bsr", | |
1753 | OPCODE_INFO1 (0xf800, | |
1754 | (0_10, OFF11b, OPRND_SHIFT_1_BIT)), | |
1755 | CSKYV1_ISA_E1), | |
1756 | #undef _RELOC16 | |
1757 | #define _RELOC16 0 | |
1758 | ||
1759 | #undef _RELAX | |
1760 | #define _RELAX 1 | |
1761 | OP16 ("jbt", | |
1762 | OPCODE_INFO1 (0xe000, | |
1763 | (0_10, JBTF, OPRND_SHIFT_0_BIT)), | |
1764 | CSKYV1_ISA_E1), | |
1765 | OP16 ("jbf", | |
1766 | OPCODE_INFO1 (0xe800, | |
1767 | (0_10, JBTF, OPRND_SHIFT_0_BIT)), | |
1768 | CSKYV1_ISA_E1), | |
1769 | #undef _TRANSFER | |
1770 | #define _TRANSFER 1 | |
1771 | OP16 ("jbr", | |
1772 | OPCODE_INFO1 (0xf000, | |
1773 | (0_10, JBR, OPRND_SHIFT_0_BIT)), | |
1774 | CSKYV1_ISA_E1), | |
1775 | #undef _TRANSFER | |
1776 | #define _TRANSFER 0 | |
1777 | #undef _RELAX | |
1778 | #define _RELAX 0 | |
1779 | ||
1780 | OP16_WITH_WORK ("jbsr", | |
1781 | OPCODE_INFO1 (0xf800, | |
1782 | (0_10, JBSR, OPRND_SHIFT_0_BIT)), | |
1783 | CSKYV1_ISA_E1, | |
1784 | v1_work_jbsr), | |
1785 | ||
1786 | /* The following are aliases for other instructions. */ | |
1787 | /* rts -> jmp r15. */ | |
1788 | #undef _TRANSFER | |
1789 | #define _TRANSFER 2 | |
1790 | OP16 ("rts", | |
1791 | OPCODE_INFO0 (0x00CF), | |
1792 | CSKYV1_ISA_E1), | |
1793 | OP16 ("rte", | |
1794 | OPCODE_INFO0 (0x0002), | |
1795 | CSKYV1_ISA_E1), | |
1796 | OP16 ("rfe", | |
1797 | OPCODE_INFO0 (0x0002), | |
1798 | CSKYV1_ISA_E1), | |
1799 | #undef _TRANSFER | |
1800 | #define _TRANSFER 0 | |
1801 | ||
1802 | /* cmphs r0,r0 */ | |
1803 | OP16 ("setc", | |
1804 | OPCODE_INFO0 (0x0c00), | |
1805 | CSKYV1_ISA_E1), | |
1806 | /* cmpne r0,r0 */ | |
1807 | OP16 ("clrc", | |
1808 | OPCODE_INFO0 (0x0f00), | |
1809 | CSKYV1_ISA_E1), | |
1810 | /* cmplti rd,1 */ | |
1811 | OP16 ("tstle", | |
1812 | OPCODE_INFO1 (0x2200, | |
1813 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1814 | CSKYV1_ISA_E1), | |
1815 | /* cmplei rd,X -> cmplti rd,X+1 */ | |
1816 | OP16 ("cmplei", | |
1817 | OPCODE_INFO2 (0x2200, | |
1818 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1819 | (4_8, IMM5b, OPRND_SHIFT_0_BIT)), | |
1820 | CSKYV1_ISA_E1), | |
1821 | /* rsubi rd,0 */ | |
1822 | OP16 ("neg", | |
1823 | OPCODE_INFO1 (0x2800, | |
1824 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1825 | CSKYV1_ISA_E1), | |
1826 | /* cmpnei rd,0. */ | |
1827 | OP16 ("tstne", | |
1828 | OPCODE_INFO1 (0x2a00, | |
1829 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1830 | CSKYV1_ISA_E1), | |
1831 | /* btsti rx,31. */ | |
1832 | OP16 ("tstlt", | |
1833 | OPCODE_INFO1 (0x37f0, | |
1834 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1835 | CSKYV1_ISA_E1), | |
1836 | /* bclri rx,log2(imm). */ | |
1837 | OP16 ("mclri", | |
1838 | OPCODE_INFO2 (0x3000, | |
1839 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1840 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), | |
1841 | CSKYV1_ISA_E1), | |
1842 | /* bgeni rx,log2(imm). */ | |
1843 | OP16 ("mgeni", | |
1844 | OPCODE_INFO2 (0x3200, | |
1845 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1846 | (4_8, IMM5b_7_31_POWER, OPRND_SHIFT_0_BIT)), | |
1847 | CSKYV1_ISA_E1), | |
1848 | /* bseti rx,log2(imm). */ | |
1849 | OP16 ("mseti", | |
1850 | OPCODE_INFO2 (0x3400, | |
1851 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1852 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), | |
1853 | CSKYV1_ISA_E1), | |
1854 | /* btsti rx,log2(imm). */ | |
1855 | OP16 ("mtsti", | |
1856 | OPCODE_INFO2 (0x3600, | |
1857 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1858 | (4_8, IMM5b_POWER, OPRND_SHIFT_0_BIT)), | |
1859 | CSKYV1_ISA_E1), | |
1860 | OP16 ("rori", | |
1861 | OPCODE_INFO2 (0x3800, | |
1862 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1863 | (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
1864 | CSKYV1_ISA_E1), | |
1865 | OP16 ("rotri", | |
1866 | OPCODE_INFO2 (0x3800, | |
1867 | (0_3, GREG0_15, OPRND_SHIFT_0_BIT), | |
1868 | (4_8, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
1869 | CSKYV1_ISA_E1), | |
1870 | /* mov r0, r0. */ | |
1871 | OP16 ("nop", | |
1872 | OPCODE_INFO0 (0x1200), | |
1873 | CSKYV1_ISA_E1), | |
1874 | ||
1875 | /* Float instruction with work. */ | |
1876 | OP16_WITH_WORK ("fabss", | |
1877 | OPCODE_INFO3 (0xffe04400, | |
1878 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1879 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1880 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1881 | CSKY_ISA_FLOAT_E1, | |
1882 | v1_work_fpu_fo), | |
1883 | OP16_WITH_WORK ("fnegs", | |
1884 | OPCODE_INFO3 (0xffe04c00, | |
1885 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1886 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1887 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1888 | CSKY_ISA_FLOAT_E1, | |
1889 | v1_work_fpu_fo), | |
1890 | OP16_WITH_WORK ("fsqrts", | |
1891 | OPCODE_INFO3 (0xffe05400, | |
1892 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1893 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1894 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1895 | CSKY_ISA_FLOAT_E1, | |
1896 | v1_work_fpu_fo), | |
1897 | OP16_WITH_WORK ("frecips", | |
1898 | OPCODE_INFO3 (0xffe05c00, | |
1899 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1900 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1901 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1902 | CSKY_ISA_FLOAT_E1, | |
1903 | v1_work_fpu_fo), | |
1904 | OP16_WITH_WORK ("fadds", | |
1905 | OPCODE_INFO4 (0xffe38000, | |
1906 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1907 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1908 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1909 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1910 | CSKY_ISA_FLOAT_E1, | |
1911 | v1_work_fpu_fo), | |
1912 | OP16_WITH_WORK ("fsubs", | |
1913 | OPCODE_INFO4 (0xffe48000, | |
1914 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1915 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1916 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1917 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1918 | CSKY_ISA_FLOAT_E1, v1_work_fpu_fo), | |
1919 | OP16_WITH_WORK ("fmacs", | |
1920 | OPCODE_INFO4 (0xffe58000, | |
1921 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1922 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1923 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1924 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1925 | CSKY_ISA_FLOAT_E1, | |
1926 | v1_work_fpu_fo), | |
1927 | OP16_WITH_WORK ("fmscs", | |
1928 | OPCODE_INFO4 (0xffe68000, | |
1929 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1930 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1931 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1932 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1933 | CSKY_ISA_FLOAT_E1, | |
1934 | v1_work_fpu_fo), | |
1935 | OP16_WITH_WORK ("fmuls", | |
1936 | OPCODE_INFO4 (0xffe78000, | |
1937 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1938 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1939 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1940 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1941 | CSKY_ISA_FLOAT_E1, | |
1942 | v1_work_fpu_fo), | |
1943 | OP16_WITH_WORK ("fdivs", | |
1944 | OPCODE_INFO4 (0xffe88000, | |
1945 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1946 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1947 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1948 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1949 | CSKY_ISA_FLOAT_E1, | |
1950 | v1_work_fpu_fo), | |
1951 | OP16_WITH_WORK ("fnmacs", | |
1952 | OPCODE_INFO4 (0xffe98000, | |
1953 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1954 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1955 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1956 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1957 | CSKY_ISA_FLOAT_E1, | |
1958 | v1_work_fpu_fo), | |
1959 | OP16_WITH_WORK ("fnmscs", | |
1960 | OPCODE_INFO4 (0xffea8000, | |
1961 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1962 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1963 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1964 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1965 | CSKY_ISA_FLOAT_E1, | |
1966 | v1_work_fpu_fo), | |
1967 | OP16_WITH_WORK ("fnmuls", | |
1968 | OPCODE_INFO4 (0xffeb8000, | |
1969 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
1970 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
1971 | (10_14, FREG, OPRND_SHIFT_0_BIT), | |
1972 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1973 | CSKY_ISA_FLOAT_E1, | |
1974 | v1_work_fpu_fo), | |
1975 | OP16_WITH_WORK ("fabsd", | |
1976 | OPCODE_INFO3 (0xffe04000, | |
1977 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
1978 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
1979 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1980 | CSKY_ISA_FLOAT_E1, | |
1981 | v1_work_fpu_fo), | |
1982 | OP16_WITH_WORK ("fnegd", | |
1983 | OPCODE_INFO3 (0xffe04800, | |
1984 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
1985 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
1986 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1987 | CSKY_ISA_FLOAT_E1, | |
1988 | v1_work_fpu_fo), | |
1989 | OP16_WITH_WORK ("fsqrtd", | |
1990 | OPCODE_INFO3 (0xffe05000, | |
1991 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
1992 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
1993 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
1994 | CSKY_ISA_FLOAT_E1, | |
1995 | v1_work_fpu_fo), | |
1996 | OP16_WITH_WORK ("frecipd", | |
1997 | OPCODE_INFO3 (0xffe05800, | |
1998 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
1999 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2000 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2001 | CSKY_ISA_FLOAT_E1, | |
2002 | v1_work_fpu_fo), | |
2003 | OP16_WITH_WORK ("faddd", | |
2004 | OPCODE_INFO4 (0xffe30000, | |
2005 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2006 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2007 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2008 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2009 | CSKY_ISA_FLOAT_E1, | |
2010 | v1_work_fpu_fo), | |
2011 | OP16_WITH_WORK ("fsubd", | |
2012 | OPCODE_INFO4 (0xffe40000, | |
2013 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2014 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2015 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2016 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2017 | CSKY_ISA_FLOAT_E1, | |
2018 | v1_work_fpu_fo), | |
2019 | OP16_WITH_WORK ("fmacd", | |
2020 | OPCODE_INFO4 (0xffe50000, | |
2021 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2022 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2023 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2024 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2025 | CSKY_ISA_FLOAT_E1, | |
2026 | v1_work_fpu_fo), | |
2027 | OP16_WITH_WORK ("fmscd", | |
2028 | OPCODE_INFO4 (0xffe60000, | |
2029 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2030 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2031 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2032 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2033 | CSKY_ISA_FLOAT_E1, | |
2034 | v1_work_fpu_fo), | |
2035 | OP16_WITH_WORK ("fmuld", | |
2036 | OPCODE_INFO4 (0xffe70000, | |
2037 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2038 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2039 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2040 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2041 | CSKY_ISA_FLOAT_E1, | |
2042 | v1_work_fpu_fo), | |
2043 | OP16_WITH_WORK ("fdivd", | |
2044 | OPCODE_INFO4 (0xffe80000, | |
2045 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2046 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2047 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2048 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2049 | CSKY_ISA_FLOAT_E1, | |
2050 | v1_work_fpu_fo), | |
2051 | OP16_WITH_WORK ("fnmacd", | |
2052 | OPCODE_INFO4 (0xffe90000, | |
2053 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2054 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2055 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2056 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2057 | CSKY_ISA_FLOAT_E1, | |
2058 | v1_work_fpu_fo), | |
2059 | OP16_WITH_WORK ("fnmscd", | |
2060 | OPCODE_INFO4 (0xffea0000, | |
2061 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2062 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2063 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2064 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2065 | CSKY_ISA_FLOAT_E1, | |
2066 | v1_work_fpu_fo), | |
2067 | OP16_WITH_WORK ("fnmuld", | |
2068 | OPCODE_INFO4 (0xffeb0000, | |
2069 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2070 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2071 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2072 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2073 | CSKY_ISA_FLOAT_E1, | |
2074 | v1_work_fpu_fo), | |
2075 | OP16_WITH_WORK ("fabsm", | |
2076 | OPCODE_INFO3 (0xffe06000, | |
2077 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2078 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2079 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2080 | CSKY_ISA_FLOAT_E1, | |
2081 | v1_work_fpu_fo), | |
2082 | OP16_WITH_WORK ("fnegm", | |
2083 | OPCODE_INFO3 (0xffe06400, | |
2084 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2085 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2086 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2087 | CSKY_ISA_FLOAT_E1, | |
2088 | v1_work_fpu_fo), | |
2089 | OP16_WITH_WORK ("faddm", | |
2090 | OPCODE_INFO4 (0xffec0000, | |
2091 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2092 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2093 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2094 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2095 | CSKY_ISA_FLOAT_E1, | |
2096 | v1_work_fpu_fo), | |
2097 | OP16_WITH_WORK ("fsubm", | |
2098 | OPCODE_INFO4 (0xffec8000, | |
2099 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2100 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2101 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2102 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2103 | CSKY_ISA_FLOAT_E1, | |
2104 | v1_work_fpu_fo), | |
2105 | OP16_WITH_WORK ("fmacm", | |
2106 | OPCODE_INFO4 (0xffed8000, | |
2107 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2108 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2109 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2110 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2111 | CSKY_ISA_FLOAT_E1, | |
2112 | v1_work_fpu_fo), | |
2113 | OP16_WITH_WORK ("fmscm", | |
2114 | OPCODE_INFO4 (0xffee0000, | |
2115 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2116 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2117 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2118 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2119 | CSKY_ISA_FLOAT_E1, | |
2120 | v1_work_fpu_fo), | |
2121 | OP16_WITH_WORK ("fmulm", | |
2122 | OPCODE_INFO4 (0xffed0000, | |
2123 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2124 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2125 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2126 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2127 | CSKY_ISA_FLOAT_E1, | |
2128 | v1_work_fpu_fo), | |
2129 | OP16_WITH_WORK ("fnmacm", | |
2130 | OPCODE_INFO4 (0xffee8000, | |
2131 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2132 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2133 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2134 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2135 | CSKY_ISA_FLOAT_E1, | |
2136 | v1_work_fpu_fo), | |
2137 | OP16_WITH_WORK ("fnmscm", | |
2138 | OPCODE_INFO4 (0xffef0000, | |
2139 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2140 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2141 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2142 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2143 | CSKY_ISA_FLOAT_E1, | |
2144 | v1_work_fpu_fo), | |
2145 | OP16_WITH_WORK ("fnmulm", | |
2146 | OPCODE_INFO4 (0xffef8000, | |
2147 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2148 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2149 | (10_14, FEREG, OPRND_SHIFT_0_BIT), | |
2150 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2151 | CSKY_ISA_FLOAT_E1, | |
2152 | v1_work_fpu_fo), | |
2153 | OP16_WITH_WORK ("fcmphsd", | |
2154 | OPCODE_INFO3 (0xffe00800, | |
2155 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2156 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2157 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2158 | CSKY_ISA_FLOAT_E1, | |
2159 | v1_work_fpu_fo_fc), | |
2160 | OP16_WITH_WORK ("fcmpltd", | |
2161 | OPCODE_INFO3 (0xffe00c00, | |
2162 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2163 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2164 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2165 | CSKY_ISA_FLOAT_E1, | |
2166 | v1_work_fpu_fo_fc), | |
2167 | OP16_WITH_WORK ("fcmpned", | |
2168 | OPCODE_INFO3 (0xffe01000, | |
2169 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2170 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2171 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2172 | CSKY_ISA_FLOAT_E1, | |
2173 | v1_work_fpu_fo_fc), | |
2174 | OP16_WITH_WORK ("fcmpuod", | |
2175 | OPCODE_INFO3 (0xffe01400, | |
2176 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2177 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2178 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2179 | CSKY_ISA_FLOAT_E1, | |
2180 | v1_work_fpu_fo_fc), | |
2181 | OP16_WITH_WORK ("fcmphss", | |
2182 | OPCODE_INFO3 (0xffe01800, | |
2183 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2184 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2185 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2186 | CSKY_ISA_FLOAT_E1, | |
2187 | v1_work_fpu_fo_fc), | |
2188 | OP16_WITH_WORK ("fcmplts", | |
2189 | OPCODE_INFO3 (0xffe01c00, | |
2190 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2191 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2192 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2193 | CSKY_ISA_FLOAT_E1, | |
2194 | v1_work_fpu_fo_fc), | |
2195 | OP16_WITH_WORK ("fcmpnes", | |
2196 | OPCODE_INFO3 (0xffe02000, | |
2197 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2198 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2199 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2200 | CSKY_ISA_FLOAT_E1, | |
2201 | v1_work_fpu_fo_fc), | |
2202 | OP16_WITH_WORK ("fcmpuos", | |
2203 | OPCODE_INFO3 (0xffe02400, | |
2204 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2205 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2206 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2207 | CSKY_ISA_FLOAT_E1, | |
2208 | v1_work_fpu_fo_fc), | |
2209 | OP16_WITH_WORK ("fcmpzhsd", | |
2210 | OPCODE_INFO2 (0xffe00400, | |
2211 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2212 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2213 | CSKY_ISA_FLOAT_E1, | |
2214 | v1_work_fpu_fo_fc), | |
2215 | OP16_WITH_WORK ("fcmpzltd", | |
2216 | OPCODE_INFO2 (0xffe00480, | |
2217 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2218 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2219 | CSKY_ISA_FLOAT_E1, | |
2220 | v1_work_fpu_fo_fc), | |
2221 | OP16_WITH_WORK ("fcmpzned", | |
2222 | OPCODE_INFO2 (0xffe00500, | |
2223 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2224 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2225 | CSKY_ISA_FLOAT_E1, | |
2226 | v1_work_fpu_fo_fc), | |
2227 | OP16_WITH_WORK ("fcmpzuod", | |
2228 | OPCODE_INFO2 (0xffe00580, | |
2229 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2230 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2231 | CSKY_ISA_FLOAT_E1, | |
2232 | v1_work_fpu_fo_fc), | |
2233 | OP16_WITH_WORK ("fcmpzhss", | |
2234 | OPCODE_INFO2 (0xffe00600, | |
2235 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2236 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2237 | CSKY_ISA_FLOAT_E1, | |
2238 | v1_work_fpu_fo_fc), | |
2239 | OP16_WITH_WORK ("fcmpzlts", | |
2240 | OPCODE_INFO2 (0xffe00680, | |
2241 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2242 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2243 | CSKY_ISA_FLOAT_E1, | |
2244 | v1_work_fpu_fo_fc), | |
2245 | OP16_WITH_WORK ("fcmpznes", | |
2246 | OPCODE_INFO2 (0xffe00700, | |
2247 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2248 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2249 | CSKY_ISA_FLOAT_E1, | |
2250 | v1_work_fpu_fo_fc), | |
2251 | OP16_WITH_WORK ("fcmpzuos", | |
2252 | OPCODE_INFO2 (0xffe00780, | |
2253 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2254 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2255 | CSKY_ISA_FLOAT_E1, | |
2256 | v1_work_fpu_fo_fc), | |
2257 | OP16_WITH_WORK ("fstod", | |
2258 | OPCODE_INFO3 (0xffe02800, | |
2259 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2260 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2261 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2262 | CSKY_ISA_FLOAT_E1, | |
2263 | v1_work_fpu_fo), | |
2264 | OP16_WITH_WORK ("fdtos", | |
2265 | OPCODE_INFO3 (0xffe02c00, | |
2266 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2267 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2268 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2269 | CSKY_ISA_FLOAT_E1, | |
2270 | v1_work_fpu_fo), | |
2271 | OP16_WITH_WORK ("fsitos", | |
2272 | OPCODE_INFO3 (0xffe03400, | |
2273 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2274 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2275 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2276 | CSKY_ISA_FLOAT_E1, | |
2277 | v1_work_fpu_fo), | |
2278 | OP16_WITH_WORK ("fsitod", | |
2279 | OPCODE_INFO3 (0xffe03000, | |
2280 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2281 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2282 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2283 | CSKY_ISA_FLOAT_E1, | |
2284 | v1_work_fpu_fo), | |
2285 | OP16_WITH_WORK ("fuitos", | |
2286 | OPCODE_INFO3 (0xffe03c00, | |
2287 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2288 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2289 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2290 | CSKY_ISA_FLOAT_E1, | |
2291 | v1_work_fpu_fo), | |
2292 | OP16_WITH_WORK ("fuitod", | |
2293 | OPCODE_INFO3 (0xffe03800, | |
2294 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2295 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2296 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2297 | CSKY_ISA_FLOAT_E1, | |
2298 | v1_work_fpu_fo), | |
2299 | OP16_WITH_WORK ("fstosi", | |
2300 | OPCODE_INFO4 (0xffe10000, | |
2301 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2302 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2303 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
2304 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2305 | CSKY_ISA_FLOAT_E1, | |
2306 | v1_work_fpu_fo), | |
2307 | OP16_WITH_WORK ("fdtosi", | |
2308 | OPCODE_INFO4 (0xffe08000, | |
2309 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2310 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2311 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
2312 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2313 | CSKY_ISA_FLOAT_E1, | |
2314 | v1_work_fpu_fo), | |
2315 | OP16_WITH_WORK ("fstoui", | |
2316 | OPCODE_INFO4 (0xffe20000, | |
2317 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2318 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2319 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
2320 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2321 | CSKY_ISA_FLOAT_E1, | |
2322 | v1_work_fpu_fo), | |
2323 | OP16_WITH_WORK ("fdtoui", | |
2324 | OPCODE_INFO4 (0xffe18000, | |
2325 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2326 | (0_4, FEREG, OPRND_SHIFT_0_BIT), | |
2327 | (13_17, RM, OPRND_SHIFT_0_BIT), | |
2328 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2329 | CSKY_ISA_FLOAT_E1, | |
2330 | v1_work_fpu_fo), | |
2331 | OP16_WITH_WORK ("fmovd", | |
2332 | OPCODE_INFO3 (0xffe06800, | |
2333 | (5_9, FEREG, OPRND_SHIFT_0_BIT), | |
2334 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2335 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2336 | CSKY_ISA_FLOAT_E1, | |
2337 | v1_work_fpu_fo), | |
2338 | OP16_WITH_WORK ("fmovs", | |
2339 | OPCODE_INFO3 (0xffe06c00, | |
2340 | (5_9, FREG, OPRND_SHIFT_0_BIT), | |
2341 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
2342 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT)), | |
2343 | CSKY_ISA_FLOAT_E1, | |
2344 | v1_work_fpu_fo), | |
2345 | OP16_WITH_WORK ("fmts", | |
2346 | OPCODE_INFO2 (0x00000000, | |
2347 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
2348 | (NONE, FREG, OPRND_SHIFT_0_BIT)), | |
2349 | CSKY_ISA_FLOAT_E1, | |
2350 | v1_work_fpu_write), | |
2351 | OP16_WITH_WORK ("fmfs", | |
2352 | OPCODE_INFO2 (0x00000000, | |
2353 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
2354 | (NONE, FREG, OPRND_SHIFT_0_BIT)), | |
2355 | CSKY_ISA_FLOAT_E1, | |
2356 | v1_work_fpu_read), | |
2357 | OP16_WITH_WORK ("fmtd", | |
2358 | OPCODE_INFO2 (0x00000000, | |
2359 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
2360 | (NONE, FEREG, OPRND_SHIFT_0_BIT)), | |
2361 | CSKY_ISA_FLOAT_E1, | |
2362 | v1_work_fpu_writed), | |
2363 | OP16_WITH_WORK ("fmfd", | |
2364 | OPCODE_INFO2 (0x00000000, | |
2365 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
2366 | (NONE, FEREG, OPRND_SHIFT_0_BIT)), | |
2367 | CSKY_ISA_FLOAT_E1, | |
2368 | v1_work_fpu_readd), | |
f24ff6e9 | 2369 | {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} |
b8891f8d AJ |
2370 | }; |
2371 | ||
2372 | #undef _TRANSFER | |
2373 | #undef _RELOC16 | |
2374 | #undef _RELOC32 | |
2375 | #undef _RELAX | |
2376 | ||
2377 | /* C-SKY v2 opcodes. */ | |
2378 | const struct csky_opcode csky_v2_opcodes[] = | |
2379 | { | |
2380 | #define _TRANSFER 0 | |
2381 | #define _RELOC16 0 | |
2382 | #define _RELOC32 0 | |
2383 | #define _RELAX 0 | |
2384 | OP16 ("bkpt", | |
2385 | OPCODE_INFO0 (0x0000), | |
2386 | CSKYV2_ISA_E1), | |
2387 | OP16_WITH_WORK ("nie", | |
2388 | OPCODE_INFO0 (0x1460), | |
2389 | CSKYV2_ISA_E1, | |
2390 | v2_work_istack), | |
2391 | OP16_WITH_WORK ("nir", | |
2392 | OPCODE_INFO0 (0x1461), | |
2393 | CSKYV2_ISA_E1, | |
2394 | v2_work_istack), | |
2395 | OP16_WITH_WORK ("ipush", | |
2396 | OPCODE_INFO0 (0x1462), | |
2397 | CSKYV2_ISA_E1, | |
2398 | v2_work_istack), | |
2399 | OP16_WITH_WORK ("ipop", | |
2400 | OPCODE_INFO0 (0x1463), | |
2401 | CSKYV2_ISA_E1, | |
2402 | v2_work_istack), | |
2403 | OP16 ("bpop.h", | |
2404 | OPCODE_INFO1 (0x14a0, | |
2405 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
2406 | CSKY_ISA_JAVA), | |
2407 | OP16 ("bpop.w", | |
2408 | OPCODE_INFO1 (0x14a2, | |
2409 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
2410 | CSKY_ISA_JAVA), | |
2411 | OP16 ("bpush.h", | |
2412 | OPCODE_INFO1 (0x14e0, | |
2413 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
2414 | CSKY_ISA_JAVA), | |
2415 | OP16 ("bpush.w", | |
2416 | OPCODE_INFO1 (0x14e2, | |
2417 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
2418 | CSKY_ISA_JAVA), | |
2419 | OP32 ("bmset", | |
2420 | OPCODE_INFO0 (0xc0001020), | |
2421 | CSKY_ISA_JAVA), | |
2422 | OP32 ("bmclr", | |
2423 | OPCODE_INFO0 (0xc0001420), | |
2424 | CSKY_ISA_JAVA), | |
2425 | OP32 ("sce", | |
2426 | OPCODE_INFO1 (0xc0001820, | |
2427 | (21_24, IMM4b, OPRND_SHIFT_0_BIT)), | |
2428 | CSKY_ISA_MP), | |
2429 | OP32 ("trap", | |
2430 | OPCODE_INFO1 (0xc0002020, | |
2431 | (10_11, IMM2b, OPRND_SHIFT_0_BIT)), | |
2432 | CSKYV2_ISA_E1), | |
2433 | /* Secure/nsecure world switch. */ | |
2434 | OP32 ("wsc", | |
2435 | OPCODE_INFO0 (0xc0003c20), | |
2436 | CSKY_ISA_TRUST), | |
2437 | OP32 ("mtcr", | |
2438 | OPCODE_INFO2 (0xc0006420, | |
2439 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2440 | (0_4or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), | |
2441 | CSKYV2_ISA_E1), | |
2442 | OP32 ("mfcr", | |
2443 | OPCODE_INFO2 (0xc0006020, | |
2444 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2445 | (16_20or21_25, CTRLREG, OPRND_SHIFT_0_BIT)), | |
2446 | CSKYV2_ISA_E1), | |
2447 | #undef _TRANSFER | |
2448 | #define _TRANSFER 2 | |
2449 | OP32 ("rte", | |
2450 | OPCODE_INFO0 (0xc0004020), | |
2451 | CSKYV2_ISA_E1), | |
2452 | OP32 ("rfi", | |
2453 | OPCODE_INFO0 (0xc0004420), | |
2454 | CSKYV2_ISA_2E3), | |
2455 | #undef _TRANSFER | |
2456 | #define _TRANSFER 0 | |
2457 | OP32 ("stop", | |
2458 | OPCODE_INFO0 (0xc0004820), | |
2459 | CSKYV2_ISA_E1), | |
2460 | OP32 ("wait", | |
2461 | OPCODE_INFO0 (0xc0004c20), | |
2462 | CSKYV2_ISA_E1), | |
2463 | OP32 ("doze", | |
2464 | OPCODE_INFO0 (0xc0005020), | |
2465 | CSKYV2_ISA_E1), | |
2466 | OP32 ("we", | |
2467 | OPCODE_INFO0 (0xc0005420), | |
2468 | CSKY_ISA_MP_1E2), | |
2469 | OP32 ("se", | |
2470 | OPCODE_INFO0 (0xc0005820), | |
2471 | CSKY_ISA_MP_1E2), | |
2472 | OP32 ("psrclr", | |
2473 | OPCODE_INFO_LIST (0xc0007020, | |
2474 | (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
2475 | CSKYV2_ISA_E1), | |
2476 | OP32 ("psrset", | |
2477 | OPCODE_INFO_LIST (0xc0007420, | |
2478 | (21_25, PSR_BITS_LIST, OPRND_SHIFT_0_BIT)), | |
2479 | CSKYV2_ISA_E1), | |
2480 | DOP32 ("abs", | |
2481 | OPCODE_INFO2 (0xc4000200, | |
2482 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2483 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2484 | OPCODE_INFO1 (0xc4000200, | |
2485 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
2486 | CSKYV2_ISA_2E3), | |
2487 | OP32 ("mvc", | |
2488 | OPCODE_INFO1 (0xc4000500, | |
2489 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
2490 | CSKYV2_ISA_1E2), | |
2491 | OP32 ("incf", | |
2492 | OPCODE_INFO3 (0xc4000c20, | |
2493 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2494 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2495 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
2496 | CSKYV2_ISA_1E2), | |
2497 | OP32 ("movf", | |
2498 | OPCODE_INFO2 (0xc4000c20, | |
2499 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2500 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2501 | CSKYV2_ISA_1E2), | |
2502 | OP32 ("inct", | |
2503 | OPCODE_INFO3 (0xc4000c40, | |
2504 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2505 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2506 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
2507 | CSKYV2_ISA_1E2), | |
2508 | OP32 ("movt", | |
2509 | OPCODE_INFO2 (0xc4000c40, | |
2510 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2511 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2512 | CSKYV2_ISA_1E2), | |
2513 | OP32 ("decf", | |
2514 | OPCODE_INFO3 (0xc4000c80, | |
2515 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2516 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2517 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
2518 | CSKYV2_ISA_1E2), | |
2519 | OP32 ("dect", | |
2520 | OPCODE_INFO3 (0xc4000d00, | |
2521 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2522 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2523 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
2524 | CSKYV2_ISA_1E2), | |
2525 | OP32 ("decgt", | |
2526 | OPCODE_INFO3 (0xc4001020, | |
2527 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2528 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2529 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
2530 | CSKYV2_ISA_2E3), | |
2531 | OP32 ("declt", | |
2532 | OPCODE_INFO3 (0xc4001040, | |
2533 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2534 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2535 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
2536 | CSKYV2_ISA_2E3), | |
2537 | OP32 ("decne", | |
2538 | OPCODE_INFO3 (0xc4001080, | |
2539 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2540 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2541 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
2542 | CSKYV2_ISA_2E3), | |
2543 | OP32 ("clrf", | |
2544 | OPCODE_INFO1 (0xc4002c20, | |
2545 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2546 | CSKYV2_ISA_2E3), | |
2547 | OP32 ("clrt", | |
2548 | OPCODE_INFO1 (0xc4002c40, | |
2549 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2550 | CSKYV2_ISA_2E3), | |
2551 | DOP32 ("rotli", | |
2552 | OPCODE_INFO3 (0xc4004900, | |
2553 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2554 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2555 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
2556 | OPCODE_INFO2 (0xc4004900, | |
2557 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
2558 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
2559 | CSKYV2_ISA_1E2), | |
2560 | OP32 ("lslc", | |
2561 | OPCODE_INFO3 (0xc4004c20, | |
2562 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2563 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2564 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
2565 | CSKYV2_ISA_1E2), | |
2566 | OP32 ("lsrc", | |
2567 | OPCODE_INFO3 (0xc4004c40, | |
2568 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2569 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2570 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
2571 | CSKYV2_ISA_1E2), | |
2572 | DOP32 ("asrc", | |
2573 | OPCODE_INFO3 (0xc4004c80, | |
2574 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2575 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2576 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
2577 | OPCODE_INFO1 (0xc4004c80, | |
2578 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
2579 | CSKYV2_ISA_1E2), | |
2580 | OP32 ("xsr", | |
2581 | OPCODE_INFO3 (0xc4004d00, | |
2582 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2583 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2584 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
2585 | CSKYV2_ISA_1E2), | |
2586 | OP32 ("bgenr", | |
2587 | OPCODE_INFO2 (0xc4005040, | |
2588 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2589 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2590 | CSKYV2_ISA_2E3), | |
2591 | DOP32 ("brev", | |
2592 | OPCODE_INFO2 (0xc4006200, | |
2593 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2594 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2595 | OPCODE_INFO1 (0xc4006200, | |
2596 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
2597 | CSKYV2_ISA_2E3), | |
2598 | OP32 ("xtrb0", | |
2599 | OPCODE_INFO2 (0xc4007020, | |
2600 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2601 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2602 | CSKYV2_ISA_1E2), | |
2603 | OP32 ("xtrb1", | |
2604 | OPCODE_INFO2 (0xc4007040, | |
2605 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2606 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2607 | CSKYV2_ISA_1E2), | |
2608 | OP32 ("xtrb2", | |
2609 | OPCODE_INFO2 (0xc4007080, | |
2610 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2611 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2612 | CSKYV2_ISA_1E2), | |
2613 | OP32 ("xtrb3", | |
2614 | OPCODE_INFO2 (0xc4007100, | |
2615 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2616 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2617 | CSKYV2_ISA_1E2), | |
2618 | OP32 ("ff0", | |
2619 | OPCODE_INFO2 (0xc4007c20, | |
2620 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2621 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2622 | CSKYV2_ISA_1E2), | |
2623 | DOP32 ("ff1", | |
2624 | OPCODE_INFO2 (0xc4007c40, | |
2625 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2626 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2627 | OPCODE_INFO1 (0xc4007c40, | |
2628 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
2629 | CSKYV2_ISA_1E2), | |
2630 | OP32 ("mulu", | |
2631 | OPCODE_INFO2 (0xc4008820, | |
2632 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2633 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2634 | CSKY_ISA_DSP), | |
2635 | OP32 ("mulua", | |
2636 | OPCODE_INFO2 (0xc4008840, | |
2637 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2638 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2639 | CSKY_ISA_DSP), | |
2640 | OP32 ("mulus", | |
2641 | OPCODE_INFO2 (0xc4008880, | |
2642 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2643 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2644 | CSKY_ISA_DSP), | |
2645 | OP32 ("muls", | |
2646 | OPCODE_INFO2 (0xc4008c20, | |
2647 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2648 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2649 | CSKY_ISA_DSP), | |
2650 | OP32 ("mulsa", | |
2651 | OPCODE_INFO2 (0xc4008c40, | |
2652 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2653 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2654 | CSKY_ISA_DSP), | |
2655 | OP32 ("mulss", | |
2656 | OPCODE_INFO2 (0xc4008c80, | |
2657 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2658 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2659 | CSKY_ISA_DSP), | |
2660 | OP32 ("mulsha", | |
2661 | OPCODE_INFO2 (0xc4009040, | |
2662 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2663 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2664 | CSKY_ISA_DSP), | |
2665 | OP32 ("mulshs", | |
2666 | OPCODE_INFO2 (0xc4009080, | |
2667 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2668 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2669 | CSKY_ISA_DSP), | |
2670 | OP32 ("mulswa", | |
2671 | OPCODE_INFO2 (0xc4009440, | |
2672 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2673 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2674 | CSKY_ISA_DSP), | |
2675 | OP32 ("mulsws", | |
8119cc38 | 2676 | OPCODE_INFO2 (0xc4009500, |
b8891f8d AJ |
2677 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
2678 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2679 | CSKY_ISA_DSP), | |
2680 | OP32 ("mfhis", | |
2681 | OPCODE_INFO1 (0xc4009820, | |
2682 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
2683 | CSKY_ISA_DSP), | |
2684 | OP32 ("mflos", | |
2685 | OPCODE_INFO1 (0xc4009880, | |
2686 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
2687 | CSKY_ISA_DSP), | |
2688 | OP32 ("mvtc", | |
2689 | OPCODE_INFO0 (0xc4009a00), | |
6a1ed910 | 2690 | CSKY_ISA_DSPE60), |
b8891f8d AJ |
2691 | OP32 ("mfhi", |
2692 | OPCODE_INFO1 (0xc4009c20, | |
2693 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
2694 | CSKY_ISA_DSP), | |
2695 | OP32 ("mthi", | |
2696 | OPCODE_INFO1 (0xc4009c40, | |
2697 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2698 | CSKY_ISA_DSP), | |
2699 | OP32 ("mflo", | |
2700 | OPCODE_INFO1 (0xc4009c80, | |
2701 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
2702 | CSKY_ISA_DSP), | |
2703 | OP32 ("mtlo", | |
2704 | OPCODE_INFO1 (0xc4009d00, | |
2705 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
2706 | CSKY_ISA_DSP), | |
2707 | OP32 ("vmulsh", | |
2708 | OPCODE_INFO2 (0xc400b020, | |
2709 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2710 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2711 | CSKY_ISA_DSP_1E2), | |
2712 | OP32 ("vmulsha", | |
2713 | OPCODE_INFO2 (0xc400b040, | |
2714 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2715 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2716 | CSKY_ISA_DSP_1E2), | |
2717 | OP32 ("vmulshs", | |
2718 | OPCODE_INFO2 (0xc400b080, | |
2719 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2720 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2721 | CSKY_ISA_DSP_1E2), | |
2722 | OP32 ("vmulsw", | |
2723 | OPCODE_INFO2 (0xc400b420, | |
2724 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2725 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2726 | CSKY_ISA_DSP_1E2), | |
2727 | OP32 ("vmulswa", | |
2728 | OPCODE_INFO2 (0xc400b440, | |
2729 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2730 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2731 | CSKY_ISA_DSP_1E2), | |
2732 | OP32 ("vmulsws", | |
2733 | OPCODE_INFO2 (0xc400b480, | |
2734 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2735 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
2736 | CSKY_ISA_DSP_1E2), | |
2737 | OP32 ("ldr.b", | |
2738 | SOPCODE_INFO2 (0xd0000000, | |
2739 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2740 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2741 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2742 | CSKYV2_ISA_2E3), | |
2743 | OP32 ("ldr.bs", | |
2744 | SOPCODE_INFO2 (0xd0001000, | |
2745 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2746 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2747 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2748 | CSKYV2_ISA_2E3), | |
2749 | OP32 ("ldr.h", | |
2750 | SOPCODE_INFO2 (0xd0000400, | |
2751 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2752 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2753 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2754 | CSKYV2_ISA_2E3), | |
2755 | OP32 ("ldr.hs", | |
2756 | SOPCODE_INFO2 (0xd0001400, | |
2757 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2758 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2759 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2760 | CSKYV2_ISA_2E3), | |
2761 | OP32 ("ldr.w", | |
2762 | SOPCODE_INFO2 (0xd0000800, | |
2763 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2764 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2765 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2766 | CSKYV2_ISA_2E3), | |
2767 | OP32 ("ldm", | |
2768 | OPCODE_INFO2 (0xd0001c20, | |
2769 | (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
2770 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
2771 | CSKYV2_ISA_1E2), | |
2772 | OP32 ("ldq", | |
2773 | OPCODE_INFO2 (0xd0801c23, | |
2774 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
2775 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
2776 | CSKYV2_ISA_2E3), | |
2777 | OP32 ("str.b", | |
2778 | SOPCODE_INFO2 (0xd4000000, | |
2779 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2780 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2781 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2782 | CSKYV2_ISA_2E3), | |
2783 | OP32 ("str.h", | |
2784 | SOPCODE_INFO2 (0xd4000400, | |
2785 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2786 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2787 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2788 | CSKYV2_ISA_2E3), | |
2789 | OP32 ("str.w", | |
2790 | SOPCODE_INFO2 (0xd4000800, | |
2791 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
2792 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2793 | (5_9or21_25, AREG_WITH_LSHIFT, OPRND_SHIFT_0_BIT))), | |
2794 | CSKYV2_ISA_2E3), | |
2795 | OP32 ("stm", | |
2796 | OPCODE_INFO2 (0xd4001c20, | |
2797 | (0_4or21_25, REGLIST_DASH, OPRND_SHIFT_0_BIT), | |
2798 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
2799 | CSKYV2_ISA_1E2), | |
2800 | OP32 ("stq", | |
2801 | OPCODE_INFO2 (0xd4801c23, | |
2802 | (NONE, REGr4_r7, OPRND_SHIFT_0_BIT), | |
2803 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
2804 | CSKYV2_ISA_2E3), | |
2805 | OP32 ("ld.bs", | |
2806 | SOPCODE_INFO2 (0xd8004000, | |
2807 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2808 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2809 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
2810 | CSKYV2_ISA_1E2), | |
2811 | OP32 ("ldbs", | |
2812 | SOPCODE_INFO2 (0xd8004000, | |
2813 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2814 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2815 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
2816 | CSKYV2_ISA_1E2), | |
2817 | OP32 ("ld.hs", | |
2818 | SOPCODE_INFO2 (0xd8005000, | |
2819 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2820 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2821 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
2822 | CSKYV2_ISA_1E2), | |
2823 | OP32 ("ldhs", | |
2824 | SOPCODE_INFO2 (0xd8005000, | |
2825 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2826 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2827 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
2828 | CSKYV2_ISA_1E2), | |
2829 | OP32 ("ld.d", | |
2830 | SOPCODE_INFO2 (0xd8003000, | |
2831 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2832 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2833 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2834 | CSKYV2_ISA_3E7), | |
2835 | OP32 ("ldex.w", | |
2836 | SOPCODE_INFO2 (0xd8007000, | |
2837 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2838 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2839 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2840 | CSKY_ISA_MP_1E2), | |
2841 | OP32 ("ldexw", | |
2842 | SOPCODE_INFO2 (0xd8007000, | |
2843 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2844 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2845 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2846 | CSKY_ISA_MP_1E2), | |
2847 | OP32 ("ldex", | |
2848 | SOPCODE_INFO2 (0xd8007000, | |
2849 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2850 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2851 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2852 | CSKY_ISA_MP_1E2), | |
2853 | OP32 ("st.d", | |
2854 | SOPCODE_INFO2 (0xdc003000, | |
2855 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2856 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2857 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2858 | CSKYV2_ISA_3E7), | |
2859 | OP32 ("stex.w", | |
2860 | SOPCODE_INFO2 (0xdc007000, | |
2861 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2862 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2863 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2864 | CSKY_ISA_MP_1E2), | |
2865 | OP32 ("stexw", | |
2866 | SOPCODE_INFO2 (0xdc007000, | |
2867 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2868 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2869 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2870 | CSKY_ISA_MP_1E2), | |
2871 | OP32 ("stex", | |
2872 | SOPCODE_INFO2 (0xdc007000, | |
2873 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2874 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
2875 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
2876 | CSKY_ISA_MP_1E2), | |
2877 | DOP32 ("andi", | |
2878 | OPCODE_INFO3 (0xe4002000, | |
2879 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2880 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2881 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
2882 | OPCODE_INFO2 (0xe4002000, | |
2883 | (16_20or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), | |
2884 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
2885 | CSKYV2_ISA_1E2), | |
2886 | OP32 ("andni", | |
2887 | OPCODE_INFO3 (0xe4003000, | |
2888 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2889 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2890 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
2891 | CSKYV2_ISA_1E2), | |
2892 | OP32 ("xori", | |
2893 | OPCODE_INFO3 (0xe4004000, | |
2894 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2895 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2896 | (0_11, IMM12b, OPRND_SHIFT_0_BIT)), | |
2897 | CSKYV2_ISA_1E2), | |
2898 | OP32 ("ins", | |
2899 | OPCODE_INFO4 (0xc4005c00, | |
2900 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
2901 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
2902 | (5_9, MSB2SIZE, OPRND_SHIFT_0_BIT), | |
2903 | (0_4, LSB2SIZE, OPRND_SHIFT_0_BIT)), | |
2904 | CSKYV2_ISA_2E3), | |
2905 | #undef _TRANSFER | |
2906 | #undef _RELOC32 | |
2907 | #define _TRANSFER 1 | |
2908 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 | |
2909 | OP32 ("jmpi", | |
2910 | OPCODE_INFO1 (0xeac00000, | |
2911 | (0_15, OFF16b, OPRND_SHIFT_2_BIT)), | |
2912 | CSKYV2_ISA_2E3), | |
2913 | #undef _TRANSFER | |
2914 | #undef _RELOC32 | |
2915 | #define _TRANSFER 0 | |
2916 | #define _RELOC32 0 | |
2917 | ||
2918 | OP32 ("fadds", | |
2919 | OPCODE_INFO3 (0xf4000000, | |
2920 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2921 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2922 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2923 | CSKY_ISA_FLOAT_E1), | |
2924 | OP32 ("fsubs", | |
2925 | OPCODE_INFO3 (0xf4000020, | |
2926 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2927 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2928 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2929 | CSKY_ISA_FLOAT_E1), | |
2930 | OP32 ("fmovs", | |
2931 | OPCODE_INFO2 (0xf4000080, | |
2932 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2933 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2934 | CSKY_ISA_FLOAT_E1), | |
2935 | OP32 ("fabss", | |
2936 | OPCODE_INFO2 (0xf40000c0, | |
2937 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2938 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2939 | CSKY_ISA_FLOAT_E1), | |
2940 | OP32 ("fnegs", | |
2941 | OPCODE_INFO2 (0xf40000e0, | |
2942 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2943 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2944 | CSKY_ISA_FLOAT_E1), | |
2945 | OP32 ("fcmpzhss", | |
2946 | OPCODE_INFO1 (0xf4000100, | |
2947 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2948 | CSKY_ISA_FLOAT_E1), | |
2949 | OP32 ("fcmpzlss", | |
2950 | OPCODE_INFO1 (0xf4000120, | |
2951 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2952 | CSKY_ISA_FLOAT_E1), | |
2953 | OP32 ("fcmpznes", | |
2954 | OPCODE_INFO1 (0xf4000140, | |
2955 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2956 | CSKY_ISA_FLOAT_E1), | |
2957 | OP32 ("fcmpzuos", | |
2958 | OPCODE_INFO1 (0xf4000160, | |
2959 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
2960 | CSKY_ISA_FLOAT_E1), | |
2961 | OP32 ("fcmphss", | |
2962 | OPCODE_INFO2 (0xf4000180, | |
2963 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2964 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2965 | CSKY_ISA_FLOAT_E1), | |
2966 | OP32 ("fcmplts", | |
2967 | OPCODE_INFO2 (0xf40001a0, | |
2968 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2969 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2970 | CSKY_ISA_FLOAT_E1), | |
2971 | OP32 ("fcmpnes", | |
2972 | OPCODE_INFO2 (0xf40001c0, | |
2973 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2974 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2975 | CSKY_ISA_FLOAT_E1), | |
2976 | OP32 ("fcmpuos", | |
2977 | OPCODE_INFO2 (0xf40001e0, | |
2978 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2979 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2980 | CSKY_ISA_FLOAT_E1), | |
2981 | OP32 ("fmuls", | |
2982 | OPCODE_INFO3 (0xf4000200, | |
2983 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2984 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2985 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2986 | CSKY_ISA_FLOAT_E1), | |
2987 | OP32 ("fmacs", | |
2988 | OPCODE_INFO3 (0xf4000280, | |
2989 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2990 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2991 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2992 | CSKY_ISA_FLOAT_E1), | |
2993 | OP32 ("fmscs", | |
2994 | OPCODE_INFO3 (0xf40002a0, | |
2995 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
2996 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
2997 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
2998 | CSKY_ISA_FLOAT_E1), | |
2999 | OP32 ("fnmacs", | |
3000 | OPCODE_INFO3 (0xf40002c0, | |
3001 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3002 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3003 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3004 | CSKY_ISA_FLOAT_E1), | |
3005 | OP32 ("fnmscs", | |
3006 | OPCODE_INFO3 (0xf40002e0, | |
3007 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3008 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3009 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3010 | CSKY_ISA_FLOAT_E1), | |
3011 | OP32 ("fnmuls", | |
3012 | OPCODE_INFO3 (0xf4000220, | |
3013 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3014 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3015 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3016 | CSKY_ISA_FLOAT_E1), | |
3017 | OP32 ("fdivs", | |
3018 | OPCODE_INFO3 (0xf4000300, | |
3019 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3020 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3021 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3022 | CSKY_ISA_FLOAT_E1), | |
3023 | OP32 ("frecips", | |
3024 | OPCODE_INFO2 (0xf4000320, | |
3025 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3026 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3027 | CSKY_ISA_FLOAT_E1), | |
3028 | OP32 ("fsqrts", | |
3029 | OPCODE_INFO2 (0xf4000340, | |
3030 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3031 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3032 | CSKY_ISA_FLOAT_E1), | |
3033 | OP32 ("faddd", | |
3034 | OPCODE_INFO3 (0xf4000800, | |
3035 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3036 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3037 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3038 | CSKY_ISA_FLOAT_1E2), | |
3039 | OP32 ("fsubd", | |
3040 | OPCODE_INFO3 (0xf4000820, | |
3041 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3042 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3043 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3044 | CSKY_ISA_FLOAT_1E2), | |
3045 | OP32 ("fmovd", | |
3046 | OPCODE_INFO2 (0xf4000880, | |
3047 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3048 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3049 | CSKY_ISA_FLOAT_1E2), | |
3050 | OP32 ("fabsd", | |
3051 | OPCODE_INFO2 (0xf40008c0, | |
3052 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3053 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3054 | CSKY_ISA_FLOAT_1E2), | |
3055 | OP32 ("fnegd", | |
3056 | OPCODE_INFO2 (0xf40008e0, | |
3057 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3058 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3059 | CSKY_ISA_FLOAT_1E2), | |
3060 | OP32 ("fcmpzhsd", | |
3061 | OPCODE_INFO1 (0xf4000900, | |
3062 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3063 | CSKY_ISA_FLOAT_1E2), | |
3064 | OP32 ("fcmpzlsd", | |
3065 | OPCODE_INFO1 (0xf4000920, | |
3066 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3067 | CSKY_ISA_FLOAT_1E2), | |
3068 | OP32 ("fcmpzned", | |
3069 | OPCODE_INFO1 (0xf4000940, | |
3070 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3071 | CSKY_ISA_FLOAT_1E2), | |
3072 | OP32 ("fcmpzuod", | |
3073 | OPCODE_INFO1 (0xf4000960, | |
3074 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3075 | CSKY_ISA_FLOAT_1E2), | |
3076 | OP32 ("fcmphsd", | |
3077 | OPCODE_INFO2 (0xf4000980, | |
3078 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3079 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3080 | CSKY_ISA_FLOAT_1E2), | |
3081 | OP32 ("fcmpltd", | |
3082 | OPCODE_INFO2 (0xf40009a0, | |
3083 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3084 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3085 | CSKY_ISA_FLOAT_1E2), | |
3086 | OP32 ("fcmpned", | |
3087 | OPCODE_INFO2 (0xf40009c0, | |
3088 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3089 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3090 | CSKY_ISA_FLOAT_1E2), | |
3091 | OP32 ("fcmpuod", | |
3092 | OPCODE_INFO2 (0xf40009e0, | |
3093 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3094 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3095 | CSKY_ISA_FLOAT_1E2), | |
3096 | OP32 ("fmuld", | |
3097 | OPCODE_INFO3 (0xf4000a00, | |
3098 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3099 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3100 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3101 | CSKY_ISA_FLOAT_1E2), | |
3102 | OP32 ("fnmuld", | |
3103 | OPCODE_INFO3 (0xf4000a20, | |
3104 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3105 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3106 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3107 | CSKY_ISA_FLOAT_1E2), | |
3108 | OP32 ("fmacd", | |
3109 | OPCODE_INFO3 (0xf4000a80, | |
3110 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3111 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3112 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3113 | CSKY_ISA_FLOAT_1E2), | |
3114 | OP32 ("fmscd", | |
3115 | OPCODE_INFO3 (0xf4000aa0, | |
3116 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3117 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3118 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3119 | CSKY_ISA_FLOAT_1E2), | |
3120 | OP32 ("fnmacd", | |
3121 | OPCODE_INFO3 (0xf4000ac0, | |
3122 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3123 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3124 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3125 | CSKY_ISA_FLOAT_1E2), | |
3126 | OP32 ("fnmscd", | |
3127 | OPCODE_INFO3 (0xf4000ae0, | |
3128 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3129 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3130 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3131 | CSKY_ISA_FLOAT_1E2), | |
3132 | OP32 ("fdivd", | |
3133 | OPCODE_INFO3 (0xf4000b00, | |
3134 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3135 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3136 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3137 | CSKY_ISA_FLOAT_1E2), | |
3138 | OP32 ("frecipd", | |
3139 | OPCODE_INFO2 (0xf4000b20, | |
3140 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3141 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3142 | CSKY_ISA_FLOAT_1E2), | |
3143 | OP32 ("fsqrtd", | |
3144 | OPCODE_INFO2 (0xf4000b40, | |
3145 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3146 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3147 | CSKY_ISA_FLOAT_1E2), | |
3148 | OP32 ("faddm", | |
3149 | OPCODE_INFO3 (0xf4001000, | |
3150 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3151 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3152 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3153 | CSKY_ISA_FLOAT_1E2), | |
3154 | OP32 ("fsubm", | |
3155 | OPCODE_INFO3 (0xf4001020, | |
3156 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3157 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3158 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3159 | CSKY_ISA_FLOAT_1E2), | |
3160 | OP32 ("fmovm", | |
3161 | OPCODE_INFO2 (0xf4001080, | |
3162 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3163 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3164 | CSKY_ISA_FLOAT_1E2), | |
3165 | OP32 ("fabsm", | |
3166 | OPCODE_INFO2 (0xf40010c0, | |
3167 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3168 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3169 | CSKY_ISA_FLOAT_1E2), | |
3170 | OP32 ("fnegm", | |
3171 | OPCODE_INFO2 (0xf40010e0, | |
3172 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3173 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3174 | CSKY_ISA_FLOAT_1E2), | |
3175 | OP32 ("fmulm", | |
3176 | OPCODE_INFO3 (0xf4001200, | |
3177 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3178 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3179 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3180 | CSKY_ISA_FLOAT_1E2), | |
3181 | OP32 ("fnmulm", | |
3182 | OPCODE_INFO3 (0xf4001220, | |
3183 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3184 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3185 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3186 | CSKY_ISA_FLOAT_1E2), | |
3187 | OP32 ("fmacm", | |
3188 | OPCODE_INFO3 (0xf4001280, | |
3189 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3190 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3191 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3192 | CSKY_ISA_FLOAT_1E2), | |
3193 | OP32 ("fmscm", | |
3194 | OPCODE_INFO3 (0xf40012a0, | |
3195 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3196 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3197 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3198 | CSKY_ISA_FLOAT_1E2), | |
3199 | OP32 ("fnmacm", | |
3200 | OPCODE_INFO3 (0xf40012c0, | |
3201 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3202 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3203 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3204 | CSKY_ISA_FLOAT_1E2), | |
3205 | OP32 ("fnmscm", | |
3206 | OPCODE_INFO3 (0xf40012e0, | |
3207 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3208 | (16_19, FREG, OPRND_SHIFT_0_BIT), | |
3209 | (21_24, FREG, OPRND_SHIFT_0_BIT)), | |
3210 | CSKY_ISA_FLOAT_1E2), | |
3211 | OP32 ("fstosi.rn", | |
3212 | OPCODE_INFO2 (0xf4001800, | |
3213 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3214 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3215 | CSKY_ISA_FLOAT_E1), | |
3216 | OP32 ("fstosi.rz", | |
3217 | OPCODE_INFO2 (0xf4001820, | |
3218 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3219 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3220 | CSKY_ISA_FLOAT_E1), | |
3221 | OP32 ("fstosi.rpi", | |
3222 | OPCODE_INFO2 (0xf4001840, | |
3223 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3224 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3225 | CSKY_ISA_FLOAT_E1), | |
3226 | OP32 ("fstosi.rni", | |
3227 | OPCODE_INFO2 (0xf4001860, | |
3228 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3229 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3230 | CSKY_ISA_FLOAT_E1), | |
3231 | OP32 ("fstoui.rn", | |
3232 | OPCODE_INFO2 (0xf4001880, | |
3233 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3234 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3235 | CSKY_ISA_FLOAT_E1), | |
3236 | OP32 ("fstoui.rz", | |
3237 | OPCODE_INFO2 (0xf40018a0, | |
3238 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3239 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3240 | CSKY_ISA_FLOAT_E1), | |
3241 | OP32 ("fstoui.rpi", | |
3242 | OPCODE_INFO2 (0xf40018c0, | |
3243 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3244 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3245 | CSKY_ISA_FLOAT_E1), | |
3246 | OP32 ("fstoui.rni", | |
3247 | OPCODE_INFO2 (0xf40018e0, | |
3248 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3249 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3250 | CSKY_ISA_FLOAT_E1), | |
3251 | OP32 ("fdtosi.rn", | |
3252 | OPCODE_INFO2 (0xf4001900, | |
3253 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3254 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3255 | CSKY_ISA_FLOAT_1E2), | |
3256 | OP32 ("fdtosi.rz", | |
3257 | OPCODE_INFO2 (0xf4001920, | |
3258 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3259 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3260 | CSKY_ISA_FLOAT_1E2), | |
3261 | OP32 ("fdtosi.rpi", | |
3262 | OPCODE_INFO2 (0xf4001940, | |
3263 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3264 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3265 | CSKY_ISA_FLOAT_1E2), | |
3266 | OP32 ("fdtosi.rni", | |
3267 | OPCODE_INFO2 (0xf4001960, | |
3268 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3269 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3270 | CSKY_ISA_FLOAT_1E2), | |
3271 | OP32 ("fdtoui.rn", | |
3272 | OPCODE_INFO2 (0xf4001980, | |
3273 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3274 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3275 | CSKY_ISA_FLOAT_1E2), | |
3276 | OP32 ("fdtoui.rz", | |
3277 | OPCODE_INFO2 (0xf40019a0, | |
3278 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3279 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3280 | CSKY_ISA_FLOAT_1E2), | |
3281 | OP32 ("fdtoui.rpi", | |
3282 | OPCODE_INFO2 (0xf40019c0, | |
3283 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3284 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3285 | CSKY_ISA_FLOAT_1E2), | |
3286 | OP32 ("fdtoui.rni", | |
3287 | OPCODE_INFO2 (0xf40019e0, | |
3288 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3289 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3290 | CSKY_ISA_FLOAT_1E2), | |
3291 | OP32 ("fsitos", | |
3292 | OPCODE_INFO2 (0xf4001a00, | |
3293 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3294 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3295 | CSKY_ISA_FLOAT_E1), | |
3296 | OP32 ("fuitos", | |
3297 | OPCODE_INFO2 (0xf4001a20, | |
3298 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3299 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3300 | CSKY_ISA_FLOAT_E1), | |
3301 | OP32 ("fsitod", | |
3302 | OPCODE_INFO2 (0xf4001a80, | |
3303 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3304 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3305 | CSKY_ISA_FLOAT_1E2), | |
3306 | OP32 ("fuitod", | |
3307 | OPCODE_INFO2 (0xf4001aa0, | |
3308 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3309 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3310 | CSKY_ISA_FLOAT_1E2), | |
3311 | OP32 ("fdtos", | |
3312 | OPCODE_INFO2 (0xf4001ac0, | |
3313 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3314 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3315 | CSKY_ISA_FLOAT_1E2), | |
3316 | OP32 ("fstod", | |
3317 | OPCODE_INFO2 (0xf4001ae0, | |
3318 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3319 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3320 | CSKY_ISA_FLOAT_1E2), | |
3321 | OP32 ("fmfvrh", | |
3322 | OPCODE_INFO2 (0xf4001b00, | |
3323 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3324 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3325 | CSKY_ISA_FLOAT_1E2), | |
3326 | OP32 ("fmfvrl", | |
3327 | OPCODE_INFO2 (0xf4001b20, | |
3328 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3329 | (16_19, FREG, OPRND_SHIFT_0_BIT)), | |
3330 | CSKY_ISA_FLOAT_E1), | |
3331 | OP32 ("fmtvrh", | |
3332 | OPCODE_INFO2 (0xf4001b40, | |
3333 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3334 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3335 | CSKY_ISA_FLOAT_1E2), | |
3336 | OP32 ("fmtvrl", | |
3337 | OPCODE_INFO2 (0xf4001b60, | |
3338 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3339 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3340 | CSKY_ISA_FLOAT_E1), | |
3341 | OP32 ("flds", | |
3342 | SOPCODE_INFO2 (0xf4002000, | |
3343 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3344 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3345 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
3346 | CSKY_ISA_FLOAT_E1), | |
3347 | OP32 ("fldd", | |
3348 | SOPCODE_INFO2 (0xf4002100, | |
3349 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3350 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3351 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
3352 | CSKY_ISA_FLOAT_1E2), | |
3353 | OP32 ("fldm", | |
3354 | SOPCODE_INFO2 (0xf4002200, | |
3355 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3356 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3357 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
3358 | CSKY_ISA_FLOAT_1E2), | |
3359 | OP32 ("fsts", | |
3360 | SOPCODE_INFO2 (0xf4002400, | |
3361 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3362 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3363 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
3364 | CSKY_ISA_FLOAT_E1), | |
3365 | OP32 ("fstd", | |
3366 | SOPCODE_INFO2 (0xf4002500, | |
3367 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3368 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3369 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_2_BIT))), | |
3370 | CSKY_ISA_FLOAT_1E2), | |
3371 | OP32 ("fstm", | |
3372 | SOPCODE_INFO2 (0xf4002600, | |
3373 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3374 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3375 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
3376 | CSKY_ISA_FLOAT_1E2), | |
3377 | OP32 ("fldrs", | |
3378 | SOPCODE_INFO2 (0xf4002800, | |
3379 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3380 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3381 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
3382 | CSKY_ISA_FLOAT_E1), | |
3383 | OP32 ("fstrs", | |
3384 | SOPCODE_INFO2 (0xf4002c00, | |
3385 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3386 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3387 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
3388 | CSKY_ISA_FLOAT_E1), | |
3389 | OP32 ("fldrd", | |
3390 | SOPCODE_INFO2 (0xf4002900, | |
3391 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3392 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3393 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
3394 | CSKY_ISA_FLOAT_1E2), | |
3395 | OP32 ("fldrm", | |
3396 | SOPCODE_INFO2 (0xf4002a00, | |
3397 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3398 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3399 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
3400 | CSKY_ISA_FLOAT_1E2), | |
3401 | OP32 ("fstrd", | |
3402 | SOPCODE_INFO2 (0xf4002d00, | |
3403 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3404 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3405 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
3406 | CSKY_ISA_FLOAT_1E2), | |
3407 | OP32 ("fstrm", | |
3408 | SOPCODE_INFO2 (0xf4002e00, | |
3409 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
3410 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3411 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
3412 | CSKY_ISA_FLOAT_1E2), | |
3413 | OP32 ("fldms", | |
3414 | OPCODE_INFO2 (0xf4003000, | |
3415 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
3416 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
3417 | CSKY_ISA_FLOAT_E1), | |
3418 | OP32 ("fldmd", | |
3419 | OPCODE_INFO2 (0xf4003100, | |
3420 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
3421 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
3422 | CSKY_ISA_FLOAT_1E2), | |
3423 | OP32 ("fldmm", | |
3424 | OPCODE_INFO2 (0xf4003200, | |
3425 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
3426 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
3427 | CSKY_ISA_FLOAT_1E2), | |
3428 | OP32 ("fstms", | |
3429 | OPCODE_INFO2 (0xf4003400, | |
3430 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
3431 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
3432 | CSKY_ISA_FLOAT_E1), | |
3433 | OP32 ("fstmd", | |
3434 | OPCODE_INFO2 (0xf4003500, | |
3435 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
3436 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
3437 | CSKY_ISA_FLOAT_1E2), | |
3438 | OP32 ("fstmm", | |
3439 | OPCODE_INFO2 (0xf4003600, | |
3440 | (0_3or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
3441 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
3442 | CSKY_ISA_FLOAT_1E2), | |
b8891f8d AJ |
3443 | DOP32 ("idly", |
3444 | OPCODE_INFO1 (0xc0001c20, | |
3445 | (21_25, OIMM5b_IDLY, OPRND_SHIFT_0_BIT)), | |
3446 | OPCODE_INFO0 (0xc0601c20), | |
3447 | CSKYV2_ISA_E1), | |
3448 | ||
3449 | #undef _RELOC32 | |
3450 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM18BY2 | |
3451 | OP32 ("grs", | |
3452 | OPCODE_INFO2 (0xcc0c0000, | |
3453 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
3454 | (0_17, IMM_OFF18b, OPRND_SHIFT_1_BIT)), | |
3455 | CSKYV2_ISA_2E3), | |
3456 | #undef _RELOC32 | |
3457 | #define _RELOC32 0 | |
3458 | DOP32 ("ixh", | |
3459 | OPCODE_INFO3 (0xc4000820, | |
3460 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3461 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3462 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3463 | OPCODE_INFO2 (0xc4000820, | |
3464 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3465 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3466 | CSKYV2_ISA_1E2), | |
3467 | DOP32 ("ixw", | |
3468 | OPCODE_INFO3 (0xc4000840, | |
3469 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3470 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3471 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3472 | OPCODE_INFO2 (0xc4000840, | |
3473 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3474 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3475 | CSKYV2_ISA_1E2), | |
3476 | OP32 ("ixd", | |
3477 | OPCODE_INFO3 (0xc4000880, | |
3478 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3479 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3480 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3481 | CSKYV2_ISA_2E3), | |
3482 | DOP32 ("divu", | |
3483 | OPCODE_INFO3 (0xc4008020, | |
3484 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3485 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3486 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3487 | OPCODE_INFO2 (0xc4008020, | |
3488 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3489 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3490 | CSKYV2_ISA_2E3), | |
3491 | DOP32 ("divs", | |
3492 | OPCODE_INFO3 (0xc4008040, | |
3493 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3494 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3495 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3496 | OPCODE_INFO2 (0xc4008040, | |
3497 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3498 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3499 | CSKYV2_ISA_2E3), | |
3500 | OP32 ("pldr", | |
3501 | SOPCODE_INFO1 (0xd8006000, | |
3502 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3503 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
3504 | CSKY_ISA_CACHE), | |
3505 | OP32 ("pldw", | |
3506 | SOPCODE_INFO1 (0xdc006000, | |
3507 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
3508 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
3509 | CSKY_ISA_CACHE), | |
3510 | OP32 ("cprgr", | |
3511 | SOPCODE_INFO2 (0xfc000000, | |
3512 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3513 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
3514 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
3515 | CSKYV2_ISA_E1), | |
3516 | OP32 ("cpwgr", | |
3517 | SOPCODE_INFO2 (0xfc001000, | |
3518 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3519 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
3520 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
3521 | CSKYV2_ISA_E1), | |
3522 | OP32 ("cprcr", | |
3523 | SOPCODE_INFO2 (0xfc002000, | |
3524 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3525 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
3526 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
3527 | CSKYV2_ISA_E1), | |
3528 | OP32 ("cpwcr", | |
3529 | SOPCODE_INFO2 (0xfc003000, | |
3530 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3531 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
3532 | (0_11 , IMM12b, OPRND_SHIFT_0_BIT))), | |
3533 | CSKYV2_ISA_E1), | |
3534 | OP32 ("cprc", | |
3535 | SOPCODE_INFO1 (0xfc004000, | |
3536 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
3537 | (0_11, IMM12b, OPRND_SHIFT_0_BIT))), | |
3538 | CSKYV2_ISA_E1), | |
3539 | OP32 ("cpop", | |
3540 | SOPCODE_INFO1 (0xfc008000, | |
3541 | ABRACKET_OPRND ((21_25, IMM5b, OPRND_SHIFT_0_BIT), | |
3542 | (0_14or16_20 , IMM15b, OPRND_SHIFT_0_BIT))), | |
3543 | CSKYV2_ISA_E1), | |
3544 | ||
3545 | OP16_OP32 ("push", | |
3546 | OPCODE_INFO_LIST (0x14c0, | |
3547 | (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
3548 | CSKYV2_ISA_E1, | |
3549 | OPCODE_INFO_LIST (0xebe00000, | |
3550 | (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
3551 | CSKYV2_ISA_2E3), | |
3552 | #undef _TRANSFER | |
3553 | #define _TRANSFER 2 | |
3554 | OP16_OP32 ("pop", | |
3555 | OPCODE_INFO_LIST (0x1480, | |
3556 | (0_4, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
3557 | CSKYV2_ISA_E1, | |
3558 | OPCODE_INFO_LIST (0xebc00000, | |
3559 | (0_8, REGLIST_DASH_COMMA, OPRND_SHIFT_0_BIT)), | |
3560 | CSKYV2_ISA_2E3), | |
3561 | #undef _TRANSFER | |
3562 | #define _TRANSFER 0 | |
3563 | OP16_OP32 ("movi", | |
3564 | OPCODE_INFO2 (0x3000, | |
3565 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3566 | (0_7, IMM8b, OPRND_SHIFT_0_BIT)), | |
3567 | CSKYV2_ISA_E1, | |
3568 | OPCODE_INFO2 (0xea000000, | |
3569 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3570 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), | |
3571 | CSKYV2_ISA_1E2), | |
3572 | /* bmaski will transfer to movi when imm < 17. */ | |
3573 | OP16_OP32 ("bmaski", | |
3574 | OPCODE_INFO2 (0x3000, | |
3575 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3576 | (0_7, IMM8b_BMASKI, OPRND_SHIFT_0_BIT)), | |
3577 | CSKYV2_ISA_1E2, | |
3578 | OPCODE_INFO2 (0xc4005020, | |
3579 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3580 | (21_25, OIMM5b_BMASKI, OPRND_SHIFT_0_BIT)), | |
3581 | CSKYV2_ISA_1E2), | |
3582 | OP16_OP32 ("cmphsi", | |
3583 | OPCODE_INFO2 (0x3800, | |
3584 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3585 | (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), | |
3586 | CSKYV2_ISA_E1, | |
3587 | OPCODE_INFO2 (0xeb000000, | |
3588 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3589 | (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), | |
3590 | CSKYV2_ISA_1E2), | |
3591 | OP16_OP32 ("cmplti", | |
3592 | OPCODE_INFO2 (0x3820, | |
3593 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3594 | (0_4, OIMM5b, OPRND_SHIFT_0_BIT)), | |
3595 | CSKYV2_ISA_E1, | |
3596 | OPCODE_INFO2 (0xeb200000, | |
3597 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3598 | (0_15, OIMM16b, OPRND_SHIFT_0_BIT)), | |
3599 | CSKYV2_ISA_1E2), | |
3600 | OP16_OP32 ("cmpnei", | |
3601 | OPCODE_INFO2 (0x3840, | |
3602 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3603 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3604 | CSKYV2_ISA_E1, | |
3605 | OPCODE_INFO2 (0xeb400000, | |
3606 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3607 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), | |
3608 | CSKYV2_ISA_1E2), | |
3609 | #undef _TRANSFER | |
3610 | #define _TRANSFER 1 | |
3611 | OP16_OP32 ("jmpix", | |
3612 | OPCODE_INFO2 (0x38e0, | |
3613 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3614 | (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), | |
3615 | CSKY_ISA_JAVA, | |
3616 | OPCODE_INFO2 (0xe9e00000, | |
3617 | (16_20, GREG0_7, OPRND_SHIFT_0_BIT), | |
3618 | (0_1, IMM2b_JMPIX, OPRND_SHIFT_0_BIT)), | |
3619 | CSKY_ISA_JAVA), | |
3620 | #undef _TRANSFER | |
3621 | #define _TRANSFER 0 | |
3622 | DOP16_DOP32 ("bclri", | |
3623 | OPCODE_INFO3 (0x3880, | |
3624 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3625 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3626 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3627 | OPCODE_INFO2 (0x3880, | |
3628 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3629 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3630 | CSKYV2_ISA_E1, | |
3631 | OPCODE_INFO3 (0xc4002820, | |
3632 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3633 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3634 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3635 | OPCODE_INFO2 (0xc4002820, | |
3636 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3637 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3638 | CSKYV2_ISA_1E2), | |
3639 | DOP16_DOP32 ("bseti", | |
3640 | OPCODE_INFO3 (0x38a0, | |
3641 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3642 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3643 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3644 | OPCODE_INFO2 (0x38a0, | |
3645 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3646 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3647 | CSKYV2_ISA_E1, | |
3648 | OPCODE_INFO3 (0xc4002840, | |
3649 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3650 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3651 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3652 | OPCODE_INFO2 (0xc4002840, | |
3653 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3654 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3655 | CSKYV2_ISA_1E2), | |
3656 | OP16_OP32_WITH_WORK ("btsti", | |
3657 | OPCODE_INFO2 (0x38c0, | |
3658 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3659 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3660 | CSKYV2_ISA_E1, | |
3661 | OPCODE_INFO2 (0xc4002880, | |
3662 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3663 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3664 | CSKYV2_ISA_1E2, v2_work_btsti), | |
3665 | DOP16_DOP32 ("lsli", | |
3666 | OPCODE_INFO3 (0x4000, | |
3667 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
3668 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3669 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3670 | OPCODE_INFO2 (0x4000, | |
3671 | (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), | |
3672 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3673 | CSKYV2_ISA_E1, | |
3674 | OPCODE_INFO3 (0xc4004820, | |
3675 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3676 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3677 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3678 | OPCODE_INFO2 (0xc4004820, | |
3679 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3680 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3681 | CSKYV2_ISA_1E2), | |
3682 | DOP16_DOP32 ("lsri", | |
3683 | OPCODE_INFO3 (0x4800, | |
3684 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
3685 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3686 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3687 | OPCODE_INFO2 (0x4800, | |
3688 | (5_7or8_10, DUP_GREG0_7, OPRND_SHIFT_0_BIT), | |
3689 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3690 | CSKYV2_ISA_E1, | |
3691 | OPCODE_INFO3 (0xc4004840, | |
3692 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3693 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3694 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3695 | OPCODE_INFO2 (0xc4004840, | |
3696 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3697 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3698 | CSKYV2_ISA_1E2), | |
3699 | OP16_OP32 ("asri", | |
3700 | OPCODE_INFO3 (0x5000, | |
3701 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
3702 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
3703 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
3704 | CSKYV2_ISA_E1, | |
3705 | OPCODE_INFO3 (0xc4004880, | |
3706 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3707 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3708 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
3709 | CSKYV2_ISA_1E2), | |
3710 | DOP16_DOP32 ("addc", | |
3711 | OPCODE_INFO2 (0x6001, | |
3712 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3713 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3714 | OPCODE_INFO3 (0x6001, | |
3715 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3716 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
3717 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
3718 | CSKYV2_ISA_E1, | |
3719 | OPCODE_INFO3 (0xc4000040, | |
3720 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3721 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3722 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3723 | OPCODE_INFO2 (0xc4000040, | |
3724 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3725 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3726 | CSKYV2_ISA_1E2), | |
3727 | DOP16_DOP32 ("subc", | |
3728 | OPCODE_INFO2 (0x6003, | |
3729 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3730 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3731 | OPCODE_INFO3 (0x6003, | |
3732 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3733 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3734 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3735 | CSKYV2_ISA_E1, | |
3736 | OPCODE_INFO3 (0xc4000100, | |
3737 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3738 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3739 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3740 | OPCODE_INFO2 (0xc4000100, | |
3741 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3742 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3743 | CSKYV2_ISA_1E2), | |
3744 | OP16_OP32 ("cmphs", | |
3745 | OPCODE_INFO2 (0x6400, | |
3746 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
3747 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3748 | CSKYV2_ISA_E1, | |
3749 | OPCODE_INFO2 (0xc4000420, | |
3750 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3751 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3752 | CSKYV2_ISA_2E3), | |
3753 | OP16_OP32 ("cmplt", | |
3754 | OPCODE_INFO2 (0x6401, | |
3755 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
3756 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3757 | CSKYV2_ISA_E1, | |
3758 | OPCODE_INFO2 (0xc4000440, | |
3759 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3760 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3761 | CSKYV2_ISA_2E3), | |
3762 | OP16_OP32 ("cmpne", | |
3763 | OPCODE_INFO2 (0x6402, | |
3764 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
3765 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3766 | CSKYV2_ISA_E1, | |
3767 | OPCODE_INFO2 (0xc4000480, | |
3768 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3769 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3770 | CSKYV2_ISA_2E3), | |
3771 | OP16_OP32 ("mvcv", | |
3772 | OPCODE_INFO1 (0x6403, | |
3773 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3774 | CSKYV2_ISA_E1, | |
3775 | OPCODE_INFO1 (0xc4000600, | |
3776 | (0_4, AREG, OPRND_SHIFT_0_BIT)), | |
3777 | CSKYV2_ISA_2E3), | |
3778 | DOP16_DOP32 ("and", | |
3779 | OPCODE_INFO2 (0x6800, | |
3780 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3781 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3782 | OPCODE_INFO3 (0x6800, | |
3783 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3784 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
3785 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
3786 | CSKYV2_ISA_E1, | |
3787 | OPCODE_INFO3 (0xc4002020, | |
3788 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3789 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3790 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3791 | OPCODE_INFO2 (0xc4002020, | |
3792 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3793 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3794 | CSKYV2_ISA_1E2), | |
3795 | DOP16_DOP32 ("andn", | |
3796 | OPCODE_INFO2 (0x6801, | |
3797 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3798 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3799 | OPCODE_INFO3 (0x6801, | |
3800 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3801 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3802 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3803 | CSKYV2_ISA_E1, | |
3804 | OPCODE_INFO3 (0xc4002040, | |
3805 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3806 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3807 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3808 | OPCODE_INFO2 (0xc4002040, | |
3809 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3810 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3811 | CSKYV2_ISA_1E2), | |
3812 | OP16_OP32 ("tst", | |
3813 | OPCODE_INFO2 (0x6802, | |
3814 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT), | |
3815 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3816 | CSKYV2_ISA_E1, | |
3817 | OPCODE_INFO2 (0xc4002080, | |
3818 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3819 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3820 | CSKYV2_ISA_2E3), | |
3821 | OP16_OP32 ("tstnbz", | |
3822 | OPCODE_INFO1 (0x6803, | |
3823 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3824 | CSKYV2_ISA_E1, | |
3825 | OPCODE_INFO1 (0xc4002100, | |
3826 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3827 | CSKYV2_ISA_2E3), | |
3828 | DOP16_DOP32 ("or", | |
3829 | OPCODE_INFO2 (0x6c00, | |
3830 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3831 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3832 | OPCODE_INFO3 (0x6c00, | |
3833 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3834 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
3835 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
3836 | CSKYV2_ISA_E1, | |
3837 | OPCODE_INFO3 (0xc4002420, | |
3838 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3839 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3840 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3841 | OPCODE_INFO2 (0xc4002420, | |
3842 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3843 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3844 | CSKYV2_ISA_1E2), | |
3845 | DOP16_DOP32 ("xor", | |
3846 | OPCODE_INFO2 (0x6c01, | |
3847 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3848 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3849 | OPCODE_INFO3 (0x6c01, | |
3850 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3851 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
3852 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
3853 | CSKYV2_ISA_E1, | |
3854 | OPCODE_INFO3 (0xc4002440, | |
3855 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3856 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3857 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3858 | OPCODE_INFO2 (0xc4002440, | |
3859 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3860 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3861 | CSKYV2_ISA_1E2), | |
3862 | DOP16_DOP32 ("nor", | |
3863 | OPCODE_INFO2 (0x6c02, | |
3864 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3865 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3866 | OPCODE_INFO3 (0x6c02, | |
3867 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3868 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
3869 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
3870 | CSKYV2_ISA_E1, | |
3871 | OPCODE_INFO3 (0xc4002480, | |
3872 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3873 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3874 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3875 | OPCODE_INFO2 (0xc4002480, | |
3876 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3877 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3878 | CSKYV2_ISA_1E2), | |
3879 | OP16_OP32 ("mov", | |
3880 | OPCODE_INFO2 (0x6c03, | |
3881 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3882 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3883 | CSKYV2_ISA_E1, | |
3884 | OPCODE_INFO2 (0xc4004820, | |
3885 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3886 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3887 | CSKYV2_ISA_1E2), | |
3888 | OP16_OP32 ("nop", | |
3889 | OPCODE_INFO0 (0x6c03), | |
3890 | CSKYV2_ISA_E1, | |
3891 | OPCODE_INFO0 (0xc4004820), | |
3892 | CSKYV2_ISA_E1), | |
3893 | DOP16_DOP32 ("lsl", | |
3894 | OPCODE_INFO2 (0x7000, | |
3895 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3896 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3897 | OPCODE_INFO3 (0x7000, | |
3898 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3899 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3900 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3901 | CSKYV2_ISA_E1, | |
3902 | OPCODE_INFO3 (0xc4004020, | |
3903 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3904 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3905 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3906 | OPCODE_INFO2 (0xc4004020, | |
3907 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3908 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3909 | CSKYV2_ISA_1E2), | |
3910 | DOP16_DOP32 ("lsr", | |
3911 | OPCODE_INFO2 (0x7001, | |
3912 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3913 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3914 | OPCODE_INFO3 (0x7001, | |
3915 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3916 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3917 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3918 | CSKYV2_ISA_E1, | |
3919 | OPCODE_INFO3 (0xc4004040, | |
3920 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3921 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3922 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3923 | OPCODE_INFO2 (0xc4004040, | |
3924 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3925 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3926 | CSKYV2_ISA_1E2), | |
3927 | DOP16_DOP32 ("asr", | |
3928 | OPCODE_INFO2 (0x7002, | |
3929 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3930 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3931 | OPCODE_INFO3 (0x7002, | |
3932 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3933 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3934 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3935 | CSKYV2_ISA_E1, | |
3936 | OPCODE_INFO3 (0xc4004080, | |
3937 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3938 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3939 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3940 | OPCODE_INFO2 (0xc4004080, | |
3941 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3942 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3943 | CSKYV2_ISA_1E2), | |
3944 | DOP16_DOP32 ("rotl", | |
3945 | OPCODE_INFO2 (0x7003, | |
3946 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3947 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3948 | OPCODE_INFO3 (0x7003, | |
3949 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3950 | (NONE, DUMMY_REG, OPRND_SHIFT_0_BIT), | |
3951 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3952 | CSKYV2_ISA_E1, | |
3953 | OPCODE_INFO3 (0xc4004100, | |
3954 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3955 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
3956 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3957 | OPCODE_INFO2 (0xc4004100, | |
3958 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
3959 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
3960 | CSKYV2_ISA_1E2), | |
3961 | DOP16_DOP32 ("zextb", | |
3962 | OPCODE_INFO2 (0x7400, | |
3963 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3964 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3965 | OPCODE_INFO1 (0x7400, | |
3966 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
3967 | CSKYV2_ISA_E1, | |
3968 | OPCODE_INFO2 (0xc40054e0, | |
3969 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3970 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3971 | OPCODE_INFO1 (0xc40054e0, | |
3972 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
3973 | CSKYV2_ISA_2E3), | |
3974 | DOP16_DOP32 ("zexth", | |
3975 | OPCODE_INFO2 (0x7401, | |
3976 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3977 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3978 | OPCODE_INFO1 (0x7401, | |
3979 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
3980 | CSKYV2_ISA_E1, | |
3981 | OPCODE_INFO2 (0xc40055e0, | |
3982 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3983 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3984 | OPCODE_INFO1 (0xc40055e0, | |
3985 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
3986 | CSKYV2_ISA_2E3), | |
3987 | DOP16_DOP32 ("sextb", | |
3988 | OPCODE_INFO2 (0x7402, | |
3989 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
3990 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
3991 | OPCODE_INFO1 (0x7402, | |
3992 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
3993 | CSKYV2_ISA_E1, | |
3994 | OPCODE_INFO2 (0xc40058e0, | |
3995 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
3996 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
3997 | OPCODE_INFO1 (0xc40058e0, | |
3998 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
3999 | CSKYV2_ISA_2E3), | |
4000 | DOP16_DOP32 ("sexth", | |
4001 | OPCODE_INFO2 (0x7403, | |
4002 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4003 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4004 | OPCODE_INFO1 (0x7403, | |
4005 | (2_5or6_9, DUP_GREG0_15, OPRND_SHIFT_0_BIT)), | |
4006 | CSKYV2_ISA_E1, | |
4007 | OPCODE_INFO2 (0xc40059e0, | |
4008 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4009 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4010 | OPCODE_INFO1 (0xc40059e0, | |
4011 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
4012 | CSKYV2_ISA_2E3), | |
4013 | OP32 ("zext", | |
4014 | OPCODE_INFO4 (0xc4005400, | |
4015 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4016 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4017 | (5_9, IMM5b, OPRND_SHIFT_0_BIT), | |
4018 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
4019 | CSKYV2_ISA_2E3), | |
4020 | OP32 ("sext", | |
4021 | OPCODE_INFO4 (0xc4005800, | |
4022 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4023 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4024 | (5_9, IMM5b, OPRND_SHIFT_0_BIT), | |
4025 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
4026 | CSKYV2_ISA_2E3), | |
4027 | #undef _TRANSFER | |
4028 | #define _TRANSFER 2 | |
4029 | OP16_OP32 ("rts", | |
4030 | OPCODE_INFO0 (0x783c), | |
4031 | CSKYV2_ISA_E1, | |
4032 | OPCODE_INFO0 (0xe8cf0000), | |
4033 | CSKYV2_ISA_E1), | |
4034 | #undef _TRANSFER | |
4035 | #define _TRANSFER 1 | |
4036 | OP16_OP32 ("jmp", | |
4037 | OPCODE_INFO1 (0x7800, | |
4038 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4039 | CSKYV2_ISA_E1, | |
4040 | OPCODE_INFO1 (0xe8c00000, | |
4041 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4042 | CSKYV2_ISA_2E3), | |
4043 | #undef _TRANSFER | |
4044 | #define _TRANSFER 0 | |
4045 | OP16_OP32 ("revb", | |
4046 | OPCODE_INFO2 (0x7802, | |
4047 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4048 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4049 | CSKYV2_ISA_1E2, | |
4050 | OPCODE_INFO2 (0xc4006080, | |
4051 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4052 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4053 | CSKYV2_ISA_2E3), | |
4054 | OP16_OP32 ("revh", | |
4055 | OPCODE_INFO2 (0x7803, | |
4056 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4057 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4058 | CSKYV2_ISA_1E2, | |
4059 | OPCODE_INFO2 (0xc4006100, | |
4060 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4061 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4062 | CSKYV2_ISA_2E3), | |
4063 | OP16_OP32 ("jsr", | |
4064 | OPCODE_INFO1 (0x7bc1, | |
4065 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4066 | CSKYV2_ISA_E1, | |
4067 | OPCODE_INFO1 (0xe8e00000, | |
4068 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4069 | CSKYV2_ISA_2E3), | |
4070 | DOP16_DOP32 ("mult", | |
4071 | OPCODE_INFO2 (0x7c00, | |
4072 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4073 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4074 | OPCODE_INFO3 (0x7c00, | |
4075 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4076 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
4077 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
4078 | CSKYV2_ISA_E1, | |
4079 | OPCODE_INFO3 (0xc4008420, | |
4080 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4081 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4082 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4083 | OPCODE_INFO2 (0xc4008420, | |
4084 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4085 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4086 | CSKYV2_ISA_1E2), | |
4087 | OP16 ("mul", | |
4088 | OPCODE_INFO2 (0x7c00, | |
4089 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4090 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4091 | CSKYV2_ISA_E1), | |
4092 | DOP16_DOP32 ("mulsh", | |
4093 | OPCODE_INFO2 (0x7c01, | |
4094 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4095 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4096 | OPCODE_INFO3 (0x7c01, | |
4097 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4098 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT), | |
4099 | (2_5, 2IN1_DUMMY, OPRND_SHIFT_0_BIT)), | |
4100 | CSKYV2_ISA_2E3, | |
4101 | OPCODE_INFO3 (0xc4009020, | |
4102 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4103 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4104 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4105 | OPCODE_INFO2 (0xc4009020, | |
4106 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4107 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4108 | CSKYV2_ISA_2E3), | |
4109 | OP16 ("muls.h", | |
4110 | OPCODE_INFO2 (0x7c01, | |
4111 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4112 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4113 | CSKYV2_ISA_2E3), | |
4114 | DOP32 ("mulsw", | |
4115 | OPCODE_INFO3 (0xc4009420, | |
4116 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4117 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4118 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4119 | OPCODE_INFO2 (0xc4009420, | |
4120 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4121 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6a1ed910 | 4122 | CSKY_ISA_DSPE60), |
b8891f8d AJ |
4123 | OP16_OP32 ("ld.b", |
4124 | SOPCODE_INFO2 (0x8000, | |
4125 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4126 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4127 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4128 | CSKYV2_ISA_E1, | |
4129 | SOPCODE_INFO2 (0xd8000000, | |
4130 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4131 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4132 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4133 | CSKYV2_ISA_E1), | |
4134 | OP16_OP32 ("ldb", | |
4135 | SOPCODE_INFO2 (0x8000, | |
4136 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4137 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4138 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4139 | CSKYV2_ISA_E1, | |
4140 | SOPCODE_INFO2 (0xd8000000, | |
4141 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4142 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4143 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4144 | CSKYV2_ISA_E1), | |
4145 | OP16_OP32 ("st.b", | |
4146 | SOPCODE_INFO2 (0xa000, | |
4147 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4148 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4149 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4150 | CSKYV2_ISA_E1, | |
4151 | SOPCODE_INFO2 (0xdc000000, | |
4152 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4153 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4154 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4155 | CSKYV2_ISA_E1), | |
4156 | OP16_OP32 ("stb", | |
4157 | SOPCODE_INFO2 (0xa000, | |
4158 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4159 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4160 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4161 | CSKYV2_ISA_E1, | |
4162 | SOPCODE_INFO2 (0xdc000000, | |
4163 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4164 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4165 | (0_11, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4166 | CSKYV2_ISA_E1), | |
4167 | ||
4168 | OP16_OP32 ("ld.h", | |
4169 | SOPCODE_INFO2 (0x8800, | |
4170 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4171 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4172 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4173 | CSKYV2_ISA_E1, | |
4174 | SOPCODE_INFO2 (0xd8001000, | |
4175 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4176 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4177 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4178 | CSKYV2_ISA_E1), | |
4179 | OP16_OP32 ("ldh", | |
4180 | SOPCODE_INFO2 (0x8800, | |
4181 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4182 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4183 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4184 | CSKYV2_ISA_E1, | |
4185 | SOPCODE_INFO2 (0xd8001000, | |
4186 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4187 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4188 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4189 | CSKYV2_ISA_E1), | |
4190 | OP16_OP32 ("st.h", | |
4191 | SOPCODE_INFO2 (0xa800, | |
4192 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4193 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4194 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4195 | CSKYV2_ISA_E1, | |
4196 | SOPCODE_INFO2 (0xdc001000, | |
4197 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4198 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4199 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4200 | CSKYV2_ISA_E1), | |
4201 | OP16_OP32 ("sth", | |
4202 | SOPCODE_INFO2 (0xa800, | |
4203 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4204 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4205 | (0_4, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4206 | CSKYV2_ISA_E1, | |
4207 | SOPCODE_INFO2 (0xdc001000, | |
4208 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4209 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4210 | (0_11, IMM_LDST, OPRND_SHIFT_1_BIT))), | |
4211 | CSKYV2_ISA_E1), | |
4212 | DOP16_OP32 ("ld.w", | |
4213 | SOPCODE_INFO2 (0x9000, | |
4214 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4215 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4216 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4217 | SOPCODE_INFO2 (0x9800, | |
4218 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4219 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4220 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4221 | CSKYV2_ISA_E1, | |
4222 | SOPCODE_INFO2 (0xd8002000, | |
4223 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4224 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4225 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4226 | CSKYV2_ISA_E1), | |
4227 | DOP16_OP32 ("ldw", | |
4228 | SOPCODE_INFO2 (0x9000, | |
4229 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4230 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4231 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4232 | SOPCODE_INFO2 (0x9800, | |
4233 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4234 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4235 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4236 | CSKYV2_ISA_E1, | |
4237 | SOPCODE_INFO2 (0xd8002000, | |
4238 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4239 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4240 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4241 | CSKYV2_ISA_E1), | |
4242 | DOP16_OP32 ("ld", | |
4243 | SOPCODE_INFO2 (0x9000, | |
4244 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4245 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4246 | (0_4, IMM_LDST, OPRND_SHIFT_0_BIT))), | |
4247 | SOPCODE_INFO2 (0x9800, | |
4248 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4249 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4250 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4251 | CSKYV2_ISA_E1, | |
4252 | SOPCODE_INFO2 (0xd8002000, | |
4253 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4254 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4255 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4256 | CSKYV2_ISA_E1), | |
4257 | DOP16_OP32 ("st.w", | |
4258 | SOPCODE_INFO2 (0xb000, | |
4259 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4260 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4261 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4262 | SOPCODE_INFO2 (0xb800, | |
4263 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4264 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4265 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4266 | CSKYV2_ISA_E1, | |
4267 | SOPCODE_INFO2 (0xdc002000, | |
4268 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4269 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4270 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4271 | CSKYV2_ISA_E1), | |
4272 | DOP16_OP32 ("stw", | |
4273 | SOPCODE_INFO2 (0xb000, | |
4274 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4275 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4276 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4277 | SOPCODE_INFO2 (0xb800, | |
4278 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4279 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4280 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4281 | CSKYV2_ISA_E1, | |
4282 | SOPCODE_INFO2 (0xdc002000, | |
4283 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4284 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4285 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4286 | CSKYV2_ISA_E1), | |
4287 | DOP16_OP32 ("st", | |
4288 | SOPCODE_INFO2 (0xb000, | |
4289 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4290 | BRACKET_OPRND ((8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4291 | (0_4, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4292 | SOPCODE_INFO2 (0xb800, | |
4293 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4294 | BRACKET_OPRND ((NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4295 | (0_4or8_10, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4296 | CSKYV2_ISA_E1, | |
4297 | SOPCODE_INFO2 (0xdc002000, | |
4298 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4299 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
4300 | (0_11, IMM_LDST, OPRND_SHIFT_2_BIT))), | |
4301 | CSKYV2_ISA_E1), | |
4302 | #ifdef BUILD_AS | |
4303 | DOP16_DOP32_WITH_WORK ("addi", | |
4304 | OPCODE_INFO2 (0x2000, | |
4305 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4306 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4307 | OPCODE_INFO3 (0x2000, | |
4308 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4309 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4310 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4311 | CSKYV2_ISA_E1, | |
4312 | OPCODE_INFO2 (0xe4000000, | |
4313 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4314 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4315 | OPCODE_INFO3 (0xe4000000, | |
4316 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4317 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4318 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4319 | CSKYV2_ISA_1E2, | |
4320 | v2_work_addi), | |
4321 | #else | |
4322 | DOP16 ("addi", | |
4323 | OPCODE_INFO2 (0x2000, | |
4324 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4325 | (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), | |
4326 | OPCODE_INFO3 (0x5802, | |
4327 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4328 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4329 | (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), | |
4330 | CSKYV2_ISA_E1), | |
4331 | DOP16 ("addi", | |
4332 | OPCODE_INFO3 (0x1800, | |
4333 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4334 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4335 | (0_7, IMM8b_LS2, OPRND_SHIFT_0_BIT)), | |
4336 | OPCODE_INFO3 (0x1400, | |
4337 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4338 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4339 | (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), | |
4340 | CSKYV2_ISA_E1), | |
4341 | DOP32 ("addi", | |
4342 | OPCODE_INFO3 (0xe4000000, | |
4343 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4344 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4345 | (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), | |
4346 | OPCODE_INFO3 (0xcc1c0000, | |
4347 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4348 | (NONE, REG_r28, OPRND_SHIFT_0_BIT), | |
4349 | (0_17, OIMM18b, OPRND_SHIFT_0_BIT)), | |
4350 | CSKYV2_ISA_1E2), | |
4351 | #endif | |
4352 | #ifdef BUILD_AS | |
4353 | DOP16_DOP32_WITH_WORK ("subi", | |
4354 | OPCODE_INFO2 (0x2800, | |
4355 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4356 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4357 | OPCODE_INFO3 (0x2800, | |
4358 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4359 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4360 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4361 | CSKYV2_ISA_E1, | |
4362 | OPCODE_INFO2 (0xe4001000, | |
4363 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4364 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4365 | OPCODE_INFO3 (0xe4001000, | |
4366 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4367 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
4368 | (NONE, IMM32b, OPRND_SHIFT_0_BIT)), | |
4369 | CSKYV2_ISA_1E2, v2_work_subi), | |
4370 | #else | |
4371 | DOP16 ("subi", | |
4372 | OPCODE_INFO2 (0x2800, | |
4373 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4374 | (0_7, OIMM8b, OPRND_SHIFT_0_BIT)), | |
4375 | OPCODE_INFO3 (0x5803, | |
4376 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4377 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4378 | (2_4, OIMM3b, OPRND_SHIFT_0_BIT)), | |
4379 | CSKYV2_ISA_E1), | |
4380 | OP32 ("subi", | |
4381 | OPCODE_INFO3 (0xe4001000, | |
4382 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4383 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4384 | (0_11, OIMM12b, OPRND_SHIFT_0_BIT)), | |
4385 | CSKYV2_ISA_1E2), | |
4386 | OP16 ("subi", | |
4387 | OPCODE_INFO3 (0x1420, | |
4388 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4389 | (NONE, REGsp, OPRND_SHIFT_0_BIT), | |
4390 | (0_4or8_9, IMM7b_LS2, OPRND_SHIFT_0_BIT)), | |
4391 | CSKYV2_ISA_E1), | |
4392 | #endif | |
4393 | DOP16_DOP32_WITH_WORK ("addu", | |
4394 | OPCODE_INFO2 (0x6000, | |
4395 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4396 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4397 | OPCODE_INFO3 (0x5800, | |
4398 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4399 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4400 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
4401 | CSKYV2_ISA_E1, | |
4402 | OPCODE_INFO3 (0xc4000020, | |
4403 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4404 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4405 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4406 | OPCODE_INFO2 (0xc4000020, | |
4407 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4408 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4409 | CSKYV2_ISA_E1, | |
4410 | v2_work_add_sub), | |
4411 | DOP16_DOP32_WITH_WORK ("add", | |
4412 | OPCODE_INFO2 (0x6000, | |
4413 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4414 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4415 | OPCODE_INFO3 (0x5800, | |
4416 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4417 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4418 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
4419 | CSKYV2_ISA_E1, | |
4420 | OPCODE_INFO3 (0xc4000020, | |
4421 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4422 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4423 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4424 | OPCODE_INFO2 (0xc4000020, | |
4425 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4426 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4427 | CSKYV2_ISA_E1, | |
4428 | v2_work_add_sub), | |
4429 | DOP16_DOP32_WITH_WORK ("subu", | |
4430 | OPCODE_INFO2 (0x6002, | |
4431 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4432 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4433 | OPCODE_INFO3 (0x5801, | |
4434 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4435 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4436 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
4437 | CSKYV2_ISA_E1, | |
4438 | OPCODE_INFO3 (0xc4000080, | |
4439 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4440 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4441 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4442 | OPCODE_INFO2 (0xc4000080, | |
4443 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4444 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4445 | CSKYV2_ISA_E1, | |
4446 | v2_work_add_sub), | |
4447 | DOP16_DOP32_WITH_WORK ("sub", | |
4448 | OPCODE_INFO2 (0x6002, | |
4449 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
4450 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
4451 | OPCODE_INFO3 (0x5801, | |
4452 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4453 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
4454 | (2_4, GREG0_7, OPRND_SHIFT_0_BIT)), | |
4455 | CSKYV2_ISA_E1, | |
4456 | OPCODE_INFO3 (0xc4000080, | |
4457 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4458 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4459 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4460 | OPCODE_INFO2 (0xc4000080, | |
4461 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
4462 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4463 | CSKYV2_ISA_E1, | |
4464 | v2_work_add_sub), | |
4465 | OP32_WITH_WORK ("fmovis", | |
4466 | OPCODE_INFO2 (0xf4001c00, | |
4467 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
4468 | (4_7or16_24, SFLOAT, OPRND_SHIFT_2_BIT)), | |
4469 | CSKY_ISA_FLOAT_1E3, | |
4470 | float_work_fmovi), | |
4471 | OP32_WITH_WORK ("fmovid", | |
4472 | OPCODE_INFO2 (0xf4001e00, | |
4473 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
4474 | (4_7or16_24, DFLOAT, OPRND_SHIFT_2_BIT)), | |
4475 | CSKY_ISA_FLOAT_3E4, | |
4476 | float_work_fmovi), | |
4477 | #undef _RELOC32 | |
4478 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM26BY2 | |
4479 | OP32 ("bsr", | |
4480 | OPCODE_INFO1 (0xe0000000, | |
4481 | (0_25, OFF26b, OPRND_SHIFT_1_BIT)), | |
4482 | CSKYV2_ISA_E1), | |
4483 | #undef _RELOC32 | |
4484 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18 | |
4485 | OP32 ("lrs.b", | |
4486 | OPCODE_INFO2 (0xcc000000, | |
4487 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4488 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4489 | CSKYV2_ISA_2E3), | |
4490 | OP32 ("srs.b", | |
4491 | OPCODE_INFO2 (0xcc100000, | |
4492 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4493 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4494 | CSKYV2_ISA_2E3), | |
4495 | #undef _RELOC32 | |
4496 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2 | |
4497 | OP32 ("lrs.h", | |
4498 | OPCODE_INFO2 (0xcc040000, | |
4499 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4500 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4501 | CSKYV2_ISA_2E3), | |
4502 | OP32 ("srs.h", | |
4503 | OPCODE_INFO2 (0xcc140000, | |
4504 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4505 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4506 | CSKYV2_ISA_2E3), | |
4507 | #undef _RELOC32 | |
4508 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 | |
4509 | OP32 ("flrws", | |
4510 | OPCODE_INFO2 (0xf4003800, | |
4511 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
4512 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
4513 | CSKY_ISA_FLOAT_1E3), | |
4514 | OP32 ("flrwd", | |
4515 | OPCODE_INFO2 (0xf4003900, | |
4516 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
4517 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
4518 | CSKY_ISA_FLOAT_3E4), | |
4519 | #undef _RELOC32 | |
4520 | #define _RELOC32 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4 | |
4521 | OP32_WITH_WORK ("lrs.w", | |
4522 | OPCODE_INFO2 (0xcc080000, | |
4523 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4524 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4525 | CSKYV2_ISA_2E3, | |
4526 | v2_work_lrsrsw), | |
4527 | OP32_WITH_WORK ("srs.w", | |
4528 | OPCODE_INFO2 (0xcc180000, | |
4529 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4530 | (0_17, LABEL_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4531 | CSKYV2_ISA_2E3, | |
4532 | v2_work_lrsrsw), | |
4533 | ||
4534 | #undef _RELOC32 | |
4535 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 | |
4536 | OP32_WITH_WORK ("jsri", | |
4537 | OPCODE_INFO1 (0xeae00000, | |
4538 | (0_15, OFF16b, OPRND_SHIFT_2_BIT)), | |
4539 | CSKYV2_ISA_2E3, | |
4540 | v2_work_jsri), | |
4541 | #undef _RELOC32 | |
4542 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY2 | |
4543 | OP32 ("bez", | |
4544 | OPCODE_INFO2 (0xe9000000, | |
4545 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4546 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
4547 | CSKYV2_ISA_2E3), | |
4548 | OP32 ("bnez", | |
4549 | OPCODE_INFO2 (0xe9200000, | |
4550 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4551 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
4552 | CSKYV2_ISA_2E3), | |
4553 | OP32 ("bhz", | |
4554 | OPCODE_INFO2 (0xe9400000, | |
4555 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4556 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
4557 | CSKYV2_ISA_2E3), | |
4558 | OP32 ("blsz", | |
4559 | OPCODE_INFO2 (0xe9600000, | |
4560 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4561 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
4562 | CSKYV2_ISA_2E3), | |
4563 | OP32 ("blz", | |
4564 | OPCODE_INFO2 (0xe9800000, | |
4565 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4566 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
4567 | CSKYV2_ISA_2E3), | |
4568 | OP32 ("bhsz", | |
4569 | OPCODE_INFO2 (0xe9a00000, | |
4570 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4571 | (0_15, OFF16b_LSL1, OPRND_SHIFT_1_BIT)), | |
4572 | CSKYV2_ISA_2E3), | |
4573 | #undef _RELAX | |
4574 | #undef _RELOC16 | |
4575 | #undef _TRANSFER | |
4576 | #define _TRANSFER 1 | |
4577 | #define _RELAX 1 | |
4578 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM10BY2 | |
4579 | OP16_OP32 ("br", | |
4580 | OPCODE_INFO1 (0x0400, | |
4581 | (0_9, UNCOND10b, OPRND_SHIFT_1_BIT)), | |
4582 | CSKYV2_ISA_E1, | |
4583 | OPCODE_INFO1 (0xe8000000, | |
4584 | (0_15, UNCOND16b, OPRND_SHIFT_1_BIT)), | |
4585 | CSKYV2_ISA_E1), | |
4586 | #undef _TRANSFER | |
4587 | #define _TRANSFER 0 | |
4588 | OP16_OP32 ("bt", | |
4589 | OPCODE_INFO1 (0x0800, | |
4590 | (0_9, COND10b, OPRND_SHIFT_1_BIT)), | |
4591 | CSKYV2_ISA_E1, | |
4592 | OPCODE_INFO1 (0xe8600000, | |
4593 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), | |
4594 | CSKYV2_ISA_1E2), | |
4595 | OP16_OP32 ("bf", | |
4596 | OPCODE_INFO1 (0x0c00, | |
4597 | (0_9, COND10b, OPRND_SHIFT_1_BIT)), | |
4598 | CSKYV2_ISA_E1, | |
4599 | OPCODE_INFO1 (0xe8400000, | |
4600 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), | |
4601 | CSKYV2_ISA_1E2), | |
d04aee0f CQ |
4602 | #undef _RELAX |
4603 | #undef _RELOC16 | |
4604 | #define _RELAX 0 | |
4605 | #define _RELOC16 0 | |
4606 | OP32 ("bnezad", | |
4607 | OPCODE_INFO2 (0xe8200000, | |
4608 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4609 | (0_15, COND16b, OPRND_SHIFT_1_BIT)), | |
4610 | CSKYV2_ISA_3E3R2), | |
b8891f8d AJ |
4611 | #undef _RELOC16 |
4612 | #undef _RELOC32 | |
b8891f8d AJ |
4613 | #define _RELOC16 0 |
4614 | #define _RELOC32 0 | |
b8891f8d AJ |
4615 | #undef _TRANSFER |
4616 | #define _TRANSFER 1 | |
4617 | OP16_WITH_WORK ("jbr", | |
4618 | OPCODE_INFO1 (0x0400, | |
4619 | (0_10, UNCOND10b, OPRND_SHIFT_1_BIT)), | |
4620 | CSKYV2_ISA_E1, | |
4621 | v2_work_jbr), | |
4622 | #undef _TRANSFER | |
4623 | #define _TRANSFER 0 | |
4624 | OP16_WITH_WORK ("jbt", | |
4625 | OPCODE_INFO1 (0x0800, | |
4626 | (0_10, COND10b, OPRND_SHIFT_1_BIT)), | |
4627 | CSKYV2_ISA_E1, | |
4628 | v2_work_jbtf), | |
4629 | OP16_WITH_WORK ("jbf", | |
4630 | OPCODE_INFO1 (0x0c00, | |
4631 | (0_10, COND10b, OPRND_SHIFT_1_BIT)), | |
4632 | CSKYV2_ISA_E1, | |
4633 | v2_work_jbtf), | |
4634 | OP32_WITH_WORK ("jbsr", | |
4635 | OPCODE_INFO1 (0xe0000000, | |
4636 | (0_25, OFF26b, OPRND_SHIFT_1_BIT)), | |
4637 | CSKYV2_ISA_E1, | |
4638 | v2_work_jbsr), | |
4639 | OP32_WITH_WORK ("movih", | |
4640 | OPCODE_INFO2 (0xea200000, | |
4641 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4642 | (0_15, IMM16b_MOVIH, OPRND_SHIFT_0_BIT)), | |
4643 | CSKYV2_ISA_1E2, | |
4644 | v2_work_movih), | |
4645 | OP32_WITH_WORK ("ori", | |
4646 | OPCODE_INFO3 (0xec000000, | |
4647 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
4648 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4649 | (0_15, IMM16b_ORI, OPRND_SHIFT_0_BIT)), | |
4650 | CSKYV2_ISA_1E2, | |
4651 | v2_work_ori), | |
4652 | DOP32_WITH_WORK ("bgeni", | |
4653 | OPCODE_INFO2 (0xea000000, | |
4654 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4655 | (0_4, IMM4b, OPRND_SHIFT_0_BIT)), | |
4656 | OPCODE_INFO2 (0xea200000, | |
4657 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4658 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
4659 | CSKYV2_ISA_E1, | |
4660 | v2_work_bgeni), | |
4661 | #undef _RELOC16 | |
4662 | #undef _RELOC32 | |
4663 | #define _RELOC16 BFD_RELOC_CKCORE_PCREL_IMM7BY4 | |
4664 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_IMM16BY4 | |
4665 | DOP16_OP32_WITH_WORK ("lrw", | |
4666 | OPCODE_INFO2 (0x1000, | |
4667 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4668 | (0_4or8_9, CONSTANT, OPRND_SHIFT_2_BIT)), | |
4669 | OPCODE_INFO2 (0x0000, | |
4670 | (5_7, GREG0_7, OPRND_SHIFT_0_BIT), | |
4671 | (0_4or8_9, ELRW_CONSTANT, OPRND_SHIFT_2_BIT)), | |
4672 | CSKYV2_ISA_E1, | |
4673 | OPCODE_INFO2 (0xea800000, | |
4674 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4675 | (0_15, CONSTANT, OPRND_SHIFT_2_BIT)), | |
4676 | CSKYV2_ISA_E1, | |
4677 | v2_work_lrw), | |
4678 | #undef _RELOC16 | |
4679 | #undef _RELOC32 | |
4680 | #define _RELOC16 0 | |
4681 | #define _RELOC32 0 | |
4682 | ||
4683 | #undef _RELAX | |
4684 | #define _RELAX 1 | |
4685 | OP32 ("jbez", | |
4686 | OPCODE_INFO2 (0xe9000000, | |
4687 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4688 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
4689 | CSKYV2_ISA_2E3), | |
4690 | OP32 ("jbnez", | |
4691 | OPCODE_INFO2 (0xe9200000, | |
4692 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4693 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
4694 | CSKYV2_ISA_2E3), | |
4695 | OP32 ("jbhz", | |
4696 | OPCODE_INFO2 (0xe9400000, | |
4697 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4698 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
4699 | CSKYV2_ISA_2E3), | |
4700 | OP32 ("jblsz", | |
4701 | OPCODE_INFO2 (0xe9600000, | |
4702 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4703 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
4704 | CSKYV2_ISA_2E3), | |
4705 | OP32 ("jblz", | |
4706 | OPCODE_INFO2 (0xe9800000, | |
4707 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4708 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
4709 | CSKYV2_ISA_2E3), | |
4710 | OP32 ("jbhsz", | |
4711 | OPCODE_INFO2 (0xe9a00000, | |
4712 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4713 | (0_15, JCOMPZ, OPRND_SHIFT_0_BIT)), | |
4714 | CSKYV2_ISA_2E3), | |
4715 | #undef _RELAX | |
4716 | #define _RELAX 0 | |
4717 | ||
531c73a3 | 4718 | /* CK860 instructions. */ |
79c8d443 CQ |
4719 | OP32 ("sync.is", |
4720 | OPCODE_INFO0 (0xc2200420), | |
4721 | CSKYV2_ISA_10E60), | |
4722 | OP32 ("sync.i", | |
4723 | OPCODE_INFO0 (0xc0200420), | |
4724 | CSKYV2_ISA_10E60), | |
4725 | OP32 ("sync.s", | |
4726 | OPCODE_INFO0 (0xc2000420), | |
4727 | CSKYV2_ISA_10E60), | |
4728 | OP32 ("bar.brwarw", | |
4729 | OPCODE_INFO0 (0xc000842f), | |
4730 | CSKYV2_ISA_10E60), | |
4731 | OP32 ("bar.brwarws", | |
4732 | OPCODE_INFO0 (0xc200842f), | |
4733 | CSKYV2_ISA_10E60), | |
4734 | OP32 ("bar.brar", | |
4735 | OPCODE_INFO0 (0xc0008425), | |
4736 | CSKYV2_ISA_10E60), | |
4737 | OP32 ("bar.brars", | |
4738 | OPCODE_INFO0 (0xc2008425), | |
4739 | CSKYV2_ISA_10E60), | |
4740 | OP32 ("bar.bwaw", | |
4741 | OPCODE_INFO0 (0xc000842a), | |
4742 | CSKYV2_ISA_10E60), | |
4743 | OP32 ("bar.bwaws", | |
4744 | OPCODE_INFO0 (0xc200842a), | |
4745 | CSKYV2_ISA_10E60), | |
4746 | OP32 ("icache.iall", | |
4747 | OPCODE_INFO0 (0xc1009020), | |
4748 | CSKYV2_ISA_10E60), | |
4749 | OP32 ("icache.ialls", | |
4750 | OPCODE_INFO0 (0xc3009020), | |
4751 | CSKYV2_ISA_10E60), | |
4752 | OP32 ("l2cache.iall", | |
4753 | OPCODE_INFO0 (0xc1009820), | |
4754 | CSKYV2_ISA_10E60), | |
4755 | OP32 ("l2cache.call", | |
4756 | OPCODE_INFO0 (0xc0809820), | |
4757 | CSKYV2_ISA_10E60), | |
4758 | OP32 ("l2cache.ciall", | |
4759 | OPCODE_INFO0 (0xc1809820), | |
4760 | CSKYV2_ISA_10E60), | |
4761 | OP32 ("icache.iva", | |
4762 | OPCODE_INFO1 (0xc1609020, | |
4763 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4764 | CSKYV2_ISA_10E60), | |
4765 | OP32 ("dcache.iall", | |
4766 | OPCODE_INFO0 (0xc1009420), | |
4767 | CSKYV2_ISA_10E60), | |
4768 | OP32 ("dcache.iva", | |
4769 | OPCODE_INFO1 (0xc1609420, | |
4770 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4771 | CSKYV2_ISA_10E60), | |
4772 | OP32 ("dcache.isw", | |
4773 | OPCODE_INFO1 (0xc1409420, | |
4774 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4775 | CSKYV2_ISA_10E60), | |
4776 | OP32 ("dcache.call", | |
4777 | OPCODE_INFO0 (0xc0809420), | |
4778 | CSKYV2_ISA_10E60), | |
4779 | OP32 ("dcache.cva", | |
4780 | OPCODE_INFO1 (0xc0e09420, | |
4781 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4782 | CSKYV2_ISA_10E60), | |
4783 | OP32 ("dcache.cval1", | |
4784 | OPCODE_INFO1 (0xc2e09420, | |
4785 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4786 | CSKYV2_ISA_10E60), | |
4787 | OP32 ("dcache.csw", | |
4788 | OPCODE_INFO1 (0xc0c09420, | |
4789 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4790 | CSKYV2_ISA_10E60), | |
4791 | OP32 ("dcache.ciall", | |
4792 | OPCODE_INFO0 (0xc1809420), | |
4793 | CSKYV2_ISA_10E60), | |
4794 | OP32 ("dcache.civa", | |
4795 | OPCODE_INFO1 (0xc1e09420, | |
4796 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4797 | CSKYV2_ISA_10E60), | |
4798 | OP32 ("dcache.cisw", | |
4799 | OPCODE_INFO1 (0xc1c09420, | |
4800 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4801 | CSKYV2_ISA_10E60), | |
4802 | OP32 ("tlbi.vaa", | |
4803 | OPCODE_INFO1 (0xc0408820, | |
4804 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4805 | CSKYV2_ISA_10E60), | |
4806 | OP32 ("tlbi.vaas", | |
4807 | OPCODE_INFO1 (0xc2408820, | |
4808 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4809 | CSKYV2_ISA_10E60), | |
4810 | OP32 ("tlbi.asid", | |
4811 | OPCODE_INFO1 (0xc0208820, | |
4812 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4813 | CSKYV2_ISA_10E60), | |
4814 | OP32 ("tlbi.asids", | |
4815 | OPCODE_INFO1 (0xc2208820, | |
4816 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4817 | CSKYV2_ISA_10E60), | |
4818 | OP32 ("tlbi.va", | |
4819 | OPCODE_INFO1 (0xc0608820, | |
4820 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4821 | CSKYV2_ISA_10E60), | |
4822 | OP32 ("tlbi.vas", | |
4823 | OPCODE_INFO1 (0xc2608820, | |
4824 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
4825 | CSKYV2_ISA_10E60), | |
4826 | OP32 ("tlbi.all", | |
4827 | OPCODE_INFO0 (0xc0008820), | |
4828 | CSKYV2_ISA_10E60), | |
4829 | OP32 ("tlbi.alls", | |
4830 | OPCODE_INFO0 (0xc2008820), | |
4831 | CSKYV2_ISA_10E60), | |
4832 | DOP32 ("sync", | |
4833 | OPCODE_INFO0 (0xc0000420), | |
4834 | OPCODE_INFO1 (0xc0000420, | |
4835 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
4836 | CSKYV2_ISA_E1), | |
531c73a3 | 4837 | |
b8891f8d | 4838 | /* The followings are enhance DSP instructions. */ |
d285ba8d CQ |
4839 | DOP32_WITH_WORK ("bloop", |
4840 | OPCODE_INFO3 (0xe9c00000, | |
b8891f8d AJ |
4841 | (16_20, AREG, OPRND_SHIFT_0_BIT), |
4842 | (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT), | |
4843 | (12_15, BLOOP_OFF4b, OPRND_SHIFT_1_BIT)), | |
d285ba8d CQ |
4844 | OPCODE_INFO2 (0xe9c00000, |
4845 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4846 | (0_11, BLOOP_OFF12b, OPRND_SHIFT_1_BIT)), | |
4847 | CSKY_ISA_DSP_ENHANCE, | |
4848 | dsp_work_bloop), | |
b8891f8d AJ |
4849 | /* The followings are ld/st instructions. */ |
4850 | OP32 ("ldbi.b", | |
4851 | OPCODE_INFO2 (0xd0008000, | |
4852 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4853 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4854 | CSKY_ISA_DSP_ENHANCE), | |
4855 | OP32 ("ldbi.h", | |
4856 | OPCODE_INFO2 (0xd0008400, | |
4857 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4858 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4859 | CSKY_ISA_DSP_ENHANCE), | |
4860 | OP32 ("ldbi.w", | |
4861 | OPCODE_INFO2 (0xd0008800, | |
4862 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4863 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4864 | CSKY_ISA_DSP_ENHANCE), | |
4865 | OP32 ("pldbi.d", | |
4866 | OPCODE_INFO2 (0xd0008c00, | |
4867 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4868 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4869 | CSKY_ISA_DSP_ENHANCE), | |
4870 | OP32 ("ldbi.hs", | |
4871 | OPCODE_INFO2 (0xd0009000, | |
4872 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4873 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4874 | CSKY_ISA_DSP_ENHANCE), | |
4875 | OP32 ("ldbi.bs", | |
4876 | OPCODE_INFO2 (0xd0009400, | |
4877 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4878 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4879 | CSKY_ISA_DSP_ENHANCE), | |
4880 | OP32 ("stbi.b", | |
4881 | OPCODE_INFO2 (0xd4008000, | |
4882 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4883 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4884 | CSKY_ISA_DSP_ENHANCE), | |
4885 | OP32 ("stbi.h", | |
4886 | OPCODE_INFO2 (0xd4008400, | |
4887 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4888 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4889 | CSKY_ISA_DSP_ENHANCE), | |
4890 | OP32 ("stbi.w", | |
4891 | OPCODE_INFO2 (0xd4008800, | |
4892 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4893 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT)), | |
4894 | CSKY_ISA_DSP_ENHANCE), | |
4895 | OP32 ("ldbir.b", | |
4896 | OPCODE_INFO3 (0xd000a000, | |
4897 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4898 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4899 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4900 | CSKY_ISA_DSP_ENHANCE), | |
4901 | OP32 ("ldbir.h", | |
4902 | OPCODE_INFO3 (0xd000a400, | |
4903 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4904 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4905 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4906 | CSKY_ISA_DSP_ENHANCE), | |
4907 | OP32 ("ldbir.w", | |
4908 | OPCODE_INFO3 (0xd000a800, | |
4909 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4910 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4911 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4912 | CSKY_ISA_DSP_ENHANCE), | |
4913 | OP32 ("pldbir.d", | |
4914 | OPCODE_INFO3 (0xd000ac00, | |
4915 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4916 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4917 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4918 | CSKY_ISA_DSP_ENHANCE), | |
4919 | OP32 ("ldbir.bs", | |
4920 | OPCODE_INFO3 (0xd000b000, | |
4921 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4922 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4923 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4924 | CSKY_ISA_DSP_ENHANCE), | |
4925 | OP32 ("ldbir.hs", | |
4926 | OPCODE_INFO3 (0xd000b400, | |
4927 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4928 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4929 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4930 | CSKY_ISA_DSP_ENHANCE), | |
4931 | OP32 ("stbir.b", | |
4932 | OPCODE_INFO3 (0xd400a000, | |
4933 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4934 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4935 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4936 | CSKY_ISA_DSP_ENHANCE), | |
4937 | OP32 ("stbir.h", | |
4938 | OPCODE_INFO3 (0xd400a400, | |
4939 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4940 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4941 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4942 | CSKY_ISA_DSP_ENHANCE), | |
4943 | OP32 ("stbir.w", | |
4944 | OPCODE_INFO3 (0xd400a800, | |
4945 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4946 | (16_20, AREG_WITH_BRACKET, OPRND_SHIFT_0_BIT), | |
4947 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4948 | CSKY_ISA_DSP_ENHANCE), | |
4949 | /* The followings are add/sub instructions. */ | |
4950 | OP32 ("padd.8", | |
4951 | OPCODE_INFO3 (0xf800c040, | |
4952 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4953 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4954 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4955 | CSKY_ISA_DSP_ENHANCE), | |
4956 | OP32 ("padd.16", | |
4957 | OPCODE_INFO3 (0xf800c000, | |
4958 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4959 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4960 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4961 | CSKY_ISA_DSP_ENHANCE), | |
4962 | OP32 ("padd.u8.s", | |
4963 | OPCODE_INFO3 (0xf800c140, | |
4964 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4965 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4966 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4967 | CSKY_ISA_DSP_ENHANCE), | |
4968 | OP32 ("padd.s8.s", | |
4969 | OPCODE_INFO3 (0xf800c1c0, | |
4970 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4971 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4972 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4973 | CSKY_ISA_DSP_ENHANCE), | |
4974 | OP32 ("padd.u16.s", | |
4975 | OPCODE_INFO3 (0xf800c100, | |
4976 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4977 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4978 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4979 | CSKY_ISA_DSP_ENHANCE), | |
4980 | OP32 ("padd.s16.s", | |
4981 | OPCODE_INFO3 (0xf800c180, | |
4982 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4983 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4984 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4985 | CSKY_ISA_DSP_ENHANCE), | |
4986 | OP32 ("add.u32.s", | |
4987 | OPCODE_INFO3 (0xf800c120, | |
4988 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4989 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4990 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4991 | CSKY_ISA_DSP_ENHANCE), | |
4992 | OP32 ("add.s32.s", | |
4993 | OPCODE_INFO3 (0xf800c1a0, | |
4994 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
4995 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
4996 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4997 | CSKY_ISA_DSP_ENHANCE), | |
4998 | OP32 ("psub.8", | |
4999 | OPCODE_INFO3 (0xf800c440, | |
5000 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5001 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5002 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5003 | CSKY_ISA_DSP_ENHANCE), | |
5004 | OP32 ("psub.16", | |
5005 | OPCODE_INFO3 (0xf800c400, | |
5006 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5007 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5008 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5009 | CSKY_ISA_DSP_ENHANCE), | |
5010 | OP32 ("psub.u8.s", | |
5011 | OPCODE_INFO3 (0xf800c540, | |
5012 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5013 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5014 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5015 | CSKY_ISA_DSP_ENHANCE), | |
5016 | OP32 ("psub.s8.s", | |
5017 | OPCODE_INFO3 (0xf800c5c0, | |
5018 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5019 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5020 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5021 | CSKY_ISA_DSP_ENHANCE), | |
5022 | OP32 ("psub.u16.s", | |
5023 | OPCODE_INFO3 (0xf800c500, | |
5024 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5025 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5026 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5027 | CSKY_ISA_DSP_ENHANCE), | |
5028 | OP32 ("psub.s16.s", | |
5029 | OPCODE_INFO3 (0xf800c580, | |
5030 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5031 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5032 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5033 | CSKY_ISA_DSP_ENHANCE), | |
5034 | OP32 ("sub.u32.s", | |
5035 | OPCODE_INFO3 (0xf800c520, | |
5036 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5037 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5038 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5039 | CSKY_ISA_DSP_ENHANCE), | |
5040 | OP32 ("sub.s32.s", | |
5041 | OPCODE_INFO3 (0xf800c5a0, | |
5042 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5043 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5044 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5045 | CSKY_ISA_DSP_ENHANCE), | |
5046 | OP32 ("paddh.u8", | |
5047 | OPCODE_INFO3 (0xf800c240, | |
5048 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5049 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5050 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5051 | CSKY_ISA_DSP_ENHANCE), | |
5052 | OP32 ("paddh.s8", | |
5053 | OPCODE_INFO3 (0xf800c2c0, | |
5054 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5055 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5056 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5057 | CSKY_ISA_DSP_ENHANCE), | |
5058 | OP32 ("paddh.u16", | |
5059 | OPCODE_INFO3 (0xf800c200, | |
5060 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5061 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5062 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5063 | CSKY_ISA_DSP_ENHANCE), | |
5064 | OP32 ("paddh.s16", | |
5065 | OPCODE_INFO3 (0xf800c280, | |
5066 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5067 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5068 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5069 | CSKY_ISA_DSP_ENHANCE), | |
5070 | OP32 ("addh.u32", | |
5071 | OPCODE_INFO3 (0xf800c220, | |
5072 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5073 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5074 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5075 | CSKY_ISA_DSP_ENHANCE), | |
5076 | OP32 ("addh.s32", | |
5077 | OPCODE_INFO3 (0xf800c2a0, | |
5078 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5079 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5080 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5081 | CSKY_ISA_DSP_ENHANCE), | |
5082 | OP32 ("psubh.u8", | |
5083 | OPCODE_INFO3 (0xf800c640, | |
5084 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5085 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5086 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5087 | CSKY_ISA_DSP_ENHANCE), | |
5088 | OP32 ("psubh.s8", | |
5089 | OPCODE_INFO3 (0xf800c6c0, | |
5090 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5091 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5092 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5093 | CSKY_ISA_DSP_ENHANCE), | |
5094 | OP32 ("psubh.u16", | |
5095 | OPCODE_INFO3 (0xf800c600, | |
5096 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5097 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5098 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5099 | CSKY_ISA_DSP_ENHANCE), | |
5100 | OP32 ("psubh.s16", | |
5101 | OPCODE_INFO3 (0xf800c680, | |
5102 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5103 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5104 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5105 | CSKY_ISA_DSP_ENHANCE), | |
5106 | OP32 ("subh.u32", | |
5107 | OPCODE_INFO3 (0xf800c620, | |
5108 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5109 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5110 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5111 | CSKY_ISA_DSP_ENHANCE), | |
5112 | OP32 ("subh.s32", | |
5113 | OPCODE_INFO3 (0xf800c6a0, | |
5114 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5115 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5116 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5117 | CSKY_ISA_DSP_ENHANCE), | |
5118 | OP32 ("add.64", | |
5119 | OPCODE_INFO3 (0xf800c060, | |
5120 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5121 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5122 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5123 | CSKY_ISA_DSP_ENHANCE), | |
5124 | OP32 ("sub.64", | |
5125 | OPCODE_INFO3 (0xf800c460, | |
5126 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5127 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5128 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5129 | CSKY_ISA_DSP_ENHANCE), | |
5130 | OP32 ("add.u64.s", | |
5131 | OPCODE_INFO3 (0xf800c160, | |
5132 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5133 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5134 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5135 | CSKY_ISA_DSP_ENHANCE), | |
5136 | OP32 ("add.s64.s", | |
5137 | OPCODE_INFO3 (0xf800c1e0, | |
5138 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5139 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5140 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5141 | CSKY_ISA_DSP_ENHANCE), | |
5142 | OP32 ("sub.u64.s", | |
5143 | OPCODE_INFO3 (0xf800c560, | |
5144 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5145 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5146 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5147 | CSKY_ISA_DSP_ENHANCE), | |
5148 | OP32 ("sub.s64.s", | |
5149 | OPCODE_INFO3 (0xf800c5e0, | |
5150 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5151 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5152 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5153 | CSKY_ISA_DSP_ENHANCE), | |
5154 | /* The following are comparison instructions. */ | |
5155 | OP32 ("pasx.16", | |
5156 | OPCODE_INFO3 (0xf800c860, | |
5157 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5158 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5159 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5160 | CSKY_ISA_DSP_ENHANCE), | |
5161 | OP32 ("psax.16", | |
5162 | OPCODE_INFO3 (0xf800cc60, | |
5163 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5164 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5165 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5166 | CSKY_ISA_DSP_ENHANCE), | |
5167 | OP32 ("pasx.u16.s", | |
5168 | OPCODE_INFO3 (0xf800c960, | |
5169 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5170 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5171 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5172 | CSKY_ISA_DSP_ENHANCE), | |
5173 | OP32 ("pasx.s16.s", | |
5174 | OPCODE_INFO3 (0xf800c9e0, | |
5175 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5176 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5177 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5178 | CSKY_ISA_DSP_ENHANCE), | |
5179 | OP32 ("psax.u16.s", | |
5180 | OPCODE_INFO3 (0xf800cd60, | |
5181 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5182 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5183 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5184 | CSKY_ISA_DSP_ENHANCE), | |
5185 | OP32 ("psax.s16.s", | |
5186 | OPCODE_INFO3 (0xf800cde0, | |
5187 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5188 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5189 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5190 | CSKY_ISA_DSP_ENHANCE), | |
5191 | OP32 ("pasxh.u16", | |
5192 | OPCODE_INFO3 (0xf800ca60, | |
5193 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5194 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5195 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5196 | CSKY_ISA_DSP_ENHANCE), | |
5197 | OP32 ("pasxh.s16", | |
5198 | OPCODE_INFO3 (0xf800cae0, | |
5199 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5200 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5201 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5202 | CSKY_ISA_DSP_ENHANCE), | |
5203 | OP32 ("psaxh.u16", | |
5204 | OPCODE_INFO3 (0xf800ce60, | |
5205 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5206 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5207 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5208 | CSKY_ISA_DSP_ENHANCE), | |
5209 | OP32 ("psaxh.s16", | |
5210 | OPCODE_INFO3 (0xf800cee0, | |
5211 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5212 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5213 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5214 | CSKY_ISA_DSP_ENHANCE), | |
5215 | OP32 ("pcmpne.8", | |
5216 | OPCODE_INFO3 (0xf800c840, | |
5217 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5218 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5219 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5220 | CSKY_ISA_DSP_ENHANCE), | |
5221 | OP32 ("pcmpne.16", | |
5222 | OPCODE_INFO3 (0xf800c800, | |
5223 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5224 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5225 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5226 | CSKY_ISA_DSP_ENHANCE), | |
5227 | OP32 ("pcmphs.u8", | |
5228 | OPCODE_INFO3 (0xf800c940, | |
5229 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5230 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5231 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5232 | CSKY_ISA_DSP_ENHANCE), | |
5233 | OP32 ("pcmphs.s8", | |
5234 | OPCODE_INFO3 (0xf800c9c0, | |
5235 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5236 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5237 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5238 | CSKY_ISA_DSP_ENHANCE), | |
5239 | OP32 ("pcmphs.u16", | |
5240 | OPCODE_INFO3 (0xf800c900, | |
5241 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5242 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5243 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5244 | CSKY_ISA_DSP_ENHANCE), | |
5245 | OP32 ("pcmphs.s16", | |
5246 | OPCODE_INFO3 (0xf800c980, | |
5247 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5248 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5249 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5250 | CSKY_ISA_DSP_ENHANCE), | |
5251 | OP32 ("pcmplt.u8", | |
5252 | OPCODE_INFO3 (0xf800ca40, | |
5253 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5254 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5255 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5256 | CSKY_ISA_DSP_ENHANCE), | |
5257 | OP32 ("pcmplt.s8", | |
5258 | OPCODE_INFO3 (0xf800cac0, | |
5259 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5260 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5261 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5262 | CSKY_ISA_DSP_ENHANCE), | |
5263 | OP32 ("pcmplt.u16", | |
5264 | OPCODE_INFO3 (0xf800ca00, | |
5265 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5266 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5267 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5268 | CSKY_ISA_DSP_ENHANCE), | |
5269 | OP32 ("pcmplt.s16", | |
5270 | OPCODE_INFO3 (0xf800ca80, | |
5271 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5272 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5273 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5274 | CSKY_ISA_DSP_ENHANCE), | |
5275 | OP32 ("pmax.u8", | |
5276 | OPCODE_INFO3 (0xf800cc40, | |
5277 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5278 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5279 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5280 | CSKY_ISA_DSP_ENHANCE), | |
5281 | OP32 ("pmax.s8", | |
5282 | OPCODE_INFO3 (0xf800ccc0, | |
5283 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5284 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5285 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5286 | CSKY_ISA_DSP_ENHANCE), | |
5287 | OP32 ("pmax.u16", | |
5288 | OPCODE_INFO3 (0xf800cc00, | |
5289 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5290 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5291 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5292 | CSKY_ISA_DSP_ENHANCE), | |
5293 | OP32 ("pmax.s16", | |
5294 | OPCODE_INFO3 (0xf800cc80, | |
5295 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5296 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5297 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5298 | CSKY_ISA_DSP_ENHANCE), | |
5299 | OP32 ("max.u32", | |
5300 | OPCODE_INFO3 (0xf800cc20, | |
5301 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5302 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5303 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5304 | CSKY_ISA_DSP_ENHANCE), | |
5305 | OP32 ("max.s32", | |
5306 | OPCODE_INFO3 (0xf800cca0, | |
5307 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5308 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5309 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5310 | CSKY_ISA_DSP_ENHANCE), | |
5311 | OP32 ("pmin.u8", | |
5312 | OPCODE_INFO3 (0xf800cd40, | |
5313 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5314 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5315 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5316 | CSKY_ISA_DSP_ENHANCE), | |
5317 | OP32 ("pmin.s8", | |
5318 | OPCODE_INFO3 (0xf800cdc0, | |
5319 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5320 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5321 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5322 | CSKY_ISA_DSP_ENHANCE), | |
5323 | OP32 ("pmin.u16", | |
5324 | OPCODE_INFO3 (0xf800cd00, | |
5325 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5326 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5327 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5328 | CSKY_ISA_DSP_ENHANCE), | |
5329 | OP32 ("pmin.s16", | |
5330 | OPCODE_INFO3 (0xf800cd80, | |
5331 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5332 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5333 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5334 | CSKY_ISA_DSP_ENHANCE), | |
5335 | OP32 ("min.u32", | |
5336 | OPCODE_INFO3 (0xf800cd20, | |
5337 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5338 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5339 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5340 | CSKY_ISA_DSP_ENHANCE), | |
5341 | OP32 ("min.s32", | |
5342 | OPCODE_INFO3 (0xf800cda0, | |
5343 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5344 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5345 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5346 | CSKY_ISA_DSP_ENHANCE), | |
5347 | OP32 ("sel", | |
5348 | OPCODE_INFO4 (0xf8009000, | |
5349 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5350 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5351 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
5352 | (5_9, AREG, OPRND_SHIFT_0_BIT)), | |
5353 | CSKY_ISA_DSP_ENHANCE), | |
5354 | /* The followings are miscs. */ | |
5355 | OP32 ("psabsa.u8", | |
5356 | OPCODE_INFO3 (0xf800e040, | |
5357 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5358 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5359 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5360 | CSKY_ISA_DSP_ENHANCE), | |
5361 | OP32 ("psabsaa.u8", | |
5362 | OPCODE_INFO3 (0xf800e140, | |
5363 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5364 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5365 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5366 | CSKY_ISA_DSP_ENHANCE), | |
5367 | OP32 ("divul", | |
5368 | OPCODE_INFO3 (0xf800e260, | |
5369 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5370 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5371 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4211a340 | 5372 | CSKYV2_ISA_3E3R3), |
b8891f8d AJ |
5373 | OP32 ("divsl", |
5374 | OPCODE_INFO3 (0xf800e2e0, | |
5375 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5376 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5377 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
4211a340 | 5378 | CSKYV2_ISA_3E3R3), |
b8891f8d AJ |
5379 | OP32 ("mulaca.s8", |
5380 | OPCODE_INFO3 (0xf800e4c0, | |
5381 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5382 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5383 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5384 | CSKY_ISA_DSP_ENHANCE), | |
5385 | /* The followings are shift instructions. */ | |
5386 | OP32 ("asri.s32.r", | |
5387 | OPCODE_INFO3 (0xf800d1a0, | |
5388 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5389 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5390 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
5391 | CSKY_ISA_DSP_ENHANCE), | |
5392 | OP32 ("asr.s32.r", | |
5393 | OPCODE_INFO3 (0xf800d1e0, | |
5394 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5395 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5396 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5397 | CSKY_ISA_DSP_ENHANCE), | |
5398 | OP32 ("lsri.u32.r", | |
5399 | OPCODE_INFO3 (0xf800d320, | |
5400 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5401 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5402 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
5403 | CSKY_ISA_DSP_ENHANCE), | |
5404 | OP32 ("lsr.u32.r", | |
5405 | OPCODE_INFO3 (0xf800d360, | |
5406 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5407 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5408 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5409 | CSKY_ISA_DSP_ENHANCE), | |
5410 | OP32 ("lsli.u32.s", | |
5411 | OPCODE_INFO3 (0xf800d520, | |
5412 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5413 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5414 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
5415 | CSKY_ISA_DSP_ENHANCE), | |
5416 | OP32 ("lsli.s32.s", | |
5417 | OPCODE_INFO3 (0xf800d5a0, | |
5418 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5419 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5420 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
5421 | CSKY_ISA_DSP_ENHANCE), | |
5422 | OP32 ("lsl.u32.s", | |
5423 | OPCODE_INFO3 (0xf800d560, | |
5424 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5425 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5426 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5427 | CSKY_ISA_DSP_ENHANCE), | |
5428 | OP32 ("lsl.s32.s", | |
5429 | OPCODE_INFO3 (0xf800d5e0, | |
5430 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5431 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5432 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5433 | CSKY_ISA_DSP_ENHANCE), | |
5434 | OP32 ("pasri.s16", | |
5435 | OPCODE_INFO3 (0xf800d080, | |
5436 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5437 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5438 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5439 | CSKY_ISA_DSP_ENHANCE), | |
5440 | OP32 ("pasr.s16", | |
5441 | OPCODE_INFO3 (0xf800d0c0, | |
5442 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5443 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5444 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5445 | CSKY_ISA_DSP_ENHANCE), | |
5446 | OP32 ("pasri.s16.r", | |
5447 | OPCODE_INFO3 (0xf800d180, | |
5448 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5449 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5450 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5451 | CSKY_ISA_DSP_ENHANCE), | |
5452 | OP32 ("pasr.s16.r", | |
5453 | OPCODE_INFO3 (0xf800d1c0, | |
5454 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5455 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5456 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5457 | CSKY_ISA_DSP_ENHANCE), | |
5458 | OP32 ("plsri.u16", | |
5459 | OPCODE_INFO3 (0xf800d200, | |
5460 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5461 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5462 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5463 | CSKY_ISA_DSP_ENHANCE), | |
5464 | OP32 ("plsr.u16", | |
5465 | OPCODE_INFO3 (0xf800d240, | |
5466 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5467 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5468 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5469 | CSKY_ISA_DSP_ENHANCE), | |
5470 | OP32 ("plsri.u16.r", | |
5471 | OPCODE_INFO3 (0xf800d300, | |
5472 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5473 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5474 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5475 | CSKY_ISA_DSP_ENHANCE), | |
5476 | OP32 ("plsr.u16.r", | |
5477 | OPCODE_INFO3 (0xf800d340, | |
5478 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5479 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5480 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5481 | CSKY_ISA_DSP_ENHANCE), | |
531c73a3 | 5482 | OP32 ("plsli.16", |
b8891f8d AJ |
5483 | OPCODE_INFO3 (0xf800d400, |
5484 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5485 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5486 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5487 | CSKY_ISA_DSP_ENHANCE), | |
5488 | OP32 ("plsl.u16", | |
5489 | OPCODE_INFO3 (0xf800d440, | |
5490 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5491 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5492 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5493 | CSKY_ISA_DSP_ENHANCE), | |
5494 | OP32 ("plsli.u16.s", | |
5495 | OPCODE_INFO3 (0xf800d500, | |
5496 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5497 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5498 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5499 | CSKY_ISA_DSP_ENHANCE), | |
5500 | OP32 ("plsli.s16.s", | |
5501 | OPCODE_INFO3 (0xf800d580, | |
5502 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5503 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5504 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5505 | CSKY_ISA_DSP_ENHANCE), | |
5506 | OP32 ("plsl.u16.s", | |
5507 | OPCODE_INFO3 (0xf800d540, | |
5508 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5509 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5510 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5511 | CSKY_ISA_DSP_ENHANCE), | |
5512 | OP32 ("plsl.s16.s", | |
5513 | OPCODE_INFO3 (0xf800d5c0, | |
5514 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5515 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5516 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5517 | CSKY_ISA_DSP_ENHANCE), | |
5518 | /* The following are package & unpackage instructions. */ | |
5519 | OP32 ("pkg", | |
5520 | OPCODE_INFO5 (0xf800a000, | |
5521 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5522 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5523 | (5_8, IMM4b, OPRND_SHIFT_0_BIT), | |
5524 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
5525 | (9_12, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5526 | CSKY_ISA_DSP_ENHANCE), | |
5527 | OP32 ("dexti", | |
5528 | OPCODE_INFO4 (0xf8009800, | |
5529 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5530 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5531 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
5532 | (5_9, IMM5b, OPRND_SHIFT_0_BIT)), | |
5533 | CSKY_ISA_DSP_ENHANCE), | |
5534 | OP32 ("dext", | |
5535 | OPCODE_INFO4 (0xf8009c00, | |
5536 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5537 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5538 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
5539 | (5_9, AREG, OPRND_SHIFT_0_BIT)), | |
5540 | CSKY_ISA_DSP_ENHANCE), | |
5541 | OP32 ("pkgll", | |
5542 | OPCODE_INFO3 (0xf800d840, | |
5543 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5544 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5545 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5546 | CSKY_ISA_DSP_ENHANCE), | |
5547 | OP32 ("pkghh", | |
5548 | OPCODE_INFO3 (0xf800d860, | |
5549 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5550 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5551 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5552 | CSKY_ISA_DSP_ENHANCE), | |
5553 | OP32 ("pext.u8.e", | |
5554 | OPCODE_INFO2 (0xf800d900, | |
5555 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5556 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5557 | CSKY_ISA_DSP_ENHANCE), | |
5558 | OP32 ("pext.s8.e", | |
5559 | OPCODE_INFO2 (0xf800d980, | |
5560 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5561 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5562 | CSKY_ISA_DSP_ENHANCE), | |
5563 | OP32 ("pextx.u8.e", | |
5564 | OPCODE_INFO2 (0xf800d920, | |
5565 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5566 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5567 | CSKY_ISA_DSP_ENHANCE), | |
5568 | OP32 ("pextx.s8.e", | |
5569 | OPCODE_INFO2 (0xf800d9a0, | |
5570 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5571 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5572 | CSKY_ISA_DSP_ENHANCE), | |
5573 | OP32 ("narl", | |
5574 | OPCODE_INFO3 (0xf800da00, | |
5575 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5576 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5577 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5578 | CSKY_ISA_DSP_ENHANCE), | |
5579 | OP32 ("narh", | |
5580 | OPCODE_INFO3 (0xf800da20, | |
5581 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5582 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5583 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5584 | CSKY_ISA_DSP_ENHANCE), | |
5585 | OP32 ("narlx", | |
5586 | OPCODE_INFO3 (0xf800da40, | |
5587 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5588 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5589 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5590 | CSKY_ISA_DSP_ENHANCE), | |
5591 | OP32 ("narhx", | |
5592 | OPCODE_INFO3 (0xf800da60, | |
5593 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5594 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5595 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5596 | CSKY_ISA_DSP_ENHANCE), | |
5597 | OP32 ("clipi.u32", | |
5598 | OPCODE_INFO3 (0xf800db00, | |
5599 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5600 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5601 | (21_25, IMM5b, OPRND_SHIFT_0_BIT)), | |
5602 | CSKY_ISA_DSP_ENHANCE), | |
5603 | OP32 ("clipi.s32", | |
5604 | OPCODE_INFO3 (0xf800db80, | |
5605 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5606 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5607 | (21_25, OIMM5b, OPRND_SHIFT_0_BIT)), | |
5608 | CSKY_ISA_DSP_ENHANCE), | |
5609 | OP32 ("clip.u32", | |
5610 | OPCODE_INFO3 (0xf800db20, | |
5611 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5612 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5613 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5614 | CSKY_ISA_DSP_ENHANCE), | |
5615 | OP32 ("clip.s32", | |
5616 | OPCODE_INFO3 (0xf800dba0, | |
5617 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5618 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5619 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5620 | CSKY_ISA_DSP_ENHANCE), | |
5621 | OP32 ("pclipi.u16", | |
5622 | OPCODE_INFO3 (0xf800db40, | |
5623 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5624 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5625 | (21_25, IMM4b, OPRND_SHIFT_0_BIT)), | |
5626 | CSKY_ISA_DSP_ENHANCE), | |
5627 | OP32 ("pclipi.s16", | |
5628 | OPCODE_INFO3 (0xf800dbc0, | |
5629 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5630 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5631 | (21_25, OIMM4b, OPRND_SHIFT_0_BIT)), | |
5632 | CSKY_ISA_DSP_ENHANCE), | |
5633 | OP32 ("pclip.u16", | |
5634 | OPCODE_INFO3 (0xf800db60, | |
5635 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5636 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5637 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5638 | CSKY_ISA_DSP_ENHANCE), | |
5639 | OP32 ("pclip.s16", | |
5640 | OPCODE_INFO3 (0xf800dbe0, | |
5641 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5642 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5643 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5644 | CSKY_ISA_DSP_ENHANCE), | |
5645 | OP32 ("pabs.s8.s", | |
5646 | OPCODE_INFO2 (0xf800dc80, | |
5647 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5648 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5649 | CSKY_ISA_DSP_ENHANCE), | |
5650 | OP32 ("pabs.s16.s", | |
5651 | OPCODE_INFO2 (0xf800dca0, | |
5652 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5653 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5654 | CSKY_ISA_DSP_ENHANCE), | |
5655 | OP32 ("abs.s32.s", | |
5656 | OPCODE_INFO2 (0xf800dcc0, | |
5657 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5658 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5659 | CSKY_ISA_DSP_ENHANCE), | |
5660 | OP32 ("pneg.s8.s", | |
5661 | OPCODE_INFO2 (0xf800dd80, | |
5662 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5663 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5664 | CSKY_ISA_DSP_ENHANCE), | |
5665 | OP32 ("pneg.s16.s", | |
5666 | OPCODE_INFO2 (0xf800dda0, | |
5667 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5668 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5669 | CSKY_ISA_DSP_ENHANCE), | |
5670 | OP32 ("neg.s32.s", | |
5671 | OPCODE_INFO2 (0xf800ddc0, | |
5672 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5673 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
5674 | CSKY_ISA_DSP_ENHANCE), | |
5675 | OP32 ("dup.8", | |
5676 | OPCODE_INFO3 (0xf800de00, | |
5677 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5678 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5679 | (5_6, IMM2b, OPRND_SHIFT_0_BIT)), | |
5680 | CSKY_ISA_DSP_ENHANCE), | |
5681 | OP32 ("dup.16", | |
5682 | OPCODE_INFO3 (0xf800df00, | |
5683 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5684 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5685 | (5_6, IMM1b, OPRND_SHIFT_0_BIT)), | |
5686 | CSKY_ISA_DSP_ENHANCE), | |
5687 | /* The followings are multiplication instructions. */ | |
5688 | OP32 ("mul.u32", | |
5689 | OPCODE_INFO3 (0xf8008000, | |
5690 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5691 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5692 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5693 | CSKYV2_ISA_3E3R1), | |
5694 | OP32 ("mul.s32", | |
5695 | OPCODE_INFO3 (0xf8008200, | |
5696 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5697 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5698 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5699 | CSKYV2_ISA_3E3R1), | |
5700 | OP32 ("mula.u32", | |
5701 | OPCODE_INFO3 (0xf8008080, | |
5702 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5703 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5704 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5705 | CSKYV2_ISA_3E3R1), | |
5706 | OP32 ("mula.s32", | |
5707 | OPCODE_INFO3 (0xf8008280, | |
5708 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5709 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5710 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5711 | CSKYV2_ISA_3E3R1), | |
5712 | OP32 ("mula.32.l", | |
5713 | OPCODE_INFO3 (0xf8008440, | |
5714 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5715 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5716 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5717 | CSKYV2_ISA_3E3R1), | |
5718 | OP32 ("mulall.s16.s", | |
5719 | OPCODE_INFO3 (0xf80081a0, | |
5720 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5721 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5722 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5723 | CSKYV2_ISA_3E3R1), | |
5724 | OP32 ("muls.u32", | |
5725 | OPCODE_INFO3 (0xf80080c0, | |
5726 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5727 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5728 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5729 | CSKY_ISA_DSP_ENHANCE), | |
5730 | OP32 ("muls.s32", | |
5731 | OPCODE_INFO3 (0xf80082c0, | |
5732 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5733 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5734 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5735 | CSKY_ISA_DSP_ENHANCE), | |
5736 | OP32 ("mula.u32.s", | |
5737 | OPCODE_INFO3 (0xf8008180, | |
5738 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5739 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5740 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5741 | CSKY_ISA_DSP_ENHANCE), | |
5742 | OP32 ("mula.s32.s", | |
5743 | OPCODE_INFO3 (0xf8008380, | |
5744 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5745 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5746 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5747 | CSKY_ISA_DSP_ENHANCE), | |
5748 | OP32 ("muls.u32.s", | |
5749 | OPCODE_INFO3 (0xf80081c0, | |
5750 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5751 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5752 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5753 | CSKY_ISA_DSP_ENHANCE), | |
5754 | OP32 ("muls.s32.s", | |
5755 | OPCODE_INFO3 (0xf80083c0, | |
5756 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5757 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5758 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5759 | CSKY_ISA_DSP_ENHANCE), | |
5760 | OP32 ("mul.s32.h", | |
5761 | OPCODE_INFO3 (0xf8008400, | |
5762 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5763 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5764 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5765 | CSKY_ISA_DSP_ENHANCE), | |
5766 | OP32 ("mul.s32.rh", | |
5767 | OPCODE_INFO3 (0xf8008600, | |
5768 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5769 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5770 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5771 | CSKY_ISA_DSP_ENHANCE), | |
5772 | OP32 ("rmul.s32.h", | |
5773 | OPCODE_INFO3 (0xf8008500, | |
5774 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5775 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5776 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5777 | CSKY_ISA_DSP_ENHANCE), | |
5778 | OP32 ("rmul.s32.rh", | |
5779 | OPCODE_INFO3 (0xf8008700, | |
5780 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5781 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5782 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5783 | CSKY_ISA_DSP_ENHANCE), | |
5784 | OP32 ("mula.s32.hs", | |
5785 | OPCODE_INFO3 (0xf8008580, | |
5786 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5787 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5788 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5789 | CSKY_ISA_DSP_ENHANCE), | |
5790 | OP32 ("muls.s32.hs", | |
5791 | OPCODE_INFO3 (0xf80085c0, | |
5792 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5793 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5794 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5795 | CSKY_ISA_DSP_ENHANCE), | |
5796 | OP32 ("mula.s32.rhs", | |
5797 | OPCODE_INFO3 (0xf8008780, | |
5798 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5799 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5800 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5801 | CSKY_ISA_DSP_ENHANCE), | |
5802 | OP32 ("muls.s32.rhs", | |
5803 | OPCODE_INFO3 (0xf80087c0, | |
5804 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5805 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5806 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5807 | CSKY_ISA_DSP_ENHANCE), | |
5808 | OP32 ("mulxl.s32", | |
5809 | OPCODE_INFO3 (0xf8008800, | |
5810 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5811 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5812 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5813 | CSKY_ISA_DSP_ENHANCE), | |
5814 | OP32 ("mulxl.s32.r", | |
5815 | OPCODE_INFO3 (0xf8008a00, | |
5816 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5817 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5818 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5819 | CSKY_ISA_DSP_ENHANCE), | |
5820 | OP32 ("mulxh.s32", | |
5821 | OPCODE_INFO3 (0xf8008c00, | |
5822 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5823 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5824 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5825 | CSKY_ISA_DSP_ENHANCE), | |
5826 | OP32 ("mulxh.s32.r", | |
5827 | OPCODE_INFO3 (0xf8008e00, | |
5828 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5829 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5830 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5831 | CSKY_ISA_DSP_ENHANCE), | |
5832 | OP32 ("rmulxl.s32", | |
5833 | OPCODE_INFO3 (0xf8008900, | |
5834 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5835 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5836 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5837 | CSKY_ISA_DSP_ENHANCE), | |
5838 | OP32 ("rmulxl.s32.r", | |
5839 | OPCODE_INFO3 (0xf8008b00, | |
5840 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5841 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5842 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5843 | CSKY_ISA_DSP_ENHANCE), | |
5844 | OP32 ("rmulxh.s32", | |
5845 | OPCODE_INFO3 (0xf8008d00, | |
5846 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5847 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5848 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5849 | CSKY_ISA_DSP_ENHANCE), | |
5850 | OP32 ("rmulxh.s32.r", | |
5851 | OPCODE_INFO3 (0xf8008f00, | |
5852 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5853 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5854 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5855 | CSKY_ISA_DSP_ENHANCE), | |
5856 | OP32 ("mulaxl.s32.s", | |
5857 | OPCODE_INFO3 (0xf8008980, | |
5858 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5859 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5860 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5861 | CSKY_ISA_DSP_ENHANCE), | |
5862 | OP32 ("mulaxl.s32.rs", | |
5863 | OPCODE_INFO3 (0xf8008b80, | |
5864 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5865 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5866 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5867 | CSKY_ISA_DSP_ENHANCE), | |
5868 | OP32 ("mulaxh.s32.s", | |
5869 | OPCODE_INFO3 (0xf8008d80, | |
5870 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5871 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5872 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5873 | CSKY_ISA_DSP_ENHANCE), | |
5874 | OP32 ("mulaxh.s32.rs", | |
5875 | OPCODE_INFO3 (0xf8008f80, | |
5876 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5877 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5878 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5879 | CSKY_ISA_DSP_ENHANCE), | |
5880 | OP32 ("mulll.s16", | |
5881 | OPCODE_INFO3 (0xf8008020, | |
5882 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5883 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5884 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5885 | CSKY_ISA_DSP_ENHANCE), | |
5886 | OP32 ("mulhh.s16", | |
5887 | OPCODE_INFO3 (0xf8008260, | |
5888 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5889 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5890 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5891 | CSKY_ISA_DSP_ENHANCE), | |
5892 | OP32 ("mulhl.s16", | |
5893 | OPCODE_INFO3 (0xf8008220, | |
5894 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5895 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5896 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5897 | CSKY_ISA_DSP_ENHANCE), | |
5898 | OP32 ("rmulll.s16", | |
5899 | OPCODE_INFO3 (0xf8008120, | |
5900 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5901 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5902 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5903 | CSKY_ISA_DSP_ENHANCE), | |
5904 | OP32 ("rmulhh.s16", | |
5905 | OPCODE_INFO3 (0xf8008360, | |
5906 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5907 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5908 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5909 | CSKY_ISA_DSP_ENHANCE), | |
5910 | OP32 ("rmulhl.s16", | |
5911 | OPCODE_INFO3 (0xf8008320, | |
5912 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5913 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5914 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5915 | CSKY_ISA_DSP_ENHANCE), | |
5916 | OP32 ("mulahh.s16.s", | |
5917 | OPCODE_INFO3 (0xf80083e0, | |
5918 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5919 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5920 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5921 | CSKY_ISA_DSP_ENHANCE), | |
5922 | OP32 ("mulahl.s16.s", | |
5923 | OPCODE_INFO3 (0xf80083a0, | |
5924 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5925 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5926 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5927 | CSKY_ISA_DSP_ENHANCE), | |
5928 | OP32 ("mulall.s16.e", | |
5929 | OPCODE_INFO3 (0xf80080a0, | |
5930 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5931 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5932 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5933 | CSKY_ISA_DSP_ENHANCE), | |
5934 | OP32 ("mulahh.s16.e", | |
5935 | OPCODE_INFO3 (0xf80082e0, | |
5936 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5937 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5938 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5939 | CSKY_ISA_DSP_ENHANCE), | |
5940 | OP32 ("mulahl.s16.e", | |
5941 | OPCODE_INFO3 (0xf80080e0, | |
5942 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5943 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5944 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5945 | CSKY_ISA_DSP_ENHANCE), | |
5946 | OP32 ("pmul.u16", | |
5947 | OPCODE_INFO3 (0xf80084a0, | |
5948 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5949 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5950 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5951 | CSKY_ISA_DSP_ENHANCE), | |
5952 | OP32 ("pmulx.u16", | |
5953 | OPCODE_INFO3 (0xf80084e0, | |
5954 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5955 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5956 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5957 | CSKY_ISA_DSP_ENHANCE), | |
5958 | OP32 ("pmul.s16", | |
5959 | OPCODE_INFO3 (0xf8008420, | |
5960 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5961 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5962 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5963 | CSKY_ISA_DSP_ENHANCE), | |
5964 | OP32 ("pmulx.s16", | |
5965 | OPCODE_INFO3 (0xf8008460, | |
5966 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5967 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5968 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5969 | CSKY_ISA_DSP_ENHANCE), | |
5970 | OP32 ("prmul.s16", | |
5971 | OPCODE_INFO3 (0xf8008520, | |
5972 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5973 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5974 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5975 | CSKY_ISA_DSP_ENHANCE), | |
5976 | OP32 ("prmulx.s16", | |
5977 | OPCODE_INFO3 (0xf8008560, | |
5978 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5979 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5980 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5981 | CSKY_ISA_DSP_ENHANCE), | |
5982 | OP32 ("prmul.s16.h", | |
5983 | OPCODE_INFO3 (0xf80085a0, | |
5984 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5985 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5986 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5987 | CSKY_ISA_DSP_ENHANCE), | |
5988 | OP32 ("prmul.s16.rh", | |
5989 | OPCODE_INFO3 (0xf80087a0, | |
5990 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5991 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5992 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5993 | CSKY_ISA_DSP_ENHANCE), | |
5994 | OP32 ("prmulx.s16.h", | |
5995 | OPCODE_INFO3 (0xf80085e0, | |
5996 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
5997 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
5998 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
5999 | CSKY_ISA_DSP_ENHANCE), | |
6000 | OP32 ("prmulx.s16.rh", | |
6001 | OPCODE_INFO3 (0xf80087e0, | |
6002 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6003 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6004 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6005 | CSKY_ISA_DSP_ENHANCE), | |
6006 | OP32 ("mulca.s16.s", | |
6007 | OPCODE_INFO3 (0xf8008920, | |
6008 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6009 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6010 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6011 | CSKY_ISA_DSP_ENHANCE), | |
6012 | OP32 ("mulcax.s16.s", | |
6013 | OPCODE_INFO3 (0xf8008960, | |
6014 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6015 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6016 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6017 | CSKY_ISA_DSP_ENHANCE), | |
6018 | OP32 ("mulcs.s16", | |
6019 | OPCODE_INFO3 (0xf8008a20, | |
6020 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6021 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6022 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6023 | CSKY_ISA_DSP_ENHANCE), | |
6024 | OP32 ("mulcsr.s16", | |
6025 | OPCODE_INFO3 (0xf8008a60, | |
6026 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6027 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6028 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6029 | CSKY_ISA_DSP_ENHANCE), | |
6030 | OP32 ("mulcsx.s16", | |
6031 | OPCODE_INFO3 (0xf8008c20, | |
6032 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6033 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6034 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6035 | CSKY_ISA_DSP_ENHANCE), | |
6036 | OP32 ("mulaca.s16.s", | |
6037 | OPCODE_INFO3 (0xf80089a0, | |
6038 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6039 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6040 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6041 | CSKY_ISA_DSP_ENHANCE), | |
6042 | OP32 ("mulacax.s16.s", | |
6043 | OPCODE_INFO3 (0xf80089e0, | |
6044 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6045 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6046 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6047 | CSKY_ISA_DSP_ENHANCE), | |
6048 | OP32 ("mulacs.s16.s", | |
6049 | OPCODE_INFO3 (0xf8008ba0, | |
6050 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6051 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6052 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6053 | CSKY_ISA_DSP_ENHANCE), | |
6054 | OP32 ("mulacsr.s16.s", | |
6055 | OPCODE_INFO3 (0xf8008be0, | |
6056 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6057 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6058 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6059 | CSKY_ISA_DSP_ENHANCE), | |
6060 | OP32 ("mulacsx.s16.s", | |
6061 | OPCODE_INFO3 (0xf8008da0, | |
6062 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6063 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6064 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6065 | CSKY_ISA_DSP_ENHANCE), | |
6066 | OP32 ("mulsca.s16.s", | |
6067 | OPCODE_INFO3 (0xf8008de0, | |
6068 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6069 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6070 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6071 | CSKY_ISA_DSP_ENHANCE), | |
6072 | OP32 ("mulscax.s16.s", | |
6073 | OPCODE_INFO3 (0xf8008fa0, | |
6074 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6075 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6076 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6077 | CSKY_ISA_DSP_ENHANCE), | |
6078 | OP32 ("mulaca.s16.e", | |
6079 | OPCODE_INFO3 (0xf80088a0, | |
6080 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6081 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6082 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6083 | CSKY_ISA_DSP_ENHANCE), | |
6084 | OP32 ("mulacax.s16.e", | |
6085 | OPCODE_INFO3 (0xf80088e0, | |
6086 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6087 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6088 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6089 | CSKY_ISA_DSP_ENHANCE), | |
6090 | OP32 ("mulacs.s16.e", | |
6091 | OPCODE_INFO3 (0xf8008aa0, | |
6092 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6093 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6094 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6095 | CSKY_ISA_DSP_ENHANCE), | |
6096 | OP32 ("mulacsr.s16.e", | |
6097 | OPCODE_INFO3 (0xf8008ae0, | |
6098 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6099 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6100 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6101 | CSKY_ISA_DSP_ENHANCE), | |
6102 | OP32 ("mulacsx.s16.e", | |
6103 | OPCODE_INFO3 (0xf8008ca0, | |
6104 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6105 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6106 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6107 | CSKY_ISA_DSP_ENHANCE), | |
6108 | OP32 ("mulsca.s16.e", | |
6109 | OPCODE_INFO3 (0xf8008ce0, | |
6110 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6111 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6112 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6113 | CSKY_ISA_DSP_ENHANCE), | |
6114 | OP32 ("mulscax.s16.e", | |
6115 | OPCODE_INFO3 (0xf8008ea0, | |
6116 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6117 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
6118 | (21_25, AREG, OPRND_SHIFT_0_BIT)), | |
6119 | CSKY_ISA_DSP_ENHANCE), | |
6120 | ||
6121 | /* The followings are vdsp instructions for ck810. */ | |
6122 | OP32 ("vdup.8", | |
6123 | OPCODE_INFO2 (0xf8000e80, | |
6124 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6125 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6126 | CSKY_ISA_VDSP), | |
6127 | OP32 ("vdup.16", | |
6128 | OPCODE_INFO2 (0xf8100e80, | |
6129 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6130 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6131 | CSKY_ISA_VDSP), | |
6132 | OP32 ("vdup.32", | |
6133 | OPCODE_INFO2 (0xfa000e80, | |
6134 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6135 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6136 | CSKY_ISA_VDSP), | |
6137 | OP32 ("vmfvr.u8", | |
6138 | OPCODE_INFO2 (0xf8001200, | |
6139 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6140 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6141 | CSKY_ISA_VDSP), | |
6142 | OP32 ("vmfvr.u16", | |
6143 | OPCODE_INFO2 (0xf8001220, | |
6144 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6145 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6146 | CSKY_ISA_VDSP), | |
6147 | OP32 ("vmfvr.u32", | |
6148 | OPCODE_INFO2 (0xf8001240, | |
6149 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6150 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6151 | CSKY_ISA_VDSP), | |
6152 | OP32 ("vmfvr.s8", | |
6153 | OPCODE_INFO2 (0xf8001280, | |
6154 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6155 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6156 | CSKY_ISA_VDSP), | |
6157 | OP32 ("vmfvr.s16", | |
6158 | OPCODE_INFO2 (0xf80012a0, | |
6159 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
6160 | (16_19or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT)), | |
6161 | CSKY_ISA_VDSP), | |
6162 | OP32 ("vmtvr.u8", | |
6163 | OPCODE_INFO2 (0xf8001300, | |
6164 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), | |
6165 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
6166 | CSKY_ISA_VDSP), | |
6167 | OP32 ("vmtvr.u16", | |
6168 | OPCODE_INFO2 (0xf8001320, | |
6169 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), | |
6170 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
6171 | CSKY_ISA_VDSP), | |
6172 | OP32 ("vmtvr.u32", | |
6173 | OPCODE_INFO2 (0xf8001340, | |
6174 | (0_3or21_24, FREG_WITH_INDEX, OPRND_SHIFT_0_BIT), | |
6175 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
6176 | CSKY_ISA_VDSP), | |
6177 | OP32 ("vldd.8", | |
6178 | SOPCODE_INFO2 (0xf8002000, | |
6179 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6180 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6181 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
6182 | CSKY_ISA_VDSP), | |
6183 | OP32 ("vldd.16", | |
6184 | SOPCODE_INFO2 (0xf8002100, | |
6185 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6186 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6187 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
6188 | CSKY_ISA_VDSP), | |
6189 | OP32 ("vldd.32", | |
6190 | SOPCODE_INFO2 (0xf8002200, | |
6191 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6192 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6193 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
6194 | CSKY_ISA_VDSP), | |
6195 | OP32 ("vldq.8", | |
6196 | SOPCODE_INFO2 (0xf8002400, | |
6197 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6198 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6199 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
6200 | CSKY_ISA_VDSP), | |
6201 | OP32 ("vldq.16", | |
6202 | SOPCODE_INFO2 (0xf8002500, | |
6203 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6204 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6205 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
6206 | CSKY_ISA_VDSP), | |
6207 | OP32 ("vldq.32", | |
6208 | SOPCODE_INFO2 (0xf8002600, | |
6209 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6210 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6211 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
6212 | CSKY_ISA_VDSP), | |
6213 | OP32 ("vstd.8", | |
6214 | SOPCODE_INFO2 (0xf8002800, | |
6215 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6216 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6217 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
6218 | CSKY_ISA_VDSP), | |
6219 | OP32 ("vstd.16", | |
6220 | SOPCODE_INFO2 (0xf8002900, | |
6221 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6222 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6223 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
6224 | CSKY_ISA_VDSP), | |
6225 | OP32 ("vstd.32", | |
6226 | SOPCODE_INFO2 (0xf8002a00, | |
6227 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6228 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6229 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_3_BIT))), | |
6230 | CSKY_ISA_VDSP), | |
6231 | OP32 ("vstq.8", | |
6232 | SOPCODE_INFO2 (0xf8002c00, | |
6233 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6234 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6235 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
6236 | CSKY_ISA_VDSP), | |
6237 | OP32 ("vstq.16", | |
6238 | SOPCODE_INFO2 (0xf8002d00, | |
6239 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6240 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6241 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
6242 | CSKY_ISA_VDSP), | |
6243 | OP32 ("vstq.32", | |
6244 | SOPCODE_INFO2 (0xf8002e00, | |
6245 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6246 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6247 | (4_7or21_24, IMM_FLDST, OPRND_SHIFT_4_BIT))), | |
6248 | CSKY_ISA_VDSP), | |
6249 | OP32 ("vldrd.8", | |
6250 | SOPCODE_INFO2 (0xf8003000, | |
6251 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6252 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6253 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6254 | CSKY_ISA_VDSP), | |
6255 | OP32 ("vldrd.16", | |
6256 | SOPCODE_INFO2 (0xf8003100, | |
6257 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6258 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6259 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6260 | CSKY_ISA_VDSP), | |
6261 | OP32 ("vldrd.32", | |
6262 | SOPCODE_INFO2 (0xf8003200, | |
6263 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6264 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6265 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6266 | CSKY_ISA_VDSP), | |
6267 | OP32 ("vldrq.8", | |
6268 | SOPCODE_INFO2 (0xf8003400, | |
6269 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6270 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6271 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6272 | CSKY_ISA_VDSP), | |
6273 | OP32 ("vldrq.16", | |
6274 | SOPCODE_INFO2 (0xf8003500, | |
6275 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6276 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6277 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6278 | CSKY_ISA_VDSP), | |
6279 | OP32 ("vldrq.32", | |
6280 | SOPCODE_INFO2 (0xf8003600, | |
6281 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6282 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6283 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6284 | CSKY_ISA_VDSP), | |
6285 | OP32 ("vstrd.8", | |
6286 | SOPCODE_INFO2 (0xf8003800, | |
6287 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6288 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6289 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6290 | CSKY_ISA_VDSP), | |
6291 | OP32 ("vstrd.16", | |
6292 | SOPCODE_INFO2 (0xf8003900, | |
6293 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6294 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6295 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6296 | CSKY_ISA_VDSP), | |
6297 | OP32 ("vstrd.32", | |
6298 | SOPCODE_INFO2 (0xf8003a00, | |
6299 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6300 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6301 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6302 | CSKY_ISA_VDSP), | |
6303 | OP32 ("vstrq.8", | |
6304 | SOPCODE_INFO2 (0xf8003c00, | |
6305 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6306 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6307 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6308 | CSKY_ISA_VDSP), | |
6309 | OP32 ("vstrq.16", | |
6310 | SOPCODE_INFO2 (0xf8003d00, | |
6311 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6312 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6313 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6314 | CSKY_ISA_VDSP), | |
6315 | OP32 ("vstrq.32", | |
6316 | SOPCODE_INFO2 (0xf8003e00, | |
6317 | (0_3, FREG, OPRND_SHIFT_0_BIT), | |
6318 | BRACKET_OPRND ((16_20, AREG, OPRND_SHIFT_0_BIT), | |
6319 | (5_6or21_25, AREG_WITH_LSHIFT_FPU, OPRND_SHIFT_0_BIT))), | |
6320 | CSKY_ISA_VDSP), | |
6321 | OP32 ("vmov", | |
6322 | OPCODE_INFO2 (0xf8000c00, | |
6323 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6324 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6325 | CSKY_ISA_VDSP), | |
6326 | OP32 ("vcadd.eu8", | |
6327 | OPCODE_INFO2 (0xf8000060, | |
6328 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6329 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6330 | CSKY_ISA_VDSP), | |
6331 | OP32 ("vcadd.eu16", | |
6332 | OPCODE_INFO2 (0xf8100060, | |
6333 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6334 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6335 | CSKY_ISA_VDSP), | |
6336 | OP32 ("vcadd.es8", | |
6337 | OPCODE_INFO2 (0xf8000070, | |
6338 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6339 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6340 | CSKY_ISA_VDSP), | |
6341 | OP32 ("vcadd.es16", | |
6342 | OPCODE_INFO2 (0xf8100070, | |
6343 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6344 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6345 | CSKY_ISA_VDSP), | |
6346 | OP32 ("vmov.eu8", | |
6347 | OPCODE_INFO2 (0xf8000c20, | |
6348 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6349 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6350 | CSKY_ISA_VDSP), | |
6351 | OP32 ("vmov.eu16", | |
6352 | OPCODE_INFO2 (0xf8100c20, | |
6353 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6354 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6355 | CSKY_ISA_VDSP), | |
6356 | OP32 ("vmov.es8", | |
6357 | OPCODE_INFO2 (0xf8000c30, | |
6358 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6359 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6360 | CSKY_ISA_VDSP), | |
6361 | OP32 ("vmov.es16", | |
6362 | OPCODE_INFO2 (0xf8100c30, | |
6363 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6364 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6365 | CSKY_ISA_VDSP), | |
6366 | OP32 ("vmov.u16.l", | |
6367 | OPCODE_INFO2 (0xf8100d00, | |
6368 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6369 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6370 | CSKY_ISA_VDSP), | |
6371 | OP32 ("vmov.u32.l", | |
6372 | OPCODE_INFO2 (0xfa000d00, | |
6373 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6374 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6375 | CSKY_ISA_VDSP), | |
6376 | OP32 ("vmov.s16.l", | |
6377 | OPCODE_INFO2 (0xf8100d10, | |
6378 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6379 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6380 | CSKY_ISA_VDSP), | |
6381 | OP32 ("vmov.s32.l", | |
6382 | OPCODE_INFO2 (0xfa000d10, | |
6383 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6384 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6385 | CSKY_ISA_VDSP), | |
6386 | OP32 ("vmov.u16.sl", | |
6387 | OPCODE_INFO2 (0xf8100d40, | |
6388 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6389 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6390 | CSKY_ISA_VDSP), | |
6391 | OP32 ("vmov.u32.sl", | |
6392 | OPCODE_INFO2 (0xfa000d40, | |
6393 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6394 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6395 | CSKY_ISA_VDSP), | |
6396 | OP32 ("vmov.s16.sl", | |
6397 | OPCODE_INFO2 (0xf8100d50, | |
6398 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6399 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6400 | CSKY_ISA_VDSP), | |
6401 | OP32 ("vmov.s32.sl", | |
6402 | OPCODE_INFO2 (0xfa000d50, | |
6403 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6404 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6405 | CSKY_ISA_VDSP), | |
6406 | OP32 ("vmov.u16.h", | |
6407 | OPCODE_INFO2 (0xf8100d60, | |
6408 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6409 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6410 | CSKY_ISA_VDSP), | |
6411 | OP32 ("vmov.u32.h", | |
6412 | OPCODE_INFO2 (0xfa000d60, | |
6413 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6414 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6415 | CSKY_ISA_VDSP), | |
6416 | OP32 ("vmov.s16.h", | |
6417 | OPCODE_INFO2 (0xf8100d70, | |
6418 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6419 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6420 | CSKY_ISA_VDSP), | |
6421 | OP32 ("vmov.s32.h", | |
6422 | OPCODE_INFO2 (0xfa000d70, | |
6423 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6424 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6425 | CSKY_ISA_VDSP), | |
6426 | OP32 ("vmov.u16.rh", | |
6427 | OPCODE_INFO2 (0xf8100d80, | |
6428 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6429 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6430 | CSKY_ISA_VDSP), | |
6431 | OP32 ("vmov.u32.rh", | |
6432 | OPCODE_INFO2 (0xfa000d80, | |
6433 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6434 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6435 | CSKY_ISA_VDSP), | |
6436 | OP32 ("vmov.s16.rh", | |
6437 | OPCODE_INFO2 (0xf8100d90, | |
6438 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6439 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6440 | CSKY_ISA_VDSP), | |
6441 | OP32 ("vmov.s32.rh", | |
6442 | OPCODE_INFO2 (0xfa000d90, | |
6443 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6444 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6445 | CSKY_ISA_VDSP), | |
6446 | OP32 ("vstou.u16.sl", | |
6447 | OPCODE_INFO2 (0xf8100dc0, | |
6448 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6449 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6450 | CSKY_ISA_VDSP), | |
6451 | OP32 ("vstou.u32.sl", | |
6452 | OPCODE_INFO2 (0xfa000dc0, | |
6453 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6454 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6455 | CSKY_ISA_VDSP), | |
6456 | OP32 ("vstou.s16.sl", | |
6457 | OPCODE_INFO2 (0xf8100dd0, | |
6458 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6459 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6460 | CSKY_ISA_VDSP), | |
6461 | OP32 ("vstou.s32.sl", | |
6462 | OPCODE_INFO2 (0xfa000dd0, | |
6463 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6464 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6465 | CSKY_ISA_VDSP), | |
6466 | OP32 ("vrev.8", | |
6467 | OPCODE_INFO2 (0xf8000e60, | |
6468 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6469 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6470 | CSKY_ISA_VDSP), | |
6471 | OP32 ("vrev.16", | |
6472 | OPCODE_INFO2 (0xf8100e60, | |
6473 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6474 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6475 | CSKY_ISA_VDSP), | |
6476 | OP32 ("vrev.32", | |
6477 | OPCODE_INFO2 (0xfa000e60, | |
6478 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6479 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6480 | CSKY_ISA_VDSP), | |
6481 | OP32 ("vcnt1.8", | |
6482 | OPCODE_INFO2 (0xf8000ea0, | |
6483 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6484 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6485 | CSKY_ISA_VDSP), | |
6486 | OP32 ("vclz.8", | |
6487 | OPCODE_INFO2 (0xf8000ec0, | |
6488 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6489 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6490 | CSKY_ISA_VDSP), | |
6491 | OP32 ("vclz.16", | |
6492 | OPCODE_INFO2 (0xf8100ec0, | |
6493 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6494 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6495 | CSKY_ISA_VDSP), | |
6496 | OP32 ("vclz.32", | |
6497 | OPCODE_INFO2 (0xfa000ec0, | |
6498 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6499 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6500 | CSKY_ISA_VDSP), | |
6501 | OP32 ("vcls.u8", | |
6502 | OPCODE_INFO2 (0xf8000ee0, | |
6503 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6504 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6505 | CSKY_ISA_VDSP), | |
6506 | OP32 ("vcls.u16", | |
6507 | OPCODE_INFO2 (0xf8100ee0, | |
6508 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6509 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6510 | CSKY_ISA_VDSP), | |
6511 | OP32 ("vcls.u32", | |
6512 | OPCODE_INFO2 (0xfa000ee0, | |
6513 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6514 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6515 | CSKY_ISA_VDSP), | |
6516 | OP32 ("vcls.s8", | |
6517 | OPCODE_INFO2 (0xf8000ef0, | |
6518 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6519 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6520 | CSKY_ISA_VDSP), | |
6521 | OP32 ("vcls.s16", | |
6522 | OPCODE_INFO2 (0xf8100ef0, | |
6523 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6524 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6525 | CSKY_ISA_VDSP), | |
6526 | OP32 ("vcls.s32", | |
6527 | OPCODE_INFO2 (0xfa000ef0, | |
6528 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6529 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6530 | CSKY_ISA_VDSP), | |
6531 | OP32 ("vabs.s8", | |
6532 | OPCODE_INFO2 (0xf8001010, | |
6533 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6534 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6535 | CSKY_ISA_VDSP), | |
6536 | OP32 ("vabs.s16", | |
6537 | OPCODE_INFO2 (0xf8101010, | |
6538 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6539 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6540 | CSKY_ISA_VDSP), | |
6541 | OP32 ("vabs.s32", | |
6542 | OPCODE_INFO2 (0xfa001010, | |
6543 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6544 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6545 | CSKY_ISA_VDSP), | |
6546 | OP32 ("vabs.u8.s", | |
6547 | OPCODE_INFO2 (0xf8001040, | |
6548 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6549 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6550 | CSKY_ISA_VDSP), | |
6551 | OP32 ("vabs.u16.s", | |
6552 | OPCODE_INFO2 (0xf8101040, | |
6553 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6554 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6555 | CSKY_ISA_VDSP), | |
6556 | OP32 ("vabs.u32.s", | |
6557 | OPCODE_INFO2 (0xfa001040, | |
6558 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6559 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6560 | CSKY_ISA_VDSP), | |
6561 | OP32 ("vabs.s8.s", | |
6562 | OPCODE_INFO2 (0xf8001050, | |
6563 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6564 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6565 | CSKY_ISA_VDSP), | |
6566 | OP32 ("vabs.s16.s", | |
6567 | OPCODE_INFO2 (0xf8101050, | |
6568 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6569 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6570 | CSKY_ISA_VDSP), | |
6571 | OP32 ("vabs.s32.s", | |
6572 | OPCODE_INFO2 (0xfa001050, | |
6573 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6574 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6575 | CSKY_ISA_VDSP), | |
6576 | OP32 ("vneg.u8", | |
6577 | OPCODE_INFO2 (0xf8001080, | |
6578 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6579 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6580 | CSKY_ISA_VDSP), | |
6581 | OP32 ("vneg.u16", | |
6582 | OPCODE_INFO2 (0xf8101080, | |
6583 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6584 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6585 | CSKY_ISA_VDSP), | |
6586 | OP32 ("vneg.u32", | |
6587 | OPCODE_INFO2 (0xfa001080, | |
6588 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6589 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6590 | CSKY_ISA_VDSP), | |
6591 | OP32 ("vneg.s8", | |
6592 | OPCODE_INFO2 (0xf8001090, | |
6593 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6594 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6595 | CSKY_ISA_VDSP), | |
6596 | OP32 ("vneg.s16", | |
6597 | OPCODE_INFO2 (0xf8101090, | |
6598 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6599 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6600 | CSKY_ISA_VDSP), | |
6601 | OP32 ("vneg.s32", | |
6602 | OPCODE_INFO2 (0xfa001090, | |
6603 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6604 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6605 | CSKY_ISA_VDSP), | |
6606 | OP32 ("vneg.u8.s", | |
6607 | OPCODE_INFO2 (0xf80010c0, | |
6608 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6609 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6610 | CSKY_ISA_VDSP), | |
6611 | OP32 ("vneg.u16.s", | |
6612 | OPCODE_INFO2 (0xf81010c0, | |
6613 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6614 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6615 | CSKY_ISA_VDSP), | |
6616 | OP32 ("vneg.u32.s", | |
6617 | OPCODE_INFO2 (0xfa0010c0, | |
6618 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6619 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6620 | CSKY_ISA_VDSP), | |
6621 | OP32 ("vneg.s8.s", | |
6622 | OPCODE_INFO2 (0xf80010d0, | |
6623 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6624 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6625 | CSKY_ISA_VDSP), | |
6626 | OP32 ("vneg.s16.s", | |
6627 | OPCODE_INFO2 (0xf81010d0, | |
6628 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6629 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6630 | CSKY_ISA_VDSP), | |
6631 | OP32 ("vneg.s32.s", | |
6632 | OPCODE_INFO2 (0xfa0010d0, | |
6633 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6634 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6635 | CSKY_ISA_VDSP), | |
6636 | OP32 ("vcmphsz.u8", | |
6637 | OPCODE_INFO2 (0xf8000880, | |
6638 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6639 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6640 | CSKY_ISA_VDSP), | |
6641 | OP32 ("vcmphsz.u16", | |
6642 | OPCODE_INFO2 (0xf8100880, | |
6643 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6644 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6645 | CSKY_ISA_VDSP), | |
6646 | OP32 ("vcmphsz.u32", | |
6647 | OPCODE_INFO2 (0xfa000880, | |
6648 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6649 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6650 | CSKY_ISA_VDSP), | |
6651 | OP32 ("vcmphsz.s8", | |
6652 | OPCODE_INFO2 (0xf8000890, | |
6653 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6654 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6655 | CSKY_ISA_VDSP), | |
6656 | OP32 ("vcmphsz.s16", | |
6657 | OPCODE_INFO2 (0xf8100890, | |
6658 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6659 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6660 | CSKY_ISA_VDSP), | |
6661 | OP32 ("vcmphsz.s32", | |
6662 | OPCODE_INFO2 (0xfa000890, | |
6663 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6664 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6665 | CSKY_ISA_VDSP), | |
6666 | OP32 ("vcmpltz.u8", | |
6667 | OPCODE_INFO2 (0xf80008a0, | |
6668 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6669 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6670 | CSKY_ISA_VDSP), | |
6671 | OP32 ("vcmpltz.u16", | |
6672 | OPCODE_INFO2 (0xf81008a0, | |
6673 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6674 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6675 | CSKY_ISA_VDSP), | |
6676 | OP32 ("vcmpltz.u32", | |
6677 | OPCODE_INFO2 (0xfa0008a0, | |
6678 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6679 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6680 | CSKY_ISA_VDSP), | |
6681 | OP32 ("vcmpltz.s8", | |
6682 | OPCODE_INFO2 (0xf80008b0, | |
6683 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6684 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6685 | CSKY_ISA_VDSP), | |
6686 | OP32 ("vcmpltz.s16", | |
6687 | OPCODE_INFO2 (0xf81008b0, | |
6688 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6689 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6690 | CSKY_ISA_VDSP), | |
6691 | OP32 ("vcmpltz.s32", | |
6692 | OPCODE_INFO2 (0xfa0008b0, | |
6693 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6694 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6695 | CSKY_ISA_VDSP), | |
6696 | OP32 ("vcmpnez.u8", | |
6697 | OPCODE_INFO2 (0xf80008c0, | |
6698 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6699 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6700 | CSKY_ISA_VDSP), | |
6701 | OP32 ("vcmpnez.u16", | |
6702 | OPCODE_INFO2 (0xf81008c0, | |
6703 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6704 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6705 | CSKY_ISA_VDSP), | |
6706 | OP32 ("vcmpnez.u32", | |
6707 | OPCODE_INFO2 (0xfa0008c0, | |
6708 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6709 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6710 | CSKY_ISA_VDSP), | |
6711 | OP32 ("vcmpnez.s8", | |
6712 | OPCODE_INFO2 (0xf80008d0, | |
6713 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6714 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6715 | CSKY_ISA_VDSP), | |
6716 | OP32 ("vcmpnez.s16", | |
6717 | OPCODE_INFO2 (0xf81008d0, | |
6718 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6719 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6720 | CSKY_ISA_VDSP), | |
6721 | OP32 ("vcmpnez.s32", | |
6722 | OPCODE_INFO2 (0xfa0008d0, | |
6723 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6724 | (16_19, VREG, OPRND_SHIFT_0_BIT)), | |
6725 | CSKY_ISA_VDSP), | |
6726 | OP32 ("vtrch.8", | |
6727 | OPCODE_INFO3 (0xf8000f40, | |
6728 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6729 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6730 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6731 | CSKY_ISA_VDSP), | |
6732 | OP32 ("vtrch.16", | |
6733 | OPCODE_INFO3 (0xf8100f40, | |
6734 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6735 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6736 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6737 | CSKY_ISA_VDSP), | |
6738 | OP32 ("vtrch.32", | |
6739 | OPCODE_INFO3 (0xfa000f40, | |
6740 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6741 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6742 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6743 | CSKY_ISA_VDSP), | |
6744 | OP32 ("vtrcl.8", | |
6745 | OPCODE_INFO3 (0xf8000f60, | |
6746 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6747 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6748 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6749 | CSKY_ISA_VDSP), | |
6750 | OP32 ("vtrcl.16", | |
6751 | OPCODE_INFO3 (0xf8100f60, | |
6752 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6753 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6754 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6755 | CSKY_ISA_VDSP), | |
6756 | OP32 ("vtrcl.32", | |
6757 | OPCODE_INFO3 (0xfa000f60, | |
6758 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6759 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6760 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6761 | CSKY_ISA_VDSP), | |
6762 | OP32 ("vadd.u8", | |
6763 | OPCODE_INFO3 (0xf8000000, | |
6764 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6765 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6766 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6767 | CSKY_ISA_VDSP), | |
6768 | OP32 ("vadd.u16", | |
6769 | OPCODE_INFO3 (0xf8100000, | |
6770 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6771 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6772 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6773 | CSKY_ISA_VDSP), | |
6774 | OP32 ("vadd.u32", | |
6775 | OPCODE_INFO3 (0xfa000000, | |
6776 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6777 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6778 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6779 | CSKY_ISA_VDSP), | |
6780 | OP32 ("vadd.s8", | |
6781 | OPCODE_INFO3 (0xf8000010, | |
6782 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6783 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6784 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6785 | CSKY_ISA_VDSP), | |
6786 | OP32 ("vadd.s16", | |
6787 | OPCODE_INFO3 (0xf8100010, | |
6788 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6789 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6790 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6791 | CSKY_ISA_VDSP), | |
6792 | OP32 ("vadd.s32", | |
6793 | OPCODE_INFO3 (0xfa000010, | |
6794 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6795 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6796 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6797 | CSKY_ISA_VDSP), | |
6798 | OP32 ("vadd.eu8", | |
6799 | OPCODE_INFO3 (0xf8000020, | |
6800 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6801 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6802 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6803 | CSKY_ISA_VDSP), | |
6804 | OP32 ("vadd.eu16", | |
6805 | OPCODE_INFO3 (0xf8100020, | |
6806 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6807 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6808 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6809 | CSKY_ISA_VDSP), | |
6810 | OP32 ("vadd.es8", | |
6811 | OPCODE_INFO3 (0xf8000030, | |
6812 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6813 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6814 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6815 | CSKY_ISA_VDSP), | |
6816 | OP32 ("vadd.es16", | |
6817 | OPCODE_INFO3 (0xf8100030, | |
6818 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6819 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6820 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6821 | CSKY_ISA_VDSP), | |
6822 | OP32 ("vcadd.u8", | |
6823 | OPCODE_INFO3 (0xf8000040, | |
6824 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6825 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6826 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6827 | CSKY_ISA_VDSP), | |
6828 | OP32 ("vcadd.u16", | |
6829 | OPCODE_INFO3 (0xf8100040, | |
6830 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6831 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6832 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6833 | CSKY_ISA_VDSP), | |
6834 | OP32 ("vcadd.u32", | |
6835 | OPCODE_INFO3 (0xfa000040, | |
6836 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6837 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6838 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6839 | CSKY_ISA_VDSP), | |
6840 | OP32 ("vcadd.s8", | |
6841 | OPCODE_INFO3 (0xf8000050, | |
6842 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6843 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6844 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6845 | CSKY_ISA_VDSP), | |
6846 | OP32 ("vcadd.s16", | |
6847 | OPCODE_INFO3 (0xf8100050, | |
6848 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6849 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6850 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6851 | CSKY_ISA_VDSP), | |
6852 | OP32 ("vcadd.s32", | |
6853 | OPCODE_INFO3 (0xfa000050, | |
6854 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6855 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6856 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6857 | CSKY_ISA_VDSP), | |
6858 | OP32 ("vadd.xu16.sl", | |
6859 | OPCODE_INFO3 (0xf8100140, | |
6860 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6861 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6862 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6863 | CSKY_ISA_VDSP), | |
6864 | OP32 ("vadd.xu32.sl", | |
6865 | OPCODE_INFO3 (0xfa000140, | |
6866 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6867 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6868 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6869 | CSKY_ISA_VDSP), | |
6870 | OP32 ("vadd.xs16.sl", | |
6871 | OPCODE_INFO3 (0xf8100150, | |
6872 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6873 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6874 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6875 | CSKY_ISA_VDSP), | |
6876 | OP32 ("vadd.xs32.sl", | |
6877 | OPCODE_INFO3 (0xfa000150, | |
6878 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6879 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6880 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6881 | CSKY_ISA_VDSP), | |
6882 | OP32 ("vadd.xu16", | |
6883 | OPCODE_INFO3 (0xf8100160, | |
6884 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6885 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6886 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6887 | CSKY_ISA_VDSP), | |
6888 | OP32 ("vadd.xu32", | |
6889 | OPCODE_INFO3 (0xfa000160, | |
6890 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6891 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6892 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6893 | CSKY_ISA_VDSP), | |
6894 | OP32 ("vadd.xs16", | |
6895 | OPCODE_INFO3 (0xf8100170, | |
6896 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6897 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6898 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6899 | CSKY_ISA_VDSP), | |
6900 | OP32 ("vadd.xs32", | |
6901 | OPCODE_INFO3 (0xfa000170, | |
6902 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6903 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6904 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6905 | CSKY_ISA_VDSP), | |
6906 | OP32 ("vaddh.u8", | |
6907 | OPCODE_INFO3 (0xf8000180, | |
6908 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6909 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6910 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6911 | CSKY_ISA_VDSP), | |
6912 | OP32 ("vaddh.u16", | |
6913 | OPCODE_INFO3 (0xf8100180, | |
6914 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6915 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6916 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6917 | CSKY_ISA_VDSP), | |
6918 | OP32 ("vaddh.u32", | |
6919 | OPCODE_INFO3 (0xfa000180, | |
6920 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6921 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6922 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6923 | CSKY_ISA_VDSP), | |
6924 | OP32 ("vaddh.s8", | |
6925 | OPCODE_INFO3 (0xf8000190, | |
6926 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6927 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6928 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6929 | CSKY_ISA_VDSP), | |
6930 | OP32 ("vaddh.s16", | |
6931 | OPCODE_INFO3 (0xf8100190, | |
6932 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6933 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6934 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6935 | CSKY_ISA_VDSP), | |
6936 | OP32 ("vaddh.s32", | |
6937 | OPCODE_INFO3 (0xfa000190, | |
6938 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6939 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6940 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6941 | CSKY_ISA_VDSP), | |
6942 | OP32 ("vaddh.u8.r", | |
6943 | OPCODE_INFO3 (0xf80001a0, | |
6944 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6945 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6946 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6947 | CSKY_ISA_VDSP), | |
6948 | OP32 ("vaddh.u16.r", | |
6949 | OPCODE_INFO3 (0xf81001a0, | |
6950 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6951 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6952 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6953 | CSKY_ISA_VDSP), | |
6954 | OP32 ("vaddh.u32.r", | |
6955 | OPCODE_INFO3 (0xfa0001a0, | |
6956 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6957 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6958 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6959 | CSKY_ISA_VDSP), | |
6960 | OP32 ("vaddh.s8.r", | |
6961 | OPCODE_INFO3 (0xf80001b0, | |
6962 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6963 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6964 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6965 | CSKY_ISA_VDSP), | |
6966 | OP32 ("vaddh.s16.r", | |
6967 | OPCODE_INFO3 (0xf81001b0, | |
6968 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6969 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6970 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6971 | CSKY_ISA_VDSP), | |
6972 | OP32 ("vaddh.s32.r", | |
6973 | OPCODE_INFO3 (0xfa0001b0, | |
6974 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6975 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6976 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6977 | CSKY_ISA_VDSP), | |
6978 | OP32 ("vadd.u8.s", | |
6979 | OPCODE_INFO3 (0xf80001c0, | |
6980 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6981 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6982 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6983 | CSKY_ISA_VDSP), | |
6984 | OP32 ("vadd.u16.s", | |
6985 | OPCODE_INFO3 (0xf81001c0, | |
6986 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6987 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6988 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6989 | CSKY_ISA_VDSP), | |
6990 | OP32 ("vadd.u32.s", | |
6991 | OPCODE_INFO3 (0xfa0001c0, | |
6992 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6993 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
6994 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
6995 | CSKY_ISA_VDSP), | |
6996 | OP32 ("vadd.s8.s", | |
6997 | OPCODE_INFO3 (0xf80001d0, | |
6998 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
6999 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7000 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7001 | CSKY_ISA_VDSP), | |
7002 | OP32 ("vadd.s16.s", | |
7003 | OPCODE_INFO3 (0xf81001d0, | |
7004 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7005 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7006 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7007 | CSKY_ISA_VDSP), | |
7008 | OP32 ("vadd.s32.s", | |
7009 | OPCODE_INFO3 (0xfa0001d0, | |
7010 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7011 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7012 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7013 | CSKY_ISA_VDSP), | |
7014 | OP32 ("vsub.u8", | |
7015 | OPCODE_INFO3 (0xf8000200, | |
7016 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7017 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7018 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7019 | CSKY_ISA_VDSP), | |
7020 | OP32 ("vsub.u16", | |
7021 | OPCODE_INFO3 (0xf8100200, | |
7022 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7023 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7024 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7025 | CSKY_ISA_VDSP), | |
7026 | OP32 ("vsub.u32", | |
7027 | OPCODE_INFO3 (0xfa000200, | |
7028 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7029 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7030 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7031 | CSKY_ISA_VDSP), | |
7032 | OP32 ("vsub.s8", | |
7033 | OPCODE_INFO3 (0xf8000210, | |
7034 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7035 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7036 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7037 | CSKY_ISA_VDSP), | |
7038 | OP32 ("vsub.s16", | |
7039 | OPCODE_INFO3 (0xf8100210, | |
7040 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7041 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7042 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7043 | CSKY_ISA_VDSP), | |
7044 | OP32 ("vsub.s32", | |
7045 | OPCODE_INFO3 (0xfa000210, | |
7046 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7047 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7048 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7049 | CSKY_ISA_VDSP), | |
7050 | OP32 ("vsub.eu8", | |
7051 | OPCODE_INFO3 (0xf8000220, | |
7052 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7053 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7054 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7055 | CSKY_ISA_VDSP), | |
7056 | OP32 ("vsub.eu16", | |
7057 | OPCODE_INFO3 (0xf8100220, | |
7058 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7059 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7060 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7061 | CSKY_ISA_VDSP), | |
7062 | OP32 ("vsub.eu32", | |
7063 | OPCODE_INFO3 (0xfa000220, | |
7064 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7065 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7066 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7067 | CSKY_ISA_VDSP), | |
7068 | OP32 ("vsub.es8", | |
7069 | OPCODE_INFO3 (0xf8000230, | |
7070 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7071 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7072 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7073 | CSKY_ISA_VDSP), | |
7074 | OP32 ("vsub.es16", | |
7075 | OPCODE_INFO3 (0xf8100230, | |
7076 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7077 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7078 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7079 | CSKY_ISA_VDSP), | |
7080 | OP32 ("vsub.es32", | |
7081 | OPCODE_INFO3 (0xfa000230, | |
7082 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7083 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7084 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7085 | CSKY_ISA_VDSP), | |
7086 | OP32 ("vsabs.u8", | |
7087 | OPCODE_INFO3 (0xf8000240, | |
7088 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7089 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7090 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7091 | CSKY_ISA_VDSP), | |
7092 | OP32 ("vsabs.u16", | |
7093 | OPCODE_INFO3 (0xf8100240, | |
7094 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7095 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7096 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7097 | CSKY_ISA_VDSP), | |
7098 | OP32 ("vsabs.u32", | |
7099 | OPCODE_INFO3 (0xfa000240, | |
7100 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7101 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7102 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7103 | CSKY_ISA_VDSP), | |
7104 | OP32 ("vsabs.s8", | |
7105 | OPCODE_INFO3 (0xf8000250, | |
7106 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7107 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7108 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7109 | CSKY_ISA_VDSP), | |
7110 | OP32 ("vsabs.s16", | |
7111 | OPCODE_INFO3 (0xf8100250, | |
7112 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7113 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7114 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7115 | CSKY_ISA_VDSP), | |
7116 | OP32 ("vsabs.s32", | |
7117 | OPCODE_INFO3 (0xfa000250, | |
7118 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7119 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7120 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7121 | CSKY_ISA_VDSP), | |
7122 | OP32 ("vsabs.eu8", | |
7123 | OPCODE_INFO3 (0xf8000260, | |
7124 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7125 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7126 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7127 | CSKY_ISA_VDSP), | |
7128 | OP32 ("vsabs.eu16", | |
7129 | OPCODE_INFO3 (0xf8100260, | |
7130 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7131 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7132 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7133 | CSKY_ISA_VDSP), | |
7134 | OP32 ("vsabs.es8", | |
7135 | OPCODE_INFO3 (0xf8000270, | |
7136 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7137 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7138 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7139 | CSKY_ISA_VDSP), | |
7140 | OP32 ("vsabs.es16", | |
7141 | OPCODE_INFO3 (0xf8100270, | |
7142 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7143 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7144 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7145 | CSKY_ISA_VDSP), | |
7146 | OP32 ("vsabsa.u8", | |
7147 | OPCODE_INFO3 (0xf8000280, | |
7148 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7149 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7150 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7151 | CSKY_ISA_VDSP), | |
7152 | OP32 ("vsabsa.u16", | |
7153 | OPCODE_INFO3 (0xf8100280, | |
7154 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7155 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7156 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7157 | CSKY_ISA_VDSP), | |
7158 | OP32 ("vsabsa.u32", | |
7159 | OPCODE_INFO3 (0xfa000280, | |
7160 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7161 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7162 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7163 | CSKY_ISA_VDSP), | |
7164 | OP32 ("vsabsa.s8", | |
7165 | OPCODE_INFO3 (0xf8000290, | |
7166 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7167 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7168 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7169 | CSKY_ISA_VDSP), | |
7170 | OP32 ("vsabsa.s16", | |
7171 | OPCODE_INFO3 (0xf8100290, | |
7172 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7173 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7174 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7175 | CSKY_ISA_VDSP), | |
7176 | OP32 ("vsabsa.s32", | |
7177 | OPCODE_INFO3 (0xfa000290, | |
7178 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7179 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7180 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7181 | CSKY_ISA_VDSP), | |
7182 | OP32 ("vsabsa.eu8", | |
7183 | OPCODE_INFO3 (0xf80002a0, | |
7184 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7185 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7186 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7187 | CSKY_ISA_VDSP), | |
7188 | OP32 ("vsabsa.eu16", | |
7189 | OPCODE_INFO3 (0xf81002a0, | |
7190 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7191 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7192 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7193 | CSKY_ISA_VDSP), | |
7194 | OP32 ("vsabsa.es8", | |
7195 | OPCODE_INFO3 (0xf80002b0, | |
7196 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7197 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7198 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7199 | CSKY_ISA_VDSP), | |
7200 | OP32 ("vsabsa.es16", | |
7201 | OPCODE_INFO3 (0xf81002b0, | |
7202 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7203 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7204 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7205 | CSKY_ISA_VDSP), | |
7206 | OP32 ("vsub.xu16", | |
7207 | OPCODE_INFO3 (0xf8100360, | |
7208 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7209 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7210 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7211 | CSKY_ISA_VDSP), | |
7212 | OP32 ("vsub.xu32", | |
7213 | OPCODE_INFO3 (0xfa000360, | |
7214 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7215 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7216 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7217 | CSKY_ISA_VDSP), | |
7218 | OP32 ("vsub.xs16", | |
7219 | OPCODE_INFO3 (0xf8100370, | |
7220 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7221 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7222 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7223 | CSKY_ISA_VDSP), | |
7224 | OP32 ("vsub.xs32", | |
7225 | OPCODE_INFO3 (0xfa000370, | |
7226 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7227 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7228 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7229 | CSKY_ISA_VDSP), | |
7230 | OP32 ("vsubh.u8", | |
7231 | OPCODE_INFO3 (0xf8000380, | |
7232 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7233 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7234 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7235 | CSKY_ISA_VDSP), | |
7236 | OP32 ("vsubh.u16", | |
7237 | OPCODE_INFO3 (0xf8100380, | |
7238 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7239 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7240 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7241 | CSKY_ISA_VDSP), | |
7242 | OP32 ("vsubh.u32", | |
7243 | OPCODE_INFO3 (0xfa000380, | |
7244 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7245 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7246 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7247 | CSKY_ISA_VDSP), | |
7248 | OP32 ("vsubh.s8", | |
7249 | OPCODE_INFO3 (0xf8000390, | |
7250 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7251 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7252 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7253 | CSKY_ISA_VDSP), | |
7254 | OP32 ("vsubh.s16", | |
7255 | OPCODE_INFO3 (0xf8100390, | |
7256 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7257 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7258 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7259 | CSKY_ISA_VDSP), | |
7260 | OP32 ("vsubh.s32", | |
7261 | OPCODE_INFO3 (0xfa000390, | |
7262 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7263 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7264 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7265 | CSKY_ISA_VDSP), | |
7266 | OP32 ("vsubh.u8.r", | |
7267 | OPCODE_INFO3 (0xf80003a0, | |
7268 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7269 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7270 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7271 | CSKY_ISA_VDSP), | |
7272 | OP32 ("vsubh.u16.r", | |
7273 | OPCODE_INFO3 (0xf81003a0, | |
7274 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7275 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7276 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7277 | CSKY_ISA_VDSP), | |
7278 | OP32 ("vsubh.u32.r", | |
7279 | OPCODE_INFO3 (0xfa0003a0, | |
7280 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7281 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7282 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7283 | CSKY_ISA_VDSP), | |
7284 | OP32 ("vsubh.s8.r", | |
7285 | OPCODE_INFO3 (0xf80003b0, | |
7286 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7287 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7288 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7289 | CSKY_ISA_VDSP), | |
7290 | OP32 ("vsubh.s16.r", | |
7291 | OPCODE_INFO3 (0xf81003b0, | |
7292 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7293 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7294 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7295 | CSKY_ISA_VDSP), | |
7296 | OP32 ("vsubh.s32.r", | |
7297 | OPCODE_INFO3 (0xfa0003b0, | |
7298 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7299 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7300 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7301 | CSKY_ISA_VDSP), | |
7302 | OP32 ("vsub.u8.s", | |
7303 | OPCODE_INFO3 (0xf80003c0, | |
7304 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7305 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7306 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7307 | CSKY_ISA_VDSP), | |
7308 | OP32 ("vsub.u16.s", | |
7309 | OPCODE_INFO3 (0xf81003c0, | |
7310 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7311 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7312 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7313 | CSKY_ISA_VDSP), | |
7314 | OP32 ("vsub.u32.s", | |
7315 | OPCODE_INFO3 (0xfa0003c0, | |
7316 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7317 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7318 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7319 | CSKY_ISA_VDSP), | |
7320 | OP32 ("vsub.s8.s", | |
7321 | OPCODE_INFO3 (0xf80003d0, | |
7322 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7323 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7324 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7325 | CSKY_ISA_VDSP), | |
7326 | OP32 ("vsub.s16.s", | |
7327 | OPCODE_INFO3 (0xf81003d0, | |
7328 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7329 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7330 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7331 | CSKY_ISA_VDSP), | |
7332 | OP32 ("vsub.s32.s", | |
7333 | OPCODE_INFO3 (0xfa0003d0, | |
7334 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7335 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7336 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7337 | CSKY_ISA_VDSP), | |
7338 | OP32 ("vmul.u8", | |
7339 | OPCODE_INFO3 (0xf8000400, | |
7340 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7341 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7342 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7343 | CSKY_ISA_VDSP), | |
7344 | OP32 ("vmul.u16", | |
7345 | OPCODE_INFO3 (0xf8100400, | |
7346 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7347 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7348 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7349 | CSKY_ISA_VDSP), | |
7350 | OP32 ("vmul.u32", | |
7351 | OPCODE_INFO3 (0xfa000400, | |
7352 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7353 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7354 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7355 | CSKY_ISA_VDSP), | |
7356 | OP32 ("vmul.s8", | |
7357 | OPCODE_INFO3 (0xf8000410, | |
7358 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7359 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7360 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7361 | CSKY_ISA_VDSP), | |
7362 | OP32 ("vmul.s16", | |
7363 | OPCODE_INFO3 (0xf8100410, | |
7364 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7365 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7366 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7367 | CSKY_ISA_VDSP), | |
7368 | OP32 ("vmul.s32", | |
7369 | OPCODE_INFO3 (0xfa000410, | |
7370 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7371 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7372 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7373 | CSKY_ISA_VDSP), | |
7374 | OP32 ("vmul.eu8", | |
7375 | OPCODE_INFO3 (0xf8000420, | |
7376 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7377 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7378 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7379 | CSKY_ISA_VDSP), | |
7380 | OP32 ("vmul.eu16", | |
7381 | OPCODE_INFO3 (0xf8100420, | |
7382 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7383 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7384 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7385 | CSKY_ISA_VDSP), | |
7386 | OP32 ("vmul.es8", | |
7387 | OPCODE_INFO3 (0xf8000430, | |
7388 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7389 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7390 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7391 | CSKY_ISA_VDSP), | |
7392 | OP32 ("vmul.es16", | |
7393 | OPCODE_INFO3 (0xf8100430, | |
7394 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7395 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7396 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7397 | CSKY_ISA_VDSP), | |
7398 | OP32 ("vmula.u8", | |
7399 | OPCODE_INFO3 (0xf8000440, | |
7400 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7401 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7402 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7403 | CSKY_ISA_VDSP), | |
7404 | OP32 ("vmula.u16", | |
7405 | OPCODE_INFO3 (0xf8100440, | |
7406 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7407 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7408 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7409 | CSKY_ISA_VDSP), | |
7410 | OP32 ("vmula.u32", | |
7411 | OPCODE_INFO3 (0xfa000440, | |
7412 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7413 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7414 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7415 | CSKY_ISA_VDSP), | |
7416 | OP32 ("vmula.s8", | |
7417 | OPCODE_INFO3 (0xf8000450, | |
7418 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7419 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7420 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7421 | CSKY_ISA_VDSP), | |
7422 | OP32 ("vmula.s16", | |
7423 | OPCODE_INFO3 (0xf8100450, | |
7424 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7425 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7426 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7427 | CSKY_ISA_VDSP), | |
7428 | OP32 ("vmula.s32", | |
7429 | OPCODE_INFO3 (0xfa000450, | |
7430 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7431 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7432 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7433 | CSKY_ISA_VDSP), | |
7434 | OP32 ("vmula.eu8", | |
7435 | OPCODE_INFO3 (0xf8000460, | |
7436 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7437 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7438 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7439 | CSKY_ISA_VDSP), | |
7440 | OP32 ("vmula.eu16", | |
7441 | OPCODE_INFO3 (0xf8100460, | |
7442 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7443 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7444 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7445 | CSKY_ISA_VDSP), | |
7446 | OP32 ("vmula.eu32", | |
7447 | OPCODE_INFO3 (0xfa000460, | |
7448 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7449 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7450 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7451 | CSKY_ISA_VDSP), | |
7452 | OP32 ("vmula.es8", | |
7453 | OPCODE_INFO3 (0xf8000470, | |
7454 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7455 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7456 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7457 | CSKY_ISA_VDSP), | |
7458 | OP32 ("vmula.es16", | |
7459 | OPCODE_INFO3 (0xf8100470, | |
7460 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7461 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7462 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7463 | CSKY_ISA_VDSP), | |
7464 | OP32 ("vmula.es32", | |
7465 | OPCODE_INFO3 (0xfa000470, | |
7466 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7467 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7468 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7469 | CSKY_ISA_VDSP), | |
7470 | OP32 ("vmuls.u8", | |
7471 | OPCODE_INFO3 (0xf8000480, | |
7472 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7473 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7474 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7475 | CSKY_ISA_VDSP), | |
7476 | OP32 ("vmuls.u16", | |
7477 | OPCODE_INFO3 (0xf8100480, | |
7478 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7479 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7480 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7481 | CSKY_ISA_VDSP), | |
7482 | OP32 ("vmuls.u32", | |
7483 | OPCODE_INFO3 (0xfa000480, | |
7484 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7485 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7486 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7487 | CSKY_ISA_VDSP), | |
7488 | OP32 ("vmuls.s8", | |
7489 | OPCODE_INFO3 (0xf8000490, | |
7490 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7491 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7492 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7493 | CSKY_ISA_VDSP), | |
7494 | OP32 ("vmuls.s16", | |
7495 | OPCODE_INFO3 (0xf8100490, | |
7496 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7497 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7498 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7499 | CSKY_ISA_VDSP), | |
7500 | OP32 ("vmuls.s32", | |
7501 | OPCODE_INFO3 (0xfa000490, | |
7502 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7503 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7504 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7505 | CSKY_ISA_VDSP), | |
7506 | OP32 ("vmuls.eu8", | |
7507 | OPCODE_INFO3 (0xf80004a0, | |
7508 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7509 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7510 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7511 | CSKY_ISA_VDSP), | |
7512 | OP32 ("vmuls.eu16", | |
7513 | OPCODE_INFO3 (0xf81004a0, | |
7514 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7515 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7516 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7517 | CSKY_ISA_VDSP), | |
7518 | OP32 ("vmuls.es8", | |
7519 | OPCODE_INFO3 (0xf80004b0, | |
7520 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7521 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7522 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7523 | CSKY_ISA_VDSP), | |
7524 | OP32 ("vmuls.es16", | |
7525 | OPCODE_INFO3 (0xf81004b0, | |
7526 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7527 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7528 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7529 | CSKY_ISA_VDSP), | |
7530 | OP32 ("vshr.u8", | |
7531 | OPCODE_INFO3 (0xf8000680, | |
7532 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7533 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7534 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7535 | CSKY_ISA_VDSP), | |
7536 | OP32 ("vshr.u16", | |
7537 | OPCODE_INFO3 (0xf8100680, | |
7538 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7539 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7540 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7541 | CSKY_ISA_VDSP), | |
7542 | OP32 ("vshr.u32", | |
7543 | OPCODE_INFO3 (0xfa000680, | |
7544 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7545 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7546 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7547 | CSKY_ISA_VDSP), | |
7548 | OP32 ("vshr.s8", | |
7549 | OPCODE_INFO3 (0xf8000690, | |
7550 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7551 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7552 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7553 | CSKY_ISA_VDSP), | |
7554 | OP32 ("vshr.s16", | |
7555 | OPCODE_INFO3 (0xf8100690, | |
7556 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7557 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7558 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7559 | CSKY_ISA_VDSP), | |
7560 | OP32 ("vshr.s32", | |
7561 | OPCODE_INFO3 (0xfa000690, | |
7562 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7563 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7564 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7565 | CSKY_ISA_VDSP), | |
7566 | OP32 ("vshr.u8.r", | |
7567 | OPCODE_INFO3 (0xf80006c0, | |
7568 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7569 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7570 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7571 | CSKY_ISA_VDSP), | |
7572 | OP32 ("vshr.u16.r", | |
7573 | OPCODE_INFO3 (0xf81006c0, | |
7574 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7575 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7576 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7577 | CSKY_ISA_VDSP), | |
7578 | OP32 ("vshr.u32.r", | |
7579 | OPCODE_INFO3 (0xfa0006c0, | |
7580 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7581 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7582 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7583 | CSKY_ISA_VDSP), | |
7584 | OP32 ("vshr.s8.r", | |
7585 | OPCODE_INFO3 (0xf80006d0, | |
7586 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7587 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7588 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7589 | CSKY_ISA_VDSP), | |
7590 | OP32 ("vshr.s16.r", | |
7591 | OPCODE_INFO3 (0xf81006d0, | |
7592 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7593 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7594 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7595 | CSKY_ISA_VDSP), | |
7596 | OP32 ("vshr.s32.r", | |
7597 | OPCODE_INFO3 (0xfa0006d0, | |
7598 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7599 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7600 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7601 | CSKY_ISA_VDSP), | |
7602 | OP32 ("vshl.u8", | |
7603 | OPCODE_INFO3 (0xf8000780, | |
7604 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7605 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7606 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7607 | CSKY_ISA_VDSP), | |
7608 | OP32 ("vshl.u16", | |
7609 | OPCODE_INFO3 (0xf8100780, | |
7610 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7611 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7612 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7613 | CSKY_ISA_VDSP), | |
7614 | OP32 ("vshl.u32", | |
7615 | OPCODE_INFO3 (0xfa000780, | |
7616 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7617 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7618 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7619 | CSKY_ISA_VDSP), | |
7620 | OP32 ("vshl.s8", | |
7621 | OPCODE_INFO3 (0xf8000790, | |
7622 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7623 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7624 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7625 | CSKY_ISA_VDSP), | |
7626 | OP32 ("vshl.s16", | |
7627 | OPCODE_INFO3 (0xf8100790, | |
7628 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7629 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7630 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7631 | CSKY_ISA_VDSP), | |
7632 | OP32 ("vshl.s32", | |
7633 | OPCODE_INFO3 (0xfa000790, | |
7634 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7635 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7636 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7637 | CSKY_ISA_VDSP), | |
7638 | OP32 ("vshl.u8.s", | |
7639 | OPCODE_INFO3 (0xf80007c0, | |
7640 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7641 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7642 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7643 | CSKY_ISA_VDSP), | |
7644 | OP32 ("vshl.u16.s", | |
7645 | OPCODE_INFO3 (0xf81007c0, | |
7646 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7647 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7648 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7649 | CSKY_ISA_VDSP), | |
7650 | OP32 ("vshl.u32.s", | |
7651 | OPCODE_INFO3 (0xfa0007c0, | |
7652 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7653 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7654 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7655 | CSKY_ISA_VDSP), | |
7656 | OP32 ("vshl.s8.s", | |
7657 | OPCODE_INFO3 (0xf80007d0, | |
7658 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7659 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7660 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7661 | CSKY_ISA_VDSP), | |
7662 | OP32 ("vshl.s16.s", | |
7663 | OPCODE_INFO3 (0xf81007d0, | |
7664 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7665 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7666 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7667 | CSKY_ISA_VDSP), | |
7668 | OP32 ("vshl.s32.s", | |
7669 | OPCODE_INFO3 (0xfa0007d0, | |
7670 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7671 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7672 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7673 | CSKY_ISA_VDSP), | |
7674 | OP32 ("vcmphs.u8", | |
7675 | OPCODE_INFO3 (0xf8000800, | |
7676 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7677 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7678 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7679 | CSKY_ISA_VDSP), | |
7680 | OP32 ("vcmphs.u16", | |
7681 | OPCODE_INFO3 (0xf8100800, | |
7682 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7683 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7684 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7685 | CSKY_ISA_VDSP), | |
7686 | OP32 ("vcmphs.u32", | |
7687 | OPCODE_INFO3 (0xfa000800, | |
7688 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7689 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7690 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7691 | CSKY_ISA_VDSP), | |
7692 | OP32 ("vcmphs.s8", | |
7693 | OPCODE_INFO3 (0xf8000810, | |
7694 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7695 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7696 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7697 | CSKY_ISA_VDSP), | |
7698 | OP32 ("vcmphs.s16", | |
7699 | OPCODE_INFO3 (0xf8100810, | |
7700 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7701 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7702 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7703 | CSKY_ISA_VDSP), | |
7704 | OP32 ("vcmphs.s32", | |
7705 | OPCODE_INFO3 (0xfa000810, | |
7706 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7707 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7708 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7709 | CSKY_ISA_VDSP), | |
7710 | OP32 ("vcmplt.u8", | |
7711 | OPCODE_INFO3 (0xf8000820, | |
7712 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7713 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7714 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7715 | CSKY_ISA_VDSP), | |
7716 | OP32 ("vcmplt.u16", | |
7717 | OPCODE_INFO3 (0xf8100820, | |
7718 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7719 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7720 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7721 | CSKY_ISA_VDSP), | |
7722 | OP32 ("vcmplt.u32", | |
7723 | OPCODE_INFO3 (0xfa000820, | |
7724 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7725 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7726 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7727 | CSKY_ISA_VDSP), | |
7728 | OP32 ("vcmplt.s8", | |
7729 | OPCODE_INFO3 (0xf8000830, | |
7730 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7731 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7732 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7733 | CSKY_ISA_VDSP), | |
7734 | OP32 ("vcmplt.s16", | |
7735 | OPCODE_INFO3 (0xf8100830, | |
7736 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7737 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7738 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7739 | CSKY_ISA_VDSP), | |
7740 | OP32 ("vcmplt.s32", | |
7741 | OPCODE_INFO3 (0xfa000830, | |
7742 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7743 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7744 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7745 | CSKY_ISA_VDSP), | |
7746 | OP32 ("vcmpne.u8", | |
7747 | OPCODE_INFO3 (0xf8000840, | |
7748 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7749 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7750 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7751 | CSKY_ISA_VDSP), | |
7752 | OP32 ("vcmpne.u16", | |
7753 | OPCODE_INFO3 (0xf8100840, | |
7754 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7755 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7756 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7757 | CSKY_ISA_VDSP), | |
7758 | OP32 ("vcmpne.u32", | |
7759 | OPCODE_INFO3 (0xfa000840, | |
7760 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7761 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7762 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7763 | CSKY_ISA_VDSP), | |
7764 | OP32 ("vcmpne.s8", | |
7765 | OPCODE_INFO3 (0xf8000850, | |
7766 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7767 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7768 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7769 | CSKY_ISA_VDSP), | |
7770 | OP32 ("vcmpne.s16", | |
7771 | OPCODE_INFO3 (0xf8100850, | |
7772 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7773 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7774 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7775 | CSKY_ISA_VDSP), | |
7776 | OP32 ("vcmpne.s32", | |
7777 | OPCODE_INFO3 (0xfa000850, | |
7778 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7779 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7780 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7781 | CSKY_ISA_VDSP), | |
7782 | OP32 ("vmax.u8", | |
7783 | OPCODE_INFO3 (0xf8000900, | |
7784 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7785 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7786 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7787 | CSKY_ISA_VDSP), | |
7788 | OP32 ("vmax.u16", | |
7789 | OPCODE_INFO3 (0xf8100900, | |
7790 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7791 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7792 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7793 | CSKY_ISA_VDSP), | |
7794 | OP32 ("vmax.u32", | |
7795 | OPCODE_INFO3 (0xfa000900, | |
7796 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7797 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7798 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7799 | CSKY_ISA_VDSP), | |
7800 | OP32 ("vmax.s8", | |
7801 | OPCODE_INFO3 (0xf8000910, | |
7802 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7803 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7804 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7805 | CSKY_ISA_VDSP), | |
7806 | OP32 ("vmax.s16", | |
7807 | OPCODE_INFO3 (0xf8100910, | |
7808 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7809 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7810 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7811 | CSKY_ISA_VDSP), | |
7812 | OP32 ("vmax.s32", | |
7813 | OPCODE_INFO3 (0xfa000910, | |
7814 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7815 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7816 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7817 | CSKY_ISA_VDSP), | |
7818 | OP32 ("vmin.u8", | |
7819 | OPCODE_INFO3 (0xf8000920, | |
7820 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7821 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7822 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7823 | CSKY_ISA_VDSP), | |
7824 | OP32 ("vmin.u16", | |
7825 | OPCODE_INFO3 (0xf8100920, | |
7826 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7827 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7828 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7829 | CSKY_ISA_VDSP), | |
7830 | OP32 ("vmin.u32", | |
7831 | OPCODE_INFO3 (0xfa000920, | |
7832 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7833 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7834 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7835 | CSKY_ISA_VDSP), | |
7836 | OP32 ("vmin.s8", | |
7837 | OPCODE_INFO3 (0xf8000930, | |
7838 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7839 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7840 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7841 | CSKY_ISA_VDSP), | |
7842 | OP32 ("vmin.s16", | |
7843 | OPCODE_INFO3 (0xf8100930, | |
7844 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7845 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7846 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7847 | CSKY_ISA_VDSP), | |
7848 | OP32 ("vmin.s32", | |
7849 | OPCODE_INFO3 (0xfa000930, | |
7850 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7851 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7852 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7853 | CSKY_ISA_VDSP), | |
7854 | OP32 ("vcmax.u8", | |
7855 | OPCODE_INFO3 (0xf8000980, | |
7856 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7857 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7858 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7859 | CSKY_ISA_VDSP), | |
7860 | OP32 ("vcmax.u16", | |
7861 | OPCODE_INFO3 (0xf8100980, | |
7862 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7863 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7864 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7865 | CSKY_ISA_VDSP), | |
7866 | OP32 ("vcmax.u32", | |
7867 | OPCODE_INFO3 (0xfa000980, | |
7868 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7869 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7870 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7871 | CSKY_ISA_VDSP), | |
7872 | OP32 ("vcmax.s8", | |
7873 | OPCODE_INFO3 (0xf8000990, | |
7874 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7875 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7876 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7877 | CSKY_ISA_VDSP), | |
7878 | OP32 ("vcmax.s16", | |
7879 | OPCODE_INFO3 (0xf8100990, | |
7880 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7881 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7882 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7883 | CSKY_ISA_VDSP), | |
7884 | OP32 ("vcmax.s32", | |
7885 | OPCODE_INFO3 (0xfa000990, | |
7886 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7887 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7888 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7889 | CSKY_ISA_VDSP), | |
7890 | OP32 ("vcmin.u8", | |
7891 | OPCODE_INFO3 (0xf80009a0, | |
7892 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7893 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7894 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7895 | CSKY_ISA_VDSP), | |
7896 | OP32 ("vcmin.u16", | |
7897 | OPCODE_INFO3 (0xf81009a0, | |
7898 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7899 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7900 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7901 | CSKY_ISA_VDSP), | |
7902 | OP32 ("vcmin.u32", | |
7903 | OPCODE_INFO3 (0xfa0009a0, | |
7904 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7905 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7906 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7907 | CSKY_ISA_VDSP), | |
7908 | OP32 ("vcmin.s8", | |
7909 | OPCODE_INFO3 (0xf80009b0, | |
7910 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7911 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7912 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7913 | CSKY_ISA_VDSP), | |
7914 | OP32 ("vcmin.s16", | |
7915 | OPCODE_INFO3 (0xf81009b0, | |
7916 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7917 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7918 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7919 | CSKY_ISA_VDSP), | |
7920 | OP32 ("vcmin.s32", | |
7921 | OPCODE_INFO3 (0xfa0009b0, | |
7922 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7923 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7924 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7925 | CSKY_ISA_VDSP), | |
7926 | OP32 ("vand.8", | |
7927 | OPCODE_INFO3 (0xf8000a00, | |
7928 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7929 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7930 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7931 | CSKY_ISA_VDSP), | |
7932 | OP32 ("vand.16", | |
7933 | OPCODE_INFO3 (0xf8100a00, | |
7934 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7935 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7936 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7937 | CSKY_ISA_VDSP), | |
7938 | OP32 ("vand.32", | |
7939 | OPCODE_INFO3 (0xfa000a00, | |
7940 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7941 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7942 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7943 | CSKY_ISA_VDSP), | |
7944 | OP32 ("vandn.8", | |
7945 | OPCODE_INFO3 (0xf8000a20, | |
7946 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7947 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7948 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7949 | CSKY_ISA_VDSP), | |
7950 | OP32 ("vandn.16", | |
7951 | OPCODE_INFO3 (0xf8100a20, | |
7952 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7953 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7954 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7955 | CSKY_ISA_VDSP), | |
7956 | OP32 ("vandn.32", | |
7957 | OPCODE_INFO3 (0xfa000a20, | |
7958 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7959 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7960 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7961 | CSKY_ISA_VDSP), | |
7962 | OP32 ("vor.8", | |
7963 | OPCODE_INFO3 (0xf8000a40, | |
7964 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7965 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7966 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7967 | CSKY_ISA_VDSP), | |
7968 | OP32 ("vor.16", | |
7969 | OPCODE_INFO3 (0xf8100a40, | |
7970 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7971 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7972 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7973 | CSKY_ISA_VDSP), | |
7974 | OP32 ("vor.32", | |
7975 | OPCODE_INFO3 (0xfa000a40, | |
7976 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7977 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7978 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7979 | CSKY_ISA_VDSP), | |
7980 | OP32 ("vnor.8", | |
7981 | OPCODE_INFO3 (0xf8000a60, | |
7982 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7983 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7984 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7985 | CSKY_ISA_VDSP), | |
7986 | OP32 ("vnor.16", | |
7987 | OPCODE_INFO3 (0xf8100a60, | |
7988 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7989 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7990 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7991 | CSKY_ISA_VDSP), | |
7992 | OP32 ("vnor.32", | |
7993 | OPCODE_INFO3 (0xfa000a60, | |
7994 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
7995 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
7996 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
7997 | CSKY_ISA_VDSP), | |
7998 | OP32 ("vxor.8", | |
7999 | OPCODE_INFO3 (0xf8000a80, | |
8000 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8001 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8002 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8003 | CSKY_ISA_VDSP), | |
8004 | OP32 ("vxor.16", | |
8005 | OPCODE_INFO3 (0xf8100a80, | |
8006 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8007 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8008 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8009 | CSKY_ISA_VDSP), | |
8010 | OP32 ("vxor.32", | |
8011 | OPCODE_INFO3 (0xfa000a80, | |
8012 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8013 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8014 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8015 | CSKY_ISA_VDSP), | |
8016 | OP32 ("vtst.8", | |
8017 | OPCODE_INFO3 (0xf8000b20, | |
8018 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8019 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8020 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8021 | CSKY_ISA_VDSP), | |
8022 | OP32 ("vtst.16", | |
8023 | OPCODE_INFO3 (0xf8100b20, | |
8024 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8025 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8026 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8027 | CSKY_ISA_VDSP), | |
8028 | OP32 ("vtst.32", | |
8029 | OPCODE_INFO3 (0xfa000b20, | |
8030 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8031 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8032 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8033 | CSKY_ISA_VDSP), | |
8034 | OP32 ("vbpermz.8", | |
8035 | OPCODE_INFO3 (0xf8000f00, | |
8036 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8037 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8038 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8039 | CSKY_ISA_VDSP), | |
8040 | OP32 ("vbpermz.16", | |
8041 | OPCODE_INFO3 (0xf8100f00, | |
8042 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8043 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8044 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8045 | CSKY_ISA_VDSP), | |
8046 | OP32 ("vbpermz.32", | |
8047 | OPCODE_INFO3 (0xfa000f00, | |
8048 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8049 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8050 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8051 | CSKY_ISA_VDSP), | |
8052 | OP32 ("vbperm.8", | |
8053 | OPCODE_INFO3 (0xf8000f20, | |
8054 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8055 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8056 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8057 | CSKY_ISA_VDSP), | |
8058 | OP32 ("vbperm.16", | |
8059 | OPCODE_INFO3 (0xf8100f20, | |
8060 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8061 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8062 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8063 | CSKY_ISA_VDSP), | |
8064 | OP32 ("vbperm.32", | |
8065 | OPCODE_INFO3 (0xfa000f20, | |
8066 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8067 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8068 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8069 | CSKY_ISA_VDSP), | |
8070 | OP32 ("vdch.8", | |
8071 | OPCODE_INFO3 (0xf8000fc0, | |
8072 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8073 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8074 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8075 | CSKY_ISA_VDSP), | |
8076 | OP32 ("vdch.16", | |
8077 | OPCODE_INFO3 (0xf8100fc0, | |
8078 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8079 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8080 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8081 | CSKY_ISA_VDSP), | |
8082 | OP32 ("vdch.32", | |
8083 | OPCODE_INFO3 (0xfa000fc0, | |
8084 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8085 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8086 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8087 | CSKY_ISA_VDSP), | |
8088 | OP32 ("vdcl.8", | |
8089 | OPCODE_INFO3 (0xf8000fe0, | |
8090 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8091 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8092 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8093 | CSKY_ISA_VDSP), | |
8094 | OP32 ("vdcl.16", | |
8095 | OPCODE_INFO3 (0xf8100fe0, | |
8096 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8097 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8098 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8099 | CSKY_ISA_VDSP), | |
8100 | OP32 ("vdcl.32", | |
8101 | OPCODE_INFO3 (0xfa000fe0, | |
8102 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8103 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8104 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8105 | CSKY_ISA_VDSP), | |
8106 | OP32 ("vich.8", | |
8107 | OPCODE_INFO3 (0xf8000f80, | |
8108 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8109 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8110 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8111 | CSKY_ISA_VDSP), | |
8112 | OP32 ("vich.16", | |
8113 | OPCODE_INFO3 (0xf8100f80, | |
8114 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8115 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8116 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8117 | CSKY_ISA_VDSP), | |
8118 | OP32 ("vich.32", | |
8119 | OPCODE_INFO3 (0xfa000f80, | |
8120 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8121 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8122 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8123 | CSKY_ISA_VDSP), | |
8124 | OP32 ("vicl.8", | |
8125 | OPCODE_INFO3 (0xf8000fa0, | |
8126 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8127 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8128 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8129 | CSKY_ISA_VDSP), | |
8130 | OP32 ("vicl.16", | |
8131 | OPCODE_INFO3 (0xf8100fa0, | |
8132 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8133 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8134 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8135 | CSKY_ISA_VDSP), | |
8136 | OP32 ("vicl.32", | |
8137 | OPCODE_INFO3 (0xfa000fa0, | |
8138 | (0_3, VREG, OPRND_SHIFT_0_BIT), | |
8139 | (16_19, VREG, OPRND_SHIFT_0_BIT), | |
8140 | (21_24, VREG, OPRND_SHIFT_0_BIT)), | |
8141 | CSKY_ISA_VDSP), | |
8142 | ||
1feede9b CQ |
8143 | #define OPRND_SHIFT0(mask, type) (mask, type, OPRND_SHIFT_0_BIT) |
8144 | #define OPRND_SHIFT1(mask, type) (mask, type, OPRND_SHIFT_1_BIT) | |
8145 | #define OPRND_SHIFT2(mask, type) (mask, type, OPRND_SHIFT_2_BIT) | |
8146 | #define OPRND_SHIFT3(mask, type) (mask, type, OPRND_SHIFT_3_BIT) | |
8147 | #define OPRND_SHIFT4(mask, type) (mask, type, OPRND_SHIFT_4_BIT) | |
8148 | ||
8149 | /* The followings are 860 floating instructions. */ | |
8150 | OP32 ("fadd.16", | |
8151 | OPCODE_INFO3 (0xf400c800, | |
8152 | OPRND_SHIFT0 (0_4, FREG), | |
8153 | OPRND_SHIFT0 (16_20, FREG), | |
8154 | OPRND_SHIFT0 (21_25, FREG)), | |
8155 | CSKY_ISA_FLOAT_7E60), | |
8156 | OP32 ("faddh", | |
8157 | OPCODE_INFO3 (0xf400c800, | |
8158 | OPRND_SHIFT0 (0_4, FREG), | |
8159 | OPRND_SHIFT0 (16_20, FREG), | |
8160 | OPRND_SHIFT0 (21_25, FREG)), | |
8161 | CSKY_ISA_FLOAT_7E60), | |
8162 | OP32 ("fsub.16", | |
8163 | OPCODE_INFO3 (0xf400c820, | |
8164 | OPRND_SHIFT0 (0_4, FREG), | |
8165 | OPRND_SHIFT0 (16_20, FREG), | |
8166 | OPRND_SHIFT0 (21_25, FREG)), | |
8167 | CSKY_ISA_FLOAT_7E60), | |
8168 | OP32 ("fsubh", | |
8169 | OPCODE_INFO3 (0xf400c820, | |
8170 | OPRND_SHIFT0 (0_4, FREG), | |
8171 | OPRND_SHIFT0 (16_20, FREG), | |
8172 | OPRND_SHIFT0 (21_25, FREG)), | |
8173 | CSKY_ISA_FLOAT_7E60), | |
8174 | OP32 ("fmov.16", | |
8175 | OPCODE_INFO2 (0xf400c880, | |
8176 | OPRND_SHIFT0 (0_4, FREG), | |
8177 | OPRND_SHIFT0 (16_20, FREG)), | |
8178 | CSKY_ISA_FLOAT_7E60), | |
8179 | OP32 ("fmovh", | |
8180 | OPCODE_INFO2 (0xf400c880, | |
8181 | OPRND_SHIFT0 (0_4, FREG), | |
8182 | OPRND_SHIFT0 (16_20, FREG)), | |
8183 | CSKY_ISA_FLOAT_7E60), | |
8184 | OP32 ("fabs.16", | |
8185 | OPCODE_INFO2 (0xf400c8c0, | |
8186 | OPRND_SHIFT0 (0_4, FREG), | |
8187 | OPRND_SHIFT0 (16_20, FREG)), | |
8188 | CSKY_ISA_FLOAT_7E60), | |
8189 | OP32 ("fabsh", | |
8190 | OPCODE_INFO2 (0xf400c8c0, | |
8191 | OPRND_SHIFT0 (0_4, FREG), | |
8192 | OPRND_SHIFT0 (16_20, FREG)), | |
8193 | CSKY_ISA_FLOAT_7E60), | |
8194 | OP32 ("fneg.16", | |
8195 | OPCODE_INFO2 (0xf400c8e0, | |
8196 | OPRND_SHIFT0 (0_4, FREG), | |
8197 | OPRND_SHIFT0 (16_20, FREG)), | |
8198 | CSKY_ISA_FLOAT_7E60), | |
8199 | OP32 ("fnegh", | |
8200 | OPCODE_INFO2 (0xf400c8e0, | |
8201 | OPRND_SHIFT0 (0_4, FREG), | |
8202 | OPRND_SHIFT0 (16_20, FREG)), | |
8203 | CSKY_ISA_FLOAT_7E60), | |
8204 | OP32 ("fcmphsz.16", | |
8205 | OPCODE_INFO1 (0xf400c900, | |
8206 | OPRND_SHIFT0 (16_20, FREG)), | |
8207 | CSKY_ISA_FLOAT_7E60), | |
8208 | OP32 ("fcmpzhsh", | |
8209 | OPCODE_INFO1 (0xf400c900, | |
8210 | OPRND_SHIFT0 (16_20, FREG)), | |
8211 | CSKY_ISA_FLOAT_7E60), | |
8212 | OP32 ("fcmpltz.16", | |
8213 | OPCODE_INFO1 (0xf400c920, | |
8214 | OPRND_SHIFT0 (16_20, FREG)), | |
8215 | CSKY_ISA_FLOAT_7E60), | |
8216 | OP32 ("fcmpzlth", | |
8217 | OPCODE_INFO1 (0xf400c920, | |
8218 | OPRND_SHIFT0 (16_20, FREG)), | |
8219 | CSKY_ISA_FLOAT_7E60), | |
8220 | OP32 ("fcmpnez.16", | |
8221 | OPCODE_INFO1 (0xf400c940, | |
8222 | OPRND_SHIFT0 (16_20, FREG)), | |
8223 | CSKY_ISA_FLOAT_7E60), | |
8224 | OP32 ("fcmpzneh", | |
8225 | OPCODE_INFO1 (0xf400c940, | |
8226 | OPRND_SHIFT0 (16_20, FREG)), | |
8227 | CSKY_ISA_FLOAT_7E60), | |
8228 | OP32 ("fcmpuoz.16", | |
8229 | OPCODE_INFO1 (0xf400c960, | |
8230 | OPRND_SHIFT0 (16_20, FREG)), | |
8231 | CSKY_ISA_FLOAT_7E60), | |
8232 | OP32 ("fcmpzuoh", | |
8233 | OPCODE_INFO1 (0xf400c960, | |
8234 | OPRND_SHIFT0 (16_20, FREG)), | |
8235 | CSKY_ISA_FLOAT_7E60), | |
8236 | OP32 ("fcmphs.16", | |
8237 | OPCODE_INFO2 (0xf400c980, | |
8238 | OPRND_SHIFT0 (16_20, FREG), | |
8239 | OPRND_SHIFT0 (21_25, FREG)), | |
8240 | CSKY_ISA_FLOAT_7E60), | |
8241 | OP32 ("fcmphsh", | |
8242 | OPCODE_INFO2 (0xf400c980, | |
8243 | OPRND_SHIFT0 (16_20, FREG), | |
8244 | OPRND_SHIFT0 (21_25, FREG)), | |
8245 | CSKY_ISA_FLOAT_7E60), | |
8246 | OP32 ("fcmplt.16", | |
8247 | OPCODE_INFO2 (0xf400c9a0, | |
8248 | OPRND_SHIFT0 (16_20, FREG), | |
8249 | OPRND_SHIFT0 (21_25, FREG)), | |
8250 | CSKY_ISA_FLOAT_7E60), | |
8251 | OP32 ("fcmpne.16", | |
8252 | OPCODE_INFO2 (0xf400c9c0, | |
8253 | OPRND_SHIFT0 (16_20, FREG), | |
8254 | OPRND_SHIFT0 (21_25, FREG)), | |
8255 | CSKY_ISA_FLOAT_7E60), | |
8256 | OP32 ("fcmpneh", | |
8257 | OPCODE_INFO2 (0xf400c9c0, | |
8258 | OPRND_SHIFT0 (16_20, FREG), | |
8259 | OPRND_SHIFT0 (21_25, FREG)), | |
8260 | CSKY_ISA_FLOAT_7E60), | |
8261 | OP32 ("fcmpuo.16", | |
8262 | OPCODE_INFO2 (0xf400c9e0, | |
8263 | OPRND_SHIFT0 (16_20, FREG), | |
8264 | OPRND_SHIFT0 (21_25, FREG)), | |
8265 | CSKY_ISA_FLOAT_7E60), | |
8266 | OP32 ("fcmpuoh", | |
8267 | OPCODE_INFO2 (0xf400c9e0, | |
8268 | OPRND_SHIFT0 (16_20, FREG), | |
8269 | OPRND_SHIFT0 (21_25, FREG)), | |
8270 | CSKY_ISA_FLOAT_7E60), | |
8271 | OP32 ("fmaxnm.16", | |
8272 | OPCODE_INFO3 (0xf400cd00, | |
8273 | OPRND_SHIFT0 (0_4, FREG), | |
8274 | OPRND_SHIFT0 (16_20, FREG), | |
8275 | OPRND_SHIFT0 (21_25, FREG)), | |
8276 | CSKY_ISA_FLOAT_7E60), | |
8277 | OP32 ("fminnm.16", | |
8278 | OPCODE_INFO3 (0xf400cd20, | |
8279 | OPRND_SHIFT0 (0_4, FREG), | |
8280 | OPRND_SHIFT0 (16_20, FREG), | |
8281 | OPRND_SHIFT0 (21_25, FREG)), | |
8282 | CSKY_ISA_FLOAT_7E60), | |
8283 | OP32 ("fcmphz.16", | |
8284 | OPCODE_INFO1 (0xf400cd40, | |
8285 | OPRND_SHIFT0 (16_20, FREG)), | |
8286 | CSKY_ISA_FLOAT_7E60), | |
8287 | OP32 ("fcmplsz.16", | |
8288 | OPCODE_INFO1 (0xf400cd60, | |
8289 | OPRND_SHIFT0 (16_20, FREG)), | |
8290 | CSKY_ISA_FLOAT_7E60), | |
8291 | OP32 ("fmul.16", | |
8292 | OPCODE_INFO3 (0xf400ca00, | |
8293 | OPRND_SHIFT0 (0_4, FREG), | |
8294 | OPRND_SHIFT0 (16_20, FREG), | |
8295 | OPRND_SHIFT0 (21_25, FREG)), | |
8296 | CSKY_ISA_FLOAT_7E60), | |
8297 | OP32 ("fmulh", | |
8298 | OPCODE_INFO3 (0xf400ca00, | |
8299 | OPRND_SHIFT0 (0_4, FREG), | |
8300 | OPRND_SHIFT0 (16_20, FREG), | |
8301 | OPRND_SHIFT0 (21_25, FREG)), | |
8302 | CSKY_ISA_FLOAT_7E60), | |
8303 | OP32 ("fnmul.16", | |
8304 | OPCODE_INFO3 (0xf400ca20, | |
8305 | OPRND_SHIFT0 (0_4, FREG), | |
8306 | OPRND_SHIFT0 (16_20, FREG), | |
8307 | OPRND_SHIFT0 (21_25, FREG)), | |
8308 | CSKY_ISA_FLOAT_7E60), | |
8309 | OP32 ("fnmulh", | |
8310 | OPCODE_INFO3 (0xf400ca20, | |
8311 | OPRND_SHIFT0 (0_4, FREG), | |
8312 | OPRND_SHIFT0 (16_20, FREG), | |
8313 | OPRND_SHIFT0 (21_25, FREG)), | |
8314 | CSKY_ISA_FLOAT_7E60), | |
8315 | OP32 ("fmula.16", | |
8316 | OPCODE_INFO3 (0xf400ca80, | |
8317 | OPRND_SHIFT0 (0_4, FREG), | |
8318 | OPRND_SHIFT0 (16_20, FREG), | |
8319 | OPRND_SHIFT0 (21_25, FREG)), | |
8320 | CSKY_ISA_FLOAT_7E60), | |
8321 | OP32 ("fmach", | |
8322 | OPCODE_INFO3 (0xf400ca80, | |
8323 | OPRND_SHIFT0 (0_4, FREG), | |
8324 | OPRND_SHIFT0 (16_20, FREG), | |
8325 | OPRND_SHIFT0 (21_25, FREG)), | |
8326 | CSKY_ISA_FLOAT_7E60), | |
8327 | OP32 ("fnmuls.16", | |
8328 | OPCODE_INFO3 (0xf400caa0, | |
8329 | OPRND_SHIFT0 (0_4, FREG), | |
8330 | OPRND_SHIFT0 (16_20, FREG), | |
8331 | OPRND_SHIFT0 (21_25, FREG)), | |
8332 | CSKY_ISA_FLOAT_7E60), | |
8333 | OP32 ("fmsch", | |
8334 | OPCODE_INFO3 (0xf400caa0, | |
8335 | OPRND_SHIFT0 (0_4, FREG), | |
8336 | OPRND_SHIFT0 (16_20, FREG), | |
8337 | OPRND_SHIFT0 (21_25, FREG)), | |
8338 | CSKY_ISA_FLOAT_7E60), | |
8339 | OP32 ("fmuls.16", | |
8340 | OPCODE_INFO3 (0xf400cac0, | |
8341 | OPRND_SHIFT0 (0_4, FREG), | |
8342 | OPRND_SHIFT0 (16_20, FREG), | |
8343 | OPRND_SHIFT0 (21_25, FREG)), | |
8344 | CSKY_ISA_FLOAT_7E60), | |
8345 | OP32 ("fnmach", | |
8346 | OPCODE_INFO3 (0xf400cac0, | |
8347 | OPRND_SHIFT0 (0_4, FREG), | |
8348 | OPRND_SHIFT0 (16_20, FREG), | |
8349 | OPRND_SHIFT0 (21_25, FREG)), | |
8350 | CSKY_ISA_FLOAT_7E60), | |
8351 | OP32 ("fnmula.16", | |
8352 | OPCODE_INFO3 (0xf400cae0, | |
8353 | OPRND_SHIFT0 (0_4, FREG), | |
8354 | OPRND_SHIFT0 (16_20, FREG), | |
8355 | OPRND_SHIFT0 (21_25, FREG)), | |
8356 | CSKY_ISA_FLOAT_7E60), | |
8357 | OP32 ("fnmsch", | |
8358 | OPCODE_INFO3 (0xf400cae0, | |
8359 | OPRND_SHIFT0 (0_4, FREG), | |
8360 | OPRND_SHIFT0 (16_20, FREG), | |
8361 | OPRND_SHIFT0 (21_25, FREG)), | |
8362 | CSKY_ISA_FLOAT_7E60), | |
8363 | OP32 ("ffmula.16", | |
8364 | OPCODE_INFO3 (0xf400ce00, | |
8365 | OPRND_SHIFT0 (0_4, FREG), | |
8366 | OPRND_SHIFT0 (16_20, FREG), | |
8367 | OPRND_SHIFT0 (21_25, FREG)), | |
8368 | CSKY_ISA_FLOAT_7E60), | |
8369 | OP32 ("ffmuls.16", | |
8370 | OPCODE_INFO3 (0xf400ce20, | |
8371 | OPRND_SHIFT0 (0_4, FREG), | |
8372 | OPRND_SHIFT0 (16_20, FREG), | |
8373 | OPRND_SHIFT0 (21_25, FREG)), | |
8374 | CSKY_ISA_FLOAT_7E60), | |
8375 | OP32 ("ffnmula.16", | |
8376 | OPCODE_INFO3 (0xf400ce40, | |
8377 | OPRND_SHIFT0 (0_4, FREG), | |
8378 | OPRND_SHIFT0 (16_20, FREG), | |
8379 | OPRND_SHIFT0 (21_25, FREG)), | |
8380 | CSKY_ISA_FLOAT_7E60), | |
8381 | OP32 ("ffnmuls.16", | |
8382 | OPCODE_INFO3 (0xf400ce60, | |
8383 | OPRND_SHIFT0 (0_4, FREG), | |
8384 | OPRND_SHIFT0 (16_20, FREG), | |
8385 | OPRND_SHIFT0 (21_25, FREG)), | |
8386 | CSKY_ISA_FLOAT_7E60), | |
8387 | OP32 ("fdivh", | |
8388 | OPCODE_INFO3 (0xf400cb00, | |
8389 | OPRND_SHIFT0 (0_4, FREG), | |
8390 | OPRND_SHIFT0 (16_20, FREG), | |
8391 | OPRND_SHIFT0 (21_25, FREG)), | |
8392 | CSKY_ISA_FLOAT_7E60), | |
8393 | OP32 ("fdiv.16", | |
8394 | OPCODE_INFO3 (0xf400cb00, | |
8395 | OPRND_SHIFT0 (0_4, FREG), | |
8396 | OPRND_SHIFT0 (16_20, FREG), | |
8397 | OPRND_SHIFT0 (21_25, FREG)), | |
8398 | CSKY_ISA_FLOAT_7E60), | |
8399 | OP32 ("freciph", | |
8400 | OPCODE_INFO2 (0xf400cb20, | |
8401 | OPRND_SHIFT0 (0_4, FREG), | |
8402 | OPRND_SHIFT0 (16_20, FREG)), | |
8403 | CSKY_ISA_FLOAT_7E60), | |
8404 | OP32 ("frecip.16", | |
8405 | OPCODE_INFO2 (0xf400cb20, | |
8406 | OPRND_SHIFT0 (0_4, FREG), | |
8407 | OPRND_SHIFT0 (16_20, FREG)), | |
8408 | CSKY_ISA_FLOAT_7E60), | |
8409 | OP32 ("fsqrt.16", | |
8410 | OPCODE_INFO2 (0xf400cb40, | |
8411 | OPRND_SHIFT0 (0_4, FREG), | |
8412 | OPRND_SHIFT0 (16_20, FREG)), | |
8413 | CSKY_ISA_FLOAT_7E60), | |
8414 | OP32 ("fsqrth", | |
8415 | OPCODE_INFO2 (0xf400cb40, | |
8416 | OPRND_SHIFT0 (0_4, FREG), | |
8417 | OPRND_SHIFT0 (16_20, FREG)), | |
8418 | CSKY_ISA_FLOAT_7E60), | |
8419 | OP32 ("fsel.16", | |
8420 | OPCODE_INFO3 (0xf400cf20, | |
8421 | OPRND_SHIFT0 (0_4, FREG), | |
8422 | OPRND_SHIFT0 (16_20, FREG), | |
8423 | OPRND_SHIFT0 (21_25, FREG)), | |
8424 | CSKY_ISA_FLOAT_7E60), | |
8425 | /* Single floating. */ | |
8426 | OP32 ("fadd.32", | |
8427 | OPCODE_INFO3 (0xf4000000, | |
8428 | OPRND_SHIFT0 (0_4, FREG), | |
8429 | OPRND_SHIFT0 (16_20, FREG), | |
8430 | OPRND_SHIFT0 (21_25, FREG)), | |
8431 | CSKY_ISA_FLOAT_7E60), | |
8432 | OP32 ("fadds", | |
8433 | OPCODE_INFO3 (0xf4000000, | |
8434 | OPRND_SHIFT0 (0_4, FREG), | |
8435 | OPRND_SHIFT0 (16_20, FREG), | |
8436 | OPRND_SHIFT0 (21_25, FREG)), | |
8437 | CSKY_ISA_FLOAT_7E60), | |
8438 | OP32 ("fsub.32", | |
8439 | OPCODE_INFO3 (0xf4000020, | |
8440 | OPRND_SHIFT0 (0_4, FREG), | |
8441 | OPRND_SHIFT0 (16_20, FREG), | |
8442 | OPRND_SHIFT0 (21_25, FREG)), | |
8443 | CSKY_ISA_FLOAT_7E60), | |
8444 | OP32 ("fsubs", | |
8445 | OPCODE_INFO3 (0xf4000020, | |
8446 | OPRND_SHIFT0 (0_4, FREG), | |
8447 | OPRND_SHIFT0 (16_20, FREG), | |
8448 | OPRND_SHIFT0 (21_25, FREG)), | |
8449 | CSKY_ISA_FLOAT_7E60), | |
8450 | OP32 ("fmov.32", | |
8451 | OPCODE_INFO2 (0xf4000080, | |
8452 | OPRND_SHIFT0 (0_4, FREG), | |
8453 | OPRND_SHIFT0 (16_20, FREG)), | |
8454 | CSKY_ISA_FLOAT_7E60), | |
8455 | OP32 ("fmovs", | |
8456 | OPCODE_INFO2 (0xf4000080, | |
8457 | OPRND_SHIFT0 (0_4, FREG), | |
8458 | OPRND_SHIFT0 (16_20, FREG)), | |
8459 | CSKY_ISA_FLOAT_7E60), | |
8460 | OP32 ("fabs.32", | |
8461 | OPCODE_INFO2 (0xf40000c0, | |
8462 | OPRND_SHIFT0 (0_4, FREG), | |
8463 | OPRND_SHIFT0 (16_20, FREG)), | |
8464 | CSKY_ISA_FLOAT_7E60), | |
8465 | OP32 ("fabss", | |
8466 | OPCODE_INFO2 (0xf40000c0, | |
8467 | OPRND_SHIFT0 (0_4, FREG), | |
8468 | OPRND_SHIFT0 (16_20, FREG)), | |
8469 | CSKY_ISA_FLOAT_7E60), | |
8470 | OP32 ("fneg.32", | |
8471 | OPCODE_INFO2 (0xf40000e0, | |
8472 | OPRND_SHIFT0 (0_4, FREG), | |
8473 | OPRND_SHIFT0 (16_20, FREG)), | |
8474 | CSKY_ISA_FLOAT_7E60), | |
8475 | OP32 ("fnegs", | |
8476 | OPCODE_INFO2 (0xf40000e0, | |
8477 | OPRND_SHIFT0 (0_4, FREG), | |
8478 | OPRND_SHIFT0 (16_20, FREG)), | |
8479 | CSKY_ISA_FLOAT_7E60), | |
8480 | OP32 ("fcmphsz.32", | |
8481 | OPCODE_INFO1 (0xf4000100, | |
8482 | OPRND_SHIFT0 (16_20, FREG)), | |
8483 | CSKY_ISA_FLOAT_7E60), | |
8484 | OP32 ("fcmpzhss", | |
8485 | OPCODE_INFO1 (0xf4000100, | |
8486 | OPRND_SHIFT0 (16_20, FREG)), | |
8487 | CSKY_ISA_FLOAT_7E60), | |
8488 | OP32 ("fcmpltz.32", | |
8489 | OPCODE_INFO1 (0xf4000120, | |
8490 | OPRND_SHIFT0 (16_20, FREG)), | |
8491 | CSKY_ISA_FLOAT_7E60), | |
8492 | OP32 ("fcmpzlts", | |
8493 | OPCODE_INFO1 (0xf4000120, | |
8494 | OPRND_SHIFT0 (16_20, FREG)), | |
8495 | CSKY_ISA_FLOAT_7E60), | |
8496 | OP32 ("fcmpnez.32", | |
8497 | OPCODE_INFO1 (0xf4000140, | |
8498 | OPRND_SHIFT0 (16_20, FREG)), | |
8499 | CSKY_ISA_FLOAT_7E60), | |
8500 | OP32 ("fcmpznes", | |
8501 | OPCODE_INFO1 (0xf4000140, | |
8502 | OPRND_SHIFT0 (16_20, FREG)), | |
8503 | CSKY_ISA_FLOAT_7E60), | |
8504 | OP32 ("fcmpuoz.32", | |
8505 | OPCODE_INFO1 (0xf4000160, | |
8506 | OPRND_SHIFT0 (16_20, FREG)), | |
8507 | CSKY_ISA_FLOAT_7E60), | |
8508 | OP32 ("fcmpzuos", | |
8509 | OPCODE_INFO1 (0xf4000160, | |
8510 | OPRND_SHIFT0 (16_20, FREG)), | |
8511 | CSKY_ISA_FLOAT_7E60), | |
8512 | OP32 ("fcmphs.32", | |
8513 | OPCODE_INFO2 (0xf4000180, | |
8514 | OPRND_SHIFT0 (16_20, FREG), | |
8515 | OPRND_SHIFT0 (21_25, FREG)), | |
8516 | CSKY_ISA_FLOAT_7E60), | |
8517 | OP32 ("fcmphss", | |
8518 | OPCODE_INFO2 (0xf4000180, | |
8519 | OPRND_SHIFT0 (16_20, FREG), | |
8520 | OPRND_SHIFT0 (21_25, FREG)), | |
8521 | CSKY_ISA_FLOAT_7E60), | |
8522 | OP32 ("fcmplt.32", | |
8523 | OPCODE_INFO2 (0xf40001a0, | |
8524 | OPRND_SHIFT0 (16_20, FREG), | |
8525 | OPRND_SHIFT0 (21_25, FREG)), | |
8526 | CSKY_ISA_FLOAT_7E60), | |
8527 | OP32 ("fcmplts", | |
8528 | OPCODE_INFO2 (0xf40001a0, | |
8529 | OPRND_SHIFT0 (16_20, FREG), | |
8530 | OPRND_SHIFT0 (21_25, FREG)), | |
8531 | CSKY_ISA_FLOAT_7E60), | |
8532 | OP32 ("fcmpne.32", | |
8533 | OPCODE_INFO2 (0xf40001c0, | |
8534 | OPRND_SHIFT0 (16_20, FREG), | |
8535 | OPRND_SHIFT0 (21_25, FREG)), | |
8536 | CSKY_ISA_FLOAT_7E60), | |
8537 | OP32 ("fcmpnes", | |
8538 | OPCODE_INFO2 (0xf40001c0, | |
8539 | OPRND_SHIFT0 (16_20, FREG), | |
8540 | OPRND_SHIFT0 (21_25, FREG)), | |
8541 | CSKY_ISA_FLOAT_7E60), | |
8542 | OP32 ("fcmpuo.32", | |
8543 | OPCODE_INFO2 (0xf40001e0, | |
8544 | OPRND_SHIFT0 (16_20, FREG), | |
8545 | OPRND_SHIFT0 (21_25, FREG)), | |
8546 | CSKY_ISA_FLOAT_7E60), | |
8547 | OP32 ("fcmpuos", | |
8548 | OPCODE_INFO2 (0xf40001e0, | |
8549 | OPRND_SHIFT0 (16_20, FREG), | |
8550 | OPRND_SHIFT0 (21_25, FREG)), | |
8551 | CSKY_ISA_FLOAT_7E60), | |
8552 | OP32 ("fmaxnm.32", | |
8553 | OPCODE_INFO3 (0xf4000500, | |
8554 | OPRND_SHIFT0 (0_4, FREG), | |
8555 | OPRND_SHIFT0 (16_20, FREG), | |
8556 | OPRND_SHIFT0 (21_25, FREG)), | |
8557 | CSKY_ISA_FLOAT_7E60), | |
8558 | OP32 ("fminnm.32", | |
8559 | OPCODE_INFO3 (0xf4000520, | |
8560 | OPRND_SHIFT0 (0_4, FREG), | |
8561 | OPRND_SHIFT0 (16_20, FREG), | |
8562 | OPRND_SHIFT0 (21_25, FREG)), | |
8563 | CSKY_ISA_FLOAT_7E60), | |
8564 | OP32 ("fcmphz.32", | |
8565 | OPCODE_INFO1 (0xf4000540, | |
8566 | OPRND_SHIFT0 (16_20, FREG)), | |
8567 | CSKY_ISA_FLOAT_7E60), | |
8568 | OP32 ("fcmplsz.32", | |
8569 | OPCODE_INFO1 (0xf4000560, | |
8570 | OPRND_SHIFT0 (16_20, FREG)), | |
8571 | CSKY_ISA_FLOAT_7E60), | |
8572 | OP32 ("fmul.32", | |
8573 | OPCODE_INFO3 (0xf4000200, | |
8574 | OPRND_SHIFT0 (0_4, FREG), | |
8575 | OPRND_SHIFT0 (16_20, FREG), | |
8576 | OPRND_SHIFT0 (21_25, FREG)), | |
8577 | CSKY_ISA_FLOAT_7E60), | |
8578 | OP32 ("fmuls", | |
8579 | OPCODE_INFO3 (0xf4000200, | |
8580 | OPRND_SHIFT0 (0_4, FREG), | |
8581 | OPRND_SHIFT0 (16_20, FREG), | |
8582 | OPRND_SHIFT0 (21_25, FREG)), | |
8583 | CSKY_ISA_FLOAT_7E60), | |
8584 | OP32 ("fnmul.32", | |
8585 | OPCODE_INFO3 (0xf4000220, | |
8586 | OPRND_SHIFT0 (0_4, FREG), | |
8587 | OPRND_SHIFT0 (16_20, FREG), | |
8588 | OPRND_SHIFT0 (21_25, FREG)), | |
8589 | CSKY_ISA_FLOAT_7E60), | |
8590 | OP32 ("fnmuls", | |
8591 | OPCODE_INFO3 (0xf4000220, | |
8592 | OPRND_SHIFT0 (0_4, FREG), | |
8593 | OPRND_SHIFT0 (16_20, FREG), | |
8594 | OPRND_SHIFT0 (21_25, FREG)), | |
8595 | CSKY_ISA_FLOAT_7E60), | |
8596 | OP32 ("fmula.32", | |
8597 | OPCODE_INFO3 (0xf4000280, | |
8598 | OPRND_SHIFT0 (0_4, FREG), | |
8599 | OPRND_SHIFT0 (16_20, FREG), | |
8600 | OPRND_SHIFT0 (21_25, FREG)), | |
8601 | CSKY_ISA_FLOAT_7E60), | |
8602 | OP32 ("fmacs", | |
8603 | OPCODE_INFO3 (0xf4000280, | |
8604 | OPRND_SHIFT0 (0_4, FREG), | |
8605 | OPRND_SHIFT0 (16_20, FREG), | |
8606 | OPRND_SHIFT0 (21_25, FREG)), | |
8607 | CSKY_ISA_FLOAT_7E60), | |
8608 | OP32 ("fnmuls.32", | |
8609 | OPCODE_INFO3 (0xf40002a0, | |
8610 | OPRND_SHIFT0 (0_4, FREG), | |
8611 | OPRND_SHIFT0 (16_20, FREG), | |
8612 | OPRND_SHIFT0 (21_25, FREG)), | |
8613 | CSKY_ISA_FLOAT_7E60), | |
8614 | OP32 ("fmscs", | |
8615 | OPCODE_INFO3 (0xf40002a0, | |
8616 | OPRND_SHIFT0 (0_4, FREG), | |
8617 | OPRND_SHIFT0 (16_20, FREG), | |
8618 | OPRND_SHIFT0 (21_25, FREG)), | |
8619 | CSKY_ISA_FLOAT_7E60), | |
8620 | OP32 ("fmuls.32", | |
8621 | OPCODE_INFO3 (0xf40002c0, | |
8622 | OPRND_SHIFT0 (0_4, FREG), | |
8623 | OPRND_SHIFT0 (16_20, FREG), | |
8624 | OPRND_SHIFT0 (21_25, FREG)), | |
8625 | CSKY_ISA_FLOAT_7E60), | |
8626 | OP32 ("fnmacs", | |
8627 | OPCODE_INFO3 (0xf40002c0, | |
8628 | OPRND_SHIFT0 (0_4, FREG), | |
8629 | OPRND_SHIFT0 (16_20, FREG), | |
8630 | OPRND_SHIFT0 (21_25, FREG)), | |
8631 | CSKY_ISA_FLOAT_7E60), | |
8632 | OP32 ("fnmula.32", | |
8633 | OPCODE_INFO3 (0xf40002e0, | |
8634 | OPRND_SHIFT0 (0_4, FREG), | |
8635 | OPRND_SHIFT0 (16_20, FREG), | |
8636 | OPRND_SHIFT0 (21_25, FREG)), | |
8637 | CSKY_ISA_FLOAT_7E60), | |
8638 | OP32 ("fnmscs", | |
8639 | OPCODE_INFO3 (0xf40002e0, | |
8640 | OPRND_SHIFT0 (0_4, FREG), | |
8641 | OPRND_SHIFT0 (16_20, FREG), | |
8642 | OPRND_SHIFT0 (21_25, FREG)), | |
8643 | CSKY_ISA_FLOAT_7E60), | |
8644 | OP32 ("ffmula.32", | |
8645 | OPCODE_INFO3 (0xf4000600, | |
8646 | OPRND_SHIFT0 (0_4, FREG), | |
8647 | OPRND_SHIFT0 (16_20, FREG), | |
8648 | OPRND_SHIFT0 (21_25, FREG)), | |
8649 | CSKY_ISA_FLOAT_7E60), | |
8650 | OP32 ("ffmuls.32", | |
8651 | OPCODE_INFO3 (0xf4000620, | |
8652 | OPRND_SHIFT0 (0_4, FREG), | |
8653 | OPRND_SHIFT0 (16_20, FREG), | |
8654 | OPRND_SHIFT0 (21_25, FREG)), | |
8655 | CSKY_ISA_FLOAT_7E60), | |
8656 | OP32 ("ffnmula.32", | |
8657 | OPCODE_INFO3 (0xf4000640, | |
8658 | OPRND_SHIFT0 (0_4, FREG), | |
8659 | OPRND_SHIFT0 (16_20, FREG), | |
8660 | OPRND_SHIFT0 (21_25, FREG)), | |
8661 | CSKY_ISA_FLOAT_7E60), | |
8662 | OP32 ("ffnmuls.32", | |
8663 | OPCODE_INFO3 (0xf4000660, | |
8664 | OPRND_SHIFT0 (0_4, FREG), | |
8665 | OPRND_SHIFT0 (16_20, FREG), | |
8666 | OPRND_SHIFT0 (21_25, FREG)), | |
8667 | CSKY_ISA_FLOAT_7E60), | |
8668 | OP32 ("fdiv.32", | |
8669 | OPCODE_INFO3 (0xf4000300, | |
8670 | OPRND_SHIFT0 (0_4, FREG), | |
8671 | OPRND_SHIFT0 (16_20, FREG), | |
8672 | OPRND_SHIFT0 (21_25, FREG)), | |
8673 | CSKY_ISA_FLOAT_7E60), | |
8674 | OP32 ("fdivs", | |
8675 | OPCODE_INFO3 (0xf4000300, | |
8676 | OPRND_SHIFT0 (0_4, FREG), | |
8677 | OPRND_SHIFT0 (16_20, FREG), | |
8678 | OPRND_SHIFT0 (21_25, FREG)), | |
8679 | CSKY_ISA_FLOAT_7E60), | |
8680 | OP32 ("frecip.32", | |
8681 | OPCODE_INFO2 (0xf4000320, | |
8682 | OPRND_SHIFT0 (0_4, FREG), | |
8683 | OPRND_SHIFT0 (16_20, FREG)), | |
8684 | CSKY_ISA_FLOAT_7E60), | |
8685 | OP32 ("frecips", | |
8686 | OPCODE_INFO2 (0xf4000320, | |
8687 | OPRND_SHIFT0 (0_4, FREG), | |
8688 | OPRND_SHIFT0 (16_20, FREG)), | |
8689 | CSKY_ISA_FLOAT_7E60), | |
8690 | OP32 ("fsqrt.32", | |
8691 | OPCODE_INFO2 (0xf4000340, | |
8692 | OPRND_SHIFT0 (0_4, FREG), | |
8693 | OPRND_SHIFT0 (16_20, FREG)), | |
8694 | CSKY_ISA_FLOAT_7E60), | |
8695 | OP32 ("fsqrts", | |
8696 | OPCODE_INFO2 (0xf4000340, | |
8697 | OPRND_SHIFT0 (0_4, FREG), | |
8698 | OPRND_SHIFT0 (16_20, FREG)), | |
8699 | CSKY_ISA_FLOAT_7E60), | |
8700 | OP32 ("fsel.32", | |
8701 | OPCODE_INFO3 (0xf4000720, | |
8702 | OPRND_SHIFT0 (0_4, FREG), | |
8703 | OPRND_SHIFT0 (16_20, FREG), | |
8704 | OPRND_SHIFT0 (21_25, FREG)), | |
8705 | CSKY_ISA_FLOAT_7E60), | |
8706 | /* Double floating. */ | |
8707 | OP32 ("fadd.64", | |
8708 | OPCODE_INFO3 (0xf4000800, | |
8709 | OPRND_SHIFT0 (0_4, FREG), | |
8710 | OPRND_SHIFT0 (16_20, FREG), | |
8711 | OPRND_SHIFT0 (21_25, FREG)), | |
8712 | CSKY_ISA_FLOAT_7E60), | |
8713 | OP32 ("faddd", | |
8714 | OPCODE_INFO3 (0xf4000800, | |
8715 | OPRND_SHIFT0 (0_4, FREG), | |
8716 | OPRND_SHIFT0 (16_20, FREG), | |
8717 | OPRND_SHIFT0 (21_25, FREG)), | |
8718 | CSKY_ISA_FLOAT_7E60), | |
8719 | OP32 ("fsub.64", | |
8720 | OPCODE_INFO3 (0xf4000820, | |
8721 | OPRND_SHIFT0 (0_4, FREG), | |
8722 | OPRND_SHIFT0 (16_20, FREG), | |
8723 | OPRND_SHIFT0 (21_25, FREG)), | |
8724 | CSKY_ISA_FLOAT_7E60), | |
8725 | OP32 ("fsubd", | |
8726 | OPCODE_INFO3 (0xf4000820, | |
8727 | OPRND_SHIFT0 (0_4, FREG), | |
8728 | OPRND_SHIFT0 (16_20, FREG), | |
8729 | OPRND_SHIFT0 (21_25, FREG)), | |
8730 | CSKY_ISA_FLOAT_7E60), | |
8731 | OP32 ("fmov.64", | |
8732 | OPCODE_INFO2 (0xf4000880, | |
8733 | OPRND_SHIFT0 (0_4, FREG), | |
8734 | OPRND_SHIFT0 (16_20, FREG)), | |
8735 | CSKY_ISA_FLOAT_7E60), | |
8736 | OP32 ("fmovd", | |
8737 | OPCODE_INFO2 (0xf4000880, | |
8738 | OPRND_SHIFT0 (0_4, FREG), | |
8739 | OPRND_SHIFT0 (16_20, FREG)), | |
8740 | CSKY_ISA_FLOAT_7E60), | |
8741 | OP32 ("fmovx.32", | |
8742 | OPCODE_INFO2 (0xf40008a0, | |
8743 | OPRND_SHIFT0 (0_4, FREG), | |
8744 | OPRND_SHIFT0 (16_20, FREG)), | |
8745 | CSKY_ISA_FLOAT_7E60), | |
8746 | OP32 ("fabs.64", | |
8747 | OPCODE_INFO2 (0xf40008c0, | |
8748 | OPRND_SHIFT0 (0_4, FREG), | |
8749 | OPRND_SHIFT0 (16_20, FREG)), | |
8750 | CSKY_ISA_FLOAT_7E60), | |
8751 | OP32 ("fabsd", | |
8752 | OPCODE_INFO2 (0xf40008c0, | |
8753 | OPRND_SHIFT0 (0_4, FREG), | |
8754 | OPRND_SHIFT0 (16_20, FREG)), | |
8755 | CSKY_ISA_FLOAT_7E60), | |
8756 | OP32 ("fneg.64", | |
8757 | OPCODE_INFO2 (0xf40008e0, | |
8758 | OPRND_SHIFT0 (0_4, FREG), | |
8759 | OPRND_SHIFT0 (16_20, FREG)), | |
8760 | CSKY_ISA_FLOAT_7E60), | |
8761 | OP32 ("fnegd", | |
8762 | OPCODE_INFO2 (0xf40008e0, | |
8763 | OPRND_SHIFT0 (0_4, FREG), | |
8764 | OPRND_SHIFT0 (16_20, FREG)), | |
8765 | CSKY_ISA_FLOAT_7E60), | |
8766 | OP32 ("fcmphsz.64", | |
8767 | OPCODE_INFO1 (0xf4000900, | |
8768 | OPRND_SHIFT0 (16_20, FREG)), | |
8769 | CSKY_ISA_FLOAT_7E60), | |
8770 | OP32 ("fcmpzhsd", | |
8771 | OPCODE_INFO1 (0xf4000900, | |
8772 | OPRND_SHIFT0 (16_20, FREG)), | |
8773 | CSKY_ISA_FLOAT_7E60), | |
8774 | OP32 ("fcmpltz.64", | |
8775 | OPCODE_INFO1 (0xf4000920, | |
8776 | OPRND_SHIFT0 (16_20, FREG)), | |
8777 | CSKY_ISA_FLOAT_7E60), | |
8778 | OP32 ("fcmpzltd", | |
8779 | OPCODE_INFO1 (0xf4000920, | |
8780 | OPRND_SHIFT0 (16_20, FREG)), | |
8781 | CSKY_ISA_FLOAT_7E60), | |
8782 | OP32 ("fcmpnez.64", | |
8783 | OPCODE_INFO1 (0xf4000940, | |
8784 | OPRND_SHIFT0 (16_20, FREG)), | |
8785 | CSKY_ISA_FLOAT_7E60), | |
8786 | OP32 ("fcmpzned", | |
8787 | OPCODE_INFO1 (0xf4000940, | |
8788 | OPRND_SHIFT0 (16_20, FREG)), | |
8789 | CSKY_ISA_FLOAT_7E60), | |
8790 | OP32 ("fcmpuoz.64", | |
8791 | OPCODE_INFO1 (0xf4000960, | |
8792 | OPRND_SHIFT0 (16_20, FREG)), | |
8793 | CSKY_ISA_FLOAT_7E60), | |
8794 | OP32 ("fcmpzuod", | |
8795 | OPCODE_INFO1 (0xf4000960, | |
8796 | OPRND_SHIFT0 (16_20, FREG)), | |
8797 | CSKY_ISA_FLOAT_7E60), | |
8798 | OP32 ("fcmphs.64", | |
8799 | OPCODE_INFO2 (0xf4000980, | |
8800 | OPRND_SHIFT0 (16_20, FREG), | |
8801 | OPRND_SHIFT0 (21_25, FREG)), | |
8802 | CSKY_ISA_FLOAT_7E60), | |
8803 | OP32 ("fcmphsd", | |
8804 | OPCODE_INFO2 (0xf4000980, | |
8805 | OPRND_SHIFT0 (16_20, FREG), | |
8806 | OPRND_SHIFT0 (21_25, FREG)), | |
8807 | CSKY_ISA_FLOAT_7E60), | |
8808 | OP32 ("fcmplt.64", | |
8809 | OPCODE_INFO2 (0xf40009a0, | |
8810 | OPRND_SHIFT0 (16_20, FREG), | |
8811 | OPRND_SHIFT0 (21_25, FREG)), | |
8812 | CSKY_ISA_FLOAT_7E60), | |
8813 | OP32 ("fcmpltd", | |
8814 | OPCODE_INFO2 (0xf40009a0, | |
8815 | OPRND_SHIFT0 (16_20, FREG), | |
8816 | OPRND_SHIFT0 (21_25, FREG)), | |
8817 | CSKY_ISA_FLOAT_7E60), | |
8818 | OP32 ("fcmpne.64", | |
8819 | OPCODE_INFO2 (0xf40009c0, | |
8820 | OPRND_SHIFT0 (16_20, FREG), | |
8821 | OPRND_SHIFT0 (21_25, FREG)), | |
8822 | CSKY_ISA_FLOAT_7E60), | |
8823 | OP32 ("fcmpned", | |
8824 | OPCODE_INFO2 (0xf40009c0, | |
8825 | OPRND_SHIFT0 (16_20, FREG), | |
8826 | OPRND_SHIFT0 (21_25, FREG)), | |
8827 | CSKY_ISA_FLOAT_7E60), | |
8828 | OP32 ("fcmpuo.64", | |
8829 | OPCODE_INFO2 (0xf40009e0, | |
8830 | OPRND_SHIFT0 (16_20, FREG), | |
8831 | OPRND_SHIFT0 (21_25, FREG)), | |
8832 | CSKY_ISA_FLOAT_7E60), | |
8833 | OP32 ("fcmpuod", | |
8834 | OPCODE_INFO2 (0xf40009e0, | |
8835 | OPRND_SHIFT0 (16_20, FREG), | |
8836 | OPRND_SHIFT0 (21_25, FREG)), | |
8837 | CSKY_ISA_FLOAT_7E60), | |
8838 | OP32 ("fmaxnm.64", | |
8839 | OPCODE_INFO3 (0xf4000d00, | |
8840 | OPRND_SHIFT0 (0_4, FREG), | |
8841 | OPRND_SHIFT0 (16_20, FREG), | |
8842 | OPRND_SHIFT0 (21_25, FREG)), | |
8843 | CSKY_ISA_FLOAT_7E60), | |
8844 | OP32 ("fminnm.64", | |
8845 | OPCODE_INFO3 (0xf4000d20, | |
8846 | OPRND_SHIFT0 (0_4, FREG), | |
8847 | OPRND_SHIFT0 (16_20, FREG), | |
8848 | OPRND_SHIFT0 (21_25, FREG)), | |
8849 | CSKY_ISA_FLOAT_7E60), | |
8850 | OP32 ("fcmphz.64", | |
8851 | OPCODE_INFO1 (0xf4000d40, | |
8852 | OPRND_SHIFT0 (16_20, FREG)), | |
8853 | CSKY_ISA_FLOAT_7E60), | |
8854 | OP32 ("fcmplsz.64", | |
8855 | OPCODE_INFO1 (0xf4000d60, | |
8856 | OPRND_SHIFT0 (16_20, FREG)), | |
8857 | CSKY_ISA_FLOAT_7E60), | |
8858 | OP32 ("fmul.64", | |
8859 | OPCODE_INFO3 (0xf4000a00, | |
8860 | OPRND_SHIFT0 (0_4, FREG), | |
8861 | OPRND_SHIFT0 (16_20, FREG), | |
8862 | OPRND_SHIFT0 (21_25, FREG)), | |
8863 | CSKY_ISA_FLOAT_7E60), | |
8864 | OP32 ("fmuld", | |
8865 | OPCODE_INFO3 (0xf4000a00, | |
8866 | OPRND_SHIFT0 (0_4, FREG), | |
8867 | OPRND_SHIFT0 (16_20, FREG), | |
8868 | OPRND_SHIFT0 (21_25, FREG)), | |
8869 | CSKY_ISA_FLOAT_7E60), | |
8870 | OP32 ("fnmul.64", | |
8871 | OPCODE_INFO3 (0xf4000a20, | |
8872 | OPRND_SHIFT0 (0_4, FREG), | |
8873 | OPRND_SHIFT0 (16_20, FREG), | |
8874 | OPRND_SHIFT0 (21_25, FREG)), | |
8875 | CSKY_ISA_FLOAT_7E60), | |
8876 | OP32 ("fnmuld", | |
8877 | OPCODE_INFO3 (0xf4000a20, | |
8878 | OPRND_SHIFT0 (0_4, FREG), | |
8879 | OPRND_SHIFT0 (16_20, FREG), | |
8880 | OPRND_SHIFT0 (21_25, FREG)), | |
8881 | CSKY_ISA_FLOAT_7E60), | |
8882 | OP32 ("fmula.64", | |
8883 | OPCODE_INFO3 (0xf4000a80, | |
8884 | OPRND_SHIFT0 (0_4, FREG), | |
8885 | OPRND_SHIFT0 (16_20, FREG), | |
8886 | OPRND_SHIFT0 (21_25, FREG)), | |
8887 | CSKY_ISA_FLOAT_7E60), | |
8888 | OP32 ("fmacd", | |
8889 | OPCODE_INFO3 (0xf4000a80, | |
8890 | OPRND_SHIFT0 (0_4, FREG), | |
8891 | OPRND_SHIFT0 (16_20, FREG), | |
8892 | OPRND_SHIFT0 (21_25, FREG)), | |
8893 | CSKY_ISA_FLOAT_7E60), | |
8894 | OP32 ("fnmuls.64", | |
8895 | OPCODE_INFO3 (0xf4000aa0, | |
8896 | OPRND_SHIFT0 (0_4, FREG), | |
8897 | OPRND_SHIFT0 (16_20, FREG), | |
8898 | OPRND_SHIFT0 (21_25, FREG)), | |
8899 | CSKY_ISA_FLOAT_7E60), | |
8900 | OP32 ("fmscd", | |
8901 | OPCODE_INFO3 (0xf4000aa0, | |
8902 | OPRND_SHIFT0 (0_4, FREG), | |
8903 | OPRND_SHIFT0 (16_20, FREG), | |
8904 | OPRND_SHIFT0 (21_25, FREG)), | |
8905 | CSKY_ISA_FLOAT_7E60), | |
8906 | OP32 ("fmuls.64", | |
8907 | OPCODE_INFO3 (0xf4000ac0, | |
8908 | OPRND_SHIFT0 (0_4, FREG), | |
8909 | OPRND_SHIFT0 (16_20, FREG), | |
8910 | OPRND_SHIFT0 (21_25, FREG)), | |
8911 | CSKY_ISA_FLOAT_7E60), | |
8912 | OP32 ("fnmacd", | |
8913 | OPCODE_INFO3 (0xf4000ac0, | |
8914 | OPRND_SHIFT0 (0_4, FREG), | |
8915 | OPRND_SHIFT0 (16_20, FREG), | |
8916 | OPRND_SHIFT0 (21_25, FREG)), | |
8917 | CSKY_ISA_FLOAT_7E60), | |
8918 | OP32 ("fnmula.64", | |
8919 | OPCODE_INFO3 (0xf4000ae0, | |
8920 | OPRND_SHIFT0 (0_4, FREG), | |
8921 | OPRND_SHIFT0 (16_20, FREG), | |
8922 | OPRND_SHIFT0 (21_25, FREG)), | |
8923 | CSKY_ISA_FLOAT_7E60), | |
8924 | OP32 ("fnmscd", | |
8925 | OPCODE_INFO3 (0xf4000ae0, | |
8926 | OPRND_SHIFT0 (0_4, FREG), | |
8927 | OPRND_SHIFT0 (16_20, FREG), | |
8928 | OPRND_SHIFT0 (21_25, FREG)), | |
8929 | CSKY_ISA_FLOAT_7E60), | |
8930 | OP32 ("ffmula.64", | |
8931 | OPCODE_INFO3 (0xf4000e00, | |
8932 | OPRND_SHIFT0 (0_4, FREG), | |
8933 | OPRND_SHIFT0 (16_20, FREG), | |
8934 | OPRND_SHIFT0 (21_25, FREG)), | |
8935 | CSKY_ISA_FLOAT_7E60), | |
8936 | OP32 ("ffmuls.64", | |
8937 | OPCODE_INFO3 (0xf4000e20, | |
8938 | OPRND_SHIFT0 (0_4, FREG), | |
8939 | OPRND_SHIFT0 (16_20, FREG), | |
8940 | OPRND_SHIFT0 (21_25, FREG)), | |
8941 | CSKY_ISA_FLOAT_7E60), | |
8942 | OP32 ("ffnmula.64", | |
8943 | OPCODE_INFO3 (0xf4000e40, | |
8944 | OPRND_SHIFT0 (0_4, FREG), | |
8945 | OPRND_SHIFT0 (16_20, FREG), | |
8946 | OPRND_SHIFT0 (21_25, FREG)), | |
8947 | CSKY_ISA_FLOAT_7E60), | |
8948 | OP32 ("ffnmuls.64", | |
8949 | OPCODE_INFO3 (0xf4000e60, | |
8950 | OPRND_SHIFT0 (0_4, FREG), | |
8951 | OPRND_SHIFT0 (16_20, FREG), | |
8952 | OPRND_SHIFT0 (21_25, FREG)), | |
8953 | CSKY_ISA_FLOAT_7E60), | |
8954 | OP32 ("fdiv.64", | |
8955 | OPCODE_INFO3 (0xf4000b00, | |
8956 | OPRND_SHIFT0 (0_4, FREG), | |
8957 | OPRND_SHIFT0 (16_20, FREG), | |
8958 | OPRND_SHIFT0 (21_25, FREG)), | |
8959 | CSKY_ISA_FLOAT_7E60), | |
8960 | OP32 ("fdivd", | |
8961 | OPCODE_INFO3 (0xf4000b00, | |
8962 | OPRND_SHIFT0 (0_4, FREG), | |
8963 | OPRND_SHIFT0 (16_20, FREG), | |
8964 | OPRND_SHIFT0 (21_25, FREG)), | |
8965 | CSKY_ISA_FLOAT_7E60), | |
8966 | OP32 ("frecip.64", | |
8967 | OPCODE_INFO2 (0xf4000b20, | |
8968 | OPRND_SHIFT0 (0_4, FREG), | |
8969 | OPRND_SHIFT0 (16_20, FREG)), | |
8970 | CSKY_ISA_FLOAT_7E60), | |
8971 | OP32 ("frecipd", | |
8972 | OPCODE_INFO2 (0xf4000b20, | |
8973 | OPRND_SHIFT0 (0_4, FREG), | |
8974 | OPRND_SHIFT0 (16_20, FREG)), | |
8975 | CSKY_ISA_FLOAT_7E60), | |
8976 | OP32 ("fsqrt.64", | |
8977 | OPCODE_INFO2 (0xf4000b40, | |
8978 | OPRND_SHIFT0 (0_4, FREG), | |
8979 | OPRND_SHIFT0 (16_20, FREG)), | |
8980 | CSKY_ISA_FLOAT_7E60), | |
8981 | OP32 ("fsqrtd", | |
8982 | OPCODE_INFO2 (0xf4000b40, | |
8983 | OPRND_SHIFT0 (0_4, FREG), | |
8984 | OPRND_SHIFT0 (16_20, FREG)), | |
8985 | CSKY_ISA_FLOAT_7E60), | |
8986 | OP32 ("fins.32", | |
8987 | OPCODE_INFO2 (0xf4000360, | |
8988 | OPRND_SHIFT0 (0_4, FREG), | |
8989 | OPRND_SHIFT0 (16_20, FREG)), | |
8990 | CSKY_ISA_FLOAT_7E60), | |
8991 | OP32 ("fsel.64", | |
8992 | OPCODE_INFO3 (0xf4000f20, | |
8993 | OPRND_SHIFT0 (0_4, FREG), | |
8994 | OPRND_SHIFT0 (16_20, FREG), | |
8995 | OPRND_SHIFT0 (21_25, FREG)), | |
8996 | CSKY_ISA_FLOAT_7E60), | |
8997 | /* SIMD floating. */ | |
8998 | OP32 ("fadd.f32", | |
8999 | OPCODE_INFO3 (0xf4001000, | |
9000 | OPRND_SHIFT0 (0_4, FREG), | |
9001 | OPRND_SHIFT0 (16_20, FREG), | |
9002 | OPRND_SHIFT0 (21_25, FREG)), | |
9003 | CSKY_ISA_FLOAT_7E60), | |
9004 | OP32 ("faddm", | |
9005 | OPCODE_INFO3 (0xf4001000, | |
9006 | OPRND_SHIFT0 (0_4, FREG), | |
9007 | OPRND_SHIFT0 (16_20, FREG), | |
9008 | OPRND_SHIFT0 (21_25, FREG)), | |
9009 | CSKY_ISA_FLOAT_7E60), | |
9010 | OP32 ("fsub.f32", | |
9011 | OPCODE_INFO3 (0xf4001020, | |
9012 | OPRND_SHIFT0 (0_4, FREG), | |
9013 | OPRND_SHIFT0 (16_20, FREG), | |
9014 | OPRND_SHIFT0 (21_25, FREG)), | |
9015 | CSKY_ISA_FLOAT_7E60), | |
9016 | OP32 ("fsubm", | |
9017 | OPCODE_INFO3 (0xf4001020, | |
9018 | OPRND_SHIFT0 (0_4, FREG), | |
9019 | OPRND_SHIFT0 (16_20, FREG), | |
9020 | OPRND_SHIFT0 (21_25, FREG)), | |
9021 | CSKY_ISA_FLOAT_7E60), | |
9022 | OP32 ("fmov.f32", | |
9023 | OPCODE_INFO2 (0xf4001080, | |
9024 | OPRND_SHIFT0 (0_4, FREG), | |
9025 | OPRND_SHIFT0 (16_20, FREG)), | |
9026 | CSKY_ISA_FLOAT_7E60), | |
9027 | OP32 ("fmovm", | |
9028 | OPCODE_INFO2 (0xf4001080, | |
9029 | OPRND_SHIFT0 (0_4, FREG), | |
9030 | OPRND_SHIFT0 (16_20, FREG)), | |
9031 | CSKY_ISA_FLOAT_7E60), | |
9032 | OP32 ("fabs.f32", | |
9033 | OPCODE_INFO2 (0xf40010c0, | |
9034 | OPRND_SHIFT0 (0_4, FREG), | |
9035 | OPRND_SHIFT0 (16_20, FREG)), | |
9036 | CSKY_ISA_FLOAT_7E60), | |
9037 | OP32 ("fabsm", | |
9038 | OPCODE_INFO2 (0xf40010c0, | |
9039 | OPRND_SHIFT0 (0_4, FREG), | |
9040 | OPRND_SHIFT0 (16_20, FREG)), | |
9041 | CSKY_ISA_FLOAT_7E60), | |
9042 | OP32 ("fneg.f32", | |
9043 | OPCODE_INFO2 (0xf40010e0, | |
9044 | OPRND_SHIFT0 (0_4, FREG), | |
9045 | OPRND_SHIFT0 (16_20, FREG)), | |
9046 | CSKY_ISA_FLOAT_7E60), | |
9047 | OP32 ("fnegm", | |
9048 | OPCODE_INFO2 (0xf40010e0, | |
9049 | OPRND_SHIFT0 (0_4, FREG), | |
9050 | OPRND_SHIFT0 (16_20, FREG)), | |
9051 | CSKY_ISA_FLOAT_7E60), | |
9052 | OP32 ("fmul.f32", | |
9053 | OPCODE_INFO3 (0xf4001200, | |
9054 | OPRND_SHIFT0 (0_4, FREG), | |
9055 | OPRND_SHIFT0 (16_20, FREG), | |
9056 | OPRND_SHIFT0 (21_25, FREG)), | |
9057 | CSKY_ISA_FLOAT_7E60), | |
9058 | OP32 ("fmulm", | |
9059 | OPCODE_INFO3 (0xf4001200, | |
9060 | OPRND_SHIFT0 (0_4, FREG), | |
9061 | OPRND_SHIFT0 (16_20, FREG), | |
9062 | OPRND_SHIFT0 (21_25, FREG)), | |
9063 | CSKY_ISA_FLOAT_7E60), | |
9064 | OP32 ("fmula.f32", | |
9065 | OPCODE_INFO3 (0xf4001280, | |
9066 | OPRND_SHIFT0 (0_4, FREG), | |
9067 | OPRND_SHIFT0 (16_20, FREG), | |
9068 | OPRND_SHIFT0 (21_25, FREG)), | |
9069 | CSKY_ISA_FLOAT_7E60), | |
9070 | OP32 ("fmuls.f32", | |
9071 | OPCODE_INFO3 (0xf40012c0, | |
9072 | OPRND_SHIFT0 (0_4, FREG), | |
9073 | OPRND_SHIFT0 (16_20, FREG), | |
9074 | OPRND_SHIFT0 (21_25, FREG)), | |
9075 | CSKY_ISA_FLOAT_7E60), | |
9076 | OP32 ("fnmacm", | |
9077 | OPCODE_INFO3 (0xf40012c0, | |
9078 | OPRND_SHIFT0 (0_4, FREG), | |
9079 | OPRND_SHIFT0 (16_20, FREG), | |
9080 | OPRND_SHIFT0 (21_25, FREG)), | |
9081 | CSKY_ISA_FLOAT_7E60), | |
9082 | /* floating formate. */ | |
9083 | OP32 ("fftoi.f32.s32.rn", | |
9084 | OPCODE_INFO2 (0xf4001800, | |
9085 | OPRND_SHIFT0 (0_4, FREG), | |
9086 | OPRND_SHIFT0 (16_20, FREG)), | |
9087 | CSKY_ISA_FLOAT_7E60), | |
9088 | OP32 ("fstosi.rn", | |
9089 | OPCODE_INFO2 (0xf4001800, | |
9090 | OPRND_SHIFT0 (0_4, FREG), | |
9091 | OPRND_SHIFT0 (16_20, FREG)), | |
9092 | CSKY_ISA_FLOAT_7E60), | |
9093 | OP32 ("fftoi.f32.s32.rz", | |
9094 | OPCODE_INFO2 (0xf4001820, | |
9095 | OPRND_SHIFT0 (0_4, FREG), | |
9096 | OPRND_SHIFT0 (16_20, FREG)), | |
9097 | CSKY_ISA_FLOAT_7E60), | |
9098 | OP32 ("fstosi.rz", | |
9099 | OPCODE_INFO2 (0xf4001820, | |
9100 | OPRND_SHIFT0 (0_4, FREG), | |
9101 | OPRND_SHIFT0 (16_20, FREG)), | |
9102 | CSKY_ISA_FLOAT_7E60), | |
9103 | OP32 ("fftoi.f32.s32.rpi", | |
9104 | OPCODE_INFO2 (0xf4001840, | |
9105 | OPRND_SHIFT0 (0_4, FREG), | |
9106 | OPRND_SHIFT0 (16_20, FREG)), | |
9107 | CSKY_ISA_FLOAT_7E60), | |
9108 | OP32 ("fstosi.rpi", | |
9109 | OPCODE_INFO2 (0xf4001840, | |
9110 | OPRND_SHIFT0 (0_4, FREG), | |
9111 | OPRND_SHIFT0 (16_20, FREG)), | |
9112 | CSKY_ISA_FLOAT_7E60), | |
9113 | OP32 ("fftoi.f32.s32.rni", | |
9114 | OPCODE_INFO2 (0xf4001860, | |
9115 | OPRND_SHIFT0 (0_4, FREG), | |
9116 | OPRND_SHIFT0 (16_20, FREG)), | |
9117 | CSKY_ISA_FLOAT_7E60), | |
9118 | OP32 ("fstosi.rni", | |
9119 | OPCODE_INFO2 (0xf4001860, | |
9120 | OPRND_SHIFT0 (0_4, FREG), | |
9121 | OPRND_SHIFT0 (16_20, FREG)), | |
9122 | CSKY_ISA_FLOAT_7E60), | |
9123 | OP32 ("fftoi.f32.u32.rn", | |
9124 | OPCODE_INFO2 (0xf4001880, | |
9125 | OPRND_SHIFT0 (0_4, FREG), | |
9126 | OPRND_SHIFT0 (16_20, FREG)), | |
9127 | CSKY_ISA_FLOAT_7E60), | |
9128 | OP32 ("fstoui.rn", | |
9129 | OPCODE_INFO2 (0xf4001880, | |
9130 | OPRND_SHIFT0 (0_4, FREG), | |
9131 | OPRND_SHIFT0 (16_20, FREG)), | |
9132 | CSKY_ISA_FLOAT_7E60), | |
9133 | OP32 ("fftoi.f32.u32.rz", | |
9134 | OPCODE_INFO2 (0xf40018a0, | |
9135 | OPRND_SHIFT0 (0_4, FREG), | |
9136 | OPRND_SHIFT0 (16_20, FREG)), | |
9137 | CSKY_ISA_FLOAT_7E60), | |
9138 | OP32 ("fstoui.rz", | |
9139 | OPCODE_INFO2 (0xf40018a0, | |
9140 | OPRND_SHIFT0 (0_4, FREG), | |
9141 | OPRND_SHIFT0 (16_20, FREG)), | |
9142 | CSKY_ISA_FLOAT_7E60), | |
9143 | OP32 ("fftoi.f32.u32.rpi", | |
9144 | OPCODE_INFO2 (0xf40018c0, | |
9145 | OPRND_SHIFT0 (0_4, FREG), | |
9146 | OPRND_SHIFT0 (16_20, FREG)), | |
9147 | CSKY_ISA_FLOAT_7E60), | |
9148 | OP32 ("fstoui.rpi", | |
9149 | OPCODE_INFO2 (0xf40018c0, | |
9150 | OPRND_SHIFT0 (0_4, FREG), | |
9151 | OPRND_SHIFT0 (16_20, FREG)), | |
9152 | CSKY_ISA_FLOAT_7E60), | |
9153 | OP32 ("fftoi.f32.u32.rni", | |
9154 | OPCODE_INFO2 (0xf40018e0, | |
9155 | OPRND_SHIFT0 (0_4, FREG), | |
9156 | OPRND_SHIFT0 (16_20, FREG)), | |
9157 | CSKY_ISA_FLOAT_7E60), | |
9158 | OP32 ("fstoui.rni", | |
9159 | OPCODE_INFO2 (0xf40018e0, | |
9160 | OPRND_SHIFT0 (0_4, FREG), | |
9161 | OPRND_SHIFT0 (16_20, FREG)), | |
9162 | CSKY_ISA_FLOAT_7E60), | |
9163 | OP32 ("fftoi.f64.s32.rn", | |
9164 | OPCODE_INFO2 (0xf4001900, | |
9165 | OPRND_SHIFT0 (0_4, FREG), | |
9166 | OPRND_SHIFT0 (16_20, FREG)), | |
9167 | CSKY_ISA_FLOAT_7E60), | |
9168 | OP32 ("fdtosi.rn", | |
9169 | OPCODE_INFO2 (0xf4001900, | |
9170 | OPRND_SHIFT0 (0_4, FREG), | |
9171 | OPRND_SHIFT0 (16_20, FREG)), | |
9172 | CSKY_ISA_FLOAT_7E60), | |
9173 | OP32 ("fftoi.f64.s32.rz", | |
9174 | OPCODE_INFO2 (0xf4001920, | |
9175 | OPRND_SHIFT0 (0_4, FREG), | |
9176 | OPRND_SHIFT0 (16_20, FREG)), | |
9177 | CSKY_ISA_FLOAT_7E60), | |
9178 | OP32 ("fdtosi.rz", | |
9179 | OPCODE_INFO2 (0xf4001920, | |
9180 | OPRND_SHIFT0 (0_4, FREG), | |
9181 | OPRND_SHIFT0 (16_20, FREG)), | |
9182 | CSKY_ISA_FLOAT_7E60), | |
9183 | OP32 ("fftoi.f64.s32.rpi", | |
9184 | OPCODE_INFO2 (0xf4001940, | |
9185 | OPRND_SHIFT0 (0_4, FREG), | |
9186 | OPRND_SHIFT0 (16_20, FREG)), | |
9187 | CSKY_ISA_FLOAT_7E60), | |
9188 | OP32 ("fdtosi.rpi", | |
9189 | OPCODE_INFO2 (0xf4001940, | |
9190 | OPRND_SHIFT0 (0_4, FREG), | |
9191 | OPRND_SHIFT0 (16_20, FREG)), | |
9192 | CSKY_ISA_FLOAT_7E60), | |
9193 | OP32 ("fftoi.f64.s32.rni", | |
9194 | OPCODE_INFO2 (0xf4001960, | |
9195 | OPRND_SHIFT0 (0_4, FREG), | |
9196 | OPRND_SHIFT0 (16_20, FREG)), | |
9197 | CSKY_ISA_FLOAT_7E60), | |
9198 | OP32 ("fdtosi.rni", | |
9199 | OPCODE_INFO2 (0xf4001960, | |
9200 | OPRND_SHIFT0 (0_4, FREG), | |
9201 | OPRND_SHIFT0 (16_20, FREG)), | |
9202 | CSKY_ISA_FLOAT_7E60), | |
9203 | OP32 ("fftoi.f64.u32.rn", | |
9204 | OPCODE_INFO2 (0xf4001980, | |
9205 | OPRND_SHIFT0 (0_4, FREG), | |
9206 | OPRND_SHIFT0 (16_20, FREG)), | |
9207 | CSKY_ISA_FLOAT_7E60), | |
9208 | OP32 ("fdtoui.rn", | |
9209 | OPCODE_INFO2 (0xf4001980, | |
9210 | OPRND_SHIFT0 (0_4, FREG), | |
9211 | OPRND_SHIFT0 (16_20, FREG)), | |
9212 | CSKY_ISA_FLOAT_7E60), | |
9213 | OP32 ("fftoi.f64.u32.rz", | |
9214 | OPCODE_INFO2 (0xf40019a0, | |
9215 | OPRND_SHIFT0 (0_4, FREG), | |
9216 | OPRND_SHIFT0 (16_20, FREG)), | |
9217 | CSKY_ISA_FLOAT_7E60), | |
9218 | OP32 ("fdtoui.rz", | |
9219 | OPCODE_INFO2 (0xf40019a0, | |
9220 | OPRND_SHIFT0 (0_4, FREG), | |
9221 | OPRND_SHIFT0 (16_20, FREG)), | |
9222 | CSKY_ISA_FLOAT_7E60), | |
9223 | OP32 ("fftoi.f64.u32.rpi", | |
9224 | OPCODE_INFO2 (0xf40019c0, | |
9225 | OPRND_SHIFT0 (0_4, FREG), | |
9226 | OPRND_SHIFT0 (16_20, FREG)), | |
9227 | CSKY_ISA_FLOAT_7E60), | |
9228 | OP32 ("fdtoui.rpi", | |
9229 | OPCODE_INFO2 (0xf40019c0, | |
9230 | OPRND_SHIFT0 (0_4, FREG), | |
9231 | OPRND_SHIFT0 (16_20, FREG)), | |
9232 | CSKY_ISA_FLOAT_7E60), | |
9233 | OP32 ("fftoi.f64.u32.rni", | |
9234 | OPCODE_INFO2 (0xf40019e0, | |
9235 | OPRND_SHIFT0 (0_4, FREG), | |
9236 | OPRND_SHIFT0 (16_20, FREG)), | |
9237 | CSKY_ISA_FLOAT_7E60), | |
9238 | OP32 ("fdtoui.rni", | |
9239 | OPCODE_INFO2 (0xf40019e0, | |
9240 | OPRND_SHIFT0 (0_4, FREG), | |
9241 | OPRND_SHIFT0 (16_20, FREG)), | |
9242 | CSKY_ISA_FLOAT_7E60), | |
9243 | OP32 ("fftoi.f16.s32.rn", | |
9244 | OPCODE_INFO2 (0xf4001c00, | |
9245 | OPRND_SHIFT0 (0_4, FREG), | |
9246 | OPRND_SHIFT0 (16_20, FREG)), | |
9247 | CSKY_ISA_FLOAT_7E60), | |
9248 | OP32 ("fhtosi.rn", | |
9249 | OPCODE_INFO2 (0xf4001c00, | |
9250 | OPRND_SHIFT0 (0_4, FREG), | |
9251 | OPRND_SHIFT0 (16_20, FREG)), | |
9252 | CSKY_ISA_FLOAT_7E60), | |
9253 | OP32 ("fftoi.f16.s32.rz", | |
9254 | OPCODE_INFO2 (0xf4001c20, | |
9255 | OPRND_SHIFT0 (0_4, FREG), | |
9256 | OPRND_SHIFT0 (16_20, FREG)), | |
9257 | CSKY_ISA_FLOAT_7E60), | |
9258 | OP32 ("fhtosi.rz", | |
9259 | OPCODE_INFO2 (0xf4001c20, | |
9260 | OPRND_SHIFT0 (0_4, FREG), | |
9261 | OPRND_SHIFT0 (16_20, FREG)), | |
9262 | CSKY_ISA_FLOAT_7E60), | |
9263 | OP32 ("fftoi.f16.s32.rpi", | |
9264 | OPCODE_INFO2 (0xf4001c40, | |
9265 | OPRND_SHIFT0 (0_4, FREG), | |
9266 | OPRND_SHIFT0 (16_20, FREG)), | |
9267 | CSKY_ISA_FLOAT_7E60), | |
9268 | OP32 ("fhtosi.rpi", | |
9269 | OPCODE_INFO2 (0xf4001c40, | |
9270 | OPRND_SHIFT0 (0_4, FREG), | |
9271 | OPRND_SHIFT0 (16_20, FREG)), | |
9272 | CSKY_ISA_FLOAT_7E60), | |
9273 | OP32 ("fftoi.f16.s32.rni", | |
9274 | OPCODE_INFO2 (0xf4001c60, | |
9275 | OPRND_SHIFT0 (0_4, FREG), | |
9276 | OPRND_SHIFT0 (16_20, FREG)), | |
9277 | CSKY_ISA_FLOAT_7E60), | |
9278 | OP32 ("fhtosi.rni", | |
9279 | OPCODE_INFO2 (0xf4001c60, | |
9280 | OPRND_SHIFT0 (0_4, FREG), | |
9281 | OPRND_SHIFT0 (16_20, FREG)), | |
9282 | CSKY_ISA_FLOAT_7E60), | |
9283 | OP32 ("fftoi.f16.u32.rn", | |
9284 | OPCODE_INFO2 (0xf4001c80, | |
9285 | OPRND_SHIFT0 (0_4, FREG), | |
9286 | OPRND_SHIFT0 (16_20, FREG)), | |
9287 | CSKY_ISA_FLOAT_7E60), | |
9288 | OP32 ("fhtoui.rn", | |
9289 | OPCODE_INFO2 (0xf4001c80, | |
9290 | OPRND_SHIFT0 (0_4, FREG), | |
9291 | OPRND_SHIFT0 (16_20, FREG)), | |
9292 | CSKY_ISA_FLOAT_7E60), | |
9293 | OP32 ("fftoi.f16.u32.rz", | |
9294 | OPCODE_INFO2 (0xf4001ca0, | |
9295 | OPRND_SHIFT0 (0_4, FREG), | |
9296 | OPRND_SHIFT0 (16_20, FREG)), | |
9297 | CSKY_ISA_FLOAT_7E60), | |
9298 | OP32 ("fhtoui.rz", | |
9299 | OPCODE_INFO2 (0xf4001ca0, | |
9300 | OPRND_SHIFT0 (0_4, FREG), | |
9301 | OPRND_SHIFT0 (16_20, FREG)), | |
9302 | CSKY_ISA_FLOAT_7E60), | |
9303 | OP32 ("fftoi.f16.u32.rpi", | |
9304 | OPCODE_INFO2 (0xf4001cc0, | |
9305 | OPRND_SHIFT0 (0_4, FREG), | |
9306 | OPRND_SHIFT0 (16_20, FREG)), | |
9307 | CSKY_ISA_FLOAT_7E60), | |
9308 | OP32 ("fhtoui.rpi", | |
9309 | OPCODE_INFO2 (0xf4001cc0, | |
9310 | OPRND_SHIFT0 (0_4, FREG), | |
9311 | OPRND_SHIFT0 (16_20, FREG)), | |
9312 | CSKY_ISA_FLOAT_7E60), | |
9313 | OP32 ("fftoi.f16.u32.rni", | |
9314 | OPCODE_INFO2 (0xf4001ce0, | |
9315 | OPRND_SHIFT0 (0_4, FREG), | |
9316 | OPRND_SHIFT0 (16_20, FREG)), | |
9317 | CSKY_ISA_FLOAT_7E60), | |
9318 | OP32 ("fhtoui.rni", | |
9319 | OPCODE_INFO2 (0xf4001ce0, | |
9320 | OPRND_SHIFT0 (0_4, FREG), | |
9321 | OPRND_SHIFT0 (16_20, FREG)), | |
9322 | CSKY_ISA_FLOAT_7E60), | |
9323 | OP32 ("fhtos", | |
9324 | OPCODE_INFO2 (0xf4001a40, | |
9325 | OPRND_SHIFT0 (0_4, FREG), | |
9326 | OPRND_SHIFT0 (16_20, FREG)), | |
9327 | CSKY_ISA_FLOAT_7E60), | |
9328 | OP32 ("fhtos.f16", | |
9329 | OPCODE_INFO2 (0xf4001a40, | |
9330 | OPRND_SHIFT0 (0_4, FREG), | |
9331 | OPRND_SHIFT0 (16_20, FREG)), | |
9332 | CSKY_ISA_FLOAT_7E60), | |
9333 | OP32 ("fstoh", | |
9334 | OPCODE_INFO2 (0xf4001a60, | |
9335 | OPRND_SHIFT0 (0_4, FREG), | |
9336 | OPRND_SHIFT0 (16_20, FREG)), | |
9337 | CSKY_ISA_FLOAT_7E60), | |
9338 | OP32 ("fstoh.f32", | |
9339 | OPCODE_INFO2 (0xf4001a60, | |
9340 | OPRND_SHIFT0 (0_4, FREG), | |
9341 | OPRND_SHIFT0 (16_20, FREG)), | |
9342 | CSKY_ISA_FLOAT_7E60), | |
9343 | OP32 ("fdtos", | |
9344 | OPCODE_INFO2 (0xf4001ac0, | |
9345 | OPRND_SHIFT0 (0_4, FREG), | |
9346 | OPRND_SHIFT0 (16_20, FREG)), | |
9347 | CSKY_ISA_FLOAT_7E60), | |
9348 | OP32 ("fdtos.f64", | |
9349 | OPCODE_INFO2 (0xf4001ac0, | |
9350 | OPRND_SHIFT0 (0_4, FREG), | |
9351 | OPRND_SHIFT0 (16_20, FREG)), | |
9352 | CSKY_ISA_FLOAT_7E60), | |
9353 | OP32 ("fstod", | |
9354 | OPCODE_INFO2 (0xf4001ae0, | |
9355 | OPRND_SHIFT0 (0_4, FREG), | |
9356 | OPRND_SHIFT0 (16_20, FREG)), | |
9357 | CSKY_ISA_FLOAT_7E60), | |
9358 | OP32 ("fmfvrh", | |
9359 | OPCODE_INFO2 (0xf4001b00, | |
9360 | OPRND_SHIFT0 (0_4, AREG), | |
9361 | OPRND_SHIFT0 (16_20, FREG)), | |
9362 | CSKY_ISA_FLOAT_7E60), | |
9363 | OP32 ("fmfvr.32.1", | |
9364 | OPCODE_INFO2 (0xf4001b20, | |
9365 | OPRND_SHIFT0 (0_4, AREG), | |
9366 | OPRND_SHIFT0 (16_20, FREG)), | |
9367 | CSKY_ISA_FLOAT_7E60), | |
9368 | OP32 ("fmfvrl", | |
9369 | OPCODE_INFO2 (0xf4001b20, | |
9370 | OPRND_SHIFT0 (0_4, AREG), | |
9371 | OPRND_SHIFT0 (16_20, FREG)), | |
9372 | CSKY_ISA_FLOAT_7E60), | |
9373 | OP32 ("fmtvr.16", | |
9374 | OPCODE_INFO2 (0xf4001fa0, | |
9375 | OPRND_SHIFT0 (0_4, FREG), | |
9376 | OPRND_SHIFT0 (16_20, AREG)), | |
9377 | CSKY_ISA_FLOAT_7E60), | |
9378 | OP32 ("fmfvr.16", | |
9379 | OPCODE_INFO2 (0xf4001f20, | |
9380 | OPRND_SHIFT0 (0_4, AREG), | |
9381 | OPRND_SHIFT0 (16_20, FREG)), | |
9382 | CSKY_ISA_FLOAT_7E60), | |
9383 | OP32 ("fmtvrh", | |
9384 | OPCODE_INFO2 (0xf4001b40, | |
9385 | OPRND_SHIFT0 (0_4, FREG), | |
9386 | OPRND_SHIFT0 (16_20, AREG)), | |
9387 | CSKY_ISA_FLOAT_7E60), | |
9388 | OP32 ("fmtvr.32.1", | |
9389 | OPCODE_INFO2 (0xf4001b60, | |
9390 | OPRND_SHIFT0 (0_4, FREG), | |
9391 | OPRND_SHIFT0 (16_20, AREG)), | |
9392 | CSKY_ISA_FLOAT_7E60), | |
9393 | OP32 ("fmtvrl", | |
9394 | OPCODE_INFO2 (0xf4001b60, | |
9395 | OPRND_SHIFT0 (0_4, FREG), | |
9396 | OPRND_SHIFT0 (16_20, AREG)), | |
9397 | CSKY_ISA_FLOAT_7E60), | |
9398 | OP32 ("fmtvr.64", | |
9399 | OPCODE_INFO3 (0xf4001f80, | |
9400 | OPRND_SHIFT0 (0_4, FREG), | |
9401 | OPRND_SHIFT0 (16_20, AREG), | |
9402 | OPRND_SHIFT0 (21_25, AREG)), | |
9403 | CSKY_ISA_FLOAT_7E60), | |
9404 | OP32 ("fmfvr.64", | |
9405 | OPCODE_INFO3 (0xf4001f00, | |
9406 | OPRND_SHIFT0 (0_4, AREG), | |
9407 | OPRND_SHIFT0 (21_25, AREG), | |
9408 | OPRND_SHIFT0 (16_20, FREG)), | |
9409 | CSKY_ISA_FLOAT_7E60), | |
9410 | OP32 ("fmtvr.32.2", | |
9411 | OPCODE_INFO3 (0xf4001fc0, | |
9412 | OPRND_SHIFT0 (0_4, FREG), | |
9413 | OPRND_SHIFT0 (16_20, AREG), | |
9414 | OPRND_SHIFT0 (21_25, AREG)), | |
9415 | CSKY_ISA_FLOAT_7E60), | |
9416 | OP32 ("fmfvr.32.2", | |
9417 | OPCODE_INFO3 (0xf4001f40, | |
9418 | OPRND_SHIFT0 (0_4, AREG), | |
9419 | OPRND_SHIFT0 (21_25, AREG), | |
9420 | OPRND_SHIFT0 (16_20, FREG)), | |
9421 | CSKY_ISA_FLOAT_7E60), | |
9422 | /* flsu. */ | |
9423 | OP32 ("fld.16", | |
9424 | SOPCODE_INFO2 (0xf4002300, | |
9425 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9426 | BRACKET_OPRND ((16_20, | |
9427 | AREG, | |
9428 | OPRND_SHIFT_0_BIT), | |
9429 | (4_7or21_24, | |
9430 | IMM_FLDST, | |
9431 | OPRND_SHIFT_1_BIT))), | |
9432 | CSKY_ISA_FLOAT_7E60), | |
9433 | OP32 ("fldh", | |
9434 | SOPCODE_INFO2 (0xf4002300, | |
9435 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9436 | BRACKET_OPRND ((16_20, | |
9437 | AREG, | |
9438 | OPRND_SHIFT_0_BIT), | |
9439 | (4_7or21_24, | |
9440 | IMM_FLDST, | |
9441 | OPRND_SHIFT_1_BIT))), | |
9442 | CSKY_ISA_FLOAT_7E60), | |
9443 | OP32_WITH_WORK ("fst.16", | |
9444 | SOPCODE_INFO2 (0xf4002700, | |
9445 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9446 | BRACKET_OPRND ((16_20, | |
9447 | AREG, | |
9448 | OPRND_SHIFT_0_BIT), | |
9449 | (4_7or21_24, | |
9450 | IMM_FLDST, | |
9451 | OPRND_SHIFT_1_BIT))), | |
9452 | CSKY_ISA_FLOAT_7E60, | |
9453 | float_work_fpuv3_fstore), | |
9454 | OP32_WITH_WORK ("fsth", | |
9455 | SOPCODE_INFO2 (0xf4002700, | |
9456 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9457 | BRACKET_OPRND ((16_20, | |
9458 | AREG, | |
9459 | OPRND_SHIFT_0_BIT), | |
9460 | (4_7or21_24, | |
9461 | IMM_FLDST, | |
9462 | OPRND_SHIFT_1_BIT))), | |
9463 | CSKY_ISA_FLOAT_7E60, | |
9464 | float_work_fpuv3_fstore), | |
9465 | OP32 ("fldr16", | |
9466 | SOPCODE_INFO2 (0xf4002b00, | |
9467 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9468 | BRACKET_OPRND ((16_20, | |
9469 | AREG, | |
9470 | OPRND_SHIFT_0_BIT), | |
9471 | (5_6or21_25, | |
9472 | AREG_WITH_LSHIFT_FPU, | |
9473 | OPRND_SHIFT_0_BIT))), | |
9474 | CSKY_ISA_FLOAT_7E60), | |
9475 | OP32 ("fldrh", | |
9476 | SOPCODE_INFO2 (0xf4002b00, | |
9477 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9478 | BRACKET_OPRND ((16_20, | |
9479 | AREG, | |
9480 | OPRND_SHIFT_0_BIT), | |
9481 | (5_6or21_25, | |
9482 | AREG_WITH_LSHIFT_FPU, | |
9483 | OPRND_SHIFT_0_BIT))), | |
9484 | CSKY_ISA_FLOAT_7E60), | |
9485 | OP32_WITH_WORK ("fstr.16", | |
9486 | SOPCODE_INFO2 (0xf4002f00, | |
9487 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9488 | BRACKET_OPRND ((16_20, | |
9489 | AREG, | |
9490 | OPRND_SHIFT_0_BIT), | |
9491 | (5_6or21_25, | |
9492 | AREG_WITH_LSHIFT_FPU, | |
9493 | OPRND_SHIFT_0_BIT))), | |
9494 | CSKY_ISA_FLOAT_7E60, | |
9495 | float_work_fpuv3_fstore), | |
9496 | OP32_WITH_WORK ("fstrh", | |
9497 | SOPCODE_INFO2 (0xf4002f00, | |
9498 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9499 | BRACKET_OPRND ((16_20, | |
9500 | AREG, | |
9501 | OPRND_SHIFT_0_BIT), | |
9502 | (5_6or21_25, | |
9503 | AREG_WITH_LSHIFT_FPU, | |
9504 | OPRND_SHIFT_0_BIT))), | |
9505 | CSKY_ISA_FLOAT_7E60, | |
9506 | float_work_fpuv3_fstore), | |
9507 | OP32 ("fldm.16", | |
9508 | OPCODE_INFO2 (0xf4003300, | |
9509 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
9510 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
9511 | CSKY_ISA_FLOAT_7E60), | |
9512 | OP32 ("fldmh", | |
9513 | OPCODE_INFO2 (0xf4003300, | |
9514 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
9515 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
9516 | CSKY_ISA_FLOAT_7E60), | |
9517 | OP32_WITH_WORK ("fstm.16", | |
9518 | OPCODE_INFO2 (0xf4003700, | |
9519 | (0_4or21_24, | |
9520 | FREGLIST_DASH, | |
9521 | OPRND_SHIFT_0_BIT), | |
9522 | (16_20, | |
9523 | AREG_WITH_BRACKET, | |
9524 | OPRND_SHIFT_0_BIT)), | |
9525 | CSKY_ISA_FLOAT_7E60, | |
9526 | float_work_fpuv3_fstore), | |
9527 | OP32_WITH_WORK ("fstmh", | |
9528 | OPCODE_INFO2 (0xf4003700, | |
9529 | (0_4or21_24, | |
9530 | FREGLIST_DASH, | |
9531 | OPRND_SHIFT_0_BIT), | |
9532 | (16_20, | |
9533 | AREG_WITH_BRACKET, | |
9534 | OPRND_SHIFT_0_BIT)), | |
9535 | CSKY_ISA_FLOAT_7E60, | |
9536 | float_work_fpuv3_fstore), | |
9537 | OP32 ("fldmu.16", | |
9538 | OPCODE_INFO2 (0xf4003380, | |
9539 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
9540 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9541 | CSKY_ISA_FLOAT_7E60), | |
9542 | OP32 ("fldmu.h", | |
9543 | OPCODE_INFO2 (0xf4003380, | |
9544 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
9545 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9546 | CSKY_ISA_FLOAT_7E60), | |
9547 | OP32_WITH_WORK ("fstmu.16", | |
9548 | OPCODE_INFO2 (0xf4003780, | |
9549 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
9550 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9551 | CSKY_ISA_FLOAT_7E60, | |
9552 | float_work_fpuv3_fstore), | |
9553 | OP32_WITH_WORK ("fstmu.h", | |
9554 | OPCODE_INFO2 (0xf4003780, | |
9555 | OPRND_SHIFT0 (0_4or21_24, FREGLIST_DASH), | |
9556 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9557 | CSKY_ISA_FLOAT_7E60, | |
9558 | float_work_fpuv3_fstore), | |
9559 | OP32 ("fld.32", | |
9560 | SOPCODE_INFO2 (0xf4002000, | |
9561 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9562 | BRACKET_OPRND ((16_20, | |
9563 | AREG, | |
9564 | OPRND_SHIFT_0_BIT), | |
9565 | (4_7or21_24, | |
9566 | IMM_FLDST, | |
9567 | OPRND_SHIFT_2_BIT))), | |
9568 | CSKY_ISA_FLOAT_7E60), | |
9569 | OP32 ("flds", | |
9570 | SOPCODE_INFO2 (0xf4002000, | |
9571 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9572 | BRACKET_OPRND ((16_20, | |
9573 | AREG, | |
9574 | OPRND_SHIFT_0_BIT), | |
9575 | (4_7or21_24, | |
9576 | IMM_FLDST, | |
9577 | OPRND_SHIFT_2_BIT))), | |
9578 | CSKY_ISA_FLOAT_7E60), | |
9579 | OP32_WITH_WORK ("fst.32", | |
9580 | SOPCODE_INFO2 (0xf4002400, | |
9581 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9582 | BRACKET_OPRND ((16_20, | |
9583 | AREG, | |
9584 | OPRND_SHIFT_0_BIT), | |
9585 | (4_7or21_24, | |
9586 | IMM_FLDST, | |
9587 | OPRND_SHIFT_2_BIT))), | |
9588 | CSKY_ISA_FLOAT_7E60, | |
9589 | float_work_fpuv3_fstore), | |
9590 | OP32_WITH_WORK ("fsts", | |
9591 | SOPCODE_INFO2 (0xf4002400, | |
9592 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9593 | BRACKET_OPRND ((16_20, | |
9594 | AREG, | |
9595 | OPRND_SHIFT_0_BIT), | |
9596 | (4_7or21_24, | |
9597 | IMM_FLDST, | |
9598 | OPRND_SHIFT_2_BIT))), | |
9599 | CSKY_ISA_FLOAT_7E60, | |
9600 | float_work_fpuv3_fstore), | |
9601 | OP32 ("fldr.32", | |
9602 | SOPCODE_INFO2 (0xf4002800, | |
9603 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9604 | BRACKET_OPRND ((16_20, | |
9605 | AREG, | |
9606 | OPRND_SHIFT_0_BIT), | |
9607 | (5_6or21_25, | |
9608 | AREG_WITH_LSHIFT_FPU, | |
9609 | OPRND_SHIFT_0_BIT))), | |
9610 | CSKY_ISA_FLOAT_7E60), | |
9611 | OP32 ("fldrs", | |
9612 | SOPCODE_INFO2 (0xf4002800, | |
9613 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9614 | BRACKET_OPRND ((16_20, | |
9615 | AREG, | |
9616 | OPRND_SHIFT_0_BIT), | |
9617 | (5_6or21_25, | |
9618 | AREG_WITH_LSHIFT_FPU, | |
9619 | OPRND_SHIFT_0_BIT))), | |
9620 | CSKY_ISA_FLOAT_7E60), | |
9621 | OP32_WITH_WORK ("fstr.32", | |
9622 | SOPCODE_INFO2 (0xf4002c00, | |
9623 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9624 | BRACKET_OPRND ((16_20, | |
9625 | AREG, | |
9626 | OPRND_SHIFT_0_BIT), | |
9627 | (5_6or21_25, | |
9628 | AREG_WITH_LSHIFT_FPU, | |
9629 | OPRND_SHIFT_0_BIT))), | |
9630 | CSKY_ISA_FLOAT_7E60, | |
9631 | float_work_fpuv3_fstore), | |
9632 | OP32_WITH_WORK ("fstrs", | |
9633 | SOPCODE_INFO2 (0xf4002c00, | |
9634 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9635 | BRACKET_OPRND ((16_20, | |
9636 | AREG, | |
9637 | OPRND_SHIFT_0_BIT), | |
9638 | (5_6or21_25, | |
9639 | AREG_WITH_LSHIFT_FPU, | |
9640 | OPRND_SHIFT_0_BIT))), | |
9641 | CSKY_ISA_FLOAT_7E60, | |
9642 | float_work_fpuv3_fstore), | |
9643 | OP32 ("fldm.32", | |
9644 | OPCODE_INFO2 (0xf4003000, | |
9645 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9646 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9647 | CSKY_ISA_FLOAT_7E60), | |
9648 | OP32 ("fldms", | |
9649 | OPCODE_INFO2 (0xf4003000, | |
9650 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9651 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9652 | CSKY_ISA_FLOAT_7E60), | |
9653 | OP32_WITH_WORK ("fstm.32", | |
9654 | OPCODE_INFO2 (0xf4003400, | |
9655 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9656 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9657 | CSKY_ISA_FLOAT_7E60, | |
9658 | float_work_fpuv3_fstore), | |
9659 | OP32_WITH_WORK ("fstms", | |
9660 | OPCODE_INFO2 (0xf4003400, | |
9661 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9662 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9663 | CSKY_ISA_FLOAT_7E60, | |
9664 | float_work_fpuv3_fstore), | |
9665 | OP32 ("fldmu.32", | |
9666 | OPCODE_INFO2 (0xf4003080, | |
9667 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9668 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9669 | CSKY_ISA_FLOAT_7E60), | |
9670 | OP32 ("fldmu.s", | |
9671 | OPCODE_INFO2 (0xf4003080, | |
9672 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9673 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9674 | CSKY_ISA_FLOAT_7E60), | |
9675 | OP32_WITH_WORK ("fstmu.32", | |
9676 | OPCODE_INFO2 (0xf4003480, | |
9677 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9678 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9679 | CSKY_ISA_FLOAT_7E60, | |
9680 | float_work_fpuv3_fstore), | |
9681 | OP32_WITH_WORK ("fstmu.s", | |
9682 | OPCODE_INFO2 (0xf4003480, | |
9683 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9684 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9685 | CSKY_ISA_FLOAT_7E60, | |
9686 | float_work_fpuv3_fstore), | |
9687 | OP32 ("fld.64", | |
9688 | SOPCODE_INFO2 (0xf4002100, | |
9689 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9690 | BRACKET_OPRND ((16_20, | |
9691 | AREG, | |
9692 | OPRND_SHIFT_0_BIT), | |
9693 | (4_7or21_24, | |
9694 | IMM_FLDST, | |
9695 | OPRND_SHIFT_2_BIT))), | |
9696 | CSKY_ISA_FLOAT_7E60), | |
9697 | OP32 ("fldd", | |
9698 | SOPCODE_INFO2 (0xf4002100, | |
9699 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9700 | BRACKET_OPRND ((16_20, | |
9701 | AREG, | |
9702 | OPRND_SHIFT_0_BIT), | |
9703 | (4_7or21_24, | |
9704 | IMM_FLDST, | |
9705 | OPRND_SHIFT_2_BIT))), | |
9706 | CSKY_ISA_FLOAT_7E60), | |
9707 | OP32_WITH_WORK ("fst.64", | |
9708 | SOPCODE_INFO2 (0xf4002500, | |
9709 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9710 | BRACKET_OPRND ((16_20, | |
9711 | AREG, | |
9712 | OPRND_SHIFT_0_BIT), | |
9713 | (4_7or21_24, | |
9714 | IMM_FLDST, | |
9715 | OPRND_SHIFT_2_BIT))), | |
9716 | CSKY_ISA_FLOAT_7E60, | |
9717 | float_work_fpuv3_fstore), | |
9718 | OP32_WITH_WORK ("fstd", | |
9719 | SOPCODE_INFO2 (0xf4002500, | |
9720 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
9721 | BRACKET_OPRND ((16_20, | |
9722 | AREG, | |
9723 | OPRND_SHIFT_0_BIT), | |
9724 | (4_7or21_24, | |
9725 | IMM_FLDST, | |
9726 | OPRND_SHIFT_2_BIT))), | |
9727 | CSKY_ISA_FLOAT_7E60, | |
9728 | float_work_fpuv3_fstore), | |
9729 | OP32 ("fldr.64", | |
9730 | SOPCODE_INFO2 (0xf4002900, | |
9731 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9732 | BRACKET_OPRND ((16_20, | |
9733 | AREG, | |
9734 | OPRND_SHIFT_0_BIT), | |
9735 | (5_6or21_25, | |
9736 | AREG_WITH_LSHIFT_FPU, | |
9737 | OPRND_SHIFT_0_BIT))), | |
9738 | CSKY_ISA_FLOAT_7E60), | |
9739 | OP32 ("fldrd", | |
9740 | SOPCODE_INFO2 (0xf4002900, | |
9741 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9742 | BRACKET_OPRND ((16_20, | |
9743 | AREG, | |
9744 | OPRND_SHIFT_0_BIT), | |
9745 | (5_6or21_25, | |
9746 | AREG_WITH_LSHIFT_FPU, | |
9747 | OPRND_SHIFT_0_BIT))), | |
9748 | CSKY_ISA_FLOAT_7E60), | |
9749 | OP32_WITH_WORK ("fstr.64", | |
9750 | SOPCODE_INFO2 (0xf4002d00, | |
9751 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9752 | BRACKET_OPRND ((16_20, | |
9753 | AREG, | |
9754 | OPRND_SHIFT_0_BIT), | |
9755 | (5_6or21_25, | |
9756 | AREG_WITH_LSHIFT_FPU, | |
9757 | OPRND_SHIFT_0_BIT))), | |
9758 | CSKY_ISA_FLOAT_7E60, | |
9759 | float_work_fpuv3_fstore), | |
9760 | OP32_WITH_WORK ("fstrd", | |
9761 | SOPCODE_INFO2 (0xf4002d00, | |
9762 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9763 | BRACKET_OPRND ((16_20, | |
9764 | AREG, | |
9765 | OPRND_SHIFT_0_BIT), | |
9766 | (5_6or21_25, | |
9767 | AREG_WITH_LSHIFT_FPU, | |
9768 | OPRND_SHIFT_0_BIT))), | |
9769 | CSKY_ISA_FLOAT_7E60, | |
9770 | float_work_fpuv3_fstore), | |
9771 | OP32 ("fldm.64", | |
9772 | OPCODE_INFO2 (0xf4003100, | |
9773 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9774 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9775 | CSKY_ISA_FLOAT_7E60), | |
9776 | OP32 ("fldmd", | |
9777 | OPCODE_INFO2 (0xf4003100, | |
9778 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9779 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9780 | CSKY_ISA_FLOAT_7E60), | |
9781 | OP32_WITH_WORK ("fstm.64", | |
9782 | OPCODE_INFO2 (0xf4003500, | |
9783 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9784 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9785 | CSKY_ISA_FLOAT_7E60, | |
9786 | float_work_fpuv3_fstore), | |
9787 | OP32_WITH_WORK ("fstmd", | |
9788 | OPCODE_INFO2 (0xf4003500, | |
9789 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9790 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9791 | CSKY_ISA_FLOAT_7E60, | |
9792 | float_work_fpuv3_fstore), | |
9793 | OP32 ("fldmu.64", | |
9794 | OPCODE_INFO2 (0xf4003180, | |
9795 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9796 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9797 | CSKY_ISA_FLOAT_7E60), | |
9798 | OP32 ("fldmu.d", | |
9799 | OPCODE_INFO2 (0xf4003180, | |
9800 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9801 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9802 | CSKY_ISA_FLOAT_7E60), | |
9803 | OP32_WITH_WORK ("fstmu.64", | |
9804 | OPCODE_INFO2 (0xf4003580, | |
9805 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9806 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9807 | CSKY_ISA_FLOAT_7E60, | |
9808 | float_work_fpuv3_fstore), | |
9809 | OP32_WITH_WORK ("fstmu.d", | |
9810 | OPCODE_INFO2 (0xf4003580, | |
9811 | OPRND_SHIFT0 (0_4or21_25, FREGLIST_DASH), | |
9812 | OPRND_SHIFT0 (16_20, AREG_WITH_BRACKET)), | |
9813 | CSKY_ISA_FLOAT_7E60, | |
9814 | float_work_fpuv3_fstore), | |
9815 | OP32 ("fldrm", | |
9816 | SOPCODE_INFO2 (0xf4002a00, | |
9817 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9818 | BRACKET_OPRND ((16_20, | |
9819 | AREG, | |
9820 | OPRND_SHIFT_0_BIT), | |
9821 | (5_6or21_25, | |
9822 | AREG_WITH_LSHIFT_FPU, | |
9823 | OPRND_SHIFT_0_BIT))), | |
9824 | CSKY_ISA_FLOAT_7E60), | |
9825 | OP32_WITH_WORK ("fstrm", | |
9826 | SOPCODE_INFO2 (0xf4002e00, | |
9827 | (0_4, FREG, OPRND_SHIFT_0_BIT), | |
9828 | BRACKET_OPRND ((16_20, | |
9829 | AREG, | |
9830 | OPRND_SHIFT_0_BIT), | |
9831 | (5_6or21_25, | |
9832 | AREG_WITH_LSHIFT_FPU, | |
9833 | OPRND_SHIFT_0_BIT))), | |
9834 | CSKY_ISA_FLOAT_7E60, | |
9835 | float_work_fpuv3_fstore), | |
9836 | OP32 ("fldmm", | |
9837 | OPCODE_INFO2 (0xf4003200, | |
9838 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
9839 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
9840 | CSKY_ISA_FLOAT_7E60), | |
9841 | OP32_WITH_WORK ("fstmm", | |
9842 | OPCODE_INFO2 (0xf4003600, | |
9843 | (0_4or21_24, FREGLIST_DASH, OPRND_SHIFT_0_BIT), | |
9844 | (16_20, AREG_WITH_BRACKET,OPRND_SHIFT_0_BIT)), | |
9845 | CSKY_ISA_FLOAT_7E60, | |
9846 | float_work_fpuv3_fstore), | |
9847 | OP32 ("fftox.f16.u16", | |
9848 | OPCODE_INFO2 (0xf4004000, | |
9849 | OPRND_SHIFT0 (0_4, FREG), | |
9850 | OPRND_SHIFT0 (16_20, FREG)), | |
9851 | CSKY_ISA_FLOAT_7E60), | |
9852 | OP32 ("fftox.f16.s16", | |
9853 | OPCODE_INFO2 (0xf4004020, | |
9854 | OPRND_SHIFT0 (0_4, FREG), | |
9855 | OPRND_SHIFT0 (16_20, FREG)), | |
9856 | CSKY_ISA_FLOAT_7E60), | |
9857 | OP32 ("fftox.f16.u32", | |
9858 | OPCODE_INFO2 (0xf4004100, | |
9859 | OPRND_SHIFT0 (0_4, FREG), | |
9860 | OPRND_SHIFT0 (16_20, FREG)), | |
9861 | CSKY_ISA_FLOAT_7E60), | |
9862 | OP32 ("fftox.f16.s32", | |
9863 | OPCODE_INFO2 (0xf4004120, | |
9864 | OPRND_SHIFT0 (0_4, FREG), | |
9865 | OPRND_SHIFT0 (16_20, FREG)), | |
9866 | CSKY_ISA_FLOAT_7E60), | |
9867 | OP32 ("fftox.f32.u32", | |
9868 | OPCODE_INFO2 (0xf4004140, | |
9869 | OPRND_SHIFT0 (0_4, FREG), | |
9870 | OPRND_SHIFT0 (16_20, FREG)), | |
9871 | CSKY_ISA_FLOAT_7E60), | |
9872 | OP32 ("fftox.f32.s32", | |
9873 | OPCODE_INFO2 (0xf4004160, | |
9874 | OPRND_SHIFT0 (0_4, FREG), | |
9875 | OPRND_SHIFT0 (16_20, FREG)), | |
9876 | CSKY_ISA_FLOAT_7E60), | |
9877 | OP32 ("fftox.f64.u32", | |
9878 | OPCODE_INFO2 (0xf4004180, | |
9879 | OPRND_SHIFT0 (0_4, FREG), | |
9880 | OPRND_SHIFT0 (16_20, FREG)), | |
9881 | CSKY_ISA_FLOAT_7E60), | |
9882 | OP32 ("fftox.f64.s32", | |
9883 | OPCODE_INFO2 (0xf40041a0, | |
9884 | OPRND_SHIFT0 (0_4, FREG), | |
9885 | OPRND_SHIFT0 (16_20, FREG)), | |
9886 | CSKY_ISA_FLOAT_7E60), | |
9887 | OP32 ("fxtof.u16.f16", | |
9888 | OPCODE_INFO2 (0xf4004800, | |
9889 | OPRND_SHIFT0 (0_4, FREG), | |
9890 | OPRND_SHIFT0 (16_20, FREG)), | |
9891 | CSKY_ISA_FLOAT_7E60), | |
9892 | OP32 ("fxtof.s16.f16", | |
9893 | OPCODE_INFO2 (0xf4004820, | |
9894 | OPRND_SHIFT0 (0_4, FREG), | |
9895 | OPRND_SHIFT0 (16_20, FREG)), | |
9896 | CSKY_ISA_FLOAT_7E60), | |
9897 | OP32 ("fxtof.u32.f16", | |
9898 | OPCODE_INFO2 (0xf4004900, | |
9899 | OPRND_SHIFT0 (0_4, FREG), | |
9900 | OPRND_SHIFT0 (16_20, FREG)), | |
9901 | CSKY_ISA_FLOAT_7E60), | |
9902 | OP32 ("fxtof.s32.f16", | |
9903 | OPCODE_INFO2 (0xf4004920, | |
9904 | OPRND_SHIFT0 (0_4, FREG), | |
9905 | OPRND_SHIFT0 (16_20, FREG)), | |
9906 | CSKY_ISA_FLOAT_7E60), | |
9907 | OP32 ("fxtof.u32.f32", | |
9908 | OPCODE_INFO2 (0xf4004940, | |
9909 | OPRND_SHIFT0 (0_4, FREG), | |
9910 | OPRND_SHIFT0 (16_20, FREG)), | |
9911 | CSKY_ISA_FLOAT_7E60), | |
9912 | OP32 ("fxtof.s32.f32", | |
9913 | OPCODE_INFO2 (0xf4004960, | |
9914 | OPRND_SHIFT0 (0_4, FREG), | |
9915 | OPRND_SHIFT0 (16_20, FREG)), | |
9916 | CSKY_ISA_FLOAT_7E60), | |
9917 | OP32 ("fxtof.u32.f64", | |
9918 | OPCODE_INFO2 (0xf4004980, | |
9919 | OPRND_SHIFT0 (0_4, FREG), | |
9920 | OPRND_SHIFT0 (16_20, FREG)), | |
9921 | CSKY_ISA_FLOAT_7E60), | |
9922 | OP32 ("fxtof.s32.f64", | |
9923 | OPCODE_INFO2 (0xf40049a0, | |
9924 | OPRND_SHIFT0 (0_4, FREG), | |
9925 | OPRND_SHIFT0 (16_20, FREG)), | |
9926 | CSKY_ISA_FLOAT_7E60), | |
9927 | OP32 ("fftoi.f16.s16", | |
9928 | OPCODE_INFO2 (0xf4004220, | |
9929 | OPRND_SHIFT0 (0_4, FREG), | |
9930 | OPRND_SHIFT0 (16_20, FREG)), | |
9931 | CSKY_ISA_FLOAT_7E60), | |
9932 | OP32 ("fftoi.f16.u16", | |
9933 | OPCODE_INFO2 (0xf4004200, | |
9934 | OPRND_SHIFT0 (0_4, FREG), | |
9935 | OPRND_SHIFT0 (16_20, FREG)), | |
9936 | CSKY_ISA_FLOAT_7E60), | |
9937 | OP32 ("fftoi.f16.s32", | |
9938 | OPCODE_INFO2 (0xf4004320, | |
9939 | OPRND_SHIFT0 (0_4, FREG), | |
9940 | OPRND_SHIFT0 (16_20, FREG)), | |
9941 | CSKY_ISA_FLOAT_7E60), | |
9942 | OP32 ("fftoi.f16.u32", | |
9943 | OPCODE_INFO2 (0xf4004300, | |
9944 | OPRND_SHIFT0 (0_4, FREG), | |
9945 | OPRND_SHIFT0 (16_20, FREG)), | |
9946 | CSKY_ISA_FLOAT_7E60), | |
9947 | OP32 ("fftoi.f32.s32", | |
9948 | OPCODE_INFO2 (0xf4004360, | |
9949 | OPRND_SHIFT0 (0_4, FREG), | |
9950 | OPRND_SHIFT0 (16_20, FREG)), | |
9951 | CSKY_ISA_FLOAT_7E60), | |
9952 | OP32 ("fftoi.f32.u32", | |
9953 | OPCODE_INFO2 (0xf4004340, | |
9954 | OPRND_SHIFT0 (0_4, FREG), | |
9955 | OPRND_SHIFT0 (16_20, FREG)), | |
9956 | CSKY_ISA_FLOAT_7E60), | |
9957 | OP32 ("fftoi.f64.s32", | |
9958 | OPCODE_INFO2 (0xf40043a0, | |
9959 | OPRND_SHIFT0 (0_4, FREG), | |
9960 | OPRND_SHIFT0 (16_20, FREG)), | |
9961 | CSKY_ISA_FLOAT_7E60), | |
9962 | OP32 ("fftoi.f64.u32", | |
9963 | OPCODE_INFO2 (0xf4004380, | |
9964 | OPRND_SHIFT0 (0_4, FREG), | |
9965 | OPRND_SHIFT0 (16_20, FREG)), | |
9966 | CSKY_ISA_FLOAT_7E60), | |
9967 | OP32 ("fitof.s16.f16", | |
9968 | OPCODE_INFO2 (0xf4004a20, | |
9969 | OPRND_SHIFT0 (0_4, FREG), | |
9970 | OPRND_SHIFT0 (16_20, FREG)), | |
9971 | CSKY_ISA_FLOAT_7E60), | |
9972 | OP32 ("fitof.u16.f16", | |
9973 | OPCODE_INFO2 (0xf4004a00, | |
9974 | OPRND_SHIFT0 (0_4, FREG), | |
9975 | OPRND_SHIFT0 (16_20, FREG)), | |
9976 | CSKY_ISA_FLOAT_7E60), | |
9977 | OP32 ("fitof.s32.f16", | |
9978 | OPCODE_INFO2 (0xf4004b20, | |
9979 | OPRND_SHIFT0 (0_4, FREG), | |
9980 | OPRND_SHIFT0 (16_20, FREG)), | |
9981 | CSKY_ISA_FLOAT_7E60), | |
9982 | OP32 ("fitof.u32.f16", | |
9983 | OPCODE_INFO2 (0xf4004b00, | |
9984 | OPRND_SHIFT0 (0_4, FREG), | |
9985 | OPRND_SHIFT0 (16_20, FREG)), | |
9986 | CSKY_ISA_FLOAT_7E60), | |
9987 | OP32 ("fitof.s32.f32", | |
9988 | OPCODE_INFO2 (0xf4004b60, | |
9989 | OPRND_SHIFT0 (0_4, FREG), | |
9990 | OPRND_SHIFT0 (16_20, FREG)), | |
9991 | CSKY_ISA_FLOAT_7E60), | |
9992 | OP32 ("fsitos", | |
9993 | OPCODE_INFO2 (0xf4004b60, | |
9994 | OPRND_SHIFT0 (0_4, FREG), | |
9995 | OPRND_SHIFT0 (16_20, FREG)), | |
9996 | CSKY_ISA_FLOAT_7E60), | |
9997 | OP32 ("fitof.u32.f32", | |
9998 | OPCODE_INFO2 (0xf4004b40, | |
9999 | OPRND_SHIFT0 (0_4, FREG), | |
10000 | OPRND_SHIFT0 (16_20, FREG)), | |
10001 | CSKY_ISA_FLOAT_7E60), | |
10002 | OP32 ("fuitos", | |
10003 | OPCODE_INFO2 (0xf4004b40, | |
10004 | OPRND_SHIFT0 (0_4, FREG), | |
10005 | OPRND_SHIFT0 (16_20, FREG)), | |
10006 | CSKY_ISA_FLOAT_7E60), | |
10007 | OP32 ("fitof.s32.f64", | |
10008 | OPCODE_INFO2 (0xf4004ba0, | |
10009 | OPRND_SHIFT0 (0_4, FREG), | |
10010 | OPRND_SHIFT0 (16_20, FREG)), | |
10011 | CSKY_ISA_FLOAT_7E60), | |
10012 | OP32 ("fsitod", | |
10013 | OPCODE_INFO2 (0xf4004ba0, | |
10014 | OPRND_SHIFT0 (0_4, FREG), | |
10015 | OPRND_SHIFT0 (16_20, FREG)), | |
10016 | CSKY_ISA_FLOAT_7E60), | |
10017 | OP32 ("fitof.u32.f64", | |
10018 | OPCODE_INFO2 (0xf4004b80, | |
10019 | OPRND_SHIFT0 (0_4, FREG), | |
10020 | OPRND_SHIFT0 (16_20, FREG)), | |
10021 | CSKY_ISA_FLOAT_7E60), | |
10022 | OP32 ("fuitod", | |
10023 | OPCODE_INFO2 (0xf4004b80, | |
10024 | OPRND_SHIFT0 (0_4, FREG), | |
10025 | OPRND_SHIFT0 (16_20, FREG)), | |
10026 | CSKY_ISA_FLOAT_7E60), | |
10027 | OP32 ("fftofi.f16.rn", | |
10028 | OPCODE_INFO2 (0xf4004400, | |
10029 | OPRND_SHIFT0 (0_4, FREG), | |
10030 | OPRND_SHIFT0 (16_20, FREG)), | |
10031 | CSKY_ISA_FLOAT_7E60), | |
10032 | OP32 ("fftofi.f16.rz", | |
10033 | OPCODE_INFO2 (0xf4004420, | |
10034 | OPRND_SHIFT0 (0_4, FREG), | |
10035 | OPRND_SHIFT0 (16_20, FREG)), | |
10036 | CSKY_ISA_FLOAT_7E60), | |
10037 | OP32 ("fftofi.f16.rpi", | |
10038 | OPCODE_INFO2 (0xf4004440, | |
10039 | OPRND_SHIFT0 (0_4, FREG), | |
10040 | OPRND_SHIFT0 (16_20, FREG)), | |
10041 | CSKY_ISA_FLOAT_7E60), | |
10042 | OP32 ("fftofi.f16.rni", | |
10043 | OPCODE_INFO2 (0xf4004460, | |
10044 | OPRND_SHIFT0 (0_4, FREG), | |
10045 | OPRND_SHIFT0 (16_20, FREG)), | |
10046 | CSKY_ISA_FLOAT_7E60), | |
10047 | OP32 ("fftofi.f32.rn", | |
10048 | OPCODE_INFO2 (0xf4004480, | |
10049 | OPRND_SHIFT0 (0_4, FREG), | |
10050 | OPRND_SHIFT0 (16_20, FREG)), | |
10051 | CSKY_ISA_FLOAT_7E60), | |
10052 | OP32 ("fftofi.f32.rz", | |
10053 | OPCODE_INFO2 (0xf40044a0, | |
10054 | OPRND_SHIFT0 (0_4, FREG), | |
10055 | OPRND_SHIFT0 (16_20, FREG)), | |
10056 | CSKY_ISA_FLOAT_7E60), | |
10057 | OP32 ("fftofi.f32.rpi", | |
10058 | OPCODE_INFO2 (0xf40044c0, | |
10059 | OPRND_SHIFT0 (0_4, FREG), | |
10060 | OPRND_SHIFT0 (16_20, FREG)), | |
10061 | CSKY_ISA_FLOAT_7E60), | |
10062 | OP32 ("fftofi.f32.rni", | |
10063 | OPCODE_INFO2 (0xf40044e0, | |
10064 | OPRND_SHIFT0 (0_4, FREG), | |
10065 | OPRND_SHIFT0 (16_20, FREG)), | |
10066 | CSKY_ISA_FLOAT_7E60), | |
10067 | OP32 ("fftofi.f64.rn", | |
10068 | OPCODE_INFO2 (0xf4004500, | |
10069 | OPRND_SHIFT0 (0_4, FREG), | |
10070 | OPRND_SHIFT0 (16_20, FREG)), | |
10071 | CSKY_ISA_FLOAT_7E60), | |
10072 | OP32 ("fftofi.f64.rz", | |
10073 | OPCODE_INFO2 (0xf4004520, | |
10074 | OPRND_SHIFT0 (0_4, FREG), | |
10075 | OPRND_SHIFT0 (16_20, FREG)), | |
10076 | CSKY_ISA_FLOAT_7E60), | |
10077 | OP32 ("fftofi.f64.rpi", | |
10078 | OPCODE_INFO2 (0xf4004540, | |
10079 | OPRND_SHIFT0 (0_4, FREG), | |
10080 | OPRND_SHIFT0 (16_20, FREG)), | |
10081 | CSKY_ISA_FLOAT_7E60), | |
10082 | OP32 ("fftofi.f64.rni", | |
10083 | OPCODE_INFO2 (0xf4004560, | |
10084 | OPRND_SHIFT0 (0_4, FREG), | |
10085 | OPRND_SHIFT0 (16_20, FREG)), | |
10086 | CSKY_ISA_FLOAT_7E60), | |
10087 | DOP32_WITH_WORK ("fmovi.16", | |
10088 | OPCODE_INFO2 (0xf400e400, | |
10089 | OPRND_SHIFT0 (0_4, FREG), | |
10090 | OPRND_SHIFT0 (5or8_9or16_25, HFLOAT_FMOVI)), | |
10091 | OPCODE_INFO3 (0xf400e400, | |
10092 | OPRND_SHIFT0 (0_4, FREG), | |
10093 | OPRND_SHIFT0 (5or8_9or20_25, IMM9b), | |
10094 | OPRND_SHIFT0 (16_19, IMM4b)), | |
10095 | CSKY_ISA_FLOAT_7E60, | |
10096 | float_work_fpuv3_fmovi), | |
10097 | DOP32_WITH_WORK ("fmovi.32", | |
10098 | OPCODE_INFO2 (0xf400e440, | |
10099 | OPRND_SHIFT0 (0_4, FREG), | |
10100 | OPRND_SHIFT0 (5or8_9or16_25, SFLOAT_FMOVI)), | |
10101 | OPCODE_INFO3 (0xf400e440, | |
10102 | OPRND_SHIFT0 (0_4, FREG), | |
10103 | OPRND_SHIFT0 (5or8_9or20_25, IMM9b), | |
10104 | OPRND_SHIFT0 (16_19, IMM4b)), | |
10105 | CSKY_ISA_FLOAT_7E60, | |
10106 | float_work_fpuv3_fmovi), | |
10107 | DOP32_WITH_WORK ("fmovi.64", | |
10108 | OPCODE_INFO2 (0xf400e480, | |
10109 | OPRND_SHIFT0 (0_4, FREG), | |
10110 | OPRND_SHIFT0 (5or8_9or16_25, DFLOAT_FMOVI)), | |
10111 | OPCODE_INFO3 (0xf400e480, | |
10112 | OPRND_SHIFT0 (0_4, FREG), | |
10113 | OPRND_SHIFT0 (5or8_9or20_25, IMM9b), | |
10114 | OPRND_SHIFT0 (16_19, IMM4b)), | |
10115 | CSKY_ISA_FLOAT_7E60, | |
10116 | float_work_fpuv3_fmovi), | |
10117 | #undef _RELOC32 | |
10118 | #define _RELOC32 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4 | |
10119 | OP32 ("flrw.32", | |
10120 | OPCODE_INFO2 (0xf4003800, | |
10121 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
10122 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
10123 | CSKY_ISA_FLOAT_7E60), | |
10124 | OP32 ("flrws", | |
10125 | OPCODE_INFO2 (0xf4003800, | |
10126 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
10127 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
10128 | CSKY_ISA_FLOAT_7E60), | |
10129 | OP32 ("flrw.64", | |
10130 | OPCODE_INFO2 (0xf4003900, | |
10131 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
10132 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
10133 | CSKY_ISA_FLOAT_7E60), | |
10134 | OP32 ("flrwd", | |
10135 | OPCODE_INFO2 (0xf4003900, | |
10136 | (0_3or25, FREG, OPRND_SHIFT_0_BIT), | |
10137 | (4_7or21_24, FCONSTANT, OPRND_SHIFT_2_BIT)), | |
10138 | CSKY_ISA_FLOAT_7E60), | |
10139 | #undef _RELOC32 | |
10140 | #define _RELOC32 0 | |
10141 | ||
b8891f8d AJ |
10142 | /* The following are aliases for other instructions. */ |
10143 | /* setc -> cmphs r0, r0 */ | |
10144 | OP16 ("setc", | |
10145 | OPCODE_INFO0 (0x6400), | |
10146 | CSKYV2_ISA_E1), | |
10147 | /* clrc -> cmpne r0, r0 */ | |
10148 | OP16 ("clrc", | |
10149 | OPCODE_INFO0 (0x6402), | |
10150 | CSKYV2_ISA_E1), | |
10151 | /* tstlt rd -> btsti rd,31 */ | |
10152 | OP32 ("tstlt", | |
10153 | OPCODE_INFO1 (0xc7e02880, | |
10154 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10155 | CSKYV2_ISA_1E2), | |
10156 | /* idly4 -> idly 4 */ | |
10157 | OP32 ("idly4", | |
10158 | OPCODE_INFO0 (0xc0601c20), | |
10159 | CSKYV2_ISA_E1), | |
10160 | /* rsub rz, ry, rx -> subu rz, rx, ry */ | |
10161 | DOP32 ("rsub", | |
10162 | OPCODE_INFO3 (0xc4000080, | |
10163 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10164 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
10165 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10166 | OPCODE_INFO2 (0xc4000080, | |
10167 | (0_4or21_25, DUP_AREG, OPRND_SHIFT_0_BIT), | |
10168 | (16_20, AREG, OPRND_SHIFT_0_BIT)), CSKYV2_ISA_1E2), | |
10169 | /* cmplei rd,X -> cmplti rd,X+1 */ | |
10170 | OP16_OP32 ("cmplei", | |
10171 | OPCODE_INFO2 (0x3820, | |
10172 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT), | |
10173 | (0_4, IMM5b, OPRND_SHIFT_0_BIT)), | |
10174 | CSKYV2_ISA_E1, | |
10175 | OPCODE_INFO2 (0xeb200000, | |
10176 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
10177 | (0_15, IMM16b, OPRND_SHIFT_0_BIT)), | |
10178 | CSKYV2_ISA_1E2), | |
10179 | /* cmpls -> cmphs */ | |
10180 | OP16_OP32 ("cmpls", | |
10181 | OPCODE_INFO2 (0x6400, | |
10182 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
10183 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
10184 | CSKYV2_ISA_E1, | |
10185 | OPCODE_INFO2 (0xc4000420, | |
10186 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
10187 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10188 | CSKYV2_ISA_2E3), | |
10189 | /* cmpgt -> cmplt */ | |
10190 | OP16_OP32 ("cmpgt", | |
10191 | OPCODE_INFO2 (0x6401, | |
10192 | (6_9, GREG0_15, OPRND_SHIFT_0_BIT), | |
10193 | (2_5, GREG0_15, OPRND_SHIFT_0_BIT)), | |
10194 | CSKYV2_ISA_E1, | |
10195 | OPCODE_INFO2 (0xc4000440, | |
10196 | (21_25, AREG, OPRND_SHIFT_0_BIT), | |
10197 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10198 | CSKYV2_ISA_2E3), | |
10199 | /* tstle rd -> cmplti rd,1 */ | |
10200 | OP16_OP32 ("tstle", | |
10201 | OPCODE_INFO1 (0x3820, | |
10202 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), | |
10203 | CSKYV2_ISA_E1, | |
10204 | OPCODE_INFO1 (0xeb200000, | |
10205 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10206 | CSKYV2_ISA_1E2), | |
10207 | /* tstne rd -> cmpnei rd,0 */ | |
10208 | OP16_OP32 ("tstne", | |
10209 | OPCODE_INFO1 (0x3840, | |
10210 | (8_10, GREG0_7, OPRND_SHIFT_0_BIT)), | |
10211 | CSKYV2_ISA_E1, | |
10212 | OPCODE_INFO1 (0xeb400000, | |
10213 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10214 | CSKYV2_ISA_1E2), | |
10215 | /* rotri rz, rx, imm5 -> rotli rz, rx, 32-imm5 */ | |
10216 | DOP32 ("rotri", | |
10217 | OPCODE_INFO3 (0xc4004900, | |
10218 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10219 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
10220 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
10221 | OPCODE_INFO2 (0xc4004900, | |
10222 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
10223 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
10224 | CSKYV2_ISA_2E3), | |
10225 | DOP32 ("rori", | |
10226 | OPCODE_INFO3 (0xc4004900, | |
10227 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10228 | (16_20, AREG, OPRND_SHIFT_0_BIT), | |
10229 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
10230 | OPCODE_INFO2 (0xc4004900, | |
10231 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT), | |
10232 | (21_25, IMM5b_RORI, OPRND_SHIFT_0_BIT)), | |
10233 | CSKYV2_ISA_2E3), | |
10234 | ||
10235 | /* rotlc rd -> addc rd, rd/ addc rd, rd, rd */ | |
10236 | OP16_OP32_WITH_WORK ("rotlc", | |
10237 | OPCODE_INFO2 (0x6001, | |
10238 | (NONE, GREG0_15, OPRND_SHIFT_0_BIT), | |
10239 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
10240 | CSKYV2_ISA_E1, | |
10241 | OPCODE_INFO2 (0xc4000040, | |
10242 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
10243 | (NONE, CONST1, OPRND_SHIFT_0_BIT)), | |
10244 | CSKYV2_ISA_2E3, | |
10245 | v2_work_rotlc), | |
10246 | /* not rd -> nor rd, rd, not rz, rx -> nor rz, rx, rx */ | |
10247 | OP16_OP32_WITH_WORK ("not", | |
10248 | OPCODE_INFO1 (0x6c02, | |
10249 | (NONE, AREG, OPRND_SHIFT_0_BIT)), | |
10250 | CSKYV2_ISA_E1, | |
10251 | OPCODE_INFO2 (0xc4002480, | |
10252 | (NONE, AREG, OPRND_SHIFT_0_BIT), | |
10253 | (NONE, AREG, OPRND_SHIFT_0_BIT)), | |
10254 | CSKYV2_ISA_E1, v2_work_not), | |
10255 | ||
10256 | /* Special force 32 bits instruction. */ | |
10257 | OP32 ("xtrb0.32", | |
10258 | OPCODE_INFO2 (0xc4007020, | |
10259 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10260 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10261 | CSKYV2_ISA_1E2), | |
10262 | OP32 ("xtrb1.32", | |
10263 | OPCODE_INFO2 (0xc4007040, | |
10264 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10265 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10266 | CSKYV2_ISA_1E2), | |
10267 | OP32 ("xtrb2.32", | |
10268 | OPCODE_INFO2 (0xc4007080, | |
10269 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10270 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10271 | CSKYV2_ISA_1E2), | |
10272 | OP32 ("xtrb3.32", | |
10273 | OPCODE_INFO2 (0xc4007100, | |
10274 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10275 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10276 | CSKYV2_ISA_1E2), | |
10277 | OP32 ("ff0.32", | |
10278 | OPCODE_INFO2 (0xc4007c20, | |
10279 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10280 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10281 | CSKYV2_ISA_1E2), | |
10282 | DOP32 ("ff1.32", | |
10283 | OPCODE_INFO2 (0xc4007c40, | |
10284 | (0_4, AREG, OPRND_SHIFT_0_BIT), | |
10285 | (16_20, AREG, OPRND_SHIFT_0_BIT)), | |
10286 | OPCODE_INFO1 (0xc4007c40, | |
10287 | (0_4or16_20, DUP_AREG, OPRND_SHIFT_0_BIT)), | |
10288 | CSKYV2_ISA_1E2), | |
1feede9b | 10289 | |
f24ff6e9 | 10290 | {NULL, 0, {}, {}, 0, 0, 0, 0, 0, NULL} |
b8891f8d | 10291 | }; |