]>
Commit | Line | Data |
---|---|---|
252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 | 89 | static void OP_VEX (int, int); |
41f5efc6 | 90 | static void OP_VexR (int, int); |
e6123d0c | 91 | static void OP_VexW (int, int); |
43234a1e | 92 | static void OP_Rounding (int, int); |
c0f3af97 | 93 | static void OP_REG_VexI4 (int, int); |
93abb146 | 94 | static void OP_VexI4 (int, int); |
c0f3af97 | 95 | static void PCLMUL_Fixup (int, int); |
43234a1e | 96 | static void VPCMP_Fixup (int, int); |
be92cb14 | 97 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 98 | static void OP_0f07 (int, int); |
b844680a L |
99 | static void OP_Monitor (int, int); |
100 | static void OP_Mwait (int, int); | |
46e883c5 L |
101 | static void NOP_Fixup1 (int, int); |
102 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 103 | static void OP_3DNowSuffix (int, int); |
ad19981d | 104 | static void CMP_Fixup (int, int); |
26ca5450 | 105 | static void BadOp (void); |
35c52694 | 106 | static void REP_Fixup (int, int); |
d835a58b | 107 | static void SEP_Fixup (int, int); |
7e8b059b | 108 | static void BND_Fixup (int, int); |
04ef582a | 109 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
110 | static void HLE_Fixup1 (int, int); |
111 | static void HLE_Fixup2 (int, int); | |
112 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 113 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 114 | static void XMM_Fixup (int, int); |
eacc9c89 | 115 | static void FXSAVE_Fixup (int, int); |
c1e679ec | 116 | |
bc31405e | 117 | static void MOVSXD_Fixup (int, int); |
252b5132 | 118 | |
43234a1e L |
119 | static void OP_Mask (int, int); |
120 | ||
6608db57 | 121 | struct dis_private { |
252b5132 RH |
122 | /* Points to first byte not fetched. */ |
123 | bfd_byte *max_fetched; | |
0b1cf022 | 124 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 125 | bfd_vma insn_start; |
e396998b | 126 | int orig_sizeflag; |
8df14d78 | 127 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
128 | }; |
129 | ||
cb712a9e L |
130 | enum address_mode |
131 | { | |
132 | mode_16bit, | |
133 | mode_32bit, | |
134 | mode_64bit | |
135 | }; | |
136 | ||
137 | enum address_mode address_mode; | |
52b15da3 | 138 | |
5076851f ILT |
139 | /* Flags for the prefixes for the current instruction. See below. */ |
140 | static int prefixes; | |
141 | ||
52b15da3 JH |
142 | /* REX prefix the current instruction. See below. */ |
143 | static int rex; | |
144 | /* Bits of REX we've already used. */ | |
145 | static int rex_used; | |
52b15da3 JH |
146 | /* Mark parts used in the REX prefix. When we are testing for |
147 | empty prefix (for 8bit register REX extension), just mask it | |
148 | out. Otherwise test for REX bit is excuse for existence of REX | |
149 | only in case value is nonzero. */ | |
150 | #define USED_REX(value) \ | |
151 | { \ | |
152 | if (value) \ | |
161a04f6 L |
153 | { \ |
154 | if ((rex & value)) \ | |
155 | rex_used |= (value) | REX_OPCODE; \ | |
156 | } \ | |
52b15da3 | 157 | else \ |
161a04f6 | 158 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
159 | } |
160 | ||
7d421014 ILT |
161 | /* Flags for prefixes which we somehow handled when printing the |
162 | current instruction. */ | |
163 | static int used_prefixes; | |
164 | ||
5076851f ILT |
165 | /* Flags stored in PREFIXES. */ |
166 | #define PREFIX_REPZ 1 | |
167 | #define PREFIX_REPNZ 2 | |
168 | #define PREFIX_LOCK 4 | |
169 | #define PREFIX_CS 8 | |
170 | #define PREFIX_SS 0x10 | |
171 | #define PREFIX_DS 0x20 | |
172 | #define PREFIX_ES 0x40 | |
173 | #define PREFIX_FS 0x80 | |
174 | #define PREFIX_GS 0x100 | |
175 | #define PREFIX_DATA 0x200 | |
176 | #define PREFIX_ADDR 0x400 | |
177 | #define PREFIX_FWAIT 0x800 | |
178 | ||
252b5132 RH |
179 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
180 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
181 | on error. */ | |
182 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 183 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
184 | ? 1 : fetch_data ((info), (addr))) |
185 | ||
186 | static int | |
26ca5450 | 187 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
188 | { |
189 | int status; | |
6608db57 | 190 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
191 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
192 | ||
0b1cf022 | 193 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
194 | status = (*info->read_memory_func) (start, |
195 | priv->max_fetched, | |
196 | addr - priv->max_fetched, | |
197 | info); | |
198 | else | |
199 | status = -1; | |
252b5132 RH |
200 | if (status != 0) |
201 | { | |
7d421014 | 202 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
203 | print_insn_i386 will do something sensible. Otherwise, print |
204 | an error. We do that here because this is where we know | |
205 | STATUS. */ | |
7d421014 | 206 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 207 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 208 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
209 | } |
210 | else | |
211 | priv->max_fetched = addr; | |
212 | return 1; | |
213 | } | |
214 | ||
bf890a93 | 215 | /* Possible values for prefix requirement. */ |
507bd325 L |
216 | #define PREFIX_IGNORED_SHIFT 16 |
217 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
218 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
219 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
220 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
221 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
222 | ||
223 | /* Opcode prefixes. */ | |
224 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
225 | | PREFIX_REPNZ \ | |
226 | | PREFIX_DATA) | |
227 | ||
228 | /* Prefixes ignored. */ | |
229 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
230 | | PREFIX_IGNORED_REPNZ \ | |
231 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 232 | |
ce518a5f | 233 | #define XX { NULL, 0 } |
507bd325 | 234 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
235 | |
236 | #define Eb { OP_E, b_mode } | |
7e8b059b | 237 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 238 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 239 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 240 | #define Ev { OP_E, v_mode } |
de89d0a3 | 241 | #define Eva { OP_E, va_mode } |
7e8b059b | 242 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 243 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
244 | #define Ed { OP_E, d_mode } |
245 | #define Edq { OP_E, dq_mode } | |
246 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 247 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
248 | #define Edb { OP_E, db_mode } |
249 | #define Edw { OP_E, dw_mode } | |
42903f7f | 250 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 251 | #define Eq { OP_E, q_mode } |
07f5af7d | 252 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
253 | #define indirEp { OP_indirE, f_mode } |
254 | #define stackEv { OP_E, stack_v_mode } | |
255 | #define Em { OP_E, m_mode } | |
256 | #define Ew { OP_E, w_mode } | |
257 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 258 | #define Ma { OP_M, a_mode } |
b844680a | 259 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 260 | #define Md { OP_M, d_mode } |
f1f8f695 | 261 | #define Mo { OP_M, o_mode } |
ce518a5f L |
262 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
263 | #define Mq { OP_M, q_mode } | |
9ab00b61 | 264 | #define Mv { OP_M, v_mode } |
d276ec69 | 265 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 266 | #define Mx { OP_M, x_mode } |
c0f3af97 | 267 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 268 | #define Gb { OP_G, b_mode } |
7e8b059b | 269 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
270 | #define Gv { OP_G, v_mode } |
271 | #define Gd { OP_G, d_mode } | |
272 | #define Gdq { OP_G, dq_mode } | |
273 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 274 | #define Gva { OP_G, va_mode } |
ce518a5f | 275 | #define Gw { OP_G, w_mode } |
ce518a5f L |
276 | #define Ib { OP_I, b_mode } |
277 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 278 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 279 | #define Iv { OP_I, v_mode } |
7bb15c6f | 280 | #define sIv { OP_sI, v_mode } |
ce518a5f | 281 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 282 | #define Id { OP_I, d_mode } |
ce518a5f L |
283 | #define Iw { OP_I, w_mode } |
284 | #define I1 { OP_I, const_1_mode } | |
285 | #define Jb { OP_J, b_mode } | |
286 | #define Jv { OP_J, v_mode } | |
376cd056 | 287 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
288 | #define Cm { OP_C, m_mode } |
289 | #define Dm { OP_D, m_mode } | |
290 | #define Td { OP_T, d_mode } | |
b844680a | 291 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
292 | |
293 | #define RMeAX { OP_REG, eAX_reg } | |
294 | #define RMeBX { OP_REG, eBX_reg } | |
295 | #define RMeCX { OP_REG, eCX_reg } | |
296 | #define RMeDX { OP_REG, eDX_reg } | |
297 | #define RMeSP { OP_REG, eSP_reg } | |
298 | #define RMeBP { OP_REG, eBP_reg } | |
299 | #define RMeSI { OP_REG, eSI_reg } | |
300 | #define RMeDI { OP_REG, eDI_reg } | |
301 | #define RMrAX { OP_REG, rAX_reg } | |
302 | #define RMrBX { OP_REG, rBX_reg } | |
303 | #define RMrCX { OP_REG, rCX_reg } | |
304 | #define RMrDX { OP_REG, rDX_reg } | |
305 | #define RMrSP { OP_REG, rSP_reg } | |
306 | #define RMrBP { OP_REG, rBP_reg } | |
307 | #define RMrSI { OP_REG, rSI_reg } | |
308 | #define RMrDI { OP_REG, rDI_reg } | |
309 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
310 | #define RMCL { OP_REG, cl_reg } |
311 | #define RMDL { OP_REG, dl_reg } | |
312 | #define RMBL { OP_REG, bl_reg } | |
313 | #define RMAH { OP_REG, ah_reg } | |
314 | #define RMCH { OP_REG, ch_reg } | |
315 | #define RMDH { OP_REG, dh_reg } | |
316 | #define RMBH { OP_REG, bh_reg } | |
317 | #define RMAX { OP_REG, ax_reg } | |
318 | #define RMDX { OP_REG, dx_reg } | |
319 | ||
320 | #define eAX { OP_IMREG, eAX_reg } | |
ce518a5f L |
321 | #define AL { OP_IMREG, al_reg } |
322 | #define CL { OP_IMREG, cl_reg } | |
ce518a5f L |
323 | #define zAX { OP_IMREG, z_mode_ax_reg } |
324 | #define indirDX { OP_IMREG, indir_dx_reg } | |
325 | ||
326 | #define Sw { OP_SEG, w_mode } | |
327 | #define Sv { OP_SEG, v_mode } | |
328 | #define Ap { OP_DIR, 0 } | |
329 | #define Ob { OP_OFF64, b_mode } | |
330 | #define Ov { OP_OFF64, v_mode } | |
331 | #define Xb { OP_DSreg, eSI_reg } | |
332 | #define Xv { OP_DSreg, eSI_reg } | |
333 | #define Xz { OP_DSreg, eSI_reg } | |
334 | #define Yb { OP_ESreg, eDI_reg } | |
335 | #define Yv { OP_ESreg, eDI_reg } | |
336 | #define DSBX { OP_DSreg, eBX_reg } | |
337 | ||
338 | #define es { OP_REG, es_reg } | |
339 | #define ss { OP_REG, ss_reg } | |
340 | #define cs { OP_REG, cs_reg } | |
341 | #define ds { OP_REG, ds_reg } | |
342 | #define fs { OP_REG, fs_reg } | |
343 | #define gs { OP_REG, gs_reg } | |
344 | ||
345 | #define MX { OP_MMX, 0 } | |
346 | #define XM { OP_XMM, 0 } | |
539f890d | 347 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 348 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 349 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 350 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 351 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 352 | #define EM { OP_EM, v_mode } |
b6169b20 | 353 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 354 | #define EMd { OP_EM, d_mode } |
14051056 | 355 | #define EMx { OP_EM, x_mode } |
4726e9a4 | 356 | #define EXbwUnit { OP_EX, bw_unit_mode } |
8976381e | 357 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 358 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 359 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 360 | #define EXq { OP_EX, q_mode } |
b6169b20 | 361 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 362 | #define EXx { OP_EX, x_mode } |
b6169b20 | 363 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 364 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 365 | #define EXymm { OP_EX, ymm_mode } |
260cd341 | 366 | #define EXtmm { OP_EX, tmm_mode } |
c0f3af97 | 367 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 368 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
369 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
370 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
371 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
372 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
373 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
374 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 375 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 376 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
377 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
378 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
379 | #define MS { OP_MS, v_mode } |
380 | #define XS { OP_XS, v_mode } | |
09335d05 | 381 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 382 | #define MXC { OP_MXC, 0 } |
ce518a5f | 383 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 384 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 385 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 386 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 387 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 388 | |
c0f3af97 | 389 | #define Vex { OP_VEX, vex_mode } |
e6123d0c | 390 | #define VexW { OP_VexW, vex_mode } |
539f890d | 391 | #define VexScalar { OP_VEX, vex_scalar_mode } |
41f5efc6 | 392 | #define VexScalarR { OP_VexR, vex_scalar_mode } |
6c30d220 | 393 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
cb21baef | 394 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 395 | #define VexTmm { OP_VEX, tmm_mode } |
c0f3af97 | 396 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 397 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 398 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 399 | #define PCLMUL { PCLMUL_Fixup, 0 } |
43234a1e | 400 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 401 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
402 | |
403 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 404 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
405 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
406 | ||
407 | #define XMask { OP_Mask, mask_mode } | |
408 | #define MaskG { OP_G, mask_mode } | |
409 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 410 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e | 411 | #define MaskVex { OP_VEX, mask_mode } |
c0f3af97 | 412 | |
6c30d220 | 413 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 414 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 415 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 416 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 417 | |
260cd341 LC |
418 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
419 | ||
35c52694 | 420 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
421 | #define Xbr { REP_Fixup, eSI_reg } |
422 | #define Xvr { REP_Fixup, eSI_reg } | |
423 | #define Ybr { REP_Fixup, eDI_reg } | |
424 | #define Yvr { REP_Fixup, eDI_reg } | |
425 | #define Yzr { REP_Fixup, eDI_reg } | |
426 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
427 | #define ALr { REP_Fixup, al_reg } | |
428 | #define eAXr { REP_Fixup, eAX_reg } | |
429 | ||
42164a71 L |
430 | /* Used handle HLE prefix for lockable instructions. */ |
431 | #define Ebh1 { HLE_Fixup1, b_mode } | |
432 | #define Evh1 { HLE_Fixup1, v_mode } | |
433 | #define Ebh2 { HLE_Fixup2, b_mode } | |
434 | #define Evh2 { HLE_Fixup2, v_mode } | |
435 | #define Ebh3 { HLE_Fixup3, b_mode } | |
436 | #define Evh3 { HLE_Fixup3, v_mode } | |
437 | ||
7e8b059b | 438 | #define BND { BND_Fixup, 0 } |
04ef582a | 439 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 440 | |
ce518a5f L |
441 | #define cond_jump_flag { NULL, cond_jump_mode } |
442 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 443 | |
252b5132 | 444 | /* bits in sizeflag */ |
252b5132 | 445 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
446 | #define AFLAG 2 |
447 | #define DFLAG 1 | |
448 | ||
51e7da1b L |
449 | enum |
450 | { | |
451 | /* byte operand */ | |
452 | b_mode = 1, | |
453 | /* byte operand with operand swapped */ | |
3873ba12 | 454 | b_swap_mode, |
e3949f17 L |
455 | /* byte operand, sign extend like 'T' suffix */ |
456 | b_T_mode, | |
51e7da1b | 457 | /* operand size depends on prefixes */ |
3873ba12 | 458 | v_mode, |
51e7da1b | 459 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 460 | v_swap_mode, |
de89d0a3 IT |
461 | /* operand size depends on address prefix */ |
462 | va_mode, | |
51e7da1b | 463 | /* word operand */ |
3873ba12 | 464 | w_mode, |
51e7da1b | 465 | /* double word operand */ |
3873ba12 | 466 | d_mode, |
51e7da1b | 467 | /* double word operand with operand swapped */ |
3873ba12 | 468 | d_swap_mode, |
51e7da1b | 469 | /* quad word operand */ |
3873ba12 | 470 | q_mode, |
51e7da1b | 471 | /* quad word operand with operand swapped */ |
3873ba12 | 472 | q_swap_mode, |
51e7da1b | 473 | /* ten-byte operand */ |
3873ba12 | 474 | t_mode, |
43234a1e L |
475 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
476 | broadcast enabled. */ | |
3873ba12 | 477 | x_mode, |
43234a1e L |
478 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
479 | evex_x_gscat_mode, | |
4726e9a4 JB |
480 | /* Similar to x_mode, but with yet different EVEX mem shifts. */ |
481 | bw_unit_mode, | |
43234a1e L |
482 | /* Similar to x_mode, but with disabled broadcast. */ |
483 | evex_x_nobcst_mode, | |
484 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
485 | in EVEX. */ | |
3873ba12 | 486 | x_swap_mode, |
51e7da1b | 487 | /* 16-byte XMM operand */ |
3873ba12 | 488 | xmm_mode, |
43234a1e L |
489 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
490 | memory operand (depending on vector length). Broadcast isn't | |
491 | allowed. */ | |
3873ba12 | 492 | xmmq_mode, |
43234a1e L |
493 | /* Same as xmmq_mode, but broadcast is allowed. */ |
494 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
495 | /* XMM register or byte memory operand */ |
496 | xmm_mb_mode, | |
497 | /* XMM register or word memory operand */ | |
498 | xmm_mw_mode, | |
499 | /* XMM register or double word memory operand */ | |
500 | xmm_md_mode, | |
501 | /* XMM register or quad word memory operand */ | |
502 | xmm_mq_mode, | |
43234a1e | 503 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 504 | xmmdw_mode, |
43234a1e | 505 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 506 | xmmqd_mode, |
43234a1e L |
507 | /* 32-byte YMM operand */ |
508 | ymm_mode, | |
509 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 510 | ymmq_mode, |
6c30d220 L |
511 | /* 32-byte YMM or 16-byte word operand */ |
512 | ymmxmm_mode, | |
260cd341 LC |
513 | /* TMM operand */ |
514 | tmm_mode, | |
51e7da1b | 515 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 516 | m_mode, |
51e7da1b | 517 | /* pair of v_mode operands */ |
3873ba12 L |
518 | a_mode, |
519 | cond_jump_mode, | |
520 | loop_jcxz_mode, | |
bc31405e | 521 | movsxd_mode, |
7e8b059b | 522 | v_bnd_mode, |
d276ec69 JB |
523 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
524 | v_bndmk_mode, | |
51e7da1b | 525 | /* operand size depends on REX prefixes. */ |
3873ba12 | 526 | dq_mode, |
376cd056 JB |
527 | /* registers like dq_mode, memory like w_mode, displacements like |
528 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 529 | dqw_mode, |
9f79e886 | 530 | /* bounds operand */ |
7e8b059b | 531 | bnd_mode, |
9f79e886 JB |
532 | /* bounds operand with operand swapped */ |
533 | bnd_swap_mode, | |
51e7da1b | 534 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
535 | f_mode, |
536 | const_1_mode, | |
07f5af7d L |
537 | /* v_mode for indirect branch opcodes. */ |
538 | indir_v_mode, | |
51e7da1b | 539 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 540 | stack_v_mode, |
51e7da1b | 541 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 542 | z_mode, |
51e7da1b | 543 | /* 16-byte operand */ |
3873ba12 | 544 | o_mode, |
51e7da1b | 545 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 546 | dqb_mode, |
1ba585e8 IT |
547 | /* registers like d_mode, memory like b_mode. */ |
548 | db_mode, | |
549 | /* registers like d_mode, memory like w_mode. */ | |
550 | dw_mode, | |
51e7da1b | 551 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 552 | dqd_mode, |
51e7da1b | 553 | /* normal vex mode */ |
3873ba12 | 554 | vex_mode, |
d55ee72f | 555 | |
825bd36c | 556 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 557 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
558 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
559 | vex_vsib_d_w_d_mode, | |
825bd36c | 560 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 561 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
562 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
563 | vex_vsib_q_w_d_mode, | |
260cd341 LC |
564 | /* mandatory non-vector SIB. */ |
565 | vex_sibmem_mode, | |
6c30d220 | 566 | |
539f890d L |
567 | /* scalar, ignore vector length. */ |
568 | scalar_mode, | |
539f890d L |
569 | /* like vex_mode, ignore vector length. */ |
570 | vex_scalar_mode, | |
825bd36c | 571 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 572 | vex_scalar_w_dq_mode, |
539f890d | 573 | |
43234a1e L |
574 | /* Static rounding. */ |
575 | evex_rounding_mode, | |
70df6fc9 L |
576 | /* Static rounding, 64-bit mode only. */ |
577 | evex_rounding_64_mode, | |
43234a1e L |
578 | /* Supress all exceptions. */ |
579 | evex_sae_mode, | |
580 | ||
581 | /* Mask register operand. */ | |
582 | mask_mode, | |
1ba585e8 IT |
583 | /* Mask register operand. */ |
584 | mask_bd_mode, | |
43234a1e | 585 | |
3873ba12 L |
586 | es_reg, |
587 | cs_reg, | |
588 | ss_reg, | |
589 | ds_reg, | |
590 | fs_reg, | |
591 | gs_reg, | |
d55ee72f | 592 | |
3873ba12 L |
593 | eAX_reg, |
594 | eCX_reg, | |
595 | eDX_reg, | |
596 | eBX_reg, | |
597 | eSP_reg, | |
598 | eBP_reg, | |
599 | eSI_reg, | |
600 | eDI_reg, | |
d55ee72f | 601 | |
3873ba12 L |
602 | al_reg, |
603 | cl_reg, | |
604 | dl_reg, | |
605 | bl_reg, | |
606 | ah_reg, | |
607 | ch_reg, | |
608 | dh_reg, | |
609 | bh_reg, | |
d55ee72f | 610 | |
3873ba12 L |
611 | ax_reg, |
612 | cx_reg, | |
613 | dx_reg, | |
614 | bx_reg, | |
615 | sp_reg, | |
616 | bp_reg, | |
617 | si_reg, | |
618 | di_reg, | |
d55ee72f | 619 | |
3873ba12 L |
620 | rAX_reg, |
621 | rCX_reg, | |
622 | rDX_reg, | |
623 | rBX_reg, | |
624 | rSP_reg, | |
625 | rBP_reg, | |
626 | rSI_reg, | |
627 | rDI_reg, | |
d55ee72f | 628 | |
3873ba12 L |
629 | z_mode_ax_reg, |
630 | indir_dx_reg | |
51e7da1b | 631 | }; |
252b5132 | 632 | |
51e7da1b L |
633 | enum |
634 | { | |
635 | FLOATCODE = 1, | |
3873ba12 L |
636 | USE_REG_TABLE, |
637 | USE_MOD_TABLE, | |
638 | USE_RM_TABLE, | |
639 | USE_PREFIX_TABLE, | |
640 | USE_X86_64_TABLE, | |
641 | USE_3BYTE_TABLE, | |
f88c9eb0 | 642 | USE_XOP_8F_TABLE, |
3873ba12 L |
643 | USE_VEX_C4_TABLE, |
644 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 645 | USE_VEX_LEN_TABLE, |
43234a1e | 646 | USE_VEX_W_TABLE, |
04e2a182 L |
647 | USE_EVEX_TABLE, |
648 | USE_EVEX_LEN_TABLE | |
51e7da1b | 649 | }; |
6439fc28 | 650 | |
bf890a93 | 651 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 652 | |
bf890a93 IT |
653 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
654 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
655 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
656 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
657 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
658 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
659 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
660 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 661 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 662 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
663 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
664 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
665 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 666 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 667 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 668 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 669 | |
51e7da1b L |
670 | enum |
671 | { | |
672 | REG_80 = 0, | |
3873ba12 | 673 | REG_81, |
7148c369 | 674 | REG_83, |
3873ba12 L |
675 | REG_8F, |
676 | REG_C0, | |
677 | REG_C1, | |
678 | REG_C6, | |
679 | REG_C7, | |
680 | REG_D0, | |
681 | REG_D1, | |
682 | REG_D2, | |
683 | REG_D3, | |
684 | REG_F6, | |
685 | REG_F7, | |
686 | REG_FE, | |
687 | REG_FF, | |
688 | REG_0F00, | |
689 | REG_0F01, | |
690 | REG_0F0D, | |
691 | REG_0F18, | |
f8687e93 JB |
692 | REG_0F1C_P_0_MOD_0, |
693 | REG_0F1E_P_1_MOD_3, | |
c4694f17 | 694 | REG_0F38D8_PREFIX_1, |
c1fa250a | 695 | REG_0F3A0F_PREFIX_1_MOD_3, |
3873ba12 L |
696 | REG_0F71, |
697 | REG_0F72, | |
698 | REG_0F73, | |
699 | REG_0FA6, | |
700 | REG_0FA7, | |
701 | REG_0FAE, | |
702 | REG_0FBA, | |
703 | REG_0FC7, | |
592a252b L |
704 | REG_VEX_0F71, |
705 | REG_VEX_0F72, | |
706 | REG_VEX_0F73, | |
707 | REG_VEX_0FAE, | |
260cd341 | 708 | REG_VEX_0F3849_X86_64_P_0_W_0_M_1, |
f12dc422 | 709 | REG_VEX_0F38F3, |
467bbef0 JB |
710 | |
711 | REG_0FXOP_09_01_L_0, | |
712 | REG_0FXOP_09_02_L_0, | |
713 | REG_0FXOP_09_12_M_1_L_0, | |
714 | REG_0FXOP_0A_12_L_0, | |
43234a1e | 715 | |
1ba585e8 | 716 | REG_EVEX_0F71, |
43234a1e L |
717 | REG_EVEX_0F72, |
718 | REG_EVEX_0F73, | |
719 | REG_EVEX_0F38C6, | |
720 | REG_EVEX_0F38C7 | |
51e7da1b | 721 | }; |
1ceb70f8 | 722 | |
51e7da1b L |
723 | enum |
724 | { | |
725 | MOD_8D = 0, | |
42164a71 L |
726 | MOD_C6_REG_7, |
727 | MOD_C7_REG_7, | |
4a357820 MZ |
728 | MOD_FF_REG_3, |
729 | MOD_FF_REG_5, | |
3873ba12 L |
730 | MOD_0F01_REG_0, |
731 | MOD_0F01_REG_1, | |
732 | MOD_0F01_REG_2, | |
733 | MOD_0F01_REG_3, | |
8eab4136 | 734 | MOD_0F01_REG_5, |
3873ba12 L |
735 | MOD_0F01_REG_7, |
736 | MOD_0F12_PREFIX_0, | |
18897deb | 737 | MOD_0F12_PREFIX_2, |
3873ba12 L |
738 | MOD_0F13, |
739 | MOD_0F16_PREFIX_0, | |
18897deb | 740 | MOD_0F16_PREFIX_2, |
3873ba12 L |
741 | MOD_0F17, |
742 | MOD_0F18_REG_0, | |
743 | MOD_0F18_REG_1, | |
744 | MOD_0F18_REG_2, | |
745 | MOD_0F18_REG_3, | |
d7189fa5 RM |
746 | MOD_0F18_REG_4, |
747 | MOD_0F18_REG_5, | |
748 | MOD_0F18_REG_6, | |
749 | MOD_0F18_REG_7, | |
7e8b059b L |
750 | MOD_0F1A_PREFIX_0, |
751 | MOD_0F1B_PREFIX_0, | |
752 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 753 | MOD_0F1C_PREFIX_0, |
603555e5 | 754 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
755 | MOD_0F2B_PREFIX_0, |
756 | MOD_0F2B_PREFIX_1, | |
757 | MOD_0F2B_PREFIX_2, | |
758 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 759 | MOD_0F50, |
3873ba12 L |
760 | MOD_0F71_REG_2, |
761 | MOD_0F71_REG_4, | |
762 | MOD_0F71_REG_6, | |
763 | MOD_0F72_REG_2, | |
764 | MOD_0F72_REG_4, | |
765 | MOD_0F72_REG_6, | |
766 | MOD_0F73_REG_2, | |
767 | MOD_0F73_REG_3, | |
768 | MOD_0F73_REG_6, | |
769 | MOD_0F73_REG_7, | |
770 | MOD_0FAE_REG_0, | |
771 | MOD_0FAE_REG_1, | |
772 | MOD_0FAE_REG_2, | |
773 | MOD_0FAE_REG_3, | |
774 | MOD_0FAE_REG_4, | |
775 | MOD_0FAE_REG_5, | |
776 | MOD_0FAE_REG_6, | |
777 | MOD_0FAE_REG_7, | |
778 | MOD_0FB2, | |
779 | MOD_0FB4, | |
780 | MOD_0FB5, | |
a8484f96 | 781 | MOD_0FC3, |
963f3586 IT |
782 | MOD_0FC7_REG_3, |
783 | MOD_0FC7_REG_4, | |
784 | MOD_0FC7_REG_5, | |
3873ba12 L |
785 | MOD_0FC7_REG_6, |
786 | MOD_0FC7_REG_7, | |
787 | MOD_0FD7, | |
788 | MOD_0FE7_PREFIX_2, | |
789 | MOD_0FF0_PREFIX_3, | |
7531c613 | 790 | MOD_0F382A, |
c4694f17 TG |
791 | MOD_0F38DC_PREFIX_1, |
792 | MOD_0F38DD_PREFIX_1, | |
793 | MOD_0F38DE_PREFIX_1, | |
794 | MOD_0F38DF_PREFIX_1, | |
7531c613 | 795 | MOD_0F38F5, |
603555e5 | 796 | MOD_0F38F6_PREFIX_0, |
5d79adc4 | 797 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 798 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 799 | MOD_0F38F8_PREFIX_3, |
035e7389 | 800 | MOD_0F38F9, |
c4694f17 TG |
801 | MOD_0F38FA_PREFIX_1, |
802 | MOD_0F38FB_PREFIX_1, | |
c1fa250a | 803 | MOD_0F3A0F_PREFIX_1, |
3873ba12 L |
804 | MOD_62_32BIT, |
805 | MOD_C4_32BIT, | |
806 | MOD_C5_32BIT, | |
592a252b | 807 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 808 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
809 | MOD_VEX_0F13, |
810 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 811 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
812 | MOD_VEX_0F17, |
813 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
814 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
815 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
816 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
817 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
818 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
819 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
820 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
821 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
822 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
823 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
824 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
825 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
826 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
827 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
828 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
829 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
830 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
831 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
832 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
833 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
834 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
835 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
836 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
837 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
838 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
839 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
840 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
841 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
842 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
843 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
844 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
845 | MOD_VEX_0F50, |
846 | MOD_VEX_0F71_REG_2, | |
847 | MOD_VEX_0F71_REG_4, | |
848 | MOD_VEX_0F71_REG_6, | |
849 | MOD_VEX_0F72_REG_2, | |
850 | MOD_VEX_0F72_REG_4, | |
851 | MOD_VEX_0F72_REG_6, | |
852 | MOD_VEX_0F73_REG_2, | |
853 | MOD_VEX_0F73_REG_3, | |
854 | MOD_VEX_0F73_REG_6, | |
855 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
856 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
857 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
858 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
859 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
860 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
861 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 862 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
863 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
864 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 865 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
866 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
867 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
868 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
869 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
870 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
871 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
872 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
873 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
874 | MOD_VEX_0FAE_REG_2, |
875 | MOD_VEX_0FAE_REG_3, | |
7531c613 JB |
876 | MOD_VEX_0FD7, |
877 | MOD_VEX_0FE7, | |
592a252b | 878 | MOD_VEX_0FF0_PREFIX_3, |
7531c613 JB |
879 | MOD_VEX_0F381A, |
880 | MOD_VEX_0F382A, | |
881 | MOD_VEX_0F382C, | |
882 | MOD_VEX_0F382D, | |
883 | MOD_VEX_0F382E, | |
884 | MOD_VEX_0F382F, | |
09d73035 CL |
885 | MOD_VEX_0F3849_X86_64_P_0_W_0, |
886 | MOD_VEX_0F3849_X86_64_P_2_W_0, | |
887 | MOD_VEX_0F3849_X86_64_P_3_W_0, | |
888 | MOD_VEX_0F384B_X86_64_P_1_W_0, | |
889 | MOD_VEX_0F384B_X86_64_P_2_W_0, | |
890 | MOD_VEX_0F384B_X86_64_P_3_W_0, | |
7531c613 | 891 | MOD_VEX_0F385A, |
09d73035 CL |
892 | MOD_VEX_0F385C_X86_64_P_1_W_0, |
893 | MOD_VEX_0F385E_X86_64_P_0_W_0, | |
894 | MOD_VEX_0F385E_X86_64_P_1_W_0, | |
895 | MOD_VEX_0F385E_X86_64_P_2_W_0, | |
896 | MOD_VEX_0F385E_X86_64_P_3_W_0, | |
7531c613 JB |
897 | MOD_VEX_0F388C, |
898 | MOD_VEX_0F388E, | |
bb5b3501 JB |
899 | MOD_VEX_0F3A30_L_0, |
900 | MOD_VEX_0F3A31_L_0, | |
901 | MOD_VEX_0F3A32_L_0, | |
902 | MOD_VEX_0F3A33_L_0, | |
43234a1e | 903 | |
467bbef0 JB |
904 | MOD_VEX_0FXOP_09_12, |
905 | ||
43234a1e | 906 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
907 | MOD_EVEX_0F12_PREFIX_2, |
908 | MOD_EVEX_0F13, | |
43234a1e | 909 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
910 | MOD_EVEX_0F16_PREFIX_2, |
911 | MOD_EVEX_0F17, | |
912 | MOD_EVEX_0F2B, | |
7531c613 JB |
913 | MOD_EVEX_0F381A_W_0, |
914 | MOD_EVEX_0F381A_W_1, | |
915 | MOD_EVEX_0F381B_W_0, | |
916 | MOD_EVEX_0F381B_W_1, | |
464d2b65 JB |
917 | MOD_EVEX_0F3828_P_1, |
918 | MOD_EVEX_0F382A_P_1_W_1, | |
919 | MOD_EVEX_0F3838_P_1, | |
920 | MOD_EVEX_0F383A_P_1_W_0, | |
7531c613 JB |
921 | MOD_EVEX_0F385A_W_0, |
922 | MOD_EVEX_0F385A_W_1, | |
923 | MOD_EVEX_0F385B_W_0, | |
924 | MOD_EVEX_0F385B_W_1, | |
464d2b65 JB |
925 | MOD_EVEX_0F387A_W_0, |
926 | MOD_EVEX_0F387B_W_0, | |
927 | MOD_EVEX_0F387C, | |
43234a1e L |
928 | MOD_EVEX_0F38C6_REG_1, |
929 | MOD_EVEX_0F38C6_REG_2, | |
930 | MOD_EVEX_0F38C6_REG_5, | |
931 | MOD_EVEX_0F38C6_REG_6, | |
932 | MOD_EVEX_0F38C7_REG_1, | |
933 | MOD_EVEX_0F38C7_REG_2, | |
934 | MOD_EVEX_0F38C7_REG_5, | |
935 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 936 | }; |
1ceb70f8 | 937 | |
51e7da1b L |
938 | enum |
939 | { | |
42164a71 L |
940 | RM_C6_REG_7 = 0, |
941 | RM_C7_REG_7, | |
942 | RM_0F01_REG_0, | |
3873ba12 L |
943 | RM_0F01_REG_1, |
944 | RM_0F01_REG_2, | |
945 | RM_0F01_REG_3, | |
f8687e93 JB |
946 | RM_0F01_REG_5_MOD_3, |
947 | RM_0F01_REG_7_MOD_3, | |
948 | RM_0F1E_P_1_MOD_3_REG_7, | |
c1fa250a | 949 | RM_0F3A0F_P_1_MOD_3_REG_0, |
f8687e93 JB |
950 | RM_0FAE_REG_6_MOD_3_P_0, |
951 | RM_0FAE_REG_7_MOD_3, | |
260cd341 | 952 | RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 |
51e7da1b | 953 | }; |
1ceb70f8 | 954 | |
51e7da1b L |
955 | enum |
956 | { | |
957 | PREFIX_90 = 0, | |
81d54bb7 CL |
958 | PREFIX_0F01_REG_1_RM_4, |
959 | PREFIX_0F01_REG_1_RM_5, | |
960 | PREFIX_0F01_REG_1_RM_6, | |
961 | PREFIX_0F01_REG_1_RM_7, | |
a847e322 | 962 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
963 | PREFIX_0F01_REG_5_MOD_0, |
964 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 965 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 966 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
f64c42a9 LC |
967 | PREFIX_0F01_REG_5_MOD_3_RM_4, |
968 | PREFIX_0F01_REG_5_MOD_3_RM_5, | |
969 | PREFIX_0F01_REG_5_MOD_3_RM_6, | |
970 | PREFIX_0F01_REG_5_MOD_3_RM_7, | |
267b8516 | 971 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
646cc3e0 GG |
972 | PREFIX_0F01_REG_7_MOD_3_RM_6, |
973 | PREFIX_0F01_REG_7_MOD_3_RM_7, | |
3233d7d0 | 974 | PREFIX_0F09, |
3873ba12 L |
975 | PREFIX_0F10, |
976 | PREFIX_0F11, | |
977 | PREFIX_0F12, | |
978 | PREFIX_0F16, | |
7e8b059b L |
979 | PREFIX_0F1A, |
980 | PREFIX_0F1B, | |
c48935d7 | 981 | PREFIX_0F1C, |
603555e5 | 982 | PREFIX_0F1E, |
3873ba12 L |
983 | PREFIX_0F2A, |
984 | PREFIX_0F2B, | |
985 | PREFIX_0F2C, | |
986 | PREFIX_0F2D, | |
987 | PREFIX_0F2E, | |
988 | PREFIX_0F2F, | |
989 | PREFIX_0F51, | |
990 | PREFIX_0F52, | |
991 | PREFIX_0F53, | |
992 | PREFIX_0F58, | |
993 | PREFIX_0F59, | |
994 | PREFIX_0F5A, | |
995 | PREFIX_0F5B, | |
996 | PREFIX_0F5C, | |
997 | PREFIX_0F5D, | |
998 | PREFIX_0F5E, | |
999 | PREFIX_0F5F, | |
1000 | PREFIX_0F60, | |
1001 | PREFIX_0F61, | |
1002 | PREFIX_0F62, | |
3873ba12 L |
1003 | PREFIX_0F6F, |
1004 | PREFIX_0F70, | |
3873ba12 L |
1005 | PREFIX_0F78, |
1006 | PREFIX_0F79, | |
1007 | PREFIX_0F7C, | |
1008 | PREFIX_0F7D, | |
1009 | PREFIX_0F7E, | |
1010 | PREFIX_0F7F, | |
f8687e93 JB |
1011 | PREFIX_0FAE_REG_0_MOD_3, |
1012 | PREFIX_0FAE_REG_1_MOD_3, | |
1013 | PREFIX_0FAE_REG_2_MOD_3, | |
1014 | PREFIX_0FAE_REG_3_MOD_3, | |
1015 | PREFIX_0FAE_REG_4_MOD_0, | |
1016 | PREFIX_0FAE_REG_4_MOD_3, | |
f8687e93 JB |
1017 | PREFIX_0FAE_REG_5_MOD_3, |
1018 | PREFIX_0FAE_REG_6_MOD_0, | |
1019 | PREFIX_0FAE_REG_6_MOD_3, | |
1020 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1021 | PREFIX_0FB8, |
f12dc422 | 1022 | PREFIX_0FBC, |
3873ba12 L |
1023 | PREFIX_0FBD, |
1024 | PREFIX_0FC2, | |
f8687e93 JB |
1025 | PREFIX_0FC7_REG_6_MOD_0, |
1026 | PREFIX_0FC7_REG_6_MOD_3, | |
1027 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1028 | PREFIX_0FD0, |
1029 | PREFIX_0FD6, | |
1030 | PREFIX_0FE6, | |
1031 | PREFIX_0FE7, | |
1032 | PREFIX_0FF0, | |
1033 | PREFIX_0FF7, | |
c4694f17 TG |
1034 | PREFIX_0F38D8, |
1035 | PREFIX_0F38DC, | |
1036 | PREFIX_0F38DD, | |
1037 | PREFIX_0F38DE, | |
1038 | PREFIX_0F38DF, | |
3873ba12 L |
1039 | PREFIX_0F38F0, |
1040 | PREFIX_0F38F1, | |
e2e1fcde | 1041 | PREFIX_0F38F6, |
c0a30a9f | 1042 | PREFIX_0F38F8, |
c4694f17 TG |
1043 | PREFIX_0F38FA, |
1044 | PREFIX_0F38FB, | |
c1fa250a | 1045 | PREFIX_0F3A0F, |
592a252b L |
1046 | PREFIX_VEX_0F10, |
1047 | PREFIX_VEX_0F11, | |
1048 | PREFIX_VEX_0F12, | |
1049 | PREFIX_VEX_0F16, | |
1050 | PREFIX_VEX_0F2A, | |
1051 | PREFIX_VEX_0F2C, | |
1052 | PREFIX_VEX_0F2D, | |
1053 | PREFIX_VEX_0F2E, | |
1054 | PREFIX_VEX_0F2F, | |
43234a1e L |
1055 | PREFIX_VEX_0F41, |
1056 | PREFIX_VEX_0F42, | |
1057 | PREFIX_VEX_0F44, | |
1058 | PREFIX_VEX_0F45, | |
1059 | PREFIX_VEX_0F46, | |
1060 | PREFIX_VEX_0F47, | |
1ba585e8 | 1061 | PREFIX_VEX_0F4A, |
43234a1e | 1062 | PREFIX_VEX_0F4B, |
592a252b L |
1063 | PREFIX_VEX_0F51, |
1064 | PREFIX_VEX_0F52, | |
1065 | PREFIX_VEX_0F53, | |
1066 | PREFIX_VEX_0F58, | |
1067 | PREFIX_VEX_0F59, | |
1068 | PREFIX_VEX_0F5A, | |
1069 | PREFIX_VEX_0F5B, | |
1070 | PREFIX_VEX_0F5C, | |
1071 | PREFIX_VEX_0F5D, | |
1072 | PREFIX_VEX_0F5E, | |
1073 | PREFIX_VEX_0F5F, | |
592a252b L |
1074 | PREFIX_VEX_0F6F, |
1075 | PREFIX_VEX_0F70, | |
592a252b L |
1076 | PREFIX_VEX_0F7C, |
1077 | PREFIX_VEX_0F7D, | |
1078 | PREFIX_VEX_0F7E, | |
1079 | PREFIX_VEX_0F7F, | |
43234a1e L |
1080 | PREFIX_VEX_0F90, |
1081 | PREFIX_VEX_0F91, | |
1082 | PREFIX_VEX_0F92, | |
1083 | PREFIX_VEX_0F93, | |
1084 | PREFIX_VEX_0F98, | |
1ba585e8 | 1085 | PREFIX_VEX_0F99, |
592a252b | 1086 | PREFIX_VEX_0FC2, |
592a252b | 1087 | PREFIX_VEX_0FD0, |
592a252b | 1088 | PREFIX_VEX_0FE6, |
592a252b | 1089 | PREFIX_VEX_0FF0, |
260cd341 LC |
1090 | PREFIX_VEX_0F3849_X86_64, |
1091 | PREFIX_VEX_0F384B_X86_64, | |
260cd341 LC |
1092 | PREFIX_VEX_0F385C_X86_64, |
1093 | PREFIX_VEX_0F385E_X86_64, | |
6c30d220 L |
1094 | PREFIX_VEX_0F38F5, |
1095 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1096 | PREFIX_VEX_0F38F7, |
43234a1e L |
1097 | PREFIX_VEX_0F3AF0, |
1098 | ||
1099 | PREFIX_EVEX_0F10, | |
1100 | PREFIX_EVEX_0F11, | |
1101 | PREFIX_EVEX_0F12, | |
43234a1e | 1102 | PREFIX_EVEX_0F16, |
43234a1e | 1103 | PREFIX_EVEX_0F2A, |
43234a1e L |
1104 | PREFIX_EVEX_0F51, |
1105 | PREFIX_EVEX_0F58, | |
1106 | PREFIX_EVEX_0F59, | |
1107 | PREFIX_EVEX_0F5A, | |
1108 | PREFIX_EVEX_0F5B, | |
1109 | PREFIX_EVEX_0F5C, | |
1110 | PREFIX_EVEX_0F5D, | |
1111 | PREFIX_EVEX_0F5E, | |
1112 | PREFIX_EVEX_0F5F, | |
43234a1e L |
1113 | PREFIX_EVEX_0F6F, |
1114 | PREFIX_EVEX_0F70, | |
43234a1e L |
1115 | PREFIX_EVEX_0F78, |
1116 | PREFIX_EVEX_0F79, | |
1117 | PREFIX_EVEX_0F7A, | |
1118 | PREFIX_EVEX_0F7B, | |
1119 | PREFIX_EVEX_0F7E, | |
1120 | PREFIX_EVEX_0F7F, | |
1121 | PREFIX_EVEX_0FC2, | |
43234a1e | 1122 | PREFIX_EVEX_0FE6, |
1ba585e8 | 1123 | PREFIX_EVEX_0F3810, |
43234a1e L |
1124 | PREFIX_EVEX_0F3811, |
1125 | PREFIX_EVEX_0F3812, | |
1126 | PREFIX_EVEX_0F3813, | |
1127 | PREFIX_EVEX_0F3814, | |
1128 | PREFIX_EVEX_0F3815, | |
1ba585e8 | 1129 | PREFIX_EVEX_0F3820, |
43234a1e L |
1130 | PREFIX_EVEX_0F3821, |
1131 | PREFIX_EVEX_0F3822, | |
1132 | PREFIX_EVEX_0F3823, | |
1133 | PREFIX_EVEX_0F3824, | |
1134 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1135 | PREFIX_EVEX_0F3826, |
43234a1e L |
1136 | PREFIX_EVEX_0F3827, |
1137 | PREFIX_EVEX_0F3828, | |
1138 | PREFIX_EVEX_0F3829, | |
1139 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1140 | PREFIX_EVEX_0F3830, |
43234a1e L |
1141 | PREFIX_EVEX_0F3831, |
1142 | PREFIX_EVEX_0F3832, | |
1143 | PREFIX_EVEX_0F3833, | |
1144 | PREFIX_EVEX_0F3834, | |
1145 | PREFIX_EVEX_0F3835, | |
1ba585e8 | 1146 | PREFIX_EVEX_0F3838, |
43234a1e L |
1147 | PREFIX_EVEX_0F3839, |
1148 | PREFIX_EVEX_0F383A, | |
47acf0bd IT |
1149 | PREFIX_EVEX_0F3852, |
1150 | PREFIX_EVEX_0F3853, | |
9186c494 | 1151 | PREFIX_EVEX_0F3868, |
53467f57 | 1152 | PREFIX_EVEX_0F3872, |
43234a1e L |
1153 | PREFIX_EVEX_0F389A, |
1154 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1155 | PREFIX_EVEX_0F38AA, |
1156 | PREFIX_EVEX_0F38AB, | |
51e7da1b | 1157 | }; |
4e7d34a6 | 1158 | |
51e7da1b L |
1159 | enum |
1160 | { | |
1161 | X86_64_06 = 0, | |
3873ba12 | 1162 | X86_64_07, |
1673df32 | 1163 | X86_64_0E, |
3873ba12 L |
1164 | X86_64_16, |
1165 | X86_64_17, | |
1166 | X86_64_1E, | |
1167 | X86_64_1F, | |
1168 | X86_64_27, | |
1169 | X86_64_2F, | |
1170 | X86_64_37, | |
1171 | X86_64_3F, | |
1172 | X86_64_60, | |
1173 | X86_64_61, | |
1174 | X86_64_62, | |
1175 | X86_64_63, | |
1176 | X86_64_6D, | |
1177 | X86_64_6F, | |
d039fef3 | 1178 | X86_64_82, |
3873ba12 | 1179 | X86_64_9A, |
aeab2b26 JB |
1180 | X86_64_C2, |
1181 | X86_64_C3, | |
3873ba12 L |
1182 | X86_64_C4, |
1183 | X86_64_C5, | |
1184 | X86_64_CE, | |
1185 | X86_64_D4, | |
1186 | X86_64_D5, | |
a72d2af2 L |
1187 | X86_64_E8, |
1188 | X86_64_E9, | |
3873ba12 L |
1189 | X86_64_EA, |
1190 | X86_64_0F01_REG_0, | |
1191 | X86_64_0F01_REG_1, | |
81d54bb7 CL |
1192 | X86_64_0F01_REG_1_RM_5_PREFIX_2, |
1193 | X86_64_0F01_REG_1_RM_6_PREFIX_2, | |
1194 | X86_64_0F01_REG_1_RM_7_PREFIX_2, | |
3873ba12 | 1195 | X86_64_0F01_REG_2, |
260cd341 | 1196 | X86_64_0F01_REG_3, |
78467458 JB |
1197 | X86_64_0F24, |
1198 | X86_64_0F26, | |
260cd341 LC |
1199 | X86_64_VEX_0F3849, |
1200 | X86_64_VEX_0F384B, | |
1201 | X86_64_VEX_0F385C, | |
f64c42a9 LC |
1202 | X86_64_VEX_0F385E, |
1203 | X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, | |
1204 | X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, | |
1205 | X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, | |
1206 | X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, | |
646cc3e0 GG |
1207 | X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, |
1208 | X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, | |
1209 | X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, | |
f64c42a9 | 1210 | X86_64_0FC7_REG_6_MOD_3_PREFIX_1 |
51e7da1b | 1211 | }; |
4e7d34a6 | 1212 | |
51e7da1b L |
1213 | enum |
1214 | { | |
1215 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1216 | THREE_BYTE_0F3A |
51e7da1b | 1217 | }; |
4e7d34a6 | 1218 | |
f88c9eb0 SP |
1219 | enum |
1220 | { | |
5dd85c99 SP |
1221 | XOP_08 = 0, |
1222 | XOP_09, | |
f88c9eb0 SP |
1223 | XOP_0A |
1224 | }; | |
1225 | ||
51e7da1b L |
1226 | enum |
1227 | { | |
1228 | VEX_0F = 0, | |
3873ba12 L |
1229 | VEX_0F38, |
1230 | VEX_0F3A | |
51e7da1b | 1231 | }; |
c0f3af97 | 1232 | |
43234a1e L |
1233 | enum |
1234 | { | |
1235 | EVEX_0F = 0, | |
1236 | EVEX_0F38, | |
1237 | EVEX_0F3A | |
1238 | }; | |
1239 | ||
51e7da1b L |
1240 | enum |
1241 | { | |
ec6f095a | 1242 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1243 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1244 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1245 | VEX_LEN_0F13_M_0, |
1246 | VEX_LEN_0F16_P_0_M_0, | |
1247 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1248 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1249 | VEX_LEN_0F17_M_0, |
43234a1e | 1250 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1251 | VEX_LEN_0F41_P_2, |
43234a1e | 1252 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1253 | VEX_LEN_0F42_P_2, |
43234a1e | 1254 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1255 | VEX_LEN_0F44_P_2, |
43234a1e | 1256 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1257 | VEX_LEN_0F45_P_2, |
43234a1e | 1258 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1259 | VEX_LEN_0F46_P_2, |
43234a1e | 1260 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1261 | VEX_LEN_0F47_P_2, |
1262 | VEX_LEN_0F4A_P_0, | |
1263 | VEX_LEN_0F4A_P_2, | |
1264 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1265 | VEX_LEN_0F4B_P_2, |
7531c613 | 1266 | VEX_LEN_0F6E, |
035e7389 | 1267 | VEX_LEN_0F77, |
592a252b L |
1268 | VEX_LEN_0F7E_P_1, |
1269 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1270 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1271 | VEX_LEN_0F90_P_2, |
43234a1e | 1272 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1273 | VEX_LEN_0F91_P_2, |
43234a1e | 1274 | VEX_LEN_0F92_P_0, |
90a915bf | 1275 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1276 | VEX_LEN_0F92_P_3, |
43234a1e | 1277 | VEX_LEN_0F93_P_0, |
90a915bf | 1278 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1279 | VEX_LEN_0F93_P_3, |
43234a1e | 1280 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1281 | VEX_LEN_0F98_P_2, |
1282 | VEX_LEN_0F99_P_0, | |
1283 | VEX_LEN_0F99_P_2, | |
592a252b L |
1284 | VEX_LEN_0FAE_R_2_M_0, |
1285 | VEX_LEN_0FAE_R_3_M_0, | |
7531c613 JB |
1286 | VEX_LEN_0FC4, |
1287 | VEX_LEN_0FC5, | |
1288 | VEX_LEN_0FD6, | |
1289 | VEX_LEN_0FF7, | |
1290 | VEX_LEN_0F3816, | |
1291 | VEX_LEN_0F3819, | |
1292 | VEX_LEN_0F381A_M_0, | |
1293 | VEX_LEN_0F3836, | |
1294 | VEX_LEN_0F3841, | |
260cd341 LC |
1295 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_0, |
1296 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0, | |
1297 | VEX_LEN_0F3849_X86_64_P_2_W_0_M_0, | |
1298 | VEX_LEN_0F3849_X86_64_P_3_W_0_M_0, | |
1299 | VEX_LEN_0F384B_X86_64_P_1_W_0_M_0, | |
1300 | VEX_LEN_0F384B_X86_64_P_2_W_0_M_0, | |
1301 | VEX_LEN_0F384B_X86_64_P_3_W_0_M_0, | |
7531c613 | 1302 | VEX_LEN_0F385A_M_0, |
260cd341 LC |
1303 | VEX_LEN_0F385C_X86_64_P_1_W_0_M_0, |
1304 | VEX_LEN_0F385E_X86_64_P_0_W_0_M_0, | |
1305 | VEX_LEN_0F385E_X86_64_P_1_W_0_M_0, | |
1306 | VEX_LEN_0F385E_X86_64_P_2_W_0_M_0, | |
1307 | VEX_LEN_0F385E_X86_64_P_3_W_0_M_0, | |
7531c613 | 1308 | VEX_LEN_0F38DB, |
035e7389 JB |
1309 | VEX_LEN_0F38F2, |
1310 | VEX_LEN_0F38F3_R_1, | |
1311 | VEX_LEN_0F38F3_R_2, | |
1312 | VEX_LEN_0F38F3_R_3, | |
6c30d220 L |
1313 | VEX_LEN_0F38F5_P_0, |
1314 | VEX_LEN_0F38F5_P_1, | |
1315 | VEX_LEN_0F38F5_P_3, | |
1316 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1317 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1318 | VEX_LEN_0F38F7_P_1, |
1319 | VEX_LEN_0F38F7_P_2, | |
1320 | VEX_LEN_0F38F7_P_3, | |
7531c613 JB |
1321 | VEX_LEN_0F3A00, |
1322 | VEX_LEN_0F3A01, | |
1323 | VEX_LEN_0F3A06, | |
1324 | VEX_LEN_0F3A14, | |
1325 | VEX_LEN_0F3A15, | |
1326 | VEX_LEN_0F3A16, | |
1327 | VEX_LEN_0F3A17, | |
1328 | VEX_LEN_0F3A18, | |
1329 | VEX_LEN_0F3A19, | |
1330 | VEX_LEN_0F3A20, | |
1331 | VEX_LEN_0F3A21, | |
1332 | VEX_LEN_0F3A22, | |
1333 | VEX_LEN_0F3A30, | |
1334 | VEX_LEN_0F3A31, | |
1335 | VEX_LEN_0F3A32, | |
1336 | VEX_LEN_0F3A33, | |
1337 | VEX_LEN_0F3A38, | |
1338 | VEX_LEN_0F3A39, | |
1339 | VEX_LEN_0F3A41, | |
1340 | VEX_LEN_0F3A46, | |
1341 | VEX_LEN_0F3A60, | |
1342 | VEX_LEN_0F3A61, | |
1343 | VEX_LEN_0F3A62, | |
1344 | VEX_LEN_0F3A63, | |
1345 | VEX_LEN_0F3ADF, | |
6c30d220 | 1346 | VEX_LEN_0F3AF0_P_3, |
467bbef0 JB |
1347 | VEX_LEN_0FXOP_08_85, |
1348 | VEX_LEN_0FXOP_08_86, | |
1349 | VEX_LEN_0FXOP_08_87, | |
1350 | VEX_LEN_0FXOP_08_8E, | |
1351 | VEX_LEN_0FXOP_08_8F, | |
1352 | VEX_LEN_0FXOP_08_95, | |
1353 | VEX_LEN_0FXOP_08_96, | |
1354 | VEX_LEN_0FXOP_08_97, | |
1355 | VEX_LEN_0FXOP_08_9E, | |
1356 | VEX_LEN_0FXOP_08_9F, | |
1357 | VEX_LEN_0FXOP_08_A3, | |
1358 | VEX_LEN_0FXOP_08_A6, | |
1359 | VEX_LEN_0FXOP_08_B6, | |
1360 | VEX_LEN_0FXOP_08_C0, | |
1361 | VEX_LEN_0FXOP_08_C1, | |
1362 | VEX_LEN_0FXOP_08_C2, | |
1363 | VEX_LEN_0FXOP_08_C3, | |
ff688e1f L |
1364 | VEX_LEN_0FXOP_08_CC, |
1365 | VEX_LEN_0FXOP_08_CD, | |
1366 | VEX_LEN_0FXOP_08_CE, | |
1367 | VEX_LEN_0FXOP_08_CF, | |
1368 | VEX_LEN_0FXOP_08_EC, | |
1369 | VEX_LEN_0FXOP_08_ED, | |
1370 | VEX_LEN_0FXOP_08_EE, | |
1371 | VEX_LEN_0FXOP_08_EF, | |
467bbef0 JB |
1372 | VEX_LEN_0FXOP_09_01, |
1373 | VEX_LEN_0FXOP_09_02, | |
1374 | VEX_LEN_0FXOP_09_12_M_1, | |
b5b098c2 JB |
1375 | VEX_LEN_0FXOP_09_82_W_0, |
1376 | VEX_LEN_0FXOP_09_83_W_0, | |
467bbef0 JB |
1377 | VEX_LEN_0FXOP_09_90, |
1378 | VEX_LEN_0FXOP_09_91, | |
1379 | VEX_LEN_0FXOP_09_92, | |
1380 | VEX_LEN_0FXOP_09_93, | |
1381 | VEX_LEN_0FXOP_09_94, | |
1382 | VEX_LEN_0FXOP_09_95, | |
1383 | VEX_LEN_0FXOP_09_96, | |
1384 | VEX_LEN_0FXOP_09_97, | |
1385 | VEX_LEN_0FXOP_09_98, | |
1386 | VEX_LEN_0FXOP_09_99, | |
1387 | VEX_LEN_0FXOP_09_9A, | |
1388 | VEX_LEN_0FXOP_09_9B, | |
1389 | VEX_LEN_0FXOP_09_C1, | |
1390 | VEX_LEN_0FXOP_09_C2, | |
1391 | VEX_LEN_0FXOP_09_C3, | |
1392 | VEX_LEN_0FXOP_09_C6, | |
1393 | VEX_LEN_0FXOP_09_C7, | |
1394 | VEX_LEN_0FXOP_09_CB, | |
1395 | VEX_LEN_0FXOP_09_D1, | |
1396 | VEX_LEN_0FXOP_09_D2, | |
1397 | VEX_LEN_0FXOP_09_D3, | |
1398 | VEX_LEN_0FXOP_09_D6, | |
1399 | VEX_LEN_0FXOP_09_D7, | |
1400 | VEX_LEN_0FXOP_09_DB, | |
1401 | VEX_LEN_0FXOP_09_E1, | |
1402 | VEX_LEN_0FXOP_09_E2, | |
1403 | VEX_LEN_0FXOP_09_E3, | |
1404 | VEX_LEN_0FXOP_0A_12, | |
51e7da1b | 1405 | }; |
c0f3af97 | 1406 | |
04e2a182 L |
1407 | enum |
1408 | { | |
7531c613 | 1409 | EVEX_LEN_0F6E = 0, |
04e2a182 L |
1410 | EVEX_LEN_0F7E_P_1, |
1411 | EVEX_LEN_0F7E_P_2, | |
7531c613 JB |
1412 | EVEX_LEN_0FC4, |
1413 | EVEX_LEN_0FC5, | |
1414 | EVEX_LEN_0FD6, | |
1415 | EVEX_LEN_0F3816, | |
1416 | EVEX_LEN_0F3819_W_0, | |
1417 | EVEX_LEN_0F3819_W_1, | |
1418 | EVEX_LEN_0F381A_W_0_M_0, | |
1419 | EVEX_LEN_0F381A_W_1_M_0, | |
1420 | EVEX_LEN_0F381B_W_0_M_0, | |
1421 | EVEX_LEN_0F381B_W_1_M_0, | |
1422 | EVEX_LEN_0F3836, | |
1423 | EVEX_LEN_0F385A_W_0_M_0, | |
1424 | EVEX_LEN_0F385A_W_1_M_0, | |
1425 | EVEX_LEN_0F385B_W_0_M_0, | |
1426 | EVEX_LEN_0F385B_W_1_M_0, | |
1427 | EVEX_LEN_0F38C6_R_1_M_0, | |
1428 | EVEX_LEN_0F38C6_R_2_M_0, | |
1429 | EVEX_LEN_0F38C6_R_5_M_0, | |
1430 | EVEX_LEN_0F38C6_R_6_M_0, | |
1431 | EVEX_LEN_0F38C7_R_1_M_0_W_0, | |
1432 | EVEX_LEN_0F38C7_R_1_M_0_W_1, | |
1433 | EVEX_LEN_0F38C7_R_2_M_0_W_0, | |
1434 | EVEX_LEN_0F38C7_R_2_M_0_W_1, | |
1435 | EVEX_LEN_0F38C7_R_5_M_0_W_0, | |
1436 | EVEX_LEN_0F38C7_R_5_M_0_W_1, | |
1437 | EVEX_LEN_0F38C7_R_6_M_0_W_0, | |
1438 | EVEX_LEN_0F38C7_R_6_M_0_W_1, | |
1439 | EVEX_LEN_0F3A00_W_1, | |
1440 | EVEX_LEN_0F3A01_W_1, | |
1441 | EVEX_LEN_0F3A14, | |
1442 | EVEX_LEN_0F3A15, | |
1443 | EVEX_LEN_0F3A16, | |
1444 | EVEX_LEN_0F3A17, | |
1445 | EVEX_LEN_0F3A18_W_0, | |
1446 | EVEX_LEN_0F3A18_W_1, | |
1447 | EVEX_LEN_0F3A19_W_0, | |
1448 | EVEX_LEN_0F3A19_W_1, | |
1449 | EVEX_LEN_0F3A1A_W_0, | |
1450 | EVEX_LEN_0F3A1A_W_1, | |
1451 | EVEX_LEN_0F3A1B_W_0, | |
1452 | EVEX_LEN_0F3A1B_W_1, | |
1453 | EVEX_LEN_0F3A20, | |
1454 | EVEX_LEN_0F3A21_W_0, | |
1455 | EVEX_LEN_0F3A22, | |
1456 | EVEX_LEN_0F3A23_W_0, | |
1457 | EVEX_LEN_0F3A23_W_1, | |
1458 | EVEX_LEN_0F3A38_W_0, | |
1459 | EVEX_LEN_0F3A38_W_1, | |
1460 | EVEX_LEN_0F3A39_W_0, | |
1461 | EVEX_LEN_0F3A39_W_1, | |
1462 | EVEX_LEN_0F3A3A_W_0, | |
1463 | EVEX_LEN_0F3A3A_W_1, | |
1464 | EVEX_LEN_0F3A3B_W_0, | |
1465 | EVEX_LEN_0F3A3B_W_1, | |
1466 | EVEX_LEN_0F3A43_W_0, | |
1467 | EVEX_LEN_0F3A43_W_1 | |
04e2a182 L |
1468 | }; |
1469 | ||
9e30b8e0 L |
1470 | enum |
1471 | { | |
ec6f095a | 1472 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1473 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1474 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1475 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1476 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1477 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1478 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1479 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1480 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1481 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1482 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1483 | VEX_W_0F47_P_2_LEN_1, |
1484 | VEX_W_0F4A_P_0_LEN_1, | |
1485 | VEX_W_0F4A_P_2_LEN_1, | |
1486 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1487 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1488 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1489 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1490 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1491 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1492 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1493 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1494 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1495 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1496 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1497 | VEX_W_0F98_P_2_LEN_0, |
1498 | VEX_W_0F99_P_0_LEN_0, | |
1499 | VEX_W_0F99_P_2_LEN_0, | |
7531c613 JB |
1500 | VEX_W_0F380C, |
1501 | VEX_W_0F380D, | |
1502 | VEX_W_0F380E, | |
1503 | VEX_W_0F380F, | |
1504 | VEX_W_0F3813, | |
1505 | VEX_W_0F3816_L_1, | |
1506 | VEX_W_0F3818, | |
1507 | VEX_W_0F3819_L_1, | |
1508 | VEX_W_0F381A_M_0_L_1, | |
1509 | VEX_W_0F382C_M_0, | |
1510 | VEX_W_0F382D_M_0, | |
1511 | VEX_W_0F382E_M_0, | |
1512 | VEX_W_0F382F_M_0, | |
1513 | VEX_W_0F3836, | |
1514 | VEX_W_0F3846, | |
260cd341 LC |
1515 | VEX_W_0F3849_X86_64_P_0, |
1516 | VEX_W_0F3849_X86_64_P_2, | |
1517 | VEX_W_0F3849_X86_64_P_3, | |
1518 | VEX_W_0F384B_X86_64_P_1, | |
1519 | VEX_W_0F384B_X86_64_P_2, | |
1520 | VEX_W_0F384B_X86_64_P_3, | |
58bf9b6a L |
1521 | VEX_W_0F3850, |
1522 | VEX_W_0F3851, | |
1523 | VEX_W_0F3852, | |
1524 | VEX_W_0F3853, | |
7531c613 JB |
1525 | VEX_W_0F3858, |
1526 | VEX_W_0F3859, | |
1527 | VEX_W_0F385A_M_0_L_0, | |
260cd341 LC |
1528 | VEX_W_0F385C_X86_64_P_1, |
1529 | VEX_W_0F385E_X86_64_P_0, | |
1530 | VEX_W_0F385E_X86_64_P_1, | |
1531 | VEX_W_0F385E_X86_64_P_2, | |
1532 | VEX_W_0F385E_X86_64_P_3, | |
7531c613 JB |
1533 | VEX_W_0F3878, |
1534 | VEX_W_0F3879, | |
1535 | VEX_W_0F38CF, | |
1536 | VEX_W_0F3A00_L_1, | |
1537 | VEX_W_0F3A01_L_1, | |
1538 | VEX_W_0F3A02, | |
1539 | VEX_W_0F3A04, | |
1540 | VEX_W_0F3A05, | |
1541 | VEX_W_0F3A06_L_1, | |
1542 | VEX_W_0F3A18_L_1, | |
1543 | VEX_W_0F3A19_L_1, | |
1544 | VEX_W_0F3A1D, | |
7531c613 JB |
1545 | VEX_W_0F3A38_L_1, |
1546 | VEX_W_0F3A39_L_1, | |
1547 | VEX_W_0F3A46_L_1, | |
1548 | VEX_W_0F3A4A, | |
1549 | VEX_W_0F3A4B, | |
1550 | VEX_W_0F3A4C, | |
1551 | VEX_W_0F3ACE, | |
1552 | VEX_W_0F3ACF, | |
43234a1e | 1553 | |
467bbef0 JB |
1554 | VEX_W_0FXOP_08_85_L_0, |
1555 | VEX_W_0FXOP_08_86_L_0, | |
1556 | VEX_W_0FXOP_08_87_L_0, | |
1557 | VEX_W_0FXOP_08_8E_L_0, | |
1558 | VEX_W_0FXOP_08_8F_L_0, | |
1559 | VEX_W_0FXOP_08_95_L_0, | |
1560 | VEX_W_0FXOP_08_96_L_0, | |
1561 | VEX_W_0FXOP_08_97_L_0, | |
1562 | VEX_W_0FXOP_08_9E_L_0, | |
1563 | VEX_W_0FXOP_08_9F_L_0, | |
1564 | VEX_W_0FXOP_08_A6_L_0, | |
1565 | VEX_W_0FXOP_08_B6_L_0, | |
1566 | VEX_W_0FXOP_08_C0_L_0, | |
1567 | VEX_W_0FXOP_08_C1_L_0, | |
1568 | VEX_W_0FXOP_08_C2_L_0, | |
1569 | VEX_W_0FXOP_08_C3_L_0, | |
1570 | VEX_W_0FXOP_08_CC_L_0, | |
1571 | VEX_W_0FXOP_08_CD_L_0, | |
1572 | VEX_W_0FXOP_08_CE_L_0, | |
1573 | VEX_W_0FXOP_08_CF_L_0, | |
1574 | VEX_W_0FXOP_08_EC_L_0, | |
1575 | VEX_W_0FXOP_08_ED_L_0, | |
1576 | VEX_W_0FXOP_08_EE_L_0, | |
1577 | VEX_W_0FXOP_08_EF_L_0, | |
1578 | ||
b5b098c2 JB |
1579 | VEX_W_0FXOP_09_80, |
1580 | VEX_W_0FXOP_09_81, | |
1581 | VEX_W_0FXOP_09_82, | |
1582 | VEX_W_0FXOP_09_83, | |
467bbef0 JB |
1583 | VEX_W_0FXOP_09_C1_L_0, |
1584 | VEX_W_0FXOP_09_C2_L_0, | |
1585 | VEX_W_0FXOP_09_C3_L_0, | |
1586 | VEX_W_0FXOP_09_C6_L_0, | |
1587 | VEX_W_0FXOP_09_C7_L_0, | |
1588 | VEX_W_0FXOP_09_CB_L_0, | |
1589 | VEX_W_0FXOP_09_D1_L_0, | |
1590 | VEX_W_0FXOP_09_D2_L_0, | |
1591 | VEX_W_0FXOP_09_D3_L_0, | |
1592 | VEX_W_0FXOP_09_D6_L_0, | |
1593 | VEX_W_0FXOP_09_D7_L_0, | |
1594 | VEX_W_0FXOP_09_DB_L_0, | |
1595 | VEX_W_0FXOP_09_E1_L_0, | |
1596 | VEX_W_0FXOP_09_E2_L_0, | |
1597 | VEX_W_0FXOP_09_E3_L_0, | |
b5b098c2 | 1598 | |
36cc073e | 1599 | EVEX_W_0F10_P_1, |
36cc073e | 1600 | EVEX_W_0F10_P_3, |
36cc073e | 1601 | EVEX_W_0F11_P_1, |
36cc073e | 1602 | EVEX_W_0F11_P_3, |
43234a1e L |
1603 | EVEX_W_0F12_P_0_M_1, |
1604 | EVEX_W_0F12_P_1, | |
43234a1e | 1605 | EVEX_W_0F12_P_3, |
43234a1e L |
1606 | EVEX_W_0F16_P_0_M_1, |
1607 | EVEX_W_0F16_P_1, | |
43234a1e | 1608 | EVEX_W_0F2A_P_3, |
43234a1e | 1609 | EVEX_W_0F51_P_1, |
43234a1e | 1610 | EVEX_W_0F51_P_3, |
43234a1e | 1611 | EVEX_W_0F58_P_1, |
43234a1e | 1612 | EVEX_W_0F58_P_3, |
43234a1e | 1613 | EVEX_W_0F59_P_1, |
43234a1e L |
1614 | EVEX_W_0F59_P_3, |
1615 | EVEX_W_0F5A_P_0, | |
1616 | EVEX_W_0F5A_P_1, | |
1617 | EVEX_W_0F5A_P_2, | |
1618 | EVEX_W_0F5A_P_3, | |
1619 | EVEX_W_0F5B_P_0, | |
1620 | EVEX_W_0F5B_P_1, | |
1621 | EVEX_W_0F5B_P_2, | |
43234a1e | 1622 | EVEX_W_0F5C_P_1, |
43234a1e | 1623 | EVEX_W_0F5C_P_3, |
43234a1e | 1624 | EVEX_W_0F5D_P_1, |
43234a1e | 1625 | EVEX_W_0F5D_P_3, |
43234a1e | 1626 | EVEX_W_0F5E_P_1, |
43234a1e | 1627 | EVEX_W_0F5E_P_3, |
43234a1e | 1628 | EVEX_W_0F5F_P_1, |
43234a1e | 1629 | EVEX_W_0F5F_P_3, |
fedfb81e | 1630 | EVEX_W_0F62, |
7531c613 | 1631 | EVEX_W_0F66, |
fedfb81e JB |
1632 | EVEX_W_0F6A, |
1633 | EVEX_W_0F6B, | |
1634 | EVEX_W_0F6C, | |
1635 | EVEX_W_0F6D, | |
43234a1e L |
1636 | EVEX_W_0F6F_P_1, |
1637 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1638 | EVEX_W_0F6F_P_3, |
43234a1e | 1639 | EVEX_W_0F70_P_2, |
7531c613 JB |
1640 | EVEX_W_0F72_R_2, |
1641 | EVEX_W_0F72_R_6, | |
1642 | EVEX_W_0F73_R_2, | |
1643 | EVEX_W_0F73_R_6, | |
1644 | EVEX_W_0F76, | |
43234a1e | 1645 | EVEX_W_0F78_P_0, |
90a915bf | 1646 | EVEX_W_0F78_P_2, |
43234a1e | 1647 | EVEX_W_0F79_P_0, |
90a915bf | 1648 | EVEX_W_0F79_P_2, |
43234a1e | 1649 | EVEX_W_0F7A_P_1, |
90a915bf | 1650 | EVEX_W_0F7A_P_2, |
43234a1e | 1651 | EVEX_W_0F7A_P_3, |
90a915bf | 1652 | EVEX_W_0F7B_P_2, |
43234a1e L |
1653 | EVEX_W_0F7B_P_3, |
1654 | EVEX_W_0F7E_P_1, | |
43234a1e L |
1655 | EVEX_W_0F7F_P_1, |
1656 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 1657 | EVEX_W_0F7F_P_3, |
43234a1e | 1658 | EVEX_W_0FC2_P_1, |
43234a1e | 1659 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
1660 | EVEX_W_0FD2, |
1661 | EVEX_W_0FD3, | |
1662 | EVEX_W_0FD4, | |
7531c613 | 1663 | EVEX_W_0FD6_L_0, |
43234a1e L |
1664 | EVEX_W_0FE6_P_1, |
1665 | EVEX_W_0FE6_P_2, | |
1666 | EVEX_W_0FE6_P_3, | |
7531c613 | 1667 | EVEX_W_0FE7, |
fedfb81e JB |
1668 | EVEX_W_0FF2, |
1669 | EVEX_W_0FF3, | |
1670 | EVEX_W_0FF4, | |
1671 | EVEX_W_0FFA, | |
1672 | EVEX_W_0FFB, | |
1673 | EVEX_W_0FFE, | |
7531c613 | 1674 | EVEX_W_0F380D, |
1ba585e8 IT |
1675 | EVEX_W_0F3810_P_1, |
1676 | EVEX_W_0F3810_P_2, | |
43234a1e | 1677 | EVEX_W_0F3811_P_1, |
1ba585e8 | 1678 | EVEX_W_0F3811_P_2, |
43234a1e | 1679 | EVEX_W_0F3812_P_1, |
1ba585e8 | 1680 | EVEX_W_0F3812_P_2, |
43234a1e L |
1681 | EVEX_W_0F3813_P_1, |
1682 | EVEX_W_0F3813_P_2, | |
1683 | EVEX_W_0F3814_P_1, | |
1684 | EVEX_W_0F3815_P_1, | |
7531c613 JB |
1685 | EVEX_W_0F3819, |
1686 | EVEX_W_0F381A, | |
1687 | EVEX_W_0F381B, | |
1688 | EVEX_W_0F381E, | |
1689 | EVEX_W_0F381F, | |
1ba585e8 | 1690 | EVEX_W_0F3820_P_1, |
43234a1e L |
1691 | EVEX_W_0F3821_P_1, |
1692 | EVEX_W_0F3822_P_1, | |
1693 | EVEX_W_0F3823_P_1, | |
1694 | EVEX_W_0F3824_P_1, | |
1695 | EVEX_W_0F3825_P_1, | |
1696 | EVEX_W_0F3825_P_2, | |
1697 | EVEX_W_0F3828_P_2, | |
1698 | EVEX_W_0F3829_P_2, | |
1699 | EVEX_W_0F382A_P_1, | |
1700 | EVEX_W_0F382A_P_2, | |
fedfb81e | 1701 | EVEX_W_0F382B, |
1ba585e8 | 1702 | EVEX_W_0F3830_P_1, |
43234a1e L |
1703 | EVEX_W_0F3831_P_1, |
1704 | EVEX_W_0F3832_P_1, | |
1705 | EVEX_W_0F3833_P_1, | |
1706 | EVEX_W_0F3834_P_1, | |
1707 | EVEX_W_0F3835_P_1, | |
1708 | EVEX_W_0F3835_P_2, | |
7531c613 | 1709 | EVEX_W_0F3837, |
43234a1e | 1710 | EVEX_W_0F383A_P_1, |
d6aab7a1 | 1711 | EVEX_W_0F3852_P_1, |
7531c613 JB |
1712 | EVEX_W_0F3859, |
1713 | EVEX_W_0F385A, | |
1714 | EVEX_W_0F385B, | |
1715 | EVEX_W_0F3870, | |
d6aab7a1 | 1716 | EVEX_W_0F3872_P_1, |
53467f57 | 1717 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 1718 | EVEX_W_0F3872_P_3, |
7531c613 JB |
1719 | EVEX_W_0F387A, |
1720 | EVEX_W_0F387B, | |
1721 | EVEX_W_0F3883, | |
1722 | EVEX_W_0F3891, | |
1723 | EVEX_W_0F3893, | |
1724 | EVEX_W_0F38A1, | |
1725 | EVEX_W_0F38A3, | |
1726 | EVEX_W_0F38C7_R_1_M_0, | |
1727 | EVEX_W_0F38C7_R_2_M_0, | |
1728 | EVEX_W_0F38C7_R_5_M_0, | |
1729 | EVEX_W_0F38C7_R_6_M_0, | |
1730 | ||
1731 | EVEX_W_0F3A00, | |
1732 | EVEX_W_0F3A01, | |
1733 | EVEX_W_0F3A05, | |
1734 | EVEX_W_0F3A08, | |
1735 | EVEX_W_0F3A09, | |
1736 | EVEX_W_0F3A0A, | |
1737 | EVEX_W_0F3A0B, | |
1738 | EVEX_W_0F3A18, | |
1739 | EVEX_W_0F3A19, | |
1740 | EVEX_W_0F3A1A, | |
1741 | EVEX_W_0F3A1B, | |
1742 | EVEX_W_0F3A21, | |
1743 | EVEX_W_0F3A23, | |
1744 | EVEX_W_0F3A38, | |
1745 | EVEX_W_0F3A39, | |
1746 | EVEX_W_0F3A3A, | |
1747 | EVEX_W_0F3A3B, | |
1748 | EVEX_W_0F3A42, | |
1749 | EVEX_W_0F3A43, | |
1750 | EVEX_W_0F3A70, | |
1751 | EVEX_W_0F3A72, | |
9e30b8e0 L |
1752 | }; |
1753 | ||
26ca5450 | 1754 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1755 | |
1756 | struct dis386 { | |
2da11e11 | 1757 | const char *name; |
ce518a5f L |
1758 | struct |
1759 | { | |
1760 | op_rtn rtn; | |
1761 | int bytemode; | |
1762 | } op[MAX_OPERANDS]; | |
bf890a93 | 1763 | unsigned int prefix_requirement; |
252b5132 RH |
1764 | }; |
1765 | ||
1766 | /* Upper case letters in the instruction names here are macros. | |
1767 | 'A' => print 'b' if no register operands or suffix_always is true | |
1768 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1769 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1770 | size prefix |
ed7841b3 | 1771 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1772 | suffix_always is true |
252b5132 | 1773 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1774 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1775 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1776 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 1777 | 'I' unused. |
8f570d62 | 1778 | 'J' unused. |
42903f7f | 1779 | 'K' => print 'd' or 'q' if rex prefix is present. |
78467458 | 1780 | 'L' unused. |
9d141669 | 1781 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1782 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1783 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
36938cab JB |
1784 | 'P' => behave as 'T' except with register operand outside of suffix_always |
1785 | mode | |
98b528ac L |
1786 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
1787 | is true | |
a35ca55a | 1788 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1789 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
36938cab JB |
1790 | 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size |
1791 | prefix or if suffix_always is true. | |
1792 | 'U' unused. | |
c3f5525f | 1793 | 'V' unused. |
a35ca55a | 1794 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1795 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 1796 | 'Y' unused. |
78467458 | 1797 | 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true. |
9d141669 | 1798 | '!' => change condition from true to false or from false to true. |
98b528ac | 1799 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
1800 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
1801 | prefix or suffix_always is true (lcall/ljmp). | |
36938cab JB |
1802 | '@' => in 64bit mode for Intel64 ISA or if instruction |
1803 | has no operand sizing prefix, print 'q' if suffix_always is true or | |
1804 | nothing otherwise; behave as 'P' in all other cases | |
98b528ac L |
1805 | |
1806 | 2 upper case letter macros: | |
04d824a4 JB |
1807 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
1808 | operands and no broadcast. | |
1809 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
1810 | register operands and no broadcast. | |
4b06377f | 1811 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
58bf9b6a | 1812 | "XV" => print "{vex3}" pseudo prefix |
b24d668c JB |
1813 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond |
1814 | being false, or no operand at all in 64bit mode, or if suffix_always | |
589958d6 | 1815 | is true. |
4b06377f L |
1816 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1817 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1818 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
492a76aa | 1819 | "DQ" => print 'd' or 'q' depending on the VEX.W bit |
bb5b3501 | 1820 | "BW" => print 'b' or 'w' depending on the VEX.W bit |
4b4c407a L |
1821 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
1822 | an operand size prefix, or suffix_always is true. print | |
1823 | 'q' if rex prefix is present. | |
52b15da3 | 1824 | |
6439fc28 AM |
1825 | Many of the above letters print nothing in Intel mode. See "putop" |
1826 | for the details. | |
52b15da3 | 1827 | |
6439fc28 | 1828 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1829 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1830 | |
6439fc28 | 1831 | static const struct dis386 dis386[] = { |
252b5132 | 1832 | /* 00 */ |
bf890a93 IT |
1833 | { "addB", { Ebh1, Gb }, 0 }, |
1834 | { "addS", { Evh1, Gv }, 0 }, | |
1835 | { "addB", { Gb, EbS }, 0 }, | |
1836 | { "addS", { Gv, EvS }, 0 }, | |
1837 | { "addB", { AL, Ib }, 0 }, | |
1838 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1839 | { X86_64_TABLE (X86_64_06) }, |
1840 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1841 | /* 08 */ |
bf890a93 IT |
1842 | { "orB", { Ebh1, Gb }, 0 }, |
1843 | { "orS", { Evh1, Gv }, 0 }, | |
1844 | { "orB", { Gb, EbS }, 0 }, | |
1845 | { "orS", { Gv, EvS }, 0 }, | |
1846 | { "orB", { AL, Ib }, 0 }, | |
1847 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 1848 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 1849 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1850 | /* 10 */ |
bf890a93 IT |
1851 | { "adcB", { Ebh1, Gb }, 0 }, |
1852 | { "adcS", { Evh1, Gv }, 0 }, | |
1853 | { "adcB", { Gb, EbS }, 0 }, | |
1854 | { "adcS", { Gv, EvS }, 0 }, | |
1855 | { "adcB", { AL, Ib }, 0 }, | |
1856 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1857 | { X86_64_TABLE (X86_64_16) }, |
1858 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1859 | /* 18 */ |
bf890a93 IT |
1860 | { "sbbB", { Ebh1, Gb }, 0 }, |
1861 | { "sbbS", { Evh1, Gv }, 0 }, | |
1862 | { "sbbB", { Gb, EbS }, 0 }, | |
1863 | { "sbbS", { Gv, EvS }, 0 }, | |
1864 | { "sbbB", { AL, Ib }, 0 }, | |
1865 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1866 | { X86_64_TABLE (X86_64_1E) }, |
1867 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1868 | /* 20 */ |
bf890a93 IT |
1869 | { "andB", { Ebh1, Gb }, 0 }, |
1870 | { "andS", { Evh1, Gv }, 0 }, | |
1871 | { "andB", { Gb, EbS }, 0 }, | |
1872 | { "andS", { Gv, EvS }, 0 }, | |
1873 | { "andB", { AL, Ib }, 0 }, | |
1874 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 1875 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1876 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1877 | /* 28 */ |
bf890a93 IT |
1878 | { "subB", { Ebh1, Gb }, 0 }, |
1879 | { "subS", { Evh1, Gv }, 0 }, | |
1880 | { "subB", { Gb, EbS }, 0 }, | |
1881 | { "subS", { Gv, EvS }, 0 }, | |
1882 | { "subB", { AL, Ib }, 0 }, | |
1883 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 1884 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1885 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1886 | /* 30 */ |
bf890a93 IT |
1887 | { "xorB", { Ebh1, Gb }, 0 }, |
1888 | { "xorS", { Evh1, Gv }, 0 }, | |
1889 | { "xorB", { Gb, EbS }, 0 }, | |
1890 | { "xorS", { Gv, EvS }, 0 }, | |
1891 | { "xorB", { AL, Ib }, 0 }, | |
1892 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 1893 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1894 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1895 | /* 38 */ |
bf890a93 IT |
1896 | { "cmpB", { Eb, Gb }, 0 }, |
1897 | { "cmpS", { Ev, Gv }, 0 }, | |
1898 | { "cmpB", { Gb, EbS }, 0 }, | |
1899 | { "cmpS", { Gv, EvS }, 0 }, | |
1900 | { "cmpB", { AL, Ib }, 0 }, | |
1901 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 1902 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1903 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1904 | /* 40 */ |
bf890a93 IT |
1905 | { "inc{S|}", { RMeAX }, 0 }, |
1906 | { "inc{S|}", { RMeCX }, 0 }, | |
1907 | { "inc{S|}", { RMeDX }, 0 }, | |
1908 | { "inc{S|}", { RMeBX }, 0 }, | |
1909 | { "inc{S|}", { RMeSP }, 0 }, | |
1910 | { "inc{S|}", { RMeBP }, 0 }, | |
1911 | { "inc{S|}", { RMeSI }, 0 }, | |
1912 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 1913 | /* 48 */ |
bf890a93 IT |
1914 | { "dec{S|}", { RMeAX }, 0 }, |
1915 | { "dec{S|}", { RMeCX }, 0 }, | |
1916 | { "dec{S|}", { RMeDX }, 0 }, | |
1917 | { "dec{S|}", { RMeBX }, 0 }, | |
1918 | { "dec{S|}", { RMeSP }, 0 }, | |
1919 | { "dec{S|}", { RMeBP }, 0 }, | |
1920 | { "dec{S|}", { RMeSI }, 0 }, | |
1921 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 1922 | /* 50 */ |
c3f5525f JB |
1923 | { "push{!P|}", { RMrAX }, 0 }, |
1924 | { "push{!P|}", { RMrCX }, 0 }, | |
1925 | { "push{!P|}", { RMrDX }, 0 }, | |
1926 | { "push{!P|}", { RMrBX }, 0 }, | |
1927 | { "push{!P|}", { RMrSP }, 0 }, | |
1928 | { "push{!P|}", { RMrBP }, 0 }, | |
1929 | { "push{!P|}", { RMrSI }, 0 }, | |
1930 | { "push{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1931 | /* 58 */ |
c3f5525f JB |
1932 | { "pop{!P|}", { RMrAX }, 0 }, |
1933 | { "pop{!P|}", { RMrCX }, 0 }, | |
1934 | { "pop{!P|}", { RMrDX }, 0 }, | |
1935 | { "pop{!P|}", { RMrBX }, 0 }, | |
1936 | { "pop{!P|}", { RMrSP }, 0 }, | |
1937 | { "pop{!P|}", { RMrBP }, 0 }, | |
1938 | { "pop{!P|}", { RMrSI }, 0 }, | |
1939 | { "pop{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1940 | /* 60 */ |
4e7d34a6 L |
1941 | { X86_64_TABLE (X86_64_60) }, |
1942 | { X86_64_TABLE (X86_64_61) }, | |
1943 | { X86_64_TABLE (X86_64_62) }, | |
1944 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1945 | { Bad_Opcode }, /* seg fs */ |
1946 | { Bad_Opcode }, /* seg gs */ | |
1947 | { Bad_Opcode }, /* op size prefix */ | |
1948 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1949 | /* 68 */ |
36938cab | 1950 | { "pushP", { sIv }, 0 }, |
bf890a93 | 1951 | { "imulS", { Gv, Ev, Iv }, 0 }, |
36938cab | 1952 | { "pushP", { sIbT }, 0 }, |
bf890a93 IT |
1953 | { "imulS", { Gv, Ev, sIb }, 0 }, |
1954 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 1955 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 1956 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 1957 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1958 | /* 70 */ |
bf890a93 IT |
1959 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
1960 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
1961 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
1962 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1963 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1964 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
1965 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1966 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1967 | /* 78 */ |
bf890a93 IT |
1968 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
1969 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
1970 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1971 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1972 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
1973 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1974 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
1975 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1976 | /* 80 */ |
1ceb70f8 L |
1977 | { REG_TABLE (REG_80) }, |
1978 | { REG_TABLE (REG_81) }, | |
d039fef3 | 1979 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 1980 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
1981 | { "testB", { Eb, Gb }, 0 }, |
1982 | { "testS", { Ev, Gv }, 0 }, | |
1983 | { "xchgB", { Ebh2, Gb }, 0 }, | |
1984 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 1985 | /* 88 */ |
bf890a93 IT |
1986 | { "movB", { Ebh3, Gb }, 0 }, |
1987 | { "movS", { Evh3, Gv }, 0 }, | |
1988 | { "movB", { Gb, EbS }, 0 }, | |
1989 | { "movS", { Gv, EvS }, 0 }, | |
1990 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 1991 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 1992 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 1993 | { REG_TABLE (REG_8F) }, |
252b5132 | 1994 | /* 90 */ |
1ceb70f8 | 1995 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
1996 | { "xchgS", { RMeCX, eAX }, 0 }, |
1997 | { "xchgS", { RMeDX, eAX }, 0 }, | |
1998 | { "xchgS", { RMeBX, eAX }, 0 }, | |
1999 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2000 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2001 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2002 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2003 | /* 98 */ |
bf890a93 IT |
2004 | { "cW{t|}R", { XX }, 0 }, |
2005 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2006 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2007 | { Bad_Opcode }, /* fwait */ |
36938cab JB |
2008 | { "pushfP", { XX }, 0 }, |
2009 | { "popfP", { XX }, 0 }, | |
bf890a93 IT |
2010 | { "sahf", { XX }, 0 }, |
2011 | { "lahf", { XX }, 0 }, | |
252b5132 | 2012 | /* a0 */ |
bf890a93 IT |
2013 | { "mov%LB", { AL, Ob }, 0 }, |
2014 | { "mov%LS", { eAX, Ov }, 0 }, | |
2015 | { "mov%LB", { Ob, AL }, 0 }, | |
2016 | { "mov%LS", { Ov, eAX }, 0 }, | |
2017 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2018 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2019 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2020 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2021 | /* a8 */ |
bf890a93 IT |
2022 | { "testB", { AL, Ib }, 0 }, |
2023 | { "testS", { eAX, Iv }, 0 }, | |
2024 | { "stosB", { Ybr, AL }, 0 }, | |
2025 | { "stosS", { Yvr, eAX }, 0 }, | |
2026 | { "lodsB", { ALr, Xb }, 0 }, | |
2027 | { "lodsS", { eAXr, Xv }, 0 }, | |
2028 | { "scasB", { AL, Yb }, 0 }, | |
2029 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2030 | /* b0 */ |
bf890a93 IT |
2031 | { "movB", { RMAL, Ib }, 0 }, |
2032 | { "movB", { RMCL, Ib }, 0 }, | |
2033 | { "movB", { RMDL, Ib }, 0 }, | |
2034 | { "movB", { RMBL, Ib }, 0 }, | |
2035 | { "movB", { RMAH, Ib }, 0 }, | |
2036 | { "movB", { RMCH, Ib }, 0 }, | |
2037 | { "movB", { RMDH, Ib }, 0 }, | |
2038 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2039 | /* b8 */ |
bf890a93 IT |
2040 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2041 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2042 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2043 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2044 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2045 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2046 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2047 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2048 | /* c0 */ |
1ceb70f8 L |
2049 | { REG_TABLE (REG_C0) }, |
2050 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2051 | { X86_64_TABLE (X86_64_C2) }, |
2052 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2053 | { X86_64_TABLE (X86_64_C4) }, |
2054 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2055 | { REG_TABLE (REG_C6) }, |
2056 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2057 | /* c8 */ |
36938cab JB |
2058 | { "enterP", { Iw, Ib }, 0 }, |
2059 | { "leaveP", { XX }, 0 }, | |
2060 | { "{l|}ret{|f}%LP", { Iw }, 0 }, | |
2061 | { "{l|}ret{|f}%LP", { XX }, 0 }, | |
bf890a93 IT |
2062 | { "int3", { XX }, 0 }, |
2063 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2064 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2065 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2066 | /* d0 */ |
1ceb70f8 L |
2067 | { REG_TABLE (REG_D0) }, |
2068 | { REG_TABLE (REG_D1) }, | |
2069 | { REG_TABLE (REG_D2) }, | |
2070 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2071 | { X86_64_TABLE (X86_64_D4) }, |
2072 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2073 | { Bad_Opcode }, |
bf890a93 | 2074 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2075 | /* d8 */ |
2076 | { FLOAT }, | |
2077 | { FLOAT }, | |
2078 | { FLOAT }, | |
2079 | { FLOAT }, | |
2080 | { FLOAT }, | |
2081 | { FLOAT }, | |
2082 | { FLOAT }, | |
2083 | { FLOAT }, | |
2084 | /* e0 */ | |
bf890a93 IT |
2085 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2086 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2087 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2088 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2089 | { "inB", { AL, Ib }, 0 }, | |
2090 | { "inG", { zAX, Ib }, 0 }, | |
2091 | { "outB", { Ib, AL }, 0 }, | |
2092 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2093 | /* e8 */ |
a72d2af2 L |
2094 | { X86_64_TABLE (X86_64_E8) }, |
2095 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2096 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2097 | { "jmp", { Jb, BND }, 0 }, |
2098 | { "inB", { AL, indirDX }, 0 }, | |
2099 | { "inG", { zAX, indirDX }, 0 }, | |
2100 | { "outB", { indirDX, AL }, 0 }, | |
2101 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2102 | /* f0 */ |
592d1631 | 2103 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2104 | { "icebp", { XX }, 0 }, |
592d1631 L |
2105 | { Bad_Opcode }, /* repne */ |
2106 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2107 | { "hlt", { XX }, 0 }, |
2108 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2109 | { REG_TABLE (REG_F6) }, |
2110 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2111 | /* f8 */ |
bf890a93 IT |
2112 | { "clc", { XX }, 0 }, |
2113 | { "stc", { XX }, 0 }, | |
2114 | { "cli", { XX }, 0 }, | |
2115 | { "sti", { XX }, 0 }, | |
2116 | { "cld", { XX }, 0 }, | |
2117 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2118 | { REG_TABLE (REG_FE) }, |
2119 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2120 | }; |
2121 | ||
6439fc28 | 2122 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2123 | /* 00 */ |
1ceb70f8 L |
2124 | { REG_TABLE (REG_0F00 ) }, |
2125 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2126 | { "larS", { Gv, Ew }, 0 }, |
2127 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2128 | { Bad_Opcode }, |
bf890a93 IT |
2129 | { "syscall", { XX }, 0 }, |
2130 | { "clts", { XX }, 0 }, | |
589958d6 | 2131 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2132 | /* 08 */ |
bf890a93 | 2133 | { "invd", { XX }, 0 }, |
3233d7d0 | 2134 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2135 | { Bad_Opcode }, |
bf890a93 | 2136 | { "ud2", { XX }, 0 }, |
592d1631 | 2137 | { Bad_Opcode }, |
b5b1fc4f | 2138 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2139 | { "femms", { XX }, 0 }, |
2140 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2141 | /* 10 */ |
1ceb70f8 L |
2142 | { PREFIX_TABLE (PREFIX_0F10) }, |
2143 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2144 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2145 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2146 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2147 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2148 | { PREFIX_TABLE (PREFIX_0F16) }, |
2149 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2150 | /* 18 */ |
1ceb70f8 | 2151 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2152 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2153 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2154 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2155 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2156 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2157 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2158 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2159 | /* 20 */ |
78467458 JB |
2160 | { "movZ", { Em, Cm }, 0 }, |
2161 | { "movZ", { Em, Dm }, 0 }, | |
2162 | { "movZ", { Cm, Em }, 0 }, | |
2163 | { "movZ", { Dm, Em }, 0 }, | |
2164 | { X86_64_TABLE (X86_64_0F24) }, | |
592d1631 | 2165 | { Bad_Opcode }, |
78467458 | 2166 | { X86_64_TABLE (X86_64_0F26) }, |
592d1631 | 2167 | { Bad_Opcode }, |
252b5132 | 2168 | /* 28 */ |
507bd325 L |
2169 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2170 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2171 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2172 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2173 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2174 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2175 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2176 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2177 | /* 30 */ |
bf890a93 IT |
2178 | { "wrmsr", { XX }, 0 }, |
2179 | { "rdtsc", { XX }, 0 }, | |
2180 | { "rdmsr", { XX }, 0 }, | |
2181 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2182 | { "sysenter", { SEP }, 0 }, |
2183 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2184 | { Bad_Opcode }, |
bf890a93 | 2185 | { "getsec", { XX }, 0 }, |
252b5132 | 2186 | /* 38 */ |
507bd325 | 2187 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2188 | { Bad_Opcode }, |
507bd325 | 2189 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2190 | { Bad_Opcode }, |
2191 | { Bad_Opcode }, | |
2192 | { Bad_Opcode }, | |
2193 | { Bad_Opcode }, | |
2194 | { Bad_Opcode }, | |
252b5132 | 2195 | /* 40 */ |
bf890a93 IT |
2196 | { "cmovoS", { Gv, Ev }, 0 }, |
2197 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2198 | { "cmovbS", { Gv, Ev }, 0 }, | |
2199 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2200 | { "cmoveS", { Gv, Ev }, 0 }, | |
2201 | { "cmovneS", { Gv, Ev }, 0 }, | |
2202 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2203 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2204 | /* 48 */ |
bf890a93 IT |
2205 | { "cmovsS", { Gv, Ev }, 0 }, |
2206 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2207 | { "cmovpS", { Gv, Ev }, 0 }, | |
2208 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2209 | { "cmovlS", { Gv, Ev }, 0 }, | |
2210 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2211 | { "cmovleS", { Gv, Ev }, 0 }, | |
2212 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2213 | /* 50 */ |
a5aaedb9 | 2214 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2215 | { PREFIX_TABLE (PREFIX_0F51) }, |
2216 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2217 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2218 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2219 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2220 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2221 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2222 | /* 58 */ |
1ceb70f8 L |
2223 | { PREFIX_TABLE (PREFIX_0F58) }, |
2224 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2225 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2226 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2227 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2228 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2229 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2230 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2231 | /* 60 */ |
1ceb70f8 L |
2232 | { PREFIX_TABLE (PREFIX_0F60) }, |
2233 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2234 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2235 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2236 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2237 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2238 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2239 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2240 | /* 68 */ |
507bd325 L |
2241 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2242 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2243 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2244 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
7531c613 JB |
2245 | { "punpcklqdq", { XM, EXx }, PREFIX_DATA }, |
2246 | { "punpckhqdq", { XM, EXx }, PREFIX_DATA }, | |
507bd325 | 2247 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2248 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2249 | /* 70 */ |
1ceb70f8 L |
2250 | { PREFIX_TABLE (PREFIX_0F70) }, |
2251 | { REG_TABLE (REG_0F71) }, | |
2252 | { REG_TABLE (REG_0F72) }, | |
2253 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2254 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2255 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2256 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2257 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2258 | /* 78 */ |
1ceb70f8 L |
2259 | { PREFIX_TABLE (PREFIX_0F78) }, |
2260 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2261 | { Bad_Opcode }, |
592d1631 | 2262 | { Bad_Opcode }, |
1ceb70f8 L |
2263 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2264 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2265 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2266 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2267 | /* 80 */ |
bf890a93 IT |
2268 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2269 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2270 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2271 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2272 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2273 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2274 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2275 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2276 | /* 88 */ |
bf890a93 IT |
2277 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2278 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2279 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2280 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2281 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2282 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2283 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2284 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2285 | /* 90 */ |
bf890a93 IT |
2286 | { "seto", { Eb }, 0 }, |
2287 | { "setno", { Eb }, 0 }, | |
2288 | { "setb", { Eb }, 0 }, | |
2289 | { "setae", { Eb }, 0 }, | |
2290 | { "sete", { Eb }, 0 }, | |
2291 | { "setne", { Eb }, 0 }, | |
2292 | { "setbe", { Eb }, 0 }, | |
2293 | { "seta", { Eb }, 0 }, | |
252b5132 | 2294 | /* 98 */ |
bf890a93 IT |
2295 | { "sets", { Eb }, 0 }, |
2296 | { "setns", { Eb }, 0 }, | |
2297 | { "setp", { Eb }, 0 }, | |
2298 | { "setnp", { Eb }, 0 }, | |
2299 | { "setl", { Eb }, 0 }, | |
2300 | { "setge", { Eb }, 0 }, | |
2301 | { "setle", { Eb }, 0 }, | |
2302 | { "setg", { Eb }, 0 }, | |
252b5132 | 2303 | /* a0 */ |
36938cab JB |
2304 | { "pushP", { fs }, 0 }, |
2305 | { "popP", { fs }, 0 }, | |
bf890a93 IT |
2306 | { "cpuid", { XX }, 0 }, |
2307 | { "btS", { Ev, Gv }, 0 }, | |
2308 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2309 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2310 | { REG_TABLE (REG_0FA6) }, |
2311 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2312 | /* a8 */ |
36938cab JB |
2313 | { "pushP", { gs }, 0 }, |
2314 | { "popP", { gs }, 0 }, | |
bf890a93 IT |
2315 | { "rsm", { XX }, 0 }, |
2316 | { "btsS", { Evh1, Gv }, 0 }, | |
2317 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2318 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2319 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2320 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2321 | /* b0 */ |
bf890a93 IT |
2322 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2323 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2324 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2325 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2326 | { MOD_TABLE (MOD_0FB4) }, |
2327 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2328 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2329 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2330 | /* b8 */ |
1ceb70f8 | 2331 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2332 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2333 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2334 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2335 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2336 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2337 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2338 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2339 | /* c0 */ |
bf890a93 IT |
2340 | { "xaddB", { Ebh1, Gb }, 0 }, |
2341 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2342 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2343 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2344 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2345 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2346 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2347 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2348 | /* c8 */ |
bf890a93 IT |
2349 | { "bswap", { RMeAX }, 0 }, |
2350 | { "bswap", { RMeCX }, 0 }, | |
2351 | { "bswap", { RMeDX }, 0 }, | |
2352 | { "bswap", { RMeBX }, 0 }, | |
2353 | { "bswap", { RMeSP }, 0 }, | |
2354 | { "bswap", { RMeBP }, 0 }, | |
2355 | { "bswap", { RMeSI }, 0 }, | |
2356 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2357 | /* d0 */ |
1ceb70f8 | 2358 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2359 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2360 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2361 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2362 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2363 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2364 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2365 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2366 | /* d8 */ |
507bd325 L |
2367 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2368 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2369 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2370 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2371 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2372 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2373 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2374 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2375 | /* e0 */ |
507bd325 L |
2376 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2377 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2378 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2379 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2380 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2381 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2382 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2383 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2384 | /* e8 */ |
507bd325 L |
2385 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2386 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2387 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2388 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2389 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2390 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2391 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2392 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2393 | /* f0 */ |
1ceb70f8 | 2394 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2395 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2396 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2397 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2398 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2399 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2400 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2401 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2402 | /* f8 */ |
507bd325 L |
2403 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2404 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2405 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2406 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2407 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2408 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2409 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2410 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2411 | }; |
2412 | ||
2413 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2414 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2415 | /* ------------------------------- */ | |
2416 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2417 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2418 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2419 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2420 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2421 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2422 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2423 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2424 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2425 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2426 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2427 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2428 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2429 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2430 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2431 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2432 | /* ------------------------------- */ | |
2433 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2434 | }; |
2435 | ||
2436 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2437 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2438 | /* ------------------------------- */ | |
252b5132 | 2439 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2440 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2441 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2442 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2443 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2444 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2445 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2446 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2447 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2448 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2449 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2450 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2451 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2452 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2453 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2454 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2455 | /* ------------------------------- */ |
2456 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2457 | }; | |
2458 | ||
252b5132 RH |
2459 | static char obuf[100]; |
2460 | static char *obufp; | |
ea397f5b | 2461 | static char *mnemonicendp; |
252b5132 RH |
2462 | static char scratchbuf[100]; |
2463 | static unsigned char *start_codep; | |
2464 | static unsigned char *insn_codep; | |
2465 | static unsigned char *codep; | |
285ca992 | 2466 | static unsigned char *end_codep; |
f16cd0d5 L |
2467 | static int last_lock_prefix; |
2468 | static int last_repz_prefix; | |
2469 | static int last_repnz_prefix; | |
2470 | static int last_data_prefix; | |
2471 | static int last_addr_prefix; | |
2472 | static int last_rex_prefix; | |
2473 | static int last_seg_prefix; | |
d9949a36 | 2474 | static int fwait_prefix; |
285ca992 L |
2475 | /* The active segment register prefix. */ |
2476 | static int active_seg_prefix; | |
f16cd0d5 L |
2477 | #define MAX_CODE_LENGTH 15 |
2478 | /* We can up to 14 prefixes since the maximum instruction length is | |
2479 | 15bytes. */ | |
2480 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2481 | static disassemble_info *the_info; |
7967e09e L |
2482 | static struct |
2483 | { | |
2484 | int mod; | |
7967e09e | 2485 | int reg; |
484c222e | 2486 | int rm; |
7967e09e L |
2487 | } |
2488 | modrm; | |
4bba6815 | 2489 | static unsigned char need_modrm; |
dfc8cf43 L |
2490 | static struct |
2491 | { | |
2492 | int scale; | |
2493 | int index; | |
2494 | int base; | |
2495 | } | |
2496 | sib; | |
c0f3af97 L |
2497 | static struct |
2498 | { | |
2499 | int register_specifier; | |
2500 | int length; | |
2501 | int prefix; | |
2502 | int w; | |
43234a1e L |
2503 | int evex; |
2504 | int r; | |
2505 | int v; | |
2506 | int mask_register_specifier; | |
2507 | int zeroing; | |
2508 | int ll; | |
2509 | int b; | |
c0f3af97 L |
2510 | } |
2511 | vex; | |
2512 | static unsigned char need_vex; | |
252b5132 | 2513 | |
ea397f5b L |
2514 | struct op |
2515 | { | |
2516 | const char *name; | |
2517 | unsigned int len; | |
2518 | }; | |
2519 | ||
4bba6815 AM |
2520 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2521 | values are stale. Hitting this abort likely indicates that you | |
2522 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2523 | #define MODRM_CHECK if (!need_modrm) abort () | |
2524 | ||
d708bcba AM |
2525 | static const char **names64; |
2526 | static const char **names32; | |
2527 | static const char **names16; | |
2528 | static const char **names8; | |
2529 | static const char **names8rex; | |
2530 | static const char **names_seg; | |
db51cc60 L |
2531 | static const char *index64; |
2532 | static const char *index32; | |
d708bcba | 2533 | static const char **index16; |
7e8b059b | 2534 | static const char **names_bnd; |
d708bcba AM |
2535 | |
2536 | static const char *intel_names64[] = { | |
2537 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2538 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2539 | }; | |
2540 | static const char *intel_names32[] = { | |
2541 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2542 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2543 | }; | |
2544 | static const char *intel_names16[] = { | |
2545 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2546 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2547 | }; | |
2548 | static const char *intel_names8[] = { | |
2549 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2550 | }; | |
2551 | static const char *intel_names8rex[] = { | |
2552 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2553 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2554 | }; | |
2555 | static const char *intel_names_seg[] = { | |
2556 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2557 | }; | |
db51cc60 L |
2558 | static const char *intel_index64 = "riz"; |
2559 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2560 | static const char *intel_index16[] = { |
2561 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2562 | }; | |
2563 | ||
2564 | static const char *att_names64[] = { | |
2565 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2566 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2567 | }; | |
d708bcba AM |
2568 | static const char *att_names32[] = { |
2569 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2570 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2571 | }; |
d708bcba AM |
2572 | static const char *att_names16[] = { |
2573 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2574 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2575 | }; |
d708bcba AM |
2576 | static const char *att_names8[] = { |
2577 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2578 | }; |
d708bcba AM |
2579 | static const char *att_names8rex[] = { |
2580 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2581 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2582 | }; | |
d708bcba AM |
2583 | static const char *att_names_seg[] = { |
2584 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2585 | }; |
db51cc60 L |
2586 | static const char *att_index64 = "%riz"; |
2587 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2588 | static const char *att_index16[] = { |
2589 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2590 | }; |
2591 | ||
b9733481 L |
2592 | static const char **names_mm; |
2593 | static const char *intel_names_mm[] = { | |
2594 | "mm0", "mm1", "mm2", "mm3", | |
2595 | "mm4", "mm5", "mm6", "mm7" | |
2596 | }; | |
2597 | static const char *att_names_mm[] = { | |
2598 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2599 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2600 | }; | |
2601 | ||
7e8b059b L |
2602 | static const char *intel_names_bnd[] = { |
2603 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2604 | }; | |
2605 | ||
2606 | static const char *att_names_bnd[] = { | |
2607 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2608 | }; | |
2609 | ||
b9733481 L |
2610 | static const char **names_xmm; |
2611 | static const char *intel_names_xmm[] = { | |
2612 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2613 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2614 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
2615 | "xmm12", "xmm13", "xmm14", "xmm15", |
2616 | "xmm16", "xmm17", "xmm18", "xmm19", | |
2617 | "xmm20", "xmm21", "xmm22", "xmm23", | |
2618 | "xmm24", "xmm25", "xmm26", "xmm27", | |
2619 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
2620 | }; |
2621 | static const char *att_names_xmm[] = { | |
2622 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2623 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2624 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
2625 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
2626 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
2627 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
2628 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
2629 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
2630 | }; |
2631 | ||
2632 | static const char **names_ymm; | |
2633 | static const char *intel_names_ymm[] = { | |
2634 | "ymm0", "ymm1", "ymm2", "ymm3", | |
2635 | "ymm4", "ymm5", "ymm6", "ymm7", | |
2636 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
2637 | "ymm12", "ymm13", "ymm14", "ymm15", |
2638 | "ymm16", "ymm17", "ymm18", "ymm19", | |
2639 | "ymm20", "ymm21", "ymm22", "ymm23", | |
2640 | "ymm24", "ymm25", "ymm26", "ymm27", | |
2641 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
2642 | }; |
2643 | static const char *att_names_ymm[] = { | |
2644 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
2645 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2646 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
2647 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
2648 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
2649 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
2650 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
2651 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
2652 | }; | |
2653 | ||
2654 | static const char **names_zmm; | |
2655 | static const char *intel_names_zmm[] = { | |
2656 | "zmm0", "zmm1", "zmm2", "zmm3", | |
2657 | "zmm4", "zmm5", "zmm6", "zmm7", | |
2658 | "zmm8", "zmm9", "zmm10", "zmm11", | |
2659 | "zmm12", "zmm13", "zmm14", "zmm15", | |
2660 | "zmm16", "zmm17", "zmm18", "zmm19", | |
2661 | "zmm20", "zmm21", "zmm22", "zmm23", | |
2662 | "zmm24", "zmm25", "zmm26", "zmm27", | |
2663 | "zmm28", "zmm29", "zmm30", "zmm31" | |
2664 | }; | |
2665 | static const char *att_names_zmm[] = { | |
2666 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
2667 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
2668 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
2669 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
2670 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
2671 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
2672 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
2673 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
2674 | }; | |
2675 | ||
260cd341 LC |
2676 | static const char **names_tmm; |
2677 | static const char *intel_names_tmm[] = { | |
2678 | "tmm0", "tmm1", "tmm2", "tmm3", | |
2679 | "tmm4", "tmm5", "tmm6", "tmm7" | |
2680 | }; | |
2681 | static const char *att_names_tmm[] = { | |
2682 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", | |
2683 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
2684 | }; | |
2685 | ||
43234a1e L |
2686 | static const char **names_mask; |
2687 | static const char *intel_names_mask[] = { | |
2688 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
2689 | }; | |
2690 | static const char *att_names_mask[] = { | |
2691 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
2692 | }; | |
2693 | ||
2694 | static const char *names_rounding[] = | |
2695 | { | |
2696 | "{rn-sae}", | |
2697 | "{rd-sae}", | |
2698 | "{ru-sae}", | |
2699 | "{rz-sae}" | |
b9733481 L |
2700 | }; |
2701 | ||
1ceb70f8 L |
2702 | static const struct dis386 reg_table[][8] = { |
2703 | /* REG_80 */ | |
252b5132 | 2704 | { |
bf890a93 IT |
2705 | { "addA", { Ebh1, Ib }, 0 }, |
2706 | { "orA", { Ebh1, Ib }, 0 }, | |
2707 | { "adcA", { Ebh1, Ib }, 0 }, | |
2708 | { "sbbA", { Ebh1, Ib }, 0 }, | |
2709 | { "andA", { Ebh1, Ib }, 0 }, | |
2710 | { "subA", { Ebh1, Ib }, 0 }, | |
2711 | { "xorA", { Ebh1, Ib }, 0 }, | |
2712 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 2713 | }, |
1ceb70f8 | 2714 | /* REG_81 */ |
252b5132 | 2715 | { |
bf890a93 IT |
2716 | { "addQ", { Evh1, Iv }, 0 }, |
2717 | { "orQ", { Evh1, Iv }, 0 }, | |
2718 | { "adcQ", { Evh1, Iv }, 0 }, | |
2719 | { "sbbQ", { Evh1, Iv }, 0 }, | |
2720 | { "andQ", { Evh1, Iv }, 0 }, | |
2721 | { "subQ", { Evh1, Iv }, 0 }, | |
2722 | { "xorQ", { Evh1, Iv }, 0 }, | |
2723 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 2724 | }, |
7148c369 | 2725 | /* REG_83 */ |
252b5132 | 2726 | { |
bf890a93 IT |
2727 | { "addQ", { Evh1, sIb }, 0 }, |
2728 | { "orQ", { Evh1, sIb }, 0 }, | |
2729 | { "adcQ", { Evh1, sIb }, 0 }, | |
2730 | { "sbbQ", { Evh1, sIb }, 0 }, | |
2731 | { "andQ", { Evh1, sIb }, 0 }, | |
2732 | { "subQ", { Evh1, sIb }, 0 }, | |
2733 | { "xorQ", { Evh1, sIb }, 0 }, | |
2734 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 2735 | }, |
1ceb70f8 | 2736 | /* REG_8F */ |
4e7d34a6 | 2737 | { |
36938cab | 2738 | { "pop{P|}", { stackEv }, 0 }, |
c48244a5 | 2739 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
2740 | { Bad_Opcode }, |
2741 | { Bad_Opcode }, | |
2742 | { Bad_Opcode }, | |
f88c9eb0 | 2743 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 2744 | }, |
1ceb70f8 | 2745 | /* REG_C0 */ |
252b5132 | 2746 | { |
bf890a93 IT |
2747 | { "rolA", { Eb, Ib }, 0 }, |
2748 | { "rorA", { Eb, Ib }, 0 }, | |
2749 | { "rclA", { Eb, Ib }, 0 }, | |
2750 | { "rcrA", { Eb, Ib }, 0 }, | |
2751 | { "shlA", { Eb, Ib }, 0 }, | |
2752 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 2753 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 2754 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 2755 | }, |
1ceb70f8 | 2756 | /* REG_C1 */ |
252b5132 | 2757 | { |
bf890a93 IT |
2758 | { "rolQ", { Ev, Ib }, 0 }, |
2759 | { "rorQ", { Ev, Ib }, 0 }, | |
2760 | { "rclQ", { Ev, Ib }, 0 }, | |
2761 | { "rcrQ", { Ev, Ib }, 0 }, | |
2762 | { "shlQ", { Ev, Ib }, 0 }, | |
2763 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 2764 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 2765 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 2766 | }, |
1ceb70f8 | 2767 | /* REG_C6 */ |
4e7d34a6 | 2768 | { |
bf890a93 | 2769 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
2770 | { Bad_Opcode }, |
2771 | { Bad_Opcode }, | |
2772 | { Bad_Opcode }, | |
2773 | { Bad_Opcode }, | |
2774 | { Bad_Opcode }, | |
2775 | { Bad_Opcode }, | |
2776 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 2777 | }, |
1ceb70f8 | 2778 | /* REG_C7 */ |
4e7d34a6 | 2779 | { |
bf890a93 | 2780 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
2781 | { Bad_Opcode }, |
2782 | { Bad_Opcode }, | |
2783 | { Bad_Opcode }, | |
2784 | { Bad_Opcode }, | |
2785 | { Bad_Opcode }, | |
2786 | { Bad_Opcode }, | |
2787 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 2788 | }, |
1ceb70f8 | 2789 | /* REG_D0 */ |
252b5132 | 2790 | { |
bf890a93 IT |
2791 | { "rolA", { Eb, I1 }, 0 }, |
2792 | { "rorA", { Eb, I1 }, 0 }, | |
2793 | { "rclA", { Eb, I1 }, 0 }, | |
2794 | { "rcrA", { Eb, I1 }, 0 }, | |
2795 | { "shlA", { Eb, I1 }, 0 }, | |
2796 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 2797 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 2798 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 2799 | }, |
1ceb70f8 | 2800 | /* REG_D1 */ |
252b5132 | 2801 | { |
bf890a93 IT |
2802 | { "rolQ", { Ev, I1 }, 0 }, |
2803 | { "rorQ", { Ev, I1 }, 0 }, | |
2804 | { "rclQ", { Ev, I1 }, 0 }, | |
2805 | { "rcrQ", { Ev, I1 }, 0 }, | |
2806 | { "shlQ", { Ev, I1 }, 0 }, | |
2807 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 2808 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 2809 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 2810 | }, |
1ceb70f8 | 2811 | /* REG_D2 */ |
252b5132 | 2812 | { |
bf890a93 IT |
2813 | { "rolA", { Eb, CL }, 0 }, |
2814 | { "rorA", { Eb, CL }, 0 }, | |
2815 | { "rclA", { Eb, CL }, 0 }, | |
2816 | { "rcrA", { Eb, CL }, 0 }, | |
2817 | { "shlA", { Eb, CL }, 0 }, | |
2818 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 2819 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 2820 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 2821 | }, |
1ceb70f8 | 2822 | /* REG_D3 */ |
252b5132 | 2823 | { |
bf890a93 IT |
2824 | { "rolQ", { Ev, CL }, 0 }, |
2825 | { "rorQ", { Ev, CL }, 0 }, | |
2826 | { "rclQ", { Ev, CL }, 0 }, | |
2827 | { "rcrQ", { Ev, CL }, 0 }, | |
2828 | { "shlQ", { Ev, CL }, 0 }, | |
2829 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 2830 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 2831 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 2832 | }, |
1ceb70f8 | 2833 | /* REG_F6 */ |
252b5132 | 2834 | { |
bf890a93 | 2835 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 2836 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
2837 | { "notA", { Ebh1 }, 0 }, |
2838 | { "negA", { Ebh1 }, 0 }, | |
2839 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
2840 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
2841 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
2842 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 2843 | }, |
1ceb70f8 | 2844 | /* REG_F7 */ |
252b5132 | 2845 | { |
bf890a93 | 2846 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 2847 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
2848 | { "notQ", { Evh1 }, 0 }, |
2849 | { "negQ", { Evh1 }, 0 }, | |
2850 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
2851 | { "imulQ", { Ev }, 0 }, | |
2852 | { "divQ", { Ev }, 0 }, | |
2853 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 2854 | }, |
1ceb70f8 | 2855 | /* REG_FE */ |
252b5132 | 2856 | { |
bf890a93 IT |
2857 | { "incA", { Ebh1 }, 0 }, |
2858 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 2859 | }, |
1ceb70f8 | 2860 | /* REG_FF */ |
252b5132 | 2861 | { |
bf890a93 IT |
2862 | { "incQ", { Evh1 }, 0 }, |
2863 | { "decQ", { Evh1 }, 0 }, | |
36938cab | 2864 | { "call{@|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 2865 | { MOD_TABLE (MOD_FF_REG_3) }, |
36938cab | 2866 | { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 2867 | { MOD_TABLE (MOD_FF_REG_5) }, |
36938cab | 2868 | { "push{P|}", { stackEv }, 0 }, |
592d1631 | 2869 | { Bad_Opcode }, |
252b5132 | 2870 | }, |
1ceb70f8 | 2871 | /* REG_0F00 */ |
252b5132 | 2872 | { |
bf890a93 IT |
2873 | { "sldtD", { Sv }, 0 }, |
2874 | { "strD", { Sv }, 0 }, | |
2875 | { "lldt", { Ew }, 0 }, | |
2876 | { "ltr", { Ew }, 0 }, | |
2877 | { "verr", { Ew }, 0 }, | |
2878 | { "verw", { Ew }, 0 }, | |
592d1631 L |
2879 | { Bad_Opcode }, |
2880 | { Bad_Opcode }, | |
252b5132 | 2881 | }, |
1ceb70f8 | 2882 | /* REG_0F01 */ |
252b5132 | 2883 | { |
1ceb70f8 L |
2884 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2885 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2886 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2887 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 2888 | { "smswD", { Sv }, 0 }, |
8eab4136 | 2889 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 2890 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 2891 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2892 | }, |
b5b1fc4f | 2893 | /* REG_0F0D */ |
252b5132 | 2894 | { |
bf890a93 IT |
2895 | { "prefetch", { Mb }, 0 }, |
2896 | { "prefetchw", { Mb }, 0 }, | |
2897 | { "prefetchwt1", { Mb }, 0 }, | |
2898 | { "prefetch", { Mb }, 0 }, | |
2899 | { "prefetch", { Mb }, 0 }, | |
2900 | { "prefetch", { Mb }, 0 }, | |
2901 | { "prefetch", { Mb }, 0 }, | |
2902 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 2903 | }, |
1ceb70f8 | 2904 | /* REG_0F18 */ |
252b5132 | 2905 | { |
1ceb70f8 L |
2906 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2907 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2908 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2909 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
2910 | { MOD_TABLE (MOD_0F18_REG_4) }, |
2911 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
2912 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
2913 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 2914 | }, |
f8687e93 | 2915 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
2916 | { |
2917 | { "cldemote", { Mb }, 0 }, | |
2918 | { "nopQ", { Ev }, 0 }, | |
2919 | { "nopQ", { Ev }, 0 }, | |
2920 | { "nopQ", { Ev }, 0 }, | |
2921 | { "nopQ", { Ev }, 0 }, | |
2922 | { "nopQ", { Ev }, 0 }, | |
2923 | { "nopQ", { Ev }, 0 }, | |
2924 | { "nopQ", { Ev }, 0 }, | |
2925 | }, | |
f8687e93 | 2926 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
2927 | { |
2928 | { "nopQ", { Ev }, 0 }, | |
464d2b65 | 2929 | { "rdsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
2930 | { "nopQ", { Ev }, 0 }, |
2931 | { "nopQ", { Ev }, 0 }, | |
2932 | { "nopQ", { Ev }, 0 }, | |
2933 | { "nopQ", { Ev }, 0 }, | |
2934 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 2935 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 2936 | }, |
c4694f17 TG |
2937 | /* REG_0F38D8_PREFIX_1 */ |
2938 | { | |
2939 | { "aesencwide128kl", { M }, 0 }, | |
2940 | { "aesdecwide128kl", { M }, 0 }, | |
2941 | { "aesencwide256kl", { M }, 0 }, | |
2942 | { "aesdecwide256kl", { M }, 0 }, | |
2943 | }, | |
c1fa250a LC |
2944 | /* REG_0F3A0F_PREFIX_1_MOD_3 */ |
2945 | { | |
2946 | { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) }, | |
2947 | }, | |
1ceb70f8 | 2948 | /* REG_0F71 */ |
a6bd098c | 2949 | { |
592d1631 L |
2950 | { Bad_Opcode }, |
2951 | { Bad_Opcode }, | |
1ceb70f8 | 2952 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 2953 | { Bad_Opcode }, |
1ceb70f8 | 2954 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 2955 | { Bad_Opcode }, |
1ceb70f8 | 2956 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 2957 | }, |
1ceb70f8 | 2958 | /* REG_0F72 */ |
a6bd098c | 2959 | { |
592d1631 L |
2960 | { Bad_Opcode }, |
2961 | { Bad_Opcode }, | |
1ceb70f8 | 2962 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 2963 | { Bad_Opcode }, |
1ceb70f8 | 2964 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 2965 | { Bad_Opcode }, |
1ceb70f8 | 2966 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 2967 | }, |
1ceb70f8 | 2968 | /* REG_0F73 */ |
252b5132 | 2969 | { |
592d1631 L |
2970 | { Bad_Opcode }, |
2971 | { Bad_Opcode }, | |
1ceb70f8 L |
2972 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2973 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
2974 | { Bad_Opcode }, |
2975 | { Bad_Opcode }, | |
1ceb70f8 L |
2976 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2977 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2978 | }, |
1ceb70f8 | 2979 | /* REG_0FA6 */ |
252b5132 | 2980 | { |
bf890a93 IT |
2981 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
2982 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
2983 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2984 | }, |
1ceb70f8 | 2985 | /* REG_0FA7 */ |
4e7d34a6 | 2986 | { |
bf890a93 IT |
2987 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
2988 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
2989 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
2990 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
2991 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
2992 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2993 | }, |
1ceb70f8 | 2994 | /* REG_0FAE */ |
4e7d34a6 | 2995 | { |
1ceb70f8 L |
2996 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2997 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2998 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2999 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3000 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3001 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3002 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3003 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3004 | }, |
1ceb70f8 | 3005 | /* REG_0FBA */ |
252b5132 | 3006 | { |
592d1631 L |
3007 | { Bad_Opcode }, |
3008 | { Bad_Opcode }, | |
3009 | { Bad_Opcode }, | |
3010 | { Bad_Opcode }, | |
bf890a93 IT |
3011 | { "btQ", { Ev, Ib }, 0 }, |
3012 | { "btsQ", { Evh1, Ib }, 0 }, | |
3013 | { "btrQ", { Evh1, Ib }, 0 }, | |
3014 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3015 | }, |
1ceb70f8 | 3016 | /* REG_0FC7 */ |
c608c12e | 3017 | { |
592d1631 | 3018 | { Bad_Opcode }, |
bf890a93 | 3019 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3020 | { Bad_Opcode }, |
963f3586 IT |
3021 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3022 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3023 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3024 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3025 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3026 | }, |
592a252b | 3027 | /* REG_VEX_0F71 */ |
c0f3af97 | 3028 | { |
592d1631 L |
3029 | { Bad_Opcode }, |
3030 | { Bad_Opcode }, | |
592a252b | 3031 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3032 | { Bad_Opcode }, |
592a252b | 3033 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3034 | { Bad_Opcode }, |
592a252b | 3035 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3036 | }, |
592a252b | 3037 | /* REG_VEX_0F72 */ |
c0f3af97 | 3038 | { |
592d1631 L |
3039 | { Bad_Opcode }, |
3040 | { Bad_Opcode }, | |
592a252b | 3041 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3042 | { Bad_Opcode }, |
592a252b | 3043 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3044 | { Bad_Opcode }, |
592a252b | 3045 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3046 | }, |
592a252b | 3047 | /* REG_VEX_0F73 */ |
c0f3af97 | 3048 | { |
592d1631 L |
3049 | { Bad_Opcode }, |
3050 | { Bad_Opcode }, | |
592a252b L |
3051 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3052 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3053 | { Bad_Opcode }, |
3054 | { Bad_Opcode }, | |
592a252b L |
3055 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3056 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3057 | }, |
592a252b | 3058 | /* REG_VEX_0FAE */ |
c0f3af97 | 3059 | { |
592d1631 L |
3060 | { Bad_Opcode }, |
3061 | { Bad_Opcode }, | |
592a252b L |
3062 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3063 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3064 | }, |
260cd341 LC |
3065 | /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */ |
3066 | { | |
3067 | { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) }, | |
3068 | }, | |
f12dc422 L |
3069 | /* REG_VEX_0F38F3 */ |
3070 | { | |
3071 | { Bad_Opcode }, | |
035e7389 JB |
3072 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) }, |
3073 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) }, | |
3074 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) }, | |
f12dc422 | 3075 | }, |
467bbef0 | 3076 | /* REG_0FXOP_09_01_L_0 */ |
2a2a0f38 QN |
3077 | { |
3078 | { Bad_Opcode }, | |
467bbef0 JB |
3079 | { "blcfill", { VexGdq, Edq }, 0 }, |
3080 | { "blsfill", { VexGdq, Edq }, 0 }, | |
3081 | { "blcs", { VexGdq, Edq }, 0 }, | |
3082 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
3083 | { "blcic", { VexGdq, Edq }, 0 }, | |
3084 | { "blsic", { VexGdq, Edq }, 0 }, | |
3085 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 3086 | }, |
467bbef0 | 3087 | /* REG_0FXOP_09_02_L_0 */ |
2a2a0f38 QN |
3088 | { |
3089 | { Bad_Opcode }, | |
467bbef0 | 3090 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
3091 | { Bad_Opcode }, |
3092 | { Bad_Opcode }, | |
3093 | { Bad_Opcode }, | |
3094 | { Bad_Opcode }, | |
467bbef0 JB |
3095 | { "blci", { VexGdq, Edq }, 0 }, |
3096 | }, | |
3097 | /* REG_0FXOP_09_12_M_1_L_0 */ | |
3098 | { | |
3099 | { "llwpcb", { Edq }, 0 }, | |
3100 | { "slwpcb", { Edq }, 0 }, | |
3101 | }, | |
3102 | /* REG_0FXOP_0A_12_L_0 */ | |
3103 | { | |
3104 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
3105 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 3106 | }, |
ad692897 L |
3107 | |
3108 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3109 | }; |
3110 | ||
1ceb70f8 L |
3111 | static const struct dis386 prefix_table[][4] = { |
3112 | /* PREFIX_90 */ | |
252b5132 | 3113 | { |
bf890a93 IT |
3114 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3115 | { "pause", { XX }, 0 }, | |
3116 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3117 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3118 | }, |
4e7d34a6 | 3119 | |
81d54bb7 CL |
3120 | /* PREFIX_0F01_REG_1_RM_4 */ |
3121 | { | |
3122 | { Bad_Opcode }, | |
3123 | { Bad_Opcode }, | |
3124 | { "tdcall", { Skip_MODRM }, 0 }, | |
3125 | { Bad_Opcode }, | |
3126 | }, | |
3127 | ||
3128 | /* PREFIX_0F01_REG_1_RM_5 */ | |
3129 | { | |
3130 | { Bad_Opcode }, | |
3131 | { Bad_Opcode }, | |
3132 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) }, | |
3133 | { Bad_Opcode }, | |
3134 | }, | |
3135 | ||
3136 | /* PREFIX_0F01_REG_1_RM_6 */ | |
3137 | { | |
3138 | { Bad_Opcode }, | |
3139 | { Bad_Opcode }, | |
3140 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) }, | |
3141 | { Bad_Opcode }, | |
3142 | }, | |
3143 | ||
3144 | /* PREFIX_0F01_REG_1_RM_7 */ | |
3145 | { | |
3146 | { "encls", { Skip_MODRM }, 0 }, | |
3147 | { Bad_Opcode }, | |
3148 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) }, | |
3149 | { Bad_Opcode }, | |
3150 | }, | |
3151 | ||
f9630fa6 | 3152 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3153 | { |
3154 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3155 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3156 | { Bad_Opcode }, |
3157 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3158 | }, |
3159 | ||
f8687e93 | 3160 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3161 | { |
3162 | { Bad_Opcode }, | |
3163 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3164 | }, | |
3165 | ||
f8687e93 | 3166 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3167 | { |
4b27d27c | 3168 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3169 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3170 | { Bad_Opcode }, |
efe30057 | 3171 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3172 | }, |
3173 | ||
3174 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3175 | { | |
3176 | { Bad_Opcode }, | |
3177 | { Bad_Opcode }, | |
3178 | { Bad_Opcode }, | |
3179 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3180 | }, |
3181 | ||
f8687e93 | 3182 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3183 | { |
3184 | { Bad_Opcode }, | |
c2f76402 | 3185 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3186 | }, |
3187 | ||
f64c42a9 LC |
3188 | /* PREFIX_0F01_REG_5_MOD_3_RM_4 */ |
3189 | { | |
3190 | { Bad_Opcode }, | |
3191 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) }, | |
3192 | }, | |
3193 | ||
3194 | /* PREFIX_0F01_REG_5_MOD_3_RM_5 */ | |
3195 | { | |
3196 | { Bad_Opcode }, | |
3197 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) }, | |
3198 | }, | |
3199 | ||
3200 | /* PREFIX_0F01_REG_5_MOD_3_RM_6 */ | |
3201 | { | |
3202 | { "rdpkru", { Skip_MODRM }, 0 }, | |
3203 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) }, | |
3204 | }, | |
3205 | ||
3206 | /* PREFIX_0F01_REG_5_MOD_3_RM_7 */ | |
3207 | { | |
3208 | { "wrpkru", { Skip_MODRM }, 0 }, | |
3209 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) }, | |
3210 | }, | |
3211 | ||
267b8516 JB |
3212 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3213 | { | |
3214 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3215 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3216 | }, |
3217 | ||
646cc3e0 GG |
3218 | /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ |
3219 | { | |
3220 | { "invlpgb", { Skip_MODRM }, 0 }, | |
3221 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) }, | |
3222 | { Bad_Opcode }, | |
3223 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) }, | |
3224 | }, | |
3225 | ||
3226 | /* PREFIX_0F01_REG_7_MOD_3_RM_7 */ | |
3227 | { | |
3228 | { "tlbsync", { Skip_MODRM }, 0 }, | |
3229 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) }, | |
3230 | { Bad_Opcode }, | |
3231 | { "pvalidate", { Skip_MODRM }, 0 }, | |
3232 | }, | |
3233 | ||
3233d7d0 IT |
3234 | /* PREFIX_0F09 */ |
3235 | { | |
3236 | { "wbinvd", { XX }, 0 }, | |
3237 | { "wbnoinvd", { XX }, 0 }, | |
3238 | }, | |
3239 | ||
1ceb70f8 | 3240 | /* PREFIX_0F10 */ |
cc0ec051 | 3241 | { |
507bd325 L |
3242 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3243 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3244 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3245 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3246 | }, |
4e7d34a6 | 3247 | |
1ceb70f8 | 3248 | /* PREFIX_0F11 */ |
30d1c836 | 3249 | { |
507bd325 L |
3250 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3251 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3252 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3253 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3254 | }, |
252b5132 | 3255 | |
1ceb70f8 | 3256 | /* PREFIX_0F12 */ |
c608c12e | 3257 | { |
1ceb70f8 | 3258 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3259 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3260 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3261 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3262 | }, |
4e7d34a6 | 3263 | |
1ceb70f8 | 3264 | /* PREFIX_0F16 */ |
c608c12e | 3265 | { |
1ceb70f8 | 3266 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3267 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3268 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3269 | }, |
4e7d34a6 | 3270 | |
7e8b059b L |
3271 | /* PREFIX_0F1A */ |
3272 | { | |
3273 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3274 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3275 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3276 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3277 | }, |
3278 | ||
3279 | /* PREFIX_0F1B */ | |
3280 | { | |
3281 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3282 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3283 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3284 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3285 | }, |
3286 | ||
c48935d7 IT |
3287 | /* PREFIX_0F1C */ |
3288 | { | |
3289 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3290 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3291 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3292 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3293 | }, | |
3294 | ||
603555e5 L |
3295 | /* PREFIX_0F1E */ |
3296 | { | |
3297 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3298 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3299 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3300 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3301 | }, | |
3302 | ||
1ceb70f8 | 3303 | /* PREFIX_0F2A */ |
c608c12e | 3304 | { |
507bd325 | 3305 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3306 | { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3307 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3308 | { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, |
c608c12e | 3309 | }, |
4e7d34a6 | 3310 | |
1ceb70f8 | 3311 | /* PREFIX_0F2B */ |
c608c12e | 3312 | { |
75c135a8 L |
3313 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3314 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3315 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3316 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3317 | }, |
4e7d34a6 | 3318 | |
1ceb70f8 | 3319 | /* PREFIX_0F2C */ |
c608c12e | 3320 | { |
507bd325 | 3321 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3322 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3323 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3324 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3325 | }, |
4e7d34a6 | 3326 | |
1ceb70f8 | 3327 | /* PREFIX_0F2D */ |
c608c12e | 3328 | { |
507bd325 | 3329 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3330 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3331 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3332 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3333 | }, |
4e7d34a6 | 3334 | |
1ceb70f8 | 3335 | /* PREFIX_0F2E */ |
c608c12e | 3336 | { |
bf890a93 | 3337 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3338 | { Bad_Opcode }, |
bf890a93 | 3339 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3340 | }, |
4e7d34a6 | 3341 | |
1ceb70f8 | 3342 | /* PREFIX_0F2F */ |
c608c12e | 3343 | { |
bf890a93 | 3344 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3345 | { Bad_Opcode }, |
bf890a93 | 3346 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3347 | }, |
4e7d34a6 | 3348 | |
1ceb70f8 | 3349 | /* PREFIX_0F51 */ |
c608c12e | 3350 | { |
507bd325 L |
3351 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3352 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3353 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3354 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3355 | }, |
4e7d34a6 | 3356 | |
1ceb70f8 | 3357 | /* PREFIX_0F52 */ |
c608c12e | 3358 | { |
507bd325 L |
3359 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3360 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3361 | }, |
4e7d34a6 | 3362 | |
1ceb70f8 | 3363 | /* PREFIX_0F53 */ |
c608c12e | 3364 | { |
507bd325 L |
3365 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3366 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3367 | }, |
4e7d34a6 | 3368 | |
1ceb70f8 | 3369 | /* PREFIX_0F58 */ |
c608c12e | 3370 | { |
507bd325 L |
3371 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3372 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3373 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3374 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3375 | }, |
4e7d34a6 | 3376 | |
1ceb70f8 | 3377 | /* PREFIX_0F59 */ |
c608c12e | 3378 | { |
507bd325 L |
3379 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3380 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3381 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3382 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3383 | }, |
4e7d34a6 | 3384 | |
1ceb70f8 | 3385 | /* PREFIX_0F5A */ |
041bd2e0 | 3386 | { |
507bd325 L |
3387 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3388 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3389 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3390 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3391 | }, |
4e7d34a6 | 3392 | |
1ceb70f8 | 3393 | /* PREFIX_0F5B */ |
041bd2e0 | 3394 | { |
507bd325 L |
3395 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3396 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3397 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3398 | }, |
4e7d34a6 | 3399 | |
1ceb70f8 | 3400 | /* PREFIX_0F5C */ |
041bd2e0 | 3401 | { |
507bd325 L |
3402 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3403 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3404 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3405 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3406 | }, |
4e7d34a6 | 3407 | |
1ceb70f8 | 3408 | /* PREFIX_0F5D */ |
041bd2e0 | 3409 | { |
507bd325 L |
3410 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3411 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3412 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3413 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3414 | }, |
4e7d34a6 | 3415 | |
1ceb70f8 | 3416 | /* PREFIX_0F5E */ |
041bd2e0 | 3417 | { |
507bd325 L |
3418 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3419 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3420 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3421 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3422 | }, |
4e7d34a6 | 3423 | |
1ceb70f8 | 3424 | /* PREFIX_0F5F */ |
041bd2e0 | 3425 | { |
507bd325 L |
3426 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3427 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3428 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3429 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3430 | }, |
4e7d34a6 | 3431 | |
1ceb70f8 | 3432 | /* PREFIX_0F60 */ |
041bd2e0 | 3433 | { |
507bd325 | 3434 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3435 | { Bad_Opcode }, |
507bd325 | 3436 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3437 | }, |
4e7d34a6 | 3438 | |
1ceb70f8 | 3439 | /* PREFIX_0F61 */ |
041bd2e0 | 3440 | { |
507bd325 | 3441 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3442 | { Bad_Opcode }, |
507bd325 | 3443 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3444 | }, |
4e7d34a6 | 3445 | |
1ceb70f8 | 3446 | /* PREFIX_0F62 */ |
041bd2e0 | 3447 | { |
507bd325 | 3448 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3449 | { Bad_Opcode }, |
507bd325 | 3450 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3451 | }, |
4e7d34a6 | 3452 | |
1ceb70f8 | 3453 | /* PREFIX_0F6F */ |
ca164297 | 3454 | { |
507bd325 L |
3455 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3456 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3457 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3458 | }, |
4e7d34a6 | 3459 | |
1ceb70f8 | 3460 | /* PREFIX_0F70 */ |
4e7d34a6 | 3461 | { |
507bd325 L |
3462 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3463 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3464 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3465 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3466 | }, |
3467 | ||
1ceb70f8 | 3468 | /* PREFIX_0F78 */ |
4e7d34a6 | 3469 | { |
bf890a93 | 3470 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3471 | { Bad_Opcode }, |
bf890a93 IT |
3472 | {"extrq", { XS, Ib, Ib }, 0 }, |
3473 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3474 | }, |
3475 | ||
1ceb70f8 | 3476 | /* PREFIX_0F79 */ |
4e7d34a6 | 3477 | { |
bf890a93 | 3478 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3479 | { Bad_Opcode }, |
bf890a93 IT |
3480 | {"extrq", { XM, XS }, 0 }, |
3481 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3482 | }, |
3483 | ||
1ceb70f8 | 3484 | /* PREFIX_0F7C */ |
ca164297 | 3485 | { |
592d1631 L |
3486 | { Bad_Opcode }, |
3487 | { Bad_Opcode }, | |
507bd325 L |
3488 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3489 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3490 | }, |
4e7d34a6 | 3491 | |
1ceb70f8 | 3492 | /* PREFIX_0F7D */ |
ca164297 | 3493 | { |
592d1631 L |
3494 | { Bad_Opcode }, |
3495 | { Bad_Opcode }, | |
507bd325 L |
3496 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3497 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3498 | }, |
4e7d34a6 | 3499 | |
1ceb70f8 | 3500 | /* PREFIX_0F7E */ |
ca164297 | 3501 | { |
507bd325 L |
3502 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3503 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3504 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3505 | }, |
4e7d34a6 | 3506 | |
1ceb70f8 | 3507 | /* PREFIX_0F7F */ |
ca164297 | 3508 | { |
507bd325 L |
3509 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3510 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3511 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3512 | }, |
4e7d34a6 | 3513 | |
f8687e93 | 3514 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3515 | { |
3516 | { Bad_Opcode }, | |
bf890a93 | 3517 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3518 | }, |
3519 | ||
f8687e93 | 3520 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3521 | { |
3522 | { Bad_Opcode }, | |
bf890a93 | 3523 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3524 | }, |
3525 | ||
f8687e93 | 3526 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3527 | { |
3528 | { Bad_Opcode }, | |
bf890a93 | 3529 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3530 | }, |
3531 | ||
f8687e93 | 3532 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3533 | { |
3534 | { Bad_Opcode }, | |
bf890a93 | 3535 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3536 | }, |
3537 | ||
f8687e93 | 3538 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3539 | { |
3540 | { "xsave", { FXSAVE }, 0 }, | |
b24d668c | 3541 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3542 | }, |
3543 | ||
f8687e93 | 3544 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3545 | { |
3546 | { Bad_Opcode }, | |
b24d668c | 3547 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3548 | }, |
3549 | ||
f8687e93 | 3550 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3551 | { |
3552 | { "lfence", { Skip_MODRM }, 0 }, | |
464d2b65 | 3553 | { "incsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
3554 | }, |
3555 | ||
f8687e93 | 3556 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3557 | { |
603555e5 L |
3558 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3559 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3560 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3561 | }, |
3562 | ||
f8687e93 | 3563 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3564 | { |
f8687e93 | 3565 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3566 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3567 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3568 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3569 | }, |
3570 | ||
f8687e93 | 3571 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3572 | { |
bf890a93 | 3573 | { "clflush", { Mb }, 0 }, |
963f3586 | 3574 | { Bad_Opcode }, |
bf890a93 | 3575 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3576 | }, |
3577 | ||
1ceb70f8 | 3578 | /* PREFIX_0FB8 */ |
ca164297 | 3579 | { |
592d1631 | 3580 | { Bad_Opcode }, |
bf890a93 | 3581 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3582 | }, |
4e7d34a6 | 3583 | |
f12dc422 L |
3584 | /* PREFIX_0FBC */ |
3585 | { | |
bf890a93 IT |
3586 | { "bsfS", { Gv, Ev }, 0 }, |
3587 | { "tzcntS", { Gv, Ev }, 0 }, | |
3588 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3589 | }, |
3590 | ||
1ceb70f8 | 3591 | /* PREFIX_0FBD */ |
050dfa73 | 3592 | { |
bf890a93 IT |
3593 | { "bsrS", { Gv, Ev }, 0 }, |
3594 | { "lzcntS", { Gv, Ev }, 0 }, | |
3595 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3596 | }, |
3597 | ||
1ceb70f8 | 3598 | /* PREFIX_0FC2 */ |
050dfa73 | 3599 | { |
507bd325 L |
3600 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3601 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3602 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3603 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3604 | }, |
246c51aa | 3605 | |
f8687e93 | 3606 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3607 | { |
bf890a93 IT |
3608 | { "vmptrld",{ Mq }, 0 }, |
3609 | { "vmxon", { Mq }, 0 }, | |
3610 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3611 | }, |
3612 | ||
f8687e93 | 3613 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3614 | { |
3615 | { "rdrand", { Ev }, 0 }, | |
f64c42a9 | 3616 | { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) }, |
f24bcbaa L |
3617 | { "rdrand", { Ev }, 0 } |
3618 | }, | |
3619 | ||
f8687e93 | 3620 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3621 | { |
3622 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3623 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3624 | { "rdseed", { Ev }, 0 }, |
3625 | }, | |
3626 | ||
1ceb70f8 | 3627 | /* PREFIX_0FD0 */ |
050dfa73 | 3628 | { |
592d1631 L |
3629 | { Bad_Opcode }, |
3630 | { Bad_Opcode }, | |
bf890a93 IT |
3631 | { "addsubpd", { XM, EXx }, 0 }, |
3632 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3633 | }, |
050dfa73 | 3634 | |
1ceb70f8 | 3635 | /* PREFIX_0FD6 */ |
050dfa73 | 3636 | { |
592d1631 | 3637 | { Bad_Opcode }, |
bf890a93 IT |
3638 | { "movq2dq",{ XM, MS }, 0 }, |
3639 | { "movq", { EXqS, XM }, 0 }, | |
3640 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3641 | }, |
3642 | ||
1ceb70f8 | 3643 | /* PREFIX_0FE6 */ |
7918206c | 3644 | { |
592d1631 | 3645 | { Bad_Opcode }, |
507bd325 L |
3646 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3647 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3648 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3649 | }, |
8b38ad71 | 3650 | |
1ceb70f8 | 3651 | /* PREFIX_0FE7 */ |
8b38ad71 | 3652 | { |
507bd325 | 3653 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3654 | { Bad_Opcode }, |
75c135a8 | 3655 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3656 | }, |
3657 | ||
1ceb70f8 | 3658 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3659 | { |
592d1631 L |
3660 | { Bad_Opcode }, |
3661 | { Bad_Opcode }, | |
3662 | { Bad_Opcode }, | |
1ceb70f8 | 3663 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3664 | }, |
3665 | ||
1ceb70f8 | 3666 | /* PREFIX_0FF7 */ |
4e7d34a6 | 3667 | { |
507bd325 | 3668 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 3669 | { Bad_Opcode }, |
507bd325 | 3670 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 3671 | }, |
42903f7f | 3672 | |
c4694f17 TG |
3673 | /* PREFIX_0F38D8 */ |
3674 | { | |
3675 | { Bad_Opcode }, | |
3676 | { REG_TABLE (REG_0F38D8_PREFIX_1) }, | |
3677 | }, | |
3678 | ||
3679 | /* PREFIX_0F38DC */ | |
3680 | { | |
3681 | { Bad_Opcode }, | |
3682 | { MOD_TABLE (MOD_0F38DC_PREFIX_1) }, | |
3683 | { "aesenc", { XM, EXx }, 0 }, | |
3684 | }, | |
3685 | ||
3686 | /* PREFIX_0F38DD */ | |
3687 | { | |
3688 | { Bad_Opcode }, | |
3689 | { MOD_TABLE (MOD_0F38DD_PREFIX_1) }, | |
3690 | { "aesenclast", { XM, EXx }, 0 }, | |
3691 | }, | |
3692 | ||
3693 | /* PREFIX_0F38DE */ | |
3694 | { | |
3695 | { Bad_Opcode }, | |
3696 | { MOD_TABLE (MOD_0F38DE_PREFIX_1) }, | |
3697 | { "aesdec", { XM, EXx }, 0 }, | |
3698 | }, | |
3699 | ||
3700 | /* PREFIX_0F38DF */ | |
3701 | { | |
3702 | { Bad_Opcode }, | |
3703 | { MOD_TABLE (MOD_0F38DF_PREFIX_1) }, | |
3704 | { "aesdeclast", { XM, EXx }, 0 }, | |
3705 | }, | |
3706 | ||
1ceb70f8 | 3707 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3708 | { |
9ab00b61 | 3709 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
592d1631 | 3710 | { Bad_Opcode }, |
9ab00b61 | 3711 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
2875b28a | 3712 | { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, |
4e7d34a6 L |
3713 | }, |
3714 | ||
1ceb70f8 | 3715 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3716 | { |
9ab00b61 | 3717 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
592d1631 | 3718 | { Bad_Opcode }, |
9ab00b61 | 3719 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
2875b28a | 3720 | { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, |
4e7d34a6 L |
3721 | }, |
3722 | ||
603555e5 L |
3723 | /* PREFIX_0F38F6 */ |
3724 | { | |
3725 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
3726 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
3727 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
3728 | { Bad_Opcode }, |
3729 | }, | |
3730 | ||
c0a30a9f L |
3731 | /* PREFIX_0F38F8 */ |
3732 | { | |
3733 | { Bad_Opcode }, | |
5d79adc4 | 3734 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 3735 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 3736 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f | 3737 | }, |
c4694f17 TG |
3738 | /* PREFIX_0F38FA */ |
3739 | { | |
3740 | { Bad_Opcode }, | |
3741 | { MOD_TABLE (MOD_0F38FA_PREFIX_1) }, | |
3742 | }, | |
3743 | ||
3744 | /* PREFIX_0F38FB */ | |
3745 | { | |
3746 | { Bad_Opcode }, | |
3747 | { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, | |
3748 | }, | |
c0a30a9f | 3749 | |
c1fa250a LC |
3750 | /* PREFIX_0F3A0F */ |
3751 | { | |
3752 | { Bad_Opcode }, | |
3753 | { MOD_TABLE (MOD_0F3A0F_PREFIX_1)}, | |
3754 | }, | |
3755 | ||
7531c613 | 3756 | /* PREFIX_VEX_0F10 */ |
42903f7f | 3757 | { |
7531c613 JB |
3758 | { "vmovups", { XM, EXx }, 0 }, |
3759 | { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 }, | |
3760 | { "vmovupd", { XM, EXx }, 0 }, | |
3761 | { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 }, | |
42903f7f L |
3762 | }, |
3763 | ||
7531c613 | 3764 | /* PREFIX_VEX_0F11 */ |
42903f7f | 3765 | { |
7531c613 JB |
3766 | { "vmovups", { EXxS, XM }, 0 }, |
3767 | { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 }, | |
3768 | { "vmovupd", { EXxS, XM }, 0 }, | |
3769 | { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 }, | |
42903f7f L |
3770 | }, |
3771 | ||
7531c613 | 3772 | /* PREFIX_VEX_0F12 */ |
42903f7f | 3773 | { |
7531c613 JB |
3774 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
3775 | { "vmovsldup", { XM, EXx }, 0 }, | |
3776 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, | |
3777 | { "vmovddup", { XM, EXymmq }, 0 }, | |
42903f7f L |
3778 | }, |
3779 | ||
7531c613 | 3780 | /* PREFIX_VEX_0F16 */ |
42903f7f | 3781 | { |
7531c613 JB |
3782 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
3783 | { "vmovshdup", { XM, EXx }, 0 }, | |
3784 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, | |
5f754f58 | 3785 | }, |
7c52e0e8 | 3786 | |
592a252b | 3787 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 3788 | { |
592d1631 | 3789 | { Bad_Opcode }, |
b24d668c | 3790 | { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 3791 | { Bad_Opcode }, |
b24d668c | 3792 | { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 3793 | }, |
7c52e0e8 | 3794 | |
592a252b | 3795 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 3796 | { |
592d1631 | 3797 | { Bad_Opcode }, |
17d3c7ec | 3798 | { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 }, |
592d1631 | 3799 | { Bad_Opcode }, |
17d3c7ec | 3800 | { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 }, |
5f754f58 | 3801 | }, |
7c52e0e8 | 3802 | |
592a252b | 3803 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 3804 | { |
592d1631 | 3805 | { Bad_Opcode }, |
17d3c7ec | 3806 | { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 }, |
592d1631 | 3807 | { Bad_Opcode }, |
17d3c7ec | 3808 | { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 }, |
7c52e0e8 L |
3809 | }, |
3810 | ||
592a252b | 3811 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 3812 | { |
17d3c7ec | 3813 | { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 3814 | { Bad_Opcode }, |
17d3c7ec | 3815 | { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
3816 | }, |
3817 | ||
592a252b | 3818 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 3819 | { |
17d3c7ec | 3820 | { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 3821 | { Bad_Opcode }, |
17d3c7ec | 3822 | { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
3823 | }, |
3824 | ||
43234a1e L |
3825 | /* PREFIX_VEX_0F41 */ |
3826 | { | |
3827 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
3828 | { Bad_Opcode }, |
3829 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
3830 | }, |
3831 | ||
3832 | /* PREFIX_VEX_0F42 */ | |
3833 | { | |
3834 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
3835 | { Bad_Opcode }, |
3836 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
3837 | }, |
3838 | ||
7531c613 | 3839 | /* PREFIX_VEX_0F44 */ |
c0f3af97 | 3840 | { |
7531c613 | 3841 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
592d1631 | 3842 | { Bad_Opcode }, |
7531c613 | 3843 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, |
c0f3af97 L |
3844 | }, |
3845 | ||
7531c613 | 3846 | /* PREFIX_VEX_0F45 */ |
0bfee649 | 3847 | { |
7531c613 | 3848 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
592d1631 | 3849 | { Bad_Opcode }, |
7531c613 | 3850 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, |
0bfee649 L |
3851 | }, |
3852 | ||
7531c613 | 3853 | /* PREFIX_VEX_0F46 */ |
43234a1e | 3854 | { |
7531c613 | 3855 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
43234a1e | 3856 | { Bad_Opcode }, |
7531c613 | 3857 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, |
43234a1e L |
3858 | }, |
3859 | ||
7531c613 | 3860 | /* PREFIX_VEX_0F47 */ |
1ba585e8 | 3861 | { |
7531c613 | 3862 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
1ba585e8 | 3863 | { Bad_Opcode }, |
7531c613 | 3864 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, |
1ba585e8 IT |
3865 | }, |
3866 | ||
7531c613 | 3867 | /* PREFIX_VEX_0F4A */ |
43234a1e | 3868 | { |
7531c613 | 3869 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 3870 | { Bad_Opcode }, |
7531c613 | 3871 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
43234a1e L |
3872 | }, |
3873 | ||
7531c613 | 3874 | /* PREFIX_VEX_0F4B */ |
1ba585e8 | 3875 | { |
7531c613 | 3876 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, |
1ba585e8 | 3877 | { Bad_Opcode }, |
7531c613 | 3878 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, |
1ba585e8 IT |
3879 | }, |
3880 | ||
7531c613 | 3881 | /* PREFIX_VEX_0F51 */ |
6c30d220 | 3882 | { |
7531c613 JB |
3883 | { "vsqrtps", { XM, EXx }, 0 }, |
3884 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3885 | { "vsqrtpd", { XM, EXx }, 0 }, | |
3886 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
6c30d220 L |
3887 | }, |
3888 | ||
7531c613 | 3889 | /* PREFIX_VEX_0F52 */ |
6c30d220 | 3890 | { |
7531c613 JB |
3891 | { "vrsqrtps", { XM, EXx }, 0 }, |
3892 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
6c30d220 L |
3893 | }, |
3894 | ||
7531c613 | 3895 | /* PREFIX_VEX_0F53 */ |
c0f3af97 | 3896 | { |
7531c613 JB |
3897 | { "vrcpps", { XM, EXx }, 0 }, |
3898 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
c0f3af97 L |
3899 | }, |
3900 | ||
7531c613 | 3901 | /* PREFIX_VEX_0F58 */ |
c0f3af97 | 3902 | { |
7531c613 JB |
3903 | { "vaddps", { XM, Vex, EXx }, 0 }, |
3904 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3905 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
3906 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3907 | }, |
3908 | ||
7531c613 | 3909 | /* PREFIX_VEX_0F59 */ |
c0f3af97 | 3910 | { |
7531c613 JB |
3911 | { "vmulps", { XM, Vex, EXx }, 0 }, |
3912 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3913 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
3914 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3915 | }, |
3916 | ||
7531c613 | 3917 | /* PREFIX_VEX_0F5A */ |
ce2f5b3c | 3918 | { |
7531c613 JB |
3919 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
3920 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3921 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
3922 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
ce2f5b3c L |
3923 | }, |
3924 | ||
7531c613 | 3925 | /* PREFIX_VEX_0F5B */ |
6c30d220 | 3926 | { |
7531c613 JB |
3927 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
3928 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
3929 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
6c30d220 L |
3930 | }, |
3931 | ||
7531c613 | 3932 | /* PREFIX_VEX_0F5C */ |
a683cc34 | 3933 | { |
7531c613 JB |
3934 | { "vsubps", { XM, Vex, EXx }, 0 }, |
3935 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3936 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
3937 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
a683cc34 SP |
3938 | }, |
3939 | ||
7531c613 | 3940 | /* PREFIX_VEX_0F5D */ |
a683cc34 | 3941 | { |
7531c613 JB |
3942 | { "vminps", { XM, Vex, EXx }, 0 }, |
3943 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3944 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
3945 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
a683cc34 SP |
3946 | }, |
3947 | ||
7531c613 | 3948 | /* PREFIX_VEX_0F5E */ |
c0f3af97 | 3949 | { |
7531c613 JB |
3950 | { "vdivps", { XM, Vex, EXx }, 0 }, |
3951 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3952 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
3953 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3954 | }, |
3955 | ||
7531c613 | 3956 | /* PREFIX_VEX_0F5F */ |
c0f3af97 | 3957 | { |
7531c613 JB |
3958 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
3959 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3960 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
3961 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3962 | }, |
3963 | ||
7531c613 | 3964 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 3965 | { |
592d1631 | 3966 | { Bad_Opcode }, |
7531c613 JB |
3967 | { "vmovdqu", { XM, EXx }, 0 }, |
3968 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
3969 | }, |
3970 | ||
7531c613 | 3971 | /* PREFIX_VEX_0F70 */ |
922d8de8 | 3972 | { |
592d1631 | 3973 | { Bad_Opcode }, |
7531c613 JB |
3974 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
3975 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
3976 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
922d8de8 DR |
3977 | }, |
3978 | ||
7531c613 | 3979 | /* PREFIX_VEX_0F7C */ |
922d8de8 | 3980 | { |
592d1631 L |
3981 | { Bad_Opcode }, |
3982 | { Bad_Opcode }, | |
7531c613 JB |
3983 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
3984 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3985 | }, |
3986 | ||
7531c613 | 3987 | /* PREFIX_VEX_0F7D */ |
922d8de8 | 3988 | { |
592d1631 L |
3989 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, | |
7531c613 JB |
3991 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
3992 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3993 | }, |
3994 | ||
7531c613 | 3995 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 3996 | { |
592d1631 | 3997 | { Bad_Opcode }, |
7531c613 JB |
3998 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
3999 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4000 | }, |
4001 | ||
7531c613 | 4002 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4003 | { |
592d1631 | 4004 | { Bad_Opcode }, |
7531c613 JB |
4005 | { "vmovdqu", { EXxS, XM }, 0 }, |
4006 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
4007 | }, |
4008 | ||
7531c613 | 4009 | /* PREFIX_VEX_0F90 */ |
c0f3af97 | 4010 | { |
7531c613 | 4011 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
592d1631 | 4012 | { Bad_Opcode }, |
7531c613 | 4013 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, |
c0f3af97 L |
4014 | }, |
4015 | ||
7531c613 | 4016 | /* PREFIX_VEX_0F91 */ |
c0f3af97 | 4017 | { |
7531c613 | 4018 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
592d1631 | 4019 | { Bad_Opcode }, |
7531c613 | 4020 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, |
c0f3af97 | 4021 | }, |
a5ff0eb2 | 4022 | |
7531c613 | 4023 | /* PREFIX_VEX_0F92 */ |
922d8de8 | 4024 | { |
7531c613 | 4025 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
592d1631 | 4026 | { Bad_Opcode }, |
7531c613 JB |
4027 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
4028 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, | |
922d8de8 DR |
4029 | }, |
4030 | ||
7531c613 | 4031 | /* PREFIX_VEX_0F93 */ |
922d8de8 | 4032 | { |
7531c613 | 4033 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
592d1631 | 4034 | { Bad_Opcode }, |
7531c613 JB |
4035 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
4036 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, | |
922d8de8 DR |
4037 | }, |
4038 | ||
7531c613 | 4039 | /* PREFIX_VEX_0F98 */ |
922d8de8 | 4040 | { |
7531c613 | 4041 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
592d1631 | 4042 | { Bad_Opcode }, |
7531c613 | 4043 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, |
922d8de8 DR |
4044 | }, |
4045 | ||
7531c613 | 4046 | /* PREFIX_VEX_0F99 */ |
922d8de8 | 4047 | { |
7531c613 | 4048 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, |
592d1631 | 4049 | { Bad_Opcode }, |
7531c613 | 4050 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, |
922d8de8 DR |
4051 | }, |
4052 | ||
7531c613 | 4053 | /* PREFIX_VEX_0FC2 */ |
922d8de8 | 4054 | { |
7531c613 JB |
4055 | { "vcmpps", { XM, Vex, EXx, CMP }, 0 }, |
4056 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 }, | |
4057 | { "vcmppd", { XM, Vex, EXx, CMP }, 0 }, | |
4058 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 }, | |
922d8de8 DR |
4059 | }, |
4060 | ||
7531c613 | 4061 | /* PREFIX_VEX_0FD0 */ |
922d8de8 | 4062 | { |
592d1631 L |
4063 | { Bad_Opcode }, |
4064 | { Bad_Opcode }, | |
7531c613 JB |
4065 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
4066 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
4067 | }, |
4068 | ||
7531c613 | 4069 | /* PREFIX_VEX_0FE6 */ |
922d8de8 | 4070 | { |
592d1631 | 4071 | { Bad_Opcode }, |
7531c613 JB |
4072 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
4073 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
4074 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
922d8de8 DR |
4075 | }, |
4076 | ||
7531c613 | 4077 | /* PREFIX_VEX_0FF0 */ |
922d8de8 | 4078 | { |
592d1631 L |
4079 | { Bad_Opcode }, |
4080 | { Bad_Opcode }, | |
7531c613 JB |
4081 | { Bad_Opcode }, |
4082 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, | |
922d8de8 DR |
4083 | }, |
4084 | ||
7531c613 | 4085 | /* PREFIX_VEX_0F3849_X86_64 */ |
922d8de8 | 4086 | { |
7531c613 | 4087 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) }, |
592d1631 | 4088 | { Bad_Opcode }, |
7531c613 JB |
4089 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) }, |
4090 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) }, | |
922d8de8 DR |
4091 | }, |
4092 | ||
7531c613 | 4093 | /* PREFIX_VEX_0F384B_X86_64 */ |
922d8de8 | 4094 | { |
592d1631 | 4095 | { Bad_Opcode }, |
7531c613 JB |
4096 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) }, |
4097 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) }, | |
4098 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, | |
922d8de8 DR |
4099 | }, |
4100 | ||
7531c613 | 4101 | /* PREFIX_VEX_0F385C_X86_64 */ |
922d8de8 | 4102 | { |
592d1631 | 4103 | { Bad_Opcode }, |
7531c613 | 4104 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) }, |
592d1631 | 4105 | { Bad_Opcode }, |
922d8de8 DR |
4106 | }, |
4107 | ||
7531c613 | 4108 | /* PREFIX_VEX_0F385E_X86_64 */ |
922d8de8 | 4109 | { |
7531c613 JB |
4110 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) }, |
4111 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) }, | |
4112 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) }, | |
4113 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, | |
922d8de8 DR |
4114 | }, |
4115 | ||
7531c613 | 4116 | /* PREFIX_VEX_0F38F5 */ |
48521003 | 4117 | { |
7531c613 JB |
4118 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
4119 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
48521003 | 4120 | { Bad_Opcode }, |
7531c613 | 4121 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
48521003 IT |
4122 | }, |
4123 | ||
7531c613 | 4124 | /* PREFIX_VEX_0F38F6 */ |
48521003 IT |
4125 | { |
4126 | { Bad_Opcode }, | |
4127 | { Bad_Opcode }, | |
7531c613 JB |
4128 | { Bad_Opcode }, |
4129 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
48521003 IT |
4130 | }, |
4131 | ||
7531c613 | 4132 | /* PREFIX_VEX_0F38F7 */ |
a5ff0eb2 | 4133 | { |
7531c613 JB |
4134 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
4135 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, | |
4136 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
4137 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
a5ff0eb2 | 4138 | }, |
6c30d220 L |
4139 | |
4140 | /* PREFIX_VEX_0F3AF0 */ | |
4141 | { | |
4142 | { Bad_Opcode }, | |
4143 | { Bad_Opcode }, | |
4144 | { Bad_Opcode }, | |
4145 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
4146 | }, | |
43234a1e | 4147 | |
ad692897 | 4148 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
4149 | }; |
4150 | ||
4151 | static const struct dis386 x86_64_table[][2] = { | |
4152 | /* X86_64_06 */ | |
4153 | { | |
bf890a93 | 4154 | { "pushP", { es }, 0 }, |
c0f3af97 L |
4155 | }, |
4156 | ||
4157 | /* X86_64_07 */ | |
4158 | { | |
bf890a93 | 4159 | { "popP", { es }, 0 }, |
c0f3af97 L |
4160 | }, |
4161 | ||
1673df32 | 4162 | /* X86_64_0E */ |
c0f3af97 | 4163 | { |
bf890a93 | 4164 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
4165 | }, |
4166 | ||
4167 | /* X86_64_16 */ | |
4168 | { | |
bf890a93 | 4169 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
4170 | }, |
4171 | ||
4172 | /* X86_64_17 */ | |
4173 | { | |
bf890a93 | 4174 | { "popP", { ss }, 0 }, |
c0f3af97 L |
4175 | }, |
4176 | ||
4177 | /* X86_64_1E */ | |
4178 | { | |
bf890a93 | 4179 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
4180 | }, |
4181 | ||
4182 | /* X86_64_1F */ | |
4183 | { | |
bf890a93 | 4184 | { "popP", { ds }, 0 }, |
c0f3af97 L |
4185 | }, |
4186 | ||
4187 | /* X86_64_27 */ | |
4188 | { | |
bf890a93 | 4189 | { "daa", { XX }, 0 }, |
c0f3af97 L |
4190 | }, |
4191 | ||
4192 | /* X86_64_2F */ | |
4193 | { | |
bf890a93 | 4194 | { "das", { XX }, 0 }, |
c0f3af97 L |
4195 | }, |
4196 | ||
4197 | /* X86_64_37 */ | |
4198 | { | |
bf890a93 | 4199 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
4200 | }, |
4201 | ||
4202 | /* X86_64_3F */ | |
4203 | { | |
bf890a93 | 4204 | { "aas", { XX }, 0 }, |
c0f3af97 L |
4205 | }, |
4206 | ||
4207 | /* X86_64_60 */ | |
4208 | { | |
bf890a93 | 4209 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
4210 | }, |
4211 | ||
4212 | /* X86_64_61 */ | |
4213 | { | |
bf890a93 | 4214 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
4215 | }, |
4216 | ||
4217 | /* X86_64_62 */ | |
4218 | { | |
4219 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 4220 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
4221 | }, |
4222 | ||
4223 | /* X86_64_63 */ | |
4224 | { | |
bf890a93 | 4225 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 4226 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
4227 | }, |
4228 | ||
4229 | /* X86_64_6D */ | |
4230 | { | |
bf890a93 IT |
4231 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
4232 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
4233 | }, |
4234 | ||
4235 | /* X86_64_6F */ | |
4236 | { | |
bf890a93 IT |
4237 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
4238 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
4239 | }, |
4240 | ||
d039fef3 | 4241 | /* X86_64_82 */ |
8b89fe14 | 4242 | { |
de194d85 | 4243 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 4244 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
4245 | }, |
4246 | ||
c0f3af97 L |
4247 | /* X86_64_9A */ |
4248 | { | |
36938cab | 4249 | { "{l|}call{P|}", { Ap }, 0 }, |
c0f3af97 L |
4250 | }, |
4251 | ||
aeab2b26 JB |
4252 | /* X86_64_C2 */ |
4253 | { | |
4254 | { "retP", { Iw, BND }, 0 }, | |
4255 | { "ret@", { Iw, BND }, 0 }, | |
4256 | }, | |
4257 | ||
4258 | /* X86_64_C3 */ | |
4259 | { | |
4260 | { "retP", { BND }, 0 }, | |
4261 | { "ret@", { BND }, 0 }, | |
4262 | }, | |
4263 | ||
c0f3af97 L |
4264 | /* X86_64_C4 */ |
4265 | { | |
4266 | { MOD_TABLE (MOD_C4_32BIT) }, | |
4267 | { VEX_C4_TABLE (VEX_0F) }, | |
4268 | }, | |
4269 | ||
4270 | /* X86_64_C5 */ | |
4271 | { | |
4272 | { MOD_TABLE (MOD_C5_32BIT) }, | |
4273 | { VEX_C5_TABLE (VEX_0F) }, | |
4274 | }, | |
4275 | ||
4276 | /* X86_64_CE */ | |
4277 | { | |
bf890a93 | 4278 | { "into", { XX }, 0 }, |
c0f3af97 L |
4279 | }, |
4280 | ||
4281 | /* X86_64_D4 */ | |
4282 | { | |
bf890a93 | 4283 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
4284 | }, |
4285 | ||
4286 | /* X86_64_D5 */ | |
4287 | { | |
bf890a93 | 4288 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
4289 | }, |
4290 | ||
a72d2af2 L |
4291 | /* X86_64_E8 */ |
4292 | { | |
4293 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 4294 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
4295 | }, |
4296 | ||
4297 | /* X86_64_E9 */ | |
4298 | { | |
4299 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 4300 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
4301 | }, |
4302 | ||
c0f3af97 L |
4303 | /* X86_64_EA */ |
4304 | { | |
36938cab | 4305 | { "{l|}jmp{P|}", { Ap }, 0 }, |
c0f3af97 L |
4306 | }, |
4307 | ||
4308 | /* X86_64_0F01_REG_0 */ | |
4309 | { | |
d1c36125 | 4310 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 4311 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
4312 | }, |
4313 | ||
4314 | /* X86_64_0F01_REG_1 */ | |
4315 | { | |
d1c36125 | 4316 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 4317 | { "sidt", { M }, 0 }, |
c0f3af97 L |
4318 | }, |
4319 | ||
81d54bb7 CL |
4320 | /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ |
4321 | { | |
4322 | { Bad_Opcode }, | |
4323 | { "seamret", { Skip_MODRM }, 0 }, | |
4324 | }, | |
4325 | ||
4326 | /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */ | |
4327 | { | |
4328 | { Bad_Opcode }, | |
4329 | { "seamops", { Skip_MODRM }, 0 }, | |
4330 | }, | |
4331 | ||
4332 | /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */ | |
4333 | { | |
4334 | { Bad_Opcode }, | |
4335 | { "seamcall", { Skip_MODRM }, 0 }, | |
4336 | }, | |
4337 | ||
c0f3af97 L |
4338 | /* X86_64_0F01_REG_2 */ |
4339 | { | |
bf890a93 IT |
4340 | { "lgdt{Q|Q}", { M }, 0 }, |
4341 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
4342 | }, |
4343 | ||
4344 | /* X86_64_0F01_REG_3 */ | |
4345 | { | |
bf890a93 IT |
4346 | { "lidt{Q|Q}", { M }, 0 }, |
4347 | { "lidt", { M }, 0 }, | |
c0f3af97 | 4348 | }, |
260cd341 | 4349 | |
78467458 JB |
4350 | { |
4351 | /* X86_64_0F24 */ | |
4352 | { "movZ", { Em, Td }, 0 }, | |
4353 | }, | |
4354 | ||
4355 | { | |
4356 | /* X86_64_0F26 */ | |
4357 | { "movZ", { Td, Em }, 0 }, | |
4358 | }, | |
4359 | ||
260cd341 LC |
4360 | /* X86_64_VEX_0F3849 */ |
4361 | { | |
4362 | { Bad_Opcode }, | |
4363 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) }, | |
4364 | }, | |
4365 | ||
4366 | /* X86_64_VEX_0F384B */ | |
4367 | { | |
4368 | { Bad_Opcode }, | |
4369 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) }, | |
4370 | }, | |
4371 | ||
4372 | /* X86_64_VEX_0F385C */ | |
4373 | { | |
4374 | { Bad_Opcode }, | |
4375 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) }, | |
4376 | }, | |
4377 | ||
4378 | /* X86_64_VEX_0F385E */ | |
4379 | { | |
4380 | { Bad_Opcode }, | |
4381 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, | |
4382 | }, | |
f64c42a9 LC |
4383 | |
4384 | /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */ | |
4385 | { | |
4386 | { Bad_Opcode }, | |
4387 | { "uiret", { Skip_MODRM }, 0 }, | |
4388 | }, | |
4389 | ||
4390 | /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */ | |
4391 | { | |
4392 | { Bad_Opcode }, | |
4393 | { "testui", { Skip_MODRM }, 0 }, | |
4394 | }, | |
4395 | ||
4396 | /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */ | |
4397 | { | |
4398 | { Bad_Opcode }, | |
4399 | { "clui", { Skip_MODRM }, 0 }, | |
4400 | }, | |
4401 | ||
4402 | /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */ | |
4403 | { | |
4404 | { Bad_Opcode }, | |
4405 | { "stui", { Skip_MODRM }, 0 }, | |
4406 | }, | |
4407 | ||
646cc3e0 GG |
4408 | /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */ |
4409 | { | |
4410 | { Bad_Opcode }, | |
4411 | { "rmpadjust", { Skip_MODRM }, 0 }, | |
4412 | }, | |
4413 | ||
4414 | /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ | |
4415 | { | |
4416 | { Bad_Opcode }, | |
4417 | { "rmpupdate", { Skip_MODRM }, 0 }, | |
4418 | }, | |
4419 | ||
4420 | /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */ | |
4421 | { | |
4422 | { Bad_Opcode }, | |
4423 | { "psmash", { Skip_MODRM }, 0 }, | |
4424 | }, | |
4425 | ||
f64c42a9 LC |
4426 | /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ |
4427 | { | |
4428 | { Bad_Opcode }, | |
4429 | { "senduipi", { Eq }, 0 }, | |
4430 | }, | |
c0f3af97 L |
4431 | }; |
4432 | ||
4433 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
4434 | |
4435 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
4436 | { |
4437 | /* 00 */ | |
507bd325 L |
4438 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
4439 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
4440 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
4441 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
4442 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
4443 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
4444 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
4445 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 4446 | /* 08 */ |
507bd325 L |
4447 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
4448 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
4449 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
4450 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
4451 | { Bad_Opcode }, |
4452 | { Bad_Opcode }, | |
4453 | { Bad_Opcode }, | |
4454 | { Bad_Opcode }, | |
f88c9eb0 | 4455 | /* 10 */ |
7531c613 | 4456 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA }, |
592d1631 L |
4457 | { Bad_Opcode }, |
4458 | { Bad_Opcode }, | |
4459 | { Bad_Opcode }, | |
7531c613 JB |
4460 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA }, |
4461 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA }, | |
592d1631 | 4462 | { Bad_Opcode }, |
7531c613 | 4463 | { "ptest", { XM, EXx }, PREFIX_DATA }, |
f88c9eb0 | 4464 | /* 18 */ |
592d1631 L |
4465 | { Bad_Opcode }, |
4466 | { Bad_Opcode }, | |
4467 | { Bad_Opcode }, | |
4468 | { Bad_Opcode }, | |
507bd325 L |
4469 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
4470 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
4471 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 4472 | { Bad_Opcode }, |
f88c9eb0 | 4473 | /* 20 */ |
7531c613 JB |
4474 | { "pmovsxbw", { XM, EXq }, PREFIX_DATA }, |
4475 | { "pmovsxbd", { XM, EXd }, PREFIX_DATA }, | |
4476 | { "pmovsxbq", { XM, EXw }, PREFIX_DATA }, | |
4477 | { "pmovsxwd", { XM, EXq }, PREFIX_DATA }, | |
4478 | { "pmovsxwq", { XM, EXd }, PREFIX_DATA }, | |
4479 | { "pmovsxdq", { XM, EXq }, PREFIX_DATA }, | |
592d1631 L |
4480 | { Bad_Opcode }, |
4481 | { Bad_Opcode }, | |
f88c9eb0 | 4482 | /* 28 */ |
7531c613 JB |
4483 | { "pmuldq", { XM, EXx }, PREFIX_DATA }, |
4484 | { "pcmpeqq", { XM, EXx }, PREFIX_DATA }, | |
4485 | { MOD_TABLE (MOD_0F382A) }, | |
4486 | { "packusdw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4487 | { Bad_Opcode }, |
4488 | { Bad_Opcode }, | |
4489 | { Bad_Opcode }, | |
4490 | { Bad_Opcode }, | |
f88c9eb0 | 4491 | /* 30 */ |
7531c613 JB |
4492 | { "pmovzxbw", { XM, EXq }, PREFIX_DATA }, |
4493 | { "pmovzxbd", { XM, EXd }, PREFIX_DATA }, | |
4494 | { "pmovzxbq", { XM, EXw }, PREFIX_DATA }, | |
4495 | { "pmovzxwd", { XM, EXq }, PREFIX_DATA }, | |
4496 | { "pmovzxwq", { XM, EXd }, PREFIX_DATA }, | |
4497 | { "pmovzxdq", { XM, EXq }, PREFIX_DATA }, | |
4498 | { Bad_Opcode }, | |
4499 | { "pcmpgtq", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4500 | /* 38 */ |
7531c613 JB |
4501 | { "pminsb", { XM, EXx }, PREFIX_DATA }, |
4502 | { "pminsd", { XM, EXx }, PREFIX_DATA }, | |
4503 | { "pminuw", { XM, EXx }, PREFIX_DATA }, | |
4504 | { "pminud", { XM, EXx }, PREFIX_DATA }, | |
4505 | { "pmaxsb", { XM, EXx }, PREFIX_DATA }, | |
4506 | { "pmaxsd", { XM, EXx }, PREFIX_DATA }, | |
4507 | { "pmaxuw", { XM, EXx }, PREFIX_DATA }, | |
4508 | { "pmaxud", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4509 | /* 40 */ |
7531c613 JB |
4510 | { "pmulld", { XM, EXx }, PREFIX_DATA }, |
4511 | { "phminposuw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4512 | { Bad_Opcode }, |
4513 | { Bad_Opcode }, | |
4514 | { Bad_Opcode }, | |
4515 | { Bad_Opcode }, | |
4516 | { Bad_Opcode }, | |
4517 | { Bad_Opcode }, | |
f88c9eb0 | 4518 | /* 48 */ |
592d1631 L |
4519 | { Bad_Opcode }, |
4520 | { Bad_Opcode }, | |
4521 | { Bad_Opcode }, | |
4522 | { Bad_Opcode }, | |
4523 | { Bad_Opcode }, | |
4524 | { Bad_Opcode }, | |
4525 | { Bad_Opcode }, | |
4526 | { Bad_Opcode }, | |
f88c9eb0 | 4527 | /* 50 */ |
592d1631 L |
4528 | { Bad_Opcode }, |
4529 | { Bad_Opcode }, | |
4530 | { Bad_Opcode }, | |
4531 | { Bad_Opcode }, | |
4532 | { Bad_Opcode }, | |
4533 | { Bad_Opcode }, | |
4534 | { Bad_Opcode }, | |
4535 | { Bad_Opcode }, | |
f88c9eb0 | 4536 | /* 58 */ |
592d1631 L |
4537 | { Bad_Opcode }, |
4538 | { Bad_Opcode }, | |
4539 | { Bad_Opcode }, | |
4540 | { Bad_Opcode }, | |
4541 | { Bad_Opcode }, | |
4542 | { Bad_Opcode }, | |
4543 | { Bad_Opcode }, | |
4544 | { Bad_Opcode }, | |
f88c9eb0 | 4545 | /* 60 */ |
592d1631 L |
4546 | { Bad_Opcode }, |
4547 | { Bad_Opcode }, | |
4548 | { Bad_Opcode }, | |
4549 | { Bad_Opcode }, | |
4550 | { Bad_Opcode }, | |
4551 | { Bad_Opcode }, | |
4552 | { Bad_Opcode }, | |
4553 | { Bad_Opcode }, | |
f88c9eb0 | 4554 | /* 68 */ |
592d1631 L |
4555 | { Bad_Opcode }, |
4556 | { Bad_Opcode }, | |
4557 | { Bad_Opcode }, | |
4558 | { Bad_Opcode }, | |
4559 | { Bad_Opcode }, | |
4560 | { Bad_Opcode }, | |
4561 | { Bad_Opcode }, | |
4562 | { Bad_Opcode }, | |
f88c9eb0 | 4563 | /* 70 */ |
592d1631 L |
4564 | { Bad_Opcode }, |
4565 | { Bad_Opcode }, | |
4566 | { Bad_Opcode }, | |
4567 | { Bad_Opcode }, | |
4568 | { Bad_Opcode }, | |
4569 | { Bad_Opcode }, | |
4570 | { Bad_Opcode }, | |
4571 | { Bad_Opcode }, | |
f88c9eb0 | 4572 | /* 78 */ |
592d1631 L |
4573 | { Bad_Opcode }, |
4574 | { Bad_Opcode }, | |
4575 | { Bad_Opcode }, | |
4576 | { Bad_Opcode }, | |
4577 | { Bad_Opcode }, | |
4578 | { Bad_Opcode }, | |
4579 | { Bad_Opcode }, | |
4580 | { Bad_Opcode }, | |
f88c9eb0 | 4581 | /* 80 */ |
7531c613 JB |
4582 | { "invept", { Gm, Mo }, PREFIX_DATA }, |
4583 | { "invvpid", { Gm, Mo }, PREFIX_DATA }, | |
4584 | { "invpcid", { Gm, M }, PREFIX_DATA }, | |
592d1631 L |
4585 | { Bad_Opcode }, |
4586 | { Bad_Opcode }, | |
4587 | { Bad_Opcode }, | |
4588 | { Bad_Opcode }, | |
4589 | { Bad_Opcode }, | |
f88c9eb0 | 4590 | /* 88 */ |
592d1631 L |
4591 | { Bad_Opcode }, |
4592 | { Bad_Opcode }, | |
4593 | { Bad_Opcode }, | |
4594 | { Bad_Opcode }, | |
4595 | { Bad_Opcode }, | |
4596 | { Bad_Opcode }, | |
4597 | { Bad_Opcode }, | |
4598 | { Bad_Opcode }, | |
f88c9eb0 | 4599 | /* 90 */ |
592d1631 L |
4600 | { Bad_Opcode }, |
4601 | { Bad_Opcode }, | |
4602 | { Bad_Opcode }, | |
4603 | { Bad_Opcode }, | |
4604 | { Bad_Opcode }, | |
4605 | { Bad_Opcode }, | |
4606 | { Bad_Opcode }, | |
4607 | { Bad_Opcode }, | |
f88c9eb0 | 4608 | /* 98 */ |
592d1631 L |
4609 | { Bad_Opcode }, |
4610 | { Bad_Opcode }, | |
4611 | { Bad_Opcode }, | |
4612 | { Bad_Opcode }, | |
4613 | { Bad_Opcode }, | |
4614 | { Bad_Opcode }, | |
4615 | { Bad_Opcode }, | |
4616 | { Bad_Opcode }, | |
f88c9eb0 | 4617 | /* a0 */ |
592d1631 L |
4618 | { Bad_Opcode }, |
4619 | { Bad_Opcode }, | |
4620 | { Bad_Opcode }, | |
4621 | { Bad_Opcode }, | |
4622 | { Bad_Opcode }, | |
4623 | { Bad_Opcode }, | |
4624 | { Bad_Opcode }, | |
4625 | { Bad_Opcode }, | |
f88c9eb0 | 4626 | /* a8 */ |
592d1631 L |
4627 | { Bad_Opcode }, |
4628 | { Bad_Opcode }, | |
4629 | { Bad_Opcode }, | |
4630 | { Bad_Opcode }, | |
4631 | { Bad_Opcode }, | |
4632 | { Bad_Opcode }, | |
4633 | { Bad_Opcode }, | |
4634 | { Bad_Opcode }, | |
f88c9eb0 | 4635 | /* b0 */ |
592d1631 L |
4636 | { Bad_Opcode }, |
4637 | { Bad_Opcode }, | |
4638 | { Bad_Opcode }, | |
4639 | { Bad_Opcode }, | |
4640 | { Bad_Opcode }, | |
4641 | { Bad_Opcode }, | |
4642 | { Bad_Opcode }, | |
4643 | { Bad_Opcode }, | |
f88c9eb0 | 4644 | /* b8 */ |
592d1631 L |
4645 | { Bad_Opcode }, |
4646 | { Bad_Opcode }, | |
4647 | { Bad_Opcode }, | |
4648 | { Bad_Opcode }, | |
4649 | { Bad_Opcode }, | |
4650 | { Bad_Opcode }, | |
4651 | { Bad_Opcode }, | |
4652 | { Bad_Opcode }, | |
f88c9eb0 | 4653 | /* c0 */ |
592d1631 L |
4654 | { Bad_Opcode }, |
4655 | { Bad_Opcode }, | |
4656 | { Bad_Opcode }, | |
4657 | { Bad_Opcode }, | |
4658 | { Bad_Opcode }, | |
4659 | { Bad_Opcode }, | |
4660 | { Bad_Opcode }, | |
4661 | { Bad_Opcode }, | |
f88c9eb0 | 4662 | /* c8 */ |
035e7389 JB |
4663 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
4664 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4665 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
4666 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, | |
4667 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4668 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
592d1631 | 4669 | { Bad_Opcode }, |
7531c613 | 4670 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA }, |
f88c9eb0 | 4671 | /* d0 */ |
592d1631 L |
4672 | { Bad_Opcode }, |
4673 | { Bad_Opcode }, | |
4674 | { Bad_Opcode }, | |
4675 | { Bad_Opcode }, | |
4676 | { Bad_Opcode }, | |
4677 | { Bad_Opcode }, | |
4678 | { Bad_Opcode }, | |
4679 | { Bad_Opcode }, | |
f88c9eb0 | 4680 | /* d8 */ |
c4694f17 | 4681 | { PREFIX_TABLE (PREFIX_0F38D8) }, |
592d1631 L |
4682 | { Bad_Opcode }, |
4683 | { Bad_Opcode }, | |
7531c613 | 4684 | { "aesimc", { XM, EXx }, PREFIX_DATA }, |
c4694f17 TG |
4685 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
4686 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
4687 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
4688 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
f88c9eb0 | 4689 | /* e0 */ |
592d1631 L |
4690 | { Bad_Opcode }, |
4691 | { Bad_Opcode }, | |
4692 | { Bad_Opcode }, | |
4693 | { Bad_Opcode }, | |
4694 | { Bad_Opcode }, | |
4695 | { Bad_Opcode }, | |
4696 | { Bad_Opcode }, | |
4697 | { Bad_Opcode }, | |
f88c9eb0 | 4698 | /* e8 */ |
592d1631 L |
4699 | { Bad_Opcode }, |
4700 | { Bad_Opcode }, | |
4701 | { Bad_Opcode }, | |
4702 | { Bad_Opcode }, | |
4703 | { Bad_Opcode }, | |
4704 | { Bad_Opcode }, | |
4705 | { Bad_Opcode }, | |
4706 | { Bad_Opcode }, | |
f88c9eb0 SP |
4707 | /* f0 */ |
4708 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
4709 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
4710 | { Bad_Opcode }, |
4711 | { Bad_Opcode }, | |
4712 | { Bad_Opcode }, | |
7531c613 | 4713 | { MOD_TABLE (MOD_0F38F5) }, |
e2e1fcde | 4714 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 4715 | { Bad_Opcode }, |
f88c9eb0 | 4716 | /* f8 */ |
c0a30a9f | 4717 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
035e7389 | 4718 | { MOD_TABLE (MOD_0F38F9) }, |
c4694f17 TG |
4719 | { PREFIX_TABLE (PREFIX_0F38FA) }, |
4720 | { PREFIX_TABLE (PREFIX_0F38FB) }, | |
592d1631 L |
4721 | { Bad_Opcode }, |
4722 | { Bad_Opcode }, | |
4723 | { Bad_Opcode }, | |
4724 | { Bad_Opcode }, | |
f88c9eb0 SP |
4725 | }, |
4726 | /* THREE_BYTE_0F3A */ | |
4727 | { | |
4728 | /* 00 */ | |
592d1631 L |
4729 | { Bad_Opcode }, |
4730 | { Bad_Opcode }, | |
4731 | { Bad_Opcode }, | |
4732 | { Bad_Opcode }, | |
4733 | { Bad_Opcode }, | |
4734 | { Bad_Opcode }, | |
4735 | { Bad_Opcode }, | |
4736 | { Bad_Opcode }, | |
f88c9eb0 | 4737 | /* 08 */ |
7531c613 JB |
4738 | { "roundps", { XM, EXx, Ib }, PREFIX_DATA }, |
4739 | { "roundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4740 | { "roundss", { XM, EXd, Ib }, PREFIX_DATA }, | |
4741 | { "roundsd", { XM, EXq, Ib }, PREFIX_DATA }, | |
4742 | { "blendps", { XM, EXx, Ib }, PREFIX_DATA }, | |
4743 | { "blendpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4744 | { "pblendw", { XM, EXx, Ib }, PREFIX_DATA }, | |
507bd325 | 4745 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 4746 | /* 10 */ |
592d1631 L |
4747 | { Bad_Opcode }, |
4748 | { Bad_Opcode }, | |
4749 | { Bad_Opcode }, | |
4750 | { Bad_Opcode }, | |
7531c613 JB |
4751 | { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA }, |
4752 | { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA }, | |
4753 | { "pextrK", { Edq, XM, Ib }, PREFIX_DATA }, | |
4754 | { "extractps", { Edqd, XM, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4755 | /* 18 */ |
592d1631 L |
4756 | { Bad_Opcode }, |
4757 | { Bad_Opcode }, | |
4758 | { Bad_Opcode }, | |
4759 | { Bad_Opcode }, | |
4760 | { Bad_Opcode }, | |
4761 | { Bad_Opcode }, | |
4762 | { Bad_Opcode }, | |
4763 | { Bad_Opcode }, | |
f88c9eb0 | 4764 | /* 20 */ |
7531c613 JB |
4765 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA }, |
4766 | { "insertps", { XM, EXd, Ib }, PREFIX_DATA }, | |
4767 | { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA }, | |
592d1631 L |
4768 | { Bad_Opcode }, |
4769 | { Bad_Opcode }, | |
4770 | { Bad_Opcode }, | |
4771 | { Bad_Opcode }, | |
4772 | { Bad_Opcode }, | |
f88c9eb0 | 4773 | /* 28 */ |
592d1631 L |
4774 | { Bad_Opcode }, |
4775 | { Bad_Opcode }, | |
4776 | { Bad_Opcode }, | |
4777 | { Bad_Opcode }, | |
4778 | { Bad_Opcode }, | |
4779 | { Bad_Opcode }, | |
4780 | { Bad_Opcode }, | |
4781 | { Bad_Opcode }, | |
f88c9eb0 | 4782 | /* 30 */ |
592d1631 L |
4783 | { Bad_Opcode }, |
4784 | { Bad_Opcode }, | |
4785 | { Bad_Opcode }, | |
4786 | { Bad_Opcode }, | |
4787 | { Bad_Opcode }, | |
4788 | { Bad_Opcode }, | |
4789 | { Bad_Opcode }, | |
4790 | { Bad_Opcode }, | |
f88c9eb0 | 4791 | /* 38 */ |
592d1631 L |
4792 | { Bad_Opcode }, |
4793 | { Bad_Opcode }, | |
4794 | { Bad_Opcode }, | |
4795 | { Bad_Opcode }, | |
4796 | { Bad_Opcode }, | |
4797 | { Bad_Opcode }, | |
4798 | { Bad_Opcode }, | |
4799 | { Bad_Opcode }, | |
f88c9eb0 | 4800 | /* 40 */ |
7531c613 JB |
4801 | { "dpps", { XM, EXx, Ib }, PREFIX_DATA }, |
4802 | { "dppd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4803 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 4804 | { Bad_Opcode }, |
7531c613 | 4805 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 L |
4806 | { Bad_Opcode }, |
4807 | { Bad_Opcode }, | |
4808 | { Bad_Opcode }, | |
f88c9eb0 | 4809 | /* 48 */ |
592d1631 L |
4810 | { Bad_Opcode }, |
4811 | { Bad_Opcode }, | |
4812 | { Bad_Opcode }, | |
4813 | { Bad_Opcode }, | |
4814 | { Bad_Opcode }, | |
4815 | { Bad_Opcode }, | |
4816 | { Bad_Opcode }, | |
4817 | { Bad_Opcode }, | |
f88c9eb0 | 4818 | /* 50 */ |
592d1631 L |
4819 | { Bad_Opcode }, |
4820 | { Bad_Opcode }, | |
4821 | { Bad_Opcode }, | |
4822 | { Bad_Opcode }, | |
4823 | { Bad_Opcode }, | |
4824 | { Bad_Opcode }, | |
4825 | { Bad_Opcode }, | |
4826 | { Bad_Opcode }, | |
f88c9eb0 | 4827 | /* 58 */ |
592d1631 L |
4828 | { Bad_Opcode }, |
4829 | { Bad_Opcode }, | |
4830 | { Bad_Opcode }, | |
4831 | { Bad_Opcode }, | |
4832 | { Bad_Opcode }, | |
4833 | { Bad_Opcode }, | |
4834 | { Bad_Opcode }, | |
4835 | { Bad_Opcode }, | |
f88c9eb0 | 4836 | /* 60 */ |
7531c613 JB |
4837 | { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
4838 | { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, | |
4839 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, | |
4840 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 L |
4841 | { Bad_Opcode }, |
4842 | { Bad_Opcode }, | |
4843 | { Bad_Opcode }, | |
4844 | { Bad_Opcode }, | |
f88c9eb0 | 4845 | /* 68 */ |
592d1631 L |
4846 | { Bad_Opcode }, |
4847 | { Bad_Opcode }, | |
4848 | { Bad_Opcode }, | |
4849 | { Bad_Opcode }, | |
4850 | { Bad_Opcode }, | |
4851 | { Bad_Opcode }, | |
4852 | { Bad_Opcode }, | |
4853 | { Bad_Opcode }, | |
f88c9eb0 | 4854 | /* 70 */ |
592d1631 L |
4855 | { Bad_Opcode }, |
4856 | { Bad_Opcode }, | |
4857 | { Bad_Opcode }, | |
4858 | { Bad_Opcode }, | |
4859 | { Bad_Opcode }, | |
4860 | { Bad_Opcode }, | |
4861 | { Bad_Opcode }, | |
4862 | { Bad_Opcode }, | |
f88c9eb0 | 4863 | /* 78 */ |
592d1631 L |
4864 | { Bad_Opcode }, |
4865 | { Bad_Opcode }, | |
4866 | { Bad_Opcode }, | |
4867 | { Bad_Opcode }, | |
4868 | { Bad_Opcode }, | |
4869 | { Bad_Opcode }, | |
4870 | { Bad_Opcode }, | |
4871 | { Bad_Opcode }, | |
f88c9eb0 | 4872 | /* 80 */ |
592d1631 L |
4873 | { Bad_Opcode }, |
4874 | { Bad_Opcode }, | |
4875 | { Bad_Opcode }, | |
4876 | { Bad_Opcode }, | |
4877 | { Bad_Opcode }, | |
4878 | { Bad_Opcode }, | |
4879 | { Bad_Opcode }, | |
4880 | { Bad_Opcode }, | |
f88c9eb0 | 4881 | /* 88 */ |
592d1631 L |
4882 | { Bad_Opcode }, |
4883 | { Bad_Opcode }, | |
4884 | { Bad_Opcode }, | |
4885 | { Bad_Opcode }, | |
4886 | { Bad_Opcode }, | |
4887 | { Bad_Opcode }, | |
4888 | { Bad_Opcode }, | |
4889 | { Bad_Opcode }, | |
f88c9eb0 | 4890 | /* 90 */ |
592d1631 L |
4891 | { Bad_Opcode }, |
4892 | { Bad_Opcode }, | |
4893 | { Bad_Opcode }, | |
4894 | { Bad_Opcode }, | |
4895 | { Bad_Opcode }, | |
4896 | { Bad_Opcode }, | |
4897 | { Bad_Opcode }, | |
4898 | { Bad_Opcode }, | |
f88c9eb0 | 4899 | /* 98 */ |
592d1631 L |
4900 | { Bad_Opcode }, |
4901 | { Bad_Opcode }, | |
4902 | { Bad_Opcode }, | |
4903 | { Bad_Opcode }, | |
4904 | { Bad_Opcode }, | |
4905 | { Bad_Opcode }, | |
4906 | { Bad_Opcode }, | |
4907 | { Bad_Opcode }, | |
f88c9eb0 | 4908 | /* a0 */ |
592d1631 L |
4909 | { Bad_Opcode }, |
4910 | { Bad_Opcode }, | |
4911 | { Bad_Opcode }, | |
4912 | { Bad_Opcode }, | |
4913 | { Bad_Opcode }, | |
4914 | { Bad_Opcode }, | |
4915 | { Bad_Opcode }, | |
4916 | { Bad_Opcode }, | |
f88c9eb0 | 4917 | /* a8 */ |
592d1631 L |
4918 | { Bad_Opcode }, |
4919 | { Bad_Opcode }, | |
4920 | { Bad_Opcode }, | |
4921 | { Bad_Opcode }, | |
4922 | { Bad_Opcode }, | |
4923 | { Bad_Opcode }, | |
4924 | { Bad_Opcode }, | |
4925 | { Bad_Opcode }, | |
f88c9eb0 | 4926 | /* b0 */ |
592d1631 L |
4927 | { Bad_Opcode }, |
4928 | { Bad_Opcode }, | |
4929 | { Bad_Opcode }, | |
4930 | { Bad_Opcode }, | |
4931 | { Bad_Opcode }, | |
4932 | { Bad_Opcode }, | |
4933 | { Bad_Opcode }, | |
4934 | { Bad_Opcode }, | |
f88c9eb0 | 4935 | /* b8 */ |
592d1631 L |
4936 | { Bad_Opcode }, |
4937 | { Bad_Opcode }, | |
4938 | { Bad_Opcode }, | |
4939 | { Bad_Opcode }, | |
4940 | { Bad_Opcode }, | |
4941 | { Bad_Opcode }, | |
4942 | { Bad_Opcode }, | |
4943 | { Bad_Opcode }, | |
f88c9eb0 | 4944 | /* c0 */ |
592d1631 L |
4945 | { Bad_Opcode }, |
4946 | { Bad_Opcode }, | |
4947 | { Bad_Opcode }, | |
4948 | { Bad_Opcode }, | |
4949 | { Bad_Opcode }, | |
4950 | { Bad_Opcode }, | |
4951 | { Bad_Opcode }, | |
4952 | { Bad_Opcode }, | |
f88c9eb0 | 4953 | /* c8 */ |
592d1631 L |
4954 | { Bad_Opcode }, |
4955 | { Bad_Opcode }, | |
4956 | { Bad_Opcode }, | |
4957 | { Bad_Opcode }, | |
035e7389 | 4958 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
592d1631 | 4959 | { Bad_Opcode }, |
7531c613 JB |
4960 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA }, |
4961 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4962 | /* d0 */ |
592d1631 L |
4963 | { Bad_Opcode }, |
4964 | { Bad_Opcode }, | |
4965 | { Bad_Opcode }, | |
4966 | { Bad_Opcode }, | |
4967 | { Bad_Opcode }, | |
4968 | { Bad_Opcode }, | |
4969 | { Bad_Opcode }, | |
4970 | { Bad_Opcode }, | |
f88c9eb0 | 4971 | /* d8 */ |
592d1631 L |
4972 | { Bad_Opcode }, |
4973 | { Bad_Opcode }, | |
4974 | { Bad_Opcode }, | |
4975 | { Bad_Opcode }, | |
4976 | { Bad_Opcode }, | |
4977 | { Bad_Opcode }, | |
4978 | { Bad_Opcode }, | |
7531c613 | 4979 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
f88c9eb0 | 4980 | /* e0 */ |
592d1631 L |
4981 | { Bad_Opcode }, |
4982 | { Bad_Opcode }, | |
4983 | { Bad_Opcode }, | |
4984 | { Bad_Opcode }, | |
4985 | { Bad_Opcode }, | |
592d1631 L |
4986 | { Bad_Opcode }, |
4987 | { Bad_Opcode }, | |
4988 | { Bad_Opcode }, | |
85f10a01 | 4989 | /* e8 */ |
592d1631 L |
4990 | { Bad_Opcode }, |
4991 | { Bad_Opcode }, | |
4992 | { Bad_Opcode }, | |
4993 | { Bad_Opcode }, | |
4994 | { Bad_Opcode }, | |
4995 | { Bad_Opcode }, | |
4996 | { Bad_Opcode }, | |
4997 | { Bad_Opcode }, | |
85f10a01 | 4998 | /* f0 */ |
c1fa250a | 4999 | { PREFIX_TABLE (PREFIX_0F3A0F) }, |
592d1631 L |
5000 | { Bad_Opcode }, |
5001 | { Bad_Opcode }, | |
5002 | { Bad_Opcode }, | |
5003 | { Bad_Opcode }, | |
5004 | { Bad_Opcode }, | |
5005 | { Bad_Opcode }, | |
5006 | { Bad_Opcode }, | |
85f10a01 | 5007 | /* f8 */ |
592d1631 L |
5008 | { Bad_Opcode }, |
5009 | { Bad_Opcode }, | |
5010 | { Bad_Opcode }, | |
5011 | { Bad_Opcode }, | |
5012 | { Bad_Opcode }, | |
5013 | { Bad_Opcode }, | |
5014 | { Bad_Opcode }, | |
5015 | { Bad_Opcode }, | |
85f10a01 | 5016 | }, |
f88c9eb0 SP |
5017 | }; |
5018 | ||
5019 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 5020 | /* XOP_08 */ |
85f10a01 MM |
5021 | { |
5022 | /* 00 */ | |
592d1631 L |
5023 | { Bad_Opcode }, |
5024 | { Bad_Opcode }, | |
5025 | { Bad_Opcode }, | |
5026 | { Bad_Opcode }, | |
5027 | { Bad_Opcode }, | |
5028 | { Bad_Opcode }, | |
5029 | { Bad_Opcode }, | |
5030 | { Bad_Opcode }, | |
85f10a01 | 5031 | /* 08 */ |
592d1631 L |
5032 | { Bad_Opcode }, |
5033 | { Bad_Opcode }, | |
5034 | { Bad_Opcode }, | |
5035 | { Bad_Opcode }, | |
5036 | { Bad_Opcode }, | |
5037 | { Bad_Opcode }, | |
5038 | { Bad_Opcode }, | |
5039 | { Bad_Opcode }, | |
85f10a01 | 5040 | /* 10 */ |
3929df09 | 5041 | { Bad_Opcode }, |
592d1631 L |
5042 | { Bad_Opcode }, |
5043 | { Bad_Opcode }, | |
5044 | { Bad_Opcode }, | |
5045 | { Bad_Opcode }, | |
5046 | { Bad_Opcode }, | |
5047 | { Bad_Opcode }, | |
5048 | { Bad_Opcode }, | |
85f10a01 | 5049 | /* 18 */ |
592d1631 L |
5050 | { Bad_Opcode }, |
5051 | { Bad_Opcode }, | |
5052 | { Bad_Opcode }, | |
5053 | { Bad_Opcode }, | |
5054 | { Bad_Opcode }, | |
5055 | { Bad_Opcode }, | |
5056 | { Bad_Opcode }, | |
5057 | { Bad_Opcode }, | |
85f10a01 | 5058 | /* 20 */ |
592d1631 L |
5059 | { Bad_Opcode }, |
5060 | { Bad_Opcode }, | |
5061 | { Bad_Opcode }, | |
5062 | { Bad_Opcode }, | |
5063 | { Bad_Opcode }, | |
5064 | { Bad_Opcode }, | |
5065 | { Bad_Opcode }, | |
5066 | { Bad_Opcode }, | |
85f10a01 | 5067 | /* 28 */ |
592d1631 L |
5068 | { Bad_Opcode }, |
5069 | { Bad_Opcode }, | |
5070 | { Bad_Opcode }, | |
5071 | { Bad_Opcode }, | |
5072 | { Bad_Opcode }, | |
5073 | { Bad_Opcode }, | |
5074 | { Bad_Opcode }, | |
5075 | { Bad_Opcode }, | |
c0f3af97 | 5076 | /* 30 */ |
592d1631 L |
5077 | { Bad_Opcode }, |
5078 | { Bad_Opcode }, | |
5079 | { Bad_Opcode }, | |
5080 | { Bad_Opcode }, | |
5081 | { Bad_Opcode }, | |
5082 | { Bad_Opcode }, | |
5083 | { Bad_Opcode }, | |
5084 | { Bad_Opcode }, | |
c0f3af97 | 5085 | /* 38 */ |
592d1631 L |
5086 | { Bad_Opcode }, |
5087 | { Bad_Opcode }, | |
5088 | { Bad_Opcode }, | |
5089 | { Bad_Opcode }, | |
5090 | { Bad_Opcode }, | |
5091 | { Bad_Opcode }, | |
5092 | { Bad_Opcode }, | |
5093 | { Bad_Opcode }, | |
c0f3af97 | 5094 | /* 40 */ |
592d1631 L |
5095 | { Bad_Opcode }, |
5096 | { Bad_Opcode }, | |
5097 | { Bad_Opcode }, | |
5098 | { Bad_Opcode }, | |
5099 | { Bad_Opcode }, | |
5100 | { Bad_Opcode }, | |
5101 | { Bad_Opcode }, | |
5102 | { Bad_Opcode }, | |
85f10a01 | 5103 | /* 48 */ |
592d1631 L |
5104 | { Bad_Opcode }, |
5105 | { Bad_Opcode }, | |
5106 | { Bad_Opcode }, | |
5107 | { Bad_Opcode }, | |
5108 | { Bad_Opcode }, | |
5109 | { Bad_Opcode }, | |
5110 | { Bad_Opcode }, | |
5111 | { Bad_Opcode }, | |
c0f3af97 | 5112 | /* 50 */ |
592d1631 L |
5113 | { Bad_Opcode }, |
5114 | { Bad_Opcode }, | |
5115 | { Bad_Opcode }, | |
5116 | { Bad_Opcode }, | |
5117 | { Bad_Opcode }, | |
5118 | { Bad_Opcode }, | |
5119 | { Bad_Opcode }, | |
5120 | { Bad_Opcode }, | |
85f10a01 | 5121 | /* 58 */ |
592d1631 L |
5122 | { Bad_Opcode }, |
5123 | { Bad_Opcode }, | |
5124 | { Bad_Opcode }, | |
5125 | { Bad_Opcode }, | |
5126 | { Bad_Opcode }, | |
5127 | { Bad_Opcode }, | |
5128 | { Bad_Opcode }, | |
5129 | { Bad_Opcode }, | |
c1e679ec | 5130 | /* 60 */ |
592d1631 L |
5131 | { Bad_Opcode }, |
5132 | { Bad_Opcode }, | |
5133 | { Bad_Opcode }, | |
5134 | { Bad_Opcode }, | |
5135 | { Bad_Opcode }, | |
5136 | { Bad_Opcode }, | |
5137 | { Bad_Opcode }, | |
5138 | { Bad_Opcode }, | |
c0f3af97 | 5139 | /* 68 */ |
592d1631 L |
5140 | { Bad_Opcode }, |
5141 | { Bad_Opcode }, | |
5142 | { Bad_Opcode }, | |
5143 | { Bad_Opcode }, | |
5144 | { Bad_Opcode }, | |
5145 | { Bad_Opcode }, | |
5146 | { Bad_Opcode }, | |
5147 | { Bad_Opcode }, | |
85f10a01 | 5148 | /* 70 */ |
592d1631 L |
5149 | { Bad_Opcode }, |
5150 | { Bad_Opcode }, | |
5151 | { Bad_Opcode }, | |
5152 | { Bad_Opcode }, | |
5153 | { Bad_Opcode }, | |
5154 | { Bad_Opcode }, | |
5155 | { Bad_Opcode }, | |
5156 | { Bad_Opcode }, | |
85f10a01 | 5157 | /* 78 */ |
592d1631 L |
5158 | { Bad_Opcode }, |
5159 | { Bad_Opcode }, | |
5160 | { Bad_Opcode }, | |
5161 | { Bad_Opcode }, | |
5162 | { Bad_Opcode }, | |
5163 | { Bad_Opcode }, | |
5164 | { Bad_Opcode }, | |
5165 | { Bad_Opcode }, | |
85f10a01 | 5166 | /* 80 */ |
592d1631 L |
5167 | { Bad_Opcode }, |
5168 | { Bad_Opcode }, | |
5169 | { Bad_Opcode }, | |
5170 | { Bad_Opcode }, | |
5171 | { Bad_Opcode }, | |
467bbef0 JB |
5172 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) }, |
5173 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) }, | |
5174 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) }, | |
5dd85c99 | 5175 | /* 88 */ |
592d1631 L |
5176 | { Bad_Opcode }, |
5177 | { Bad_Opcode }, | |
5178 | { Bad_Opcode }, | |
5179 | { Bad_Opcode }, | |
5180 | { Bad_Opcode }, | |
5181 | { Bad_Opcode }, | |
467bbef0 JB |
5182 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) }, |
5183 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) }, | |
5dd85c99 | 5184 | /* 90 */ |
592d1631 L |
5185 | { Bad_Opcode }, |
5186 | { Bad_Opcode }, | |
5187 | { Bad_Opcode }, | |
5188 | { Bad_Opcode }, | |
5189 | { Bad_Opcode }, | |
467bbef0 JB |
5190 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) }, |
5191 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) }, | |
5192 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) }, | |
5dd85c99 | 5193 | /* 98 */ |
592d1631 L |
5194 | { Bad_Opcode }, |
5195 | { Bad_Opcode }, | |
5196 | { Bad_Opcode }, | |
5197 | { Bad_Opcode }, | |
5198 | { Bad_Opcode }, | |
5199 | { Bad_Opcode }, | |
467bbef0 JB |
5200 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) }, |
5201 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) }, | |
5dd85c99 | 5202 | /* a0 */ |
592d1631 L |
5203 | { Bad_Opcode }, |
5204 | { Bad_Opcode }, | |
b13b1bc0 | 5205 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
467bbef0 | 5206 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) }, |
592d1631 L |
5207 | { Bad_Opcode }, |
5208 | { Bad_Opcode }, | |
467bbef0 | 5209 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) }, |
592d1631 | 5210 | { Bad_Opcode }, |
5dd85c99 | 5211 | /* a8 */ |
592d1631 L |
5212 | { Bad_Opcode }, |
5213 | { Bad_Opcode }, | |
5214 | { Bad_Opcode }, | |
5215 | { Bad_Opcode }, | |
5216 | { Bad_Opcode }, | |
5217 | { Bad_Opcode }, | |
5218 | { Bad_Opcode }, | |
5219 | { Bad_Opcode }, | |
5dd85c99 | 5220 | /* b0 */ |
592d1631 L |
5221 | { Bad_Opcode }, |
5222 | { Bad_Opcode }, | |
5223 | { Bad_Opcode }, | |
5224 | { Bad_Opcode }, | |
5225 | { Bad_Opcode }, | |
5226 | { Bad_Opcode }, | |
467bbef0 | 5227 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) }, |
592d1631 | 5228 | { Bad_Opcode }, |
5dd85c99 | 5229 | /* b8 */ |
592d1631 L |
5230 | { Bad_Opcode }, |
5231 | { Bad_Opcode }, | |
5232 | { Bad_Opcode }, | |
5233 | { Bad_Opcode }, | |
5234 | { Bad_Opcode }, | |
5235 | { Bad_Opcode }, | |
5236 | { Bad_Opcode }, | |
5237 | { Bad_Opcode }, | |
5dd85c99 | 5238 | /* c0 */ |
467bbef0 JB |
5239 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) }, |
5240 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) }, | |
5241 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) }, | |
5242 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) }, | |
592d1631 L |
5243 | { Bad_Opcode }, |
5244 | { Bad_Opcode }, | |
5245 | { Bad_Opcode }, | |
5246 | { Bad_Opcode }, | |
5dd85c99 | 5247 | /* c8 */ |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
5250 | { Bad_Opcode }, | |
5251 | { Bad_Opcode }, | |
ff688e1f L |
5252 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
5253 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
5254 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
5255 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 5256 | /* d0 */ |
592d1631 L |
5257 | { Bad_Opcode }, |
5258 | { Bad_Opcode }, | |
5259 | { Bad_Opcode }, | |
5260 | { Bad_Opcode }, | |
5261 | { Bad_Opcode }, | |
5262 | { Bad_Opcode }, | |
5263 | { Bad_Opcode }, | |
5264 | { Bad_Opcode }, | |
5dd85c99 | 5265 | /* d8 */ |
592d1631 L |
5266 | { Bad_Opcode }, |
5267 | { Bad_Opcode }, | |
5268 | { Bad_Opcode }, | |
5269 | { Bad_Opcode }, | |
5270 | { Bad_Opcode }, | |
5271 | { Bad_Opcode }, | |
5272 | { Bad_Opcode }, | |
5273 | { Bad_Opcode }, | |
5dd85c99 | 5274 | /* e0 */ |
592d1631 L |
5275 | { Bad_Opcode }, |
5276 | { Bad_Opcode }, | |
5277 | { Bad_Opcode }, | |
5278 | { Bad_Opcode }, | |
5279 | { Bad_Opcode }, | |
5280 | { Bad_Opcode }, | |
5281 | { Bad_Opcode }, | |
5282 | { Bad_Opcode }, | |
5dd85c99 | 5283 | /* e8 */ |
592d1631 L |
5284 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, | |
5286 | { Bad_Opcode }, | |
5287 | { Bad_Opcode }, | |
ff688e1f L |
5288 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
5289 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
5290 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
5291 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 5292 | /* f0 */ |
592d1631 L |
5293 | { Bad_Opcode }, |
5294 | { Bad_Opcode }, | |
5295 | { Bad_Opcode }, | |
5296 | { Bad_Opcode }, | |
5297 | { Bad_Opcode }, | |
5298 | { Bad_Opcode }, | |
5299 | { Bad_Opcode }, | |
5300 | { Bad_Opcode }, | |
5dd85c99 | 5301 | /* f8 */ |
592d1631 L |
5302 | { Bad_Opcode }, |
5303 | { Bad_Opcode }, | |
5304 | { Bad_Opcode }, | |
5305 | { Bad_Opcode }, | |
5306 | { Bad_Opcode }, | |
5307 | { Bad_Opcode }, | |
5308 | { Bad_Opcode }, | |
5309 | { Bad_Opcode }, | |
5dd85c99 SP |
5310 | }, |
5311 | /* XOP_09 */ | |
5312 | { | |
5313 | /* 00 */ | |
592d1631 | 5314 | { Bad_Opcode }, |
467bbef0 JB |
5315 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) }, |
5316 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) }, | |
592d1631 L |
5317 | { Bad_Opcode }, |
5318 | { Bad_Opcode }, | |
5319 | { Bad_Opcode }, | |
5320 | { Bad_Opcode }, | |
5321 | { Bad_Opcode }, | |
5dd85c99 | 5322 | /* 08 */ |
592d1631 L |
5323 | { Bad_Opcode }, |
5324 | { Bad_Opcode }, | |
5325 | { Bad_Opcode }, | |
5326 | { Bad_Opcode }, | |
5327 | { Bad_Opcode }, | |
5328 | { Bad_Opcode }, | |
5329 | { Bad_Opcode }, | |
5330 | { Bad_Opcode }, | |
5dd85c99 | 5331 | /* 10 */ |
592d1631 L |
5332 | { Bad_Opcode }, |
5333 | { Bad_Opcode }, | |
467bbef0 | 5334 | { MOD_TABLE (MOD_VEX_0FXOP_09_12) }, |
592d1631 L |
5335 | { Bad_Opcode }, |
5336 | { Bad_Opcode }, | |
5337 | { Bad_Opcode }, | |
5338 | { Bad_Opcode }, | |
5339 | { Bad_Opcode }, | |
5dd85c99 | 5340 | /* 18 */ |
592d1631 L |
5341 | { Bad_Opcode }, |
5342 | { Bad_Opcode }, | |
5343 | { Bad_Opcode }, | |
5344 | { Bad_Opcode }, | |
5345 | { Bad_Opcode }, | |
5346 | { Bad_Opcode }, | |
5347 | { Bad_Opcode }, | |
5348 | { Bad_Opcode }, | |
5dd85c99 | 5349 | /* 20 */ |
592d1631 L |
5350 | { Bad_Opcode }, |
5351 | { Bad_Opcode }, | |
5352 | { Bad_Opcode }, | |
5353 | { Bad_Opcode }, | |
5354 | { Bad_Opcode }, | |
5355 | { Bad_Opcode }, | |
5356 | { Bad_Opcode }, | |
5357 | { Bad_Opcode }, | |
5dd85c99 | 5358 | /* 28 */ |
592d1631 L |
5359 | { Bad_Opcode }, |
5360 | { Bad_Opcode }, | |
5361 | { Bad_Opcode }, | |
5362 | { Bad_Opcode }, | |
5363 | { Bad_Opcode }, | |
5364 | { Bad_Opcode }, | |
5365 | { Bad_Opcode }, | |
5366 | { Bad_Opcode }, | |
5dd85c99 | 5367 | /* 30 */ |
592d1631 L |
5368 | { Bad_Opcode }, |
5369 | { Bad_Opcode }, | |
5370 | { Bad_Opcode }, | |
5371 | { Bad_Opcode }, | |
5372 | { Bad_Opcode }, | |
5373 | { Bad_Opcode }, | |
5374 | { Bad_Opcode }, | |
5375 | { Bad_Opcode }, | |
5dd85c99 | 5376 | /* 38 */ |
592d1631 L |
5377 | { Bad_Opcode }, |
5378 | { Bad_Opcode }, | |
5379 | { Bad_Opcode }, | |
5380 | { Bad_Opcode }, | |
5381 | { Bad_Opcode }, | |
5382 | { Bad_Opcode }, | |
5383 | { Bad_Opcode }, | |
5384 | { Bad_Opcode }, | |
5dd85c99 | 5385 | /* 40 */ |
592d1631 L |
5386 | { Bad_Opcode }, |
5387 | { Bad_Opcode }, | |
5388 | { Bad_Opcode }, | |
5389 | { Bad_Opcode }, | |
5390 | { Bad_Opcode }, | |
5391 | { Bad_Opcode }, | |
5392 | { Bad_Opcode }, | |
5393 | { Bad_Opcode }, | |
5dd85c99 | 5394 | /* 48 */ |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
5397 | { Bad_Opcode }, | |
5398 | { Bad_Opcode }, | |
5399 | { Bad_Opcode }, | |
5400 | { Bad_Opcode }, | |
5401 | { Bad_Opcode }, | |
5402 | { Bad_Opcode }, | |
5dd85c99 | 5403 | /* 50 */ |
592d1631 L |
5404 | { Bad_Opcode }, |
5405 | { Bad_Opcode }, | |
5406 | { Bad_Opcode }, | |
5407 | { Bad_Opcode }, | |
5408 | { Bad_Opcode }, | |
5409 | { Bad_Opcode }, | |
5410 | { Bad_Opcode }, | |
5411 | { Bad_Opcode }, | |
5dd85c99 | 5412 | /* 58 */ |
592d1631 L |
5413 | { Bad_Opcode }, |
5414 | { Bad_Opcode }, | |
5415 | { Bad_Opcode }, | |
5416 | { Bad_Opcode }, | |
5417 | { Bad_Opcode }, | |
5418 | { Bad_Opcode }, | |
5419 | { Bad_Opcode }, | |
5420 | { Bad_Opcode }, | |
5dd85c99 | 5421 | /* 60 */ |
592d1631 L |
5422 | { Bad_Opcode }, |
5423 | { Bad_Opcode }, | |
5424 | { Bad_Opcode }, | |
5425 | { Bad_Opcode }, | |
5426 | { Bad_Opcode }, | |
5427 | { Bad_Opcode }, | |
5428 | { Bad_Opcode }, | |
5429 | { Bad_Opcode }, | |
5dd85c99 | 5430 | /* 68 */ |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
5433 | { Bad_Opcode }, | |
5434 | { Bad_Opcode }, | |
5435 | { Bad_Opcode }, | |
5436 | { Bad_Opcode }, | |
5437 | { Bad_Opcode }, | |
5438 | { Bad_Opcode }, | |
5dd85c99 | 5439 | /* 70 */ |
592d1631 L |
5440 | { Bad_Opcode }, |
5441 | { Bad_Opcode }, | |
5442 | { Bad_Opcode }, | |
5443 | { Bad_Opcode }, | |
5444 | { Bad_Opcode }, | |
5445 | { Bad_Opcode }, | |
5446 | { Bad_Opcode }, | |
5447 | { Bad_Opcode }, | |
5dd85c99 | 5448 | /* 78 */ |
592d1631 L |
5449 | { Bad_Opcode }, |
5450 | { Bad_Opcode }, | |
5451 | { Bad_Opcode }, | |
5452 | { Bad_Opcode }, | |
5453 | { Bad_Opcode }, | |
5454 | { Bad_Opcode }, | |
5455 | { Bad_Opcode }, | |
5456 | { Bad_Opcode }, | |
5dd85c99 | 5457 | /* 80 */ |
b5b098c2 JB |
5458 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
5459 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
5460 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
5461 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
5462 | { Bad_Opcode }, |
5463 | { Bad_Opcode }, | |
5464 | { Bad_Opcode }, | |
5465 | { Bad_Opcode }, | |
5dd85c99 | 5466 | /* 88 */ |
592d1631 L |
5467 | { Bad_Opcode }, |
5468 | { Bad_Opcode }, | |
5469 | { Bad_Opcode }, | |
5470 | { Bad_Opcode }, | |
5471 | { Bad_Opcode }, | |
5472 | { Bad_Opcode }, | |
5473 | { Bad_Opcode }, | |
5474 | { Bad_Opcode }, | |
5dd85c99 | 5475 | /* 90 */ |
467bbef0 JB |
5476 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) }, |
5477 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) }, | |
5478 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) }, | |
5479 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) }, | |
5480 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) }, | |
5481 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) }, | |
5482 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) }, | |
5483 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) }, | |
5dd85c99 | 5484 | /* 98 */ |
467bbef0 JB |
5485 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) }, |
5486 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) }, | |
5487 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) }, | |
5488 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) }, | |
592d1631 L |
5489 | { Bad_Opcode }, |
5490 | { Bad_Opcode }, | |
5491 | { Bad_Opcode }, | |
5492 | { Bad_Opcode }, | |
5dd85c99 | 5493 | /* a0 */ |
592d1631 L |
5494 | { Bad_Opcode }, |
5495 | { Bad_Opcode }, | |
5496 | { Bad_Opcode }, | |
5497 | { Bad_Opcode }, | |
5498 | { Bad_Opcode }, | |
5499 | { Bad_Opcode }, | |
5500 | { Bad_Opcode }, | |
5501 | { Bad_Opcode }, | |
5dd85c99 | 5502 | /* a8 */ |
592d1631 L |
5503 | { Bad_Opcode }, |
5504 | { Bad_Opcode }, | |
5505 | { Bad_Opcode }, | |
5506 | { Bad_Opcode }, | |
5507 | { Bad_Opcode }, | |
5508 | { Bad_Opcode }, | |
5509 | { Bad_Opcode }, | |
5510 | { Bad_Opcode }, | |
5dd85c99 | 5511 | /* b0 */ |
592d1631 L |
5512 | { Bad_Opcode }, |
5513 | { Bad_Opcode }, | |
5514 | { Bad_Opcode }, | |
5515 | { Bad_Opcode }, | |
5516 | { Bad_Opcode }, | |
5517 | { Bad_Opcode }, | |
5518 | { Bad_Opcode }, | |
5519 | { Bad_Opcode }, | |
5dd85c99 | 5520 | /* b8 */ |
592d1631 L |
5521 | { Bad_Opcode }, |
5522 | { Bad_Opcode }, | |
5523 | { Bad_Opcode }, | |
5524 | { Bad_Opcode }, | |
5525 | { Bad_Opcode }, | |
5526 | { Bad_Opcode }, | |
5527 | { Bad_Opcode }, | |
5528 | { Bad_Opcode }, | |
5dd85c99 | 5529 | /* c0 */ |
592d1631 | 5530 | { Bad_Opcode }, |
467bbef0 JB |
5531 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) }, |
5532 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) }, | |
5533 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) }, | |
592d1631 L |
5534 | { Bad_Opcode }, |
5535 | { Bad_Opcode }, | |
467bbef0 JB |
5536 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) }, |
5537 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) }, | |
5dd85c99 | 5538 | /* c8 */ |
592d1631 L |
5539 | { Bad_Opcode }, |
5540 | { Bad_Opcode }, | |
5541 | { Bad_Opcode }, | |
467bbef0 | 5542 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) }, |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
5545 | { Bad_Opcode }, | |
5546 | { Bad_Opcode }, | |
5dd85c99 | 5547 | /* d0 */ |
592d1631 | 5548 | { Bad_Opcode }, |
467bbef0 JB |
5549 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) }, |
5550 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) }, | |
5551 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) }, | |
592d1631 L |
5552 | { Bad_Opcode }, |
5553 | { Bad_Opcode }, | |
467bbef0 JB |
5554 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) }, |
5555 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) }, | |
5dd85c99 | 5556 | /* d8 */ |
592d1631 L |
5557 | { Bad_Opcode }, |
5558 | { Bad_Opcode }, | |
5559 | { Bad_Opcode }, | |
467bbef0 | 5560 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) }, |
592d1631 L |
5561 | { Bad_Opcode }, |
5562 | { Bad_Opcode }, | |
5563 | { Bad_Opcode }, | |
5564 | { Bad_Opcode }, | |
5dd85c99 | 5565 | /* e0 */ |
592d1631 | 5566 | { Bad_Opcode }, |
467bbef0 JB |
5567 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) }, |
5568 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) }, | |
5569 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) }, | |
592d1631 L |
5570 | { Bad_Opcode }, |
5571 | { Bad_Opcode }, | |
5572 | { Bad_Opcode }, | |
5573 | { Bad_Opcode }, | |
4e7d34a6 | 5574 | /* e8 */ |
592d1631 L |
5575 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, | |
5577 | { Bad_Opcode }, | |
5578 | { Bad_Opcode }, | |
5579 | { Bad_Opcode }, | |
5580 | { Bad_Opcode }, | |
5581 | { Bad_Opcode }, | |
5582 | { Bad_Opcode }, | |
4e7d34a6 | 5583 | /* f0 */ |
592d1631 L |
5584 | { Bad_Opcode }, |
5585 | { Bad_Opcode }, | |
5586 | { Bad_Opcode }, | |
5587 | { Bad_Opcode }, | |
5588 | { Bad_Opcode }, | |
5589 | { Bad_Opcode }, | |
5590 | { Bad_Opcode }, | |
5591 | { Bad_Opcode }, | |
4e7d34a6 | 5592 | /* f8 */ |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
5595 | { Bad_Opcode }, | |
5596 | { Bad_Opcode }, | |
5597 | { Bad_Opcode }, | |
5598 | { Bad_Opcode }, | |
5599 | { Bad_Opcode }, | |
5600 | { Bad_Opcode }, | |
4e7d34a6 | 5601 | }, |
f88c9eb0 | 5602 | /* XOP_0A */ |
4e7d34a6 L |
5603 | { |
5604 | /* 00 */ | |
592d1631 L |
5605 | { Bad_Opcode }, |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
5608 | { Bad_Opcode }, | |
5609 | { Bad_Opcode }, | |
5610 | { Bad_Opcode }, | |
5611 | { Bad_Opcode }, | |
5612 | { Bad_Opcode }, | |
4e7d34a6 | 5613 | /* 08 */ |
592d1631 L |
5614 | { Bad_Opcode }, |
5615 | { Bad_Opcode }, | |
5616 | { Bad_Opcode }, | |
5617 | { Bad_Opcode }, | |
5618 | { Bad_Opcode }, | |
5619 | { Bad_Opcode }, | |
5620 | { Bad_Opcode }, | |
5621 | { Bad_Opcode }, | |
4e7d34a6 | 5622 | /* 10 */ |
c1dc7af5 | 5623 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 5624 | { Bad_Opcode }, |
467bbef0 | 5625 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) }, |
592d1631 L |
5626 | { Bad_Opcode }, |
5627 | { Bad_Opcode }, | |
5628 | { Bad_Opcode }, | |
5629 | { Bad_Opcode }, | |
5630 | { Bad_Opcode }, | |
4e7d34a6 | 5631 | /* 18 */ |
592d1631 L |
5632 | { Bad_Opcode }, |
5633 | { Bad_Opcode }, | |
5634 | { Bad_Opcode }, | |
5635 | { Bad_Opcode }, | |
5636 | { Bad_Opcode }, | |
5637 | { Bad_Opcode }, | |
5638 | { Bad_Opcode }, | |
5639 | { Bad_Opcode }, | |
4e7d34a6 | 5640 | /* 20 */ |
592d1631 L |
5641 | { Bad_Opcode }, |
5642 | { Bad_Opcode }, | |
5643 | { Bad_Opcode }, | |
5644 | { Bad_Opcode }, | |
5645 | { Bad_Opcode }, | |
5646 | { Bad_Opcode }, | |
5647 | { Bad_Opcode }, | |
5648 | { Bad_Opcode }, | |
4e7d34a6 | 5649 | /* 28 */ |
592d1631 L |
5650 | { Bad_Opcode }, |
5651 | { Bad_Opcode }, | |
5652 | { Bad_Opcode }, | |
5653 | { Bad_Opcode }, | |
5654 | { Bad_Opcode }, | |
5655 | { Bad_Opcode }, | |
5656 | { Bad_Opcode }, | |
5657 | { Bad_Opcode }, | |
4e7d34a6 | 5658 | /* 30 */ |
592d1631 L |
5659 | { Bad_Opcode }, |
5660 | { Bad_Opcode }, | |
5661 | { Bad_Opcode }, | |
5662 | { Bad_Opcode }, | |
5663 | { Bad_Opcode }, | |
5664 | { Bad_Opcode }, | |
5665 | { Bad_Opcode }, | |
5666 | { Bad_Opcode }, | |
c0f3af97 | 5667 | /* 38 */ |
592d1631 L |
5668 | { Bad_Opcode }, |
5669 | { Bad_Opcode }, | |
5670 | { Bad_Opcode }, | |
5671 | { Bad_Opcode }, | |
5672 | { Bad_Opcode }, | |
5673 | { Bad_Opcode }, | |
5674 | { Bad_Opcode }, | |
5675 | { Bad_Opcode }, | |
c0f3af97 | 5676 | /* 40 */ |
592d1631 L |
5677 | { Bad_Opcode }, |
5678 | { Bad_Opcode }, | |
5679 | { Bad_Opcode }, | |
5680 | { Bad_Opcode }, | |
5681 | { Bad_Opcode }, | |
5682 | { Bad_Opcode }, | |
5683 | { Bad_Opcode }, | |
5684 | { Bad_Opcode }, | |
c1e679ec | 5685 | /* 48 */ |
592d1631 L |
5686 | { Bad_Opcode }, |
5687 | { Bad_Opcode }, | |
5688 | { Bad_Opcode }, | |
5689 | { Bad_Opcode }, | |
5690 | { Bad_Opcode }, | |
5691 | { Bad_Opcode }, | |
5692 | { Bad_Opcode }, | |
5693 | { Bad_Opcode }, | |
c1e679ec | 5694 | /* 50 */ |
592d1631 L |
5695 | { Bad_Opcode }, |
5696 | { Bad_Opcode }, | |
5697 | { Bad_Opcode }, | |
5698 | { Bad_Opcode }, | |
5699 | { Bad_Opcode }, | |
5700 | { Bad_Opcode }, | |
5701 | { Bad_Opcode }, | |
5702 | { Bad_Opcode }, | |
4e7d34a6 | 5703 | /* 58 */ |
592d1631 L |
5704 | { Bad_Opcode }, |
5705 | { Bad_Opcode }, | |
5706 | { Bad_Opcode }, | |
5707 | { Bad_Opcode }, | |
5708 | { Bad_Opcode }, | |
5709 | { Bad_Opcode }, | |
5710 | { Bad_Opcode }, | |
5711 | { Bad_Opcode }, | |
4e7d34a6 | 5712 | /* 60 */ |
592d1631 L |
5713 | { Bad_Opcode }, |
5714 | { Bad_Opcode }, | |
5715 | { Bad_Opcode }, | |
5716 | { Bad_Opcode }, | |
5717 | { Bad_Opcode }, | |
5718 | { Bad_Opcode }, | |
5719 | { Bad_Opcode }, | |
5720 | { Bad_Opcode }, | |
4e7d34a6 | 5721 | /* 68 */ |
592d1631 L |
5722 | { Bad_Opcode }, |
5723 | { Bad_Opcode }, | |
5724 | { Bad_Opcode }, | |
5725 | { Bad_Opcode }, | |
5726 | { Bad_Opcode }, | |
5727 | { Bad_Opcode }, | |
5728 | { Bad_Opcode }, | |
5729 | { Bad_Opcode }, | |
4e7d34a6 | 5730 | /* 70 */ |
592d1631 L |
5731 | { Bad_Opcode }, |
5732 | { Bad_Opcode }, | |
5733 | { Bad_Opcode }, | |
5734 | { Bad_Opcode }, | |
5735 | { Bad_Opcode }, | |
5736 | { Bad_Opcode }, | |
5737 | { Bad_Opcode }, | |
5738 | { Bad_Opcode }, | |
4e7d34a6 | 5739 | /* 78 */ |
592d1631 L |
5740 | { Bad_Opcode }, |
5741 | { Bad_Opcode }, | |
5742 | { Bad_Opcode }, | |
5743 | { Bad_Opcode }, | |
5744 | { Bad_Opcode }, | |
5745 | { Bad_Opcode }, | |
5746 | { Bad_Opcode }, | |
5747 | { Bad_Opcode }, | |
4e7d34a6 | 5748 | /* 80 */ |
592d1631 L |
5749 | { Bad_Opcode }, |
5750 | { Bad_Opcode }, | |
5751 | { Bad_Opcode }, | |
5752 | { Bad_Opcode }, | |
5753 | { Bad_Opcode }, | |
5754 | { Bad_Opcode }, | |
5755 | { Bad_Opcode }, | |
5756 | { Bad_Opcode }, | |
4e7d34a6 | 5757 | /* 88 */ |
592d1631 L |
5758 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, | |
5760 | { Bad_Opcode }, | |
5761 | { Bad_Opcode }, | |
5762 | { Bad_Opcode }, | |
5763 | { Bad_Opcode }, | |
5764 | { Bad_Opcode }, | |
5765 | { Bad_Opcode }, | |
4e7d34a6 | 5766 | /* 90 */ |
592d1631 L |
5767 | { Bad_Opcode }, |
5768 | { Bad_Opcode }, | |
5769 | { Bad_Opcode }, | |
5770 | { Bad_Opcode }, | |
5771 | { Bad_Opcode }, | |
5772 | { Bad_Opcode }, | |
5773 | { Bad_Opcode }, | |
5774 | { Bad_Opcode }, | |
4e7d34a6 | 5775 | /* 98 */ |
592d1631 L |
5776 | { Bad_Opcode }, |
5777 | { Bad_Opcode }, | |
5778 | { Bad_Opcode }, | |
5779 | { Bad_Opcode }, | |
5780 | { Bad_Opcode }, | |
5781 | { Bad_Opcode }, | |
5782 | { Bad_Opcode }, | |
5783 | { Bad_Opcode }, | |
4e7d34a6 | 5784 | /* a0 */ |
592d1631 L |
5785 | { Bad_Opcode }, |
5786 | { Bad_Opcode }, | |
5787 | { Bad_Opcode }, | |
5788 | { Bad_Opcode }, | |
5789 | { Bad_Opcode }, | |
5790 | { Bad_Opcode }, | |
5791 | { Bad_Opcode }, | |
5792 | { Bad_Opcode }, | |
4e7d34a6 | 5793 | /* a8 */ |
592d1631 L |
5794 | { Bad_Opcode }, |
5795 | { Bad_Opcode }, | |
5796 | { Bad_Opcode }, | |
5797 | { Bad_Opcode }, | |
5798 | { Bad_Opcode }, | |
5799 | { Bad_Opcode }, | |
5800 | { Bad_Opcode }, | |
5801 | { Bad_Opcode }, | |
d5d7db8e | 5802 | /* b0 */ |
592d1631 L |
5803 | { Bad_Opcode }, |
5804 | { Bad_Opcode }, | |
5805 | { Bad_Opcode }, | |
5806 | { Bad_Opcode }, | |
5807 | { Bad_Opcode }, | |
5808 | { Bad_Opcode }, | |
5809 | { Bad_Opcode }, | |
5810 | { Bad_Opcode }, | |
85f10a01 | 5811 | /* b8 */ |
592d1631 L |
5812 | { Bad_Opcode }, |
5813 | { Bad_Opcode }, | |
5814 | { Bad_Opcode }, | |
5815 | { Bad_Opcode }, | |
5816 | { Bad_Opcode }, | |
5817 | { Bad_Opcode }, | |
5818 | { Bad_Opcode }, | |
5819 | { Bad_Opcode }, | |
85f10a01 | 5820 | /* c0 */ |
592d1631 L |
5821 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, | |
5823 | { Bad_Opcode }, | |
5824 | { Bad_Opcode }, | |
5825 | { Bad_Opcode }, | |
5826 | { Bad_Opcode }, | |
5827 | { Bad_Opcode }, | |
5828 | { Bad_Opcode }, | |
85f10a01 | 5829 | /* c8 */ |
592d1631 L |
5830 | { Bad_Opcode }, |
5831 | { Bad_Opcode }, | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
5834 | { Bad_Opcode }, | |
5835 | { Bad_Opcode }, | |
5836 | { Bad_Opcode }, | |
5837 | { Bad_Opcode }, | |
85f10a01 | 5838 | /* d0 */ |
592d1631 L |
5839 | { Bad_Opcode }, |
5840 | { Bad_Opcode }, | |
5841 | { Bad_Opcode }, | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
5844 | { Bad_Opcode }, | |
5845 | { Bad_Opcode }, | |
5846 | { Bad_Opcode }, | |
85f10a01 | 5847 | /* d8 */ |
592d1631 L |
5848 | { Bad_Opcode }, |
5849 | { Bad_Opcode }, | |
5850 | { Bad_Opcode }, | |
5851 | { Bad_Opcode }, | |
5852 | { Bad_Opcode }, | |
5853 | { Bad_Opcode }, | |
5854 | { Bad_Opcode }, | |
5855 | { Bad_Opcode }, | |
85f10a01 | 5856 | /* e0 */ |
592d1631 L |
5857 | { Bad_Opcode }, |
5858 | { Bad_Opcode }, | |
5859 | { Bad_Opcode }, | |
5860 | { Bad_Opcode }, | |
5861 | { Bad_Opcode }, | |
5862 | { Bad_Opcode }, | |
5863 | { Bad_Opcode }, | |
5864 | { Bad_Opcode }, | |
85f10a01 | 5865 | /* e8 */ |
592d1631 L |
5866 | { Bad_Opcode }, |
5867 | { Bad_Opcode }, | |
5868 | { Bad_Opcode }, | |
5869 | { Bad_Opcode }, | |
5870 | { Bad_Opcode }, | |
5871 | { Bad_Opcode }, | |
5872 | { Bad_Opcode }, | |
5873 | { Bad_Opcode }, | |
85f10a01 | 5874 | /* f0 */ |
592d1631 L |
5875 | { Bad_Opcode }, |
5876 | { Bad_Opcode }, | |
5877 | { Bad_Opcode }, | |
5878 | { Bad_Opcode }, | |
5879 | { Bad_Opcode }, | |
5880 | { Bad_Opcode }, | |
5881 | { Bad_Opcode }, | |
5882 | { Bad_Opcode }, | |
85f10a01 | 5883 | /* f8 */ |
592d1631 L |
5884 | { Bad_Opcode }, |
5885 | { Bad_Opcode }, | |
5886 | { Bad_Opcode }, | |
5887 | { Bad_Opcode }, | |
5888 | { Bad_Opcode }, | |
5889 | { Bad_Opcode }, | |
5890 | { Bad_Opcode }, | |
5891 | { Bad_Opcode }, | |
85f10a01 | 5892 | }, |
c0f3af97 L |
5893 | }; |
5894 | ||
5895 | static const struct dis386 vex_table[][256] = { | |
5896 | /* VEX_0F */ | |
85f10a01 MM |
5897 | { |
5898 | /* 00 */ | |
592d1631 L |
5899 | { Bad_Opcode }, |
5900 | { Bad_Opcode }, | |
5901 | { Bad_Opcode }, | |
5902 | { Bad_Opcode }, | |
5903 | { Bad_Opcode }, | |
5904 | { Bad_Opcode }, | |
5905 | { Bad_Opcode }, | |
5906 | { Bad_Opcode }, | |
85f10a01 | 5907 | /* 08 */ |
592d1631 L |
5908 | { Bad_Opcode }, |
5909 | { Bad_Opcode }, | |
5910 | { Bad_Opcode }, | |
5911 | { Bad_Opcode }, | |
5912 | { Bad_Opcode }, | |
5913 | { Bad_Opcode }, | |
5914 | { Bad_Opcode }, | |
5915 | { Bad_Opcode }, | |
c0f3af97 | 5916 | /* 10 */ |
592a252b L |
5917 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
5918 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
5919 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
5920 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
5921 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5922 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
5923 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
5924 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 5925 | /* 18 */ |
592d1631 L |
5926 | { Bad_Opcode }, |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
5931 | { Bad_Opcode }, | |
5932 | { Bad_Opcode }, | |
5933 | { Bad_Opcode }, | |
c0f3af97 | 5934 | /* 20 */ |
592d1631 L |
5935 | { Bad_Opcode }, |
5936 | { Bad_Opcode }, | |
5937 | { Bad_Opcode }, | |
5938 | { Bad_Opcode }, | |
5939 | { Bad_Opcode }, | |
5940 | { Bad_Opcode }, | |
5941 | { Bad_Opcode }, | |
5942 | { Bad_Opcode }, | |
c0f3af97 | 5943 | /* 28 */ |
bf926894 JB |
5944 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
5945 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
5946 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
5947 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
5948 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
5949 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
5950 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
5951 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 5952 | /* 30 */ |
592d1631 L |
5953 | { Bad_Opcode }, |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
5956 | { Bad_Opcode }, | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
5959 | { Bad_Opcode }, | |
5960 | { Bad_Opcode }, | |
4e7d34a6 | 5961 | /* 38 */ |
592d1631 L |
5962 | { Bad_Opcode }, |
5963 | { Bad_Opcode }, | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
5966 | { Bad_Opcode }, | |
5967 | { Bad_Opcode }, | |
5968 | { Bad_Opcode }, | |
5969 | { Bad_Opcode }, | |
d5d7db8e | 5970 | /* 40 */ |
592d1631 | 5971 | { Bad_Opcode }, |
43234a1e L |
5972 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
5973 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 5974 | { Bad_Opcode }, |
43234a1e L |
5975 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
5976 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
5977 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
5978 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 5979 | /* 48 */ |
592d1631 L |
5980 | { Bad_Opcode }, |
5981 | { Bad_Opcode }, | |
1ba585e8 | 5982 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 5983 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
5984 | { Bad_Opcode }, |
5985 | { Bad_Opcode }, | |
5986 | { Bad_Opcode }, | |
5987 | { Bad_Opcode }, | |
d5d7db8e | 5988 | /* 50 */ |
592a252b L |
5989 | { MOD_TABLE (MOD_VEX_0F50) }, |
5990 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
5991 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
5992 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
5993 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5994 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
5995 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
5996 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 5997 | /* 58 */ |
592a252b L |
5998 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
5999 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
6000 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
6001 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
6002 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
6003 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
6004 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
6005 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 6006 | /* 60 */ |
7531c613 JB |
6007 | { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA }, |
6008 | { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6009 | { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6010 | { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6011 | { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6012 | { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6013 | { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6014 | { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6015 | /* 68 */ |
7531c613 JB |
6016 | { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA }, |
6017 | { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6018 | { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6019 | { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6020 | { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6021 | { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6022 | { VEX_LEN_TABLE (VEX_LEN_0F6E) }, | |
592a252b | 6023 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
c0f3af97 | 6024 | /* 70 */ |
592a252b L |
6025 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
6026 | { REG_TABLE (REG_VEX_0F71) }, | |
6027 | { REG_TABLE (REG_VEX_0F72) }, | |
6028 | { REG_TABLE (REG_VEX_0F73) }, | |
7531c613 JB |
6029 | { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA }, |
6030 | { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6031 | { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA }, | |
035e7389 | 6032 | { VEX_LEN_TABLE (VEX_LEN_0F77) }, |
c0f3af97 | 6033 | /* 78 */ |
592d1631 L |
6034 | { Bad_Opcode }, |
6035 | { Bad_Opcode }, | |
6036 | { Bad_Opcode }, | |
6037 | { Bad_Opcode }, | |
592a252b L |
6038 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
6039 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
6040 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
6041 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 6042 | /* 80 */ |
592d1631 L |
6043 | { Bad_Opcode }, |
6044 | { Bad_Opcode }, | |
6045 | { Bad_Opcode }, | |
6046 | { Bad_Opcode }, | |
6047 | { Bad_Opcode }, | |
6048 | { Bad_Opcode }, | |
6049 | { Bad_Opcode }, | |
6050 | { Bad_Opcode }, | |
c0f3af97 | 6051 | /* 88 */ |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
6054 | { Bad_Opcode }, | |
6055 | { Bad_Opcode }, | |
6056 | { Bad_Opcode }, | |
6057 | { Bad_Opcode }, | |
6058 | { Bad_Opcode }, | |
6059 | { Bad_Opcode }, | |
c0f3af97 | 6060 | /* 90 */ |
43234a1e L |
6061 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
6062 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
6063 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
6064 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
6065 | { Bad_Opcode }, |
6066 | { Bad_Opcode }, | |
6067 | { Bad_Opcode }, | |
6068 | { Bad_Opcode }, | |
c0f3af97 | 6069 | /* 98 */ |
43234a1e | 6070 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 6071 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
6072 | { Bad_Opcode }, |
6073 | { Bad_Opcode }, | |
6074 | { Bad_Opcode }, | |
6075 | { Bad_Opcode }, | |
6076 | { Bad_Opcode }, | |
6077 | { Bad_Opcode }, | |
c0f3af97 | 6078 | /* a0 */ |
592d1631 L |
6079 | { Bad_Opcode }, |
6080 | { Bad_Opcode }, | |
6081 | { Bad_Opcode }, | |
6082 | { Bad_Opcode }, | |
6083 | { Bad_Opcode }, | |
6084 | { Bad_Opcode }, | |
6085 | { Bad_Opcode }, | |
6086 | { Bad_Opcode }, | |
c0f3af97 | 6087 | /* a8 */ |
592d1631 L |
6088 | { Bad_Opcode }, |
6089 | { Bad_Opcode }, | |
6090 | { Bad_Opcode }, | |
6091 | { Bad_Opcode }, | |
6092 | { Bad_Opcode }, | |
6093 | { Bad_Opcode }, | |
592a252b | 6094 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 6095 | { Bad_Opcode }, |
c0f3af97 | 6096 | /* b0 */ |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
6099 | { Bad_Opcode }, | |
6100 | { Bad_Opcode }, | |
6101 | { Bad_Opcode }, | |
6102 | { Bad_Opcode }, | |
6103 | { Bad_Opcode }, | |
6104 | { Bad_Opcode }, | |
c0f3af97 | 6105 | /* b8 */ |
592d1631 L |
6106 | { Bad_Opcode }, |
6107 | { Bad_Opcode }, | |
6108 | { Bad_Opcode }, | |
6109 | { Bad_Opcode }, | |
6110 | { Bad_Opcode }, | |
6111 | { Bad_Opcode }, | |
6112 | { Bad_Opcode }, | |
6113 | { Bad_Opcode }, | |
c0f3af97 | 6114 | /* c0 */ |
592d1631 L |
6115 | { Bad_Opcode }, |
6116 | { Bad_Opcode }, | |
592a252b | 6117 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 6118 | { Bad_Opcode }, |
7531c613 JB |
6119 | { VEX_LEN_TABLE (VEX_LEN_0FC4) }, |
6120 | { VEX_LEN_TABLE (VEX_LEN_0FC5) }, | |
bf926894 | 6121 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 6122 | { Bad_Opcode }, |
c0f3af97 | 6123 | /* c8 */ |
592d1631 L |
6124 | { Bad_Opcode }, |
6125 | { Bad_Opcode }, | |
6126 | { Bad_Opcode }, | |
6127 | { Bad_Opcode }, | |
6128 | { Bad_Opcode }, | |
6129 | { Bad_Opcode }, | |
6130 | { Bad_Opcode }, | |
6131 | { Bad_Opcode }, | |
c0f3af97 | 6132 | /* d0 */ |
592a252b | 6133 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
7531c613 JB |
6134 | { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
6135 | { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6136 | { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6137 | { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6138 | { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6139 | { VEX_LEN_TABLE (VEX_LEN_0FD6) }, | |
6140 | { MOD_TABLE (MOD_VEX_0FD7) }, | |
c0f3af97 | 6141 | /* d8 */ |
7531c613 JB |
6142 | { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA }, |
6143 | { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6144 | { "vpminub", { XM, Vex, EXx }, PREFIX_DATA }, | |
6145 | { "vpand", { XM, Vex, EXx }, PREFIX_DATA }, | |
6146 | { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6147 | { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6148 | { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA }, | |
6149 | { "vpandn", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6150 | /* e0 */ |
7531c613 JB |
6151 | { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA }, |
6152 | { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6153 | { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6154 | { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6155 | { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6156 | { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA }, | |
592a252b | 6157 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
7531c613 | 6158 | { MOD_TABLE (MOD_VEX_0FE7) }, |
c0f3af97 | 6159 | /* e8 */ |
7531c613 JB |
6160 | { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6161 | { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6162 | { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6163 | { "vpor", { XM, Vex, EXx }, PREFIX_DATA }, | |
6164 | { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6165 | { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6166 | { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6167 | { "vpxor", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6168 | /* f0 */ |
592a252b | 6169 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
7531c613 JB |
6170 | { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
6171 | { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6172 | { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6173 | { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6174 | { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6175 | { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6176 | { VEX_LEN_TABLE (VEX_LEN_0FF7) }, | |
c0f3af97 | 6177 | /* f8 */ |
7531c613 JB |
6178 | { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA }, |
6179 | { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6180 | { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6181 | { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6182 | { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6183 | { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6184 | { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
592d1631 | 6185 | { Bad_Opcode }, |
c0f3af97 L |
6186 | }, |
6187 | /* VEX_0F38 */ | |
6188 | { | |
6189 | /* 00 */ | |
7531c613 JB |
6190 | { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA }, |
6191 | { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6192 | { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6193 | { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6194 | { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6195 | { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6196 | { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6197 | { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6198 | /* 08 */ |
7531c613 JB |
6199 | { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA }, |
6200 | { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6201 | { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6202 | { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6203 | { VEX_W_TABLE (VEX_W_0F380C) }, | |
6204 | { VEX_W_TABLE (VEX_W_0F380D) }, | |
6205 | { VEX_W_TABLE (VEX_W_0F380E) }, | |
6206 | { VEX_W_TABLE (VEX_W_0F380F) }, | |
c0f3af97 | 6207 | /* 10 */ |
592d1631 L |
6208 | { Bad_Opcode }, |
6209 | { Bad_Opcode }, | |
6210 | { Bad_Opcode }, | |
7531c613 | 6211 | { VEX_W_TABLE (VEX_W_0F3813) }, |
592d1631 L |
6212 | { Bad_Opcode }, |
6213 | { Bad_Opcode }, | |
7531c613 JB |
6214 | { VEX_LEN_TABLE (VEX_LEN_0F3816) }, |
6215 | { "vptest", { XM, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6216 | /* 18 */ |
7531c613 JB |
6217 | { VEX_W_TABLE (VEX_W_0F3818) }, |
6218 | { VEX_LEN_TABLE (VEX_LEN_0F3819) }, | |
6219 | { MOD_TABLE (MOD_VEX_0F381A) }, | |
592d1631 | 6220 | { Bad_Opcode }, |
7531c613 JB |
6221 | { "vpabsb", { XM, EXx }, PREFIX_DATA }, |
6222 | { "vpabsw", { XM, EXx }, PREFIX_DATA }, | |
6223 | { "vpabsd", { XM, EXx }, PREFIX_DATA }, | |
592d1631 | 6224 | { Bad_Opcode }, |
c0f3af97 | 6225 | /* 20 */ |
7531c613 JB |
6226 | { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6227 | { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6228 | { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6229 | { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6230 | { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6231 | { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
592d1631 L |
6232 | { Bad_Opcode }, |
6233 | { Bad_Opcode }, | |
c0f3af97 | 6234 | /* 28 */ |
7531c613 JB |
6235 | { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA }, |
6236 | { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6237 | { MOD_TABLE (MOD_VEX_0F382A) }, | |
6238 | { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6239 | { MOD_TABLE (MOD_VEX_0F382C) }, | |
6240 | { MOD_TABLE (MOD_VEX_0F382D) }, | |
6241 | { MOD_TABLE (MOD_VEX_0F382E) }, | |
6242 | { MOD_TABLE (MOD_VEX_0F382F) }, | |
c0f3af97 | 6243 | /* 30 */ |
7531c613 JB |
6244 | { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6245 | { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6246 | { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6247 | { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6248 | { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6249 | { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
6250 | { VEX_LEN_TABLE (VEX_LEN_0F3836) }, | |
6251 | { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6252 | /* 38 */ |
7531c613 JB |
6253 | { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6254 | { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6255 | { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6256 | { "vpminud", { XM, Vex, EXx }, PREFIX_DATA }, | |
6257 | { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6258 | { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6259 | { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6260 | { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6261 | /* 40 */ |
7531c613 JB |
6262 | { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA }, |
6263 | { VEX_LEN_TABLE (VEX_LEN_0F3841) }, | |
592d1631 L |
6264 | { Bad_Opcode }, |
6265 | { Bad_Opcode }, | |
6266 | { Bad_Opcode }, | |
7531c613 JB |
6267 | { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, |
6268 | { VEX_W_TABLE (VEX_W_0F3846) }, | |
6269 | { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6270 | /* 48 */ |
592d1631 | 6271 | { Bad_Opcode }, |
260cd341 | 6272 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 6273 | { Bad_Opcode }, |
260cd341 | 6274 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
6275 | { Bad_Opcode }, |
6276 | { Bad_Opcode }, | |
6277 | { Bad_Opcode }, | |
6278 | { Bad_Opcode }, | |
c0f3af97 | 6279 | /* 50 */ |
58bf9b6a L |
6280 | { VEX_W_TABLE (VEX_W_0F3850) }, |
6281 | { VEX_W_TABLE (VEX_W_0F3851) }, | |
6282 | { VEX_W_TABLE (VEX_W_0F3852) }, | |
6283 | { VEX_W_TABLE (VEX_W_0F3853) }, | |
592d1631 L |
6284 | { Bad_Opcode }, |
6285 | { Bad_Opcode }, | |
6286 | { Bad_Opcode }, | |
6287 | { Bad_Opcode }, | |
c0f3af97 | 6288 | /* 58 */ |
7531c613 JB |
6289 | { VEX_W_TABLE (VEX_W_0F3858) }, |
6290 | { VEX_W_TABLE (VEX_W_0F3859) }, | |
6291 | { MOD_TABLE (MOD_VEX_0F385A) }, | |
592d1631 | 6292 | { Bad_Opcode }, |
260cd341 | 6293 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 6294 | { Bad_Opcode }, |
260cd341 | 6295 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 6296 | { Bad_Opcode }, |
c0f3af97 | 6297 | /* 60 */ |
592d1631 L |
6298 | { Bad_Opcode }, |
6299 | { Bad_Opcode }, | |
6300 | { Bad_Opcode }, | |
6301 | { Bad_Opcode }, | |
6302 | { Bad_Opcode }, | |
6303 | { Bad_Opcode }, | |
6304 | { Bad_Opcode }, | |
6305 | { Bad_Opcode }, | |
c0f3af97 | 6306 | /* 68 */ |
592d1631 L |
6307 | { Bad_Opcode }, |
6308 | { Bad_Opcode }, | |
6309 | { Bad_Opcode }, | |
6310 | { Bad_Opcode }, | |
6311 | { Bad_Opcode }, | |
6312 | { Bad_Opcode }, | |
6313 | { Bad_Opcode }, | |
6314 | { Bad_Opcode }, | |
c0f3af97 | 6315 | /* 70 */ |
592d1631 L |
6316 | { Bad_Opcode }, |
6317 | { Bad_Opcode }, | |
6318 | { Bad_Opcode }, | |
6319 | { Bad_Opcode }, | |
6320 | { Bad_Opcode }, | |
6321 | { Bad_Opcode }, | |
6322 | { Bad_Opcode }, | |
6323 | { Bad_Opcode }, | |
c0f3af97 | 6324 | /* 78 */ |
7531c613 JB |
6325 | { VEX_W_TABLE (VEX_W_0F3878) }, |
6326 | { VEX_W_TABLE (VEX_W_0F3879) }, | |
592d1631 L |
6327 | { Bad_Opcode }, |
6328 | { Bad_Opcode }, | |
6329 | { Bad_Opcode }, | |
6330 | { Bad_Opcode }, | |
6331 | { Bad_Opcode }, | |
6332 | { Bad_Opcode }, | |
c0f3af97 | 6333 | /* 80 */ |
592d1631 L |
6334 | { Bad_Opcode }, |
6335 | { Bad_Opcode }, | |
6336 | { Bad_Opcode }, | |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
6340 | { Bad_Opcode }, | |
6341 | { Bad_Opcode }, | |
c0f3af97 | 6342 | /* 88 */ |
592d1631 L |
6343 | { Bad_Opcode }, |
6344 | { Bad_Opcode }, | |
6345 | { Bad_Opcode }, | |
6346 | { Bad_Opcode }, | |
7531c613 | 6347 | { MOD_TABLE (MOD_VEX_0F388C) }, |
592d1631 | 6348 | { Bad_Opcode }, |
7531c613 | 6349 | { MOD_TABLE (MOD_VEX_0F388E) }, |
592d1631 | 6350 | { Bad_Opcode }, |
c0f3af97 | 6351 | /* 90 */ |
7531c613 JB |
6352 | { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA }, |
6353 | { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, | |
6354 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA }, | |
6355 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, | |
592d1631 L |
6356 | { Bad_Opcode }, |
6357 | { Bad_Opcode }, | |
7531c613 JB |
6358 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6359 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6360 | /* 98 */ |
7531c613 JB |
6361 | { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6362 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6363 | { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6364 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6365 | { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6366 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6367 | { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6368 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6369 | /* a0 */ |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
6372 | { Bad_Opcode }, | |
6373 | { Bad_Opcode }, | |
6374 | { Bad_Opcode }, | |
6375 | { Bad_Opcode }, | |
7531c613 JB |
6376 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6377 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6378 | /* a8 */ |
7531c613 JB |
6379 | { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6380 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6381 | { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6382 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6383 | { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6384 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6385 | { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6386 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6387 | /* b0 */ |
592d1631 L |
6388 | { Bad_Opcode }, |
6389 | { Bad_Opcode }, | |
6390 | { Bad_Opcode }, | |
6391 | { Bad_Opcode }, | |
6392 | { Bad_Opcode }, | |
6393 | { Bad_Opcode }, | |
7531c613 JB |
6394 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6395 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6396 | /* b8 */ |
7531c613 JB |
6397 | { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6398 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6399 | { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6400 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6401 | { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6402 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6403 | { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6404 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6405 | /* c0 */ |
592d1631 L |
6406 | { Bad_Opcode }, |
6407 | { Bad_Opcode }, | |
6408 | { Bad_Opcode }, | |
6409 | { Bad_Opcode }, | |
6410 | { Bad_Opcode }, | |
6411 | { Bad_Opcode }, | |
6412 | { Bad_Opcode }, | |
6413 | { Bad_Opcode }, | |
c0f3af97 | 6414 | /* c8 */ |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
6417 | { Bad_Opcode }, | |
6418 | { Bad_Opcode }, | |
6419 | { Bad_Opcode }, | |
6420 | { Bad_Opcode }, | |
6421 | { Bad_Opcode }, | |
7531c613 | 6422 | { VEX_W_TABLE (VEX_W_0F38CF) }, |
c0f3af97 | 6423 | /* d0 */ |
592d1631 L |
6424 | { Bad_Opcode }, |
6425 | { Bad_Opcode }, | |
6426 | { Bad_Opcode }, | |
6427 | { Bad_Opcode }, | |
6428 | { Bad_Opcode }, | |
6429 | { Bad_Opcode }, | |
6430 | { Bad_Opcode }, | |
6431 | { Bad_Opcode }, | |
c0f3af97 | 6432 | /* d8 */ |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
6435 | { Bad_Opcode }, | |
7531c613 JB |
6436 | { VEX_LEN_TABLE (VEX_LEN_0F38DB) }, |
6437 | { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA }, | |
6438 | { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
6439 | { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, | |
6440 | { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6441 | /* e0 */ |
592d1631 L |
6442 | { Bad_Opcode }, |
6443 | { Bad_Opcode }, | |
6444 | { Bad_Opcode }, | |
6445 | { Bad_Opcode }, | |
6446 | { Bad_Opcode }, | |
6447 | { Bad_Opcode }, | |
6448 | { Bad_Opcode }, | |
6449 | { Bad_Opcode }, | |
c0f3af97 | 6450 | /* e8 */ |
592d1631 L |
6451 | { Bad_Opcode }, |
6452 | { Bad_Opcode }, | |
6453 | { Bad_Opcode }, | |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
6457 | { Bad_Opcode }, | |
6458 | { Bad_Opcode }, | |
c0f3af97 | 6459 | /* f0 */ |
592d1631 L |
6460 | { Bad_Opcode }, |
6461 | { Bad_Opcode }, | |
035e7389 | 6462 | { VEX_LEN_TABLE (VEX_LEN_0F38F2) }, |
f12dc422 | 6463 | { REG_TABLE (REG_VEX_0F38F3) }, |
592d1631 | 6464 | { Bad_Opcode }, |
6c30d220 L |
6465 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
6466 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 6467 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 6468 | /* f8 */ |
592d1631 L |
6469 | { Bad_Opcode }, |
6470 | { Bad_Opcode }, | |
6471 | { Bad_Opcode }, | |
6472 | { Bad_Opcode }, | |
6473 | { Bad_Opcode }, | |
6474 | { Bad_Opcode }, | |
6475 | { Bad_Opcode }, | |
6476 | { Bad_Opcode }, | |
c0f3af97 L |
6477 | }, |
6478 | /* VEX_0F3A */ | |
6479 | { | |
6480 | /* 00 */ | |
7531c613 JB |
6481 | { VEX_LEN_TABLE (VEX_LEN_0F3A00) }, |
6482 | { VEX_LEN_TABLE (VEX_LEN_0F3A01) }, | |
6483 | { VEX_W_TABLE (VEX_W_0F3A02) }, | |
592d1631 | 6484 | { Bad_Opcode }, |
7531c613 JB |
6485 | { VEX_W_TABLE (VEX_W_0F3A04) }, |
6486 | { VEX_W_TABLE (VEX_W_0F3A05) }, | |
6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A06) }, | |
592d1631 | 6488 | { Bad_Opcode }, |
c0f3af97 | 6489 | /* 08 */ |
7531c613 JB |
6490 | { "vroundps", { XM, EXx, Ib }, PREFIX_DATA }, |
6491 | { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
6492 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA }, | |
6493 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA }, | |
6494 | { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6495 | { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6496 | { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6497 | { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
c0f3af97 | 6498 | /* 10 */ |
592d1631 L |
6499 | { Bad_Opcode }, |
6500 | { Bad_Opcode }, | |
6501 | { Bad_Opcode }, | |
6502 | { Bad_Opcode }, | |
7531c613 JB |
6503 | { VEX_LEN_TABLE (VEX_LEN_0F3A14) }, |
6504 | { VEX_LEN_TABLE (VEX_LEN_0F3A15) }, | |
6505 | { VEX_LEN_TABLE (VEX_LEN_0F3A16) }, | |
6506 | { VEX_LEN_TABLE (VEX_LEN_0F3A17) }, | |
c0f3af97 | 6507 | /* 18 */ |
7531c613 JB |
6508 | { VEX_LEN_TABLE (VEX_LEN_0F3A18) }, |
6509 | { VEX_LEN_TABLE (VEX_LEN_0F3A19) }, | |
592d1631 L |
6510 | { Bad_Opcode }, |
6511 | { Bad_Opcode }, | |
6512 | { Bad_Opcode }, | |
7531c613 | 6513 | { VEX_W_TABLE (VEX_W_0F3A1D) }, |
592d1631 L |
6514 | { Bad_Opcode }, |
6515 | { Bad_Opcode }, | |
c0f3af97 | 6516 | /* 20 */ |
7531c613 JB |
6517 | { VEX_LEN_TABLE (VEX_LEN_0F3A20) }, |
6518 | { VEX_LEN_TABLE (VEX_LEN_0F3A21) }, | |
6519 | { VEX_LEN_TABLE (VEX_LEN_0F3A22) }, | |
592d1631 L |
6520 | { Bad_Opcode }, |
6521 | { Bad_Opcode }, | |
6522 | { Bad_Opcode }, | |
6523 | { Bad_Opcode }, | |
6524 | { Bad_Opcode }, | |
c0f3af97 | 6525 | /* 28 */ |
592d1631 L |
6526 | { Bad_Opcode }, |
6527 | { Bad_Opcode }, | |
6528 | { Bad_Opcode }, | |
6529 | { Bad_Opcode }, | |
6530 | { Bad_Opcode }, | |
6531 | { Bad_Opcode }, | |
6532 | { Bad_Opcode }, | |
6533 | { Bad_Opcode }, | |
c0f3af97 | 6534 | /* 30 */ |
7531c613 JB |
6535 | { VEX_LEN_TABLE (VEX_LEN_0F3A30) }, |
6536 | { VEX_LEN_TABLE (VEX_LEN_0F3A31) }, | |
6537 | { VEX_LEN_TABLE (VEX_LEN_0F3A32) }, | |
6538 | { VEX_LEN_TABLE (VEX_LEN_0F3A33) }, | |
592d1631 L |
6539 | { Bad_Opcode }, |
6540 | { Bad_Opcode }, | |
6541 | { Bad_Opcode }, | |
6542 | { Bad_Opcode }, | |
c0f3af97 | 6543 | /* 38 */ |
7531c613 JB |
6544 | { VEX_LEN_TABLE (VEX_LEN_0F3A38) }, |
6545 | { VEX_LEN_TABLE (VEX_LEN_0F3A39) }, | |
592d1631 L |
6546 | { Bad_Opcode }, |
6547 | { Bad_Opcode }, | |
6548 | { Bad_Opcode }, | |
6549 | { Bad_Opcode }, | |
6550 | { Bad_Opcode }, | |
6551 | { Bad_Opcode }, | |
c0f3af97 | 6552 | /* 40 */ |
7531c613 JB |
6553 | { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
6554 | { VEX_LEN_TABLE (VEX_LEN_0F3A41) }, | |
6555 | { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 6556 | { Bad_Opcode }, |
7531c613 | 6557 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 | 6558 | { Bad_Opcode }, |
7531c613 | 6559 | { VEX_LEN_TABLE (VEX_LEN_0F3A46) }, |
592d1631 | 6560 | { Bad_Opcode }, |
c0f3af97 | 6561 | /* 48 */ |
7531c613 JB |
6562 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, |
6563 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, | |
6564 | { VEX_W_TABLE (VEX_W_0F3A4A) }, | |
6565 | { VEX_W_TABLE (VEX_W_0F3A4B) }, | |
6566 | { VEX_W_TABLE (VEX_W_0F3A4C) }, | |
592d1631 L |
6567 | { Bad_Opcode }, |
6568 | { Bad_Opcode }, | |
6569 | { Bad_Opcode }, | |
c0f3af97 | 6570 | /* 50 */ |
592d1631 L |
6571 | { Bad_Opcode }, |
6572 | { Bad_Opcode }, | |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
6575 | { Bad_Opcode }, | |
6576 | { Bad_Opcode }, | |
6577 | { Bad_Opcode }, | |
6578 | { Bad_Opcode }, | |
c0f3af97 | 6579 | /* 58 */ |
592d1631 L |
6580 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, | |
6582 | { Bad_Opcode }, | |
6583 | { Bad_Opcode }, | |
7531c613 JB |
6584 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6585 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6586 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6587 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c0f3af97 | 6588 | /* 60 */ |
7531c613 JB |
6589 | { VEX_LEN_TABLE (VEX_LEN_0F3A60) }, |
6590 | { VEX_LEN_TABLE (VEX_LEN_0F3A61) }, | |
6591 | { VEX_LEN_TABLE (VEX_LEN_0F3A62) }, | |
6592 | { VEX_LEN_TABLE (VEX_LEN_0F3A63) }, | |
592d1631 L |
6593 | { Bad_Opcode }, |
6594 | { Bad_Opcode }, | |
6595 | { Bad_Opcode }, | |
6596 | { Bad_Opcode }, | |
c0f3af97 | 6597 | /* 68 */ |
7531c613 JB |
6598 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6599 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6600 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6601 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
6602 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6603 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6604 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6605 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6606 | /* 70 */ |
592d1631 L |
6607 | { Bad_Opcode }, |
6608 | { Bad_Opcode }, | |
6609 | { Bad_Opcode }, | |
6610 | { Bad_Opcode }, | |
6611 | { Bad_Opcode }, | |
6612 | { Bad_Opcode }, | |
6613 | { Bad_Opcode }, | |
6614 | { Bad_Opcode }, | |
c0f3af97 | 6615 | /* 78 */ |
7531c613 JB |
6616 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6617 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6618 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6619 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
6620 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6621 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6622 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6623 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6624 | /* 80 */ |
592d1631 L |
6625 | { Bad_Opcode }, |
6626 | { Bad_Opcode }, | |
6627 | { Bad_Opcode }, | |
6628 | { Bad_Opcode }, | |
6629 | { Bad_Opcode }, | |
6630 | { Bad_Opcode }, | |
6631 | { Bad_Opcode }, | |
6632 | { Bad_Opcode }, | |
c0f3af97 | 6633 | /* 88 */ |
592d1631 L |
6634 | { Bad_Opcode }, |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
6639 | { Bad_Opcode }, | |
6640 | { Bad_Opcode }, | |
6641 | { Bad_Opcode }, | |
c0f3af97 | 6642 | /* 90 */ |
592d1631 L |
6643 | { Bad_Opcode }, |
6644 | { Bad_Opcode }, | |
6645 | { Bad_Opcode }, | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
6648 | { Bad_Opcode }, | |
6649 | { Bad_Opcode }, | |
6650 | { Bad_Opcode }, | |
c0f3af97 | 6651 | /* 98 */ |
592d1631 L |
6652 | { Bad_Opcode }, |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
6658 | { Bad_Opcode }, | |
6659 | { Bad_Opcode }, | |
c0f3af97 | 6660 | /* a0 */ |
592d1631 L |
6661 | { Bad_Opcode }, |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
6667 | { Bad_Opcode }, | |
6668 | { Bad_Opcode }, | |
c0f3af97 | 6669 | /* a8 */ |
592d1631 L |
6670 | { Bad_Opcode }, |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
6676 | { Bad_Opcode }, | |
6677 | { Bad_Opcode }, | |
c0f3af97 | 6678 | /* b0 */ |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
6684 | { Bad_Opcode }, | |
6685 | { Bad_Opcode }, | |
6686 | { Bad_Opcode }, | |
c0f3af97 | 6687 | /* b8 */ |
592d1631 L |
6688 | { Bad_Opcode }, |
6689 | { Bad_Opcode }, | |
6690 | { Bad_Opcode }, | |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
6694 | { Bad_Opcode }, | |
6695 | { Bad_Opcode }, | |
c0f3af97 | 6696 | /* c0 */ |
592d1631 L |
6697 | { Bad_Opcode }, |
6698 | { Bad_Opcode }, | |
6699 | { Bad_Opcode }, | |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
6702 | { Bad_Opcode }, | |
6703 | { Bad_Opcode }, | |
6704 | { Bad_Opcode }, | |
c0f3af97 | 6705 | /* c8 */ |
592d1631 L |
6706 | { Bad_Opcode }, |
6707 | { Bad_Opcode }, | |
6708 | { Bad_Opcode }, | |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
7531c613 JB |
6712 | { VEX_W_TABLE (VEX_W_0F3ACE) }, |
6713 | { VEX_W_TABLE (VEX_W_0F3ACF) }, | |
c0f3af97 | 6714 | /* d0 */ |
592d1631 L |
6715 | { Bad_Opcode }, |
6716 | { Bad_Opcode }, | |
6717 | { Bad_Opcode }, | |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
6721 | { Bad_Opcode }, | |
6722 | { Bad_Opcode }, | |
c0f3af97 | 6723 | /* d8 */ |
592d1631 L |
6724 | { Bad_Opcode }, |
6725 | { Bad_Opcode }, | |
6726 | { Bad_Opcode }, | |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
7531c613 | 6731 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF) }, |
c0f3af97 | 6732 | /* e0 */ |
592d1631 L |
6733 | { Bad_Opcode }, |
6734 | { Bad_Opcode }, | |
6735 | { Bad_Opcode }, | |
6736 | { Bad_Opcode }, | |
6737 | { Bad_Opcode }, | |
6738 | { Bad_Opcode }, | |
6739 | { Bad_Opcode }, | |
6740 | { Bad_Opcode }, | |
c0f3af97 | 6741 | /* e8 */ |
592d1631 L |
6742 | { Bad_Opcode }, |
6743 | { Bad_Opcode }, | |
6744 | { Bad_Opcode }, | |
6745 | { Bad_Opcode }, | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
6748 | { Bad_Opcode }, | |
6749 | { Bad_Opcode }, | |
c0f3af97 | 6750 | /* f0 */ |
6c30d220 | 6751 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
6752 | { Bad_Opcode }, |
6753 | { Bad_Opcode }, | |
6754 | { Bad_Opcode }, | |
6755 | { Bad_Opcode }, | |
6756 | { Bad_Opcode }, | |
6757 | { Bad_Opcode }, | |
6758 | { Bad_Opcode }, | |
c0f3af97 | 6759 | /* f8 */ |
592d1631 L |
6760 | { Bad_Opcode }, |
6761 | { Bad_Opcode }, | |
6762 | { Bad_Opcode }, | |
6763 | { Bad_Opcode }, | |
6764 | { Bad_Opcode }, | |
6765 | { Bad_Opcode }, | |
6766 | { Bad_Opcode }, | |
6767 | { Bad_Opcode }, | |
c0f3af97 L |
6768 | }, |
6769 | }; | |
6770 | ||
43234a1e | 6771 | #include "i386-dis-evex.h" |
ad692897 | 6772 | |
c0f3af97 | 6773 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 6774 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 6775 | { |
89e65d17 | 6776 | { "vmovlpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6777 | }, |
6778 | ||
592a252b | 6779 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 6780 | { |
89e65d17 | 6781 | { "vmovhlps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6782 | }, |
6783 | ||
592a252b | 6784 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 6785 | { |
bf926894 | 6786 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6787 | }, |
6788 | ||
18897deb | 6789 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 6790 | { |
89e65d17 | 6791 | { "vmovhpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6792 | }, |
6793 | ||
592a252b | 6794 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 6795 | { |
89e65d17 | 6796 | { "vmovlhps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6797 | }, |
6798 | ||
592a252b | 6799 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 6800 | { |
bf926894 | 6801 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6802 | }, |
6803 | ||
43234a1e L |
6804 | /* VEX_LEN_0F41_P_0 */ |
6805 | { | |
6806 | { Bad_Opcode }, | |
6807 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
6808 | }, | |
1ba585e8 IT |
6809 | /* VEX_LEN_0F41_P_2 */ |
6810 | { | |
6811 | { Bad_Opcode }, | |
6812 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
6813 | }, | |
43234a1e L |
6814 | /* VEX_LEN_0F42_P_0 */ |
6815 | { | |
6816 | { Bad_Opcode }, | |
6817 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
6818 | }, | |
1ba585e8 IT |
6819 | /* VEX_LEN_0F42_P_2 */ |
6820 | { | |
6821 | { Bad_Opcode }, | |
6822 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
6823 | }, | |
43234a1e L |
6824 | /* VEX_LEN_0F44_P_0 */ |
6825 | { | |
6826 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
6827 | }, | |
1ba585e8 IT |
6828 | /* VEX_LEN_0F44_P_2 */ |
6829 | { | |
6830 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
6831 | }, | |
43234a1e L |
6832 | /* VEX_LEN_0F45_P_0 */ |
6833 | { | |
6834 | { Bad_Opcode }, | |
6835 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
6836 | }, | |
1ba585e8 IT |
6837 | /* VEX_LEN_0F45_P_2 */ |
6838 | { | |
6839 | { Bad_Opcode }, | |
6840 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
6841 | }, | |
43234a1e L |
6842 | /* VEX_LEN_0F46_P_0 */ |
6843 | { | |
6844 | { Bad_Opcode }, | |
6845 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
6846 | }, | |
1ba585e8 IT |
6847 | /* VEX_LEN_0F46_P_2 */ |
6848 | { | |
6849 | { Bad_Opcode }, | |
6850 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
6851 | }, | |
43234a1e L |
6852 | /* VEX_LEN_0F47_P_0 */ |
6853 | { | |
6854 | { Bad_Opcode }, | |
6855 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
6856 | }, | |
1ba585e8 IT |
6857 | /* VEX_LEN_0F47_P_2 */ |
6858 | { | |
6859 | { Bad_Opcode }, | |
6860 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
6861 | }, | |
6862 | /* VEX_LEN_0F4A_P_0 */ | |
6863 | { | |
6864 | { Bad_Opcode }, | |
6865 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
6866 | }, | |
6867 | /* VEX_LEN_0F4A_P_2 */ | |
6868 | { | |
6869 | { Bad_Opcode }, | |
6870 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
6871 | }, | |
6872 | /* VEX_LEN_0F4B_P_0 */ | |
6873 | { | |
6874 | { Bad_Opcode }, | |
6875 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
6876 | }, | |
43234a1e L |
6877 | /* VEX_LEN_0F4B_P_2 */ |
6878 | { | |
6879 | { Bad_Opcode }, | |
6880 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
6881 | }, | |
6882 | ||
7531c613 | 6883 | /* VEX_LEN_0F6E */ |
c0f3af97 | 6884 | { |
7531c613 | 6885 | { "vmovK", { XMScalar, Edq }, PREFIX_DATA }, |
c0f3af97 L |
6886 | }, |
6887 | ||
035e7389 | 6888 | /* VEX_LEN_0F77 */ |
c0f3af97 | 6889 | { |
ec6f095a L |
6890 | { "vzeroupper", { XX }, 0 }, |
6891 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
6892 | }, |
6893 | ||
ec6f095a | 6894 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 6895 | { |
5b872f7d | 6896 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
6897 | }, |
6898 | ||
ec6f095a | 6899 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 6900 | { |
ec6f095a | 6901 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
6902 | }, |
6903 | ||
ec6f095a | 6904 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 6905 | { |
ec6f095a | 6906 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
6907 | }, |
6908 | ||
ec6f095a | 6909 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 6910 | { |
ec6f095a | 6911 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
6912 | }, |
6913 | ||
ec6f095a | 6914 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 6915 | { |
ec6f095a | 6916 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
6917 | }, |
6918 | ||
ec6f095a | 6919 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 6920 | { |
ec6f095a | 6921 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
6922 | }, |
6923 | ||
ec6f095a | 6924 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 6925 | { |
ec6f095a | 6926 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
6927 | }, |
6928 | ||
ec6f095a | 6929 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 6930 | { |
ec6f095a | 6931 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
6932 | }, |
6933 | ||
ec6f095a | 6934 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 6935 | { |
58a211d2 | 6936 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
6937 | }, |
6938 | ||
ec6f095a | 6939 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 6940 | { |
ec6f095a | 6941 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
6942 | }, |
6943 | ||
ec6f095a | 6944 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 6945 | { |
ec6f095a | 6946 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
6947 | }, |
6948 | ||
ec6f095a | 6949 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 6950 | { |
58a211d2 | 6951 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
6952 | }, |
6953 | ||
ec6f095a | 6954 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
6955 | { |
6956 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
6957 | }, | |
6958 | ||
1ba585e8 IT |
6959 | /* VEX_LEN_0F98_P_2 */ |
6960 | { | |
6961 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
6962 | }, | |
6963 | ||
6964 | /* VEX_LEN_0F99_P_0 */ | |
6965 | { | |
6966 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
6967 | }, | |
6968 | ||
6969 | /* VEX_LEN_0F99_P_2 */ | |
6970 | { | |
6971 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
6972 | }, | |
6973 | ||
6c30d220 | 6974 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 6975 | { |
ec6f095a | 6976 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
6977 | }, |
6978 | ||
6c30d220 | 6979 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 6980 | { |
ec6f095a | 6981 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
6982 | }, |
6983 | ||
7531c613 | 6984 | /* VEX_LEN_0FC4 */ |
c0f3af97 | 6985 | { |
7531c613 | 6986 | { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6987 | }, |
6988 | ||
7531c613 | 6989 | /* VEX_LEN_0FC5 */ |
c0f3af97 | 6990 | { |
7531c613 | 6991 | { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6992 | }, |
6993 | ||
7531c613 | 6994 | /* VEX_LEN_0FD6 */ |
c0f3af97 | 6995 | { |
7531c613 | 6996 | { "vmovq", { EXqS, XMScalar }, PREFIX_DATA }, |
c0f3af97 L |
6997 | }, |
6998 | ||
7531c613 | 6999 | /* VEX_LEN_0FF7 */ |
c0f3af97 | 7000 | { |
7531c613 | 7001 | { "vmaskmovdqu", { XM, XS }, PREFIX_DATA }, |
c0f3af97 L |
7002 | }, |
7003 | ||
7531c613 | 7004 | /* VEX_LEN_0F3816 */ |
c0f3af97 | 7005 | { |
6c30d220 | 7006 | { Bad_Opcode }, |
7531c613 | 7007 | { VEX_W_TABLE (VEX_W_0F3816_L_1) }, |
c0f3af97 L |
7008 | }, |
7009 | ||
7531c613 | 7010 | /* VEX_LEN_0F3819 */ |
c0f3af97 | 7011 | { |
6c30d220 | 7012 | { Bad_Opcode }, |
7531c613 | 7013 | { VEX_W_TABLE (VEX_W_0F3819_L_1) }, |
c0f3af97 L |
7014 | }, |
7015 | ||
7531c613 | 7016 | /* VEX_LEN_0F381A_M_0 */ |
c0f3af97 | 7017 | { |
6c30d220 | 7018 | { Bad_Opcode }, |
7531c613 | 7019 | { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) }, |
c0f3af97 L |
7020 | }, |
7021 | ||
7531c613 | 7022 | /* VEX_LEN_0F3836 */ |
c0f3af97 | 7023 | { |
6c30d220 | 7024 | { Bad_Opcode }, |
7531c613 | 7025 | { VEX_W_TABLE (VEX_W_0F3836) }, |
c0f3af97 L |
7026 | }, |
7027 | ||
7531c613 | 7028 | /* VEX_LEN_0F3841 */ |
c0f3af97 | 7029 | { |
7531c613 | 7030 | { "vphminposuw", { XM, EXx }, PREFIX_DATA }, |
c0f3af97 L |
7031 | }, |
7032 | ||
260cd341 LC |
7033 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */ |
7034 | { | |
7035 | { "ldtilecfg", { M }, 0 }, | |
7036 | }, | |
7037 | ||
7038 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */ | |
7039 | { | |
7040 | { "tilerelease", { Skip_MODRM }, 0 }, | |
7041 | }, | |
7042 | ||
7043 | /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */ | |
7044 | { | |
7045 | { "sttilecfg", { M }, 0 }, | |
7046 | }, | |
7047 | ||
7048 | /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */ | |
7049 | { | |
7050 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
7051 | }, | |
7052 | ||
7053 | /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */ | |
7054 | { | |
7055 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
7056 | }, | |
7057 | /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */ | |
7058 | { | |
7059 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
7060 | }, | |
7061 | ||
7062 | /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */ | |
7063 | { | |
7064 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
7065 | }, | |
7066 | ||
7531c613 | 7067 | /* VEX_LEN_0F385A_M_0 */ |
6c30d220 L |
7068 | { |
7069 | { Bad_Opcode }, | |
7531c613 | 7070 | { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) }, |
6c30d220 L |
7071 | }, |
7072 | ||
260cd341 LC |
7073 | /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */ |
7074 | { | |
7075 | { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 }, | |
7076 | }, | |
7077 | ||
7078 | /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */ | |
7079 | { | |
7080 | { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, | |
7081 | }, | |
7082 | ||
7083 | /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */ | |
7084 | { | |
7085 | { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 }, | |
7086 | }, | |
7087 | ||
7088 | /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */ | |
7089 | { | |
7090 | { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 }, | |
7091 | }, | |
7092 | ||
7093 | /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */ | |
7094 | { | |
7095 | { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 }, | |
7096 | }, | |
7097 | ||
7531c613 | 7098 | /* VEX_LEN_0F38DB */ |
a5ff0eb2 | 7099 | { |
7531c613 | 7100 | { "vaesimc", { XM, EXx }, PREFIX_DATA }, |
a5ff0eb2 L |
7101 | }, |
7102 | ||
035e7389 | 7103 | /* VEX_LEN_0F38F2 */ |
f12dc422 | 7104 | { |
035e7389 | 7105 | { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7106 | }, |
7107 | ||
035e7389 | 7108 | /* VEX_LEN_0F38F3_R_1 */ |
f12dc422 | 7109 | { |
035e7389 | 7110 | { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7111 | }, |
7112 | ||
035e7389 | 7113 | /* VEX_LEN_0F38F3_R_2 */ |
f12dc422 | 7114 | { |
035e7389 | 7115 | { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7116 | }, |
7117 | ||
035e7389 | 7118 | /* VEX_LEN_0F38F3_R_3 */ |
f12dc422 | 7119 | { |
035e7389 | 7120 | { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7121 | }, |
7122 | ||
6c30d220 L |
7123 | /* VEX_LEN_0F38F5_P_0 */ |
7124 | { | |
bf890a93 | 7125 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7126 | }, |
7127 | ||
7128 | /* VEX_LEN_0F38F5_P_1 */ | |
7129 | { | |
bf890a93 | 7130 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
7131 | }, |
7132 | ||
7133 | /* VEX_LEN_0F38F5_P_3 */ | |
7134 | { | |
bf890a93 | 7135 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
7136 | }, |
7137 | ||
7138 | /* VEX_LEN_0F38F6_P_3 */ | |
7139 | { | |
bf890a93 | 7140 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
7141 | }, |
7142 | ||
f12dc422 L |
7143 | /* VEX_LEN_0F38F7_P_0 */ |
7144 | { | |
bf890a93 | 7145 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
7146 | }, |
7147 | ||
6c30d220 L |
7148 | /* VEX_LEN_0F38F7_P_1 */ |
7149 | { | |
bf890a93 | 7150 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7151 | }, |
7152 | ||
7153 | /* VEX_LEN_0F38F7_P_2 */ | |
7154 | { | |
bf890a93 | 7155 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7156 | }, |
7157 | ||
7158 | /* VEX_LEN_0F38F7_P_3 */ | |
7159 | { | |
bf890a93 | 7160 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7161 | }, |
7162 | ||
7531c613 | 7163 | /* VEX_LEN_0F3A00 */ |
6c30d220 L |
7164 | { |
7165 | { Bad_Opcode }, | |
7531c613 | 7166 | { VEX_W_TABLE (VEX_W_0F3A00_L_1) }, |
6c30d220 L |
7167 | }, |
7168 | ||
7531c613 | 7169 | /* VEX_LEN_0F3A01 */ |
6c30d220 L |
7170 | { |
7171 | { Bad_Opcode }, | |
7531c613 | 7172 | { VEX_W_TABLE (VEX_W_0F3A01_L_1) }, |
6c30d220 L |
7173 | }, |
7174 | ||
7531c613 | 7175 | /* VEX_LEN_0F3A06 */ |
c0f3af97 | 7176 | { |
592d1631 | 7177 | { Bad_Opcode }, |
7531c613 | 7178 | { VEX_W_TABLE (VEX_W_0F3A06_L_1) }, |
c0f3af97 L |
7179 | }, |
7180 | ||
7531c613 | 7181 | /* VEX_LEN_0F3A14 */ |
c0f3af97 | 7182 | { |
7531c613 | 7183 | { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7184 | }, |
7185 | ||
7531c613 | 7186 | /* VEX_LEN_0F3A15 */ |
c0f3af97 | 7187 | { |
7531c613 | 7188 | { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7189 | }, |
7190 | ||
7531c613 | 7191 | /* VEX_LEN_0F3A16 */ |
c0f3af97 | 7192 | { |
7531c613 | 7193 | { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7194 | }, |
7195 | ||
7531c613 | 7196 | /* VEX_LEN_0F3A17 */ |
c0f3af97 | 7197 | { |
7531c613 | 7198 | { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7199 | }, |
7200 | ||
7531c613 | 7201 | /* VEX_LEN_0F3A18 */ |
c0f3af97 | 7202 | { |
592d1631 | 7203 | { Bad_Opcode }, |
7531c613 | 7204 | { VEX_W_TABLE (VEX_W_0F3A18_L_1) }, |
c0f3af97 L |
7205 | }, |
7206 | ||
7531c613 | 7207 | /* VEX_LEN_0F3A19 */ |
c0f3af97 | 7208 | { |
592d1631 | 7209 | { Bad_Opcode }, |
7531c613 | 7210 | { VEX_W_TABLE (VEX_W_0F3A19_L_1) }, |
c0f3af97 L |
7211 | }, |
7212 | ||
7531c613 | 7213 | /* VEX_LEN_0F3A20 */ |
c0f3af97 | 7214 | { |
7531c613 | 7215 | { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7216 | }, |
7217 | ||
7531c613 | 7218 | /* VEX_LEN_0F3A21 */ |
c0f3af97 | 7219 | { |
7531c613 | 7220 | { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7221 | }, |
7222 | ||
7531c613 | 7223 | /* VEX_LEN_0F3A22 */ |
c0f3af97 | 7224 | { |
7531c613 | 7225 | { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7226 | }, |
7227 | ||
7531c613 | 7228 | /* VEX_LEN_0F3A30 */ |
43234a1e | 7229 | { |
bb5b3501 | 7230 | { MOD_TABLE (MOD_VEX_0F3A30_L_0) }, |
43234a1e L |
7231 | }, |
7232 | ||
7531c613 | 7233 | /* VEX_LEN_0F3A31 */ |
1ba585e8 | 7234 | { |
bb5b3501 | 7235 | { MOD_TABLE (MOD_VEX_0F3A31_L_0) }, |
1ba585e8 IT |
7236 | }, |
7237 | ||
7531c613 | 7238 | /* VEX_LEN_0F3A32 */ |
43234a1e | 7239 | { |
bb5b3501 | 7240 | { MOD_TABLE (MOD_VEX_0F3A32_L_0) }, |
43234a1e L |
7241 | }, |
7242 | ||
7531c613 | 7243 | /* VEX_LEN_0F3A33 */ |
1ba585e8 | 7244 | { |
bb5b3501 | 7245 | { MOD_TABLE (MOD_VEX_0F3A33_L_0) }, |
1ba585e8 IT |
7246 | }, |
7247 | ||
7531c613 | 7248 | /* VEX_LEN_0F3A38 */ |
c0f3af97 | 7249 | { |
6c30d220 | 7250 | { Bad_Opcode }, |
7531c613 | 7251 | { VEX_W_TABLE (VEX_W_0F3A38_L_1) }, |
c0f3af97 L |
7252 | }, |
7253 | ||
7531c613 | 7254 | /* VEX_LEN_0F3A39 */ |
c0f3af97 | 7255 | { |
6c30d220 | 7256 | { Bad_Opcode }, |
7531c613 | 7257 | { VEX_W_TABLE (VEX_W_0F3A39_L_1) }, |
6c30d220 L |
7258 | }, |
7259 | ||
7531c613 | 7260 | /* VEX_LEN_0F3A41 */ |
6c30d220 | 7261 | { |
7531c613 | 7262 | { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7263 | }, |
7264 | ||
7531c613 | 7265 | /* VEX_LEN_0F3A46 */ |
c0f3af97 | 7266 | { |
6c30d220 | 7267 | { Bad_Opcode }, |
7531c613 | 7268 | { VEX_W_TABLE (VEX_W_0F3A46_L_1) }, |
c0f3af97 L |
7269 | }, |
7270 | ||
7531c613 | 7271 | /* VEX_LEN_0F3A60 */ |
c0f3af97 | 7272 | { |
7531c613 | 7273 | { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7274 | }, |
7275 | ||
7531c613 | 7276 | /* VEX_LEN_0F3A61 */ |
c0f3af97 | 7277 | { |
7531c613 | 7278 | { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7279 | }, |
7280 | ||
7531c613 | 7281 | /* VEX_LEN_0F3A62 */ |
c0f3af97 | 7282 | { |
7531c613 | 7283 | { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7284 | }, |
7285 | ||
7531c613 | 7286 | /* VEX_LEN_0F3A63 */ |
c0f3af97 | 7287 | { |
7531c613 | 7288 | { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7289 | }, |
7290 | ||
7531c613 | 7291 | /* VEX_LEN_0F3ADF */ |
a5ff0eb2 | 7292 | { |
7531c613 | 7293 | { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
a5ff0eb2 | 7294 | }, |
4c807e72 | 7295 | |
6c30d220 L |
7296 | /* VEX_LEN_0F3AF0_P_3 */ |
7297 | { | |
bf890a93 | 7298 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
7299 | }, |
7300 | ||
467bbef0 JB |
7301 | /* VEX_LEN_0FXOP_08_85 */ |
7302 | { | |
7303 | { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) }, | |
7304 | }, | |
7305 | ||
7306 | /* VEX_LEN_0FXOP_08_86 */ | |
7307 | { | |
7308 | { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) }, | |
7309 | }, | |
7310 | ||
7311 | /* VEX_LEN_0FXOP_08_87 */ | |
7312 | { | |
7313 | { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) }, | |
7314 | }, | |
7315 | ||
7316 | /* VEX_LEN_0FXOP_08_8E */ | |
7317 | { | |
7318 | { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) }, | |
7319 | }, | |
7320 | ||
7321 | /* VEX_LEN_0FXOP_08_8F */ | |
7322 | { | |
7323 | { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) }, | |
7324 | }, | |
7325 | ||
7326 | /* VEX_LEN_0FXOP_08_95 */ | |
7327 | { | |
7328 | { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) }, | |
7329 | }, | |
7330 | ||
7331 | /* VEX_LEN_0FXOP_08_96 */ | |
7332 | { | |
7333 | { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) }, | |
7334 | }, | |
7335 | ||
7336 | /* VEX_LEN_0FXOP_08_97 */ | |
7337 | { | |
7338 | { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) }, | |
7339 | }, | |
7340 | ||
7341 | /* VEX_LEN_0FXOP_08_9E */ | |
7342 | { | |
7343 | { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) }, | |
7344 | }, | |
7345 | ||
7346 | /* VEX_LEN_0FXOP_08_9F */ | |
7347 | { | |
7348 | { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) }, | |
7349 | }, | |
7350 | ||
7351 | /* VEX_LEN_0FXOP_08_A3 */ | |
7352 | { | |
7353 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7354 | }, | |
7355 | ||
7356 | /* VEX_LEN_0FXOP_08_A6 */ | |
7357 | { | |
7358 | { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) }, | |
7359 | }, | |
7360 | ||
7361 | /* VEX_LEN_0FXOP_08_B6 */ | |
7362 | { | |
7363 | { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) }, | |
7364 | }, | |
7365 | ||
7366 | /* VEX_LEN_0FXOP_08_C0 */ | |
7367 | { | |
7368 | { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) }, | |
7369 | }, | |
7370 | ||
7371 | /* VEX_LEN_0FXOP_08_C1 */ | |
7372 | { | |
7373 | { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) }, | |
7374 | }, | |
7375 | ||
7376 | /* VEX_LEN_0FXOP_08_C2 */ | |
7377 | { | |
7378 | { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) }, | |
7379 | }, | |
7380 | ||
7381 | /* VEX_LEN_0FXOP_08_C3 */ | |
7382 | { | |
7383 | { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) }, | |
7384 | }, | |
7385 | ||
ff688e1f L |
7386 | /* VEX_LEN_0FXOP_08_CC */ |
7387 | { | |
467bbef0 | 7388 | { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) }, |
ff688e1f L |
7389 | }, |
7390 | ||
7391 | /* VEX_LEN_0FXOP_08_CD */ | |
7392 | { | |
467bbef0 | 7393 | { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) }, |
ff688e1f L |
7394 | }, |
7395 | ||
7396 | /* VEX_LEN_0FXOP_08_CE */ | |
7397 | { | |
467bbef0 | 7398 | { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) }, |
ff688e1f L |
7399 | }, |
7400 | ||
7401 | /* VEX_LEN_0FXOP_08_CF */ | |
7402 | { | |
467bbef0 | 7403 | { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) }, |
ff688e1f L |
7404 | }, |
7405 | ||
7406 | /* VEX_LEN_0FXOP_08_EC */ | |
7407 | { | |
467bbef0 | 7408 | { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) }, |
ff688e1f L |
7409 | }, |
7410 | ||
7411 | /* VEX_LEN_0FXOP_08_ED */ | |
7412 | { | |
467bbef0 | 7413 | { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) }, |
ff688e1f L |
7414 | }, |
7415 | ||
7416 | /* VEX_LEN_0FXOP_08_EE */ | |
7417 | { | |
467bbef0 | 7418 | { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) }, |
ff688e1f L |
7419 | }, |
7420 | ||
7421 | /* VEX_LEN_0FXOP_08_EF */ | |
7422 | { | |
467bbef0 JB |
7423 | { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) }, |
7424 | }, | |
7425 | ||
7426 | /* VEX_LEN_0FXOP_09_01 */ | |
7427 | { | |
7428 | { REG_TABLE (REG_0FXOP_09_01_L_0) }, | |
7429 | }, | |
7430 | ||
7431 | /* VEX_LEN_0FXOP_09_02 */ | |
7432 | { | |
7433 | { REG_TABLE (REG_0FXOP_09_02_L_0) }, | |
7434 | }, | |
7435 | ||
7436 | /* VEX_LEN_0FXOP_09_12_M_1 */ | |
7437 | { | |
7438 | { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) }, | |
ff688e1f L |
7439 | }, |
7440 | ||
b5b098c2 | 7441 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 7442 | { |
b5b098c2 | 7443 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 7444 | }, |
4c807e72 | 7445 | |
b5b098c2 | 7446 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 7447 | { |
b5b098c2 | 7448 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 7449 | }, |
467bbef0 JB |
7450 | |
7451 | /* VEX_LEN_0FXOP_09_90 */ | |
7452 | { | |
7453 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
7454 | }, | |
7455 | ||
7456 | /* VEX_LEN_0FXOP_09_91 */ | |
7457 | { | |
7458 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
7459 | }, | |
7460 | ||
7461 | /* VEX_LEN_0FXOP_09_92 */ | |
7462 | { | |
7463 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
7464 | }, | |
7465 | ||
7466 | /* VEX_LEN_0FXOP_09_93 */ | |
7467 | { | |
7468 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
7469 | }, | |
7470 | ||
7471 | /* VEX_LEN_0FXOP_09_94 */ | |
7472 | { | |
7473 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
7474 | }, | |
7475 | ||
7476 | /* VEX_LEN_0FXOP_09_95 */ | |
7477 | { | |
7478 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
7479 | }, | |
7480 | ||
7481 | /* VEX_LEN_0FXOP_09_96 */ | |
7482 | { | |
7483 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
7484 | }, | |
7485 | ||
7486 | /* VEX_LEN_0FXOP_09_97 */ | |
7487 | { | |
7488 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
7489 | }, | |
7490 | ||
7491 | /* VEX_LEN_0FXOP_09_98 */ | |
7492 | { | |
7493 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
7494 | }, | |
7495 | ||
7496 | /* VEX_LEN_0FXOP_09_99 */ | |
7497 | { | |
7498 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
7499 | }, | |
7500 | ||
7501 | /* VEX_LEN_0FXOP_09_9A */ | |
7502 | { | |
7503 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
7504 | }, | |
7505 | ||
7506 | /* VEX_LEN_0FXOP_09_9B */ | |
7507 | { | |
7508 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
7509 | }, | |
7510 | ||
7511 | /* VEX_LEN_0FXOP_09_C1 */ | |
7512 | { | |
7513 | { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) }, | |
7514 | }, | |
7515 | ||
7516 | /* VEX_LEN_0FXOP_09_C2 */ | |
7517 | { | |
7518 | { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) }, | |
7519 | }, | |
7520 | ||
7521 | /* VEX_LEN_0FXOP_09_C3 */ | |
7522 | { | |
7523 | { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) }, | |
7524 | }, | |
7525 | ||
7526 | /* VEX_LEN_0FXOP_09_C6 */ | |
7527 | { | |
7528 | { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) }, | |
7529 | }, | |
7530 | ||
7531 | /* VEX_LEN_0FXOP_09_C7 */ | |
7532 | { | |
7533 | { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) }, | |
7534 | }, | |
7535 | ||
7536 | /* VEX_LEN_0FXOP_09_CB */ | |
7537 | { | |
7538 | { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) }, | |
7539 | }, | |
7540 | ||
7541 | /* VEX_LEN_0FXOP_09_D1 */ | |
7542 | { | |
7543 | { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) }, | |
7544 | }, | |
7545 | ||
7546 | /* VEX_LEN_0FXOP_09_D2 */ | |
7547 | { | |
7548 | { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) }, | |
7549 | }, | |
7550 | ||
7551 | /* VEX_LEN_0FXOP_09_D3 */ | |
7552 | { | |
7553 | { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) }, | |
7554 | }, | |
7555 | ||
7556 | /* VEX_LEN_0FXOP_09_D6 */ | |
7557 | { | |
7558 | { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) }, | |
7559 | }, | |
7560 | ||
7561 | /* VEX_LEN_0FXOP_09_D7 */ | |
7562 | { | |
7563 | { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) }, | |
7564 | }, | |
7565 | ||
7566 | /* VEX_LEN_0FXOP_09_DB */ | |
7567 | { | |
7568 | { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) }, | |
7569 | }, | |
7570 | ||
7571 | /* VEX_LEN_0FXOP_09_E1 */ | |
7572 | { | |
7573 | { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) }, | |
7574 | }, | |
7575 | ||
7576 | /* VEX_LEN_0FXOP_09_E2 */ | |
7577 | { | |
7578 | { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) }, | |
7579 | }, | |
7580 | ||
7581 | /* VEX_LEN_0FXOP_09_E3 */ | |
7582 | { | |
7583 | { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) }, | |
7584 | }, | |
7585 | ||
7586 | /* VEX_LEN_0FXOP_0A_12 */ | |
7587 | { | |
7588 | { REG_TABLE (REG_0FXOP_0A_12_L_0) }, | |
7589 | }, | |
331d2d0d L |
7590 | }; |
7591 | ||
ad692897 | 7592 | #include "i386-dis-evex-len.h" |
04e2a182 | 7593 | |
9e30b8e0 | 7594 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
7595 | { |
7596 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
7597 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
7598 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
7599 | }, |
7600 | { | |
7601 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
7602 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
7603 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
7604 | }, |
7605 | { | |
7606 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
7607 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
7608 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
7609 | }, |
7610 | { | |
7611 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
7612 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
7613 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
7614 | }, |
7615 | { | |
7616 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
7617 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
7618 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
7619 | }, |
7620 | { | |
7621 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
7622 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
7623 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
7624 | }, |
7625 | { | |
ec6f095a L |
7626 | /* VEX_W_0F45_P_0_LEN_1 */ |
7627 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
7628 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
7629 | }, |
7630 | { | |
ec6f095a L |
7631 | /* VEX_W_0F45_P_2_LEN_1 */ |
7632 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
7633 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
7634 | }, |
7635 | { | |
ec6f095a L |
7636 | /* VEX_W_0F46_P_0_LEN_1 */ |
7637 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
7638 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
7639 | }, |
7640 | { | |
ec6f095a L |
7641 | /* VEX_W_0F46_P_2_LEN_1 */ |
7642 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
7643 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
7644 | }, |
7645 | { | |
ec6f095a L |
7646 | /* VEX_W_0F47_P_0_LEN_1 */ |
7647 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
7648 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
7649 | }, |
7650 | { | |
ec6f095a L |
7651 | /* VEX_W_0F47_P_2_LEN_1 */ |
7652 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
7653 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
7654 | }, |
7655 | { | |
ec6f095a L |
7656 | /* VEX_W_0F4A_P_0_LEN_1 */ |
7657 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
7658 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
7659 | }, |
7660 | { | |
ec6f095a L |
7661 | /* VEX_W_0F4A_P_2_LEN_1 */ |
7662 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
7663 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
7664 | }, |
7665 | { | |
ec6f095a L |
7666 | /* VEX_W_0F4B_P_0_LEN_1 */ |
7667 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
7668 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
7669 | }, |
7670 | { | |
ec6f095a L |
7671 | /* VEX_W_0F4B_P_2_LEN_1 */ |
7672 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
7673 | }, |
7674 | { | |
ec6f095a L |
7675 | /* VEX_W_0F90_P_0_LEN_0 */ |
7676 | { "kmovw", { MaskG, MaskE }, 0 }, | |
7677 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
7678 | }, |
7679 | { | |
ec6f095a L |
7680 | /* VEX_W_0F90_P_2_LEN_0 */ |
7681 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
7682 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
7683 | }, |
7684 | { | |
ec6f095a L |
7685 | /* VEX_W_0F91_P_0_LEN_0 */ |
7686 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
7687 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
7688 | }, |
7689 | { | |
ec6f095a L |
7690 | /* VEX_W_0F91_P_2_LEN_0 */ |
7691 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
7692 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
7693 | }, |
7694 | { | |
ec6f095a L |
7695 | /* VEX_W_0F92_P_0_LEN_0 */ |
7696 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
7697 | }, |
7698 | { | |
ec6f095a L |
7699 | /* VEX_W_0F92_P_2_LEN_0 */ |
7700 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 7701 | }, |
9e30b8e0 | 7702 | { |
ec6f095a L |
7703 | /* VEX_W_0F93_P_0_LEN_0 */ |
7704 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
7705 | }, |
7706 | { | |
ec6f095a L |
7707 | /* VEX_W_0F93_P_2_LEN_0 */ |
7708 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 7709 | }, |
9e30b8e0 | 7710 | { |
ec6f095a L |
7711 | /* VEX_W_0F98_P_0_LEN_0 */ |
7712 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
7713 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
7714 | }, |
7715 | { | |
ec6f095a L |
7716 | /* VEX_W_0F98_P_2_LEN_0 */ |
7717 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
7718 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
7719 | }, |
7720 | { | |
ec6f095a L |
7721 | /* VEX_W_0F99_P_0_LEN_0 */ |
7722 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
7723 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
7724 | }, |
7725 | { | |
ec6f095a L |
7726 | /* VEX_W_0F99_P_2_LEN_0 */ |
7727 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
7728 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 7729 | }, |
9e30b8e0 | 7730 | { |
7531c613 JB |
7731 | /* VEX_W_0F380C */ |
7732 | { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7733 | }, |
7734 | { | |
7531c613 JB |
7735 | /* VEX_W_0F380D */ |
7736 | { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7737 | }, |
7738 | { | |
7531c613 JB |
7739 | /* VEX_W_0F380E */ |
7740 | { "vtestps", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7741 | }, |
7742 | { | |
7531c613 JB |
7743 | /* VEX_W_0F380F */ |
7744 | { "vtestpd", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7745 | }, |
6431c801 | 7746 | { |
7531c613 JB |
7747 | /* VEX_W_0F3813 */ |
7748 | { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA }, | |
6431c801 | 7749 | }, |
6c30d220 | 7750 | { |
7531c613 JB |
7751 | /* VEX_W_0F3816_L_1 */ |
7752 | { "vpermps", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7753 | }, |
bcf2684f | 7754 | { |
7531c613 JB |
7755 | /* VEX_W_0F3818 */ |
7756 | { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA }, | |
bcf2684f | 7757 | }, |
9e30b8e0 | 7758 | { |
7531c613 JB |
7759 | /* VEX_W_0F3819_L_1 */ |
7760 | { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA }, | |
9e30b8e0 L |
7761 | }, |
7762 | { | |
7531c613 JB |
7763 | /* VEX_W_0F381A_M_0_L_1 */ |
7764 | { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA }, | |
9e30b8e0 | 7765 | }, |
53aa04a0 | 7766 | { |
7531c613 JB |
7767 | /* VEX_W_0F382C_M_0 */ |
7768 | { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA }, | |
53aa04a0 L |
7769 | }, |
7770 | { | |
7531c613 JB |
7771 | /* VEX_W_0F382D_M_0 */ |
7772 | { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA }, | |
53aa04a0 L |
7773 | }, |
7774 | { | |
7531c613 JB |
7775 | /* VEX_W_0F382E_M_0 */ |
7776 | { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA }, | |
53aa04a0 L |
7777 | }, |
7778 | { | |
7531c613 JB |
7779 | /* VEX_W_0F382F_M_0 */ |
7780 | { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA }, | |
53aa04a0 | 7781 | }, |
6c30d220 | 7782 | { |
7531c613 JB |
7783 | /* VEX_W_0F3836 */ |
7784 | { "vpermd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7785 | }, |
6c30d220 | 7786 | { |
7531c613 JB |
7787 | /* VEX_W_0F3846 */ |
7788 | { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7789 | }, |
260cd341 LC |
7790 | { |
7791 | /* VEX_W_0F3849_X86_64_P_0 */ | |
7792 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) }, | |
7793 | }, | |
7794 | { | |
7795 | /* VEX_W_0F3849_X86_64_P_2 */ | |
7796 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) }, | |
7797 | }, | |
7798 | { | |
7799 | /* VEX_W_0F3849_X86_64_P_3 */ | |
7800 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) }, | |
7801 | }, | |
7802 | { | |
7803 | /* VEX_W_0F384B_X86_64_P_1 */ | |
7804 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) }, | |
7805 | }, | |
7806 | { | |
7807 | /* VEX_W_0F384B_X86_64_P_2 */ | |
7808 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) }, | |
7809 | }, | |
7810 | { | |
7811 | /* VEX_W_0F384B_X86_64_P_3 */ | |
7812 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) }, | |
7813 | }, | |
58bf9b6a L |
7814 | { |
7815 | /* VEX_W_0F3850 */ | |
7816 | { "%XV vpdpbusd", { XM, Vex, EXx }, 0 }, | |
7817 | }, | |
7818 | { | |
7819 | /* VEX_W_0F3851 */ | |
7820 | { "%XV vpdpbusds", { XM, Vex, EXx }, 0 }, | |
7821 | }, | |
7822 | { | |
7823 | /* VEX_W_0F3852 */ | |
7824 | { "%XV vpdpwssd", { XM, Vex, EXx }, 0 }, | |
7825 | }, | |
7826 | { | |
7827 | /* VEX_W_0F3853 */ | |
7828 | { "%XV vpdpwssds", { XM, Vex, EXx }, 0 }, | |
7829 | }, | |
6c30d220 | 7830 | { |
7531c613 JB |
7831 | /* VEX_W_0F3858 */ |
7832 | { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA }, | |
6c30d220 L |
7833 | }, |
7834 | { | |
7531c613 JB |
7835 | /* VEX_W_0F3859 */ |
7836 | { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA }, | |
6c30d220 L |
7837 | }, |
7838 | { | |
7531c613 JB |
7839 | /* VEX_W_0F385A_M_0_L_0 */ |
7840 | { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA }, | |
6c30d220 | 7841 | }, |
260cd341 LC |
7842 | { |
7843 | /* VEX_W_0F385C_X86_64_P_1 */ | |
7844 | { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) }, | |
7845 | }, | |
7846 | { | |
7847 | /* VEX_W_0F385E_X86_64_P_0 */ | |
7848 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, | |
7849 | }, | |
7850 | { | |
7851 | /* VEX_W_0F385E_X86_64_P_1 */ | |
7852 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) }, | |
7853 | }, | |
7854 | { | |
7855 | /* VEX_W_0F385E_X86_64_P_2 */ | |
7856 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) }, | |
7857 | }, | |
7858 | { | |
7859 | /* VEX_W_0F385E_X86_64_P_3 */ | |
7860 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, | |
7861 | }, | |
6c30d220 | 7862 | { |
7531c613 JB |
7863 | /* VEX_W_0F3878 */ |
7864 | { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA }, | |
6c30d220 L |
7865 | }, |
7866 | { | |
7531c613 JB |
7867 | /* VEX_W_0F3879 */ |
7868 | { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA }, | |
6c30d220 | 7869 | }, |
48521003 | 7870 | { |
7531c613 JB |
7871 | /* VEX_W_0F38CF */ |
7872 | { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, | |
48521003 | 7873 | }, |
6c30d220 | 7874 | { |
7531c613 | 7875 | /* VEX_W_0F3A00_L_1 */ |
6c30d220 | 7876 | { Bad_Opcode }, |
7531c613 | 7877 | { "vpermq", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7878 | }, |
7879 | { | |
7531c613 | 7880 | /* VEX_W_0F3A01_L_1 */ |
6c30d220 | 7881 | { Bad_Opcode }, |
7531c613 | 7882 | { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7883 | }, |
7884 | { | |
7531c613 JB |
7885 | /* VEX_W_0F3A02 */ |
7886 | { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7887 | }, |
9e30b8e0 | 7888 | { |
7531c613 JB |
7889 | /* VEX_W_0F3A04 */ |
7890 | { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7891 | }, |
7892 | { | |
7531c613 JB |
7893 | /* VEX_W_0F3A05 */ |
7894 | { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7895 | }, |
7896 | { | |
7531c613 JB |
7897 | /* VEX_W_0F3A06_L_1 */ |
7898 | { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7899 | }, |
9e30b8e0 | 7900 | { |
7531c613 JB |
7901 | /* VEX_W_0F3A18_L_1 */ |
7902 | { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7903 | }, |
7904 | { | |
7531c613 JB |
7905 | /* VEX_W_0F3A19_L_1 */ |
7906 | { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7907 | }, |
6431c801 | 7908 | { |
7531c613 JB |
7909 | /* VEX_W_0F3A1D */ |
7910 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA }, | |
6431c801 | 7911 | }, |
6c30d220 | 7912 | { |
7531c613 JB |
7913 | /* VEX_W_0F3A38_L_1 */ |
7914 | { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
6c30d220 L |
7915 | }, |
7916 | { | |
7531c613 JB |
7917 | /* VEX_W_0F3A39_L_1 */ |
7918 | { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
6c30d220 | 7919 | }, |
6c30d220 | 7920 | { |
7531c613 JB |
7921 | /* VEX_W_0F3A46_L_1 */ |
7922 | { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7923 | }, |
9e30b8e0 | 7924 | { |
7531c613 JB |
7925 | /* VEX_W_0F3A4A */ |
7926 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7927 | }, |
7928 | { | |
7531c613 JB |
7929 | /* VEX_W_0F3A4B */ |
7930 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7931 | }, |
7932 | { | |
7531c613 JB |
7933 | /* VEX_W_0F3A4C */ |
7934 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 | 7935 | }, |
48521003 | 7936 | { |
7531c613 | 7937 | /* VEX_W_0F3ACE */ |
48521003 | 7938 | { Bad_Opcode }, |
7531c613 | 7939 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 IT |
7940 | }, |
7941 | { | |
7531c613 | 7942 | /* VEX_W_0F3ACF */ |
48521003 | 7943 | { Bad_Opcode }, |
7531c613 | 7944 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 | 7945 | }, |
467bbef0 JB |
7946 | /* VEX_W_0FXOP_08_85_L_0 */ |
7947 | { | |
7948 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7949 | }, | |
7950 | /* VEX_W_0FXOP_08_86_L_0 */ | |
7951 | { | |
7952 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7953 | }, | |
7954 | /* VEX_W_0FXOP_08_87_L_0 */ | |
7955 | { | |
7956 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7957 | }, | |
7958 | /* VEX_W_0FXOP_08_8E_L_0 */ | |
7959 | { | |
7960 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7961 | }, | |
7962 | /* VEX_W_0FXOP_08_8F_L_0 */ | |
7963 | { | |
7964 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7965 | }, | |
7966 | /* VEX_W_0FXOP_08_95_L_0 */ | |
7967 | { | |
7968 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7969 | }, | |
7970 | /* VEX_W_0FXOP_08_96_L_0 */ | |
7971 | { | |
7972 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7973 | }, | |
7974 | /* VEX_W_0FXOP_08_97_L_0 */ | |
7975 | { | |
7976 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7977 | }, | |
7978 | /* VEX_W_0FXOP_08_9E_L_0 */ | |
7979 | { | |
7980 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7981 | }, | |
7982 | /* VEX_W_0FXOP_08_9F_L_0 */ | |
7983 | { | |
7984 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7985 | }, | |
7986 | /* VEX_W_0FXOP_08_A6_L_0 */ | |
7987 | { | |
7988 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7989 | }, | |
7990 | /* VEX_W_0FXOP_08_B6_L_0 */ | |
7991 | { | |
7992 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7993 | }, | |
7994 | /* VEX_W_0FXOP_08_C0_L_0 */ | |
7995 | { | |
7996 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
7997 | }, | |
7998 | /* VEX_W_0FXOP_08_C1_L_0 */ | |
7999 | { | |
8000 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
8001 | }, | |
8002 | /* VEX_W_0FXOP_08_C2_L_0 */ | |
8003 | { | |
8004 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
8005 | }, | |
8006 | /* VEX_W_0FXOP_08_C3_L_0 */ | |
8007 | { | |
8008 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
8009 | }, | |
8010 | /* VEX_W_0FXOP_08_CC_L_0 */ | |
8011 | { | |
89e65d17 | 8012 | { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8013 | }, |
8014 | /* VEX_W_0FXOP_08_CD_L_0 */ | |
8015 | { | |
89e65d17 | 8016 | { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8017 | }, |
8018 | /* VEX_W_0FXOP_08_CE_L_0 */ | |
8019 | { | |
89e65d17 | 8020 | { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8021 | }, |
8022 | /* VEX_W_0FXOP_08_CF_L_0 */ | |
8023 | { | |
89e65d17 | 8024 | { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8025 | }, |
8026 | /* VEX_W_0FXOP_08_EC_L_0 */ | |
8027 | { | |
89e65d17 | 8028 | { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8029 | }, |
8030 | /* VEX_W_0FXOP_08_ED_L_0 */ | |
8031 | { | |
89e65d17 | 8032 | { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8033 | }, |
8034 | /* VEX_W_0FXOP_08_EE_L_0 */ | |
8035 | { | |
89e65d17 | 8036 | { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
8037 | }, |
8038 | /* VEX_W_0FXOP_08_EF_L_0 */ | |
8039 | { | |
89e65d17 | 8040 | { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 8041 | }, |
b5b098c2 JB |
8042 | /* VEX_W_0FXOP_09_80 */ |
8043 | { | |
8044 | { "vfrczps", { XM, EXx }, 0 }, | |
8045 | }, | |
8046 | /* VEX_W_0FXOP_09_81 */ | |
8047 | { | |
8048 | { "vfrczpd", { XM, EXx }, 0 }, | |
8049 | }, | |
8050 | /* VEX_W_0FXOP_09_82 */ | |
8051 | { | |
8052 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
8053 | }, | |
8054 | /* VEX_W_0FXOP_09_83 */ | |
8055 | { | |
8056 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
8057 | }, | |
467bbef0 JB |
8058 | /* VEX_W_0FXOP_09_C1_L_0 */ |
8059 | { | |
8060 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
8061 | }, | |
8062 | /* VEX_W_0FXOP_09_C2_L_0 */ | |
8063 | { | |
8064 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8065 | }, | |
8066 | /* VEX_W_0FXOP_09_C3_L_0 */ | |
8067 | { | |
8068 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
8069 | }, | |
8070 | /* VEX_W_0FXOP_09_C6_L_0 */ | |
8071 | { | |
8072 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
8073 | }, | |
8074 | /* VEX_W_0FXOP_09_C7_L_0 */ | |
8075 | { | |
8076 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
8077 | }, | |
8078 | /* VEX_W_0FXOP_09_CB_L_0 */ | |
8079 | { | |
8080 | { "vphadddq", { XM, EXxmm }, 0 }, | |
8081 | }, | |
8082 | /* VEX_W_0FXOP_09_D1_L_0 */ | |
8083 | { | |
8084 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
8085 | }, | |
8086 | /* VEX_W_0FXOP_09_D2_L_0 */ | |
8087 | { | |
8088 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8089 | }, | |
8090 | /* VEX_W_0FXOP_09_D3_L_0 */ | |
8091 | { | |
8092 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
8093 | }, | |
8094 | /* VEX_W_0FXOP_09_D6_L_0 */ | |
8095 | { | |
8096 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
8097 | }, | |
8098 | /* VEX_W_0FXOP_09_D7_L_0 */ | |
8099 | { | |
8100 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
8101 | }, | |
8102 | /* VEX_W_0FXOP_09_DB_L_0 */ | |
8103 | { | |
8104 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
8105 | }, | |
8106 | /* VEX_W_0FXOP_09_E1_L_0 */ | |
8107 | { | |
8108 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
8109 | }, | |
8110 | /* VEX_W_0FXOP_09_E2_L_0 */ | |
8111 | { | |
8112 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8113 | }, | |
8114 | /* VEX_W_0FXOP_09_E3_L_0 */ | |
8115 | { | |
8116 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
8117 | }, | |
ad692897 L |
8118 | |
8119 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
8120 | }; |
8121 | ||
8122 | static const struct dis386 mod_table[][2] = { | |
8123 | { | |
8124 | /* MOD_8D */ | |
bf890a93 | 8125 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 8126 | }, |
42164a71 L |
8127 | { |
8128 | /* MOD_C6_REG_7 */ | |
8129 | { Bad_Opcode }, | |
8130 | { RM_TABLE (RM_C6_REG_7) }, | |
8131 | }, | |
8132 | { | |
8133 | /* MOD_C7_REG_7 */ | |
8134 | { Bad_Opcode }, | |
8135 | { RM_TABLE (RM_C7_REG_7) }, | |
8136 | }, | |
4a357820 MZ |
8137 | { |
8138 | /* MOD_FF_REG_3 */ | |
8f570d62 | 8139 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
8140 | }, |
8141 | { | |
8142 | /* MOD_FF_REG_5 */ | |
8f570d62 | 8143 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 8144 | }, |
9e30b8e0 L |
8145 | { |
8146 | /* MOD_0F01_REG_0 */ | |
8147 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
8148 | { RM_TABLE (RM_0F01_REG_0) }, | |
8149 | }, | |
8150 | { | |
8151 | /* MOD_0F01_REG_1 */ | |
8152 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
8153 | { RM_TABLE (RM_0F01_REG_1) }, | |
8154 | }, | |
8155 | { | |
8156 | /* MOD_0F01_REG_2 */ | |
8157 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
8158 | { RM_TABLE (RM_0F01_REG_2) }, | |
8159 | }, | |
8160 | { | |
8161 | /* MOD_0F01_REG_3 */ | |
8162 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
8163 | { RM_TABLE (RM_0F01_REG_3) }, | |
8164 | }, | |
8eab4136 L |
8165 | { |
8166 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
8167 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
8168 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 8169 | }, |
9e30b8e0 L |
8170 | { |
8171 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 8172 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 8173 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
8174 | }, |
8175 | { | |
8176 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
8177 | { "movlpX", { XM, EXq }, 0 }, |
8178 | { "movhlps", { XM, EXq }, 0 }, | |
8179 | }, | |
8180 | { | |
8181 | /* MOD_0F12_PREFIX_2 */ | |
8182 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
8183 | }, |
8184 | { | |
8185 | /* MOD_0F13 */ | |
507bd325 | 8186 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
8187 | }, |
8188 | { | |
8189 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 8190 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 8191 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 8192 | }, |
18897deb JB |
8193 | { |
8194 | /* MOD_0F16_PREFIX_2 */ | |
8195 | { "movhpX", { XM, EXq }, 0 }, | |
8196 | }, | |
9e30b8e0 L |
8197 | { |
8198 | /* MOD_0F17 */ | |
507bd325 | 8199 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
8200 | }, |
8201 | { | |
8202 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 8203 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
8204 | }, |
8205 | { | |
8206 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 8207 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
8208 | }, |
8209 | { | |
8210 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 8211 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
8212 | }, |
8213 | { | |
8214 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 8215 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 8216 | }, |
d7189fa5 RM |
8217 | { |
8218 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 8219 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
8220 | }, |
8221 | { | |
8222 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 8223 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
8224 | }, |
8225 | { | |
8226 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 8227 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
8228 | }, |
8229 | { | |
8230 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 8231 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 8232 | }, |
7e8b059b L |
8233 | { |
8234 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 8235 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 8236 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
8237 | }, |
8238 | { | |
8239 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 8240 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 8241 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
8242 | }, |
8243 | { | |
8244 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 8245 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 8246 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 8247 | }, |
c48935d7 IT |
8248 | { |
8249 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 8250 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
8251 | { "nopQ", { Ev }, 0 }, |
8252 | }, | |
603555e5 L |
8253 | { |
8254 | /* MOD_0F1E_PREFIX_1 */ | |
8255 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 8256 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 8257 | }, |
75c135a8 L |
8258 | { |
8259 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 8260 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8261 | }, |
8262 | { | |
8263 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 8264 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8265 | }, |
8266 | { | |
8267 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 8268 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8269 | }, |
8270 | { | |
8271 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 8272 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8273 | }, |
8274 | { | |
a5aaedb9 | 8275 | /* MOD_0F50 */ |
592d1631 | 8276 | { Bad_Opcode }, |
507bd325 | 8277 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 8278 | }, |
b844680a | 8279 | { |
1ceb70f8 | 8280 | /* MOD_0F71_REG_2 */ |
592d1631 | 8281 | { Bad_Opcode }, |
7531c613 | 8282 | { "psrlw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8283 | }, |
8284 | { | |
1ceb70f8 | 8285 | /* MOD_0F71_REG_4 */ |
592d1631 | 8286 | { Bad_Opcode }, |
7531c613 | 8287 | { "psraw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8288 | }, |
8289 | { | |
1ceb70f8 | 8290 | /* MOD_0F71_REG_6 */ |
592d1631 | 8291 | { Bad_Opcode }, |
7531c613 | 8292 | { "psllw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8293 | }, |
8294 | { | |
1ceb70f8 | 8295 | /* MOD_0F72_REG_2 */ |
592d1631 | 8296 | { Bad_Opcode }, |
7531c613 | 8297 | { "psrld", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8298 | }, |
8299 | { | |
1ceb70f8 | 8300 | /* MOD_0F72_REG_4 */ |
592d1631 | 8301 | { Bad_Opcode }, |
7531c613 | 8302 | { "psrad", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8303 | }, |
8304 | { | |
1ceb70f8 | 8305 | /* MOD_0F72_REG_6 */ |
592d1631 | 8306 | { Bad_Opcode }, |
7531c613 | 8307 | { "pslld", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8308 | }, |
8309 | { | |
1ceb70f8 | 8310 | /* MOD_0F73_REG_2 */ |
592d1631 | 8311 | { Bad_Opcode }, |
7531c613 | 8312 | { "psrlq", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8313 | }, |
8314 | { | |
1ceb70f8 | 8315 | /* MOD_0F73_REG_3 */ |
592d1631 | 8316 | { Bad_Opcode }, |
7531c613 | 8317 | { "psrldq", { XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
8318 | }, |
8319 | { | |
8320 | /* MOD_0F73_REG_6 */ | |
592d1631 | 8321 | { Bad_Opcode }, |
7531c613 | 8322 | { "psllq", { MS, Ib }, PREFIX_OPCODE }, |
c0f3af97 L |
8323 | }, |
8324 | { | |
8325 | /* MOD_0F73_REG_7 */ | |
592d1631 | 8326 | { Bad_Opcode }, |
7531c613 | 8327 | { "pslldq", { XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
8328 | }, |
8329 | { | |
8330 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 8331 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 8332 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
8333 | }, |
8334 | { | |
8335 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 8336 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 8337 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
8338 | }, |
8339 | { | |
8340 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 8341 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 8342 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
8343 | }, |
8344 | { | |
8345 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 8346 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 8347 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
8348 | }, |
8349 | { | |
8350 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
8351 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
8352 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
8353 | }, |
8354 | { | |
8355 | /* MOD_0FAE_REG_5 */ | |
035e7389 | 8356 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, |
f8687e93 | 8357 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, |
c0f3af97 L |
8358 | }, |
8359 | { | |
8360 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
8361 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
8362 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
8363 | }, |
8364 | { | |
8365 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
8366 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
8367 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
8368 | }, |
8369 | { | |
8370 | /* MOD_0FB2 */ | |
bf890a93 | 8371 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8372 | }, |
8373 | { | |
8374 | /* MOD_0FB4 */ | |
bf890a93 | 8375 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8376 | }, |
8377 | { | |
8378 | /* MOD_0FB5 */ | |
bf890a93 | 8379 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 8380 | }, |
a8484f96 L |
8381 | { |
8382 | /* MOD_0FC3 */ | |
035e7389 | 8383 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
a8484f96 | 8384 | }, |
963f3586 IT |
8385 | { |
8386 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 8387 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
8388 | }, |
8389 | { | |
8390 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 8391 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
8392 | }, |
8393 | { | |
8394 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 8395 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 8396 | }, |
c0f3af97 L |
8397 | { |
8398 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
8399 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
8400 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
8401 | }, |
8402 | { | |
8403 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 8404 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 8405 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
8406 | }, |
8407 | { | |
8408 | /* MOD_0FD7 */ | |
592d1631 | 8409 | { Bad_Opcode }, |
bf890a93 | 8410 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
8411 | }, |
8412 | { | |
8413 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 8414 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
8415 | }, |
8416 | { | |
8417 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 8418 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
8419 | }, |
8420 | { | |
7531c613 JB |
8421 | /* MOD_0F382A */ |
8422 | { "movntdqa", { XM, Mx }, PREFIX_DATA }, | |
c0f3af97 | 8423 | }, |
c4694f17 TG |
8424 | { |
8425 | /* MOD_0F38DC_PREFIX_1 */ | |
8426 | { "aesenc128kl", { XM, M }, 0 }, | |
8427 | { "loadiwkey", { XM, EXx }, 0 }, | |
8428 | }, | |
8429 | { | |
8430 | /* MOD_0F38DD_PREFIX_1 */ | |
8431 | { "aesdec128kl", { XM, M }, 0 }, | |
8432 | }, | |
8433 | { | |
8434 | /* MOD_0F38DE_PREFIX_1 */ | |
8435 | { "aesenc256kl", { XM, M }, 0 }, | |
8436 | }, | |
8437 | { | |
8438 | /* MOD_0F38DF_PREFIX_1 */ | |
8439 | { "aesdec256kl", { XM, M }, 0 }, | |
8440 | }, | |
603555e5 | 8441 | { |
7531c613 JB |
8442 | /* MOD_0F38F5 */ |
8443 | { "wrussK", { M, Gdq }, PREFIX_DATA }, | |
603555e5 L |
8444 | }, |
8445 | { | |
8446 | /* MOD_0F38F6_PREFIX_0 */ | |
8447 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
8448 | }, | |
5d79adc4 L |
8449 | { |
8450 | /* MOD_0F38F8_PREFIX_1 */ | |
8451 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
8452 | }, | |
c0a30a9f L |
8453 | { |
8454 | /* MOD_0F38F8_PREFIX_2 */ | |
8455 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
8456 | }, | |
5d79adc4 L |
8457 | { |
8458 | /* MOD_0F38F8_PREFIX_3 */ | |
8459 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
8460 | }, | |
c0a30a9f | 8461 | { |
035e7389 JB |
8462 | /* MOD_0F38F9 */ |
8463 | { "movdiri", { Edq, Gdq }, PREFIX_OPCODE }, | |
c0a30a9f | 8464 | }, |
c4694f17 TG |
8465 | { |
8466 | /* MOD_0F38FA_PREFIX_1 */ | |
8467 | { Bad_Opcode }, | |
8468 | { "encodekey128", { Gd, Ed }, 0 }, | |
8469 | }, | |
8470 | { | |
8471 | /* MOD_0F38FB_PREFIX_1 */ | |
8472 | { Bad_Opcode }, | |
8473 | { "encodekey256", { Gd, Ed }, 0 }, | |
8474 | }, | |
c1fa250a LC |
8475 | { |
8476 | /* MOD_0F3A0F_PREFIX_1 */ | |
8477 | { Bad_Opcode }, | |
8478 | { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) }, | |
8479 | }, | |
c0f3af97 L |
8480 | { |
8481 | /* MOD_62_32BIT */ | |
bf890a93 | 8482 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 8483 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
8484 | }, |
8485 | { | |
8486 | /* MOD_C4_32BIT */ | |
bf890a93 | 8487 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8488 | { VEX_C4_TABLE (VEX_0F) }, |
8489 | }, | |
8490 | { | |
8491 | /* MOD_C5_32BIT */ | |
bf890a93 | 8492 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8493 | { VEX_C5_TABLE (VEX_0F) }, |
8494 | }, | |
8495 | { | |
592a252b L |
8496 | /* MOD_VEX_0F12_PREFIX_0 */ |
8497 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
8498 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 8499 | }, |
18897deb JB |
8500 | { |
8501 | /* MOD_VEX_0F12_PREFIX_2 */ | |
8502 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
8503 | }, | |
c0f3af97 | 8504 | { |
592a252b L |
8505 | /* MOD_VEX_0F13 */ |
8506 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
8507 | }, |
8508 | { | |
592a252b L |
8509 | /* MOD_VEX_0F16_PREFIX_0 */ |
8510 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
8511 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 8512 | }, |
18897deb JB |
8513 | { |
8514 | /* MOD_VEX_0F16_PREFIX_2 */ | |
8515 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
8516 | }, | |
c0f3af97 | 8517 | { |
592a252b L |
8518 | /* MOD_VEX_0F17 */ |
8519 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
8520 | }, |
8521 | { | |
592a252b | 8522 | /* MOD_VEX_0F2B */ |
bf926894 | 8523 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 8524 | }, |
ab4e4ed5 AF |
8525 | { |
8526 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
8527 | { Bad_Opcode }, | |
464d2b65 | 8528 | { "kandw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8529 | }, |
8530 | { | |
8531 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
8532 | { Bad_Opcode }, | |
464d2b65 | 8533 | { "kandq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8534 | }, |
8535 | { | |
8536 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
8537 | { Bad_Opcode }, | |
464d2b65 | 8538 | { "kandb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8539 | }, |
8540 | { | |
8541 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
8542 | { Bad_Opcode }, | |
464d2b65 | 8543 | { "kandd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8544 | }, |
8545 | { | |
8546 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
8547 | { Bad_Opcode }, | |
464d2b65 | 8548 | { "kandnw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8549 | }, |
8550 | { | |
8551 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
8552 | { Bad_Opcode }, | |
464d2b65 | 8553 | { "kandnq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8554 | }, |
8555 | { | |
8556 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
8557 | { Bad_Opcode }, | |
464d2b65 | 8558 | { "kandnb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8559 | }, |
8560 | { | |
8561 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
8562 | { Bad_Opcode }, | |
464d2b65 | 8563 | { "kandnd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8564 | }, |
8565 | { | |
8566 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
8567 | { Bad_Opcode }, | |
464d2b65 | 8568 | { "knotw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8569 | }, |
8570 | { | |
8571 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
8572 | { Bad_Opcode }, | |
464d2b65 | 8573 | { "knotq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8574 | }, |
8575 | { | |
8576 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
8577 | { Bad_Opcode }, | |
464d2b65 | 8578 | { "knotb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8579 | }, |
8580 | { | |
8581 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
8582 | { Bad_Opcode }, | |
464d2b65 | 8583 | { "knotd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8584 | }, |
8585 | { | |
8586 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
8587 | { Bad_Opcode }, | |
464d2b65 | 8588 | { "korw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8589 | }, |
8590 | { | |
8591 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
8592 | { Bad_Opcode }, | |
464d2b65 | 8593 | { "korq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8594 | }, |
8595 | { | |
8596 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
8597 | { Bad_Opcode }, | |
464d2b65 | 8598 | { "korb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8599 | }, |
8600 | { | |
8601 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
8602 | { Bad_Opcode }, | |
464d2b65 | 8603 | { "kord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8604 | }, |
8605 | { | |
8606 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
8607 | { Bad_Opcode }, | |
464d2b65 | 8608 | { "kxnorw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8609 | }, |
8610 | { | |
8611 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
8612 | { Bad_Opcode }, | |
464d2b65 | 8613 | { "kxnorq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8614 | }, |
8615 | { | |
8616 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
8617 | { Bad_Opcode }, | |
464d2b65 | 8618 | { "kxnorb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8619 | }, |
8620 | { | |
8621 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
8622 | { Bad_Opcode }, | |
464d2b65 | 8623 | { "kxnord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8624 | }, |
8625 | { | |
8626 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
8627 | { Bad_Opcode }, | |
464d2b65 | 8628 | { "kxorw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8629 | }, |
8630 | { | |
8631 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
8632 | { Bad_Opcode }, | |
464d2b65 | 8633 | { "kxorq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8634 | }, |
8635 | { | |
8636 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
8637 | { Bad_Opcode }, | |
464d2b65 | 8638 | { "kxorb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8639 | }, |
8640 | { | |
8641 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
8642 | { Bad_Opcode }, | |
464d2b65 | 8643 | { "kxord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8644 | }, |
8645 | { | |
8646 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
8647 | { Bad_Opcode }, | |
464d2b65 | 8648 | { "kaddw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8649 | }, |
8650 | { | |
8651 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
8652 | { Bad_Opcode }, | |
464d2b65 | 8653 | { "kaddq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8654 | }, |
8655 | { | |
8656 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
8657 | { Bad_Opcode }, | |
464d2b65 | 8658 | { "kaddb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8659 | }, |
8660 | { | |
8661 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
8662 | { Bad_Opcode }, | |
464d2b65 | 8663 | { "kaddd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8664 | }, |
8665 | { | |
8666 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
8667 | { Bad_Opcode }, | |
464d2b65 | 8668 | { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8669 | }, |
8670 | { | |
8671 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
8672 | { Bad_Opcode }, | |
464d2b65 | 8673 | { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8674 | }, |
8675 | { | |
8676 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
8677 | { Bad_Opcode }, | |
464d2b65 | 8678 | { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 | 8679 | }, |
c0f3af97 | 8680 | { |
592a252b | 8681 | /* MOD_VEX_0F50 */ |
592d1631 | 8682 | { Bad_Opcode }, |
bf926894 | 8683 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
8684 | }, |
8685 | { | |
592a252b | 8686 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 8687 | { Bad_Opcode }, |
7531c613 | 8688 | { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8689 | }, |
8690 | { | |
592a252b | 8691 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 8692 | { Bad_Opcode }, |
7531c613 | 8693 | { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8694 | }, |
8695 | { | |
592a252b | 8696 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 8697 | { Bad_Opcode }, |
7531c613 | 8698 | { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8699 | }, |
8700 | { | |
592a252b | 8701 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 8702 | { Bad_Opcode }, |
7531c613 | 8703 | { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a | 8704 | }, |
d8faab4e | 8705 | { |
592a252b | 8706 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 8707 | { Bad_Opcode }, |
7531c613 | 8708 | { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA }, |
d8faab4e L |
8709 | }, |
8710 | { | |
592a252b | 8711 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 8712 | { Bad_Opcode }, |
7531c613 | 8713 | { "vpslld", { Vex, XS, Ib }, PREFIX_DATA }, |
d8faab4e | 8714 | }, |
876d4bfa | 8715 | { |
592a252b | 8716 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 8717 | { Bad_Opcode }, |
7531c613 | 8718 | { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa L |
8719 | }, |
8720 | { | |
592a252b | 8721 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 8722 | { Bad_Opcode }, |
7531c613 | 8723 | { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA }, |
475a2301 L |
8724 | }, |
8725 | { | |
592a252b | 8726 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 8727 | { Bad_Opcode }, |
7531c613 | 8728 | { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa L |
8729 | }, |
8730 | { | |
592a252b | 8731 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 8732 | { Bad_Opcode }, |
7531c613 | 8733 | { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa | 8734 | }, |
ab4e4ed5 AF |
8735 | { |
8736 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
8737 | { "kmovw", { Ew, MaskG }, 0 }, | |
8738 | { Bad_Opcode }, | |
8739 | }, | |
8740 | { | |
8741 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
8742 | { "kmovq", { Eq, MaskG }, 0 }, | |
8743 | { Bad_Opcode }, | |
8744 | }, | |
8745 | { | |
8746 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
8747 | { "kmovb", { Eb, MaskG }, 0 }, | |
8748 | { Bad_Opcode }, | |
8749 | }, | |
8750 | { | |
8751 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
8752 | { "kmovd", { Ed, MaskG }, 0 }, | |
8753 | { Bad_Opcode }, | |
8754 | }, | |
8755 | { | |
8756 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
8757 | { Bad_Opcode }, | |
464d2b65 | 8758 | { "kmovw", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8759 | }, |
8760 | { | |
8761 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
8762 | { Bad_Opcode }, | |
464d2b65 | 8763 | { "kmovb", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8764 | }, |
8765 | { | |
58a211d2 | 8766 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 8767 | { Bad_Opcode }, |
464d2b65 | 8768 | { "kmovK", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8769 | }, |
8770 | { | |
8771 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
8772 | { Bad_Opcode }, | |
464d2b65 | 8773 | { "kmovw", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8774 | }, |
8775 | { | |
8776 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
8777 | { Bad_Opcode }, | |
464d2b65 | 8778 | { "kmovb", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8779 | }, |
8780 | { | |
58a211d2 | 8781 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 8782 | { Bad_Opcode }, |
464d2b65 | 8783 | { "kmovK", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8784 | }, |
8785 | { | |
8786 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
8787 | { Bad_Opcode }, | |
464d2b65 | 8788 | { "kortestw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8789 | }, |
8790 | { | |
8791 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
8792 | { Bad_Opcode }, | |
464d2b65 | 8793 | { "kortestq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8794 | }, |
8795 | { | |
8796 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
8797 | { Bad_Opcode }, | |
464d2b65 | 8798 | { "kortestb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8799 | }, |
8800 | { | |
8801 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
8802 | { Bad_Opcode }, | |
464d2b65 | 8803 | { "kortestd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8804 | }, |
8805 | { | |
8806 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
8807 | { Bad_Opcode }, | |
464d2b65 | 8808 | { "ktestw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8809 | }, |
8810 | { | |
8811 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
8812 | { Bad_Opcode }, | |
464d2b65 | 8813 | { "ktestq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8814 | }, |
8815 | { | |
8816 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
8817 | { Bad_Opcode }, | |
464d2b65 | 8818 | { "ktestb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8819 | }, |
8820 | { | |
8821 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
8822 | { Bad_Opcode }, | |
464d2b65 | 8823 | { "ktestd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 | 8824 | }, |
876d4bfa | 8825 | { |
592a252b L |
8826 | /* MOD_VEX_0FAE_REG_2 */ |
8827 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 8828 | }, |
bbedc832 | 8829 | { |
592a252b L |
8830 | /* MOD_VEX_0FAE_REG_3 */ |
8831 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 8832 | }, |
144c41d9 | 8833 | { |
7531c613 | 8834 | /* MOD_VEX_0FD7 */ |
592d1631 | 8835 | { Bad_Opcode }, |
7531c613 | 8836 | { "vpmovmskb", { Gdq, XS }, PREFIX_DATA }, |
144c41d9 | 8837 | }, |
1afd85e3 | 8838 | { |
7531c613 JB |
8839 | /* MOD_VEX_0FE7 */ |
8840 | { "vmovntdq", { Mx, XM }, PREFIX_DATA }, | |
1afd85e3 L |
8841 | }, |
8842 | { | |
592a252b | 8843 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 8844 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 8845 | }, |
75c135a8 | 8846 | { |
7531c613 JB |
8847 | /* MOD_VEX_0F381A */ |
8848 | { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) }, | |
75c135a8 | 8849 | }, |
1afd85e3 | 8850 | { |
7531c613 JB |
8851 | /* MOD_VEX_0F382A */ |
8852 | { "vmovntdqa", { XM, Mx }, PREFIX_DATA }, | |
1afd85e3 | 8853 | }, |
75c135a8 | 8854 | { |
7531c613 JB |
8855 | /* MOD_VEX_0F382C */ |
8856 | { VEX_W_TABLE (VEX_W_0F382C_M_0) }, | |
75c135a8 | 8857 | }, |
1afd85e3 | 8858 | { |
7531c613 JB |
8859 | /* MOD_VEX_0F382D */ |
8860 | { VEX_W_TABLE (VEX_W_0F382D_M_0) }, | |
1afd85e3 L |
8861 | }, |
8862 | { | |
7531c613 JB |
8863 | /* MOD_VEX_0F382E */ |
8864 | { VEX_W_TABLE (VEX_W_0F382E_M_0) }, | |
1afd85e3 L |
8865 | }, |
8866 | { | |
7531c613 JB |
8867 | /* MOD_VEX_0F382F */ |
8868 | { VEX_W_TABLE (VEX_W_0F382F_M_0) }, | |
1afd85e3 | 8869 | }, |
09d73035 CL |
8870 | { |
8871 | /* MOD_VEX_0F3849_X86_64_P_0_W_0 */ | |
8872 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) }, | |
8873 | { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) }, | |
8874 | }, | |
8875 | { | |
8876 | /* MOD_VEX_0F3849_X86_64_P_2_W_0 */ | |
8877 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) }, | |
8878 | }, | |
8879 | { | |
8880 | /* MOD_VEX_0F3849_X86_64_P_3_W_0 */ | |
8881 | { Bad_Opcode }, | |
8882 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) }, | |
8883 | }, | |
8884 | { | |
8885 | /* MOD_VEX_0F384B_X86_64_P_1_W_0 */ | |
8886 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) }, | |
8887 | }, | |
8888 | { | |
8889 | /* MOD_VEX_0F384B_X86_64_P_2_W_0 */ | |
8890 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) }, | |
8891 | }, | |
8892 | { | |
8893 | /* MOD_VEX_0F384B_X86_64_P_3_W_0 */ | |
8894 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) }, | |
8895 | }, | |
6c30d220 | 8896 | { |
7531c613 JB |
8897 | /* MOD_VEX_0F385A */ |
8898 | { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) }, | |
6c30d220 | 8899 | }, |
09d73035 CL |
8900 | { |
8901 | /* MOD_VEX_0F385C_X86_64_P_1_W_0 */ | |
8902 | { Bad_Opcode }, | |
8903 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) }, | |
8904 | }, | |
8905 | { | |
8906 | /* MOD_VEX_0F385E_X86_64_P_0_W_0 */ | |
8907 | { Bad_Opcode }, | |
8908 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) }, | |
8909 | }, | |
8910 | { | |
8911 | /* MOD_VEX_0F385E_X86_64_P_1_W_0 */ | |
8912 | { Bad_Opcode }, | |
8913 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) }, | |
8914 | }, | |
8915 | { | |
8916 | /* MOD_VEX_0F385E_X86_64_P_2_W_0 */ | |
8917 | { Bad_Opcode }, | |
8918 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) }, | |
8919 | }, | |
8920 | { | |
8921 | /* MOD_VEX_0F385E_X86_64_P_3_W_0 */ | |
8922 | { Bad_Opcode }, | |
8923 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) }, | |
8924 | }, | |
6c30d220 | 8925 | { |
7531c613 JB |
8926 | /* MOD_VEX_0F388C */ |
8927 | { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA }, | |
6c30d220 L |
8928 | }, |
8929 | { | |
7531c613 JB |
8930 | /* MOD_VEX_0F388E */ |
8931 | { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA }, | |
6c30d220 | 8932 | }, |
ab4e4ed5 | 8933 | { |
bb5b3501 | 8934 | /* MOD_VEX_0F3A30_L_0 */ |
ab4e4ed5 | 8935 | { Bad_Opcode }, |
464d2b65 | 8936 | { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8937 | }, |
8938 | { | |
bb5b3501 | 8939 | /* MOD_VEX_0F3A31_L_0 */ |
ab4e4ed5 | 8940 | { Bad_Opcode }, |
464d2b65 | 8941 | { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8942 | }, |
8943 | { | |
bb5b3501 | 8944 | /* MOD_VEX_0F3A32_L_0 */ |
ab4e4ed5 | 8945 | { Bad_Opcode }, |
464d2b65 | 8946 | { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8947 | }, |
8948 | { | |
bb5b3501 | 8949 | /* MOD_VEX_0F3A33_L_0 */ |
ab4e4ed5 | 8950 | { Bad_Opcode }, |
464d2b65 | 8951 | { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 | 8952 | }, |
467bbef0 JB |
8953 | { |
8954 | /* MOD_VEX_0FXOP_09_12 */ | |
8955 | { Bad_Opcode }, | |
8956 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) }, | |
8957 | }, | |
ad692897 L |
8958 | |
8959 | #include "i386-dis-evex-mod.h" | |
b844680a L |
8960 | }; |
8961 | ||
1ceb70f8 | 8962 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
8963 | { |
8964 | /* RM_C6_REG_7 */ | |
bf890a93 | 8965 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
8966 | }, |
8967 | { | |
8968 | /* RM_C7_REG_7 */ | |
376cd056 | 8969 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 8970 | }, |
b844680a | 8971 | { |
1ceb70f8 | 8972 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 8973 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
8974 | { "vmcall", { Skip_MODRM }, 0 }, |
8975 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
8976 | { "vmresume", { Skip_MODRM }, 0 }, | |
8977 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 8978 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
8979 | }, |
8980 | { | |
1ceb70f8 | 8981 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
8982 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
8983 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
8984 | { "clac", { Skip_MODRM }, 0 }, | |
8985 | { "stac", { Skip_MODRM }, 0 }, | |
81d54bb7 CL |
8986 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, |
8987 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, | |
8988 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) }, | |
8989 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) }, | |
b844680a | 8990 | }, |
475a2301 L |
8991 | { |
8992 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
8993 | { "xgetbv", { Skip_MODRM }, 0 }, |
8994 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
8995 | { Bad_Opcode }, |
8996 | { Bad_Opcode }, | |
bf890a93 IT |
8997 | { "vmfunc", { Skip_MODRM }, 0 }, |
8998 | { "xend", { Skip_MODRM }, 0 }, | |
8999 | { "xtest", { Skip_MODRM }, 0 }, | |
9000 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 9001 | }, |
b844680a | 9002 | { |
1ceb70f8 | 9003 | /* RM_0F01_REG_3 */ |
bf890a93 | 9004 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 9005 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
9006 | { "vmload", { Skip_MODRM }, 0 }, |
9007 | { "vmsave", { Skip_MODRM }, 0 }, | |
9008 | { "stgi", { Skip_MODRM }, 0 }, | |
9009 | { "clgi", { Skip_MODRM }, 0 }, | |
9010 | { "skinit", { Skip_MODRM }, 0 }, | |
9011 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 9012 | }, |
8eab4136 | 9013 | { |
f8687e93 JB |
9014 | /* RM_0F01_REG_5_MOD_3 */ |
9015 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 9016 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 9017 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 | 9018 | { Bad_Opcode }, |
f64c42a9 LC |
9019 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) }, |
9020 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) }, | |
9021 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) }, | |
9022 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) }, | |
8eab4136 | 9023 | }, |
4e7d34a6 | 9024 | { |
f8687e93 | 9025 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
9026 | { "swapgs", { Skip_MODRM }, 0 }, |
9027 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 | 9028 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
035e7389 | 9029 | { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, |
bf890a93 | 9030 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 9031 | { "rdpru", { Skip_MODRM }, 0 }, |
646cc3e0 GG |
9032 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) }, |
9033 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) }, | |
b844680a | 9034 | }, |
603555e5 | 9035 | { |
f8687e93 | 9036 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
9037 | { "nopQ", { Ev }, 0 }, |
9038 | { "nopQ", { Ev }, 0 }, | |
9039 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
9040 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
9041 | { "nopQ", { Ev }, 0 }, | |
9042 | { "nopQ", { Ev }, 0 }, | |
9043 | { "nopQ", { Ev }, 0 }, | |
9044 | { "nopQ", { Ev }, 0 }, | |
9045 | }, | |
c1fa250a LC |
9046 | { |
9047 | /* RM_0F3A0F_P_1_MOD_3_REG_0 */ | |
9048 | { "hreset", { Skip_MODRM, Ib }, 0 }, | |
9049 | }, | |
b844680a | 9050 | { |
f8687e93 | 9051 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 9052 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 9053 | }, |
bbedc832 | 9054 | { |
f8687e93 | 9055 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
9056 | { "sfence", { Skip_MODRM }, 0 }, |
9057 | ||
144c41d9 | 9058 | }, |
260cd341 LC |
9059 | { |
9060 | /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */ | |
9061 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) }, | |
9062 | }, | |
b844680a L |
9063 | }; |
9064 | ||
c608c12e AM |
9065 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
9066 | ||
f16cd0d5 L |
9067 | /* We use the high bit to indicate different name for the same |
9068 | prefix. */ | |
f16cd0d5 | 9069 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
9070 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
9071 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 9072 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 9073 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 9074 | |
1d67fe3b TT |
9075 | /* Remember if the current op is a jump instruction. */ |
9076 | static bfd_boolean op_is_jump = FALSE; | |
9077 | ||
f16cd0d5 | 9078 | static int |
26ca5450 | 9079 | ckprefix (void) |
252b5132 | 9080 | { |
f16cd0d5 | 9081 | int newrex, i, length; |
52b15da3 | 9082 | rex = 0; |
252b5132 | 9083 | prefixes = 0; |
7d421014 | 9084 | used_prefixes = 0; |
52b15da3 | 9085 | rex_used = 0; |
f16cd0d5 L |
9086 | last_lock_prefix = -1; |
9087 | last_repz_prefix = -1; | |
9088 | last_repnz_prefix = -1; | |
9089 | last_data_prefix = -1; | |
9090 | last_addr_prefix = -1; | |
9091 | last_rex_prefix = -1; | |
9092 | last_seg_prefix = -1; | |
d9949a36 | 9093 | fwait_prefix = -1; |
285ca992 | 9094 | active_seg_prefix = 0; |
f310f33d L |
9095 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
9096 | all_prefixes[i] = 0; | |
9097 | i = 0; | |
f16cd0d5 L |
9098 | length = 0; |
9099 | /* The maximum instruction length is 15bytes. */ | |
9100 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
9101 | { |
9102 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 9103 | newrex = 0; |
252b5132 RH |
9104 | switch (*codep) |
9105 | { | |
52b15da3 JH |
9106 | /* REX prefixes family. */ |
9107 | case 0x40: | |
9108 | case 0x41: | |
9109 | case 0x42: | |
9110 | case 0x43: | |
9111 | case 0x44: | |
9112 | case 0x45: | |
9113 | case 0x46: | |
9114 | case 0x47: | |
9115 | case 0x48: | |
9116 | case 0x49: | |
9117 | case 0x4a: | |
9118 | case 0x4b: | |
9119 | case 0x4c: | |
9120 | case 0x4d: | |
9121 | case 0x4e: | |
9122 | case 0x4f: | |
f16cd0d5 L |
9123 | if (address_mode == mode_64bit) |
9124 | newrex = *codep; | |
9125 | else | |
9126 | return 1; | |
9127 | last_rex_prefix = i; | |
52b15da3 | 9128 | break; |
252b5132 RH |
9129 | case 0xf3: |
9130 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 9131 | last_repz_prefix = i; |
252b5132 RH |
9132 | break; |
9133 | case 0xf2: | |
9134 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 9135 | last_repnz_prefix = i; |
252b5132 RH |
9136 | break; |
9137 | case 0xf0: | |
9138 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 9139 | last_lock_prefix = i; |
252b5132 RH |
9140 | break; |
9141 | case 0x2e: | |
9142 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 9143 | last_seg_prefix = i; |
285ca992 | 9144 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
9145 | break; |
9146 | case 0x36: | |
9147 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 9148 | last_seg_prefix = i; |
285ca992 | 9149 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
9150 | break; |
9151 | case 0x3e: | |
9152 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 9153 | last_seg_prefix = i; |
285ca992 | 9154 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
9155 | break; |
9156 | case 0x26: | |
9157 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 9158 | last_seg_prefix = i; |
285ca992 | 9159 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
9160 | break; |
9161 | case 0x64: | |
9162 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 9163 | last_seg_prefix = i; |
285ca992 | 9164 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
9165 | break; |
9166 | case 0x65: | |
9167 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 9168 | last_seg_prefix = i; |
285ca992 | 9169 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
9170 | break; |
9171 | case 0x66: | |
9172 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 9173 | last_data_prefix = i; |
252b5132 RH |
9174 | break; |
9175 | case 0x67: | |
9176 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 9177 | last_addr_prefix = i; |
252b5132 | 9178 | break; |
5076851f | 9179 | case FWAIT_OPCODE: |
252b5132 RH |
9180 | /* fwait is really an instruction. If there are prefixes |
9181 | before the fwait, they belong to the fwait, *not* to the | |
9182 | following instruction. */ | |
d9949a36 | 9183 | fwait_prefix = i; |
3e7d61b2 | 9184 | if (prefixes || rex) |
252b5132 RH |
9185 | { |
9186 | prefixes |= PREFIX_FWAIT; | |
9187 | codep++; | |
6c067bbb RM |
9188 | /* This ensures that the previous REX prefixes are noticed |
9189 | as unused prefixes, as in the return case below. */ | |
9190 | rex_used = rex; | |
f16cd0d5 | 9191 | return 1; |
252b5132 RH |
9192 | } |
9193 | prefixes = PREFIX_FWAIT; | |
9194 | break; | |
9195 | default: | |
f16cd0d5 | 9196 | return 1; |
252b5132 | 9197 | } |
52b15da3 JH |
9198 | /* Rex is ignored when followed by another prefix. */ |
9199 | if (rex) | |
9200 | { | |
3e7d61b2 | 9201 | rex_used = rex; |
f16cd0d5 | 9202 | return 1; |
52b15da3 | 9203 | } |
f16cd0d5 | 9204 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 9205 | all_prefixes[i++] = *codep; |
52b15da3 | 9206 | rex = newrex; |
252b5132 | 9207 | codep++; |
f16cd0d5 L |
9208 | length++; |
9209 | } | |
9210 | return 0; | |
9211 | } | |
9212 | ||
7d421014 ILT |
9213 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
9214 | prefix byte. */ | |
9215 | ||
9216 | static const char * | |
26ca5450 | 9217 | prefix_name (int pref, int sizeflag) |
7d421014 | 9218 | { |
0003779b L |
9219 | static const char *rexes [16] = |
9220 | { | |
9221 | "rex", /* 0x40 */ | |
9222 | "rex.B", /* 0x41 */ | |
9223 | "rex.X", /* 0x42 */ | |
9224 | "rex.XB", /* 0x43 */ | |
9225 | "rex.R", /* 0x44 */ | |
9226 | "rex.RB", /* 0x45 */ | |
9227 | "rex.RX", /* 0x46 */ | |
9228 | "rex.RXB", /* 0x47 */ | |
9229 | "rex.W", /* 0x48 */ | |
9230 | "rex.WB", /* 0x49 */ | |
9231 | "rex.WX", /* 0x4a */ | |
9232 | "rex.WXB", /* 0x4b */ | |
9233 | "rex.WR", /* 0x4c */ | |
9234 | "rex.WRB", /* 0x4d */ | |
9235 | "rex.WRX", /* 0x4e */ | |
9236 | "rex.WRXB", /* 0x4f */ | |
9237 | }; | |
9238 | ||
7d421014 ILT |
9239 | switch (pref) |
9240 | { | |
52b15da3 JH |
9241 | /* REX prefixes family. */ |
9242 | case 0x40: | |
52b15da3 | 9243 | case 0x41: |
52b15da3 | 9244 | case 0x42: |
52b15da3 | 9245 | case 0x43: |
52b15da3 | 9246 | case 0x44: |
52b15da3 | 9247 | case 0x45: |
52b15da3 | 9248 | case 0x46: |
52b15da3 | 9249 | case 0x47: |
52b15da3 | 9250 | case 0x48: |
52b15da3 | 9251 | case 0x49: |
52b15da3 | 9252 | case 0x4a: |
52b15da3 | 9253 | case 0x4b: |
52b15da3 | 9254 | case 0x4c: |
52b15da3 | 9255 | case 0x4d: |
52b15da3 | 9256 | case 0x4e: |
52b15da3 | 9257 | case 0x4f: |
0003779b | 9258 | return rexes [pref - 0x40]; |
7d421014 ILT |
9259 | case 0xf3: |
9260 | return "repz"; | |
9261 | case 0xf2: | |
9262 | return "repnz"; | |
9263 | case 0xf0: | |
9264 | return "lock"; | |
9265 | case 0x2e: | |
9266 | return "cs"; | |
9267 | case 0x36: | |
9268 | return "ss"; | |
9269 | case 0x3e: | |
9270 | return "ds"; | |
9271 | case 0x26: | |
9272 | return "es"; | |
9273 | case 0x64: | |
9274 | return "fs"; | |
9275 | case 0x65: | |
9276 | return "gs"; | |
9277 | case 0x66: | |
9278 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
9279 | case 0x67: | |
cb712a9e | 9280 | if (address_mode == mode_64bit) |
db6eb5be | 9281 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 9282 | else |
2888cb7a | 9283 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
9284 | case FWAIT_OPCODE: |
9285 | return "fwait"; | |
f16cd0d5 L |
9286 | case REP_PREFIX: |
9287 | return "rep"; | |
42164a71 L |
9288 | case XACQUIRE_PREFIX: |
9289 | return "xacquire"; | |
9290 | case XRELEASE_PREFIX: | |
9291 | return "xrelease"; | |
7e8b059b L |
9292 | case BND_PREFIX: |
9293 | return "bnd"; | |
04ef582a L |
9294 | case NOTRACK_PREFIX: |
9295 | return "notrack"; | |
7d421014 ILT |
9296 | default: |
9297 | return NULL; | |
9298 | } | |
9299 | } | |
9300 | ||
ce518a5f L |
9301 | static char op_out[MAX_OPERANDS][100]; |
9302 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 9303 | static int two_source_ops; |
ce518a5f L |
9304 | static bfd_vma op_address[MAX_OPERANDS]; |
9305 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 9306 | static bfd_vma start_pc; |
ce518a5f | 9307 | |
252b5132 RH |
9308 | /* |
9309 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
9310 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
9311 | * section of the "Virtual 8086 Mode" chapter.) | |
9312 | * 'pc' should be the address of this instruction, it will | |
9313 | * be used to print the target address if this is a relative jump or call | |
9314 | * The function returns the length of this instruction in bytes. | |
9315 | */ | |
9316 | ||
252b5132 | 9317 | static char intel_syntax; |
9d141669 | 9318 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
9319 | static char open_char; |
9320 | static char close_char; | |
9321 | static char separator_char; | |
9322 | static char scale_char; | |
9323 | ||
5db04b09 L |
9324 | enum x86_64_isa |
9325 | { | |
d835a58b | 9326 | amd64 = 1, |
5db04b09 L |
9327 | intel64 |
9328 | }; | |
9329 | ||
9330 | static enum x86_64_isa isa64; | |
9331 | ||
e396998b AM |
9332 | /* Here for backwards compatibility. When gdb stops using |
9333 | print_insn_i386_att and print_insn_i386_intel these functions can | |
9334 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 9335 | int |
26ca5450 | 9336 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9337 | { |
9338 | intel_syntax = 0; | |
e396998b AM |
9339 | |
9340 | return print_insn (pc, info); | |
252b5132 RH |
9341 | } |
9342 | ||
9343 | int | |
26ca5450 | 9344 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9345 | { |
9346 | intel_syntax = 1; | |
e396998b AM |
9347 | |
9348 | return print_insn (pc, info); | |
252b5132 RH |
9349 | } |
9350 | ||
e396998b | 9351 | int |
26ca5450 | 9352 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
9353 | { |
9354 | intel_syntax = -1; | |
9355 | ||
9356 | return print_insn (pc, info); | |
9357 | } | |
9358 | ||
f59a29b9 L |
9359 | void |
9360 | print_i386_disassembler_options (FILE *stream) | |
9361 | { | |
9362 | fprintf (stream, _("\n\ | |
9363 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
9364 | with the -M switch (multiple options should be separated by commas):\n")); | |
9365 | ||
9366 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
9367 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
9368 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
9369 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
9370 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
9371 | fprintf (stream, _(" att-mnemonic\n" |
9372 | " Display instruction in AT&T mnemonic\n")); | |
9373 | fprintf (stream, _(" intel-mnemonic\n" | |
9374 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
9375 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
9376 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
9377 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
9378 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
9379 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
9380 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
9381 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
9382 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
9383 | } |
9384 | ||
592d1631 | 9385 | /* Bad opcode. */ |
bf890a93 | 9386 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 9387 | |
b844680a L |
9388 | /* Get a pointer to struct dis386 with a valid name. */ |
9389 | ||
9390 | static const struct dis386 * | |
8bb15339 | 9391 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 9392 | { |
91d6fa6a | 9393 | int vindex, vex_table_index; |
b844680a L |
9394 | |
9395 | if (dp->name != NULL) | |
9396 | return dp; | |
9397 | ||
9398 | switch (dp->op[0].bytemode) | |
9399 | { | |
1ceb70f8 L |
9400 | case USE_REG_TABLE: |
9401 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
9402 | break; | |
9403 | ||
9404 | case USE_MOD_TABLE: | |
91d6fa6a NC |
9405 | vindex = modrm.mod == 0x3 ? 1 : 0; |
9406 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
9407 | break; |
9408 | ||
9409 | case USE_RM_TABLE: | |
9410 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
9411 | break; |
9412 | ||
4e7d34a6 | 9413 | case USE_PREFIX_TABLE: |
c0f3af97 | 9414 | if (need_vex) |
b844680a | 9415 | { |
c0f3af97 L |
9416 | /* The prefix in VEX is implicit. */ |
9417 | switch (vex.prefix) | |
9418 | { | |
9419 | case 0: | |
91d6fa6a | 9420 | vindex = 0; |
c0f3af97 L |
9421 | break; |
9422 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 9423 | vindex = 1; |
c0f3af97 L |
9424 | break; |
9425 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 9426 | vindex = 2; |
c0f3af97 L |
9427 | break; |
9428 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 9429 | vindex = 3; |
c0f3af97 L |
9430 | break; |
9431 | default: | |
9432 | abort (); | |
9433 | break; | |
9434 | } | |
b844680a | 9435 | } |
7bb15c6f | 9436 | else |
b844680a | 9437 | { |
285ca992 L |
9438 | int last_prefix = -1; |
9439 | int prefix = 0; | |
91d6fa6a | 9440 | vindex = 0; |
285ca992 L |
9441 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
9442 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
9443 | last one wins. */ | |
9444 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 9445 | { |
285ca992 | 9446 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 9447 | { |
285ca992 L |
9448 | vindex = 1; |
9449 | prefix = PREFIX_REPZ; | |
9450 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
9451 | } |
9452 | else | |
b844680a | 9453 | { |
285ca992 L |
9454 | vindex = 3; |
9455 | prefix = PREFIX_REPNZ; | |
9456 | last_prefix = last_repnz_prefix; | |
b844680a | 9457 | } |
285ca992 | 9458 | |
507bd325 L |
9459 | /* Check if prefix should be ignored. */ |
9460 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
9461 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
9462 | & prefix) != 0) | |
285ca992 L |
9463 | vindex = 0; |
9464 | } | |
9465 | ||
9466 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
9467 | { | |
9468 | vindex = 2; | |
9469 | prefix = PREFIX_DATA; | |
9470 | last_prefix = last_data_prefix; | |
9471 | } | |
9472 | ||
9473 | if (vindex != 0) | |
9474 | { | |
9475 | used_prefixes |= prefix; | |
9476 | all_prefixes[last_prefix] = 0; | |
b844680a L |
9477 | } |
9478 | } | |
91d6fa6a | 9479 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
9480 | break; |
9481 | ||
4e7d34a6 | 9482 | case USE_X86_64_TABLE: |
91d6fa6a NC |
9483 | vindex = address_mode == mode_64bit ? 1 : 0; |
9484 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
9485 | break; |
9486 | ||
4e7d34a6 | 9487 | case USE_3BYTE_TABLE: |
8bb15339 | 9488 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
9489 | vindex = *codep++; |
9490 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 9491 | end_codep = codep; |
8bb15339 L |
9492 | modrm.mod = (*codep >> 6) & 3; |
9493 | modrm.reg = (*codep >> 3) & 7; | |
9494 | modrm.rm = *codep & 7; | |
9495 | break; | |
9496 | ||
c0f3af97 L |
9497 | case USE_VEX_LEN_TABLE: |
9498 | if (!need_vex) | |
9499 | abort (); | |
9500 | ||
9501 | switch (vex.length) | |
9502 | { | |
9503 | case 128: | |
91d6fa6a | 9504 | vindex = 0; |
c0f3af97 L |
9505 | break; |
9506 | case 256: | |
91d6fa6a | 9507 | vindex = 1; |
c0f3af97 L |
9508 | break; |
9509 | default: | |
9510 | abort (); | |
9511 | break; | |
9512 | } | |
9513 | ||
91d6fa6a | 9514 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
9515 | break; |
9516 | ||
04e2a182 L |
9517 | case USE_EVEX_LEN_TABLE: |
9518 | if (!vex.evex) | |
9519 | abort (); | |
9520 | ||
9521 | switch (vex.length) | |
9522 | { | |
9523 | case 128: | |
9524 | vindex = 0; | |
9525 | break; | |
9526 | case 256: | |
9527 | vindex = 1; | |
9528 | break; | |
9529 | case 512: | |
9530 | vindex = 2; | |
9531 | break; | |
9532 | default: | |
9533 | abort (); | |
9534 | break; | |
9535 | } | |
9536 | ||
9537 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
9538 | break; | |
9539 | ||
f88c9eb0 SP |
9540 | case USE_XOP_8F_TABLE: |
9541 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
9542 | rex = ~(*codep >> 5) & 0x7; |
9543 | ||
9544 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
9545 | switch ((*codep & 0x1f)) | |
9546 | { | |
9547 | default: | |
f07af43e L |
9548 | dp = &bad_opcode; |
9549 | return dp; | |
5dd85c99 SP |
9550 | case 0x8: |
9551 | vex_table_index = XOP_08; | |
9552 | break; | |
f88c9eb0 SP |
9553 | case 0x9: |
9554 | vex_table_index = XOP_09; | |
9555 | break; | |
9556 | case 0xa: | |
9557 | vex_table_index = XOP_0A; | |
9558 | break; | |
9559 | } | |
9560 | codep++; | |
9561 | vex.w = *codep & 0x80; | |
9562 | if (vex.w && address_mode == mode_64bit) | |
9563 | rex |= REX_W; | |
9564 | ||
9565 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 9566 | if (address_mode != mode_64bit) |
f07af43e | 9567 | { |
abfcb414 AP |
9568 | /* In 16/32-bit mode REX_B is silently ignored. */ |
9569 | rex &= ~REX_B; | |
f07af43e | 9570 | } |
f88c9eb0 SP |
9571 | |
9572 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9573 | switch ((*codep & 0x3)) | |
9574 | { | |
9575 | case 0: | |
f88c9eb0 SP |
9576 | break; |
9577 | case 1: | |
9578 | vex.prefix = DATA_PREFIX_OPCODE; | |
9579 | break; | |
9580 | case 2: | |
9581 | vex.prefix = REPE_PREFIX_OPCODE; | |
9582 | break; | |
9583 | case 3: | |
9584 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9585 | break; | |
9586 | } | |
9587 | need_vex = 1; | |
f88c9eb0 | 9588 | codep++; |
91d6fa6a NC |
9589 | vindex = *codep++; |
9590 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 9591 | |
285ca992 | 9592 | end_codep = codep; |
c48244a5 SP |
9593 | FETCH_DATA (info, codep + 1); |
9594 | modrm.mod = (*codep >> 6) & 3; | |
9595 | modrm.reg = (*codep >> 3) & 7; | |
9596 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
9597 | |
9598 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
9599 | having to decode the bits for every otherwise valid encoding. */ | |
9600 | if (vex.prefix) | |
9601 | return &bad_opcode; | |
f88c9eb0 SP |
9602 | break; |
9603 | ||
c0f3af97 | 9604 | case USE_VEX_C4_TABLE: |
43234a1e | 9605 | /* VEX prefix. */ |
c0f3af97 | 9606 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
9607 | rex = ~(*codep >> 5) & 0x7; |
9608 | switch ((*codep & 0x1f)) | |
9609 | { | |
9610 | default: | |
f07af43e L |
9611 | dp = &bad_opcode; |
9612 | return dp; | |
c0f3af97 | 9613 | case 0x1: |
f88c9eb0 | 9614 | vex_table_index = VEX_0F; |
c0f3af97 L |
9615 | break; |
9616 | case 0x2: | |
f88c9eb0 | 9617 | vex_table_index = VEX_0F38; |
c0f3af97 L |
9618 | break; |
9619 | case 0x3: | |
f88c9eb0 | 9620 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
9621 | break; |
9622 | } | |
9623 | codep++; | |
9624 | vex.w = *codep & 0x80; | |
9889cbb1 | 9625 | if (address_mode == mode_64bit) |
f07af43e | 9626 | { |
9889cbb1 L |
9627 | if (vex.w) |
9628 | rex |= REX_W; | |
9889cbb1 L |
9629 | } |
9630 | else | |
9631 | { | |
9632 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
9633 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 9634 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 9635 | rex = 0; |
f07af43e | 9636 | } |
5f847646 | 9637 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
9638 | vex.length = (*codep & 0x4) ? 256 : 128; |
9639 | switch ((*codep & 0x3)) | |
9640 | { | |
9641 | case 0: | |
c0f3af97 L |
9642 | break; |
9643 | case 1: | |
9644 | vex.prefix = DATA_PREFIX_OPCODE; | |
9645 | break; | |
9646 | case 2: | |
9647 | vex.prefix = REPE_PREFIX_OPCODE; | |
9648 | break; | |
9649 | case 3: | |
9650 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9651 | break; | |
9652 | } | |
9653 | need_vex = 1; | |
c0f3af97 | 9654 | codep++; |
91d6fa6a NC |
9655 | vindex = *codep++; |
9656 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 9657 | end_codep = codep; |
53c4d625 JB |
9658 | /* There is no MODRM byte for VEX0F 77. */ |
9659 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
9660 | { |
9661 | FETCH_DATA (info, codep + 1); | |
9662 | modrm.mod = (*codep >> 6) & 3; | |
9663 | modrm.reg = (*codep >> 3) & 7; | |
9664 | modrm.rm = *codep & 7; | |
9665 | } | |
9666 | break; | |
9667 | ||
9668 | case USE_VEX_C5_TABLE: | |
43234a1e | 9669 | /* VEX prefix. */ |
c0f3af97 | 9670 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
9671 | rex = (*codep & 0x80) ? 0 : REX_R; |
9672 | ||
9889cbb1 L |
9673 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
9674 | VEX.vvvv is 1. */ | |
c0f3af97 | 9675 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
9676 | vex.length = (*codep & 0x4) ? 256 : 128; |
9677 | switch ((*codep & 0x3)) | |
9678 | { | |
9679 | case 0: | |
c0f3af97 L |
9680 | break; |
9681 | case 1: | |
9682 | vex.prefix = DATA_PREFIX_OPCODE; | |
9683 | break; | |
9684 | case 2: | |
9685 | vex.prefix = REPE_PREFIX_OPCODE; | |
9686 | break; | |
9687 | case 3: | |
9688 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9689 | break; | |
9690 | } | |
9691 | need_vex = 1; | |
c0f3af97 | 9692 | codep++; |
91d6fa6a NC |
9693 | vindex = *codep++; |
9694 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 9695 | end_codep = codep; |
53c4d625 JB |
9696 | /* There is no MODRM byte for VEX 77. */ |
9697 | if (vindex != 0x77) | |
c0f3af97 L |
9698 | { |
9699 | FETCH_DATA (info, codep + 1); | |
9700 | modrm.mod = (*codep >> 6) & 3; | |
9701 | modrm.reg = (*codep >> 3) & 7; | |
9702 | modrm.rm = *codep & 7; | |
9703 | } | |
9704 | break; | |
9705 | ||
9e30b8e0 L |
9706 | case USE_VEX_W_TABLE: |
9707 | if (!need_vex) | |
9708 | abort (); | |
9709 | ||
9710 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
9711 | break; | |
9712 | ||
43234a1e L |
9713 | case USE_EVEX_TABLE: |
9714 | two_source_ops = 0; | |
9715 | /* EVEX prefix. */ | |
9716 | vex.evex = 1; | |
9717 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
9718 | /* The first byte after 0x62. */ |
9719 | rex = ~(*codep >> 5) & 0x7; | |
9720 | vex.r = *codep & 0x10; | |
9721 | switch ((*codep & 0xf)) | |
9722 | { | |
9723 | default: | |
9724 | return &bad_opcode; | |
9725 | case 0x1: | |
9726 | vex_table_index = EVEX_0F; | |
9727 | break; | |
9728 | case 0x2: | |
9729 | vex_table_index = EVEX_0F38; | |
9730 | break; | |
9731 | case 0x3: | |
9732 | vex_table_index = EVEX_0F3A; | |
9733 | break; | |
9734 | } | |
9735 | ||
9736 | /* The second byte after 0x62. */ | |
9737 | codep++; | |
9738 | vex.w = *codep & 0x80; | |
9739 | if (vex.w && address_mode == mode_64bit) | |
9740 | rex |= REX_W; | |
9741 | ||
9742 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
9743 | |
9744 | /* The U bit. */ | |
9745 | if (!(*codep & 0x4)) | |
9746 | return &bad_opcode; | |
9747 | ||
9748 | switch ((*codep & 0x3)) | |
9749 | { | |
9750 | case 0: | |
43234a1e L |
9751 | break; |
9752 | case 1: | |
9753 | vex.prefix = DATA_PREFIX_OPCODE; | |
9754 | break; | |
9755 | case 2: | |
9756 | vex.prefix = REPE_PREFIX_OPCODE; | |
9757 | break; | |
9758 | case 3: | |
9759 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9760 | break; | |
9761 | } | |
9762 | ||
9763 | /* The third byte after 0x62. */ | |
9764 | codep++; | |
9765 | ||
9766 | /* Remember the static rounding bits. */ | |
9767 | vex.ll = (*codep >> 5) & 3; | |
9768 | vex.b = (*codep & 0x10) != 0; | |
9769 | ||
9770 | vex.v = *codep & 0x8; | |
9771 | vex.mask_register_specifier = *codep & 0x7; | |
9772 | vex.zeroing = *codep & 0x80; | |
9773 | ||
5f847646 JB |
9774 | if (address_mode != mode_64bit) |
9775 | { | |
9776 | /* In 16/32-bit mode silently ignore following bits. */ | |
9777 | rex &= ~REX_B; | |
9778 | vex.r = 1; | |
9779 | vex.v = 1; | |
9780 | } | |
9781 | ||
43234a1e | 9782 | need_vex = 1; |
43234a1e L |
9783 | codep++; |
9784 | vindex = *codep++; | |
9785 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 9786 | end_codep = codep; |
43234a1e L |
9787 | FETCH_DATA (info, codep + 1); |
9788 | modrm.mod = (*codep >> 6) & 3; | |
9789 | modrm.reg = (*codep >> 3) & 7; | |
9790 | modrm.rm = *codep & 7; | |
9791 | ||
9792 | /* Set vector length. */ | |
9793 | if (modrm.mod == 3 && vex.b) | |
9794 | vex.length = 512; | |
9795 | else | |
9796 | { | |
9797 | switch (vex.ll) | |
9798 | { | |
9799 | case 0x0: | |
9800 | vex.length = 128; | |
9801 | break; | |
9802 | case 0x1: | |
9803 | vex.length = 256; | |
9804 | break; | |
9805 | case 0x2: | |
9806 | vex.length = 512; | |
9807 | break; | |
9808 | default: | |
9809 | return &bad_opcode; | |
9810 | } | |
9811 | } | |
9812 | break; | |
9813 | ||
592d1631 L |
9814 | case 0: |
9815 | dp = &bad_opcode; | |
9816 | break; | |
9817 | ||
b844680a | 9818 | default: |
d34b5006 | 9819 | abort (); |
b844680a L |
9820 | } |
9821 | ||
9822 | if (dp->name != NULL) | |
9823 | return dp; | |
9824 | else | |
8bb15339 | 9825 | return get_valid_dis386 (dp, info); |
b844680a L |
9826 | } |
9827 | ||
dfc8cf43 | 9828 | static void |
55cf16e1 | 9829 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
9830 | { |
9831 | /* If modrm.mod == 3, operand must be register. */ | |
9832 | if (need_modrm | |
55cf16e1 | 9833 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
9834 | && modrm.mod != 3 |
9835 | && modrm.rm == 4) | |
9836 | { | |
9837 | FETCH_DATA (info, codep + 2); | |
9838 | sib.index = (codep [1] >> 3) & 7; | |
9839 | sib.scale = (codep [1] >> 6) & 3; | |
9840 | sib.base = codep [1] & 7; | |
9841 | } | |
9842 | } | |
9843 | ||
e396998b | 9844 | static int |
26ca5450 | 9845 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 9846 | { |
2da11e11 | 9847 | const struct dis386 *dp; |
252b5132 | 9848 | int i; |
ce518a5f | 9849 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 9850 | int needcomma; |
df18fdba | 9851 | int sizeflag, orig_sizeflag; |
e396998b | 9852 | const char *p; |
252b5132 | 9853 | struct dis_private priv; |
f16cd0d5 | 9854 | int prefix_length; |
252b5132 | 9855 | |
d7921315 L |
9856 | priv.orig_sizeflag = AFLAG | DFLAG; |
9857 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 9858 | address_mode = mode_32bit; |
2da11e11 | 9859 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
9860 | { |
9861 | address_mode = mode_16bit; | |
9862 | priv.orig_sizeflag = 0; | |
9863 | } | |
2da11e11 | 9864 | else |
d7921315 L |
9865 | address_mode = mode_64bit; |
9866 | ||
9867 | if (intel_syntax == (char) -1) | |
9868 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
9869 | |
9870 | for (p = info->disassembler_options; p != NULL; ) | |
9871 | { | |
5db04b09 L |
9872 | if (CONST_STRNEQ (p, "amd64")) |
9873 | isa64 = amd64; | |
9874 | else if (CONST_STRNEQ (p, "intel64")) | |
9875 | isa64 = intel64; | |
9876 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 9877 | { |
cb712a9e | 9878 | address_mode = mode_64bit; |
2a1bb84c | 9879 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9880 | } |
0112cd26 | 9881 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 9882 | { |
cb712a9e | 9883 | address_mode = mode_32bit; |
2a1bb84c | 9884 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9885 | } |
0112cd26 | 9886 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 9887 | { |
cb712a9e | 9888 | address_mode = mode_16bit; |
2a1bb84c | 9889 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 9890 | } |
0112cd26 | 9891 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
9892 | { |
9893 | intel_syntax = 1; | |
9d141669 L |
9894 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
9895 | intel_mnemonic = 1; | |
e396998b | 9896 | } |
0112cd26 | 9897 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
9898 | { |
9899 | intel_syntax = 0; | |
9d141669 L |
9900 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
9901 | intel_mnemonic = 0; | |
e396998b | 9902 | } |
0112cd26 | 9903 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 9904 | { |
f59a29b9 L |
9905 | if (address_mode == mode_64bit) |
9906 | { | |
9907 | if (p[4] == '3' && p[5] == '2') | |
9908 | priv.orig_sizeflag &= ~AFLAG; | |
9909 | else if (p[4] == '6' && p[5] == '4') | |
9910 | priv.orig_sizeflag |= AFLAG; | |
9911 | } | |
9912 | else | |
9913 | { | |
9914 | if (p[4] == '1' && p[5] == '6') | |
9915 | priv.orig_sizeflag &= ~AFLAG; | |
9916 | else if (p[4] == '3' && p[5] == '2') | |
9917 | priv.orig_sizeflag |= AFLAG; | |
9918 | } | |
e396998b | 9919 | } |
0112cd26 | 9920 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
9921 | { |
9922 | if (p[4] == '1' && p[5] == '6') | |
9923 | priv.orig_sizeflag &= ~DFLAG; | |
9924 | else if (p[4] == '3' && p[5] == '2') | |
9925 | priv.orig_sizeflag |= DFLAG; | |
9926 | } | |
0112cd26 | 9927 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
9928 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
9929 | ||
9930 | p = strchr (p, ','); | |
9931 | if (p != NULL) | |
9932 | p++; | |
9933 | } | |
9934 | ||
c0f92bf9 L |
9935 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
9936 | { | |
9937 | (*info->fprintf_func) (info->stream, | |
9938 | _("64-bit address is disabled")); | |
9939 | return -1; | |
9940 | } | |
9941 | ||
e396998b AM |
9942 | if (intel_syntax) |
9943 | { | |
9944 | names64 = intel_names64; | |
9945 | names32 = intel_names32; | |
9946 | names16 = intel_names16; | |
9947 | names8 = intel_names8; | |
9948 | names8rex = intel_names8rex; | |
9949 | names_seg = intel_names_seg; | |
b9733481 | 9950 | names_mm = intel_names_mm; |
7e8b059b | 9951 | names_bnd = intel_names_bnd; |
b9733481 L |
9952 | names_xmm = intel_names_xmm; |
9953 | names_ymm = intel_names_ymm; | |
43234a1e | 9954 | names_zmm = intel_names_zmm; |
260cd341 | 9955 | names_tmm = intel_names_tmm; |
db51cc60 L |
9956 | index64 = intel_index64; |
9957 | index32 = intel_index32; | |
43234a1e | 9958 | names_mask = intel_names_mask; |
e396998b AM |
9959 | index16 = intel_index16; |
9960 | open_char = '['; | |
9961 | close_char = ']'; | |
9962 | separator_char = '+'; | |
9963 | scale_char = '*'; | |
9964 | } | |
9965 | else | |
9966 | { | |
9967 | names64 = att_names64; | |
9968 | names32 = att_names32; | |
9969 | names16 = att_names16; | |
9970 | names8 = att_names8; | |
9971 | names8rex = att_names8rex; | |
9972 | names_seg = att_names_seg; | |
b9733481 | 9973 | names_mm = att_names_mm; |
7e8b059b | 9974 | names_bnd = att_names_bnd; |
b9733481 L |
9975 | names_xmm = att_names_xmm; |
9976 | names_ymm = att_names_ymm; | |
43234a1e | 9977 | names_zmm = att_names_zmm; |
260cd341 | 9978 | names_tmm = att_names_tmm; |
db51cc60 L |
9979 | index64 = att_index64; |
9980 | index32 = att_index32; | |
43234a1e | 9981 | names_mask = att_names_mask; |
e396998b AM |
9982 | index16 = att_index16; |
9983 | open_char = '('; | |
9984 | close_char = ')'; | |
9985 | separator_char = ','; | |
9986 | scale_char = ','; | |
9987 | } | |
2da11e11 | 9988 | |
4fe53c98 | 9989 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
9990 | puts most long word instructions on a single line. Use 8 bytes |
9991 | for Intel L1OM. */ | |
d7921315 | 9992 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
9993 | info->bytes_per_line = 8; |
9994 | else | |
9995 | info->bytes_per_line = 7; | |
252b5132 | 9996 | |
26ca5450 | 9997 | info->private_data = &priv; |
252b5132 RH |
9998 | priv.max_fetched = priv.the_buffer; |
9999 | priv.insn_start = pc; | |
252b5132 RH |
10000 | |
10001 | obuf[0] = 0; | |
ce518a5f L |
10002 | for (i = 0; i < MAX_OPERANDS; ++i) |
10003 | { | |
10004 | op_out[i][0] = 0; | |
10005 | op_index[i] = -1; | |
10006 | } | |
252b5132 RH |
10007 | |
10008 | the_info = info; | |
10009 | start_pc = pc; | |
e396998b AM |
10010 | start_codep = priv.the_buffer; |
10011 | codep = priv.the_buffer; | |
252b5132 | 10012 | |
8df14d78 | 10013 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 10014 | { |
7d421014 ILT |
10015 | const char *name; |
10016 | ||
5076851f | 10017 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
10018 | means we have an incomplete instruction of some sort. Just |
10019 | print the first byte as a prefix or a .byte pseudo-op. */ | |
10020 | if (codep > priv.the_buffer) | |
5076851f | 10021 | { |
e396998b | 10022 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
10023 | if (name != NULL) |
10024 | (*info->fprintf_func) (info->stream, "%s", name); | |
10025 | else | |
5076851f | 10026 | { |
7d421014 ILT |
10027 | /* Just print the first byte as a .byte instruction. */ |
10028 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 10029 | (unsigned int) priv.the_buffer[0]); |
5076851f | 10030 | } |
5076851f | 10031 | |
7d421014 | 10032 | return 1; |
5076851f ILT |
10033 | } |
10034 | ||
10035 | return -1; | |
10036 | } | |
10037 | ||
52b15da3 | 10038 | obufp = obuf; |
f16cd0d5 L |
10039 | sizeflag = priv.orig_sizeflag; |
10040 | ||
10041 | if (!ckprefix () || rex_used) | |
10042 | { | |
10043 | /* Too many prefixes or unused REX prefixes. */ | |
10044 | for (i = 0; | |
f6dd4781 | 10045 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 10046 | i++) |
de882298 | 10047 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 10048 | i == 0 ? "" : " ", |
f16cd0d5 | 10049 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 10050 | return i; |
f16cd0d5 | 10051 | } |
252b5132 RH |
10052 | |
10053 | insn_codep = codep; | |
10054 | ||
10055 | FETCH_DATA (info, codep + 1); | |
10056 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
10057 | ||
3e7d61b2 | 10058 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 10059 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 10060 | { |
86a80a50 | 10061 | /* Handle prefixes before fwait. */ |
d9949a36 | 10062 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
10063 | i++) |
10064 | (*info->fprintf_func) (info->stream, "%s ", | |
10065 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 10066 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 10067 | return i + 1; |
252b5132 RH |
10068 | } |
10069 | ||
252b5132 RH |
10070 | if (*codep == 0x0f) |
10071 | { | |
eec0f4ca | 10072 | unsigned char threebyte; |
5f40e14d JS |
10073 | |
10074 | codep++; | |
10075 | FETCH_DATA (info, codep + 1); | |
10076 | threebyte = *codep; | |
eec0f4ca | 10077 | dp = &dis386_twobyte[threebyte]; |
0e9f3bf1 | 10078 | need_modrm = twobyte_has_modrm[threebyte]; |
eec0f4ca | 10079 | codep++; |
252b5132 RH |
10080 | } |
10081 | else | |
10082 | { | |
6439fc28 | 10083 | dp = &dis386[*codep]; |
252b5132 | 10084 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 10085 | codep++; |
252b5132 | 10086 | } |
246c51aa | 10087 | |
df18fdba L |
10088 | /* Save sizeflag for printing the extra prefixes later before updating |
10089 | it for mnemonic and operand processing. The prefix names depend | |
10090 | only on the address mode. */ | |
10091 | orig_sizeflag = sizeflag; | |
c608c12e | 10092 | if (prefixes & PREFIX_ADDR) |
df18fdba | 10093 | sizeflag ^= AFLAG; |
b844680a | 10094 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 10095 | sizeflag ^= DFLAG; |
3ffd33cf | 10096 | |
285ca992 | 10097 | end_codep = codep; |
8bb15339 | 10098 | if (need_modrm) |
252b5132 RH |
10099 | { |
10100 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
10101 | modrm.mod = (*codep >> 6) & 3; |
10102 | modrm.reg = (*codep >> 3) & 7; | |
10103 | modrm.rm = *codep & 7; | |
252b5132 | 10104 | } |
0e9f3bf1 L |
10105 | else |
10106 | memset (&modrm, 0, sizeof (modrm)); | |
252b5132 | 10107 | |
42d5f9c6 | 10108 | need_vex = 0; |
caf0678c | 10109 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 10110 | |
ce518a5f | 10111 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 10112 | { |
55cf16e1 | 10113 | get_sib (info, sizeflag); |
252b5132 RH |
10114 | dofloat (sizeflag); |
10115 | } | |
10116 | else | |
10117 | { | |
8bb15339 | 10118 | dp = get_valid_dis386 (dp, info); |
b844680a | 10119 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 10120 | { |
55cf16e1 | 10121 | get_sib (info, sizeflag); |
ce518a5f L |
10122 | for (i = 0; i < MAX_OPERANDS; ++i) |
10123 | { | |
246c51aa | 10124 | obufp = op_out[i]; |
ce518a5f L |
10125 | op_ad = MAX_OPERANDS - 1 - i; |
10126 | if (dp->op[i].rtn) | |
10127 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
10128 | /* For EVEX instruction after the last operand masking |
10129 | should be printed. */ | |
10130 | if (i == 0 && vex.evex) | |
10131 | { | |
10132 | /* Don't print {%k0}. */ | |
10133 | if (vex.mask_register_specifier) | |
10134 | { | |
10135 | oappend ("{"); | |
10136 | oappend (names_mask[vex.mask_register_specifier]); | |
10137 | oappend ("}"); | |
10138 | } | |
10139 | if (vex.zeroing) | |
10140 | oappend ("{z}"); | |
10141 | } | |
ce518a5f | 10142 | } |
6439fc28 | 10143 | } |
252b5132 RH |
10144 | } |
10145 | ||
1d67fe3b TT |
10146 | /* Clear instruction information. */ |
10147 | if (the_info) | |
10148 | { | |
10149 | the_info->insn_info_valid = 0; | |
10150 | the_info->branch_delay_insns = 0; | |
10151 | the_info->data_size = 0; | |
10152 | the_info->insn_type = dis_noninsn; | |
10153 | the_info->target = 0; | |
10154 | the_info->target2 = 0; | |
10155 | } | |
10156 | ||
10157 | /* Reset jump operation indicator. */ | |
10158 | op_is_jump = FALSE; | |
10159 | ||
10160 | { | |
10161 | int jump_detection = 0; | |
10162 | ||
10163 | /* Extract flags. */ | |
10164 | for (i = 0; i < MAX_OPERANDS; ++i) | |
10165 | { | |
10166 | if ((dp->op[i].rtn == OP_J) | |
10167 | || (dp->op[i].rtn == OP_indirE)) | |
10168 | jump_detection |= 1; | |
10169 | else if ((dp->op[i].rtn == BND_Fixup) | |
10170 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
10171 | jump_detection |= 2; | |
10172 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
10173 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
10174 | jump_detection |= 4; | |
10175 | } | |
10176 | ||
10177 | /* Determine if this is a jump or branch. */ | |
10178 | if ((jump_detection & 0x3) == 0x3) | |
10179 | { | |
10180 | op_is_jump = TRUE; | |
10181 | if (jump_detection & 0x4) | |
10182 | the_info->insn_type = dis_condbranch; | |
10183 | else | |
10184 | the_info->insn_type = | |
10185 | (dp->name && !strncmp(dp->name, "call", 4)) | |
10186 | ? dis_jsr : dis_branch; | |
10187 | } | |
10188 | } | |
10189 | ||
63c6fc6c L |
10190 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
10191 | are all 0s in inverted form. */ | |
10192 | if (need_vex && vex.register_specifier != 0) | |
10193 | { | |
10194 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10195 | return end_codep - priv.the_buffer; | |
10196 | } | |
10197 | ||
7531c613 JB |
10198 | switch (dp->prefix_requirement) |
10199 | { | |
10200 | case PREFIX_DATA: | |
10201 | /* If only the data prefix is marked as mandatory, its absence renders | |
10202 | the encoding invalid. Most other PREFIX_OPCODE rules still apply. */ | |
10203 | if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA)) | |
10204 | { | |
10205 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10206 | return end_codep - priv.the_buffer; | |
10207 | } | |
10208 | used_prefixes |= PREFIX_DATA; | |
10209 | /* Fall through. */ | |
10210 | case PREFIX_OPCODE: | |
10211 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is | |
10212 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
10213 | used by putop and MMX/SSE operand and may be overridden by the | |
10214 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
10215 | separately. */ | |
10216 | if (((need_vex | |
10217 | ? vex.prefix == REPE_PREFIX_OPCODE | |
10218 | || vex.prefix == REPNE_PREFIX_OPCODE | |
10219 | : (prefixes | |
10220 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
10221 | && (used_prefixes | |
10222 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
10223 | || (((need_vex | |
10224 | ? vex.prefix == DATA_PREFIX_OPCODE | |
10225 | : ((prefixes | |
10226 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
10227 | == PREFIX_DATA)) | |
10228 | && (used_prefixes & PREFIX_DATA) == 0)) | |
10229 | || (vex.evex && dp->prefix_requirement != PREFIX_DATA | |
10230 | && !vex.w != !(used_prefixes & PREFIX_DATA))) | |
10231 | { | |
10232 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10233 | return end_codep - priv.the_buffer; | |
10234 | } | |
10235 | break; | |
10236 | } | |
10237 | ||
d869730d | 10238 | /* Check if the REX prefix is used. */ |
73239888 | 10239 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
10240 | all_prefixes[last_rex_prefix] = 0; |
10241 | ||
5e6718e4 | 10242 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
10243 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
10244 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 10245 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
10246 | all_prefixes[last_seg_prefix] = 0; |
10247 | ||
5e6718e4 | 10248 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
10249 | if ((prefixes & PREFIX_ADDR) != 0 |
10250 | && (used_prefixes & PREFIX_ADDR) != 0) | |
10251 | all_prefixes[last_addr_prefix] = 0; | |
10252 | ||
df18fdba L |
10253 | /* Check if the DATA prefix is used. */ |
10254 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
10255 | && (used_prefixes & PREFIX_DATA) != 0 |
10256 | && !need_vex) | |
df18fdba | 10257 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 10258 | |
df18fdba | 10259 | /* Print the extra prefixes. */ |
f16cd0d5 | 10260 | prefix_length = 0; |
f310f33d | 10261 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
10262 | if (all_prefixes[i]) |
10263 | { | |
10264 | const char *name; | |
df18fdba | 10265 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
10266 | if (name == NULL) |
10267 | abort (); | |
10268 | prefix_length += strlen (name) + 1; | |
10269 | (*info->fprintf_func) (info->stream, "%s ", name); | |
10270 | } | |
b844680a | 10271 | |
f16cd0d5 L |
10272 | /* Check maximum code length. */ |
10273 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
10274 | { | |
10275 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10276 | return MAX_CODE_LENGTH; | |
10277 | } | |
b844680a | 10278 | |
ea397f5b | 10279 | obufp = mnemonicendp; |
f16cd0d5 | 10280 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
10281 | oappend (" "); |
10282 | oappend (" "); | |
10283 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
10284 | ||
10285 | /* The enter and bound instructions are printed with operands in the same | |
10286 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 10287 | if (intel_syntax || two_source_ops) |
252b5132 | 10288 | { |
185b1163 L |
10289 | bfd_vma riprel; |
10290 | ||
ce518a5f | 10291 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 10292 | op_txt[i] = op_out[i]; |
246c51aa | 10293 | |
3a8547d2 JB |
10294 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
10295 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
10296 | { | |
10297 | op_txt[2] = op_out[3]; | |
10298 | op_txt[3] = op_out[2]; | |
10299 | } | |
10300 | ||
ce518a5f L |
10301 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
10302 | { | |
6c067bbb RM |
10303 | op_ad = op_index[i]; |
10304 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
10305 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
10306 | riprel = op_riprel[i]; |
10307 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
10308 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 10309 | } |
252b5132 RH |
10310 | } |
10311 | else | |
10312 | { | |
ce518a5f | 10313 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 10314 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
10315 | } |
10316 | ||
ce518a5f L |
10317 | needcomma = 0; |
10318 | for (i = 0; i < MAX_OPERANDS; ++i) | |
10319 | if (*op_txt[i]) | |
10320 | { | |
10321 | if (needcomma) | |
10322 | (*info->fprintf_func) (info->stream, ","); | |
10323 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
10324 | { |
10325 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
10326 | ||
10327 | if (the_info && op_is_jump) | |
10328 | { | |
10329 | the_info->insn_info_valid = 1; | |
10330 | the_info->branch_delay_insns = 0; | |
10331 | the_info->data_size = 0; | |
10332 | the_info->target = target; | |
10333 | the_info->target2 = 0; | |
10334 | } | |
10335 | (*info->print_address_func) (target, info); | |
10336 | } | |
ce518a5f L |
10337 | else |
10338 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
10339 | needcomma = 1; | |
10340 | } | |
050dfa73 | 10341 | |
ce518a5f | 10342 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
10343 | if (op_index[i] != -1 && op_riprel[i]) |
10344 | { | |
10345 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 10346 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 10347 | + op_address[op_index[i]]), info); |
185b1163 | 10348 | break; |
52b15da3 | 10349 | } |
e396998b | 10350 | return codep - priv.the_buffer; |
252b5132 RH |
10351 | } |
10352 | ||
6439fc28 | 10353 | static const char *float_mem[] = { |
252b5132 | 10354 | /* d8 */ |
7c52e0e8 L |
10355 | "fadd{s|}", |
10356 | "fmul{s|}", | |
10357 | "fcom{s|}", | |
10358 | "fcomp{s|}", | |
10359 | "fsub{s|}", | |
10360 | "fsubr{s|}", | |
10361 | "fdiv{s|}", | |
10362 | "fdivr{s|}", | |
db6eb5be | 10363 | /* d9 */ |
7c52e0e8 | 10364 | "fld{s|}", |
252b5132 | 10365 | "(bad)", |
7c52e0e8 L |
10366 | "fst{s|}", |
10367 | "fstp{s|}", | |
d1c36125 | 10368 | "fldenv{C|C}", |
252b5132 | 10369 | "fldcw", |
d1c36125 | 10370 | "fNstenv{C|C}", |
252b5132 RH |
10371 | "fNstcw", |
10372 | /* da */ | |
7c52e0e8 L |
10373 | "fiadd{l|}", |
10374 | "fimul{l|}", | |
10375 | "ficom{l|}", | |
10376 | "ficomp{l|}", | |
10377 | "fisub{l|}", | |
10378 | "fisubr{l|}", | |
10379 | "fidiv{l|}", | |
10380 | "fidivr{l|}", | |
252b5132 | 10381 | /* db */ |
7c52e0e8 L |
10382 | "fild{l|}", |
10383 | "fisttp{l|}", | |
10384 | "fist{l|}", | |
10385 | "fistp{l|}", | |
252b5132 | 10386 | "(bad)", |
464dc4af | 10387 | "fld{t|}", |
252b5132 | 10388 | "(bad)", |
464dc4af | 10389 | "fstp{t|}", |
252b5132 | 10390 | /* dc */ |
7c52e0e8 L |
10391 | "fadd{l|}", |
10392 | "fmul{l|}", | |
10393 | "fcom{l|}", | |
10394 | "fcomp{l|}", | |
10395 | "fsub{l|}", | |
10396 | "fsubr{l|}", | |
10397 | "fdiv{l|}", | |
10398 | "fdivr{l|}", | |
252b5132 | 10399 | /* dd */ |
7c52e0e8 L |
10400 | "fld{l|}", |
10401 | "fisttp{ll|}", | |
10402 | "fst{l||}", | |
10403 | "fstp{l|}", | |
d1c36125 | 10404 | "frstor{C|C}", |
252b5132 | 10405 | "(bad)", |
d1c36125 | 10406 | "fNsave{C|C}", |
252b5132 RH |
10407 | "fNstsw", |
10408 | /* de */ | |
ac465521 JB |
10409 | "fiadd{s|}", |
10410 | "fimul{s|}", | |
10411 | "ficom{s|}", | |
10412 | "ficomp{s|}", | |
10413 | "fisub{s|}", | |
10414 | "fisubr{s|}", | |
10415 | "fidiv{s|}", | |
10416 | "fidivr{s|}", | |
252b5132 | 10417 | /* df */ |
ac465521 JB |
10418 | "fild{s|}", |
10419 | "fisttp{s|}", | |
10420 | "fist{s|}", | |
10421 | "fistp{s|}", | |
252b5132 | 10422 | "fbld", |
7c52e0e8 | 10423 | "fild{ll|}", |
252b5132 | 10424 | "fbstp", |
7c52e0e8 | 10425 | "fistp{ll|}", |
1d9f512f AM |
10426 | }; |
10427 | ||
10428 | static const unsigned char float_mem_mode[] = { | |
10429 | /* d8 */ | |
10430 | d_mode, | |
10431 | d_mode, | |
10432 | d_mode, | |
10433 | d_mode, | |
10434 | d_mode, | |
10435 | d_mode, | |
10436 | d_mode, | |
10437 | d_mode, | |
10438 | /* d9 */ | |
10439 | d_mode, | |
10440 | 0, | |
10441 | d_mode, | |
10442 | d_mode, | |
10443 | 0, | |
10444 | w_mode, | |
10445 | 0, | |
10446 | w_mode, | |
10447 | /* da */ | |
10448 | d_mode, | |
10449 | d_mode, | |
10450 | d_mode, | |
10451 | d_mode, | |
10452 | d_mode, | |
10453 | d_mode, | |
10454 | d_mode, | |
10455 | d_mode, | |
10456 | /* db */ | |
10457 | d_mode, | |
10458 | d_mode, | |
10459 | d_mode, | |
10460 | d_mode, | |
10461 | 0, | |
9306ca4a | 10462 | t_mode, |
1d9f512f | 10463 | 0, |
9306ca4a | 10464 | t_mode, |
1d9f512f AM |
10465 | /* dc */ |
10466 | q_mode, | |
10467 | q_mode, | |
10468 | q_mode, | |
10469 | q_mode, | |
10470 | q_mode, | |
10471 | q_mode, | |
10472 | q_mode, | |
10473 | q_mode, | |
10474 | /* dd */ | |
10475 | q_mode, | |
10476 | q_mode, | |
10477 | q_mode, | |
10478 | q_mode, | |
10479 | 0, | |
10480 | 0, | |
10481 | 0, | |
10482 | w_mode, | |
10483 | /* de */ | |
10484 | w_mode, | |
10485 | w_mode, | |
10486 | w_mode, | |
10487 | w_mode, | |
10488 | w_mode, | |
10489 | w_mode, | |
10490 | w_mode, | |
10491 | w_mode, | |
10492 | /* df */ | |
10493 | w_mode, | |
10494 | w_mode, | |
10495 | w_mode, | |
10496 | w_mode, | |
9306ca4a | 10497 | t_mode, |
1d9f512f | 10498 | q_mode, |
9306ca4a | 10499 | t_mode, |
1d9f512f | 10500 | q_mode |
252b5132 RH |
10501 | }; |
10502 | ||
ce518a5f L |
10503 | #define ST { OP_ST, 0 } |
10504 | #define STi { OP_STi, 0 } | |
252b5132 | 10505 | |
48c97fa1 L |
10506 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
10507 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
10508 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
10509 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
10510 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
10511 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
10512 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
10513 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
10514 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 10515 | |
2da11e11 | 10516 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
10517 | /* d8 */ |
10518 | { | |
bf890a93 IT |
10519 | { "fadd", { ST, STi }, 0 }, |
10520 | { "fmul", { ST, STi }, 0 }, | |
10521 | { "fcom", { STi }, 0 }, | |
10522 | { "fcomp", { STi }, 0 }, | |
10523 | { "fsub", { ST, STi }, 0 }, | |
10524 | { "fsubr", { ST, STi }, 0 }, | |
10525 | { "fdiv", { ST, STi }, 0 }, | |
10526 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
10527 | }, |
10528 | /* d9 */ | |
10529 | { | |
bf890a93 IT |
10530 | { "fld", { STi }, 0 }, |
10531 | { "fxch", { STi }, 0 }, | |
252b5132 | 10532 | { FGRPd9_2 }, |
592d1631 | 10533 | { Bad_Opcode }, |
252b5132 RH |
10534 | { FGRPd9_4 }, |
10535 | { FGRPd9_5 }, | |
10536 | { FGRPd9_6 }, | |
10537 | { FGRPd9_7 }, | |
10538 | }, | |
10539 | /* da */ | |
10540 | { | |
bf890a93 IT |
10541 | { "fcmovb", { ST, STi }, 0 }, |
10542 | { "fcmove", { ST, STi }, 0 }, | |
10543 | { "fcmovbe",{ ST, STi }, 0 }, | |
10544 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 10545 | { Bad_Opcode }, |
252b5132 | 10546 | { FGRPda_5 }, |
592d1631 L |
10547 | { Bad_Opcode }, |
10548 | { Bad_Opcode }, | |
252b5132 RH |
10549 | }, |
10550 | /* db */ | |
10551 | { | |
bf890a93 IT |
10552 | { "fcmovnb",{ ST, STi }, 0 }, |
10553 | { "fcmovne",{ ST, STi }, 0 }, | |
10554 | { "fcmovnbe",{ ST, STi }, 0 }, | |
10555 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 10556 | { FGRPdb_4 }, |
bf890a93 IT |
10557 | { "fucomi", { ST, STi }, 0 }, |
10558 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 10559 | { Bad_Opcode }, |
252b5132 RH |
10560 | }, |
10561 | /* dc */ | |
10562 | { | |
bf890a93 IT |
10563 | { "fadd", { STi, ST }, 0 }, |
10564 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
10565 | { Bad_Opcode }, |
10566 | { Bad_Opcode }, | |
d53e6b98 JB |
10567 | { "fsub{!M|r}", { STi, ST }, 0 }, |
10568 | { "fsub{M|}", { STi, ST }, 0 }, | |
10569 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
10570 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
10571 | }, |
10572 | /* dd */ | |
10573 | { | |
bf890a93 | 10574 | { "ffree", { STi }, 0 }, |
592d1631 | 10575 | { Bad_Opcode }, |
bf890a93 IT |
10576 | { "fst", { STi }, 0 }, |
10577 | { "fstp", { STi }, 0 }, | |
10578 | { "fucom", { STi }, 0 }, | |
10579 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
10580 | { Bad_Opcode }, |
10581 | { Bad_Opcode }, | |
252b5132 RH |
10582 | }, |
10583 | /* de */ | |
10584 | { | |
bf890a93 IT |
10585 | { "faddp", { STi, ST }, 0 }, |
10586 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 10587 | { Bad_Opcode }, |
252b5132 | 10588 | { FGRPde_3 }, |
d53e6b98 JB |
10589 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
10590 | { "fsub{M|}p", { STi, ST }, 0 }, | |
10591 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
10592 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
10593 | }, |
10594 | /* df */ | |
10595 | { | |
bf890a93 | 10596 | { "ffreep", { STi }, 0 }, |
592d1631 L |
10597 | { Bad_Opcode }, |
10598 | { Bad_Opcode }, | |
10599 | { Bad_Opcode }, | |
252b5132 | 10600 | { FGRPdf_4 }, |
bf890a93 IT |
10601 | { "fucomip", { ST, STi }, 0 }, |
10602 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 10603 | { Bad_Opcode }, |
252b5132 RH |
10604 | }, |
10605 | }; | |
10606 | ||
252b5132 | 10607 | static char *fgrps[][8] = { |
48c97fa1 L |
10608 | /* Bad opcode 0 */ |
10609 | { | |
10610 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10611 | }, | |
10612 | ||
10613 | /* d9_2 1 */ | |
252b5132 RH |
10614 | { |
10615 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10616 | }, | |
10617 | ||
48c97fa1 | 10618 | /* d9_4 2 */ |
252b5132 RH |
10619 | { |
10620 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
10621 | }, | |
10622 | ||
48c97fa1 | 10623 | /* d9_5 3 */ |
252b5132 RH |
10624 | { |
10625 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
10626 | }, | |
10627 | ||
48c97fa1 | 10628 | /* d9_6 4 */ |
252b5132 RH |
10629 | { |
10630 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
10631 | }, | |
10632 | ||
48c97fa1 | 10633 | /* d9_7 5 */ |
252b5132 RH |
10634 | { |
10635 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
10636 | }, | |
10637 | ||
48c97fa1 | 10638 | /* da_5 6 */ |
252b5132 RH |
10639 | { |
10640 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10641 | }, | |
10642 | ||
48c97fa1 | 10643 | /* db_4 7 */ |
252b5132 | 10644 | { |
309d3373 JB |
10645 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
10646 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
10647 | }, |
10648 | ||
48c97fa1 | 10649 | /* de_3 8 */ |
252b5132 RH |
10650 | { |
10651 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10652 | }, | |
10653 | ||
48c97fa1 | 10654 | /* df_4 9 */ |
252b5132 RH |
10655 | { |
10656 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10657 | }, | |
10658 | }; | |
10659 | ||
b6169b20 L |
10660 | static void |
10661 | swap_operand (void) | |
10662 | { | |
10663 | mnemonicendp[0] = '.'; | |
10664 | mnemonicendp[1] = 's'; | |
10665 | mnemonicendp += 2; | |
10666 | } | |
10667 | ||
b844680a L |
10668 | static void |
10669 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
10670 | int sizeflag ATTRIBUTE_UNUSED) | |
10671 | { | |
10672 | /* Skip mod/rm byte. */ | |
10673 | MODRM_CHECK; | |
10674 | codep++; | |
10675 | } | |
10676 | ||
252b5132 | 10677 | static void |
26ca5450 | 10678 | dofloat (int sizeflag) |
252b5132 | 10679 | { |
2da11e11 | 10680 | const struct dis386 *dp; |
252b5132 RH |
10681 | unsigned char floatop; |
10682 | ||
10683 | floatop = codep[-1]; | |
10684 | ||
7967e09e | 10685 | if (modrm.mod != 3) |
252b5132 | 10686 | { |
7967e09e | 10687 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
10688 | |
10689 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 10690 | obufp = op_out[0]; |
6e50d963 | 10691 | op_ad = 2; |
1d9f512f | 10692 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
10693 | return; |
10694 | } | |
6608db57 | 10695 | /* Skip mod/rm byte. */ |
4bba6815 | 10696 | MODRM_CHECK; |
252b5132 RH |
10697 | codep++; |
10698 | ||
7967e09e | 10699 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
10700 | if (dp->name == NULL) |
10701 | { | |
7967e09e | 10702 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 10703 | |
6608db57 | 10704 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 10705 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 10706 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
10707 | } |
10708 | else | |
10709 | { | |
10710 | putop (dp->name, sizeflag); | |
10711 | ||
ce518a5f | 10712 | obufp = op_out[0]; |
6e50d963 | 10713 | op_ad = 2; |
ce518a5f L |
10714 | if (dp->op[0].rtn) |
10715 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 10716 | |
ce518a5f | 10717 | obufp = op_out[1]; |
6e50d963 | 10718 | op_ad = 1; |
ce518a5f L |
10719 | if (dp->op[1].rtn) |
10720 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
10721 | } |
10722 | } | |
10723 | ||
9ce09ba2 RM |
10724 | /* Like oappend (below), but S is a string starting with '%'. |
10725 | In Intel syntax, the '%' is elided. */ | |
10726 | static void | |
10727 | oappend_maybe_intel (const char *s) | |
10728 | { | |
10729 | oappend (s + intel_syntax); | |
10730 | } | |
10731 | ||
252b5132 | 10732 | static void |
26ca5450 | 10733 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10734 | { |
9ce09ba2 | 10735 | oappend_maybe_intel ("%st"); |
252b5132 RH |
10736 | } |
10737 | ||
252b5132 | 10738 | static void |
26ca5450 | 10739 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10740 | { |
7967e09e | 10741 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 10742 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
10743 | } |
10744 | ||
6608db57 | 10745 | /* Capital letters in template are macros. */ |
6439fc28 | 10746 | static int |
d3ce72d0 | 10747 | putop (const char *in_template, int sizeflag) |
252b5132 | 10748 | { |
2da11e11 | 10749 | const char *p; |
9306ca4a | 10750 | int alt = 0; |
9d141669 | 10751 | int cond = 1; |
21a3faeb | 10752 | unsigned int l = 0, len = 0; |
98b528ac L |
10753 | char last[4]; |
10754 | ||
d3ce72d0 | 10755 | for (p = in_template; *p; p++) |
252b5132 | 10756 | { |
21a3faeb JB |
10757 | if (len > l) |
10758 | { | |
10759 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
10760 | abort (); | |
10761 | last[l++] = *p; | |
10762 | continue; | |
10763 | } | |
252b5132 RH |
10764 | switch (*p) |
10765 | { | |
10766 | default: | |
10767 | *obufp++ = *p; | |
10768 | break; | |
98b528ac L |
10769 | case '%': |
10770 | len++; | |
10771 | break; | |
9d141669 L |
10772 | case '!': |
10773 | cond = 0; | |
10774 | break; | |
6439fc28 | 10775 | case '{': |
6439fc28 | 10776 | if (intel_syntax) |
6439fc28 AM |
10777 | { |
10778 | while (*++p != '|') | |
7c52e0e8 L |
10779 | if (*p == '}' || *p == '\0') |
10780 | abort (); | |
d1c36125 | 10781 | alt = 1; |
6439fc28 | 10782 | } |
d1c36125 | 10783 | break; |
6439fc28 AM |
10784 | case '|': |
10785 | while (*++p != '}') | |
10786 | { | |
10787 | if (*p == '\0') | |
10788 | abort (); | |
10789 | } | |
10790 | break; | |
10791 | case '}': | |
d1c36125 | 10792 | alt = 0; |
6439fc28 | 10793 | break; |
252b5132 | 10794 | case 'A': |
db6eb5be AM |
10795 | if (intel_syntax) |
10796 | break; | |
0e9f3bf1 L |
10797 | if ((need_modrm && modrm.mod != 3) |
10798 | || (sizeflag & SUFFIX_ALWAYS)) | |
252b5132 RH |
10799 | *obufp++ = 'b'; |
10800 | break; | |
10801 | case 'B': | |
21a3faeb | 10802 | if (l == 0) |
4b06377f | 10803 | { |
dc1e8a47 | 10804 | case_B: |
4b06377f L |
10805 | if (intel_syntax) |
10806 | break; | |
10807 | if (sizeflag & SUFFIX_ALWAYS) | |
10808 | *obufp++ = 'b'; | |
10809 | } | |
21a3faeb | 10810 | else if (l == 1 && last[0] == 'L') |
4b06377f | 10811 | { |
4b06377f L |
10812 | if (address_mode == mode_64bit |
10813 | && !(prefixes & PREFIX_ADDR)) | |
10814 | { | |
10815 | *obufp++ = 'a'; | |
10816 | *obufp++ = 'b'; | |
10817 | *obufp++ = 's'; | |
10818 | } | |
10819 | ||
10820 | goto case_B; | |
10821 | } | |
21a3faeb JB |
10822 | else |
10823 | abort (); | |
252b5132 | 10824 | break; |
9306ca4a JB |
10825 | case 'C': |
10826 | if (intel_syntax && !alt) | |
10827 | break; | |
10828 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
10829 | { | |
10830 | if (sizeflag & DFLAG) | |
10831 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10832 | else | |
10833 | *obufp++ = intel_syntax ? 'w' : 's'; | |
10834 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10835 | } | |
10836 | break; | |
ed7841b3 JB |
10837 | case 'D': |
10838 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
10839 | break; | |
161a04f6 | 10840 | USED_REX (REX_W); |
7967e09e | 10841 | if (modrm.mod == 3) |
ed7841b3 | 10842 | { |
161a04f6 | 10843 | if (rex & REX_W) |
ed7841b3 | 10844 | *obufp++ = 'q'; |
ed7841b3 | 10845 | else |
f16cd0d5 L |
10846 | { |
10847 | if (sizeflag & DFLAG) | |
10848 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10849 | else | |
10850 | *obufp++ = 'w'; | |
10851 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10852 | } | |
ed7841b3 JB |
10853 | } |
10854 | else | |
10855 | *obufp++ = 'w'; | |
10856 | break; | |
252b5132 | 10857 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 10858 | if (address_mode == mode_64bit) |
c1a64871 JH |
10859 | { |
10860 | if (sizeflag & AFLAG) | |
10861 | *obufp++ = 'r'; | |
10862 | else | |
10863 | *obufp++ = 'e'; | |
10864 | } | |
10865 | else | |
10866 | if (sizeflag & AFLAG) | |
10867 | *obufp++ = 'e'; | |
3ffd33cf AM |
10868 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10869 | break; | |
10870 | case 'F': | |
db6eb5be AM |
10871 | if (intel_syntax) |
10872 | break; | |
e396998b | 10873 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
10874 | { |
10875 | if (sizeflag & AFLAG) | |
cb712a9e | 10876 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 10877 | else |
cb712a9e | 10878 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
10879 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10880 | } | |
252b5132 | 10881 | break; |
52fd6d94 JB |
10882 | case 'G': |
10883 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
10884 | break; | |
161a04f6 | 10885 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10886 | *obufp++ = 'l'; |
10887 | else | |
10888 | *obufp++ = 'w'; | |
161a04f6 | 10889 | if (!(rex & REX_W)) |
52fd6d94 JB |
10890 | used_prefixes |= (prefixes & PREFIX_DATA); |
10891 | break; | |
5dd0794d | 10892 | case 'H': |
db6eb5be AM |
10893 | if (intel_syntax) |
10894 | break; | |
5dd0794d AM |
10895 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
10896 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
10897 | { | |
10898 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
10899 | *obufp++ = ','; | |
10900 | *obufp++ = 'p'; | |
10901 | if (prefixes & PREFIX_DS) | |
10902 | *obufp++ = 't'; | |
10903 | else | |
10904 | *obufp++ = 'n'; | |
10905 | } | |
10906 | break; | |
42903f7f L |
10907 | case 'K': |
10908 | USED_REX (REX_W); | |
10909 | if (rex & REX_W) | |
10910 | *obufp++ = 'q'; | |
10911 | else | |
10912 | *obufp++ = 'd'; | |
10913 | break; | |
252b5132 | 10914 | case 'L': |
78467458 | 10915 | abort (); |
9d141669 L |
10916 | case 'M': |
10917 | if (intel_mnemonic != cond) | |
10918 | *obufp++ = 'r'; | |
10919 | break; | |
252b5132 RH |
10920 | case 'N': |
10921 | if ((prefixes & PREFIX_FWAIT) == 0) | |
10922 | *obufp++ = 'n'; | |
7d421014 ILT |
10923 | else |
10924 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 10925 | break; |
52b15da3 | 10926 | case 'O': |
161a04f6 L |
10927 | USED_REX (REX_W); |
10928 | if (rex & REX_W) | |
6439fc28 | 10929 | *obufp++ = 'o'; |
a35ca55a JB |
10930 | else if (intel_syntax && (sizeflag & DFLAG)) |
10931 | *obufp++ = 'q'; | |
52b15da3 JH |
10932 | else |
10933 | *obufp++ = 'd'; | |
161a04f6 | 10934 | if (!(rex & REX_W)) |
a35ca55a | 10935 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 10936 | break; |
36938cab JB |
10937 | case '@': |
10938 | if (address_mode == mode_64bit | |
10939 | && (isa64 == intel64 || (rex & REX_W) | |
10940 | || !(prefixes & PREFIX_DATA))) | |
6439fc28 | 10941 | { |
36938cab JB |
10942 | if (sizeflag & SUFFIX_ALWAYS) |
10943 | *obufp++ = 'q'; | |
6439fc28 AM |
10944 | break; |
10945 | } | |
6608db57 | 10946 | /* Fall through. */ |
252b5132 | 10947 | case 'P': |
21a3faeb | 10948 | if (l == 0) |
d9e3625e | 10949 | { |
0e9f3bf1 | 10950 | if ((modrm.mod == 3 || !cond) |
c3f5525f | 10951 | && !(sizeflag & SUFFIX_ALWAYS)) |
36938cab JB |
10952 | break; |
10953 | /* Fall through. */ | |
10954 | case 'T': | |
10955 | if ((!(rex & REX_W) && (prefixes & PREFIX_DATA)) | |
10956 | || ((sizeflag & SUFFIX_ALWAYS) | |
10957 | && address_mode != mode_64bit)) | |
4b4c407a | 10958 | { |
36938cab JB |
10959 | *obufp++ = (sizeflag & DFLAG) ? |
10960 | intel_syntax ? 'd' : 'l' : 'w'; | |
10961 | used_prefixes |= (prefixes & PREFIX_DATA); | |
d9e3625e | 10962 | } |
36938cab JB |
10963 | else if (sizeflag & SUFFIX_ALWAYS) |
10964 | *obufp++ = 'q'; | |
d9e3625e | 10965 | } |
21a3faeb | 10966 | else if (l == 1 && last[0] == 'L') |
252b5132 | 10967 | { |
4b4c407a L |
10968 | if ((prefixes & PREFIX_DATA) |
10969 | || (rex & REX_W) | |
10970 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10971 | { |
4b4c407a L |
10972 | USED_REX (REX_W); |
10973 | if (rex & REX_W) | |
10974 | *obufp++ = 'q'; | |
10975 | else | |
10976 | { | |
10977 | if (sizeflag & DFLAG) | |
10978 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10979 | else | |
10980 | *obufp++ = 'w'; | |
10981 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10982 | } | |
52b15da3 | 10983 | } |
252b5132 | 10984 | } |
21a3faeb JB |
10985 | else |
10986 | abort (); | |
252b5132 RH |
10987 | break; |
10988 | case 'Q': | |
21a3faeb | 10989 | if (l == 0) |
252b5132 | 10990 | { |
98b528ac L |
10991 | if (intel_syntax && !alt) |
10992 | break; | |
10993 | USED_REX (REX_W); | |
0e9f3bf1 L |
10994 | if ((need_modrm && modrm.mod != 3) |
10995 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10996 | { |
98b528ac L |
10997 | if (rex & REX_W) |
10998 | *obufp++ = 'q'; | |
52b15da3 | 10999 | else |
98b528ac L |
11000 | { |
11001 | if (sizeflag & DFLAG) | |
11002 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
11003 | else | |
11004 | *obufp++ = 'w'; | |
f16cd0d5 | 11005 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 11006 | } |
52b15da3 | 11007 | } |
98b528ac | 11008 | } |
492a76aa JB |
11009 | else if (l == 1 && last[0] == 'D') |
11010 | *obufp++ = vex.w ? 'q' : 'd'; | |
21a3faeb | 11011 | else if (l == 1 && last[0] == 'L') |
98b528ac | 11012 | { |
b24d668c JB |
11013 | if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) |
11014 | : address_mode != mode_64bit) | |
98b528ac L |
11015 | break; |
11016 | if ((rex & REX_W)) | |
11017 | { | |
11018 | USED_REX (REX_W); | |
11019 | *obufp++ = 'q'; | |
11020 | } | |
5b316d90 | 11021 | else if((address_mode == mode_64bit && cond) |
589958d6 JB |
11022 | || (sizeflag & SUFFIX_ALWAYS)) |
11023 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 11024 | } |
21a3faeb JB |
11025 | else |
11026 | abort (); | |
252b5132 RH |
11027 | break; |
11028 | case 'R': | |
161a04f6 L |
11029 | USED_REX (REX_W); |
11030 | if (rex & REX_W) | |
a35ca55a JB |
11031 | *obufp++ = 'q'; |
11032 | else if (sizeflag & DFLAG) | |
c608c12e | 11033 | { |
a35ca55a | 11034 | if (intel_syntax) |
c608c12e | 11035 | *obufp++ = 'd'; |
c608c12e | 11036 | else |
a35ca55a | 11037 | *obufp++ = 'l'; |
c608c12e | 11038 | } |
252b5132 | 11039 | else |
a35ca55a JB |
11040 | *obufp++ = 'w'; |
11041 | if (intel_syntax && !p[1] | |
161a04f6 | 11042 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 11043 | *obufp++ = 'e'; |
161a04f6 | 11044 | if (!(rex & REX_W)) |
52b15da3 | 11045 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11046 | break; |
11047 | case 'S': | |
21a3faeb | 11048 | if (l == 0) |
252b5132 | 11049 | { |
dc1e8a47 | 11050 | case_S: |
4b06377f L |
11051 | if (intel_syntax) |
11052 | break; | |
11053 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 11054 | { |
4b06377f L |
11055 | if (rex & REX_W) |
11056 | *obufp++ = 'q'; | |
52b15da3 | 11057 | else |
4b06377f L |
11058 | { |
11059 | if (sizeflag & DFLAG) | |
11060 | *obufp++ = 'l'; | |
11061 | else | |
11062 | *obufp++ = 'w'; | |
11063 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11064 | } | |
11065 | } | |
11066 | } | |
21a3faeb | 11067 | else if (l == 1 && last[0] == 'L') |
4b06377f | 11068 | { |
4b06377f L |
11069 | if (address_mode == mode_64bit |
11070 | && !(prefixes & PREFIX_ADDR)) | |
11071 | { | |
11072 | *obufp++ = 'a'; | |
11073 | *obufp++ = 'b'; | |
11074 | *obufp++ = 's'; | |
11075 | } | |
11076 | ||
11077 | goto case_S; | |
252b5132 | 11078 | } |
21a3faeb JB |
11079 | else |
11080 | abort (); | |
252b5132 | 11081 | break; |
f0e8d0ba JB |
11082 | case 'V': |
11083 | if (l == 0) | |
11084 | abort (); | |
58bf9b6a L |
11085 | else if (l == 1 |
11086 | && (last[0] == 'L' || last[0] == 'X')) | |
f0e8d0ba | 11087 | { |
58bf9b6a L |
11088 | if (last[0] == 'X') |
11089 | { | |
11090 | *obufp++ = '{'; | |
11091 | *obufp++ = 'v'; | |
11092 | *obufp++ = 'e'; | |
11093 | *obufp++ = 'x'; | |
11094 | *obufp++ = '3'; | |
11095 | *obufp++ = '}'; | |
11096 | } | |
11097 | else if (rex & REX_W) | |
f0e8d0ba JB |
11098 | { |
11099 | *obufp++ = 'a'; | |
11100 | *obufp++ = 'b'; | |
11101 | *obufp++ = 's'; | |
11102 | } | |
11103 | } | |
11104 | else | |
11105 | abort (); | |
11106 | goto case_S; | |
11107 | case 'W': | |
11108 | if (l == 0) | |
11109 | { | |
11110 | /* operand size flag for cwtl, cbtw */ | |
11111 | USED_REX (REX_W); | |
11112 | if (rex & REX_W) | |
11113 | { | |
11114 | if (intel_syntax) | |
11115 | *obufp++ = 'd'; | |
11116 | else | |
11117 | *obufp++ = 'l'; | |
11118 | } | |
11119 | else if (sizeflag & DFLAG) | |
11120 | *obufp++ = 'w'; | |
11121 | else | |
11122 | *obufp++ = 'b'; | |
11123 | if (!(rex & REX_W)) | |
11124 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11125 | } | |
11126 | else if (l == 1) | |
11127 | { | |
11128 | if (!need_vex) | |
11129 | abort (); | |
11130 | if (last[0] == 'X') | |
11131 | *obufp++ = vex.w ? 'd': 's'; | |
11132 | else if (last[0] == 'B') | |
11133 | *obufp++ = vex.w ? 'w': 'b'; | |
11134 | else | |
11135 | abort (); | |
11136 | } | |
11137 | else | |
11138 | abort (); | |
11139 | break; | |
041bd2e0 | 11140 | case 'X': |
21a3faeb JB |
11141 | if (l != 0) |
11142 | abort (); | |
bf926894 JB |
11143 | if (need_vex |
11144 | ? vex.prefix == DATA_PREFIX_OPCODE | |
11145 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 11146 | { |
bf926894 JB |
11147 | *obufp++ = 'd'; |
11148 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 11149 | } |
041bd2e0 | 11150 | else |
bf926894 | 11151 | *obufp++ = 's'; |
041bd2e0 | 11152 | break; |
76f227a5 | 11153 | case 'Y': |
21a3faeb | 11154 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 11155 | { |
c0f3af97 L |
11156 | if (!need_vex) |
11157 | abort (); | |
11158 | if (intel_syntax | |
04d824a4 | 11159 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
11160 | break; |
11161 | switch (vex.length) | |
11162 | { | |
11163 | case 128: | |
11164 | *obufp++ = 'x'; | |
11165 | break; | |
11166 | case 256: | |
11167 | *obufp++ = 'y'; | |
11168 | break; | |
04d824a4 JB |
11169 | case 512: |
11170 | if (!vex.evex) | |
c0f3af97 | 11171 | default: |
04d824a4 | 11172 | abort (); |
c0f3af97 | 11173 | } |
76f227a5 | 11174 | } |
21a3faeb JB |
11175 | else |
11176 | abort (); | |
76f227a5 | 11177 | break; |
78467458 JB |
11178 | case 'Z': |
11179 | if (l == 0) | |
11180 | { | |
11181 | /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */ | |
11182 | modrm.mod = 3; | |
11183 | if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS)) | |
11184 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; | |
11185 | } | |
11186 | else if (l == 1 && last[0] == 'X') | |
11187 | { | |
11188 | if (!need_vex || !vex.evex) | |
11189 | abort (); | |
11190 | if (intel_syntax | |
11191 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
11192 | break; | |
11193 | switch (vex.length) | |
11194 | { | |
11195 | case 128: | |
11196 | *obufp++ = 'x'; | |
11197 | break; | |
11198 | case 256: | |
11199 | *obufp++ = 'y'; | |
11200 | break; | |
11201 | case 512: | |
11202 | *obufp++ = 'z'; | |
11203 | break; | |
11204 | default: | |
11205 | abort (); | |
11206 | } | |
11207 | } | |
11208 | else | |
11209 | abort (); | |
11210 | break; | |
a72d2af2 L |
11211 | case '^': |
11212 | if (intel_syntax) | |
11213 | break; | |
5990e377 JB |
11214 | if (isa64 == intel64 && (rex & REX_W)) |
11215 | { | |
11216 | USED_REX (REX_W); | |
11217 | *obufp++ = 'q'; | |
11218 | break; | |
11219 | } | |
a72d2af2 L |
11220 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
11221 | { | |
11222 | if (sizeflag & DFLAG) | |
11223 | *obufp++ = 'l'; | |
11224 | else | |
11225 | *obufp++ = 'w'; | |
11226 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11227 | } | |
11228 | break; | |
252b5132 | 11229 | } |
21a3faeb JB |
11230 | |
11231 | if (len == l) | |
11232 | len = l = 0; | |
252b5132 RH |
11233 | } |
11234 | *obufp = 0; | |
ea397f5b | 11235 | mnemonicendp = obufp; |
6439fc28 | 11236 | return 0; |
252b5132 RH |
11237 | } |
11238 | ||
11239 | static void | |
26ca5450 | 11240 | oappend (const char *s) |
252b5132 | 11241 | { |
ea397f5b | 11242 | obufp = stpcpy (obufp, s); |
252b5132 RH |
11243 | } |
11244 | ||
11245 | static void | |
26ca5450 | 11246 | append_seg (void) |
252b5132 | 11247 | { |
285ca992 L |
11248 | /* Only print the active segment register. */ |
11249 | if (!active_seg_prefix) | |
11250 | return; | |
11251 | ||
11252 | used_prefixes |= active_seg_prefix; | |
11253 | switch (active_seg_prefix) | |
7d421014 | 11254 | { |
285ca992 | 11255 | case PREFIX_CS: |
9ce09ba2 | 11256 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
11257 | break; |
11258 | case PREFIX_DS: | |
9ce09ba2 | 11259 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
11260 | break; |
11261 | case PREFIX_SS: | |
9ce09ba2 | 11262 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
11263 | break; |
11264 | case PREFIX_ES: | |
9ce09ba2 | 11265 | oappend_maybe_intel ("%es:"); |
285ca992 L |
11266 | break; |
11267 | case PREFIX_FS: | |
9ce09ba2 | 11268 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
11269 | break; |
11270 | case PREFIX_GS: | |
9ce09ba2 | 11271 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
11272 | break; |
11273 | default: | |
11274 | break; | |
7d421014 | 11275 | } |
252b5132 RH |
11276 | } |
11277 | ||
11278 | static void | |
26ca5450 | 11279 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
11280 | { |
11281 | if (!intel_syntax) | |
11282 | oappend ("*"); | |
11283 | OP_E (bytemode, sizeflag); | |
11284 | } | |
11285 | ||
52b15da3 | 11286 | static void |
26ca5450 | 11287 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 11288 | { |
cb712a9e | 11289 | if (address_mode == mode_64bit) |
52b15da3 JH |
11290 | { |
11291 | if (hex) | |
11292 | { | |
11293 | char tmp[30]; | |
11294 | int i; | |
11295 | buf[0] = '0'; | |
11296 | buf[1] = 'x'; | |
11297 | sprintf_vma (tmp, disp); | |
6608db57 | 11298 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
11299 | strcpy (buf + 2, tmp + i); |
11300 | } | |
11301 | else | |
11302 | { | |
11303 | bfd_signed_vma v = disp; | |
11304 | char tmp[30]; | |
11305 | int i; | |
11306 | if (v < 0) | |
11307 | { | |
11308 | *(buf++) = '-'; | |
11309 | v = -disp; | |
6608db57 | 11310 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
11311 | if (v < 0) |
11312 | { | |
11313 | strcpy (buf, "9223372036854775808"); | |
11314 | return; | |
11315 | } | |
11316 | } | |
11317 | if (!v) | |
11318 | { | |
11319 | strcpy (buf, "0"); | |
11320 | return; | |
11321 | } | |
11322 | ||
11323 | i = 0; | |
11324 | tmp[29] = 0; | |
11325 | while (v) | |
11326 | { | |
6608db57 | 11327 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
11328 | v /= 10; |
11329 | i++; | |
11330 | } | |
11331 | strcpy (buf, tmp + 29 - i); | |
11332 | } | |
11333 | } | |
11334 | else | |
11335 | { | |
11336 | if (hex) | |
11337 | sprintf (buf, "0x%x", (unsigned int) disp); | |
11338 | else | |
11339 | sprintf (buf, "%d", (int) disp); | |
11340 | } | |
11341 | } | |
11342 | ||
5d669648 L |
11343 | /* Put DISP in BUF as signed hex number. */ |
11344 | ||
11345 | static void | |
11346 | print_displacement (char *buf, bfd_vma disp) | |
11347 | { | |
11348 | bfd_signed_vma val = disp; | |
11349 | char tmp[30]; | |
11350 | int i, j = 0; | |
11351 | ||
11352 | if (val < 0) | |
11353 | { | |
11354 | buf[j++] = '-'; | |
11355 | val = -disp; | |
11356 | ||
11357 | /* Check for possible overflow. */ | |
11358 | if (val < 0) | |
11359 | { | |
11360 | switch (address_mode) | |
11361 | { | |
11362 | case mode_64bit: | |
11363 | strcpy (buf + j, "0x8000000000000000"); | |
11364 | break; | |
11365 | case mode_32bit: | |
11366 | strcpy (buf + j, "0x80000000"); | |
11367 | break; | |
11368 | case mode_16bit: | |
11369 | strcpy (buf + j, "0x8000"); | |
11370 | break; | |
11371 | } | |
11372 | return; | |
11373 | } | |
11374 | } | |
11375 | ||
11376 | buf[j++] = '0'; | |
11377 | buf[j++] = 'x'; | |
11378 | ||
0af1713e | 11379 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
11380 | for (i = 0; tmp[i] == '0'; i++) |
11381 | continue; | |
11382 | if (tmp[i] == '\0') | |
11383 | i--; | |
11384 | strcpy (buf + j, tmp + i); | |
11385 | } | |
11386 | ||
3f31e633 JB |
11387 | static void |
11388 | intel_operand_size (int bytemode, int sizeflag) | |
11389 | { | |
43234a1e L |
11390 | if (vex.evex |
11391 | && vex.b | |
11392 | && (bytemode == x_mode | |
11393 | || bytemode == evex_half_bcst_xmmq_mode)) | |
11394 | { | |
11395 | if (vex.w) | |
11396 | oappend ("QWORD PTR "); | |
11397 | else | |
11398 | oappend ("DWORD PTR "); | |
11399 | return; | |
11400 | } | |
3f31e633 JB |
11401 | switch (bytemode) |
11402 | { | |
11403 | case b_mode: | |
b6169b20 | 11404 | case b_swap_mode: |
42903f7f | 11405 | case dqb_mode: |
1ba585e8 | 11406 | case db_mode: |
3f31e633 JB |
11407 | oappend ("BYTE PTR "); |
11408 | break; | |
11409 | case w_mode: | |
1ba585e8 | 11410 | case dw_mode: |
3f31e633 JB |
11411 | case dqw_mode: |
11412 | oappend ("WORD PTR "); | |
11413 | break; | |
07f5af7d L |
11414 | case indir_v_mode: |
11415 | if (address_mode == mode_64bit && isa64 == intel64) | |
11416 | { | |
11417 | oappend ("QWORD PTR "); | |
11418 | break; | |
11419 | } | |
1a0670f3 | 11420 | /* Fall through. */ |
1a114b12 | 11421 | case stack_v_mode: |
7bb15c6f | 11422 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
11423 | { |
11424 | oappend ("QWORD PTR "); | |
3f31e633 JB |
11425 | break; |
11426 | } | |
1a0670f3 | 11427 | /* Fall through. */ |
3f31e633 | 11428 | case v_mode: |
b6169b20 | 11429 | case v_swap_mode: |
3f31e633 | 11430 | case dq_mode: |
161a04f6 L |
11431 | USED_REX (REX_W); |
11432 | if (rex & REX_W) | |
3f31e633 | 11433 | oappend ("QWORD PTR "); |
035e7389 JB |
11434 | else if (bytemode == dq_mode) |
11435 | oappend ("DWORD PTR "); | |
3f31e633 | 11436 | else |
f16cd0d5 | 11437 | { |
035e7389 | 11438 | if (sizeflag & DFLAG) |
f16cd0d5 L |
11439 | oappend ("DWORD PTR "); |
11440 | else | |
11441 | oappend ("WORD PTR "); | |
11442 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11443 | } | |
3f31e633 | 11444 | break; |
52fd6d94 | 11445 | case z_mode: |
161a04f6 | 11446 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
11447 | *obufp++ = 'D'; |
11448 | oappend ("WORD PTR "); | |
161a04f6 | 11449 | if (!(rex & REX_W)) |
52fd6d94 JB |
11450 | used_prefixes |= (prefixes & PREFIX_DATA); |
11451 | break; | |
34b772a6 JB |
11452 | case a_mode: |
11453 | if (sizeflag & DFLAG) | |
11454 | oappend ("QWORD PTR "); | |
11455 | else | |
11456 | oappend ("DWORD PTR "); | |
11457 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11458 | break; | |
bc31405e L |
11459 | case movsxd_mode: |
11460 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
11461 | oappend ("WORD PTR "); | |
11462 | else | |
11463 | oappend ("DWORD PTR "); | |
11464 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11465 | break; | |
3f31e633 | 11466 | case d_mode: |
fa99fab2 | 11467 | case d_swap_mode: |
42903f7f | 11468 | case dqd_mode: |
3f31e633 JB |
11469 | oappend ("DWORD PTR "); |
11470 | break; | |
11471 | case q_mode: | |
b6169b20 | 11472 | case q_swap_mode: |
3f31e633 JB |
11473 | oappend ("QWORD PTR "); |
11474 | break; | |
11475 | case m_mode: | |
cb712a9e | 11476 | if (address_mode == mode_64bit) |
3f31e633 JB |
11477 | oappend ("QWORD PTR "); |
11478 | else | |
11479 | oappend ("DWORD PTR "); | |
11480 | break; | |
11481 | case f_mode: | |
11482 | if (sizeflag & DFLAG) | |
11483 | oappend ("FWORD PTR "); | |
11484 | else | |
11485 | oappend ("DWORD PTR "); | |
11486 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11487 | break; | |
11488 | case t_mode: | |
11489 | oappend ("TBYTE PTR "); | |
11490 | break; | |
11491 | case x_mode: | |
b6169b20 | 11492 | case x_swap_mode: |
43234a1e L |
11493 | case evex_x_gscat_mode: |
11494 | case evex_x_nobcst_mode: | |
4726e9a4 | 11495 | case bw_unit_mode: |
c0f3af97 L |
11496 | if (need_vex) |
11497 | { | |
11498 | switch (vex.length) | |
11499 | { | |
11500 | case 128: | |
11501 | oappend ("XMMWORD PTR "); | |
11502 | break; | |
11503 | case 256: | |
11504 | oappend ("YMMWORD PTR "); | |
11505 | break; | |
43234a1e L |
11506 | case 512: |
11507 | oappend ("ZMMWORD PTR "); | |
11508 | break; | |
c0f3af97 L |
11509 | default: |
11510 | abort (); | |
11511 | } | |
11512 | } | |
11513 | else | |
11514 | oappend ("XMMWORD PTR "); | |
11515 | break; | |
11516 | case xmm_mode: | |
3f31e633 JB |
11517 | oappend ("XMMWORD PTR "); |
11518 | break; | |
43234a1e L |
11519 | case ymm_mode: |
11520 | oappend ("YMMWORD PTR "); | |
11521 | break; | |
c0f3af97 | 11522 | case xmmq_mode: |
43234a1e | 11523 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
11524 | if (!need_vex) |
11525 | abort (); | |
11526 | ||
11527 | switch (vex.length) | |
11528 | { | |
11529 | case 128: | |
11530 | oappend ("QWORD PTR "); | |
11531 | break; | |
11532 | case 256: | |
11533 | oappend ("XMMWORD PTR "); | |
11534 | break; | |
43234a1e L |
11535 | case 512: |
11536 | oappend ("YMMWORD PTR "); | |
11537 | break; | |
c0f3af97 L |
11538 | default: |
11539 | abort (); | |
11540 | } | |
11541 | break; | |
6c30d220 L |
11542 | case xmm_mb_mode: |
11543 | if (!need_vex) | |
11544 | abort (); | |
11545 | ||
11546 | switch (vex.length) | |
11547 | { | |
11548 | case 128: | |
11549 | case 256: | |
43234a1e | 11550 | case 512: |
6c30d220 L |
11551 | oappend ("BYTE PTR "); |
11552 | break; | |
11553 | default: | |
11554 | abort (); | |
11555 | } | |
11556 | break; | |
11557 | case xmm_mw_mode: | |
11558 | if (!need_vex) | |
11559 | abort (); | |
11560 | ||
11561 | switch (vex.length) | |
11562 | { | |
11563 | case 128: | |
11564 | case 256: | |
43234a1e | 11565 | case 512: |
6c30d220 L |
11566 | oappend ("WORD PTR "); |
11567 | break; | |
11568 | default: | |
11569 | abort (); | |
11570 | } | |
11571 | break; | |
11572 | case xmm_md_mode: | |
11573 | if (!need_vex) | |
11574 | abort (); | |
11575 | ||
11576 | switch (vex.length) | |
11577 | { | |
11578 | case 128: | |
11579 | case 256: | |
43234a1e | 11580 | case 512: |
6c30d220 L |
11581 | oappend ("DWORD PTR "); |
11582 | break; | |
11583 | default: | |
11584 | abort (); | |
11585 | } | |
11586 | break; | |
11587 | case xmm_mq_mode: | |
11588 | if (!need_vex) | |
11589 | abort (); | |
11590 | ||
11591 | switch (vex.length) | |
11592 | { | |
11593 | case 128: | |
11594 | case 256: | |
43234a1e | 11595 | case 512: |
6c30d220 L |
11596 | oappend ("QWORD PTR "); |
11597 | break; | |
11598 | default: | |
11599 | abort (); | |
11600 | } | |
11601 | break; | |
11602 | case xmmdw_mode: | |
11603 | if (!need_vex) | |
11604 | abort (); | |
11605 | ||
11606 | switch (vex.length) | |
11607 | { | |
11608 | case 128: | |
11609 | oappend ("WORD PTR "); | |
11610 | break; | |
11611 | case 256: | |
11612 | oappend ("DWORD PTR "); | |
11613 | break; | |
43234a1e L |
11614 | case 512: |
11615 | oappend ("QWORD PTR "); | |
11616 | break; | |
6c30d220 L |
11617 | default: |
11618 | abort (); | |
11619 | } | |
11620 | break; | |
11621 | case xmmqd_mode: | |
11622 | if (!need_vex) | |
11623 | abort (); | |
11624 | ||
11625 | switch (vex.length) | |
11626 | { | |
11627 | case 128: | |
11628 | oappend ("DWORD PTR "); | |
11629 | break; | |
11630 | case 256: | |
11631 | oappend ("QWORD PTR "); | |
11632 | break; | |
43234a1e L |
11633 | case 512: |
11634 | oappend ("XMMWORD PTR "); | |
11635 | break; | |
6c30d220 L |
11636 | default: |
11637 | abort (); | |
11638 | } | |
11639 | break; | |
c0f3af97 L |
11640 | case ymmq_mode: |
11641 | if (!need_vex) | |
11642 | abort (); | |
11643 | ||
11644 | switch (vex.length) | |
11645 | { | |
11646 | case 128: | |
11647 | oappend ("QWORD PTR "); | |
11648 | break; | |
11649 | case 256: | |
11650 | oappend ("YMMWORD PTR "); | |
11651 | break; | |
43234a1e L |
11652 | case 512: |
11653 | oappend ("ZMMWORD PTR "); | |
11654 | break; | |
c0f3af97 L |
11655 | default: |
11656 | abort (); | |
11657 | } | |
11658 | break; | |
6c30d220 L |
11659 | case ymmxmm_mode: |
11660 | if (!need_vex) | |
11661 | abort (); | |
11662 | ||
11663 | switch (vex.length) | |
11664 | { | |
11665 | case 128: | |
11666 | case 256: | |
11667 | oappend ("XMMWORD PTR "); | |
11668 | break; | |
11669 | default: | |
11670 | abort (); | |
11671 | } | |
11672 | break; | |
fb9c77c7 L |
11673 | case o_mode: |
11674 | oappend ("OWORD PTR "); | |
11675 | break; | |
1c480963 | 11676 | case vex_scalar_w_dq_mode: |
0bfee649 L |
11677 | if (!need_vex) |
11678 | abort (); | |
11679 | ||
11680 | if (vex.w) | |
11681 | oappend ("QWORD PTR "); | |
11682 | else | |
11683 | oappend ("DWORD PTR "); | |
11684 | break; | |
43234a1e L |
11685 | case vex_vsib_d_w_dq_mode: |
11686 | case vex_vsib_q_w_dq_mode: | |
11687 | if (!need_vex) | |
11688 | abort (); | |
11689 | ||
11690 | if (!vex.evex) | |
11691 | { | |
11692 | if (vex.w) | |
11693 | oappend ("QWORD PTR "); | |
11694 | else | |
11695 | oappend ("DWORD PTR "); | |
11696 | } | |
11697 | else | |
11698 | { | |
b28d1bda IT |
11699 | switch (vex.length) |
11700 | { | |
11701 | case 128: | |
11702 | oappend ("XMMWORD PTR "); | |
11703 | break; | |
11704 | case 256: | |
11705 | oappend ("YMMWORD PTR "); | |
11706 | break; | |
11707 | case 512: | |
11708 | oappend ("ZMMWORD PTR "); | |
11709 | break; | |
11710 | default: | |
11711 | abort (); | |
11712 | } | |
43234a1e L |
11713 | } |
11714 | break; | |
5fc35d96 IT |
11715 | case vex_vsib_q_w_d_mode: |
11716 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 11717 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
11718 | abort (); |
11719 | ||
b28d1bda IT |
11720 | switch (vex.length) |
11721 | { | |
11722 | case 128: | |
11723 | oappend ("QWORD PTR "); | |
11724 | break; | |
11725 | case 256: | |
11726 | oappend ("XMMWORD PTR "); | |
11727 | break; | |
11728 | case 512: | |
11729 | oappend ("YMMWORD PTR "); | |
11730 | break; | |
11731 | default: | |
11732 | abort (); | |
11733 | } | |
5fc35d96 IT |
11734 | |
11735 | break; | |
1ba585e8 IT |
11736 | case mask_bd_mode: |
11737 | if (!need_vex || vex.length != 128) | |
11738 | abort (); | |
11739 | if (vex.w) | |
11740 | oappend ("DWORD PTR "); | |
11741 | else | |
11742 | oappend ("BYTE PTR "); | |
11743 | break; | |
43234a1e L |
11744 | case mask_mode: |
11745 | if (!need_vex) | |
11746 | abort (); | |
1ba585e8 IT |
11747 | if (vex.w) |
11748 | oappend ("QWORD PTR "); | |
11749 | else | |
11750 | oappend ("WORD PTR "); | |
43234a1e | 11751 | break; |
6c75cc62 | 11752 | case v_bnd_mode: |
d276ec69 | 11753 | case v_bndmk_mode: |
3f31e633 JB |
11754 | default: |
11755 | break; | |
11756 | } | |
11757 | } | |
11758 | ||
252b5132 | 11759 | static void |
c0f3af97 | 11760 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 11761 | { |
c0f3af97 L |
11762 | int reg = modrm.rm; |
11763 | const char **names; | |
252b5132 | 11764 | |
c0f3af97 L |
11765 | USED_REX (REX_B); |
11766 | if ((rex & REX_B)) | |
11767 | reg += 8; | |
252b5132 | 11768 | |
b6169b20 | 11769 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 11770 | && (bytemode == b_swap_mode |
9f79e886 | 11771 | || bytemode == bnd_swap_mode |
60227d64 | 11772 | || bytemode == v_swap_mode)) |
b6169b20 L |
11773 | swap_operand (); |
11774 | ||
c0f3af97 | 11775 | switch (bytemode) |
252b5132 | 11776 | { |
c0f3af97 | 11777 | case b_mode: |
b6169b20 | 11778 | case b_swap_mode: |
e184e611 JB |
11779 | if (reg & 4) |
11780 | USED_REX (0); | |
c0f3af97 L |
11781 | if (rex) |
11782 | names = names8rex; | |
11783 | else | |
11784 | names = names8; | |
11785 | break; | |
11786 | case w_mode: | |
11787 | names = names16; | |
11788 | break; | |
11789 | case d_mode: | |
1ba585e8 IT |
11790 | case dw_mode: |
11791 | case db_mode: | |
c0f3af97 L |
11792 | names = names32; |
11793 | break; | |
11794 | case q_mode: | |
11795 | names = names64; | |
11796 | break; | |
11797 | case m_mode: | |
6c75cc62 | 11798 | case v_bnd_mode: |
c0f3af97 L |
11799 | names = address_mode == mode_64bit ? names64 : names32; |
11800 | break; | |
7e8b059b | 11801 | case bnd_mode: |
9f79e886 | 11802 | case bnd_swap_mode: |
0d96e4df L |
11803 | if (reg > 0x3) |
11804 | { | |
11805 | oappend ("(bad)"); | |
11806 | return; | |
11807 | } | |
7e8b059b L |
11808 | names = names_bnd; |
11809 | break; | |
07f5af7d L |
11810 | case indir_v_mode: |
11811 | if (address_mode == mode_64bit && isa64 == intel64) | |
11812 | { | |
11813 | names = names64; | |
11814 | break; | |
11815 | } | |
1a0670f3 | 11816 | /* Fall through. */ |
c0f3af97 | 11817 | case stack_v_mode: |
7bb15c6f | 11818 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 11819 | { |
c0f3af97 | 11820 | names = names64; |
252b5132 | 11821 | break; |
252b5132 | 11822 | } |
c0f3af97 | 11823 | bytemode = v_mode; |
1a0670f3 | 11824 | /* Fall through. */ |
c0f3af97 | 11825 | case v_mode: |
b6169b20 | 11826 | case v_swap_mode: |
c0f3af97 L |
11827 | case dq_mode: |
11828 | case dqb_mode: | |
11829 | case dqd_mode: | |
11830 | case dqw_mode: | |
11831 | USED_REX (REX_W); | |
11832 | if (rex & REX_W) | |
11833 | names = names64; | |
035e7389 JB |
11834 | else if (bytemode != v_mode && bytemode != v_swap_mode) |
11835 | names = names32; | |
c0f3af97 | 11836 | else |
f16cd0d5 | 11837 | { |
035e7389 | 11838 | if (sizeflag & DFLAG) |
f16cd0d5 L |
11839 | names = names32; |
11840 | else | |
11841 | names = names16; | |
11842 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11843 | } | |
c0f3af97 | 11844 | break; |
bc31405e L |
11845 | case movsxd_mode: |
11846 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
11847 | names = names16; | |
11848 | else | |
11849 | names = names32; | |
11850 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11851 | break; | |
de89d0a3 IT |
11852 | case va_mode: |
11853 | names = (address_mode == mode_64bit | |
11854 | ? names64 : names32); | |
11855 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
11856 | names = (address_mode == mode_16bit |
11857 | ? names16 : names); | |
de89d0a3 IT |
11858 | else |
11859 | { | |
11860 | /* Remove "addr16/addr32". */ | |
11861 | all_prefixes[last_addr_prefix] = 0; | |
11862 | names = (address_mode != mode_32bit | |
11863 | ? names32 : names16); | |
11864 | used_prefixes |= PREFIX_ADDR; | |
11865 | } | |
11866 | break; | |
1ba585e8 | 11867 | case mask_bd_mode: |
43234a1e | 11868 | case mask_mode: |
9889cbb1 L |
11869 | if (reg > 0x7) |
11870 | { | |
11871 | oappend ("(bad)"); | |
11872 | return; | |
11873 | } | |
43234a1e L |
11874 | names = names_mask; |
11875 | break; | |
c0f3af97 L |
11876 | case 0: |
11877 | return; | |
11878 | default: | |
11879 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
11880 | return; |
11881 | } | |
c0f3af97 L |
11882 | oappend (names[reg]); |
11883 | } | |
11884 | ||
11885 | static void | |
c1e679ec | 11886 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
11887 | { |
11888 | bfd_vma disp = 0; | |
11889 | int add = (rex & REX_B) ? 8 : 0; | |
11890 | int riprel = 0; | |
43234a1e L |
11891 | int shift; |
11892 | ||
11893 | if (vex.evex) | |
11894 | { | |
11895 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
11896 | if (vex.b | |
11897 | && bytemode != x_mode | |
90a915bf | 11898 | && bytemode != xmmq_mode |
43234a1e L |
11899 | && bytemode != evex_half_bcst_xmmq_mode) |
11900 | { | |
11901 | BadOp (); | |
11902 | return; | |
11903 | } | |
11904 | switch (bytemode) | |
11905 | { | |
1ba585e8 IT |
11906 | case dqw_mode: |
11907 | case dw_mode: | |
059edf8b | 11908 | case xmm_mw_mode: |
1ba585e8 IT |
11909 | shift = 1; |
11910 | break; | |
11911 | case dqb_mode: | |
11912 | case db_mode: | |
059edf8b | 11913 | case xmm_mb_mode: |
1ba585e8 IT |
11914 | shift = 0; |
11915 | break; | |
b50c9f31 JB |
11916 | case dq_mode: |
11917 | if (address_mode != mode_64bit) | |
11918 | { | |
059edf8b JB |
11919 | case dqd_mode: |
11920 | case xmm_md_mode: | |
11921 | case d_mode: | |
11922 | case d_swap_mode: | |
b50c9f31 JB |
11923 | shift = 2; |
11924 | break; | |
11925 | } | |
11926 | /* fall through */ | |
4102be5c | 11927 | case vex_scalar_w_dq_mode: |
43234a1e | 11928 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 11929 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 11930 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 11931 | case vex_vsib_q_w_d_mode: |
43234a1e | 11932 | case evex_x_gscat_mode: |
43234a1e L |
11933 | shift = vex.w ? 3 : 2; |
11934 | break; | |
43234a1e L |
11935 | case x_mode: |
11936 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 11937 | case xmmq_mode: |
43234a1e L |
11938 | if (vex.b) |
11939 | { | |
11940 | shift = vex.w ? 3 : 2; | |
11941 | break; | |
11942 | } | |
1a0670f3 | 11943 | /* Fall through. */ |
43234a1e L |
11944 | case xmmqd_mode: |
11945 | case xmmdw_mode: | |
43234a1e L |
11946 | case ymmq_mode: |
11947 | case evex_x_nobcst_mode: | |
11948 | case x_swap_mode: | |
11949 | switch (vex.length) | |
11950 | { | |
11951 | case 128: | |
11952 | shift = 4; | |
11953 | break; | |
11954 | case 256: | |
11955 | shift = 5; | |
11956 | break; | |
11957 | case 512: | |
11958 | shift = 6; | |
11959 | break; | |
11960 | default: | |
11961 | abort (); | |
11962 | } | |
059edf8b JB |
11963 | /* Make necessary corrections to shift for modes that need it. */ |
11964 | if (bytemode == xmmq_mode | |
11965 | || bytemode == evex_half_bcst_xmmq_mode | |
11966 | || (bytemode == ymmq_mode && vex.length == 128)) | |
11967 | shift -= 1; | |
11968 | else if (bytemode == xmmqd_mode) | |
11969 | shift -= 2; | |
11970 | else if (bytemode == xmmdw_mode) | |
11971 | shift -= 3; | |
43234a1e L |
11972 | break; |
11973 | case ymm_mode: | |
11974 | shift = 5; | |
11975 | break; | |
11976 | case xmm_mode: | |
11977 | shift = 4; | |
11978 | break; | |
11979 | case xmm_mq_mode: | |
11980 | case q_mode: | |
43234a1e | 11981 | case q_swap_mode: |
43234a1e L |
11982 | shift = 3; |
11983 | break; | |
4726e9a4 JB |
11984 | case bw_unit_mode: |
11985 | shift = vex.w ? 1 : 0; | |
11986 | break; | |
43234a1e L |
11987 | default: |
11988 | abort (); | |
11989 | } | |
43234a1e L |
11990 | } |
11991 | else | |
11992 | shift = 0; | |
252b5132 | 11993 | |
c0f3af97 | 11994 | USED_REX (REX_B); |
3f31e633 JB |
11995 | if (intel_syntax) |
11996 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
11997 | append_seg (); |
11998 | ||
5d669648 | 11999 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 12000 | { |
5d669648 L |
12001 | /* 32/64 bit address mode */ |
12002 | int havedisp; | |
252b5132 RH |
12003 | int havesib; |
12004 | int havebase; | |
0f7da397 | 12005 | int haveindex; |
20afcfb7 | 12006 | int needindex; |
1bc60e56 | 12007 | int needaddr32; |
82c18208 | 12008 | int base, rbase; |
91d6fa6a | 12009 | int vindex = 0; |
252b5132 | 12010 | int scale = 0; |
7e8b059b L |
12011 | int addr32flag = !((sizeflag & AFLAG) |
12012 | || bytemode == v_bnd_mode | |
d276ec69 | 12013 | || bytemode == v_bndmk_mode |
9f79e886 JB |
12014 | || bytemode == bnd_mode |
12015 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
12016 | const char **indexes64 = names64; |
12017 | const char **indexes32 = names32; | |
252b5132 RH |
12018 | |
12019 | havesib = 0; | |
12020 | havebase = 1; | |
0f7da397 | 12021 | haveindex = 0; |
7967e09e | 12022 | base = modrm.rm; |
252b5132 RH |
12023 | |
12024 | if (base == 4) | |
12025 | { | |
12026 | havesib = 1; | |
dfc8cf43 | 12027 | vindex = sib.index; |
161a04f6 L |
12028 | USED_REX (REX_X); |
12029 | if (rex & REX_X) | |
91d6fa6a | 12030 | vindex += 8; |
6c30d220 L |
12031 | switch (bytemode) |
12032 | { | |
12033 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 12034 | case vex_vsib_d_w_d_mode: |
6c30d220 | 12035 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 12036 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
12037 | if (!need_vex) |
12038 | abort (); | |
43234a1e L |
12039 | if (vex.evex) |
12040 | { | |
12041 | if (!vex.v) | |
12042 | vindex += 16; | |
12043 | } | |
6c30d220 L |
12044 | |
12045 | haveindex = 1; | |
12046 | switch (vex.length) | |
12047 | { | |
12048 | case 128: | |
7bb15c6f | 12049 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
12050 | break; |
12051 | case 256: | |
5fc35d96 IT |
12052 | if (!vex.w |
12053 | || bytemode == vex_vsib_q_w_dq_mode | |
12054 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 12055 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 12056 | else |
7bb15c6f | 12057 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 12058 | break; |
43234a1e | 12059 | case 512: |
5fc35d96 IT |
12060 | if (!vex.w |
12061 | || bytemode == vex_vsib_q_w_dq_mode | |
12062 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
12063 | indexes64 = indexes32 = names_zmm; |
12064 | else | |
12065 | indexes64 = indexes32 = names_ymm; | |
12066 | break; | |
6c30d220 L |
12067 | default: |
12068 | abort (); | |
12069 | } | |
12070 | break; | |
12071 | default: | |
12072 | haveindex = vindex != 4; | |
12073 | break; | |
12074 | } | |
12075 | scale = sib.scale; | |
12076 | base = sib.base; | |
252b5132 RH |
12077 | codep++; |
12078 | } | |
260cd341 LC |
12079 | else |
12080 | { | |
12081 | /* mandatory non-vector SIB must have sib */ | |
12082 | if (bytemode == vex_sibmem_mode) | |
12083 | { | |
12084 | oappend ("(bad)"); | |
12085 | return; | |
12086 | } | |
12087 | } | |
82c18208 | 12088 | rbase = base + add; |
252b5132 | 12089 | |
7967e09e | 12090 | switch (modrm.mod) |
252b5132 RH |
12091 | { |
12092 | case 0: | |
82c18208 | 12093 | if (base == 5) |
252b5132 RH |
12094 | { |
12095 | havebase = 0; | |
cb712a9e | 12096 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
12097 | riprel = 1; |
12098 | disp = get32s (); | |
d276ec69 JB |
12099 | if (riprel && bytemode == v_bndmk_mode) |
12100 | { | |
12101 | oappend ("(bad)"); | |
12102 | return; | |
12103 | } | |
252b5132 RH |
12104 | } |
12105 | break; | |
12106 | case 1: | |
12107 | FETCH_DATA (the_info, codep + 1); | |
12108 | disp = *codep++; | |
12109 | if ((disp & 0x80) != 0) | |
12110 | disp -= 0x100; | |
43234a1e L |
12111 | if (vex.evex && shift > 0) |
12112 | disp <<= shift; | |
252b5132 RH |
12113 | break; |
12114 | case 2: | |
52b15da3 | 12115 | disp = get32s (); |
252b5132 RH |
12116 | break; |
12117 | } | |
12118 | ||
1bc60e56 L |
12119 | needindex = 0; |
12120 | needaddr32 = 0; | |
12121 | if (havesib | |
12122 | && !havebase | |
12123 | && !haveindex | |
12124 | && address_mode != mode_16bit) | |
12125 | { | |
12126 | if (address_mode == mode_64bit) | |
12127 | { | |
8e58ef80 L |
12128 | if (addr32flag) |
12129 | { | |
12130 | /* Without base nor index registers, zero-extend the | |
12131 | lower 32-bit displacement to 64 bits. */ | |
12132 | disp = (unsigned int) disp; | |
bf4ba07c | 12133 | needindex = 1; |
8e58ef80 | 12134 | } |
1bc60e56 L |
12135 | needaddr32 = 1; |
12136 | } | |
12137 | else | |
12138 | { | |
12139 | /* In 32-bit mode, we need index register to tell [offset] | |
12140 | from [eiz*1 + offset]. */ | |
12141 | needindex = 1; | |
12142 | } | |
12143 | } | |
12144 | ||
20afcfb7 L |
12145 | havedisp = (havebase |
12146 | || needindex | |
12147 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 12148 | |
252b5132 | 12149 | if (!intel_syntax) |
82c18208 | 12150 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 12151 | { |
5d669648 L |
12152 | if (havedisp || riprel) |
12153 | print_displacement (scratchbuf, disp); | |
12154 | else | |
12155 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 12156 | oappend (scratchbuf); |
52b15da3 JH |
12157 | if (riprel) |
12158 | { | |
12159 | set_op (disp, 1); | |
28596323 | 12160 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 12161 | } |
db6eb5be | 12162 | } |
2da11e11 | 12163 | |
c1dc7af5 | 12164 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
12165 | && (address_mode != mode_64bit |
12166 | || ((bytemode != v_bnd_mode) | |
12167 | && (bytemode != v_bndmk_mode) | |
12168 | && (bytemode != bnd_mode) | |
12169 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
12170 | used_prefixes |= PREFIX_ADDR; |
12171 | ||
5d669648 | 12172 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 12173 | { |
252b5132 | 12174 | *obufp++ = open_char; |
52b15da3 | 12175 | if (intel_syntax && riprel) |
185b1163 L |
12176 | { |
12177 | set_op (disp, 1); | |
28596323 | 12178 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 12179 | } |
db6eb5be | 12180 | *obufp = '\0'; |
252b5132 | 12181 | if (havebase) |
7e8b059b | 12182 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 12183 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
12184 | if (havesib) |
12185 | { | |
db51cc60 L |
12186 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
12187 | print index to tell base + index from base. */ | |
12188 | if (scale != 0 | |
20afcfb7 | 12189 | || needindex |
db51cc60 L |
12190 | || haveindex |
12191 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 12192 | { |
9306ca4a | 12193 | if (!intel_syntax || havebase) |
db6eb5be | 12194 | { |
9306ca4a JB |
12195 | *obufp++ = separator_char; |
12196 | *obufp = '\0'; | |
db6eb5be | 12197 | } |
db51cc60 | 12198 | if (haveindex) |
7e8b059b | 12199 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 12200 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 12201 | else |
7e8b059b | 12202 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
12203 | ? index64 : index32); |
12204 | ||
db6eb5be AM |
12205 | *obufp++ = scale_char; |
12206 | *obufp = '\0'; | |
12207 | sprintf (scratchbuf, "%d", 1 << scale); | |
12208 | oappend (scratchbuf); | |
12209 | } | |
252b5132 | 12210 | } |
185b1163 | 12211 | if (intel_syntax |
82c18208 | 12212 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 12213 | { |
db51cc60 | 12214 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
12215 | { |
12216 | *obufp++ = '+'; | |
12217 | *obufp = '\0'; | |
12218 | } | |
05203043 | 12219 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
12220 | { |
12221 | *obufp++ = '-'; | |
12222 | *obufp = '\0'; | |
b4b39349 | 12223 | disp = -disp; |
3d456fa1 JB |
12224 | } |
12225 | ||
db51cc60 L |
12226 | if (havedisp) |
12227 | print_displacement (scratchbuf, disp); | |
12228 | else | |
12229 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
12230 | oappend (scratchbuf); |
12231 | } | |
252b5132 RH |
12232 | |
12233 | *obufp++ = close_char; | |
db6eb5be | 12234 | *obufp = '\0'; |
252b5132 RH |
12235 | } |
12236 | else if (intel_syntax) | |
db6eb5be | 12237 | { |
82c18208 | 12238 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 12239 | { |
285ca992 | 12240 | if (!active_seg_prefix) |
252b5132 | 12241 | { |
d708bcba | 12242 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
12243 | oappend (":"); |
12244 | } | |
52b15da3 | 12245 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
12246 | oappend (scratchbuf); |
12247 | } | |
12248 | } | |
252b5132 | 12249 | } |
a23b33b3 JB |
12250 | else if (bytemode == v_bnd_mode |
12251 | || bytemode == v_bndmk_mode | |
12252 | || bytemode == bnd_mode | |
12253 | || bytemode == bnd_swap_mode) | |
12254 | { | |
12255 | oappend ("(bad)"); | |
12256 | return; | |
12257 | } | |
252b5132 | 12258 | else |
f16cd0d5 L |
12259 | { |
12260 | /* 16 bit address mode */ | |
12261 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 12262 | switch (modrm.mod) |
252b5132 RH |
12263 | { |
12264 | case 0: | |
7967e09e | 12265 | if (modrm.rm == 6) |
252b5132 RH |
12266 | { |
12267 | disp = get16 (); | |
12268 | if ((disp & 0x8000) != 0) | |
12269 | disp -= 0x10000; | |
12270 | } | |
12271 | break; | |
12272 | case 1: | |
12273 | FETCH_DATA (the_info, codep + 1); | |
12274 | disp = *codep++; | |
12275 | if ((disp & 0x80) != 0) | |
12276 | disp -= 0x100; | |
65f3ed04 JB |
12277 | if (vex.evex && shift > 0) |
12278 | disp <<= shift; | |
252b5132 RH |
12279 | break; |
12280 | case 2: | |
12281 | disp = get16 (); | |
12282 | if ((disp & 0x8000) != 0) | |
12283 | disp -= 0x10000; | |
12284 | break; | |
12285 | } | |
12286 | ||
12287 | if (!intel_syntax) | |
7967e09e | 12288 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 12289 | { |
5d669648 | 12290 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
12291 | oappend (scratchbuf); |
12292 | } | |
252b5132 | 12293 | |
7967e09e | 12294 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
12295 | { |
12296 | *obufp++ = open_char; | |
db6eb5be | 12297 | *obufp = '\0'; |
7967e09e | 12298 | oappend (index16[modrm.rm]); |
5d669648 L |
12299 | if (intel_syntax |
12300 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 12301 | { |
5d669648 | 12302 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
12303 | { |
12304 | *obufp++ = '+'; | |
12305 | *obufp = '\0'; | |
12306 | } | |
7967e09e | 12307 | else if (modrm.mod != 1) |
3d456fa1 JB |
12308 | { |
12309 | *obufp++ = '-'; | |
12310 | *obufp = '\0'; | |
b4b39349 | 12311 | disp = -disp; |
3d456fa1 JB |
12312 | } |
12313 | ||
5d669648 | 12314 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
12315 | oappend (scratchbuf); |
12316 | } | |
12317 | ||
db6eb5be AM |
12318 | *obufp++ = close_char; |
12319 | *obufp = '\0'; | |
252b5132 | 12320 | } |
3d456fa1 JB |
12321 | else if (intel_syntax) |
12322 | { | |
285ca992 | 12323 | if (!active_seg_prefix) |
3d456fa1 JB |
12324 | { |
12325 | oappend (names_seg[ds_reg - es_reg]); | |
12326 | oappend (":"); | |
12327 | } | |
12328 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
12329 | oappend (scratchbuf); | |
12330 | } | |
252b5132 | 12331 | } |
43234a1e L |
12332 | if (vex.evex && vex.b |
12333 | && (bytemode == x_mode | |
90a915bf | 12334 | || bytemode == xmmq_mode |
43234a1e L |
12335 | || bytemode == evex_half_bcst_xmmq_mode)) |
12336 | { | |
90a915bf IT |
12337 | if (vex.w |
12338 | || bytemode == xmmq_mode | |
12339 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
12340 | { |
12341 | switch (vex.length) | |
12342 | { | |
12343 | case 128: | |
12344 | oappend ("{1to2}"); | |
12345 | break; | |
12346 | case 256: | |
12347 | oappend ("{1to4}"); | |
12348 | break; | |
12349 | case 512: | |
12350 | oappend ("{1to8}"); | |
12351 | break; | |
12352 | default: | |
12353 | abort (); | |
12354 | } | |
12355 | } | |
43234a1e | 12356 | else |
b28d1bda IT |
12357 | { |
12358 | switch (vex.length) | |
12359 | { | |
12360 | case 128: | |
12361 | oappend ("{1to4}"); | |
12362 | break; | |
12363 | case 256: | |
12364 | oappend ("{1to8}"); | |
12365 | break; | |
12366 | case 512: | |
12367 | oappend ("{1to16}"); | |
12368 | break; | |
12369 | default: | |
12370 | abort (); | |
12371 | } | |
12372 | } | |
43234a1e | 12373 | } |
252b5132 RH |
12374 | } |
12375 | ||
c0f3af97 | 12376 | static void |
8b3f93e7 | 12377 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
12378 | { |
12379 | /* Skip mod/rm byte. */ | |
12380 | MODRM_CHECK; | |
12381 | codep++; | |
12382 | ||
12383 | if (modrm.mod == 3) | |
12384 | OP_E_register (bytemode, sizeflag); | |
12385 | else | |
c1e679ec | 12386 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
12387 | } |
12388 | ||
252b5132 | 12389 | static void |
26ca5450 | 12390 | OP_G (int bytemode, int sizeflag) |
252b5132 | 12391 | { |
52b15da3 | 12392 | int add = 0; |
c0a30a9f | 12393 | const char **names; |
161a04f6 L |
12394 | USED_REX (REX_R); |
12395 | if (rex & REX_R) | |
52b15da3 | 12396 | add += 8; |
252b5132 RH |
12397 | switch (bytemode) |
12398 | { | |
12399 | case b_mode: | |
e184e611 JB |
12400 | if (modrm.reg & 4) |
12401 | USED_REX (0); | |
52b15da3 | 12402 | if (rex) |
7967e09e | 12403 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 12404 | else |
7967e09e | 12405 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
12406 | break; |
12407 | case w_mode: | |
7967e09e | 12408 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
12409 | break; |
12410 | case d_mode: | |
1ba585e8 IT |
12411 | case db_mode: |
12412 | case dw_mode: | |
7967e09e | 12413 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
12414 | break; |
12415 | case q_mode: | |
7967e09e | 12416 | oappend (names64[modrm.reg + add]); |
252b5132 | 12417 | break; |
7e8b059b | 12418 | case bnd_mode: |
0d96e4df L |
12419 | if (modrm.reg > 0x3) |
12420 | { | |
12421 | oappend ("(bad)"); | |
12422 | return; | |
12423 | } | |
7e8b059b L |
12424 | oappend (names_bnd[modrm.reg]); |
12425 | break; | |
252b5132 | 12426 | case v_mode: |
9306ca4a | 12427 | case dq_mode: |
42903f7f L |
12428 | case dqb_mode: |
12429 | case dqd_mode: | |
9306ca4a | 12430 | case dqw_mode: |
bc31405e | 12431 | case movsxd_mode: |
161a04f6 L |
12432 | USED_REX (REX_W); |
12433 | if (rex & REX_W) | |
7967e09e | 12434 | oappend (names64[modrm.reg + add]); |
035e7389 JB |
12435 | else if (bytemode != v_mode && bytemode != movsxd_mode) |
12436 | oappend (names32[modrm.reg + add]); | |
252b5132 | 12437 | else |
f16cd0d5 | 12438 | { |
035e7389 | 12439 | if (sizeflag & DFLAG) |
f16cd0d5 L |
12440 | oappend (names32[modrm.reg + add]); |
12441 | else | |
12442 | oappend (names16[modrm.reg + add]); | |
12443 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12444 | } | |
252b5132 | 12445 | break; |
c0a30a9f L |
12446 | case va_mode: |
12447 | names = (address_mode == mode_64bit | |
12448 | ? names64 : names32); | |
12449 | if (!(prefixes & PREFIX_ADDR)) | |
12450 | { | |
12451 | if (address_mode == mode_16bit) | |
12452 | names = names16; | |
12453 | } | |
12454 | else | |
12455 | { | |
12456 | /* Remove "addr16/addr32". */ | |
12457 | all_prefixes[last_addr_prefix] = 0; | |
12458 | names = (address_mode != mode_32bit | |
12459 | ? names32 : names16); | |
12460 | used_prefixes |= PREFIX_ADDR; | |
12461 | } | |
12462 | oappend (names[modrm.reg + add]); | |
12463 | break; | |
90700ea2 | 12464 | case m_mode: |
cb712a9e | 12465 | if (address_mode == mode_64bit) |
7967e09e | 12466 | oappend (names64[modrm.reg + add]); |
90700ea2 | 12467 | else |
7967e09e | 12468 | oappend (names32[modrm.reg + add]); |
90700ea2 | 12469 | break; |
1ba585e8 | 12470 | case mask_bd_mode: |
43234a1e | 12471 | case mask_mode: |
9889cbb1 L |
12472 | if ((modrm.reg + add) > 0x7) |
12473 | { | |
12474 | oappend ("(bad)"); | |
12475 | return; | |
12476 | } | |
43234a1e L |
12477 | oappend (names_mask[modrm.reg + add]); |
12478 | break; | |
252b5132 RH |
12479 | default: |
12480 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12481 | break; | |
12482 | } | |
12483 | } | |
12484 | ||
52b15da3 | 12485 | static bfd_vma |
26ca5450 | 12486 | get64 (void) |
52b15da3 | 12487 | { |
5dd0794d | 12488 | bfd_vma x; |
52b15da3 | 12489 | #ifdef BFD64 |
5dd0794d AM |
12490 | unsigned int a; |
12491 | unsigned int b; | |
12492 | ||
52b15da3 JH |
12493 | FETCH_DATA (the_info, codep + 8); |
12494 | a = *codep++ & 0xff; | |
12495 | a |= (*codep++ & 0xff) << 8; | |
12496 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 12497 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 12498 | b = *codep++ & 0xff; |
52b15da3 JH |
12499 | b |= (*codep++ & 0xff) << 8; |
12500 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 12501 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
12502 | x = a + ((bfd_vma) b << 32); |
12503 | #else | |
6608db57 | 12504 | abort (); |
5dd0794d | 12505 | x = 0; |
52b15da3 JH |
12506 | #endif |
12507 | return x; | |
12508 | } | |
12509 | ||
12510 | static bfd_signed_vma | |
26ca5450 | 12511 | get32 (void) |
252b5132 | 12512 | { |
b4b39349 | 12513 | bfd_vma x = 0; |
252b5132 RH |
12514 | |
12515 | FETCH_DATA (the_info, codep + 4); | |
b4b39349 AM |
12516 | x = *codep++ & (bfd_vma) 0xff; |
12517 | x |= (*codep++ & (bfd_vma) 0xff) << 8; | |
12518 | x |= (*codep++ & (bfd_vma) 0xff) << 16; | |
12519 | x |= (*codep++ & (bfd_vma) 0xff) << 24; | |
52b15da3 JH |
12520 | return x; |
12521 | } | |
12522 | ||
12523 | static bfd_signed_vma | |
26ca5450 | 12524 | get32s (void) |
52b15da3 | 12525 | { |
b4b39349 | 12526 | bfd_vma x = 0; |
52b15da3 JH |
12527 | |
12528 | FETCH_DATA (the_info, codep + 4); | |
b4b39349 AM |
12529 | x = *codep++ & (bfd_vma) 0xff; |
12530 | x |= (*codep++ & (bfd_vma) 0xff) << 8; | |
12531 | x |= (*codep++ & (bfd_vma) 0xff) << 16; | |
12532 | x |= (*codep++ & (bfd_vma) 0xff) << 24; | |
52b15da3 | 12533 | |
b4b39349 | 12534 | x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); |
52b15da3 | 12535 | |
252b5132 RH |
12536 | return x; |
12537 | } | |
12538 | ||
12539 | static int | |
26ca5450 | 12540 | get16 (void) |
252b5132 RH |
12541 | { |
12542 | int x = 0; | |
12543 | ||
12544 | FETCH_DATA (the_info, codep + 2); | |
12545 | x = *codep++ & 0xff; | |
12546 | x |= (*codep++ & 0xff) << 8; | |
12547 | return x; | |
12548 | } | |
12549 | ||
12550 | static void | |
26ca5450 | 12551 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
12552 | { |
12553 | op_index[op_ad] = op_ad; | |
cb712a9e | 12554 | if (address_mode == mode_64bit) |
7081ff04 AJ |
12555 | { |
12556 | op_address[op_ad] = op; | |
12557 | op_riprel[op_ad] = riprel; | |
12558 | } | |
12559 | else | |
12560 | { | |
12561 | /* Mask to get a 32-bit address. */ | |
12562 | op_address[op_ad] = op & 0xffffffff; | |
12563 | op_riprel[op_ad] = riprel & 0xffffffff; | |
12564 | } | |
252b5132 RH |
12565 | } |
12566 | ||
12567 | static void | |
26ca5450 | 12568 | OP_REG (int code, int sizeflag) |
252b5132 | 12569 | { |
2da11e11 | 12570 | const char *s; |
9b60702d | 12571 | int add; |
de882298 RM |
12572 | |
12573 | switch (code) | |
12574 | { | |
12575 | case es_reg: case ss_reg: case cs_reg: | |
12576 | case ds_reg: case fs_reg: case gs_reg: | |
12577 | oappend (names_seg[code - es_reg]); | |
12578 | return; | |
12579 | } | |
12580 | ||
161a04f6 L |
12581 | USED_REX (REX_B); |
12582 | if (rex & REX_B) | |
52b15da3 | 12583 | add = 8; |
9b60702d L |
12584 | else |
12585 | add = 0; | |
52b15da3 JH |
12586 | |
12587 | switch (code) | |
12588 | { | |
52b15da3 JH |
12589 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
12590 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
12591 | s = names16[code - ax_reg + add]; | |
12592 | break; | |
e184e611 | 12593 | case ah_reg: case ch_reg: case dh_reg: case bh_reg: |
52b15da3 | 12594 | USED_REX (0); |
e184e611 JB |
12595 | /* Fall through. */ |
12596 | case al_reg: case cl_reg: case dl_reg: case bl_reg: | |
52b15da3 JH |
12597 | if (rex) |
12598 | s = names8rex[code - al_reg + add]; | |
12599 | else | |
12600 | s = names8[code - al_reg]; | |
12601 | break; | |
6439fc28 AM |
12602 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
12603 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 12604 | if (address_mode == mode_64bit |
6c067bbb | 12605 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12606 | { |
12607 | s = names64[code - rAX_reg + add]; | |
12608 | break; | |
12609 | } | |
12610 | code += eAX_reg - rAX_reg; | |
6608db57 | 12611 | /* Fall through. */ |
52b15da3 JH |
12612 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
12613 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
12614 | USED_REX (REX_W); |
12615 | if (rex & REX_W) | |
52b15da3 | 12616 | s = names64[code - eAX_reg + add]; |
52b15da3 | 12617 | else |
f16cd0d5 L |
12618 | { |
12619 | if (sizeflag & DFLAG) | |
12620 | s = names32[code - eAX_reg + add]; | |
12621 | else | |
12622 | s = names16[code - eAX_reg + add]; | |
12623 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12624 | } | |
52b15da3 | 12625 | break; |
52b15da3 JH |
12626 | default: |
12627 | s = INTERNAL_DISASSEMBLER_ERROR; | |
12628 | break; | |
12629 | } | |
12630 | oappend (s); | |
12631 | } | |
12632 | ||
12633 | static void | |
26ca5450 | 12634 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
12635 | { |
12636 | const char *s; | |
252b5132 RH |
12637 | |
12638 | switch (code) | |
12639 | { | |
12640 | case indir_dx_reg: | |
d708bcba | 12641 | if (intel_syntax) |
52fd6d94 | 12642 | s = "dx"; |
d708bcba | 12643 | else |
db6eb5be | 12644 | s = "(%dx)"; |
252b5132 | 12645 | break; |
e8b5d5f9 JB |
12646 | case al_reg: case cl_reg: |
12647 | s = names8[code - al_reg]; | |
252b5132 | 12648 | break; |
e8b5d5f9 | 12649 | case eAX_reg: |
161a04f6 L |
12650 | USED_REX (REX_W); |
12651 | if (rex & REX_W) | |
f16cd0d5 | 12652 | { |
e8b5d5f9 JB |
12653 | s = *names64; |
12654 | break; | |
f16cd0d5 | 12655 | } |
e8b5d5f9 | 12656 | /* Fall through. */ |
52fd6d94 | 12657 | case z_mode_ax_reg: |
161a04f6 | 12658 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12659 | s = *names32; |
12660 | else | |
12661 | s = *names16; | |
161a04f6 | 12662 | if (!(rex & REX_W)) |
52fd6d94 JB |
12663 | used_prefixes |= (prefixes & PREFIX_DATA); |
12664 | break; | |
252b5132 RH |
12665 | default: |
12666 | s = INTERNAL_DISASSEMBLER_ERROR; | |
12667 | break; | |
12668 | } | |
12669 | oappend (s); | |
12670 | } | |
12671 | ||
12672 | static void | |
26ca5450 | 12673 | OP_I (int bytemode, int sizeflag) |
252b5132 | 12674 | { |
52b15da3 JH |
12675 | bfd_signed_vma op; |
12676 | bfd_signed_vma mask = -1; | |
252b5132 RH |
12677 | |
12678 | switch (bytemode) | |
12679 | { | |
12680 | case b_mode: | |
12681 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
12682 | op = *codep++; |
12683 | mask = 0xff; | |
12684 | break; | |
252b5132 | 12685 | case v_mode: |
161a04f6 L |
12686 | USED_REX (REX_W); |
12687 | if (rex & REX_W) | |
52b15da3 | 12688 | op = get32s (); |
252b5132 | 12689 | else |
52b15da3 | 12690 | { |
f16cd0d5 L |
12691 | if (sizeflag & DFLAG) |
12692 | { | |
12693 | op = get32 (); | |
12694 | mask = 0xffffffff; | |
12695 | } | |
12696 | else | |
12697 | { | |
12698 | op = get16 (); | |
12699 | mask = 0xfffff; | |
12700 | } | |
12701 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 12702 | } |
252b5132 | 12703 | break; |
c1dc7af5 JB |
12704 | case d_mode: |
12705 | mask = 0xffffffff; | |
12706 | op = get32 (); | |
12707 | break; | |
252b5132 | 12708 | case w_mode: |
52b15da3 | 12709 | mask = 0xfffff; |
252b5132 RH |
12710 | op = get16 (); |
12711 | break; | |
9306ca4a JB |
12712 | case const_1_mode: |
12713 | if (intel_syntax) | |
6c067bbb | 12714 | oappend ("1"); |
9306ca4a | 12715 | return; |
252b5132 RH |
12716 | default: |
12717 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12718 | return; | |
12719 | } | |
12720 | ||
52b15da3 JH |
12721 | op &= mask; |
12722 | scratchbuf[0] = '$'; | |
d708bcba | 12723 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 12724 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
12725 | scratchbuf[0] = '\0'; |
12726 | } | |
12727 | ||
12728 | static void | |
26ca5450 | 12729 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 12730 | { |
a280ab8e | 12731 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
12732 | { |
12733 | OP_I (bytemode, sizeflag); | |
12734 | return; | |
12735 | } | |
12736 | ||
a280ab8e | 12737 | USED_REX (REX_W); |
52b15da3 | 12738 | |
52b15da3 | 12739 | scratchbuf[0] = '$'; |
a280ab8e | 12740 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 12741 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12742 | scratchbuf[0] = '\0'; |
12743 | } | |
12744 | ||
12745 | static void | |
26ca5450 | 12746 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 12747 | { |
52b15da3 | 12748 | bfd_signed_vma op; |
252b5132 RH |
12749 | |
12750 | switch (bytemode) | |
12751 | { | |
12752 | case b_mode: | |
e3949f17 | 12753 | case b_T_mode: |
252b5132 RH |
12754 | FETCH_DATA (the_info, codep + 1); |
12755 | op = *codep++; | |
12756 | if ((op & 0x80) != 0) | |
12757 | op -= 0x100; | |
e3949f17 L |
12758 | if (bytemode == b_T_mode) |
12759 | { | |
12760 | if (address_mode != mode_64bit | |
7bb15c6f | 12761 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 12762 | { |
6c067bbb RM |
12763 | /* The operand-size prefix is overridden by a REX prefix. */ |
12764 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
12765 | op &= 0xffffffff; |
12766 | else | |
12767 | op &= 0xffff; | |
12768 | } | |
12769 | } | |
12770 | else | |
12771 | { | |
12772 | if (!(rex & REX_W)) | |
12773 | { | |
12774 | if (sizeflag & DFLAG) | |
12775 | op &= 0xffffffff; | |
12776 | else | |
12777 | op &= 0xffff; | |
12778 | } | |
12779 | } | |
252b5132 RH |
12780 | break; |
12781 | case v_mode: | |
7bb15c6f RM |
12782 | /* The operand-size prefix is overridden by a REX prefix. */ |
12783 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 12784 | op = get32s (); |
252b5132 | 12785 | else |
d9e3625e | 12786 | op = get16 (); |
252b5132 RH |
12787 | break; |
12788 | default: | |
12789 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12790 | return; | |
12791 | } | |
52b15da3 JH |
12792 | |
12793 | scratchbuf[0] = '$'; | |
12794 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 12795 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12796 | } |
12797 | ||
12798 | static void | |
26ca5450 | 12799 | OP_J (int bytemode, int sizeflag) |
252b5132 | 12800 | { |
52b15da3 | 12801 | bfd_vma disp; |
7081ff04 | 12802 | bfd_vma mask = -1; |
65ca155d | 12803 | bfd_vma segment = 0; |
252b5132 RH |
12804 | |
12805 | switch (bytemode) | |
12806 | { | |
12807 | case b_mode: | |
12808 | FETCH_DATA (the_info, codep + 1); | |
12809 | disp = *codep++; | |
12810 | if ((disp & 0x80) != 0) | |
12811 | disp -= 0x100; | |
12812 | break; | |
12813 | case v_mode: | |
376cd056 | 12814 | case dqw_mode: |
5db04b09 L |
12815 | if ((sizeflag & DFLAG) |
12816 | || (address_mode == mode_64bit | |
d835a58b | 12817 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 12818 | || (rex & REX_W)))) |
52b15da3 | 12819 | disp = get32s (); |
252b5132 RH |
12820 | else |
12821 | { | |
12822 | disp = get16 (); | |
206717e8 L |
12823 | if ((disp & 0x8000) != 0) |
12824 | disp -= 0x10000; | |
65ca155d L |
12825 | /* In 16bit mode, address is wrapped around at 64k within |
12826 | the same segment. Otherwise, a data16 prefix on a jump | |
12827 | instruction means that the pc is masked to 16 bits after | |
12828 | the displacement is added! */ | |
12829 | mask = 0xffff; | |
12830 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 12831 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 12832 | & ~((bfd_vma) 0xffff)); |
252b5132 | 12833 | } |
5db04b09 | 12834 | if (address_mode != mode_64bit |
d835a58b | 12835 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 12836 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
12837 | break; |
12838 | default: | |
12839 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12840 | return; | |
12841 | } | |
42d5f9c6 | 12842 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
12843 | set_op (disp, 0); |
12844 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
12845 | oappend (scratchbuf); |
12846 | } | |
12847 | ||
252b5132 | 12848 | static void |
ed7841b3 | 12849 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 12850 | { |
ed7841b3 | 12851 | if (bytemode == w_mode) |
7967e09e | 12852 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 12853 | else |
7967e09e | 12854 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
12855 | } |
12856 | ||
12857 | static void | |
26ca5450 | 12858 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
12859 | { |
12860 | int seg, offset; | |
12861 | ||
c608c12e | 12862 | if (sizeflag & DFLAG) |
252b5132 | 12863 | { |
c608c12e AM |
12864 | offset = get32 (); |
12865 | seg = get16 (); | |
252b5132 | 12866 | } |
c608c12e AM |
12867 | else |
12868 | { | |
12869 | offset = get16 (); | |
12870 | seg = get16 (); | |
12871 | } | |
7d421014 | 12872 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 12873 | if (intel_syntax) |
3f31e633 | 12874 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
12875 | else |
12876 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 12877 | oappend (scratchbuf); |
252b5132 RH |
12878 | } |
12879 | ||
252b5132 | 12880 | static void |
3f31e633 | 12881 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 12882 | { |
52b15da3 | 12883 | bfd_vma off; |
252b5132 | 12884 | |
3f31e633 JB |
12885 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12886 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
12887 | append_seg (); |
12888 | ||
cb712a9e | 12889 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
12890 | off = get32 (); |
12891 | else | |
12892 | off = get16 (); | |
12893 | ||
12894 | if (intel_syntax) | |
12895 | { | |
285ca992 | 12896 | if (!active_seg_prefix) |
252b5132 | 12897 | { |
d708bcba | 12898 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
12899 | oappend (":"); |
12900 | } | |
12901 | } | |
52b15da3 JH |
12902 | print_operand_value (scratchbuf, 1, off); |
12903 | oappend (scratchbuf); | |
12904 | } | |
6439fc28 | 12905 | |
52b15da3 | 12906 | static void |
3f31e633 | 12907 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
12908 | { |
12909 | bfd_vma off; | |
12910 | ||
539e75ad L |
12911 | if (address_mode != mode_64bit |
12912 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
12913 | { |
12914 | OP_OFF (bytemode, sizeflag); | |
12915 | return; | |
12916 | } | |
12917 | ||
3f31e633 JB |
12918 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12919 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
12920 | append_seg (); |
12921 | ||
6608db57 | 12922 | off = get64 (); |
52b15da3 JH |
12923 | |
12924 | if (intel_syntax) | |
12925 | { | |
285ca992 | 12926 | if (!active_seg_prefix) |
52b15da3 | 12927 | { |
d708bcba | 12928 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
12929 | oappend (":"); |
12930 | } | |
12931 | } | |
12932 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
12933 | oappend (scratchbuf); |
12934 | } | |
12935 | ||
12936 | static void | |
26ca5450 | 12937 | ptr_reg (int code, int sizeflag) |
252b5132 | 12938 | { |
2da11e11 | 12939 | const char *s; |
d708bcba | 12940 | |
1d9f512f | 12941 | *obufp++ = open_char; |
20f0a1fc | 12942 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 12943 | if (address_mode == mode_64bit) |
c1a64871 JH |
12944 | { |
12945 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 12946 | s = names32[code - eAX_reg]; |
c1a64871 | 12947 | else |
db6eb5be | 12948 | s = names64[code - eAX_reg]; |
c1a64871 | 12949 | } |
52b15da3 | 12950 | else if (sizeflag & AFLAG) |
252b5132 RH |
12951 | s = names32[code - eAX_reg]; |
12952 | else | |
12953 | s = names16[code - eAX_reg]; | |
12954 | oappend (s); | |
1d9f512f AM |
12955 | *obufp++ = close_char; |
12956 | *obufp = 0; | |
252b5132 RH |
12957 | } |
12958 | ||
12959 | static void | |
26ca5450 | 12960 | OP_ESreg (int code, int sizeflag) |
252b5132 | 12961 | { |
9306ca4a | 12962 | if (intel_syntax) |
52fd6d94 JB |
12963 | { |
12964 | switch (codep[-1]) | |
12965 | { | |
12966 | case 0x6d: /* insw/insl */ | |
12967 | intel_operand_size (z_mode, sizeflag); | |
12968 | break; | |
12969 | case 0xa5: /* movsw/movsl/movsq */ | |
12970 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12971 | case 0xab: /* stosw/stosl */ | |
12972 | case 0xaf: /* scasw/scasl */ | |
12973 | intel_operand_size (v_mode, sizeflag); | |
12974 | break; | |
12975 | default: | |
12976 | intel_operand_size (b_mode, sizeflag); | |
12977 | } | |
12978 | } | |
9ce09ba2 | 12979 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
12980 | ptr_reg (code, sizeflag); |
12981 | } | |
12982 | ||
12983 | static void | |
26ca5450 | 12984 | OP_DSreg (int code, int sizeflag) |
252b5132 | 12985 | { |
9306ca4a | 12986 | if (intel_syntax) |
52fd6d94 JB |
12987 | { |
12988 | switch (codep[-1]) | |
12989 | { | |
12990 | case 0x6f: /* outsw/outsl */ | |
12991 | intel_operand_size (z_mode, sizeflag); | |
12992 | break; | |
12993 | case 0xa5: /* movsw/movsl/movsq */ | |
12994 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12995 | case 0xad: /* lodsw/lodsl/lodsq */ | |
12996 | intel_operand_size (v_mode, sizeflag); | |
12997 | break; | |
12998 | default: | |
12999 | intel_operand_size (b_mode, sizeflag); | |
13000 | } | |
13001 | } | |
285ca992 L |
13002 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
13003 | default segment register DS is printed. */ | |
13004 | if (!active_seg_prefix) | |
13005 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 13006 | append_seg (); |
252b5132 RH |
13007 | ptr_reg (code, sizeflag); |
13008 | } | |
13009 | ||
252b5132 | 13010 | static void |
26ca5450 | 13011 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13012 | { |
9b60702d | 13013 | int add; |
161a04f6 | 13014 | if (rex & REX_R) |
c4a530c5 | 13015 | { |
161a04f6 | 13016 | USED_REX (REX_R); |
c4a530c5 JB |
13017 | add = 8; |
13018 | } | |
cb712a9e | 13019 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 13020 | { |
f16cd0d5 | 13021 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
13022 | used_prefixes |= PREFIX_LOCK; |
13023 | add = 8; | |
13024 | } | |
9b60702d L |
13025 | else |
13026 | add = 0; | |
7967e09e | 13027 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 13028 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13029 | } |
13030 | ||
252b5132 | 13031 | static void |
26ca5450 | 13032 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13033 | { |
9b60702d | 13034 | int add; |
161a04f6 L |
13035 | USED_REX (REX_R); |
13036 | if (rex & REX_R) | |
52b15da3 | 13037 | add = 8; |
9b60702d L |
13038 | else |
13039 | add = 0; | |
d708bcba | 13040 | if (intel_syntax) |
bfbd9438 | 13041 | sprintf (scratchbuf, "dr%d", modrm.reg + add); |
d708bcba | 13042 | else |
7967e09e | 13043 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
13044 | oappend (scratchbuf); |
13045 | } | |
13046 | ||
252b5132 | 13047 | static void |
26ca5450 | 13048 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13049 | { |
7967e09e | 13050 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 13051 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13052 | } |
13053 | ||
252b5132 | 13054 | static void |
26ca5450 | 13055 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13056 | { |
b9733481 L |
13057 | int reg = modrm.reg; |
13058 | const char **names; | |
13059 | ||
041bd2e0 JH |
13060 | used_prefixes |= (prefixes & PREFIX_DATA); |
13061 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 13062 | { |
b9733481 | 13063 | names = names_xmm; |
161a04f6 L |
13064 | USED_REX (REX_R); |
13065 | if (rex & REX_R) | |
b9733481 | 13066 | reg += 8; |
20f0a1fc | 13067 | } |
041bd2e0 | 13068 | else |
b9733481 L |
13069 | names = names_mm; |
13070 | oappend (names[reg]); | |
252b5132 RH |
13071 | } |
13072 | ||
c608c12e | 13073 | static void |
c0f3af97 | 13074 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 13075 | { |
b9733481 L |
13076 | int reg = modrm.reg; |
13077 | const char **names; | |
13078 | ||
161a04f6 L |
13079 | USED_REX (REX_R); |
13080 | if (rex & REX_R) | |
b9733481 | 13081 | reg += 8; |
43234a1e L |
13082 | if (vex.evex) |
13083 | { | |
13084 | if (!vex.r) | |
13085 | reg += 16; | |
13086 | } | |
13087 | ||
539f890d L |
13088 | if (need_vex |
13089 | && bytemode != xmm_mode | |
43234a1e L |
13090 | && bytemode != xmmq_mode |
13091 | && bytemode != evex_half_bcst_xmmq_mode | |
13092 | && bytemode != ymm_mode | |
260cd341 | 13093 | && bytemode != tmm_mode |
539f890d | 13094 | && bytemode != scalar_mode) |
c0f3af97 L |
13095 | { |
13096 | switch (vex.length) | |
13097 | { | |
13098 | case 128: | |
b9733481 | 13099 | names = names_xmm; |
c0f3af97 L |
13100 | break; |
13101 | case 256: | |
5fc35d96 IT |
13102 | if (vex.w |
13103 | || (bytemode != vex_vsib_q_w_dq_mode | |
13104 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
13105 | names = names_ymm; |
13106 | else | |
13107 | names = names_xmm; | |
c0f3af97 | 13108 | break; |
43234a1e L |
13109 | case 512: |
13110 | names = names_zmm; | |
13111 | break; | |
c0f3af97 L |
13112 | default: |
13113 | abort (); | |
13114 | } | |
13115 | } | |
43234a1e L |
13116 | else if (bytemode == xmmq_mode |
13117 | || bytemode == evex_half_bcst_xmmq_mode) | |
13118 | { | |
13119 | switch (vex.length) | |
13120 | { | |
13121 | case 128: | |
13122 | case 256: | |
13123 | names = names_xmm; | |
13124 | break; | |
13125 | case 512: | |
13126 | names = names_ymm; | |
13127 | break; | |
13128 | default: | |
13129 | abort (); | |
13130 | } | |
13131 | } | |
260cd341 LC |
13132 | else if (bytemode == tmm_mode) |
13133 | { | |
13134 | modrm.reg = reg; | |
13135 | if (reg >= 8) | |
13136 | { | |
13137 | oappend ("(bad)"); | |
13138 | return; | |
13139 | } | |
13140 | names = names_tmm; | |
13141 | } | |
43234a1e L |
13142 | else if (bytemode == ymm_mode) |
13143 | names = names_ymm; | |
c0f3af97 | 13144 | else |
b9733481 L |
13145 | names = names_xmm; |
13146 | oappend (names[reg]); | |
c608c12e AM |
13147 | } |
13148 | ||
252b5132 | 13149 | static void |
26ca5450 | 13150 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 13151 | { |
b9733481 L |
13152 | int reg; |
13153 | const char **names; | |
13154 | ||
7967e09e | 13155 | if (modrm.mod != 3) |
252b5132 | 13156 | { |
b6169b20 L |
13157 | if (intel_syntax |
13158 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
13159 | { |
13160 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
13161 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 13162 | } |
252b5132 RH |
13163 | OP_E (bytemode, sizeflag); |
13164 | return; | |
13165 | } | |
13166 | ||
b6169b20 L |
13167 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
13168 | swap_operand (); | |
13169 | ||
6608db57 | 13170 | /* Skip mod/rm byte. */ |
4bba6815 | 13171 | MODRM_CHECK; |
252b5132 | 13172 | codep++; |
041bd2e0 | 13173 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 13174 | reg = modrm.rm; |
041bd2e0 | 13175 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 13176 | { |
b9733481 | 13177 | names = names_xmm; |
161a04f6 L |
13178 | USED_REX (REX_B); |
13179 | if (rex & REX_B) | |
b9733481 | 13180 | reg += 8; |
20f0a1fc | 13181 | } |
041bd2e0 | 13182 | else |
b9733481 L |
13183 | names = names_mm; |
13184 | oappend (names[reg]); | |
252b5132 RH |
13185 | } |
13186 | ||
246c51aa L |
13187 | /* cvt* are the only instructions in sse2 which have |
13188 | both SSE and MMX operands and also have 0x66 prefix | |
13189 | in their opcode. 0x66 was originally used to differentiate | |
13190 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
13191 | cvt* separately using OP_EMC and OP_MXC */ |
13192 | static void | |
13193 | OP_EMC (int bytemode, int sizeflag) | |
13194 | { | |
7967e09e | 13195 | if (modrm.mod != 3) |
4d9567e0 MM |
13196 | { |
13197 | if (intel_syntax && bytemode == v_mode) | |
13198 | { | |
13199 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
13200 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 13201 | } |
4d9567e0 MM |
13202 | OP_E (bytemode, sizeflag); |
13203 | return; | |
13204 | } | |
246c51aa | 13205 | |
4d9567e0 MM |
13206 | /* Skip mod/rm byte. */ |
13207 | MODRM_CHECK; | |
13208 | codep++; | |
13209 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 13210 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
13211 | } |
13212 | ||
13213 | static void | |
13214 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13215 | { | |
13216 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 13217 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
13218 | } |
13219 | ||
c608c12e | 13220 | static void |
26ca5450 | 13221 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 13222 | { |
b9733481 L |
13223 | int reg; |
13224 | const char **names; | |
d6f574e0 L |
13225 | |
13226 | /* Skip mod/rm byte. */ | |
13227 | MODRM_CHECK; | |
13228 | codep++; | |
13229 | ||
7967e09e | 13230 | if (modrm.mod != 3) |
c608c12e | 13231 | { |
c1e679ec | 13232 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
13233 | return; |
13234 | } | |
d6f574e0 | 13235 | |
b9733481 | 13236 | reg = modrm.rm; |
161a04f6 L |
13237 | USED_REX (REX_B); |
13238 | if (rex & REX_B) | |
b9733481 | 13239 | reg += 8; |
43234a1e L |
13240 | if (vex.evex) |
13241 | { | |
13242 | USED_REX (REX_X); | |
13243 | if ((rex & REX_X)) | |
13244 | reg += 16; | |
13245 | } | |
c608c12e | 13246 | |
b6169b20 | 13247 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
13248 | && (bytemode == x_swap_mode |
13249 | || bytemode == d_swap_mode | |
41f5efc6 | 13250 | || bytemode == q_swap_mode)) |
b6169b20 L |
13251 | swap_operand (); |
13252 | ||
c0f3af97 L |
13253 | if (need_vex |
13254 | && bytemode != xmm_mode | |
6c30d220 L |
13255 | && bytemode != xmmdw_mode |
13256 | && bytemode != xmmqd_mode | |
13257 | && bytemode != xmm_mb_mode | |
13258 | && bytemode != xmm_mw_mode | |
13259 | && bytemode != xmm_md_mode | |
13260 | && bytemode != xmm_mq_mode | |
539f890d | 13261 | && bytemode != xmmq_mode |
43234a1e L |
13262 | && bytemode != evex_half_bcst_xmmq_mode |
13263 | && bytemode != ymm_mode | |
260cd341 | 13264 | && bytemode != tmm_mode |
1c480963 | 13265 | && bytemode != vex_scalar_w_dq_mode) |
c0f3af97 L |
13266 | { |
13267 | switch (vex.length) | |
13268 | { | |
13269 | case 128: | |
b9733481 | 13270 | names = names_xmm; |
c0f3af97 L |
13271 | break; |
13272 | case 256: | |
b9733481 | 13273 | names = names_ymm; |
c0f3af97 | 13274 | break; |
43234a1e L |
13275 | case 512: |
13276 | names = names_zmm; | |
13277 | break; | |
c0f3af97 L |
13278 | default: |
13279 | abort (); | |
13280 | } | |
13281 | } | |
43234a1e L |
13282 | else if (bytemode == xmmq_mode |
13283 | || bytemode == evex_half_bcst_xmmq_mode) | |
13284 | { | |
13285 | switch (vex.length) | |
13286 | { | |
13287 | case 128: | |
13288 | case 256: | |
13289 | names = names_xmm; | |
13290 | break; | |
13291 | case 512: | |
13292 | names = names_ymm; | |
13293 | break; | |
13294 | default: | |
13295 | abort (); | |
13296 | } | |
13297 | } | |
260cd341 LC |
13298 | else if (bytemode == tmm_mode) |
13299 | { | |
13300 | modrm.rm = reg; | |
13301 | if (reg >= 8) | |
13302 | { | |
13303 | oappend ("(bad)"); | |
13304 | return; | |
13305 | } | |
13306 | names = names_tmm; | |
13307 | } | |
43234a1e L |
13308 | else if (bytemode == ymm_mode) |
13309 | names = names_ymm; | |
c0f3af97 | 13310 | else |
b9733481 L |
13311 | names = names_xmm; |
13312 | oappend (names[reg]); | |
c608c12e AM |
13313 | } |
13314 | ||
252b5132 | 13315 | static void |
26ca5450 | 13316 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 13317 | { |
7967e09e | 13318 | if (modrm.mod == 3) |
2da11e11 AM |
13319 | OP_EM (bytemode, sizeflag); |
13320 | else | |
6608db57 | 13321 | BadOp (); |
252b5132 RH |
13322 | } |
13323 | ||
992aaec9 | 13324 | static void |
26ca5450 | 13325 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 13326 | { |
7967e09e | 13327 | if (modrm.mod == 3) |
992aaec9 AM |
13328 | OP_EX (bytemode, sizeflag); |
13329 | else | |
6608db57 | 13330 | BadOp (); |
992aaec9 AM |
13331 | } |
13332 | ||
cc0ec051 AM |
13333 | static void |
13334 | OP_M (int bytemode, int sizeflag) | |
13335 | { | |
7967e09e | 13336 | if (modrm.mod == 3) |
75413a22 L |
13337 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
13338 | BadOp (); | |
cc0ec051 AM |
13339 | else |
13340 | OP_E (bytemode, sizeflag); | |
13341 | } | |
13342 | ||
13343 | static void | |
13344 | OP_0f07 (int bytemode, int sizeflag) | |
13345 | { | |
7967e09e | 13346 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
13347 | BadOp (); |
13348 | else | |
13349 | OP_E (bytemode, sizeflag); | |
13350 | } | |
13351 | ||
46e883c5 | 13352 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 13353 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 13354 | |
cc0ec051 | 13355 | static void |
46e883c5 | 13356 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 13357 | { |
8b38ad71 L |
13358 | if ((prefixes & PREFIX_DATA) != 0 |
13359 | || (rex != 0 | |
13360 | && rex != 0x48 | |
13361 | && address_mode == mode_64bit)) | |
46e883c5 L |
13362 | OP_REG (bytemode, sizeflag); |
13363 | else | |
13364 | strcpy (obuf, "nop"); | |
13365 | } | |
13366 | ||
13367 | static void | |
13368 | NOP_Fixup2 (int bytemode, int sizeflag) | |
13369 | { | |
8b38ad71 L |
13370 | if ((prefixes & PREFIX_DATA) != 0 |
13371 | || (rex != 0 | |
13372 | && rex != 0x48 | |
13373 | && address_mode == mode_64bit)) | |
46e883c5 | 13374 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
13375 | } |
13376 | ||
84037f8c | 13377 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
13378 | /* 00 */ NULL, NULL, NULL, NULL, |
13379 | /* 04 */ NULL, NULL, NULL, NULL, | |
13380 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13381 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
13382 | /* 10 */ NULL, NULL, NULL, NULL, |
13383 | /* 14 */ NULL, NULL, NULL, NULL, | |
13384 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13385 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
13386 | /* 20 */ NULL, NULL, NULL, NULL, |
13387 | /* 24 */ NULL, NULL, NULL, NULL, | |
13388 | /* 28 */ NULL, NULL, NULL, NULL, | |
13389 | /* 2C */ NULL, NULL, NULL, NULL, | |
13390 | /* 30 */ NULL, NULL, NULL, NULL, | |
13391 | /* 34 */ NULL, NULL, NULL, NULL, | |
13392 | /* 38 */ NULL, NULL, NULL, NULL, | |
13393 | /* 3C */ NULL, NULL, NULL, NULL, | |
13394 | /* 40 */ NULL, NULL, NULL, NULL, | |
13395 | /* 44 */ NULL, NULL, NULL, NULL, | |
13396 | /* 48 */ NULL, NULL, NULL, NULL, | |
13397 | /* 4C */ NULL, NULL, NULL, NULL, | |
13398 | /* 50 */ NULL, NULL, NULL, NULL, | |
13399 | /* 54 */ NULL, NULL, NULL, NULL, | |
13400 | /* 58 */ NULL, NULL, NULL, NULL, | |
13401 | /* 5C */ NULL, NULL, NULL, NULL, | |
13402 | /* 60 */ NULL, NULL, NULL, NULL, | |
13403 | /* 64 */ NULL, NULL, NULL, NULL, | |
13404 | /* 68 */ NULL, NULL, NULL, NULL, | |
13405 | /* 6C */ NULL, NULL, NULL, NULL, | |
13406 | /* 70 */ NULL, NULL, NULL, NULL, | |
13407 | /* 74 */ NULL, NULL, NULL, NULL, | |
13408 | /* 78 */ NULL, NULL, NULL, NULL, | |
13409 | /* 7C */ NULL, NULL, NULL, NULL, | |
13410 | /* 80 */ NULL, NULL, NULL, NULL, | |
13411 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
13412 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
13413 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
13414 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
13415 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
13416 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
13417 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
13418 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
13419 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
13420 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
13421 | /* AC */ NULL, NULL, "pfacc", NULL, | |
13422 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 13423 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 13424 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
13425 | /* BC */ NULL, NULL, NULL, "pavgusb", |
13426 | /* C0 */ NULL, NULL, NULL, NULL, | |
13427 | /* C4 */ NULL, NULL, NULL, NULL, | |
13428 | /* C8 */ NULL, NULL, NULL, NULL, | |
13429 | /* CC */ NULL, NULL, NULL, NULL, | |
13430 | /* D0 */ NULL, NULL, NULL, NULL, | |
13431 | /* D4 */ NULL, NULL, NULL, NULL, | |
13432 | /* D8 */ NULL, NULL, NULL, NULL, | |
13433 | /* DC */ NULL, NULL, NULL, NULL, | |
13434 | /* E0 */ NULL, NULL, NULL, NULL, | |
13435 | /* E4 */ NULL, NULL, NULL, NULL, | |
13436 | /* E8 */ NULL, NULL, NULL, NULL, | |
13437 | /* EC */ NULL, NULL, NULL, NULL, | |
13438 | /* F0 */ NULL, NULL, NULL, NULL, | |
13439 | /* F4 */ NULL, NULL, NULL, NULL, | |
13440 | /* F8 */ NULL, NULL, NULL, NULL, | |
13441 | /* FC */ NULL, NULL, NULL, NULL, | |
13442 | }; | |
13443 | ||
13444 | static void | |
26ca5450 | 13445 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
13446 | { |
13447 | const char *mnemonic; | |
13448 | ||
13449 | FETCH_DATA (the_info, codep + 1); | |
13450 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
13451 | place where an 8-bit immediate would normally go. ie. the last | |
13452 | byte of the instruction. */ | |
ea397f5b | 13453 | obufp = mnemonicendp; |
c608c12e | 13454 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 13455 | if (mnemonic) |
2da11e11 | 13456 | oappend (mnemonic); |
252b5132 RH |
13457 | else |
13458 | { | |
13459 | /* Since a variable sized modrm/sib chunk is between the start | |
13460 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
13461 | all the modrm processing first, and don't know until now that | |
13462 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
13463 | op_out[0][0] = '\0'; |
13464 | op_out[1][0] = '\0'; | |
6608db57 | 13465 | BadOp (); |
252b5132 | 13466 | } |
ea397f5b | 13467 | mnemonicendp = obufp; |
252b5132 | 13468 | } |
c608c12e | 13469 | |
c4de7606 | 13470 | static const struct op simd_cmp_op[] = |
ea397f5b L |
13471 | { |
13472 | { STRING_COMMA_LEN ("eq") }, | |
13473 | { STRING_COMMA_LEN ("lt") }, | |
13474 | { STRING_COMMA_LEN ("le") }, | |
13475 | { STRING_COMMA_LEN ("unord") }, | |
13476 | { STRING_COMMA_LEN ("neq") }, | |
13477 | { STRING_COMMA_LEN ("nlt") }, | |
13478 | { STRING_COMMA_LEN ("nle") }, | |
13479 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
13480 | }; |
13481 | ||
c4de7606 JB |
13482 | static const struct op vex_cmp_op[] = |
13483 | { | |
13484 | { STRING_COMMA_LEN ("eq_uq") }, | |
13485 | { STRING_COMMA_LEN ("nge") }, | |
13486 | { STRING_COMMA_LEN ("ngt") }, | |
13487 | { STRING_COMMA_LEN ("false") }, | |
13488 | { STRING_COMMA_LEN ("neq_oq") }, | |
13489 | { STRING_COMMA_LEN ("ge") }, | |
13490 | { STRING_COMMA_LEN ("gt") }, | |
13491 | { STRING_COMMA_LEN ("true") }, | |
13492 | { STRING_COMMA_LEN ("eq_os") }, | |
13493 | { STRING_COMMA_LEN ("lt_oq") }, | |
13494 | { STRING_COMMA_LEN ("le_oq") }, | |
13495 | { STRING_COMMA_LEN ("unord_s") }, | |
13496 | { STRING_COMMA_LEN ("neq_us") }, | |
13497 | { STRING_COMMA_LEN ("nlt_uq") }, | |
13498 | { STRING_COMMA_LEN ("nle_uq") }, | |
13499 | { STRING_COMMA_LEN ("ord_s") }, | |
13500 | { STRING_COMMA_LEN ("eq_us") }, | |
13501 | { STRING_COMMA_LEN ("nge_uq") }, | |
13502 | { STRING_COMMA_LEN ("ngt_uq") }, | |
13503 | { STRING_COMMA_LEN ("false_os") }, | |
13504 | { STRING_COMMA_LEN ("neq_os") }, | |
13505 | { STRING_COMMA_LEN ("ge_oq") }, | |
13506 | { STRING_COMMA_LEN ("gt_oq") }, | |
13507 | { STRING_COMMA_LEN ("true_us") }, | |
13508 | }; | |
13509 | ||
c608c12e | 13510 | static void |
ad19981d | 13511 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
13512 | { |
13513 | unsigned int cmp_type; | |
13514 | ||
13515 | FETCH_DATA (the_info, codep + 1); | |
13516 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 13517 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 13518 | { |
ad19981d | 13519 | char suffix [3]; |
ea397f5b | 13520 | char *p = mnemonicendp - 2; |
ad19981d L |
13521 | suffix[0] = p[0]; |
13522 | suffix[1] = p[1]; | |
13523 | suffix[2] = '\0'; | |
ea397f5b L |
13524 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
13525 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e | 13526 | } |
c4de7606 JB |
13527 | else if (need_vex |
13528 | && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) | |
13529 | { | |
13530 | char suffix [3]; | |
13531 | char *p = mnemonicendp - 2; | |
13532 | suffix[0] = p[0]; | |
13533 | suffix[1] = p[1]; | |
13534 | suffix[2] = '\0'; | |
13535 | cmp_type -= ARRAY_SIZE (simd_cmp_op); | |
13536 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); | |
13537 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
13538 | } | |
c608c12e AM |
13539 | else |
13540 | { | |
ad19981d L |
13541 | /* We have a reserved extension byte. Output it directly. */ |
13542 | scratchbuf[0] = '$'; | |
13543 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 13544 | oappend_maybe_intel (scratchbuf); |
ad19981d | 13545 | scratchbuf[0] = '\0'; |
c608c12e AM |
13546 | } |
13547 | } | |
13548 | ||
9916071f | 13549 | static void |
7abb8d81 | 13550 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 13551 | { |
7abb8d81 | 13552 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
13553 | if (!intel_syntax) |
13554 | { | |
081e283f JB |
13555 | strcpy (op_out[0], names32[0]); |
13556 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 13557 | if (bytemode == eBX_reg) |
081e283f | 13558 | strcpy (op_out[2], names32[3]); |
b844680a L |
13559 | two_source_ops = 1; |
13560 | } | |
13561 | /* Skip mod/rm byte. */ | |
13562 | MODRM_CHECK; | |
13563 | codep++; | |
13564 | } | |
13565 | ||
13566 | static void | |
13567 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
13568 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 13569 | { |
081e283f | 13570 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 13571 | if (!intel_syntax) |
ca164297 | 13572 | { |
cb712a9e L |
13573 | const char **names = (address_mode == mode_64bit |
13574 | ? names64 : names32); | |
1d9f512f | 13575 | |
081e283f | 13576 | if (prefixes & PREFIX_ADDR) |
ca164297 | 13577 | { |
b844680a | 13578 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 13579 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
13580 | names = (address_mode != mode_32bit |
13581 | ? names32 : names16); | |
b844680a | 13582 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 13583 | } |
081e283f JB |
13584 | else if (address_mode == mode_16bit) |
13585 | names = names16; | |
13586 | strcpy (op_out[0], names[0]); | |
13587 | strcpy (op_out[1], names32[1]); | |
13588 | strcpy (op_out[2], names32[2]); | |
b844680a | 13589 | two_source_ops = 1; |
ca164297 | 13590 | } |
b844680a L |
13591 | /* Skip mod/rm byte. */ |
13592 | MODRM_CHECK; | |
13593 | codep++; | |
30123838 JB |
13594 | } |
13595 | ||
6608db57 KH |
13596 | static void |
13597 | BadOp (void) | |
2da11e11 | 13598 | { |
6608db57 KH |
13599 | /* Throw away prefixes and 1st. opcode byte. */ |
13600 | codep = insn_codep + 1; | |
2da11e11 AM |
13601 | oappend ("(bad)"); |
13602 | } | |
4cc91dba | 13603 | |
35c52694 L |
13604 | static void |
13605 | REP_Fixup (int bytemode, int sizeflag) | |
13606 | { | |
13607 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
13608 | lods and stos. */ | |
35c52694 | 13609 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 13610 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
13611 | |
13612 | switch (bytemode) | |
13613 | { | |
13614 | case al_reg: | |
13615 | case eAX_reg: | |
13616 | case indir_dx_reg: | |
13617 | OP_IMREG (bytemode, sizeflag); | |
13618 | break; | |
13619 | case eDI_reg: | |
13620 | OP_ESreg (bytemode, sizeflag); | |
13621 | break; | |
13622 | case eSI_reg: | |
13623 | OP_DSreg (bytemode, sizeflag); | |
13624 | break; | |
13625 | default: | |
13626 | abort (); | |
13627 | break; | |
13628 | } | |
13629 | } | |
f5804c90 | 13630 | |
d835a58b JB |
13631 | static void |
13632 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13633 | { | |
13634 | if ( isa64 != amd64 ) | |
13635 | return; | |
13636 | ||
13637 | obufp = obuf; | |
13638 | BadOp (); | |
13639 | mnemonicendp = obufp; | |
13640 | ++codep; | |
13641 | } | |
13642 | ||
7e8b059b L |
13643 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
13644 | "bnd". */ | |
13645 | ||
13646 | static void | |
13647 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13648 | { | |
13649 | if (prefixes & PREFIX_REPNZ) | |
13650 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
13651 | } | |
13652 | ||
04ef582a L |
13653 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
13654 | "notrack". */ | |
13655 | ||
13656 | static void | |
13657 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13658 | int sizeflag ATTRIBUTE_UNUSED) | |
13659 | { | |
9fef80d6 | 13660 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
13661 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
13662 | { | |
4e9ac44a | 13663 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 13664 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
13665 | active_seg_prefix = 0; |
13666 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
13667 | } | |
13668 | } | |
13669 | ||
42164a71 L |
13670 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
13671 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
13672 | */ | |
13673 | ||
13674 | static void | |
13675 | HLE_Fixup1 (int bytemode, int sizeflag) | |
13676 | { | |
13677 | if (modrm.mod != 3 | |
13678 | && (prefixes & PREFIX_LOCK) != 0) | |
13679 | { | |
13680 | if (prefixes & PREFIX_REPZ) | |
13681 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13682 | if (prefixes & PREFIX_REPNZ) | |
13683 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13684 | } | |
13685 | ||
13686 | OP_E (bytemode, sizeflag); | |
13687 | } | |
13688 | ||
13689 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
13690 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
13691 | */ | |
13692 | ||
13693 | static void | |
13694 | HLE_Fixup2 (int bytemode, int sizeflag) | |
13695 | { | |
13696 | if (modrm.mod != 3) | |
13697 | { | |
13698 | if (prefixes & PREFIX_REPZ) | |
13699 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13700 | if (prefixes & PREFIX_REPNZ) | |
13701 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13702 | } | |
13703 | ||
13704 | OP_E (bytemode, sizeflag); | |
13705 | } | |
13706 | ||
13707 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
13708 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
13709 | ||
13710 | static void | |
13711 | HLE_Fixup3 (int bytemode, int sizeflag) | |
13712 | { | |
13713 | if (modrm.mod != 3 | |
13714 | && last_repz_prefix > last_repnz_prefix | |
13715 | && (prefixes & PREFIX_REPZ) != 0) | |
13716 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13717 | ||
13718 | OP_E (bytemode, sizeflag); | |
13719 | } | |
13720 | ||
f5804c90 L |
13721 | static void |
13722 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
13723 | { | |
161a04f6 L |
13724 | USED_REX (REX_W); |
13725 | if (rex & REX_W) | |
f5804c90 L |
13726 | { |
13727 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
13728 | char *p = mnemonicendp - 2; |
13729 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 13730 | bytemode = o_mode; |
f5804c90 | 13731 | } |
42164a71 L |
13732 | else if ((prefixes & PREFIX_LOCK) != 0) |
13733 | { | |
13734 | if (prefixes & PREFIX_REPZ) | |
13735 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13736 | if (prefixes & PREFIX_REPNZ) | |
13737 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13738 | } | |
13739 | ||
f5804c90 L |
13740 | OP_M (bytemode, sizeflag); |
13741 | } | |
42903f7f L |
13742 | |
13743 | static void | |
13744 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
13745 | { | |
b9733481 L |
13746 | const char **names; |
13747 | ||
c0f3af97 L |
13748 | if (need_vex) |
13749 | { | |
13750 | switch (vex.length) | |
13751 | { | |
13752 | case 128: | |
b9733481 | 13753 | names = names_xmm; |
c0f3af97 L |
13754 | break; |
13755 | case 256: | |
b9733481 | 13756 | names = names_ymm; |
c0f3af97 L |
13757 | break; |
13758 | default: | |
13759 | abort (); | |
13760 | } | |
13761 | } | |
13762 | else | |
b9733481 L |
13763 | names = names_xmm; |
13764 | oappend (names[reg]); | |
42903f7f | 13765 | } |
381d071f L |
13766 | |
13767 | static void | |
eacc9c89 L |
13768 | FXSAVE_Fixup (int bytemode, int sizeflag) |
13769 | { | |
13770 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
13771 | USED_REX (REX_W); | |
13772 | if (rex & REX_W) | |
13773 | { | |
13774 | char *p = mnemonicendp; | |
13775 | *p++ = '6'; | |
13776 | *p++ = '4'; | |
13777 | *p = '\0'; | |
13778 | mnemonicendp = p; | |
13779 | } | |
13780 | OP_M (bytemode, sizeflag); | |
15c7c1d8 JB |
13781 | } |
13782 | ||
c0f3af97 L |
13783 | /* Display the destination register operand for instructions with |
13784 | VEX. */ | |
13785 | ||
13786 | static void | |
13787 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13788 | { | |
539f890d | 13789 | int reg; |
b9733481 L |
13790 | const char **names; |
13791 | ||
c0f3af97 L |
13792 | if (!need_vex) |
13793 | abort (); | |
13794 | ||
539f890d | 13795 | reg = vex.register_specifier; |
63c6fc6c | 13796 | vex.register_specifier = 0; |
5f847646 JB |
13797 | if (address_mode != mode_64bit) |
13798 | reg &= 7; | |
13799 | else if (vex.evex && !vex.v) | |
13800 | reg += 16; | |
43234a1e | 13801 | |
539f890d L |
13802 | if (bytemode == vex_scalar_mode) |
13803 | { | |
13804 | oappend (names_xmm[reg]); | |
13805 | return; | |
13806 | } | |
13807 | ||
260cd341 LC |
13808 | if (bytemode == tmm_mode) |
13809 | { | |
13810 | /* All 3 TMM registers must be distinct. */ | |
13811 | if (reg >= 8) | |
13812 | oappend ("(bad)"); | |
13813 | else | |
13814 | { | |
13815 | /* This must be the 3rd operand. */ | |
13816 | if (obufp != op_out[2]) | |
13817 | abort (); | |
13818 | oappend (names_tmm[reg]); | |
13819 | if (reg == modrm.reg || reg == modrm.rm) | |
13820 | strcpy (obufp, "/(bad)"); | |
13821 | } | |
13822 | ||
13823 | if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg) | |
13824 | { | |
13825 | if (modrm.reg <= 8 | |
13826 | && (modrm.reg == modrm.rm || modrm.reg == reg)) | |
13827 | strcat (op_out[0], "/(bad)"); | |
13828 | if (modrm.rm <= 8 | |
13829 | && (modrm.rm == modrm.reg || modrm.rm == reg)) | |
13830 | strcat (op_out[1], "/(bad)"); | |
13831 | } | |
13832 | ||
13833 | return; | |
13834 | } | |
13835 | ||
c0f3af97 L |
13836 | switch (vex.length) |
13837 | { | |
13838 | case 128: | |
13839 | switch (bytemode) | |
13840 | { | |
13841 | case vex_mode: | |
6c30d220 | 13842 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13843 | case vex_vsib_q_w_d_mode: |
cb21baef L |
13844 | names = names_xmm; |
13845 | break; | |
13846 | case dq_mode: | |
390a6789 | 13847 | if (rex & REX_W) |
cb21baef L |
13848 | names = names64; |
13849 | else | |
13850 | names = names32; | |
c0f3af97 | 13851 | break; |
1ba585e8 | 13852 | case mask_bd_mode: |
43234a1e | 13853 | case mask_mode: |
9889cbb1 L |
13854 | if (reg > 0x7) |
13855 | { | |
13856 | oappend ("(bad)"); | |
13857 | return; | |
13858 | } | |
43234a1e L |
13859 | names = names_mask; |
13860 | break; | |
c0f3af97 L |
13861 | default: |
13862 | abort (); | |
13863 | return; | |
13864 | } | |
c0f3af97 L |
13865 | break; |
13866 | case 256: | |
13867 | switch (bytemode) | |
13868 | { | |
13869 | case vex_mode: | |
6c30d220 L |
13870 | names = names_ymm; |
13871 | break; | |
13872 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 13873 | case vex_vsib_q_w_d_mode: |
6c30d220 | 13874 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 13875 | break; |
1ba585e8 | 13876 | case mask_bd_mode: |
43234a1e | 13877 | case mask_mode: |
9889cbb1 L |
13878 | if (reg > 0x7) |
13879 | { | |
13880 | oappend ("(bad)"); | |
13881 | return; | |
13882 | } | |
43234a1e L |
13883 | names = names_mask; |
13884 | break; | |
c0f3af97 | 13885 | default: |
a37a2806 NC |
13886 | /* See PR binutils/20893 for a reproducer. */ |
13887 | oappend ("(bad)"); | |
c0f3af97 L |
13888 | return; |
13889 | } | |
c0f3af97 | 13890 | break; |
43234a1e L |
13891 | case 512: |
13892 | names = names_zmm; | |
13893 | break; | |
c0f3af97 L |
13894 | default: |
13895 | abort (); | |
13896 | break; | |
13897 | } | |
539f890d | 13898 | oappend (names[reg]); |
c0f3af97 L |
13899 | } |
13900 | ||
41f5efc6 JB |
13901 | static void |
13902 | OP_VexR (int bytemode, int sizeflag) | |
13903 | { | |
13904 | if (modrm.mod == 3) | |
13905 | OP_VEX (bytemode, sizeflag); | |
13906 | } | |
13907 | ||
5dd85c99 | 13908 | static void |
e6123d0c | 13909 | OP_VexW (int bytemode, int sizeflag) |
5dd85c99 | 13910 | { |
e6123d0c | 13911 | OP_VEX (bytemode, sizeflag); |
5dd85c99 | 13912 | |
5dd85c99 | 13913 | if (vex.w) |
5f847646 | 13914 | { |
e6123d0c JB |
13915 | /* Swap 2nd and 3rd operands. */ |
13916 | strcpy (scratchbuf, op_out[2]); | |
13917 | strcpy (op_out[2], op_out[1]); | |
13918 | strcpy (op_out[1], scratchbuf); | |
5f847646 | 13919 | } |
5dd85c99 SP |
13920 | } |
13921 | ||
c0f3af97 L |
13922 | static void |
13923 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13924 | { | |
13925 | int reg; | |
6384fd9e | 13926 | const char **names = names_xmm; |
b9733481 | 13927 | |
c0f3af97 L |
13928 | FETCH_DATA (the_info, codep + 1); |
13929 | reg = *codep++; | |
13930 | ||
6384fd9e | 13931 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
13932 | abort (); |
13933 | ||
c0f3af97 | 13934 | reg >>= 4; |
5f847646 JB |
13935 | if (address_mode != mode_64bit) |
13936 | reg &= 7; | |
dae39acc | 13937 | |
6384fd9e JB |
13938 | if (bytemode == x_mode && vex.length == 256) |
13939 | names = names_ymm; | |
13940 | ||
b9733481 | 13941 | oappend (names[reg]); |
b13b1bc0 JB |
13942 | |
13943 | if (vex.w) | |
13944 | { | |
13945 | /* Swap 3rd and 4th operands. */ | |
13946 | strcpy (scratchbuf, op_out[3]); | |
13947 | strcpy (op_out[3], op_out[2]); | |
13948 | strcpy (op_out[2], scratchbuf); | |
13949 | } | |
c0f3af97 L |
13950 | } |
13951 | ||
922d8de8 | 13952 | static void |
93abb146 JB |
13953 | OP_VexI4 (int bytemode ATTRIBUTE_UNUSED, |
13954 | int sizeflag ATTRIBUTE_UNUSED) | |
922d8de8 | 13955 | { |
93abb146 JB |
13956 | scratchbuf[0] = '$'; |
13957 | print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf); | |
13958 | oappend_maybe_intel (scratchbuf); | |
922d8de8 DR |
13959 | } |
13960 | ||
43234a1e L |
13961 | static void |
13962 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13963 | int sizeflag ATTRIBUTE_UNUSED) | |
13964 | { | |
13965 | unsigned int cmp_type; | |
13966 | ||
13967 | if (!vex.evex) | |
13968 | abort (); | |
13969 | ||
13970 | FETCH_DATA (the_info, codep + 1); | |
13971 | cmp_type = *codep++ & 0xff; | |
13972 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
13973 | If it's the case, print suffix, otherwise - print the immediate. */ | |
13974 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
13975 | && cmp_type != 3 | |
13976 | && cmp_type != 7) | |
13977 | { | |
13978 | char suffix [3]; | |
13979 | char *p = mnemonicendp - 2; | |
13980 | ||
13981 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
13982 | if (p[0] == 'p') | |
13983 | { | |
13984 | p++; | |
13985 | suffix[0] = p[0]; | |
13986 | suffix[1] = '\0'; | |
13987 | } | |
13988 | else | |
13989 | { | |
13990 | suffix[0] = p[0]; | |
13991 | suffix[1] = p[1]; | |
13992 | suffix[2] = '\0'; | |
13993 | } | |
13994 | ||
13995 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
13996 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
13997 | } | |
be92cb14 JB |
13998 | else |
13999 | { | |
14000 | /* We have a reserved extension byte. Output it directly. */ | |
14001 | scratchbuf[0] = '$'; | |
14002 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
14003 | oappend_maybe_intel (scratchbuf); | |
14004 | scratchbuf[0] = '\0'; | |
14005 | } | |
14006 | } | |
14007 | ||
14008 | static const struct op xop_cmp_op[] = | |
14009 | { | |
14010 | { STRING_COMMA_LEN ("lt") }, | |
14011 | { STRING_COMMA_LEN ("le") }, | |
14012 | { STRING_COMMA_LEN ("gt") }, | |
14013 | { STRING_COMMA_LEN ("ge") }, | |
14014 | { STRING_COMMA_LEN ("eq") }, | |
14015 | { STRING_COMMA_LEN ("neq") }, | |
14016 | { STRING_COMMA_LEN ("false") }, | |
14017 | { STRING_COMMA_LEN ("true") } | |
14018 | }; | |
14019 | ||
14020 | static void | |
14021 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
14022 | int sizeflag ATTRIBUTE_UNUSED) | |
14023 | { | |
14024 | unsigned int cmp_type; | |
14025 | ||
14026 | FETCH_DATA (the_info, codep + 1); | |
14027 | cmp_type = *codep++ & 0xff; | |
14028 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
14029 | { | |
14030 | char suffix[3]; | |
14031 | char *p = mnemonicendp - 2; | |
14032 | ||
14033 | /* vpcom* can have both one- and two-lettered suffix. */ | |
14034 | if (p[0] == 'm') | |
14035 | { | |
14036 | p++; | |
14037 | suffix[0] = p[0]; | |
14038 | suffix[1] = '\0'; | |
14039 | } | |
14040 | else | |
14041 | { | |
14042 | suffix[0] = p[0]; | |
14043 | suffix[1] = p[1]; | |
14044 | suffix[2] = '\0'; | |
14045 | } | |
14046 | ||
14047 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
14048 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
14049 | } | |
43234a1e L |
14050 | else |
14051 | { | |
14052 | /* We have a reserved extension byte. Output it directly. */ | |
14053 | scratchbuf[0] = '$'; | |
14054 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 14055 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
14056 | scratchbuf[0] = '\0'; |
14057 | } | |
14058 | } | |
14059 | ||
ea397f5b L |
14060 | static const struct op pclmul_op[] = |
14061 | { | |
14062 | { STRING_COMMA_LEN ("lql") }, | |
14063 | { STRING_COMMA_LEN ("hql") }, | |
14064 | { STRING_COMMA_LEN ("lqh") }, | |
14065 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
14066 | }; |
14067 | ||
14068 | static void | |
14069 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
14070 | int sizeflag ATTRIBUTE_UNUSED) | |
14071 | { | |
14072 | unsigned int pclmul_type; | |
14073 | ||
14074 | FETCH_DATA (the_info, codep + 1); | |
14075 | pclmul_type = *codep++ & 0xff; | |
14076 | switch (pclmul_type) | |
14077 | { | |
14078 | case 0x10: | |
14079 | pclmul_type = 2; | |
14080 | break; | |
14081 | case 0x11: | |
14082 | pclmul_type = 3; | |
14083 | break; | |
14084 | default: | |
14085 | break; | |
7bb15c6f | 14086 | } |
c0f3af97 L |
14087 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
14088 | { | |
14089 | char suffix [4]; | |
ea397f5b | 14090 | char *p = mnemonicendp - 3; |
c0f3af97 L |
14091 | suffix[0] = p[0]; |
14092 | suffix[1] = p[1]; | |
14093 | suffix[2] = p[2]; | |
14094 | suffix[3] = '\0'; | |
ea397f5b L |
14095 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
14096 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
14097 | } |
14098 | else | |
14099 | { | |
14100 | /* We have a reserved extension byte. Output it directly. */ | |
14101 | scratchbuf[0] = '$'; | |
14102 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 14103 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
14104 | scratchbuf[0] = '\0'; |
14105 | } | |
14106 | } | |
14107 | ||
bc31405e L |
14108 | static void |
14109 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
14110 | { | |
14111 | /* Add proper suffix to "movsxd". */ | |
14112 | char *p = mnemonicendp; | |
14113 | ||
14114 | switch (bytemode) | |
14115 | { | |
14116 | case movsxd_mode: | |
14117 | if (intel_syntax) | |
14118 | { | |
14119 | *p++ = 'x'; | |
14120 | *p++ = 'd'; | |
14121 | goto skip; | |
14122 | } | |
14123 | ||
14124 | USED_REX (REX_W); | |
14125 | if (rex & REX_W) | |
14126 | { | |
14127 | *p++ = 'l'; | |
14128 | *p++ = 'q'; | |
14129 | } | |
14130 | else | |
14131 | { | |
14132 | *p++ = 'x'; | |
14133 | *p++ = 'd'; | |
14134 | } | |
14135 | break; | |
14136 | default: | |
14137 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14138 | break; | |
14139 | } | |
14140 | ||
dc1e8a47 | 14141 | skip: |
bc31405e L |
14142 | mnemonicendp = p; |
14143 | *p = '\0'; | |
14144 | OP_E (bytemode, sizeflag); | |
14145 | } | |
14146 | ||
43234a1e L |
14147 | static void |
14148 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14149 | { | |
14150 | if (!vex.evex | |
1ba585e8 | 14151 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
14152 | abort (); |
14153 | ||
14154 | USED_REX (REX_R); | |
14155 | if ((rex & REX_R) != 0 || !vex.r) | |
14156 | { | |
14157 | BadOp (); | |
14158 | return; | |
14159 | } | |
14160 | ||
14161 | oappend (names_mask [modrm.reg]); | |
14162 | } | |
14163 | ||
14164 | static void | |
14165 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14166 | { | |
43234a1e L |
14167 | if (modrm.mod == 3 && vex.b) |
14168 | switch (bytemode) | |
14169 | { | |
70df6fc9 L |
14170 | case evex_rounding_64_mode: |
14171 | if (address_mode != mode_64bit) | |
14172 | { | |
14173 | oappend ("(bad)"); | |
14174 | break; | |
14175 | } | |
14176 | /* Fall through. */ | |
43234a1e L |
14177 | case evex_rounding_mode: |
14178 | oappend (names_rounding[vex.ll]); | |
14179 | break; | |
14180 | case evex_sae_mode: | |
14181 | oappend ("{sae}"); | |
14182 | break; | |
14183 | default: | |
6df22cf6 | 14184 | abort (); |
43234a1e L |
14185 | break; |
14186 | } | |
14187 | } |