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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
d835a58b | 110 | static void SEP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
bc31405e | 127 | static void MOVSXD_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
52b15da3 JH |
156 | /* Mark parts used in the REX prefix. When we are testing for |
157 | empty prefix (for 8bit register REX extension), just mask it | |
158 | out. Otherwise test for REX bit is excuse for existence of REX | |
159 | only in case value is nonzero. */ | |
160 | #define USED_REX(value) \ | |
161 | { \ | |
162 | if (value) \ | |
161a04f6 L |
163 | { \ |
164 | if ((rex & value)) \ | |
165 | rex_used |= (value) | REX_OPCODE; \ | |
166 | } \ | |
52b15da3 | 167 | else \ |
161a04f6 | 168 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
169 | } |
170 | ||
7d421014 ILT |
171 | /* Flags for prefixes which we somehow handled when printing the |
172 | current instruction. */ | |
173 | static int used_prefixes; | |
174 | ||
5076851f ILT |
175 | /* Flags stored in PREFIXES. */ |
176 | #define PREFIX_REPZ 1 | |
177 | #define PREFIX_REPNZ 2 | |
178 | #define PREFIX_LOCK 4 | |
179 | #define PREFIX_CS 8 | |
180 | #define PREFIX_SS 0x10 | |
181 | #define PREFIX_DS 0x20 | |
182 | #define PREFIX_ES 0x40 | |
183 | #define PREFIX_FS 0x80 | |
184 | #define PREFIX_GS 0x100 | |
185 | #define PREFIX_DATA 0x200 | |
186 | #define PREFIX_ADDR 0x400 | |
187 | #define PREFIX_FWAIT 0x800 | |
188 | ||
252b5132 RH |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
191 | on error. */ | |
192 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
194 | ? 1 : fetch_data ((info), (addr))) |
195 | ||
196 | static int | |
26ca5450 | 197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
198 | { |
199 | int status; | |
6608db57 | 200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
202 | ||
0b1cf022 | 203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
204 | status = (*info->read_memory_func) (start, |
205 | priv->max_fetched, | |
206 | addr - priv->max_fetched, | |
207 | info); | |
208 | else | |
209 | status = -1; | |
252b5132 RH |
210 | if (status != 0) |
211 | { | |
7d421014 | 212 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
213 | print_insn_i386 will do something sensible. Otherwise, print |
214 | an error. We do that here because this is where we know | |
215 | STATUS. */ | |
7d421014 | 216 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 217 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
219 | } |
220 | else | |
221 | priv->max_fetched = addr; | |
222 | return 1; | |
223 | } | |
224 | ||
bf890a93 | 225 | /* Possible values for prefix requirement. */ |
507bd325 L |
226 | #define PREFIX_IGNORED_SHIFT 16 |
227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
232 | ||
233 | /* Opcode prefixes. */ | |
234 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
235 | | PREFIX_REPNZ \ | |
236 | | PREFIX_DATA) | |
237 | ||
238 | /* Prefixes ignored. */ | |
239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
240 | | PREFIX_IGNORED_REPNZ \ | |
241 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 242 | |
ce518a5f | 243 | #define XX { NULL, 0 } |
507bd325 | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
245 | |
246 | #define Eb { OP_E, b_mode } | |
7e8b059b | 247 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 248 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 249 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 250 | #define Ev { OP_E, v_mode } |
de89d0a3 | 251 | #define Eva { OP_E, va_mode } |
7e8b059b | 252 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 253 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
254 | #define Ed { OP_E, d_mode } |
255 | #define Edq { OP_E, dq_mode } | |
256 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 257 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
258 | #define Edb { OP_E, db_mode } |
259 | #define Edw { OP_E, dw_mode } | |
42903f7f | 260 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 261 | #define Eq { OP_E, q_mode } |
07f5af7d | 262 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
263 | #define indirEp { OP_indirE, f_mode } |
264 | #define stackEv { OP_E, stack_v_mode } | |
265 | #define Em { OP_E, m_mode } | |
266 | #define Ew { OP_E, w_mode } | |
267 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 268 | #define Ma { OP_M, a_mode } |
b844680a | 269 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 270 | #define Md { OP_M, d_mode } |
f1f8f695 | 271 | #define Mo { OP_M, o_mode } |
ce518a5f L |
272 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
273 | #define Mq { OP_M, q_mode } | |
d276ec69 | 274 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 275 | #define Mx { OP_M, x_mode } |
c0f3af97 | 276 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 277 | #define Gb { OP_G, b_mode } |
7e8b059b | 278 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
279 | #define Gv { OP_G, v_mode } |
280 | #define Gd { OP_G, d_mode } | |
281 | #define Gdq { OP_G, dq_mode } | |
282 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 283 | #define Gva { OP_G, va_mode } |
ce518a5f | 284 | #define Gw { OP_G, w_mode } |
6f74c397 | 285 | #define Rd { OP_R, d_mode } |
43234a1e | 286 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 287 | #define Rm { OP_R, m_mode } |
ce518a5f L |
288 | #define Ib { OP_I, b_mode } |
289 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 290 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 291 | #define Iv { OP_I, v_mode } |
7bb15c6f | 292 | #define sIv { OP_sI, v_mode } |
ce518a5f | 293 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 294 | #define Id { OP_I, d_mode } |
ce518a5f L |
295 | #define Iw { OP_I, w_mode } |
296 | #define I1 { OP_I, const_1_mode } | |
297 | #define Jb { OP_J, b_mode } | |
298 | #define Jv { OP_J, v_mode } | |
376cd056 | 299 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
300 | #define Cm { OP_C, m_mode } |
301 | #define Dm { OP_D, m_mode } | |
302 | #define Td { OP_T, d_mode } | |
b844680a | 303 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
304 | |
305 | #define RMeAX { OP_REG, eAX_reg } | |
306 | #define RMeBX { OP_REG, eBX_reg } | |
307 | #define RMeCX { OP_REG, eCX_reg } | |
308 | #define RMeDX { OP_REG, eDX_reg } | |
309 | #define RMeSP { OP_REG, eSP_reg } | |
310 | #define RMeBP { OP_REG, eBP_reg } | |
311 | #define RMeSI { OP_REG, eSI_reg } | |
312 | #define RMeDI { OP_REG, eDI_reg } | |
313 | #define RMrAX { OP_REG, rAX_reg } | |
314 | #define RMrBX { OP_REG, rBX_reg } | |
315 | #define RMrCX { OP_REG, rCX_reg } | |
316 | #define RMrDX { OP_REG, rDX_reg } | |
317 | #define RMrSP { OP_REG, rSP_reg } | |
318 | #define RMrBP { OP_REG, rBP_reg } | |
319 | #define RMrSI { OP_REG, rSI_reg } | |
320 | #define RMrDI { OP_REG, rDI_reg } | |
321 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
322 | #define RMCL { OP_REG, cl_reg } |
323 | #define RMDL { OP_REG, dl_reg } | |
324 | #define RMBL { OP_REG, bl_reg } | |
325 | #define RMAH { OP_REG, ah_reg } | |
326 | #define RMCH { OP_REG, ch_reg } | |
327 | #define RMDH { OP_REG, dh_reg } | |
328 | #define RMBH { OP_REG, bh_reg } | |
329 | #define RMAX { OP_REG, ax_reg } | |
330 | #define RMDX { OP_REG, dx_reg } | |
331 | ||
332 | #define eAX { OP_IMREG, eAX_reg } | |
333 | #define eBX { OP_IMREG, eBX_reg } | |
334 | #define eCX { OP_IMREG, eCX_reg } | |
335 | #define eDX { OP_IMREG, eDX_reg } | |
336 | #define eSP { OP_IMREG, eSP_reg } | |
337 | #define eBP { OP_IMREG, eBP_reg } | |
338 | #define eSI { OP_IMREG, eSI_reg } | |
339 | #define eDI { OP_IMREG, eDI_reg } | |
340 | #define AL { OP_IMREG, al_reg } | |
341 | #define CL { OP_IMREG, cl_reg } | |
342 | #define DL { OP_IMREG, dl_reg } | |
343 | #define BL { OP_IMREG, bl_reg } | |
344 | #define AH { OP_IMREG, ah_reg } | |
345 | #define CH { OP_IMREG, ch_reg } | |
346 | #define DH { OP_IMREG, dh_reg } | |
347 | #define BH { OP_IMREG, bh_reg } | |
348 | #define AX { OP_IMREG, ax_reg } | |
349 | #define DX { OP_IMREG, dx_reg } | |
350 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
351 | #define indirDX { OP_IMREG, indir_dx_reg } | |
352 | ||
353 | #define Sw { OP_SEG, w_mode } | |
354 | #define Sv { OP_SEG, v_mode } | |
355 | #define Ap { OP_DIR, 0 } | |
356 | #define Ob { OP_OFF64, b_mode } | |
357 | #define Ov { OP_OFF64, v_mode } | |
358 | #define Xb { OP_DSreg, eSI_reg } | |
359 | #define Xv { OP_DSreg, eSI_reg } | |
360 | #define Xz { OP_DSreg, eSI_reg } | |
361 | #define Yb { OP_ESreg, eDI_reg } | |
362 | #define Yv { OP_ESreg, eDI_reg } | |
363 | #define DSBX { OP_DSreg, eBX_reg } | |
364 | ||
365 | #define es { OP_REG, es_reg } | |
366 | #define ss { OP_REG, ss_reg } | |
367 | #define cs { OP_REG, cs_reg } | |
368 | #define ds { OP_REG, ds_reg } | |
369 | #define fs { OP_REG, fs_reg } | |
370 | #define gs { OP_REG, gs_reg } | |
371 | ||
372 | #define MX { OP_MMX, 0 } | |
373 | #define XM { OP_XMM, 0 } | |
539f890d | 374 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 375 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 376 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 377 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 378 | #define EM { OP_EM, v_mode } |
b6169b20 | 379 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 380 | #define EMd { OP_EM, d_mode } |
14051056 | 381 | #define EMx { OP_EM, x_mode } |
53467f57 | 382 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 383 | #define EXw { OP_EX, w_mode } |
53467f57 | 384 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 385 | #define EXd { OP_EX, d_mode } |
539f890d | 386 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 387 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 388 | #define EXq { OP_EX, q_mode } |
539f890d L |
389 | #define EXqScalar { OP_EX, q_scalar_mode } |
390 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 391 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 392 | #define EXx { OP_EX, x_mode } |
b6169b20 | 393 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 394 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 395 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 396 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 397 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
398 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
399 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
400 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
401 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
402 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
403 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 404 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 405 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
406 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
407 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
408 | #define MS { OP_MS, v_mode } |
409 | #define XS { OP_XS, v_mode } | |
09335d05 | 410 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 411 | #define MXC { OP_MXC, 0 } |
ce518a5f | 412 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 413 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 414 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 415 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 416 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
417 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
418 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 419 | |
c0f3af97 | 420 | #define Vex { OP_VEX, vex_mode } |
539f890d | 421 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 422 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
423 | #define Vex128 { OP_VEX, vex128_mode } |
424 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 425 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 426 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 427 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
428 | #define EXVexW { OP_EX_VexW, x_mode } |
429 | #define EXdVexW { OP_EX_VexW, d_mode } | |
430 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 431 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 432 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 433 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
434 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
435 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 436 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 437 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 438 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
439 | |
440 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 441 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
442 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
443 | ||
444 | #define XMask { OP_Mask, mask_mode } | |
445 | #define MaskG { OP_G, mask_mode } | |
446 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 447 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
448 | #define MaskR { OP_R, mask_mode } |
449 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 450 | |
6c30d220 | 451 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 452 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 453 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 454 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 455 | |
35c52694 | 456 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
457 | #define Xbr { REP_Fixup, eSI_reg } |
458 | #define Xvr { REP_Fixup, eSI_reg } | |
459 | #define Ybr { REP_Fixup, eDI_reg } | |
460 | #define Yvr { REP_Fixup, eDI_reg } | |
461 | #define Yzr { REP_Fixup, eDI_reg } | |
462 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
463 | #define ALr { REP_Fixup, al_reg } | |
464 | #define eAXr { REP_Fixup, eAX_reg } | |
465 | ||
42164a71 L |
466 | /* Used handle HLE prefix for lockable instructions. */ |
467 | #define Ebh1 { HLE_Fixup1, b_mode } | |
468 | #define Evh1 { HLE_Fixup1, v_mode } | |
469 | #define Ebh2 { HLE_Fixup2, b_mode } | |
470 | #define Evh2 { HLE_Fixup2, v_mode } | |
471 | #define Ebh3 { HLE_Fixup3, b_mode } | |
472 | #define Evh3 { HLE_Fixup3, v_mode } | |
473 | ||
7e8b059b | 474 | #define BND { BND_Fixup, 0 } |
04ef582a | 475 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 476 | |
ce518a5f L |
477 | #define cond_jump_flag { NULL, cond_jump_mode } |
478 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 479 | |
252b5132 | 480 | /* bits in sizeflag */ |
252b5132 | 481 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
482 | #define AFLAG 2 |
483 | #define DFLAG 1 | |
484 | ||
51e7da1b L |
485 | enum |
486 | { | |
487 | /* byte operand */ | |
488 | b_mode = 1, | |
489 | /* byte operand with operand swapped */ | |
3873ba12 | 490 | b_swap_mode, |
e3949f17 L |
491 | /* byte operand, sign extend like 'T' suffix */ |
492 | b_T_mode, | |
51e7da1b | 493 | /* operand size depends on prefixes */ |
3873ba12 | 494 | v_mode, |
51e7da1b | 495 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 496 | v_swap_mode, |
de89d0a3 IT |
497 | /* operand size depends on address prefix */ |
498 | va_mode, | |
51e7da1b | 499 | /* word operand */ |
3873ba12 | 500 | w_mode, |
51e7da1b | 501 | /* double word operand */ |
3873ba12 | 502 | d_mode, |
51e7da1b | 503 | /* double word operand with operand swapped */ |
3873ba12 | 504 | d_swap_mode, |
51e7da1b | 505 | /* quad word operand */ |
3873ba12 | 506 | q_mode, |
51e7da1b | 507 | /* quad word operand with operand swapped */ |
3873ba12 | 508 | q_swap_mode, |
51e7da1b | 509 | /* ten-byte operand */ |
3873ba12 | 510 | t_mode, |
43234a1e L |
511 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
512 | broadcast enabled. */ | |
3873ba12 | 513 | x_mode, |
43234a1e L |
514 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
515 | evex_x_gscat_mode, | |
516 | /* Similar to x_mode, but with disabled broadcast. */ | |
517 | evex_x_nobcst_mode, | |
518 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
519 | in EVEX. */ | |
3873ba12 | 520 | x_swap_mode, |
51e7da1b | 521 | /* 16-byte XMM operand */ |
3873ba12 | 522 | xmm_mode, |
43234a1e L |
523 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
524 | memory operand (depending on vector length). Broadcast isn't | |
525 | allowed. */ | |
3873ba12 | 526 | xmmq_mode, |
43234a1e L |
527 | /* Same as xmmq_mode, but broadcast is allowed. */ |
528 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
529 | /* XMM register or byte memory operand */ |
530 | xmm_mb_mode, | |
531 | /* XMM register or word memory operand */ | |
532 | xmm_mw_mode, | |
533 | /* XMM register or double word memory operand */ | |
534 | xmm_md_mode, | |
535 | /* XMM register or quad word memory operand */ | |
536 | xmm_mq_mode, | |
43234a1e | 537 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 538 | xmmdw_mode, |
43234a1e | 539 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 540 | xmmqd_mode, |
43234a1e L |
541 | /* 32-byte YMM operand */ |
542 | ymm_mode, | |
543 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 544 | ymmq_mode, |
6c30d220 L |
545 | /* 32-byte YMM or 16-byte word operand */ |
546 | ymmxmm_mode, | |
51e7da1b | 547 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 548 | m_mode, |
51e7da1b | 549 | /* pair of v_mode operands */ |
3873ba12 L |
550 | a_mode, |
551 | cond_jump_mode, | |
552 | loop_jcxz_mode, | |
bc31405e | 553 | movsxd_mode, |
7e8b059b | 554 | v_bnd_mode, |
d276ec69 JB |
555 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
556 | v_bndmk_mode, | |
51e7da1b | 557 | /* operand size depends on REX prefixes. */ |
3873ba12 | 558 | dq_mode, |
376cd056 JB |
559 | /* registers like dq_mode, memory like w_mode, displacements like |
560 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 561 | dqw_mode, |
9f79e886 | 562 | /* bounds operand */ |
7e8b059b | 563 | bnd_mode, |
9f79e886 JB |
564 | /* bounds operand with operand swapped */ |
565 | bnd_swap_mode, | |
51e7da1b | 566 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
567 | f_mode, |
568 | const_1_mode, | |
07f5af7d L |
569 | /* v_mode for indirect branch opcodes. */ |
570 | indir_v_mode, | |
51e7da1b | 571 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 572 | stack_v_mode, |
51e7da1b | 573 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 574 | z_mode, |
51e7da1b | 575 | /* 16-byte operand */ |
3873ba12 | 576 | o_mode, |
51e7da1b | 577 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 578 | dqb_mode, |
1ba585e8 IT |
579 | /* registers like d_mode, memory like b_mode. */ |
580 | db_mode, | |
581 | /* registers like d_mode, memory like w_mode. */ | |
582 | dw_mode, | |
51e7da1b | 583 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 584 | dqd_mode, |
51e7da1b | 585 | /* normal vex mode */ |
3873ba12 | 586 | vex_mode, |
51e7da1b | 587 | /* 128bit vex mode */ |
3873ba12 | 588 | vex128_mode, |
51e7da1b | 589 | /* 256bit vex mode */ |
3873ba12 | 590 | vex256_mode, |
d55ee72f | 591 | |
825bd36c | 592 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 593 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
594 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
595 | vex_vsib_d_w_d_mode, | |
825bd36c | 596 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 597 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
598 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
599 | vex_vsib_q_w_d_mode, | |
6c30d220 | 600 | |
539f890d L |
601 | /* scalar, ignore vector length. */ |
602 | scalar_mode, | |
53467f57 IT |
603 | /* like b_mode, ignore vector length. */ |
604 | b_scalar_mode, | |
605 | /* like w_mode, ignore vector length. */ | |
606 | w_scalar_mode, | |
539f890d L |
607 | /* like d_mode, ignore vector length. */ |
608 | d_scalar_mode, | |
609 | /* like d_swap_mode, ignore vector length. */ | |
610 | d_scalar_swap_mode, | |
611 | /* like q_mode, ignore vector length. */ | |
612 | q_scalar_mode, | |
613 | /* like q_swap_mode, ignore vector length. */ | |
614 | q_scalar_swap_mode, | |
615 | /* like vex_mode, ignore vector length. */ | |
616 | vex_scalar_mode, | |
825bd36c | 617 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 618 | vex_scalar_w_dq_mode, |
539f890d | 619 | |
43234a1e L |
620 | /* Static rounding. */ |
621 | evex_rounding_mode, | |
70df6fc9 L |
622 | /* Static rounding, 64-bit mode only. */ |
623 | evex_rounding_64_mode, | |
43234a1e L |
624 | /* Supress all exceptions. */ |
625 | evex_sae_mode, | |
626 | ||
627 | /* Mask register operand. */ | |
628 | mask_mode, | |
1ba585e8 IT |
629 | /* Mask register operand. */ |
630 | mask_bd_mode, | |
43234a1e | 631 | |
3873ba12 L |
632 | es_reg, |
633 | cs_reg, | |
634 | ss_reg, | |
635 | ds_reg, | |
636 | fs_reg, | |
637 | gs_reg, | |
d55ee72f | 638 | |
3873ba12 L |
639 | eAX_reg, |
640 | eCX_reg, | |
641 | eDX_reg, | |
642 | eBX_reg, | |
643 | eSP_reg, | |
644 | eBP_reg, | |
645 | eSI_reg, | |
646 | eDI_reg, | |
d55ee72f | 647 | |
3873ba12 L |
648 | al_reg, |
649 | cl_reg, | |
650 | dl_reg, | |
651 | bl_reg, | |
652 | ah_reg, | |
653 | ch_reg, | |
654 | dh_reg, | |
655 | bh_reg, | |
d55ee72f | 656 | |
3873ba12 L |
657 | ax_reg, |
658 | cx_reg, | |
659 | dx_reg, | |
660 | bx_reg, | |
661 | sp_reg, | |
662 | bp_reg, | |
663 | si_reg, | |
664 | di_reg, | |
d55ee72f | 665 | |
3873ba12 L |
666 | rAX_reg, |
667 | rCX_reg, | |
668 | rDX_reg, | |
669 | rBX_reg, | |
670 | rSP_reg, | |
671 | rBP_reg, | |
672 | rSI_reg, | |
673 | rDI_reg, | |
d55ee72f | 674 | |
3873ba12 L |
675 | z_mode_ax_reg, |
676 | indir_dx_reg | |
51e7da1b | 677 | }; |
252b5132 | 678 | |
51e7da1b L |
679 | enum |
680 | { | |
681 | FLOATCODE = 1, | |
3873ba12 L |
682 | USE_REG_TABLE, |
683 | USE_MOD_TABLE, | |
684 | USE_RM_TABLE, | |
685 | USE_PREFIX_TABLE, | |
686 | USE_X86_64_TABLE, | |
687 | USE_3BYTE_TABLE, | |
f88c9eb0 | 688 | USE_XOP_8F_TABLE, |
3873ba12 L |
689 | USE_VEX_C4_TABLE, |
690 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 691 | USE_VEX_LEN_TABLE, |
43234a1e | 692 | USE_VEX_W_TABLE, |
04e2a182 L |
693 | USE_EVEX_TABLE, |
694 | USE_EVEX_LEN_TABLE | |
51e7da1b | 695 | }; |
6439fc28 | 696 | |
bf890a93 | 697 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 698 | |
bf890a93 IT |
699 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
700 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
701 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
702 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
703 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
704 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
705 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
706 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 707 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 708 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
709 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
710 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
711 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 712 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 713 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 714 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 715 | |
51e7da1b L |
716 | enum |
717 | { | |
718 | REG_80 = 0, | |
3873ba12 | 719 | REG_81, |
7148c369 | 720 | REG_83, |
3873ba12 L |
721 | REG_8F, |
722 | REG_C0, | |
723 | REG_C1, | |
724 | REG_C6, | |
725 | REG_C7, | |
726 | REG_D0, | |
727 | REG_D1, | |
728 | REG_D2, | |
729 | REG_D3, | |
730 | REG_F6, | |
731 | REG_F7, | |
732 | REG_FE, | |
733 | REG_FF, | |
734 | REG_0F00, | |
735 | REG_0F01, | |
736 | REG_0F0D, | |
737 | REG_0F18, | |
f8687e93 JB |
738 | REG_0F1C_P_0_MOD_0, |
739 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
740 | REG_0F71, |
741 | REG_0F72, | |
742 | REG_0F73, | |
743 | REG_0FA6, | |
744 | REG_0FA7, | |
745 | REG_0FAE, | |
746 | REG_0FBA, | |
747 | REG_0FC7, | |
592a252b L |
748 | REG_VEX_0F71, |
749 | REG_VEX_0F72, | |
750 | REG_VEX_0F73, | |
751 | REG_VEX_0FAE, | |
f12dc422 | 752 | REG_VEX_0F38F3, |
f88c9eb0 | 753 | REG_XOP_LWPCB, |
2a2a0f38 QN |
754 | REG_XOP_LWP, |
755 | REG_XOP_TBM_01, | |
43234a1e L |
756 | REG_XOP_TBM_02, |
757 | ||
1ba585e8 | 758 | REG_EVEX_0F71, |
43234a1e L |
759 | REG_EVEX_0F72, |
760 | REG_EVEX_0F73, | |
761 | REG_EVEX_0F38C6, | |
762 | REG_EVEX_0F38C7 | |
51e7da1b | 763 | }; |
1ceb70f8 | 764 | |
51e7da1b L |
765 | enum |
766 | { | |
767 | MOD_8D = 0, | |
42164a71 L |
768 | MOD_C6_REG_7, |
769 | MOD_C7_REG_7, | |
4a357820 MZ |
770 | MOD_FF_REG_3, |
771 | MOD_FF_REG_5, | |
3873ba12 L |
772 | MOD_0F01_REG_0, |
773 | MOD_0F01_REG_1, | |
774 | MOD_0F01_REG_2, | |
775 | MOD_0F01_REG_3, | |
8eab4136 | 776 | MOD_0F01_REG_5, |
3873ba12 L |
777 | MOD_0F01_REG_7, |
778 | MOD_0F12_PREFIX_0, | |
18897deb | 779 | MOD_0F12_PREFIX_2, |
3873ba12 L |
780 | MOD_0F13, |
781 | MOD_0F16_PREFIX_0, | |
18897deb | 782 | MOD_0F16_PREFIX_2, |
3873ba12 L |
783 | MOD_0F17, |
784 | MOD_0F18_REG_0, | |
785 | MOD_0F18_REG_1, | |
786 | MOD_0F18_REG_2, | |
787 | MOD_0F18_REG_3, | |
d7189fa5 RM |
788 | MOD_0F18_REG_4, |
789 | MOD_0F18_REG_5, | |
790 | MOD_0F18_REG_6, | |
791 | MOD_0F18_REG_7, | |
7e8b059b L |
792 | MOD_0F1A_PREFIX_0, |
793 | MOD_0F1B_PREFIX_0, | |
794 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 795 | MOD_0F1C_PREFIX_0, |
603555e5 | 796 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
797 | MOD_0F24, |
798 | MOD_0F26, | |
799 | MOD_0F2B_PREFIX_0, | |
800 | MOD_0F2B_PREFIX_1, | |
801 | MOD_0F2B_PREFIX_2, | |
802 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 803 | MOD_0F50, |
3873ba12 L |
804 | MOD_0F71_REG_2, |
805 | MOD_0F71_REG_4, | |
806 | MOD_0F71_REG_6, | |
807 | MOD_0F72_REG_2, | |
808 | MOD_0F72_REG_4, | |
809 | MOD_0F72_REG_6, | |
810 | MOD_0F73_REG_2, | |
811 | MOD_0F73_REG_3, | |
812 | MOD_0F73_REG_6, | |
813 | MOD_0F73_REG_7, | |
814 | MOD_0FAE_REG_0, | |
815 | MOD_0FAE_REG_1, | |
816 | MOD_0FAE_REG_2, | |
817 | MOD_0FAE_REG_3, | |
818 | MOD_0FAE_REG_4, | |
819 | MOD_0FAE_REG_5, | |
820 | MOD_0FAE_REG_6, | |
821 | MOD_0FAE_REG_7, | |
822 | MOD_0FB2, | |
823 | MOD_0FB4, | |
824 | MOD_0FB5, | |
a8484f96 | 825 | MOD_0FC3, |
963f3586 IT |
826 | MOD_0FC7_REG_3, |
827 | MOD_0FC7_REG_4, | |
828 | MOD_0FC7_REG_5, | |
3873ba12 L |
829 | MOD_0FC7_REG_6, |
830 | MOD_0FC7_REG_7, | |
831 | MOD_0FD7, | |
832 | MOD_0FE7_PREFIX_2, | |
833 | MOD_0FF0_PREFIX_3, | |
834 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
835 | MOD_0F38F5_PREFIX_2, |
836 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 837 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 838 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 839 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 840 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
841 | MOD_62_32BIT, |
842 | MOD_C4_32BIT, | |
843 | MOD_C5_32BIT, | |
592a252b | 844 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 845 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
846 | MOD_VEX_0F13, |
847 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 848 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
849 | MOD_VEX_0F17, |
850 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
851 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
852 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
853 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
854 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
855 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
856 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
857 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
858 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
859 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
860 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
861 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
862 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
863 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
864 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
865 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
866 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
867 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
868 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
869 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
870 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
871 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
872 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
873 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
874 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
875 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
876 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
877 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
878 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
879 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
880 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
881 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
882 | MOD_VEX_0F50, |
883 | MOD_VEX_0F71_REG_2, | |
884 | MOD_VEX_0F71_REG_4, | |
885 | MOD_VEX_0F71_REG_6, | |
886 | MOD_VEX_0F72_REG_2, | |
887 | MOD_VEX_0F72_REG_4, | |
888 | MOD_VEX_0F72_REG_6, | |
889 | MOD_VEX_0F73_REG_2, | |
890 | MOD_VEX_0F73_REG_3, | |
891 | MOD_VEX_0F73_REG_6, | |
892 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
893 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
894 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
895 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
896 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
897 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
898 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 899 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
900 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
901 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 902 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
903 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
904 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
905 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
906 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
907 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
908 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
909 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
910 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
911 | MOD_VEX_0FAE_REG_2, |
912 | MOD_VEX_0FAE_REG_3, | |
913 | MOD_VEX_0FD7_PREFIX_2, | |
914 | MOD_VEX_0FE7_PREFIX_2, | |
915 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
916 | MOD_VEX_0F381A_PREFIX_2, |
917 | MOD_VEX_0F382A_PREFIX_2, | |
918 | MOD_VEX_0F382C_PREFIX_2, | |
919 | MOD_VEX_0F382D_PREFIX_2, | |
920 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
921 | MOD_VEX_0F382F_PREFIX_2, |
922 | MOD_VEX_0F385A_PREFIX_2, | |
923 | MOD_VEX_0F388C_PREFIX_2, | |
924 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
925 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
926 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
927 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
928 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
929 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
930 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
931 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
932 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 933 | |
43234a1e | 934 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
935 | MOD_EVEX_0F12_PREFIX_2, |
936 | MOD_EVEX_0F13, | |
43234a1e | 937 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
938 | MOD_EVEX_0F16_PREFIX_2, |
939 | MOD_EVEX_0F17, | |
940 | MOD_EVEX_0F2B, | |
43234a1e L |
941 | MOD_EVEX_0F38C6_REG_1, |
942 | MOD_EVEX_0F38C6_REG_2, | |
943 | MOD_EVEX_0F38C6_REG_5, | |
944 | MOD_EVEX_0F38C6_REG_6, | |
945 | MOD_EVEX_0F38C7_REG_1, | |
946 | MOD_EVEX_0F38C7_REG_2, | |
947 | MOD_EVEX_0F38C7_REG_5, | |
948 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 949 | }; |
1ceb70f8 | 950 | |
51e7da1b L |
951 | enum |
952 | { | |
42164a71 L |
953 | RM_C6_REG_7 = 0, |
954 | RM_C7_REG_7, | |
955 | RM_0F01_REG_0, | |
3873ba12 L |
956 | RM_0F01_REG_1, |
957 | RM_0F01_REG_2, | |
958 | RM_0F01_REG_3, | |
f8687e93 JB |
959 | RM_0F01_REG_5_MOD_3, |
960 | RM_0F01_REG_7_MOD_3, | |
961 | RM_0F1E_P_1_MOD_3_REG_7, | |
962 | RM_0FAE_REG_6_MOD_3_P_0, | |
963 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 964 | }; |
1ceb70f8 | 965 | |
51e7da1b L |
966 | enum |
967 | { | |
968 | PREFIX_90 = 0, | |
a847e322 | 969 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
970 | PREFIX_0F01_REG_5_MOD_0, |
971 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 972 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 973 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
974 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
975 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 976 | PREFIX_0F09, |
3873ba12 L |
977 | PREFIX_0F10, |
978 | PREFIX_0F11, | |
979 | PREFIX_0F12, | |
980 | PREFIX_0F16, | |
7e8b059b L |
981 | PREFIX_0F1A, |
982 | PREFIX_0F1B, | |
c48935d7 | 983 | PREFIX_0F1C, |
603555e5 | 984 | PREFIX_0F1E, |
3873ba12 L |
985 | PREFIX_0F2A, |
986 | PREFIX_0F2B, | |
987 | PREFIX_0F2C, | |
988 | PREFIX_0F2D, | |
989 | PREFIX_0F2E, | |
990 | PREFIX_0F2F, | |
991 | PREFIX_0F51, | |
992 | PREFIX_0F52, | |
993 | PREFIX_0F53, | |
994 | PREFIX_0F58, | |
995 | PREFIX_0F59, | |
996 | PREFIX_0F5A, | |
997 | PREFIX_0F5B, | |
998 | PREFIX_0F5C, | |
999 | PREFIX_0F5D, | |
1000 | PREFIX_0F5E, | |
1001 | PREFIX_0F5F, | |
1002 | PREFIX_0F60, | |
1003 | PREFIX_0F61, | |
1004 | PREFIX_0F62, | |
1005 | PREFIX_0F6C, | |
1006 | PREFIX_0F6D, | |
1007 | PREFIX_0F6F, | |
1008 | PREFIX_0F70, | |
1009 | PREFIX_0F73_REG_3, | |
1010 | PREFIX_0F73_REG_7, | |
1011 | PREFIX_0F78, | |
1012 | PREFIX_0F79, | |
1013 | PREFIX_0F7C, | |
1014 | PREFIX_0F7D, | |
1015 | PREFIX_0F7E, | |
1016 | PREFIX_0F7F, | |
f8687e93 JB |
1017 | PREFIX_0FAE_REG_0_MOD_3, |
1018 | PREFIX_0FAE_REG_1_MOD_3, | |
1019 | PREFIX_0FAE_REG_2_MOD_3, | |
1020 | PREFIX_0FAE_REG_3_MOD_3, | |
1021 | PREFIX_0FAE_REG_4_MOD_0, | |
1022 | PREFIX_0FAE_REG_4_MOD_3, | |
1023 | PREFIX_0FAE_REG_5_MOD_0, | |
1024 | PREFIX_0FAE_REG_5_MOD_3, | |
1025 | PREFIX_0FAE_REG_6_MOD_0, | |
1026 | PREFIX_0FAE_REG_6_MOD_3, | |
1027 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1028 | PREFIX_0FB8, |
f12dc422 | 1029 | PREFIX_0FBC, |
3873ba12 L |
1030 | PREFIX_0FBD, |
1031 | PREFIX_0FC2, | |
f8687e93 JB |
1032 | PREFIX_0FC3_MOD_0, |
1033 | PREFIX_0FC7_REG_6_MOD_0, | |
1034 | PREFIX_0FC7_REG_6_MOD_3, | |
1035 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1036 | PREFIX_0FD0, |
1037 | PREFIX_0FD6, | |
1038 | PREFIX_0FE6, | |
1039 | PREFIX_0FE7, | |
1040 | PREFIX_0FF0, | |
1041 | PREFIX_0FF7, | |
1042 | PREFIX_0F3810, | |
1043 | PREFIX_0F3814, | |
1044 | PREFIX_0F3815, | |
1045 | PREFIX_0F3817, | |
1046 | PREFIX_0F3820, | |
1047 | PREFIX_0F3821, | |
1048 | PREFIX_0F3822, | |
1049 | PREFIX_0F3823, | |
1050 | PREFIX_0F3824, | |
1051 | PREFIX_0F3825, | |
1052 | PREFIX_0F3828, | |
1053 | PREFIX_0F3829, | |
1054 | PREFIX_0F382A, | |
1055 | PREFIX_0F382B, | |
1056 | PREFIX_0F3830, | |
1057 | PREFIX_0F3831, | |
1058 | PREFIX_0F3832, | |
1059 | PREFIX_0F3833, | |
1060 | PREFIX_0F3834, | |
1061 | PREFIX_0F3835, | |
1062 | PREFIX_0F3837, | |
1063 | PREFIX_0F3838, | |
1064 | PREFIX_0F3839, | |
1065 | PREFIX_0F383A, | |
1066 | PREFIX_0F383B, | |
1067 | PREFIX_0F383C, | |
1068 | PREFIX_0F383D, | |
1069 | PREFIX_0F383E, | |
1070 | PREFIX_0F383F, | |
1071 | PREFIX_0F3840, | |
1072 | PREFIX_0F3841, | |
1073 | PREFIX_0F3880, | |
1074 | PREFIX_0F3881, | |
6c30d220 | 1075 | PREFIX_0F3882, |
a0046408 L |
1076 | PREFIX_0F38C8, |
1077 | PREFIX_0F38C9, | |
1078 | PREFIX_0F38CA, | |
1079 | PREFIX_0F38CB, | |
1080 | PREFIX_0F38CC, | |
1081 | PREFIX_0F38CD, | |
48521003 | 1082 | PREFIX_0F38CF, |
3873ba12 L |
1083 | PREFIX_0F38DB, |
1084 | PREFIX_0F38DC, | |
1085 | PREFIX_0F38DD, | |
1086 | PREFIX_0F38DE, | |
1087 | PREFIX_0F38DF, | |
1088 | PREFIX_0F38F0, | |
1089 | PREFIX_0F38F1, | |
603555e5 | 1090 | PREFIX_0F38F5, |
e2e1fcde | 1091 | PREFIX_0F38F6, |
c0a30a9f L |
1092 | PREFIX_0F38F8, |
1093 | PREFIX_0F38F9, | |
3873ba12 L |
1094 | PREFIX_0F3A08, |
1095 | PREFIX_0F3A09, | |
1096 | PREFIX_0F3A0A, | |
1097 | PREFIX_0F3A0B, | |
1098 | PREFIX_0F3A0C, | |
1099 | PREFIX_0F3A0D, | |
1100 | PREFIX_0F3A0E, | |
1101 | PREFIX_0F3A14, | |
1102 | PREFIX_0F3A15, | |
1103 | PREFIX_0F3A16, | |
1104 | PREFIX_0F3A17, | |
1105 | PREFIX_0F3A20, | |
1106 | PREFIX_0F3A21, | |
1107 | PREFIX_0F3A22, | |
1108 | PREFIX_0F3A40, | |
1109 | PREFIX_0F3A41, | |
1110 | PREFIX_0F3A42, | |
1111 | PREFIX_0F3A44, | |
1112 | PREFIX_0F3A60, | |
1113 | PREFIX_0F3A61, | |
1114 | PREFIX_0F3A62, | |
1115 | PREFIX_0F3A63, | |
a0046408 | 1116 | PREFIX_0F3ACC, |
48521003 IT |
1117 | PREFIX_0F3ACE, |
1118 | PREFIX_0F3ACF, | |
3873ba12 | 1119 | PREFIX_0F3ADF, |
592a252b L |
1120 | PREFIX_VEX_0F10, |
1121 | PREFIX_VEX_0F11, | |
1122 | PREFIX_VEX_0F12, | |
1123 | PREFIX_VEX_0F16, | |
1124 | PREFIX_VEX_0F2A, | |
1125 | PREFIX_VEX_0F2C, | |
1126 | PREFIX_VEX_0F2D, | |
1127 | PREFIX_VEX_0F2E, | |
1128 | PREFIX_VEX_0F2F, | |
43234a1e L |
1129 | PREFIX_VEX_0F41, |
1130 | PREFIX_VEX_0F42, | |
1131 | PREFIX_VEX_0F44, | |
1132 | PREFIX_VEX_0F45, | |
1133 | PREFIX_VEX_0F46, | |
1134 | PREFIX_VEX_0F47, | |
1ba585e8 | 1135 | PREFIX_VEX_0F4A, |
43234a1e | 1136 | PREFIX_VEX_0F4B, |
592a252b L |
1137 | PREFIX_VEX_0F51, |
1138 | PREFIX_VEX_0F52, | |
1139 | PREFIX_VEX_0F53, | |
1140 | PREFIX_VEX_0F58, | |
1141 | PREFIX_VEX_0F59, | |
1142 | PREFIX_VEX_0F5A, | |
1143 | PREFIX_VEX_0F5B, | |
1144 | PREFIX_VEX_0F5C, | |
1145 | PREFIX_VEX_0F5D, | |
1146 | PREFIX_VEX_0F5E, | |
1147 | PREFIX_VEX_0F5F, | |
1148 | PREFIX_VEX_0F60, | |
1149 | PREFIX_VEX_0F61, | |
1150 | PREFIX_VEX_0F62, | |
1151 | PREFIX_VEX_0F63, | |
1152 | PREFIX_VEX_0F64, | |
1153 | PREFIX_VEX_0F65, | |
1154 | PREFIX_VEX_0F66, | |
1155 | PREFIX_VEX_0F67, | |
1156 | PREFIX_VEX_0F68, | |
1157 | PREFIX_VEX_0F69, | |
1158 | PREFIX_VEX_0F6A, | |
1159 | PREFIX_VEX_0F6B, | |
1160 | PREFIX_VEX_0F6C, | |
1161 | PREFIX_VEX_0F6D, | |
1162 | PREFIX_VEX_0F6E, | |
1163 | PREFIX_VEX_0F6F, | |
1164 | PREFIX_VEX_0F70, | |
1165 | PREFIX_VEX_0F71_REG_2, | |
1166 | PREFIX_VEX_0F71_REG_4, | |
1167 | PREFIX_VEX_0F71_REG_6, | |
1168 | PREFIX_VEX_0F72_REG_2, | |
1169 | PREFIX_VEX_0F72_REG_4, | |
1170 | PREFIX_VEX_0F72_REG_6, | |
1171 | PREFIX_VEX_0F73_REG_2, | |
1172 | PREFIX_VEX_0F73_REG_3, | |
1173 | PREFIX_VEX_0F73_REG_6, | |
1174 | PREFIX_VEX_0F73_REG_7, | |
1175 | PREFIX_VEX_0F74, | |
1176 | PREFIX_VEX_0F75, | |
1177 | PREFIX_VEX_0F76, | |
1178 | PREFIX_VEX_0F77, | |
1179 | PREFIX_VEX_0F7C, | |
1180 | PREFIX_VEX_0F7D, | |
1181 | PREFIX_VEX_0F7E, | |
1182 | PREFIX_VEX_0F7F, | |
43234a1e L |
1183 | PREFIX_VEX_0F90, |
1184 | PREFIX_VEX_0F91, | |
1185 | PREFIX_VEX_0F92, | |
1186 | PREFIX_VEX_0F93, | |
1187 | PREFIX_VEX_0F98, | |
1ba585e8 | 1188 | PREFIX_VEX_0F99, |
592a252b L |
1189 | PREFIX_VEX_0FC2, |
1190 | PREFIX_VEX_0FC4, | |
1191 | PREFIX_VEX_0FC5, | |
1192 | PREFIX_VEX_0FD0, | |
1193 | PREFIX_VEX_0FD1, | |
1194 | PREFIX_VEX_0FD2, | |
1195 | PREFIX_VEX_0FD3, | |
1196 | PREFIX_VEX_0FD4, | |
1197 | PREFIX_VEX_0FD5, | |
1198 | PREFIX_VEX_0FD6, | |
1199 | PREFIX_VEX_0FD7, | |
1200 | PREFIX_VEX_0FD8, | |
1201 | PREFIX_VEX_0FD9, | |
1202 | PREFIX_VEX_0FDA, | |
1203 | PREFIX_VEX_0FDB, | |
1204 | PREFIX_VEX_0FDC, | |
1205 | PREFIX_VEX_0FDD, | |
1206 | PREFIX_VEX_0FDE, | |
1207 | PREFIX_VEX_0FDF, | |
1208 | PREFIX_VEX_0FE0, | |
1209 | PREFIX_VEX_0FE1, | |
1210 | PREFIX_VEX_0FE2, | |
1211 | PREFIX_VEX_0FE3, | |
1212 | PREFIX_VEX_0FE4, | |
1213 | PREFIX_VEX_0FE5, | |
1214 | PREFIX_VEX_0FE6, | |
1215 | PREFIX_VEX_0FE7, | |
1216 | PREFIX_VEX_0FE8, | |
1217 | PREFIX_VEX_0FE9, | |
1218 | PREFIX_VEX_0FEA, | |
1219 | PREFIX_VEX_0FEB, | |
1220 | PREFIX_VEX_0FEC, | |
1221 | PREFIX_VEX_0FED, | |
1222 | PREFIX_VEX_0FEE, | |
1223 | PREFIX_VEX_0FEF, | |
1224 | PREFIX_VEX_0FF0, | |
1225 | PREFIX_VEX_0FF1, | |
1226 | PREFIX_VEX_0FF2, | |
1227 | PREFIX_VEX_0FF3, | |
1228 | PREFIX_VEX_0FF4, | |
1229 | PREFIX_VEX_0FF5, | |
1230 | PREFIX_VEX_0FF6, | |
1231 | PREFIX_VEX_0FF7, | |
1232 | PREFIX_VEX_0FF8, | |
1233 | PREFIX_VEX_0FF9, | |
1234 | PREFIX_VEX_0FFA, | |
1235 | PREFIX_VEX_0FFB, | |
1236 | PREFIX_VEX_0FFC, | |
1237 | PREFIX_VEX_0FFD, | |
1238 | PREFIX_VEX_0FFE, | |
1239 | PREFIX_VEX_0F3800, | |
1240 | PREFIX_VEX_0F3801, | |
1241 | PREFIX_VEX_0F3802, | |
1242 | PREFIX_VEX_0F3803, | |
1243 | PREFIX_VEX_0F3804, | |
1244 | PREFIX_VEX_0F3805, | |
1245 | PREFIX_VEX_0F3806, | |
1246 | PREFIX_VEX_0F3807, | |
1247 | PREFIX_VEX_0F3808, | |
1248 | PREFIX_VEX_0F3809, | |
1249 | PREFIX_VEX_0F380A, | |
1250 | PREFIX_VEX_0F380B, | |
1251 | PREFIX_VEX_0F380C, | |
1252 | PREFIX_VEX_0F380D, | |
1253 | PREFIX_VEX_0F380E, | |
1254 | PREFIX_VEX_0F380F, | |
1255 | PREFIX_VEX_0F3813, | |
6c30d220 | 1256 | PREFIX_VEX_0F3816, |
592a252b L |
1257 | PREFIX_VEX_0F3817, |
1258 | PREFIX_VEX_0F3818, | |
1259 | PREFIX_VEX_0F3819, | |
1260 | PREFIX_VEX_0F381A, | |
1261 | PREFIX_VEX_0F381C, | |
1262 | PREFIX_VEX_0F381D, | |
1263 | PREFIX_VEX_0F381E, | |
1264 | PREFIX_VEX_0F3820, | |
1265 | PREFIX_VEX_0F3821, | |
1266 | PREFIX_VEX_0F3822, | |
1267 | PREFIX_VEX_0F3823, | |
1268 | PREFIX_VEX_0F3824, | |
1269 | PREFIX_VEX_0F3825, | |
1270 | PREFIX_VEX_0F3828, | |
1271 | PREFIX_VEX_0F3829, | |
1272 | PREFIX_VEX_0F382A, | |
1273 | PREFIX_VEX_0F382B, | |
1274 | PREFIX_VEX_0F382C, | |
1275 | PREFIX_VEX_0F382D, | |
1276 | PREFIX_VEX_0F382E, | |
1277 | PREFIX_VEX_0F382F, | |
1278 | PREFIX_VEX_0F3830, | |
1279 | PREFIX_VEX_0F3831, | |
1280 | PREFIX_VEX_0F3832, | |
1281 | PREFIX_VEX_0F3833, | |
1282 | PREFIX_VEX_0F3834, | |
1283 | PREFIX_VEX_0F3835, | |
6c30d220 | 1284 | PREFIX_VEX_0F3836, |
592a252b L |
1285 | PREFIX_VEX_0F3837, |
1286 | PREFIX_VEX_0F3838, | |
1287 | PREFIX_VEX_0F3839, | |
1288 | PREFIX_VEX_0F383A, | |
1289 | PREFIX_VEX_0F383B, | |
1290 | PREFIX_VEX_0F383C, | |
1291 | PREFIX_VEX_0F383D, | |
1292 | PREFIX_VEX_0F383E, | |
1293 | PREFIX_VEX_0F383F, | |
1294 | PREFIX_VEX_0F3840, | |
1295 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1296 | PREFIX_VEX_0F3845, |
1297 | PREFIX_VEX_0F3846, | |
1298 | PREFIX_VEX_0F3847, | |
1299 | PREFIX_VEX_0F3858, | |
1300 | PREFIX_VEX_0F3859, | |
1301 | PREFIX_VEX_0F385A, | |
1302 | PREFIX_VEX_0F3878, | |
1303 | PREFIX_VEX_0F3879, | |
1304 | PREFIX_VEX_0F388C, | |
1305 | PREFIX_VEX_0F388E, | |
1306 | PREFIX_VEX_0F3890, | |
1307 | PREFIX_VEX_0F3891, | |
1308 | PREFIX_VEX_0F3892, | |
1309 | PREFIX_VEX_0F3893, | |
592a252b L |
1310 | PREFIX_VEX_0F3896, |
1311 | PREFIX_VEX_0F3897, | |
1312 | PREFIX_VEX_0F3898, | |
1313 | PREFIX_VEX_0F3899, | |
1314 | PREFIX_VEX_0F389A, | |
1315 | PREFIX_VEX_0F389B, | |
1316 | PREFIX_VEX_0F389C, | |
1317 | PREFIX_VEX_0F389D, | |
1318 | PREFIX_VEX_0F389E, | |
1319 | PREFIX_VEX_0F389F, | |
1320 | PREFIX_VEX_0F38A6, | |
1321 | PREFIX_VEX_0F38A7, | |
1322 | PREFIX_VEX_0F38A8, | |
1323 | PREFIX_VEX_0F38A9, | |
1324 | PREFIX_VEX_0F38AA, | |
1325 | PREFIX_VEX_0F38AB, | |
1326 | PREFIX_VEX_0F38AC, | |
1327 | PREFIX_VEX_0F38AD, | |
1328 | PREFIX_VEX_0F38AE, | |
1329 | PREFIX_VEX_0F38AF, | |
1330 | PREFIX_VEX_0F38B6, | |
1331 | PREFIX_VEX_0F38B7, | |
1332 | PREFIX_VEX_0F38B8, | |
1333 | PREFIX_VEX_0F38B9, | |
1334 | PREFIX_VEX_0F38BA, | |
1335 | PREFIX_VEX_0F38BB, | |
1336 | PREFIX_VEX_0F38BC, | |
1337 | PREFIX_VEX_0F38BD, | |
1338 | PREFIX_VEX_0F38BE, | |
1339 | PREFIX_VEX_0F38BF, | |
48521003 | 1340 | PREFIX_VEX_0F38CF, |
592a252b L |
1341 | PREFIX_VEX_0F38DB, |
1342 | PREFIX_VEX_0F38DC, | |
1343 | PREFIX_VEX_0F38DD, | |
1344 | PREFIX_VEX_0F38DE, | |
1345 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1346 | PREFIX_VEX_0F38F2, |
1347 | PREFIX_VEX_0F38F3_REG_1, | |
1348 | PREFIX_VEX_0F38F3_REG_2, | |
1349 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1350 | PREFIX_VEX_0F38F5, |
1351 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1352 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1353 | PREFIX_VEX_0F3A00, |
1354 | PREFIX_VEX_0F3A01, | |
1355 | PREFIX_VEX_0F3A02, | |
592a252b L |
1356 | PREFIX_VEX_0F3A04, |
1357 | PREFIX_VEX_0F3A05, | |
1358 | PREFIX_VEX_0F3A06, | |
1359 | PREFIX_VEX_0F3A08, | |
1360 | PREFIX_VEX_0F3A09, | |
1361 | PREFIX_VEX_0F3A0A, | |
1362 | PREFIX_VEX_0F3A0B, | |
1363 | PREFIX_VEX_0F3A0C, | |
1364 | PREFIX_VEX_0F3A0D, | |
1365 | PREFIX_VEX_0F3A0E, | |
1366 | PREFIX_VEX_0F3A0F, | |
1367 | PREFIX_VEX_0F3A14, | |
1368 | PREFIX_VEX_0F3A15, | |
1369 | PREFIX_VEX_0F3A16, | |
1370 | PREFIX_VEX_0F3A17, | |
1371 | PREFIX_VEX_0F3A18, | |
1372 | PREFIX_VEX_0F3A19, | |
1373 | PREFIX_VEX_0F3A1D, | |
1374 | PREFIX_VEX_0F3A20, | |
1375 | PREFIX_VEX_0F3A21, | |
1376 | PREFIX_VEX_0F3A22, | |
43234a1e | 1377 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1378 | PREFIX_VEX_0F3A31, |
43234a1e | 1379 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1380 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1381 | PREFIX_VEX_0F3A38, |
1382 | PREFIX_VEX_0F3A39, | |
592a252b L |
1383 | PREFIX_VEX_0F3A40, |
1384 | PREFIX_VEX_0F3A41, | |
1385 | PREFIX_VEX_0F3A42, | |
1386 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1387 | PREFIX_VEX_0F3A46, |
592a252b L |
1388 | PREFIX_VEX_0F3A48, |
1389 | PREFIX_VEX_0F3A49, | |
1390 | PREFIX_VEX_0F3A4A, | |
1391 | PREFIX_VEX_0F3A4B, | |
1392 | PREFIX_VEX_0F3A4C, | |
1393 | PREFIX_VEX_0F3A5C, | |
1394 | PREFIX_VEX_0F3A5D, | |
1395 | PREFIX_VEX_0F3A5E, | |
1396 | PREFIX_VEX_0F3A5F, | |
1397 | PREFIX_VEX_0F3A60, | |
1398 | PREFIX_VEX_0F3A61, | |
1399 | PREFIX_VEX_0F3A62, | |
1400 | PREFIX_VEX_0F3A63, | |
1401 | PREFIX_VEX_0F3A68, | |
1402 | PREFIX_VEX_0F3A69, | |
1403 | PREFIX_VEX_0F3A6A, | |
1404 | PREFIX_VEX_0F3A6B, | |
1405 | PREFIX_VEX_0F3A6C, | |
1406 | PREFIX_VEX_0F3A6D, | |
1407 | PREFIX_VEX_0F3A6E, | |
1408 | PREFIX_VEX_0F3A6F, | |
1409 | PREFIX_VEX_0F3A78, | |
1410 | PREFIX_VEX_0F3A79, | |
1411 | PREFIX_VEX_0F3A7A, | |
1412 | PREFIX_VEX_0F3A7B, | |
1413 | PREFIX_VEX_0F3A7C, | |
1414 | PREFIX_VEX_0F3A7D, | |
1415 | PREFIX_VEX_0F3A7E, | |
1416 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1417 | PREFIX_VEX_0F3ACE, |
1418 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1419 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1420 | PREFIX_VEX_0F3AF0, |
1421 | ||
1422 | PREFIX_EVEX_0F10, | |
1423 | PREFIX_EVEX_0F11, | |
1424 | PREFIX_EVEX_0F12, | |
43234a1e | 1425 | PREFIX_EVEX_0F16, |
43234a1e | 1426 | PREFIX_EVEX_0F2A, |
43234a1e L |
1427 | PREFIX_EVEX_0F2C, |
1428 | PREFIX_EVEX_0F2D, | |
1429 | PREFIX_EVEX_0F2E, | |
1430 | PREFIX_EVEX_0F2F, | |
1431 | PREFIX_EVEX_0F51, | |
1432 | PREFIX_EVEX_0F58, | |
1433 | PREFIX_EVEX_0F59, | |
1434 | PREFIX_EVEX_0F5A, | |
1435 | PREFIX_EVEX_0F5B, | |
1436 | PREFIX_EVEX_0F5C, | |
1437 | PREFIX_EVEX_0F5D, | |
1438 | PREFIX_EVEX_0F5E, | |
1439 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1440 | PREFIX_EVEX_0F60, |
1441 | PREFIX_EVEX_0F61, | |
43234a1e | 1442 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1443 | PREFIX_EVEX_0F63, |
1444 | PREFIX_EVEX_0F64, | |
1445 | PREFIX_EVEX_0F65, | |
43234a1e | 1446 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1447 | PREFIX_EVEX_0F67, |
1448 | PREFIX_EVEX_0F68, | |
1449 | PREFIX_EVEX_0F69, | |
43234a1e | 1450 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1451 | PREFIX_EVEX_0F6B, |
43234a1e L |
1452 | PREFIX_EVEX_0F6C, |
1453 | PREFIX_EVEX_0F6D, | |
1454 | PREFIX_EVEX_0F6E, | |
1455 | PREFIX_EVEX_0F6F, | |
1456 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1457 | PREFIX_EVEX_0F71_REG_2, |
1458 | PREFIX_EVEX_0F71_REG_4, | |
1459 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1460 | PREFIX_EVEX_0F72_REG_0, |
1461 | PREFIX_EVEX_0F72_REG_1, | |
1462 | PREFIX_EVEX_0F72_REG_2, | |
1463 | PREFIX_EVEX_0F72_REG_4, | |
1464 | PREFIX_EVEX_0F72_REG_6, | |
1465 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1466 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1467 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1468 | PREFIX_EVEX_0F73_REG_7, |
1469 | PREFIX_EVEX_0F74, | |
1470 | PREFIX_EVEX_0F75, | |
43234a1e L |
1471 | PREFIX_EVEX_0F76, |
1472 | PREFIX_EVEX_0F78, | |
1473 | PREFIX_EVEX_0F79, | |
1474 | PREFIX_EVEX_0F7A, | |
1475 | PREFIX_EVEX_0F7B, | |
1476 | PREFIX_EVEX_0F7E, | |
1477 | PREFIX_EVEX_0F7F, | |
1478 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1479 | PREFIX_EVEX_0FC4, |
1480 | PREFIX_EVEX_0FC5, | |
1ba585e8 | 1481 | PREFIX_EVEX_0FD1, |
43234a1e L |
1482 | PREFIX_EVEX_0FD2, |
1483 | PREFIX_EVEX_0FD3, | |
1484 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1485 | PREFIX_EVEX_0FD5, |
43234a1e | 1486 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1487 | PREFIX_EVEX_0FD8, |
1488 | PREFIX_EVEX_0FD9, | |
1489 | PREFIX_EVEX_0FDA, | |
43234a1e | 1490 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1491 | PREFIX_EVEX_0FDC, |
1492 | PREFIX_EVEX_0FDD, | |
1493 | PREFIX_EVEX_0FDE, | |
43234a1e | 1494 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1495 | PREFIX_EVEX_0FE0, |
1496 | PREFIX_EVEX_0FE1, | |
43234a1e | 1497 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1498 | PREFIX_EVEX_0FE3, |
1499 | PREFIX_EVEX_0FE4, | |
1500 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1501 | PREFIX_EVEX_0FE6, |
1502 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1503 | PREFIX_EVEX_0FE8, |
1504 | PREFIX_EVEX_0FE9, | |
1505 | PREFIX_EVEX_0FEA, | |
43234a1e | 1506 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1507 | PREFIX_EVEX_0FEC, |
1508 | PREFIX_EVEX_0FED, | |
1509 | PREFIX_EVEX_0FEE, | |
43234a1e | 1510 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1511 | PREFIX_EVEX_0FF1, |
43234a1e L |
1512 | PREFIX_EVEX_0FF2, |
1513 | PREFIX_EVEX_0FF3, | |
1514 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1515 | PREFIX_EVEX_0FF5, |
1516 | PREFIX_EVEX_0FF6, | |
1517 | PREFIX_EVEX_0FF8, | |
1518 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1519 | PREFIX_EVEX_0FFA, |
1520 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1521 | PREFIX_EVEX_0FFC, |
1522 | PREFIX_EVEX_0FFD, | |
43234a1e | 1523 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1524 | PREFIX_EVEX_0F3800, |
1525 | PREFIX_EVEX_0F3804, | |
1526 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1527 | PREFIX_EVEX_0F380C, |
1528 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1529 | PREFIX_EVEX_0F3810, |
43234a1e L |
1530 | PREFIX_EVEX_0F3811, |
1531 | PREFIX_EVEX_0F3812, | |
1532 | PREFIX_EVEX_0F3813, | |
1533 | PREFIX_EVEX_0F3814, | |
1534 | PREFIX_EVEX_0F3815, | |
1535 | PREFIX_EVEX_0F3816, | |
1536 | PREFIX_EVEX_0F3818, | |
1537 | PREFIX_EVEX_0F3819, | |
1538 | PREFIX_EVEX_0F381A, | |
1539 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1540 | PREFIX_EVEX_0F381C, |
1541 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1542 | PREFIX_EVEX_0F381E, |
1543 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1544 | PREFIX_EVEX_0F3820, |
43234a1e L |
1545 | PREFIX_EVEX_0F3821, |
1546 | PREFIX_EVEX_0F3822, | |
1547 | PREFIX_EVEX_0F3823, | |
1548 | PREFIX_EVEX_0F3824, | |
1549 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1550 | PREFIX_EVEX_0F3826, |
43234a1e L |
1551 | PREFIX_EVEX_0F3827, |
1552 | PREFIX_EVEX_0F3828, | |
1553 | PREFIX_EVEX_0F3829, | |
1554 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1555 | PREFIX_EVEX_0F382B, |
43234a1e L |
1556 | PREFIX_EVEX_0F382C, |
1557 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1558 | PREFIX_EVEX_0F3830, |
43234a1e L |
1559 | PREFIX_EVEX_0F3831, |
1560 | PREFIX_EVEX_0F3832, | |
1561 | PREFIX_EVEX_0F3833, | |
1562 | PREFIX_EVEX_0F3834, | |
1563 | PREFIX_EVEX_0F3835, | |
1564 | PREFIX_EVEX_0F3836, | |
1565 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1566 | PREFIX_EVEX_0F3838, |
43234a1e L |
1567 | PREFIX_EVEX_0F3839, |
1568 | PREFIX_EVEX_0F383A, | |
1569 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1570 | PREFIX_EVEX_0F383C, |
43234a1e | 1571 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1572 | PREFIX_EVEX_0F383E, |
43234a1e L |
1573 | PREFIX_EVEX_0F383F, |
1574 | PREFIX_EVEX_0F3840, | |
1575 | PREFIX_EVEX_0F3842, | |
1576 | PREFIX_EVEX_0F3843, | |
1577 | PREFIX_EVEX_0F3844, | |
1578 | PREFIX_EVEX_0F3845, | |
1579 | PREFIX_EVEX_0F3846, | |
1580 | PREFIX_EVEX_0F3847, | |
1581 | PREFIX_EVEX_0F384C, | |
1582 | PREFIX_EVEX_0F384D, | |
1583 | PREFIX_EVEX_0F384E, | |
1584 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1585 | PREFIX_EVEX_0F3850, |
1586 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1587 | PREFIX_EVEX_0F3852, |
1588 | PREFIX_EVEX_0F3853, | |
ee6872be | 1589 | PREFIX_EVEX_0F3854, |
620214f7 | 1590 | PREFIX_EVEX_0F3855, |
43234a1e L |
1591 | PREFIX_EVEX_0F3858, |
1592 | PREFIX_EVEX_0F3859, | |
1593 | PREFIX_EVEX_0F385A, | |
1594 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1595 | PREFIX_EVEX_0F3862, |
1596 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1597 | PREFIX_EVEX_0F3864, |
1598 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1599 | PREFIX_EVEX_0F3866, |
9186c494 | 1600 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1601 | PREFIX_EVEX_0F3870, |
1602 | PREFIX_EVEX_0F3871, | |
1603 | PREFIX_EVEX_0F3872, | |
1604 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1605 | PREFIX_EVEX_0F3875, |
43234a1e L |
1606 | PREFIX_EVEX_0F3876, |
1607 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1608 | PREFIX_EVEX_0F3878, |
1609 | PREFIX_EVEX_0F3879, | |
1610 | PREFIX_EVEX_0F387A, | |
1611 | PREFIX_EVEX_0F387B, | |
43234a1e | 1612 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1613 | PREFIX_EVEX_0F387D, |
43234a1e L |
1614 | PREFIX_EVEX_0F387E, |
1615 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1616 | PREFIX_EVEX_0F3883, |
43234a1e L |
1617 | PREFIX_EVEX_0F3888, |
1618 | PREFIX_EVEX_0F3889, | |
1619 | PREFIX_EVEX_0F388A, | |
1620 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1621 | PREFIX_EVEX_0F388D, |
ee6872be | 1622 | PREFIX_EVEX_0F388F, |
43234a1e L |
1623 | PREFIX_EVEX_0F3890, |
1624 | PREFIX_EVEX_0F3891, | |
1625 | PREFIX_EVEX_0F3892, | |
1626 | PREFIX_EVEX_0F3893, | |
1627 | PREFIX_EVEX_0F3896, | |
1628 | PREFIX_EVEX_0F3897, | |
1629 | PREFIX_EVEX_0F3898, | |
1630 | PREFIX_EVEX_0F3899, | |
1631 | PREFIX_EVEX_0F389A, | |
1632 | PREFIX_EVEX_0F389B, | |
1633 | PREFIX_EVEX_0F389C, | |
1634 | PREFIX_EVEX_0F389D, | |
1635 | PREFIX_EVEX_0F389E, | |
1636 | PREFIX_EVEX_0F389F, | |
1637 | PREFIX_EVEX_0F38A0, | |
1638 | PREFIX_EVEX_0F38A1, | |
1639 | PREFIX_EVEX_0F38A2, | |
1640 | PREFIX_EVEX_0F38A3, | |
1641 | PREFIX_EVEX_0F38A6, | |
1642 | PREFIX_EVEX_0F38A7, | |
1643 | PREFIX_EVEX_0F38A8, | |
1644 | PREFIX_EVEX_0F38A9, | |
1645 | PREFIX_EVEX_0F38AA, | |
1646 | PREFIX_EVEX_0F38AB, | |
1647 | PREFIX_EVEX_0F38AC, | |
1648 | PREFIX_EVEX_0F38AD, | |
1649 | PREFIX_EVEX_0F38AE, | |
1650 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1651 | PREFIX_EVEX_0F38B4, |
1652 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1653 | PREFIX_EVEX_0F38B6, |
1654 | PREFIX_EVEX_0F38B7, | |
1655 | PREFIX_EVEX_0F38B8, | |
1656 | PREFIX_EVEX_0F38B9, | |
1657 | PREFIX_EVEX_0F38BA, | |
1658 | PREFIX_EVEX_0F38BB, | |
1659 | PREFIX_EVEX_0F38BC, | |
1660 | PREFIX_EVEX_0F38BD, | |
1661 | PREFIX_EVEX_0F38BE, | |
1662 | PREFIX_EVEX_0F38BF, | |
1663 | PREFIX_EVEX_0F38C4, | |
1664 | PREFIX_EVEX_0F38C6_REG_1, | |
1665 | PREFIX_EVEX_0F38C6_REG_2, | |
1666 | PREFIX_EVEX_0F38C6_REG_5, | |
1667 | PREFIX_EVEX_0F38C6_REG_6, | |
1668 | PREFIX_EVEX_0F38C7_REG_1, | |
1669 | PREFIX_EVEX_0F38C7_REG_2, | |
1670 | PREFIX_EVEX_0F38C7_REG_5, | |
1671 | PREFIX_EVEX_0F38C7_REG_6, | |
1672 | PREFIX_EVEX_0F38C8, | |
1673 | PREFIX_EVEX_0F38CA, | |
1674 | PREFIX_EVEX_0F38CB, | |
1675 | PREFIX_EVEX_0F38CC, | |
1676 | PREFIX_EVEX_0F38CD, | |
48521003 | 1677 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1678 | PREFIX_EVEX_0F38DC, |
1679 | PREFIX_EVEX_0F38DD, | |
1680 | PREFIX_EVEX_0F38DE, | |
1681 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1682 | |
1683 | PREFIX_EVEX_0F3A00, | |
1684 | PREFIX_EVEX_0F3A01, | |
1685 | PREFIX_EVEX_0F3A03, | |
1686 | PREFIX_EVEX_0F3A04, | |
1687 | PREFIX_EVEX_0F3A05, | |
1688 | PREFIX_EVEX_0F3A08, | |
1689 | PREFIX_EVEX_0F3A09, | |
1690 | PREFIX_EVEX_0F3A0A, | |
1691 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1692 | PREFIX_EVEX_0F3A0F, |
1693 | PREFIX_EVEX_0F3A14, | |
1694 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1695 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1696 | PREFIX_EVEX_0F3A17, |
1697 | PREFIX_EVEX_0F3A18, | |
1698 | PREFIX_EVEX_0F3A19, | |
1699 | PREFIX_EVEX_0F3A1A, | |
1700 | PREFIX_EVEX_0F3A1B, | |
1701 | PREFIX_EVEX_0F3A1D, | |
1702 | PREFIX_EVEX_0F3A1E, | |
1703 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1704 | PREFIX_EVEX_0F3A20, |
43234a1e | 1705 | PREFIX_EVEX_0F3A21, |
90a915bf | 1706 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1707 | PREFIX_EVEX_0F3A23, |
1708 | PREFIX_EVEX_0F3A25, | |
1709 | PREFIX_EVEX_0F3A26, | |
1710 | PREFIX_EVEX_0F3A27, | |
1711 | PREFIX_EVEX_0F3A38, | |
1712 | PREFIX_EVEX_0F3A39, | |
1713 | PREFIX_EVEX_0F3A3A, | |
1714 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1715 | PREFIX_EVEX_0F3A3E, |
1716 | PREFIX_EVEX_0F3A3F, | |
1717 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1718 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1719 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1720 | PREFIX_EVEX_0F3A50, |
1721 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1722 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1723 | PREFIX_EVEX_0F3A55, |
1724 | PREFIX_EVEX_0F3A56, | |
1725 | PREFIX_EVEX_0F3A57, | |
1726 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1727 | PREFIX_EVEX_0F3A67, |
1728 | PREFIX_EVEX_0F3A70, | |
1729 | PREFIX_EVEX_0F3A71, | |
1730 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1731 | PREFIX_EVEX_0F3A73, |
1732 | PREFIX_EVEX_0F3ACE, | |
1733 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1734 | }; |
4e7d34a6 | 1735 | |
51e7da1b L |
1736 | enum |
1737 | { | |
1738 | X86_64_06 = 0, | |
3873ba12 | 1739 | X86_64_07, |
1673df32 | 1740 | X86_64_0E, |
3873ba12 L |
1741 | X86_64_16, |
1742 | X86_64_17, | |
1743 | X86_64_1E, | |
1744 | X86_64_1F, | |
1745 | X86_64_27, | |
1746 | X86_64_2F, | |
1747 | X86_64_37, | |
1748 | X86_64_3F, | |
1749 | X86_64_60, | |
1750 | X86_64_61, | |
1751 | X86_64_62, | |
1752 | X86_64_63, | |
1753 | X86_64_6D, | |
1754 | X86_64_6F, | |
d039fef3 | 1755 | X86_64_82, |
3873ba12 | 1756 | X86_64_9A, |
aeab2b26 JB |
1757 | X86_64_C2, |
1758 | X86_64_C3, | |
3873ba12 L |
1759 | X86_64_C4, |
1760 | X86_64_C5, | |
1761 | X86_64_CE, | |
1762 | X86_64_D4, | |
1763 | X86_64_D5, | |
a72d2af2 L |
1764 | X86_64_E8, |
1765 | X86_64_E9, | |
3873ba12 L |
1766 | X86_64_EA, |
1767 | X86_64_0F01_REG_0, | |
1768 | X86_64_0F01_REG_1, | |
1769 | X86_64_0F01_REG_2, | |
1770 | X86_64_0F01_REG_3 | |
51e7da1b | 1771 | }; |
4e7d34a6 | 1772 | |
51e7da1b L |
1773 | enum |
1774 | { | |
1775 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1776 | THREE_BYTE_0F3A |
51e7da1b | 1777 | }; |
4e7d34a6 | 1778 | |
f88c9eb0 SP |
1779 | enum |
1780 | { | |
5dd85c99 SP |
1781 | XOP_08 = 0, |
1782 | XOP_09, | |
f88c9eb0 SP |
1783 | XOP_0A |
1784 | }; | |
1785 | ||
51e7da1b L |
1786 | enum |
1787 | { | |
1788 | VEX_0F = 0, | |
3873ba12 L |
1789 | VEX_0F38, |
1790 | VEX_0F3A | |
51e7da1b | 1791 | }; |
c0f3af97 | 1792 | |
43234a1e L |
1793 | enum |
1794 | { | |
1795 | EVEX_0F = 0, | |
1796 | EVEX_0F38, | |
1797 | EVEX_0F3A | |
1798 | }; | |
1799 | ||
51e7da1b L |
1800 | enum |
1801 | { | |
ec6f095a | 1802 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1803 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1804 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1805 | VEX_LEN_0F13_M_0, |
1806 | VEX_LEN_0F16_P_0_M_0, | |
1807 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1808 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1809 | VEX_LEN_0F17_M_0, |
43234a1e | 1810 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1811 | VEX_LEN_0F41_P_2, |
43234a1e | 1812 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1813 | VEX_LEN_0F42_P_2, |
43234a1e | 1814 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1815 | VEX_LEN_0F44_P_2, |
43234a1e | 1816 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1817 | VEX_LEN_0F45_P_2, |
43234a1e | 1818 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1819 | VEX_LEN_0F46_P_2, |
43234a1e | 1820 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1821 | VEX_LEN_0F47_P_2, |
1822 | VEX_LEN_0F4A_P_0, | |
1823 | VEX_LEN_0F4A_P_2, | |
1824 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1825 | VEX_LEN_0F4B_P_2, |
592a252b | 1826 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1827 | VEX_LEN_0F77_P_0, |
592a252b L |
1828 | VEX_LEN_0F7E_P_1, |
1829 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1830 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1831 | VEX_LEN_0F90_P_2, |
43234a1e | 1832 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1833 | VEX_LEN_0F91_P_2, |
43234a1e | 1834 | VEX_LEN_0F92_P_0, |
90a915bf | 1835 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1836 | VEX_LEN_0F92_P_3, |
43234a1e | 1837 | VEX_LEN_0F93_P_0, |
90a915bf | 1838 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1839 | VEX_LEN_0F93_P_3, |
43234a1e | 1840 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1841 | VEX_LEN_0F98_P_2, |
1842 | VEX_LEN_0F99_P_0, | |
1843 | VEX_LEN_0F99_P_2, | |
592a252b L |
1844 | VEX_LEN_0FAE_R_2_M_0, |
1845 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1846 | VEX_LEN_0FC4_P_2, |
1847 | VEX_LEN_0FC5_P_2, | |
592a252b | 1848 | VEX_LEN_0FD6_P_2, |
592a252b | 1849 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1850 | VEX_LEN_0F3816_P_2, |
1851 | VEX_LEN_0F3819_P_2, | |
592a252b | 1852 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1853 | VEX_LEN_0F3836_P_2, |
592a252b | 1854 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1855 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1856 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1857 | VEX_LEN_0F38F2_P_0, |
1858 | VEX_LEN_0F38F3_R_1_P_0, | |
1859 | VEX_LEN_0F38F3_R_2_P_0, | |
1860 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1861 | VEX_LEN_0F38F5_P_0, |
1862 | VEX_LEN_0F38F5_P_1, | |
1863 | VEX_LEN_0F38F5_P_3, | |
1864 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1865 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1866 | VEX_LEN_0F38F7_P_1, |
1867 | VEX_LEN_0F38F7_P_2, | |
1868 | VEX_LEN_0F38F7_P_3, | |
1869 | VEX_LEN_0F3A00_P_2, | |
1870 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1871 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1872 | VEX_LEN_0F3A14_P_2, |
1873 | VEX_LEN_0F3A15_P_2, | |
1874 | VEX_LEN_0F3A16_P_2, | |
1875 | VEX_LEN_0F3A17_P_2, | |
1876 | VEX_LEN_0F3A18_P_2, | |
1877 | VEX_LEN_0F3A19_P_2, | |
1878 | VEX_LEN_0F3A20_P_2, | |
1879 | VEX_LEN_0F3A21_P_2, | |
1880 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1881 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1882 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1883 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1884 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1885 | VEX_LEN_0F3A38_P_2, |
1886 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1887 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1888 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1889 | VEX_LEN_0F3A60_P_2, |
1890 | VEX_LEN_0F3A61_P_2, | |
1891 | VEX_LEN_0F3A62_P_2, | |
1892 | VEX_LEN_0F3A63_P_2, | |
1893 | VEX_LEN_0F3A6A_P_2, | |
1894 | VEX_LEN_0F3A6B_P_2, | |
1895 | VEX_LEN_0F3A6E_P_2, | |
1896 | VEX_LEN_0F3A6F_P_2, | |
1897 | VEX_LEN_0F3A7A_P_2, | |
1898 | VEX_LEN_0F3A7B_P_2, | |
1899 | VEX_LEN_0F3A7E_P_2, | |
1900 | VEX_LEN_0F3A7F_P_2, | |
1901 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1902 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1903 | VEX_LEN_0FXOP_08_CC, |
1904 | VEX_LEN_0FXOP_08_CD, | |
1905 | VEX_LEN_0FXOP_08_CE, | |
1906 | VEX_LEN_0FXOP_08_CF, | |
1907 | VEX_LEN_0FXOP_08_EC, | |
1908 | VEX_LEN_0FXOP_08_ED, | |
1909 | VEX_LEN_0FXOP_08_EE, | |
1910 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1911 | VEX_LEN_0FXOP_09_80, |
1912 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1913 | }; |
c0f3af97 | 1914 | |
04e2a182 L |
1915 | enum |
1916 | { | |
1917 | EVEX_LEN_0F6E_P_2 = 0, | |
1918 | EVEX_LEN_0F7E_P_1, | |
1919 | EVEX_LEN_0F7E_P_2, | |
12efd68d | 1920 | EVEX_LEN_0FD6_P_2, |
f0a6222e L |
1921 | EVEX_LEN_0F3819_P_2_W_0, |
1922 | EVEX_LEN_0F3819_P_2_W_1, | |
1923 | EVEX_LEN_0F381A_P_2_W_0, | |
1924 | EVEX_LEN_0F381A_P_2_W_1, | |
1925 | EVEX_LEN_0F381B_P_2_W_0, | |
1926 | EVEX_LEN_0F381B_P_2_W_1, | |
1927 | EVEX_LEN_0F385A_P_2_W_0, | |
1928 | EVEX_LEN_0F385A_P_2_W_1, | |
1929 | EVEX_LEN_0F385B_P_2_W_0, | |
1930 | EVEX_LEN_0F385B_P_2_W_1, | |
e395f487 L |
1931 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1932 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1933 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1934 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1935 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1936 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1937 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1938 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1939 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1940 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1941 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1942 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
12efd68d L |
1943 | EVEX_LEN_0F3A18_P_2_W_0, |
1944 | EVEX_LEN_0F3A18_P_2_W_1, | |
1945 | EVEX_LEN_0F3A19_P_2_W_0, | |
1946 | EVEX_LEN_0F3A19_P_2_W_1, | |
1947 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1948 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1949 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 L |
1950 | EVEX_LEN_0F3A1B_P_2_W_1, |
1951 | EVEX_LEN_0F3A23_P_2_W_0, | |
1952 | EVEX_LEN_0F3A23_P_2_W_1, | |
1953 | EVEX_LEN_0F3A38_P_2_W_0, | |
1954 | EVEX_LEN_0F3A38_P_2_W_1, | |
1955 | EVEX_LEN_0F3A39_P_2_W_0, | |
1956 | EVEX_LEN_0F3A39_P_2_W_1, | |
1957 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1958 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1959 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1960 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1961 | EVEX_LEN_0F3A43_P_2_W_0, | |
1962 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1963 | }; |
1964 | ||
9e30b8e0 L |
1965 | enum |
1966 | { | |
ec6f095a | 1967 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1968 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1969 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1970 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1971 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1972 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1973 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1974 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1975 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1976 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1977 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1978 | VEX_W_0F47_P_2_LEN_1, |
1979 | VEX_W_0F4A_P_0_LEN_1, | |
1980 | VEX_W_0F4A_P_2_LEN_1, | |
1981 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1982 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1983 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1984 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1985 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1986 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1987 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1988 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1989 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1990 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1991 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1992 | VEX_W_0F98_P_2_LEN_0, |
1993 | VEX_W_0F99_P_0_LEN_0, | |
1994 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1995 | VEX_W_0F380C_P_2, |
1996 | VEX_W_0F380D_P_2, | |
1997 | VEX_W_0F380E_P_2, | |
1998 | VEX_W_0F380F_P_2, | |
6c30d220 | 1999 | VEX_W_0F3816_P_2, |
6c30d220 L |
2000 | VEX_W_0F3818_P_2, |
2001 | VEX_W_0F3819_P_2, | |
592a252b | 2002 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
2003 | VEX_W_0F382C_P_2_M_0, |
2004 | VEX_W_0F382D_P_2_M_0, | |
2005 | VEX_W_0F382E_P_2_M_0, | |
2006 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 2007 | VEX_W_0F3836_P_2, |
6c30d220 L |
2008 | VEX_W_0F3846_P_2, |
2009 | VEX_W_0F3858_P_2, | |
2010 | VEX_W_0F3859_P_2, | |
2011 | VEX_W_0F385A_P_2_M_0, | |
2012 | VEX_W_0F3878_P_2, | |
2013 | VEX_W_0F3879_P_2, | |
48521003 | 2014 | VEX_W_0F38CF_P_2, |
6c30d220 L |
2015 | VEX_W_0F3A00_P_2, |
2016 | VEX_W_0F3A01_P_2, | |
2017 | VEX_W_0F3A02_P_2, | |
592a252b L |
2018 | VEX_W_0F3A04_P_2, |
2019 | VEX_W_0F3A05_P_2, | |
2020 | VEX_W_0F3A06_P_2, | |
592a252b L |
2021 | VEX_W_0F3A18_P_2, |
2022 | VEX_W_0F3A19_P_2, | |
43234a1e | 2023 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2024 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2025 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2026 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2027 | VEX_W_0F3A38_P_2, |
2028 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2029 | VEX_W_0F3A46_P_2, |
592a252b L |
2030 | VEX_W_0F3A48_P_2, |
2031 | VEX_W_0F3A49_P_2, | |
2032 | VEX_W_0F3A4A_P_2, | |
2033 | VEX_W_0F3A4B_P_2, | |
2034 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2035 | VEX_W_0F3ACE_P_2, |
2036 | VEX_W_0F3ACF_P_2, | |
43234a1e | 2037 | |
36cc073e | 2038 | EVEX_W_0F10_P_1, |
36cc073e | 2039 | EVEX_W_0F10_P_3, |
36cc073e | 2040 | EVEX_W_0F11_P_1, |
36cc073e | 2041 | EVEX_W_0F11_P_3, |
43234a1e L |
2042 | EVEX_W_0F12_P_0_M_1, |
2043 | EVEX_W_0F12_P_1, | |
43234a1e | 2044 | EVEX_W_0F12_P_3, |
43234a1e L |
2045 | EVEX_W_0F16_P_0_M_1, |
2046 | EVEX_W_0F16_P_1, | |
43234a1e | 2047 | EVEX_W_0F2A_P_3, |
43234a1e | 2048 | EVEX_W_0F51_P_1, |
43234a1e | 2049 | EVEX_W_0F51_P_3, |
43234a1e | 2050 | EVEX_W_0F58_P_1, |
43234a1e | 2051 | EVEX_W_0F58_P_3, |
43234a1e | 2052 | EVEX_W_0F59_P_1, |
43234a1e L |
2053 | EVEX_W_0F59_P_3, |
2054 | EVEX_W_0F5A_P_0, | |
2055 | EVEX_W_0F5A_P_1, | |
2056 | EVEX_W_0F5A_P_2, | |
2057 | EVEX_W_0F5A_P_3, | |
2058 | EVEX_W_0F5B_P_0, | |
2059 | EVEX_W_0F5B_P_1, | |
2060 | EVEX_W_0F5B_P_2, | |
43234a1e | 2061 | EVEX_W_0F5C_P_1, |
43234a1e | 2062 | EVEX_W_0F5C_P_3, |
43234a1e | 2063 | EVEX_W_0F5D_P_1, |
43234a1e | 2064 | EVEX_W_0F5D_P_3, |
43234a1e | 2065 | EVEX_W_0F5E_P_1, |
43234a1e | 2066 | EVEX_W_0F5E_P_3, |
43234a1e | 2067 | EVEX_W_0F5F_P_1, |
43234a1e L |
2068 | EVEX_W_0F5F_P_3, |
2069 | EVEX_W_0F62_P_2, | |
2070 | EVEX_W_0F66_P_2, | |
2071 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2072 | EVEX_W_0F6B_P_2, |
43234a1e L |
2073 | EVEX_W_0F6C_P_2, |
2074 | EVEX_W_0F6D_P_2, | |
43234a1e L |
2075 | EVEX_W_0F6F_P_1, |
2076 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2077 | EVEX_W_0F6F_P_3, |
43234a1e L |
2078 | EVEX_W_0F70_P_2, |
2079 | EVEX_W_0F72_R_2_P_2, | |
2080 | EVEX_W_0F72_R_6_P_2, | |
2081 | EVEX_W_0F73_R_2_P_2, | |
2082 | EVEX_W_0F73_R_6_P_2, | |
2083 | EVEX_W_0F76_P_2, | |
2084 | EVEX_W_0F78_P_0, | |
90a915bf | 2085 | EVEX_W_0F78_P_2, |
43234a1e | 2086 | EVEX_W_0F79_P_0, |
90a915bf | 2087 | EVEX_W_0F79_P_2, |
43234a1e | 2088 | EVEX_W_0F7A_P_1, |
90a915bf | 2089 | EVEX_W_0F7A_P_2, |
43234a1e | 2090 | EVEX_W_0F7A_P_3, |
90a915bf | 2091 | EVEX_W_0F7B_P_2, |
43234a1e L |
2092 | EVEX_W_0F7B_P_3, |
2093 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2094 | EVEX_W_0F7F_P_1, |
2095 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2096 | EVEX_W_0F7F_P_3, |
43234a1e | 2097 | EVEX_W_0FC2_P_1, |
43234a1e | 2098 | EVEX_W_0FC2_P_3, |
43234a1e L |
2099 | EVEX_W_0FD2_P_2, |
2100 | EVEX_W_0FD3_P_2, | |
2101 | EVEX_W_0FD4_P_2, | |
2102 | EVEX_W_0FD6_P_2, | |
2103 | EVEX_W_0FE6_P_1, | |
2104 | EVEX_W_0FE6_P_2, | |
2105 | EVEX_W_0FE6_P_3, | |
2106 | EVEX_W_0FE7_P_2, | |
2107 | EVEX_W_0FF2_P_2, | |
2108 | EVEX_W_0FF3_P_2, | |
2109 | EVEX_W_0FF4_P_2, | |
2110 | EVEX_W_0FFA_P_2, | |
2111 | EVEX_W_0FFB_P_2, | |
2112 | EVEX_W_0FFE_P_2, | |
2113 | EVEX_W_0F380C_P_2, | |
2114 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2115 | EVEX_W_0F3810_P_1, |
2116 | EVEX_W_0F3810_P_2, | |
43234a1e | 2117 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2118 | EVEX_W_0F3811_P_2, |
43234a1e | 2119 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2120 | EVEX_W_0F3812_P_2, |
43234a1e L |
2121 | EVEX_W_0F3813_P_1, |
2122 | EVEX_W_0F3813_P_2, | |
2123 | EVEX_W_0F3814_P_1, | |
2124 | EVEX_W_0F3815_P_1, | |
2125 | EVEX_W_0F3818_P_2, | |
2126 | EVEX_W_0F3819_P_2, | |
2127 | EVEX_W_0F381A_P_2, | |
2128 | EVEX_W_0F381B_P_2, | |
2129 | EVEX_W_0F381E_P_2, | |
2130 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2131 | EVEX_W_0F3820_P_1, |
43234a1e L |
2132 | EVEX_W_0F3821_P_1, |
2133 | EVEX_W_0F3822_P_1, | |
2134 | EVEX_W_0F3823_P_1, | |
2135 | EVEX_W_0F3824_P_1, | |
2136 | EVEX_W_0F3825_P_1, | |
2137 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2138 | EVEX_W_0F3826_P_1, |
2139 | EVEX_W_0F3826_P_2, | |
2140 | EVEX_W_0F3828_P_1, | |
43234a1e | 2141 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2142 | EVEX_W_0F3829_P_1, |
43234a1e L |
2143 | EVEX_W_0F3829_P_2, |
2144 | EVEX_W_0F382A_P_1, | |
2145 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2146 | EVEX_W_0F382B_P_2, |
2147 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2148 | EVEX_W_0F3831_P_1, |
2149 | EVEX_W_0F3832_P_1, | |
2150 | EVEX_W_0F3833_P_1, | |
2151 | EVEX_W_0F3834_P_1, | |
2152 | EVEX_W_0F3835_P_1, | |
2153 | EVEX_W_0F3835_P_2, | |
2154 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2155 | EVEX_W_0F3838_P_1, |
2156 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2157 | EVEX_W_0F383A_P_1, |
2158 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2159 | EVEX_W_0F3852_P_1, |
ee6872be | 2160 | EVEX_W_0F3854_P_2, |
620214f7 | 2161 | EVEX_W_0F3855_P_2, |
43234a1e L |
2162 | EVEX_W_0F3858_P_2, |
2163 | EVEX_W_0F3859_P_2, | |
2164 | EVEX_W_0F385A_P_2, | |
2165 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2166 | EVEX_W_0F3862_P_2, |
2167 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2168 | EVEX_W_0F3866_P_2, |
9186c494 | 2169 | EVEX_W_0F3868_P_3, |
53467f57 IT |
2170 | EVEX_W_0F3870_P_2, |
2171 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2172 | EVEX_W_0F3872_P_1, |
53467f57 | 2173 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2174 | EVEX_W_0F3872_P_3, |
53467f57 | 2175 | EVEX_W_0F3873_P_2, |
1ba585e8 IT |
2176 | EVEX_W_0F3875_P_2, |
2177 | EVEX_W_0F3878_P_2, | |
2178 | EVEX_W_0F3879_P_2, | |
2179 | EVEX_W_0F387A_P_2, | |
2180 | EVEX_W_0F387B_P_2, | |
2181 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2182 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2183 | EVEX_W_0F388D_P_2, |
43234a1e L |
2184 | EVEX_W_0F3891_P_2, |
2185 | EVEX_W_0F3893_P_2, | |
2186 | EVEX_W_0F38A1_P_2, | |
2187 | EVEX_W_0F38A3_P_2, | |
2188 | EVEX_W_0F38C7_R_1_P_2, | |
2189 | EVEX_W_0F38C7_R_2_P_2, | |
2190 | EVEX_W_0F38C7_R_5_P_2, | |
2191 | EVEX_W_0F38C7_R_6_P_2, | |
2192 | ||
2193 | EVEX_W_0F3A00_P_2, | |
2194 | EVEX_W_0F3A01_P_2, | |
2195 | EVEX_W_0F3A04_P_2, | |
2196 | EVEX_W_0F3A05_P_2, | |
2197 | EVEX_W_0F3A08_P_2, | |
2198 | EVEX_W_0F3A09_P_2, | |
2199 | EVEX_W_0F3A0A_P_2, | |
2200 | EVEX_W_0F3A0B_P_2, | |
2201 | EVEX_W_0F3A18_P_2, | |
2202 | EVEX_W_0F3A19_P_2, | |
2203 | EVEX_W_0F3A1A_P_2, | |
2204 | EVEX_W_0F3A1B_P_2, | |
2205 | EVEX_W_0F3A1D_P_2, | |
2206 | EVEX_W_0F3A21_P_2, | |
2207 | EVEX_W_0F3A23_P_2, | |
2208 | EVEX_W_0F3A38_P_2, | |
2209 | EVEX_W_0F3A39_P_2, | |
2210 | EVEX_W_0F3A3A_P_2, | |
2211 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2212 | EVEX_W_0F3A3E_P_2, |
2213 | EVEX_W_0F3A3F_P_2, | |
2214 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2215 | EVEX_W_0F3A43_P_2, |
2216 | EVEX_W_0F3A50_P_2, | |
2217 | EVEX_W_0F3A51_P_2, | |
2218 | EVEX_W_0F3A56_P_2, | |
2219 | EVEX_W_0F3A57_P_2, | |
2220 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2221 | EVEX_W_0F3A67_P_2, |
2222 | EVEX_W_0F3A70_P_2, | |
2223 | EVEX_W_0F3A71_P_2, | |
2224 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2225 | EVEX_W_0F3A73_P_2, |
2226 | EVEX_W_0F3ACE_P_2, | |
2227 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2228 | }; |
2229 | ||
26ca5450 | 2230 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2231 | |
2232 | struct dis386 { | |
2da11e11 | 2233 | const char *name; |
ce518a5f L |
2234 | struct |
2235 | { | |
2236 | op_rtn rtn; | |
2237 | int bytemode; | |
2238 | } op[MAX_OPERANDS]; | |
bf890a93 | 2239 | unsigned int prefix_requirement; |
252b5132 RH |
2240 | }; |
2241 | ||
2242 | /* Upper case letters in the instruction names here are macros. | |
2243 | 'A' => print 'b' if no register operands or suffix_always is true | |
2244 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2245 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2246 | size prefix |
ed7841b3 | 2247 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2248 | suffix_always is true |
252b5132 | 2249 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2250 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2251 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2252 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2253 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2254 | for some of the macro letters) |
9306ca4a | 2255 | 'J' => print 'l' |
42903f7f | 2256 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2257 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2258 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2259 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2260 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2261 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2262 | or suffix_always is true. print 'q' if rex prefix is present. |
2263 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2264 | is true | |
a35ca55a | 2265 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2266 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2267 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2268 | prefix and behave as 'P' otherwise | |
2269 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2270 | prefix and behave as 'Q' otherwise | |
2271 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2272 | prefix and behave as 'S' otherwise | |
a35ca55a | 2273 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2274 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2275 | 'Y' unused. |
6dd5059a | 2276 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2277 | '!' => change condition from true to false or from false to true. |
98b528ac | 2278 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2279 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2280 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2281 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2282 | on operand size prefix. | |
07f5af7d L |
2283 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2284 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2285 | otherwise | |
98b528ac L |
2286 | |
2287 | 2 upper case letter macros: | |
04d824a4 JB |
2288 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2289 | operands and no broadcast. | |
2290 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2291 | register operands and no broadcast. | |
4b06377f L |
2292 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2293 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2294 | or suffix_always is true |
4b06377f L |
2295 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2296 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2297 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2298 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2299 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2300 | an operand size prefix, or suffix_always is true. print | |
2301 | 'q' if rex prefix is present. | |
52b15da3 | 2302 | |
6439fc28 AM |
2303 | Many of the above letters print nothing in Intel mode. See "putop" |
2304 | for the details. | |
52b15da3 | 2305 | |
6439fc28 | 2306 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2307 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2308 | |
6439fc28 | 2309 | static const struct dis386 dis386[] = { |
252b5132 | 2310 | /* 00 */ |
bf890a93 IT |
2311 | { "addB", { Ebh1, Gb }, 0 }, |
2312 | { "addS", { Evh1, Gv }, 0 }, | |
2313 | { "addB", { Gb, EbS }, 0 }, | |
2314 | { "addS", { Gv, EvS }, 0 }, | |
2315 | { "addB", { AL, Ib }, 0 }, | |
2316 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2317 | { X86_64_TABLE (X86_64_06) }, |
2318 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2319 | /* 08 */ |
bf890a93 IT |
2320 | { "orB", { Ebh1, Gb }, 0 }, |
2321 | { "orS", { Evh1, Gv }, 0 }, | |
2322 | { "orB", { Gb, EbS }, 0 }, | |
2323 | { "orS", { Gv, EvS }, 0 }, | |
2324 | { "orB", { AL, Ib }, 0 }, | |
2325 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2326 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2327 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2328 | /* 10 */ |
bf890a93 IT |
2329 | { "adcB", { Ebh1, Gb }, 0 }, |
2330 | { "adcS", { Evh1, Gv }, 0 }, | |
2331 | { "adcB", { Gb, EbS }, 0 }, | |
2332 | { "adcS", { Gv, EvS }, 0 }, | |
2333 | { "adcB", { AL, Ib }, 0 }, | |
2334 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2335 | { X86_64_TABLE (X86_64_16) }, |
2336 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2337 | /* 18 */ |
bf890a93 IT |
2338 | { "sbbB", { Ebh1, Gb }, 0 }, |
2339 | { "sbbS", { Evh1, Gv }, 0 }, | |
2340 | { "sbbB", { Gb, EbS }, 0 }, | |
2341 | { "sbbS", { Gv, EvS }, 0 }, | |
2342 | { "sbbB", { AL, Ib }, 0 }, | |
2343 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2344 | { X86_64_TABLE (X86_64_1E) }, |
2345 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2346 | /* 20 */ |
bf890a93 IT |
2347 | { "andB", { Ebh1, Gb }, 0 }, |
2348 | { "andS", { Evh1, Gv }, 0 }, | |
2349 | { "andB", { Gb, EbS }, 0 }, | |
2350 | { "andS", { Gv, EvS }, 0 }, | |
2351 | { "andB", { AL, Ib }, 0 }, | |
2352 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2353 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2354 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2355 | /* 28 */ |
bf890a93 IT |
2356 | { "subB", { Ebh1, Gb }, 0 }, |
2357 | { "subS", { Evh1, Gv }, 0 }, | |
2358 | { "subB", { Gb, EbS }, 0 }, | |
2359 | { "subS", { Gv, EvS }, 0 }, | |
2360 | { "subB", { AL, Ib }, 0 }, | |
2361 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2362 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2363 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2364 | /* 30 */ |
bf890a93 IT |
2365 | { "xorB", { Ebh1, Gb }, 0 }, |
2366 | { "xorS", { Evh1, Gv }, 0 }, | |
2367 | { "xorB", { Gb, EbS }, 0 }, | |
2368 | { "xorS", { Gv, EvS }, 0 }, | |
2369 | { "xorB", { AL, Ib }, 0 }, | |
2370 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2371 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2372 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2373 | /* 38 */ |
bf890a93 IT |
2374 | { "cmpB", { Eb, Gb }, 0 }, |
2375 | { "cmpS", { Ev, Gv }, 0 }, | |
2376 | { "cmpB", { Gb, EbS }, 0 }, | |
2377 | { "cmpS", { Gv, EvS }, 0 }, | |
2378 | { "cmpB", { AL, Ib }, 0 }, | |
2379 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2380 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2381 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2382 | /* 40 */ |
bf890a93 IT |
2383 | { "inc{S|}", { RMeAX }, 0 }, |
2384 | { "inc{S|}", { RMeCX }, 0 }, | |
2385 | { "inc{S|}", { RMeDX }, 0 }, | |
2386 | { "inc{S|}", { RMeBX }, 0 }, | |
2387 | { "inc{S|}", { RMeSP }, 0 }, | |
2388 | { "inc{S|}", { RMeBP }, 0 }, | |
2389 | { "inc{S|}", { RMeSI }, 0 }, | |
2390 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2391 | /* 48 */ |
bf890a93 IT |
2392 | { "dec{S|}", { RMeAX }, 0 }, |
2393 | { "dec{S|}", { RMeCX }, 0 }, | |
2394 | { "dec{S|}", { RMeDX }, 0 }, | |
2395 | { "dec{S|}", { RMeBX }, 0 }, | |
2396 | { "dec{S|}", { RMeSP }, 0 }, | |
2397 | { "dec{S|}", { RMeBP }, 0 }, | |
2398 | { "dec{S|}", { RMeSI }, 0 }, | |
2399 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2400 | /* 50 */ |
bf890a93 IT |
2401 | { "pushV", { RMrAX }, 0 }, |
2402 | { "pushV", { RMrCX }, 0 }, | |
2403 | { "pushV", { RMrDX }, 0 }, | |
2404 | { "pushV", { RMrBX }, 0 }, | |
2405 | { "pushV", { RMrSP }, 0 }, | |
2406 | { "pushV", { RMrBP }, 0 }, | |
2407 | { "pushV", { RMrSI }, 0 }, | |
2408 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2409 | /* 58 */ |
bf890a93 IT |
2410 | { "popV", { RMrAX }, 0 }, |
2411 | { "popV", { RMrCX }, 0 }, | |
2412 | { "popV", { RMrDX }, 0 }, | |
2413 | { "popV", { RMrBX }, 0 }, | |
2414 | { "popV", { RMrSP }, 0 }, | |
2415 | { "popV", { RMrBP }, 0 }, | |
2416 | { "popV", { RMrSI }, 0 }, | |
2417 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2418 | /* 60 */ |
4e7d34a6 L |
2419 | { X86_64_TABLE (X86_64_60) }, |
2420 | { X86_64_TABLE (X86_64_61) }, | |
2421 | { X86_64_TABLE (X86_64_62) }, | |
2422 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2423 | { Bad_Opcode }, /* seg fs */ |
2424 | { Bad_Opcode }, /* seg gs */ | |
2425 | { Bad_Opcode }, /* op size prefix */ | |
2426 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2427 | /* 68 */ |
bf890a93 IT |
2428 | { "pushT", { sIv }, 0 }, |
2429 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2430 | { "pushT", { sIbT }, 0 }, | |
2431 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2432 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2433 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2434 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2435 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2436 | /* 70 */ |
bf890a93 IT |
2437 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2438 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2439 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2440 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2441 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2442 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2443 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2444 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2445 | /* 78 */ |
bf890a93 IT |
2446 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2447 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2448 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2449 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2450 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2451 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2452 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2453 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2454 | /* 80 */ |
1ceb70f8 L |
2455 | { REG_TABLE (REG_80) }, |
2456 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2457 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2458 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2459 | { "testB", { Eb, Gb }, 0 }, |
2460 | { "testS", { Ev, Gv }, 0 }, | |
2461 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2462 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2463 | /* 88 */ |
bf890a93 IT |
2464 | { "movB", { Ebh3, Gb }, 0 }, |
2465 | { "movS", { Evh3, Gv }, 0 }, | |
2466 | { "movB", { Gb, EbS }, 0 }, | |
2467 | { "movS", { Gv, EvS }, 0 }, | |
2468 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2469 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2470 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2471 | { REG_TABLE (REG_8F) }, |
252b5132 | 2472 | /* 90 */ |
1ceb70f8 | 2473 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2474 | { "xchgS", { RMeCX, eAX }, 0 }, |
2475 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2476 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2477 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2478 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2479 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2480 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2481 | /* 98 */ |
bf890a93 IT |
2482 | { "cW{t|}R", { XX }, 0 }, |
2483 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2484 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2485 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2486 | { "pushfT", { XX }, 0 }, |
2487 | { "popfT", { XX }, 0 }, | |
2488 | { "sahf", { XX }, 0 }, | |
2489 | { "lahf", { XX }, 0 }, | |
252b5132 | 2490 | /* a0 */ |
bf890a93 IT |
2491 | { "mov%LB", { AL, Ob }, 0 }, |
2492 | { "mov%LS", { eAX, Ov }, 0 }, | |
2493 | { "mov%LB", { Ob, AL }, 0 }, | |
2494 | { "mov%LS", { Ov, eAX }, 0 }, | |
2495 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2496 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2497 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2498 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2499 | /* a8 */ |
bf890a93 IT |
2500 | { "testB", { AL, Ib }, 0 }, |
2501 | { "testS", { eAX, Iv }, 0 }, | |
2502 | { "stosB", { Ybr, AL }, 0 }, | |
2503 | { "stosS", { Yvr, eAX }, 0 }, | |
2504 | { "lodsB", { ALr, Xb }, 0 }, | |
2505 | { "lodsS", { eAXr, Xv }, 0 }, | |
2506 | { "scasB", { AL, Yb }, 0 }, | |
2507 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2508 | /* b0 */ |
bf890a93 IT |
2509 | { "movB", { RMAL, Ib }, 0 }, |
2510 | { "movB", { RMCL, Ib }, 0 }, | |
2511 | { "movB", { RMDL, Ib }, 0 }, | |
2512 | { "movB", { RMBL, Ib }, 0 }, | |
2513 | { "movB", { RMAH, Ib }, 0 }, | |
2514 | { "movB", { RMCH, Ib }, 0 }, | |
2515 | { "movB", { RMDH, Ib }, 0 }, | |
2516 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2517 | /* b8 */ |
bf890a93 IT |
2518 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2519 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2520 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2521 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2522 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2523 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2524 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2525 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2526 | /* c0 */ |
1ceb70f8 L |
2527 | { REG_TABLE (REG_C0) }, |
2528 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2529 | { X86_64_TABLE (X86_64_C2) }, |
2530 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2531 | { X86_64_TABLE (X86_64_C4) }, |
2532 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2533 | { REG_TABLE (REG_C6) }, |
2534 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2535 | /* c8 */ |
bf890a93 IT |
2536 | { "enterT", { Iw, Ib }, 0 }, |
2537 | { "leaveT", { XX }, 0 }, | |
2538 | { "Jret{|f}P", { Iw }, 0 }, | |
2539 | { "Jret{|f}P", { XX }, 0 }, | |
2540 | { "int3", { XX }, 0 }, | |
2541 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2542 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2543 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2544 | /* d0 */ |
1ceb70f8 L |
2545 | { REG_TABLE (REG_D0) }, |
2546 | { REG_TABLE (REG_D1) }, | |
2547 | { REG_TABLE (REG_D2) }, | |
2548 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2549 | { X86_64_TABLE (X86_64_D4) }, |
2550 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2551 | { Bad_Opcode }, |
bf890a93 | 2552 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2553 | /* d8 */ |
2554 | { FLOAT }, | |
2555 | { FLOAT }, | |
2556 | { FLOAT }, | |
2557 | { FLOAT }, | |
2558 | { FLOAT }, | |
2559 | { FLOAT }, | |
2560 | { FLOAT }, | |
2561 | { FLOAT }, | |
2562 | /* e0 */ | |
bf890a93 IT |
2563 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2564 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2565 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2566 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2567 | { "inB", { AL, Ib }, 0 }, | |
2568 | { "inG", { zAX, Ib }, 0 }, | |
2569 | { "outB", { Ib, AL }, 0 }, | |
2570 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2571 | /* e8 */ |
a72d2af2 L |
2572 | { X86_64_TABLE (X86_64_E8) }, |
2573 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2574 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2575 | { "jmp", { Jb, BND }, 0 }, |
2576 | { "inB", { AL, indirDX }, 0 }, | |
2577 | { "inG", { zAX, indirDX }, 0 }, | |
2578 | { "outB", { indirDX, AL }, 0 }, | |
2579 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2580 | /* f0 */ |
592d1631 | 2581 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2582 | { "icebp", { XX }, 0 }, |
592d1631 L |
2583 | { Bad_Opcode }, /* repne */ |
2584 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2585 | { "hlt", { XX }, 0 }, |
2586 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2587 | { REG_TABLE (REG_F6) }, |
2588 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2589 | /* f8 */ |
bf890a93 IT |
2590 | { "clc", { XX }, 0 }, |
2591 | { "stc", { XX }, 0 }, | |
2592 | { "cli", { XX }, 0 }, | |
2593 | { "sti", { XX }, 0 }, | |
2594 | { "cld", { XX }, 0 }, | |
2595 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2596 | { REG_TABLE (REG_FE) }, |
2597 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2598 | }; |
2599 | ||
6439fc28 | 2600 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2601 | /* 00 */ |
1ceb70f8 L |
2602 | { REG_TABLE (REG_0F00 ) }, |
2603 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2604 | { "larS", { Gv, Ew }, 0 }, |
2605 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2606 | { Bad_Opcode }, |
bf890a93 IT |
2607 | { "syscall", { XX }, 0 }, |
2608 | { "clts", { XX }, 0 }, | |
2609 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2610 | /* 08 */ |
bf890a93 | 2611 | { "invd", { XX }, 0 }, |
3233d7d0 | 2612 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2613 | { Bad_Opcode }, |
bf890a93 | 2614 | { "ud2", { XX }, 0 }, |
592d1631 | 2615 | { Bad_Opcode }, |
b5b1fc4f | 2616 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2617 | { "femms", { XX }, 0 }, |
2618 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2619 | /* 10 */ |
1ceb70f8 L |
2620 | { PREFIX_TABLE (PREFIX_0F10) }, |
2621 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2622 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2623 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2624 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2625 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2626 | { PREFIX_TABLE (PREFIX_0F16) }, |
2627 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2628 | /* 18 */ |
1ceb70f8 | 2629 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2630 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2631 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2632 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2633 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2634 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2635 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2636 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2637 | /* 20 */ |
bf890a93 IT |
2638 | { "movZ", { Rm, Cm }, 0 }, |
2639 | { "movZ", { Rm, Dm }, 0 }, | |
2640 | { "movZ", { Cm, Rm }, 0 }, | |
2641 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2642 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2643 | { Bad_Opcode }, |
1ceb70f8 | 2644 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2645 | { Bad_Opcode }, |
252b5132 | 2646 | /* 28 */ |
507bd325 L |
2647 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2648 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2649 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2650 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2651 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2652 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2653 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2654 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2655 | /* 30 */ |
bf890a93 IT |
2656 | { "wrmsr", { XX }, 0 }, |
2657 | { "rdtsc", { XX }, 0 }, | |
2658 | { "rdmsr", { XX }, 0 }, | |
2659 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2660 | { "sysenter", { SEP }, 0 }, |
2661 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2662 | { Bad_Opcode }, |
bf890a93 | 2663 | { "getsec", { XX }, 0 }, |
252b5132 | 2664 | /* 38 */ |
507bd325 | 2665 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2666 | { Bad_Opcode }, |
507bd325 | 2667 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2668 | { Bad_Opcode }, |
2669 | { Bad_Opcode }, | |
2670 | { Bad_Opcode }, | |
2671 | { Bad_Opcode }, | |
2672 | { Bad_Opcode }, | |
252b5132 | 2673 | /* 40 */ |
bf890a93 IT |
2674 | { "cmovoS", { Gv, Ev }, 0 }, |
2675 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2676 | { "cmovbS", { Gv, Ev }, 0 }, | |
2677 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2678 | { "cmoveS", { Gv, Ev }, 0 }, | |
2679 | { "cmovneS", { Gv, Ev }, 0 }, | |
2680 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2681 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2682 | /* 48 */ |
bf890a93 IT |
2683 | { "cmovsS", { Gv, Ev }, 0 }, |
2684 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2685 | { "cmovpS", { Gv, Ev }, 0 }, | |
2686 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2687 | { "cmovlS", { Gv, Ev }, 0 }, | |
2688 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2689 | { "cmovleS", { Gv, Ev }, 0 }, | |
2690 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2691 | /* 50 */ |
a5aaedb9 | 2692 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2693 | { PREFIX_TABLE (PREFIX_0F51) }, |
2694 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2695 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2696 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2697 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2698 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2699 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2700 | /* 58 */ |
1ceb70f8 L |
2701 | { PREFIX_TABLE (PREFIX_0F58) }, |
2702 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2703 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2704 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2705 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2706 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2707 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2708 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2709 | /* 60 */ |
1ceb70f8 L |
2710 | { PREFIX_TABLE (PREFIX_0F60) }, |
2711 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2712 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2713 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2714 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2715 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2716 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2717 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2718 | /* 68 */ |
507bd325 L |
2719 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2720 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2721 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2722 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2723 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2724 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2725 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2726 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2727 | /* 70 */ |
1ceb70f8 L |
2728 | { PREFIX_TABLE (PREFIX_0F70) }, |
2729 | { REG_TABLE (REG_0F71) }, | |
2730 | { REG_TABLE (REG_0F72) }, | |
2731 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2732 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2733 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2734 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2735 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2736 | /* 78 */ |
1ceb70f8 L |
2737 | { PREFIX_TABLE (PREFIX_0F78) }, |
2738 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2739 | { Bad_Opcode }, |
592d1631 | 2740 | { Bad_Opcode }, |
1ceb70f8 L |
2741 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2742 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2743 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2744 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2745 | /* 80 */ |
bf890a93 IT |
2746 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2747 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2748 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2749 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2750 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2751 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2752 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2753 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2754 | /* 88 */ |
bf890a93 IT |
2755 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2756 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2757 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2758 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2759 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2760 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2761 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2762 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2763 | /* 90 */ |
bf890a93 IT |
2764 | { "seto", { Eb }, 0 }, |
2765 | { "setno", { Eb }, 0 }, | |
2766 | { "setb", { Eb }, 0 }, | |
2767 | { "setae", { Eb }, 0 }, | |
2768 | { "sete", { Eb }, 0 }, | |
2769 | { "setne", { Eb }, 0 }, | |
2770 | { "setbe", { Eb }, 0 }, | |
2771 | { "seta", { Eb }, 0 }, | |
252b5132 | 2772 | /* 98 */ |
bf890a93 IT |
2773 | { "sets", { Eb }, 0 }, |
2774 | { "setns", { Eb }, 0 }, | |
2775 | { "setp", { Eb }, 0 }, | |
2776 | { "setnp", { Eb }, 0 }, | |
2777 | { "setl", { Eb }, 0 }, | |
2778 | { "setge", { Eb }, 0 }, | |
2779 | { "setle", { Eb }, 0 }, | |
2780 | { "setg", { Eb }, 0 }, | |
252b5132 | 2781 | /* a0 */ |
bf890a93 IT |
2782 | { "pushT", { fs }, 0 }, |
2783 | { "popT", { fs }, 0 }, | |
2784 | { "cpuid", { XX }, 0 }, | |
2785 | { "btS", { Ev, Gv }, 0 }, | |
2786 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2787 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2788 | { REG_TABLE (REG_0FA6) }, |
2789 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2790 | /* a8 */ |
bf890a93 IT |
2791 | { "pushT", { gs }, 0 }, |
2792 | { "popT", { gs }, 0 }, | |
2793 | { "rsm", { XX }, 0 }, | |
2794 | { "btsS", { Evh1, Gv }, 0 }, | |
2795 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2796 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2797 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2798 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2799 | /* b0 */ |
bf890a93 IT |
2800 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2801 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2802 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2803 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2804 | { MOD_TABLE (MOD_0FB4) }, |
2805 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2806 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2807 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2808 | /* b8 */ |
1ceb70f8 | 2809 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2810 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2811 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2812 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2813 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2814 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2815 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2816 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2817 | /* c0 */ |
bf890a93 IT |
2818 | { "xaddB", { Ebh1, Gb }, 0 }, |
2819 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2820 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2821 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2822 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2823 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2824 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2825 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2826 | /* c8 */ |
bf890a93 IT |
2827 | { "bswap", { RMeAX }, 0 }, |
2828 | { "bswap", { RMeCX }, 0 }, | |
2829 | { "bswap", { RMeDX }, 0 }, | |
2830 | { "bswap", { RMeBX }, 0 }, | |
2831 | { "bswap", { RMeSP }, 0 }, | |
2832 | { "bswap", { RMeBP }, 0 }, | |
2833 | { "bswap", { RMeSI }, 0 }, | |
2834 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2835 | /* d0 */ |
1ceb70f8 | 2836 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2837 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2838 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2839 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2840 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2841 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2842 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2843 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2844 | /* d8 */ |
507bd325 L |
2845 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2846 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2847 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2848 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2849 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2850 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2851 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2852 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2853 | /* e0 */ |
507bd325 L |
2854 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2855 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2856 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2857 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2858 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2859 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2860 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2861 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2862 | /* e8 */ |
507bd325 L |
2863 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2864 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2865 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2866 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2867 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2868 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2869 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2870 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2871 | /* f0 */ |
1ceb70f8 | 2872 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2873 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2874 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2875 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2876 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2877 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2878 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2879 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2880 | /* f8 */ |
507bd325 L |
2881 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2882 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2883 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2884 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2885 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2886 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2887 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2888 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2889 | }; |
2890 | ||
2891 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2892 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2893 | /* ------------------------------- */ | |
2894 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2895 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2896 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2897 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2898 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2899 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2900 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2901 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2902 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2903 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2904 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2905 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2906 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2907 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2908 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2909 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2910 | /* ------------------------------- */ | |
2911 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2912 | }; |
2913 | ||
2914 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2915 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2916 | /* ------------------------------- */ | |
252b5132 | 2917 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2918 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2919 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2920 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2921 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2922 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2923 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2924 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2925 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2926 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2927 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2928 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2929 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2930 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2931 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2932 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2933 | /* ------------------------------- */ |
2934 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2935 | }; | |
2936 | ||
252b5132 RH |
2937 | static char obuf[100]; |
2938 | static char *obufp; | |
ea397f5b | 2939 | static char *mnemonicendp; |
252b5132 RH |
2940 | static char scratchbuf[100]; |
2941 | static unsigned char *start_codep; | |
2942 | static unsigned char *insn_codep; | |
2943 | static unsigned char *codep; | |
285ca992 | 2944 | static unsigned char *end_codep; |
f16cd0d5 L |
2945 | static int last_lock_prefix; |
2946 | static int last_repz_prefix; | |
2947 | static int last_repnz_prefix; | |
2948 | static int last_data_prefix; | |
2949 | static int last_addr_prefix; | |
2950 | static int last_rex_prefix; | |
2951 | static int last_seg_prefix; | |
d9949a36 | 2952 | static int fwait_prefix; |
285ca992 L |
2953 | /* The active segment register prefix. */ |
2954 | static int active_seg_prefix; | |
f16cd0d5 L |
2955 | #define MAX_CODE_LENGTH 15 |
2956 | /* We can up to 14 prefixes since the maximum instruction length is | |
2957 | 15bytes. */ | |
2958 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2959 | static disassemble_info *the_info; |
7967e09e L |
2960 | static struct |
2961 | { | |
2962 | int mod; | |
7967e09e | 2963 | int reg; |
484c222e | 2964 | int rm; |
7967e09e L |
2965 | } |
2966 | modrm; | |
4bba6815 | 2967 | static unsigned char need_modrm; |
dfc8cf43 L |
2968 | static struct |
2969 | { | |
2970 | int scale; | |
2971 | int index; | |
2972 | int base; | |
2973 | } | |
2974 | sib; | |
c0f3af97 L |
2975 | static struct |
2976 | { | |
2977 | int register_specifier; | |
2978 | int length; | |
2979 | int prefix; | |
2980 | int w; | |
43234a1e L |
2981 | int evex; |
2982 | int r; | |
2983 | int v; | |
2984 | int mask_register_specifier; | |
2985 | int zeroing; | |
2986 | int ll; | |
2987 | int b; | |
c0f3af97 L |
2988 | } |
2989 | vex; | |
2990 | static unsigned char need_vex; | |
2991 | static unsigned char need_vex_reg; | |
dae39acc | 2992 | static unsigned char vex_w_done; |
252b5132 | 2993 | |
ea397f5b L |
2994 | struct op |
2995 | { | |
2996 | const char *name; | |
2997 | unsigned int len; | |
2998 | }; | |
2999 | ||
4bba6815 AM |
3000 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3001 | values are stale. Hitting this abort likely indicates that you | |
3002 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3003 | #define MODRM_CHECK if (!need_modrm) abort () | |
3004 | ||
d708bcba AM |
3005 | static const char **names64; |
3006 | static const char **names32; | |
3007 | static const char **names16; | |
3008 | static const char **names8; | |
3009 | static const char **names8rex; | |
3010 | static const char **names_seg; | |
db51cc60 L |
3011 | static const char *index64; |
3012 | static const char *index32; | |
d708bcba | 3013 | static const char **index16; |
7e8b059b | 3014 | static const char **names_bnd; |
d708bcba AM |
3015 | |
3016 | static const char *intel_names64[] = { | |
3017 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3018 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3019 | }; | |
3020 | static const char *intel_names32[] = { | |
3021 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3022 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3023 | }; | |
3024 | static const char *intel_names16[] = { | |
3025 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3026 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3027 | }; | |
3028 | static const char *intel_names8[] = { | |
3029 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3030 | }; | |
3031 | static const char *intel_names8rex[] = { | |
3032 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3033 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3034 | }; | |
3035 | static const char *intel_names_seg[] = { | |
3036 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3037 | }; | |
db51cc60 L |
3038 | static const char *intel_index64 = "riz"; |
3039 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3040 | static const char *intel_index16[] = { |
3041 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3042 | }; | |
3043 | ||
3044 | static const char *att_names64[] = { | |
3045 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3046 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3047 | }; | |
d708bcba AM |
3048 | static const char *att_names32[] = { |
3049 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3050 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3051 | }; |
d708bcba AM |
3052 | static const char *att_names16[] = { |
3053 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3054 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3055 | }; |
d708bcba AM |
3056 | static const char *att_names8[] = { |
3057 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3058 | }; |
d708bcba AM |
3059 | static const char *att_names8rex[] = { |
3060 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3061 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3062 | }; | |
d708bcba AM |
3063 | static const char *att_names_seg[] = { |
3064 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3065 | }; |
db51cc60 L |
3066 | static const char *att_index64 = "%riz"; |
3067 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3068 | static const char *att_index16[] = { |
3069 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3070 | }; |
3071 | ||
b9733481 L |
3072 | static const char **names_mm; |
3073 | static const char *intel_names_mm[] = { | |
3074 | "mm0", "mm1", "mm2", "mm3", | |
3075 | "mm4", "mm5", "mm6", "mm7" | |
3076 | }; | |
3077 | static const char *att_names_mm[] = { | |
3078 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3079 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3080 | }; | |
3081 | ||
7e8b059b L |
3082 | static const char *intel_names_bnd[] = { |
3083 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3084 | }; | |
3085 | ||
3086 | static const char *att_names_bnd[] = { | |
3087 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3088 | }; | |
3089 | ||
b9733481 L |
3090 | static const char **names_xmm; |
3091 | static const char *intel_names_xmm[] = { | |
3092 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3093 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3094 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3095 | "xmm12", "xmm13", "xmm14", "xmm15", |
3096 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3097 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3098 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3099 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3100 | }; |
3101 | static const char *att_names_xmm[] = { | |
3102 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3103 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3104 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3105 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3106 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3107 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3108 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3109 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3110 | }; |
3111 | ||
3112 | static const char **names_ymm; | |
3113 | static const char *intel_names_ymm[] = { | |
3114 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3115 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3116 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3117 | "ymm12", "ymm13", "ymm14", "ymm15", |
3118 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3119 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3120 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3121 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3122 | }; |
3123 | static const char *att_names_ymm[] = { | |
3124 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3125 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3126 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3127 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3128 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3129 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3130 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3131 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3132 | }; | |
3133 | ||
3134 | static const char **names_zmm; | |
3135 | static const char *intel_names_zmm[] = { | |
3136 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3137 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3138 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3139 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3140 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3141 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3142 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3143 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3144 | }; | |
3145 | static const char *att_names_zmm[] = { | |
3146 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3147 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3148 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3149 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3150 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3151 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3152 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3153 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3154 | }; | |
3155 | ||
3156 | static const char **names_mask; | |
3157 | static const char *intel_names_mask[] = { | |
3158 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3159 | }; | |
3160 | static const char *att_names_mask[] = { | |
3161 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3162 | }; | |
3163 | ||
3164 | static const char *names_rounding[] = | |
3165 | { | |
3166 | "{rn-sae}", | |
3167 | "{rd-sae}", | |
3168 | "{ru-sae}", | |
3169 | "{rz-sae}" | |
b9733481 L |
3170 | }; |
3171 | ||
1ceb70f8 L |
3172 | static const struct dis386 reg_table[][8] = { |
3173 | /* REG_80 */ | |
252b5132 | 3174 | { |
bf890a93 IT |
3175 | { "addA", { Ebh1, Ib }, 0 }, |
3176 | { "orA", { Ebh1, Ib }, 0 }, | |
3177 | { "adcA", { Ebh1, Ib }, 0 }, | |
3178 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3179 | { "andA", { Ebh1, Ib }, 0 }, | |
3180 | { "subA", { Ebh1, Ib }, 0 }, | |
3181 | { "xorA", { Ebh1, Ib }, 0 }, | |
3182 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3183 | }, |
1ceb70f8 | 3184 | /* REG_81 */ |
252b5132 | 3185 | { |
bf890a93 IT |
3186 | { "addQ", { Evh1, Iv }, 0 }, |
3187 | { "orQ", { Evh1, Iv }, 0 }, | |
3188 | { "adcQ", { Evh1, Iv }, 0 }, | |
3189 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3190 | { "andQ", { Evh1, Iv }, 0 }, | |
3191 | { "subQ", { Evh1, Iv }, 0 }, | |
3192 | { "xorQ", { Evh1, Iv }, 0 }, | |
3193 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3194 | }, |
7148c369 | 3195 | /* REG_83 */ |
252b5132 | 3196 | { |
bf890a93 IT |
3197 | { "addQ", { Evh1, sIb }, 0 }, |
3198 | { "orQ", { Evh1, sIb }, 0 }, | |
3199 | { "adcQ", { Evh1, sIb }, 0 }, | |
3200 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3201 | { "andQ", { Evh1, sIb }, 0 }, | |
3202 | { "subQ", { Evh1, sIb }, 0 }, | |
3203 | { "xorQ", { Evh1, sIb }, 0 }, | |
3204 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3205 | }, |
1ceb70f8 | 3206 | /* REG_8F */ |
4e7d34a6 | 3207 | { |
bf890a93 | 3208 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3209 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3210 | { Bad_Opcode }, |
3211 | { Bad_Opcode }, | |
3212 | { Bad_Opcode }, | |
f88c9eb0 | 3213 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3214 | }, |
1ceb70f8 | 3215 | /* REG_C0 */ |
252b5132 | 3216 | { |
bf890a93 IT |
3217 | { "rolA", { Eb, Ib }, 0 }, |
3218 | { "rorA", { Eb, Ib }, 0 }, | |
3219 | { "rclA", { Eb, Ib }, 0 }, | |
3220 | { "rcrA", { Eb, Ib }, 0 }, | |
3221 | { "shlA", { Eb, Ib }, 0 }, | |
3222 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3223 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3224 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3225 | }, |
1ceb70f8 | 3226 | /* REG_C1 */ |
252b5132 | 3227 | { |
bf890a93 IT |
3228 | { "rolQ", { Ev, Ib }, 0 }, |
3229 | { "rorQ", { Ev, Ib }, 0 }, | |
3230 | { "rclQ", { Ev, Ib }, 0 }, | |
3231 | { "rcrQ", { Ev, Ib }, 0 }, | |
3232 | { "shlQ", { Ev, Ib }, 0 }, | |
3233 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3234 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3235 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3236 | }, |
1ceb70f8 | 3237 | /* REG_C6 */ |
4e7d34a6 | 3238 | { |
bf890a93 | 3239 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3240 | { Bad_Opcode }, |
3241 | { Bad_Opcode }, | |
3242 | { Bad_Opcode }, | |
3243 | { Bad_Opcode }, | |
3244 | { Bad_Opcode }, | |
3245 | { Bad_Opcode }, | |
3246 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3247 | }, |
1ceb70f8 | 3248 | /* REG_C7 */ |
4e7d34a6 | 3249 | { |
bf890a93 | 3250 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3251 | { Bad_Opcode }, |
3252 | { Bad_Opcode }, | |
3253 | { Bad_Opcode }, | |
3254 | { Bad_Opcode }, | |
3255 | { Bad_Opcode }, | |
3256 | { Bad_Opcode }, | |
3257 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3258 | }, |
1ceb70f8 | 3259 | /* REG_D0 */ |
252b5132 | 3260 | { |
bf890a93 IT |
3261 | { "rolA", { Eb, I1 }, 0 }, |
3262 | { "rorA", { Eb, I1 }, 0 }, | |
3263 | { "rclA", { Eb, I1 }, 0 }, | |
3264 | { "rcrA", { Eb, I1 }, 0 }, | |
3265 | { "shlA", { Eb, I1 }, 0 }, | |
3266 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3267 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3268 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3269 | }, |
1ceb70f8 | 3270 | /* REG_D1 */ |
252b5132 | 3271 | { |
bf890a93 IT |
3272 | { "rolQ", { Ev, I1 }, 0 }, |
3273 | { "rorQ", { Ev, I1 }, 0 }, | |
3274 | { "rclQ", { Ev, I1 }, 0 }, | |
3275 | { "rcrQ", { Ev, I1 }, 0 }, | |
3276 | { "shlQ", { Ev, I1 }, 0 }, | |
3277 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3278 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3279 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3280 | }, |
1ceb70f8 | 3281 | /* REG_D2 */ |
252b5132 | 3282 | { |
bf890a93 IT |
3283 | { "rolA", { Eb, CL }, 0 }, |
3284 | { "rorA", { Eb, CL }, 0 }, | |
3285 | { "rclA", { Eb, CL }, 0 }, | |
3286 | { "rcrA", { Eb, CL }, 0 }, | |
3287 | { "shlA", { Eb, CL }, 0 }, | |
3288 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3289 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3290 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3291 | }, |
1ceb70f8 | 3292 | /* REG_D3 */ |
252b5132 | 3293 | { |
bf890a93 IT |
3294 | { "rolQ", { Ev, CL }, 0 }, |
3295 | { "rorQ", { Ev, CL }, 0 }, | |
3296 | { "rclQ", { Ev, CL }, 0 }, | |
3297 | { "rcrQ", { Ev, CL }, 0 }, | |
3298 | { "shlQ", { Ev, CL }, 0 }, | |
3299 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3300 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3301 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3302 | }, |
1ceb70f8 | 3303 | /* REG_F6 */ |
252b5132 | 3304 | { |
bf890a93 | 3305 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3306 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3307 | { "notA", { Ebh1 }, 0 }, |
3308 | { "negA", { Ebh1 }, 0 }, | |
3309 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3310 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3311 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3312 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3313 | }, |
1ceb70f8 | 3314 | /* REG_F7 */ |
252b5132 | 3315 | { |
bf890a93 | 3316 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3317 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3318 | { "notQ", { Evh1 }, 0 }, |
3319 | { "negQ", { Evh1 }, 0 }, | |
3320 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3321 | { "imulQ", { Ev }, 0 }, | |
3322 | { "divQ", { Ev }, 0 }, | |
3323 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3324 | }, |
1ceb70f8 | 3325 | /* REG_FE */ |
252b5132 | 3326 | { |
bf890a93 IT |
3327 | { "incA", { Ebh1 }, 0 }, |
3328 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3329 | }, |
1ceb70f8 | 3330 | /* REG_FF */ |
252b5132 | 3331 | { |
bf890a93 IT |
3332 | { "incQ", { Evh1 }, 0 }, |
3333 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3334 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3335 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3336 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3337 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3338 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3339 | { Bad_Opcode }, |
252b5132 | 3340 | }, |
1ceb70f8 | 3341 | /* REG_0F00 */ |
252b5132 | 3342 | { |
bf890a93 IT |
3343 | { "sldtD", { Sv }, 0 }, |
3344 | { "strD", { Sv }, 0 }, | |
3345 | { "lldt", { Ew }, 0 }, | |
3346 | { "ltr", { Ew }, 0 }, | |
3347 | { "verr", { Ew }, 0 }, | |
3348 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3349 | { Bad_Opcode }, |
3350 | { Bad_Opcode }, | |
252b5132 | 3351 | }, |
1ceb70f8 | 3352 | /* REG_0F01 */ |
252b5132 | 3353 | { |
1ceb70f8 L |
3354 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3355 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3356 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3357 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3358 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3359 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3360 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3361 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3362 | }, |
b5b1fc4f | 3363 | /* REG_0F0D */ |
252b5132 | 3364 | { |
bf890a93 IT |
3365 | { "prefetch", { Mb }, 0 }, |
3366 | { "prefetchw", { Mb }, 0 }, | |
3367 | { "prefetchwt1", { Mb }, 0 }, | |
3368 | { "prefetch", { Mb }, 0 }, | |
3369 | { "prefetch", { Mb }, 0 }, | |
3370 | { "prefetch", { Mb }, 0 }, | |
3371 | { "prefetch", { Mb }, 0 }, | |
3372 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3373 | }, |
1ceb70f8 | 3374 | /* REG_0F18 */ |
252b5132 | 3375 | { |
1ceb70f8 L |
3376 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3377 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3378 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3379 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3380 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3381 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3382 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3383 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3384 | }, |
f8687e93 | 3385 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3386 | { |
3387 | { "cldemote", { Mb }, 0 }, | |
3388 | { "nopQ", { Ev }, 0 }, | |
3389 | { "nopQ", { Ev }, 0 }, | |
3390 | { "nopQ", { Ev }, 0 }, | |
3391 | { "nopQ", { Ev }, 0 }, | |
3392 | { "nopQ", { Ev }, 0 }, | |
3393 | { "nopQ", { Ev }, 0 }, | |
3394 | { "nopQ", { Ev }, 0 }, | |
3395 | }, | |
f8687e93 | 3396 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3397 | { |
3398 | { "nopQ", { Ev }, 0 }, | |
3399 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3400 | { "nopQ", { Ev }, 0 }, | |
3401 | { "nopQ", { Ev }, 0 }, | |
3402 | { "nopQ", { Ev }, 0 }, | |
3403 | { "nopQ", { Ev }, 0 }, | |
3404 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3405 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3406 | }, |
1ceb70f8 | 3407 | /* REG_0F71 */ |
a6bd098c | 3408 | { |
592d1631 L |
3409 | { Bad_Opcode }, |
3410 | { Bad_Opcode }, | |
1ceb70f8 | 3411 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3412 | { Bad_Opcode }, |
1ceb70f8 | 3413 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3414 | { Bad_Opcode }, |
1ceb70f8 | 3415 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3416 | }, |
1ceb70f8 | 3417 | /* REG_0F72 */ |
a6bd098c | 3418 | { |
592d1631 L |
3419 | { Bad_Opcode }, |
3420 | { Bad_Opcode }, | |
1ceb70f8 | 3421 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3422 | { Bad_Opcode }, |
1ceb70f8 | 3423 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3424 | { Bad_Opcode }, |
1ceb70f8 | 3425 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3426 | }, |
1ceb70f8 | 3427 | /* REG_0F73 */ |
252b5132 | 3428 | { |
592d1631 L |
3429 | { Bad_Opcode }, |
3430 | { Bad_Opcode }, | |
1ceb70f8 L |
3431 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3432 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3433 | { Bad_Opcode }, |
3434 | { Bad_Opcode }, | |
1ceb70f8 L |
3435 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3436 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3437 | }, |
1ceb70f8 | 3438 | /* REG_0FA6 */ |
252b5132 | 3439 | { |
bf890a93 IT |
3440 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3441 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3442 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3443 | }, |
1ceb70f8 | 3444 | /* REG_0FA7 */ |
4e7d34a6 | 3445 | { |
bf890a93 IT |
3446 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3447 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3448 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3449 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3450 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3451 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3452 | }, |
1ceb70f8 | 3453 | /* REG_0FAE */ |
4e7d34a6 | 3454 | { |
1ceb70f8 L |
3455 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3456 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3457 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3458 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3459 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3460 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3461 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3462 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3463 | }, |
1ceb70f8 | 3464 | /* REG_0FBA */ |
252b5132 | 3465 | { |
592d1631 L |
3466 | { Bad_Opcode }, |
3467 | { Bad_Opcode }, | |
3468 | { Bad_Opcode }, | |
3469 | { Bad_Opcode }, | |
bf890a93 IT |
3470 | { "btQ", { Ev, Ib }, 0 }, |
3471 | { "btsQ", { Evh1, Ib }, 0 }, | |
3472 | { "btrQ", { Evh1, Ib }, 0 }, | |
3473 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3474 | }, |
1ceb70f8 | 3475 | /* REG_0FC7 */ |
c608c12e | 3476 | { |
592d1631 | 3477 | { Bad_Opcode }, |
bf890a93 | 3478 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3479 | { Bad_Opcode }, |
963f3586 IT |
3480 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3481 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3482 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3483 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3484 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3485 | }, |
592a252b | 3486 | /* REG_VEX_0F71 */ |
c0f3af97 | 3487 | { |
592d1631 L |
3488 | { Bad_Opcode }, |
3489 | { Bad_Opcode }, | |
592a252b | 3490 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3491 | { Bad_Opcode }, |
592a252b | 3492 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3493 | { Bad_Opcode }, |
592a252b | 3494 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3495 | }, |
592a252b | 3496 | /* REG_VEX_0F72 */ |
c0f3af97 | 3497 | { |
592d1631 L |
3498 | { Bad_Opcode }, |
3499 | { Bad_Opcode }, | |
592a252b | 3500 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3501 | { Bad_Opcode }, |
592a252b | 3502 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3503 | { Bad_Opcode }, |
592a252b | 3504 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3505 | }, |
592a252b | 3506 | /* REG_VEX_0F73 */ |
c0f3af97 | 3507 | { |
592d1631 L |
3508 | { Bad_Opcode }, |
3509 | { Bad_Opcode }, | |
592a252b L |
3510 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3511 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3512 | { Bad_Opcode }, |
3513 | { Bad_Opcode }, | |
592a252b L |
3514 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3515 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3516 | }, |
592a252b | 3517 | /* REG_VEX_0FAE */ |
c0f3af97 | 3518 | { |
592d1631 L |
3519 | { Bad_Opcode }, |
3520 | { Bad_Opcode }, | |
592a252b L |
3521 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3522 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3523 | }, |
f12dc422 L |
3524 | /* REG_VEX_0F38F3 */ |
3525 | { | |
3526 | { Bad_Opcode }, | |
3527 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3528 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3529 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3530 | }, | |
f88c9eb0 SP |
3531 | /* REG_XOP_LWPCB */ |
3532 | { | |
bf890a93 IT |
3533 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3534 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3535 | }, |
3536 | /* REG_XOP_LWP */ | |
3537 | { | |
c1dc7af5 JB |
3538 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3539 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3540 | }, |
2a2a0f38 QN |
3541 | /* REG_XOP_TBM_01 */ |
3542 | { | |
3543 | { Bad_Opcode }, | |
c1dc7af5 JB |
3544 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3545 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3546 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3547 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3548 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3549 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3550 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3551 | }, |
3552 | /* REG_XOP_TBM_02 */ | |
3553 | { | |
3554 | { Bad_Opcode }, | |
c1dc7af5 | 3555 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3556 | { Bad_Opcode }, |
3557 | { Bad_Opcode }, | |
3558 | { Bad_Opcode }, | |
3559 | { Bad_Opcode }, | |
c1dc7af5 | 3560 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3561 | }, |
ad692897 L |
3562 | |
3563 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3564 | }; |
3565 | ||
1ceb70f8 L |
3566 | static const struct dis386 prefix_table[][4] = { |
3567 | /* PREFIX_90 */ | |
252b5132 | 3568 | { |
bf890a93 IT |
3569 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3570 | { "pause", { XX }, 0 }, | |
3571 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3572 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3573 | }, |
4e7d34a6 | 3574 | |
f9630fa6 | 3575 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3576 | { |
3577 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3578 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3579 | }, |
3580 | ||
f8687e93 | 3581 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3582 | { |
3583 | { Bad_Opcode }, | |
3584 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3585 | }, | |
3586 | ||
f8687e93 | 3587 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3588 | { |
4b27d27c | 3589 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3590 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3591 | { Bad_Opcode }, |
efe30057 | 3592 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3593 | }, |
3594 | ||
3595 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3596 | { | |
3597 | { Bad_Opcode }, | |
3598 | { Bad_Opcode }, | |
3599 | { Bad_Opcode }, | |
3600 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3601 | }, |
3602 | ||
f8687e93 | 3603 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3604 | { |
3605 | { Bad_Opcode }, | |
c2f76402 | 3606 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3607 | }, |
3608 | ||
267b8516 JB |
3609 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3610 | { | |
3611 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3612 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3613 | }, |
3614 | ||
3615 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3616 | { | |
7abb8d81 | 3617 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3618 | }, |
3619 | ||
3233d7d0 IT |
3620 | /* PREFIX_0F09 */ |
3621 | { | |
3622 | { "wbinvd", { XX }, 0 }, | |
3623 | { "wbnoinvd", { XX }, 0 }, | |
3624 | }, | |
3625 | ||
1ceb70f8 | 3626 | /* PREFIX_0F10 */ |
cc0ec051 | 3627 | { |
507bd325 L |
3628 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3629 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3630 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3631 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3632 | }, |
4e7d34a6 | 3633 | |
1ceb70f8 | 3634 | /* PREFIX_0F11 */ |
30d1c836 | 3635 | { |
507bd325 L |
3636 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3637 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3638 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3639 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3640 | }, |
252b5132 | 3641 | |
1ceb70f8 | 3642 | /* PREFIX_0F12 */ |
c608c12e | 3643 | { |
1ceb70f8 | 3644 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3645 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3646 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3647 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3648 | }, |
4e7d34a6 | 3649 | |
1ceb70f8 | 3650 | /* PREFIX_0F16 */ |
c608c12e | 3651 | { |
1ceb70f8 | 3652 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3653 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3654 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3655 | }, |
4e7d34a6 | 3656 | |
7e8b059b L |
3657 | /* PREFIX_0F1A */ |
3658 | { | |
3659 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3660 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3661 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3662 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3663 | }, |
3664 | ||
3665 | /* PREFIX_0F1B */ | |
3666 | { | |
3667 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3668 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3669 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3670 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3671 | }, |
3672 | ||
c48935d7 IT |
3673 | /* PREFIX_0F1C */ |
3674 | { | |
3675 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3676 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3677 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3678 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3679 | }, | |
3680 | ||
603555e5 L |
3681 | /* PREFIX_0F1E */ |
3682 | { | |
3683 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3684 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3685 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3686 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3687 | }, | |
3688 | ||
1ceb70f8 | 3689 | /* PREFIX_0F2A */ |
c608c12e | 3690 | { |
507bd325 | 3691 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3692 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3693 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3694 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3695 | }, |
4e7d34a6 | 3696 | |
1ceb70f8 | 3697 | /* PREFIX_0F2B */ |
c608c12e | 3698 | { |
75c135a8 L |
3699 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3700 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3701 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3702 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3703 | }, |
4e7d34a6 | 3704 | |
1ceb70f8 | 3705 | /* PREFIX_0F2C */ |
c608c12e | 3706 | { |
507bd325 | 3707 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3708 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3709 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3710 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3711 | }, |
4e7d34a6 | 3712 | |
1ceb70f8 | 3713 | /* PREFIX_0F2D */ |
c608c12e | 3714 | { |
507bd325 | 3715 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3716 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3717 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3718 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3719 | }, |
4e7d34a6 | 3720 | |
1ceb70f8 | 3721 | /* PREFIX_0F2E */ |
c608c12e | 3722 | { |
bf890a93 | 3723 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3724 | { Bad_Opcode }, |
bf890a93 | 3725 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3726 | }, |
4e7d34a6 | 3727 | |
1ceb70f8 | 3728 | /* PREFIX_0F2F */ |
c608c12e | 3729 | { |
bf890a93 | 3730 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3731 | { Bad_Opcode }, |
bf890a93 | 3732 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3733 | }, |
4e7d34a6 | 3734 | |
1ceb70f8 | 3735 | /* PREFIX_0F51 */ |
c608c12e | 3736 | { |
507bd325 L |
3737 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3738 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3739 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3740 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3741 | }, |
4e7d34a6 | 3742 | |
1ceb70f8 | 3743 | /* PREFIX_0F52 */ |
c608c12e | 3744 | { |
507bd325 L |
3745 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3746 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3747 | }, |
4e7d34a6 | 3748 | |
1ceb70f8 | 3749 | /* PREFIX_0F53 */ |
c608c12e | 3750 | { |
507bd325 L |
3751 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3752 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3753 | }, |
4e7d34a6 | 3754 | |
1ceb70f8 | 3755 | /* PREFIX_0F58 */ |
c608c12e | 3756 | { |
507bd325 L |
3757 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3758 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3759 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3760 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3761 | }, |
4e7d34a6 | 3762 | |
1ceb70f8 | 3763 | /* PREFIX_0F59 */ |
c608c12e | 3764 | { |
507bd325 L |
3765 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3766 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3767 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3768 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3769 | }, |
4e7d34a6 | 3770 | |
1ceb70f8 | 3771 | /* PREFIX_0F5A */ |
041bd2e0 | 3772 | { |
507bd325 L |
3773 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3774 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3775 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3776 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3777 | }, |
4e7d34a6 | 3778 | |
1ceb70f8 | 3779 | /* PREFIX_0F5B */ |
041bd2e0 | 3780 | { |
507bd325 L |
3781 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3782 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3783 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3784 | }, |
4e7d34a6 | 3785 | |
1ceb70f8 | 3786 | /* PREFIX_0F5C */ |
041bd2e0 | 3787 | { |
507bd325 L |
3788 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3789 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3790 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3791 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3792 | }, |
4e7d34a6 | 3793 | |
1ceb70f8 | 3794 | /* PREFIX_0F5D */ |
041bd2e0 | 3795 | { |
507bd325 L |
3796 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3797 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3798 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3799 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3800 | }, |
4e7d34a6 | 3801 | |
1ceb70f8 | 3802 | /* PREFIX_0F5E */ |
041bd2e0 | 3803 | { |
507bd325 L |
3804 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3805 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3806 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3807 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3808 | }, |
4e7d34a6 | 3809 | |
1ceb70f8 | 3810 | /* PREFIX_0F5F */ |
041bd2e0 | 3811 | { |
507bd325 L |
3812 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3813 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3814 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3815 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3816 | }, |
4e7d34a6 | 3817 | |
1ceb70f8 | 3818 | /* PREFIX_0F60 */ |
041bd2e0 | 3819 | { |
507bd325 | 3820 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3821 | { Bad_Opcode }, |
507bd325 | 3822 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3823 | }, |
4e7d34a6 | 3824 | |
1ceb70f8 | 3825 | /* PREFIX_0F61 */ |
041bd2e0 | 3826 | { |
507bd325 | 3827 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3828 | { Bad_Opcode }, |
507bd325 | 3829 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3830 | }, |
4e7d34a6 | 3831 | |
1ceb70f8 | 3832 | /* PREFIX_0F62 */ |
041bd2e0 | 3833 | { |
507bd325 | 3834 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3835 | { Bad_Opcode }, |
507bd325 | 3836 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3837 | }, |
4e7d34a6 | 3838 | |
1ceb70f8 | 3839 | /* PREFIX_0F6C */ |
041bd2e0 | 3840 | { |
592d1631 L |
3841 | { Bad_Opcode }, |
3842 | { Bad_Opcode }, | |
507bd325 | 3843 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3844 | }, |
4e7d34a6 | 3845 | |
1ceb70f8 | 3846 | /* PREFIX_0F6D */ |
0f17484f | 3847 | { |
592d1631 L |
3848 | { Bad_Opcode }, |
3849 | { Bad_Opcode }, | |
507bd325 | 3850 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3851 | }, |
4e7d34a6 | 3852 | |
1ceb70f8 | 3853 | /* PREFIX_0F6F */ |
ca164297 | 3854 | { |
507bd325 L |
3855 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3856 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3857 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3858 | }, |
4e7d34a6 | 3859 | |
1ceb70f8 | 3860 | /* PREFIX_0F70 */ |
4e7d34a6 | 3861 | { |
507bd325 L |
3862 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3863 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3864 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3865 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3866 | }, |
3867 | ||
92fddf8e L |
3868 | /* PREFIX_0F73_REG_3 */ |
3869 | { | |
592d1631 L |
3870 | { Bad_Opcode }, |
3871 | { Bad_Opcode }, | |
bf890a93 | 3872 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3873 | }, |
3874 | ||
3875 | /* PREFIX_0F73_REG_7 */ | |
3876 | { | |
592d1631 L |
3877 | { Bad_Opcode }, |
3878 | { Bad_Opcode }, | |
bf890a93 | 3879 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3880 | }, |
3881 | ||
1ceb70f8 | 3882 | /* PREFIX_0F78 */ |
4e7d34a6 | 3883 | { |
bf890a93 | 3884 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3885 | { Bad_Opcode }, |
bf890a93 IT |
3886 | {"extrq", { XS, Ib, Ib }, 0 }, |
3887 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3888 | }, |
3889 | ||
1ceb70f8 | 3890 | /* PREFIX_0F79 */ |
4e7d34a6 | 3891 | { |
bf890a93 | 3892 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3893 | { Bad_Opcode }, |
bf890a93 IT |
3894 | {"extrq", { XM, XS }, 0 }, |
3895 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3896 | }, |
3897 | ||
1ceb70f8 | 3898 | /* PREFIX_0F7C */ |
ca164297 | 3899 | { |
592d1631 L |
3900 | { Bad_Opcode }, |
3901 | { Bad_Opcode }, | |
507bd325 L |
3902 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3903 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3904 | }, |
4e7d34a6 | 3905 | |
1ceb70f8 | 3906 | /* PREFIX_0F7D */ |
ca164297 | 3907 | { |
592d1631 L |
3908 | { Bad_Opcode }, |
3909 | { Bad_Opcode }, | |
507bd325 L |
3910 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3911 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3912 | }, |
4e7d34a6 | 3913 | |
1ceb70f8 | 3914 | /* PREFIX_0F7E */ |
ca164297 | 3915 | { |
507bd325 L |
3916 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3917 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3918 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3919 | }, |
4e7d34a6 | 3920 | |
1ceb70f8 | 3921 | /* PREFIX_0F7F */ |
ca164297 | 3922 | { |
507bd325 L |
3923 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3924 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3925 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3926 | }, |
4e7d34a6 | 3927 | |
f8687e93 | 3928 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3929 | { |
3930 | { Bad_Opcode }, | |
bf890a93 | 3931 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3932 | }, |
3933 | ||
f8687e93 | 3934 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3935 | { |
3936 | { Bad_Opcode }, | |
bf890a93 | 3937 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3938 | }, |
3939 | ||
f8687e93 | 3940 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3941 | { |
3942 | { Bad_Opcode }, | |
bf890a93 | 3943 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3944 | }, |
3945 | ||
f8687e93 | 3946 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3947 | { |
3948 | { Bad_Opcode }, | |
bf890a93 | 3949 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3950 | }, |
3951 | ||
f8687e93 | 3952 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3953 | { |
3954 | { "xsave", { FXSAVE }, 0 }, | |
3955 | { "ptwrite%LQ", { Edq }, 0 }, | |
3956 | }, | |
3957 | ||
f8687e93 | 3958 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3959 | { |
3960 | { Bad_Opcode }, | |
3961 | { "ptwrite%LQ", { Edq }, 0 }, | |
3962 | }, | |
3963 | ||
f8687e93 | 3964 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3965 | { |
3966 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3967 | }, |
3968 | ||
f8687e93 | 3969 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3970 | { |
3971 | { "lfence", { Skip_MODRM }, 0 }, | |
3972 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3973 | }, |
3974 | ||
f8687e93 | 3975 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3976 | { |
603555e5 L |
3977 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3978 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3979 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3980 | }, |
3981 | ||
f8687e93 | 3982 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3983 | { |
f8687e93 | 3984 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3985 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3986 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3987 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3988 | }, |
3989 | ||
f8687e93 | 3990 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3991 | { |
bf890a93 | 3992 | { "clflush", { Mb }, 0 }, |
963f3586 | 3993 | { Bad_Opcode }, |
bf890a93 | 3994 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3995 | }, |
3996 | ||
1ceb70f8 | 3997 | /* PREFIX_0FB8 */ |
ca164297 | 3998 | { |
592d1631 | 3999 | { Bad_Opcode }, |
bf890a93 | 4000 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4001 | }, |
4e7d34a6 | 4002 | |
f12dc422 L |
4003 | /* PREFIX_0FBC */ |
4004 | { | |
bf890a93 IT |
4005 | { "bsfS", { Gv, Ev }, 0 }, |
4006 | { "tzcntS", { Gv, Ev }, 0 }, | |
4007 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4008 | }, |
4009 | ||
1ceb70f8 | 4010 | /* PREFIX_0FBD */ |
050dfa73 | 4011 | { |
bf890a93 IT |
4012 | { "bsrS", { Gv, Ev }, 0 }, |
4013 | { "lzcntS", { Gv, Ev }, 0 }, | |
4014 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4015 | }, |
4016 | ||
1ceb70f8 | 4017 | /* PREFIX_0FC2 */ |
050dfa73 | 4018 | { |
507bd325 L |
4019 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4020 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4021 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4022 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4023 | }, |
246c51aa | 4024 | |
f8687e93 | 4025 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 4026 | { |
e1a1babd | 4027 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
4028 | }, |
4029 | ||
f8687e93 | 4030 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 4031 | { |
bf890a93 IT |
4032 | { "vmptrld",{ Mq }, 0 }, |
4033 | { "vmxon", { Mq }, 0 }, | |
4034 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4035 | }, |
4036 | ||
f8687e93 | 4037 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
4038 | { |
4039 | { "rdrand", { Ev }, 0 }, | |
4040 | { Bad_Opcode }, | |
4041 | { "rdrand", { Ev }, 0 } | |
4042 | }, | |
4043 | ||
f8687e93 | 4044 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
4045 | { |
4046 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4047 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4048 | { "rdseed", { Ev }, 0 }, |
4049 | }, | |
4050 | ||
1ceb70f8 | 4051 | /* PREFIX_0FD0 */ |
050dfa73 | 4052 | { |
592d1631 L |
4053 | { Bad_Opcode }, |
4054 | { Bad_Opcode }, | |
bf890a93 IT |
4055 | { "addsubpd", { XM, EXx }, 0 }, |
4056 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4057 | }, |
050dfa73 | 4058 | |
1ceb70f8 | 4059 | /* PREFIX_0FD6 */ |
050dfa73 | 4060 | { |
592d1631 | 4061 | { Bad_Opcode }, |
bf890a93 IT |
4062 | { "movq2dq",{ XM, MS }, 0 }, |
4063 | { "movq", { EXqS, XM }, 0 }, | |
4064 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4065 | }, |
4066 | ||
1ceb70f8 | 4067 | /* PREFIX_0FE6 */ |
7918206c | 4068 | { |
592d1631 | 4069 | { Bad_Opcode }, |
507bd325 L |
4070 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4071 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4072 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4073 | }, |
8b38ad71 | 4074 | |
1ceb70f8 | 4075 | /* PREFIX_0FE7 */ |
8b38ad71 | 4076 | { |
507bd325 | 4077 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4078 | { Bad_Opcode }, |
75c135a8 | 4079 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4080 | }, |
4081 | ||
1ceb70f8 | 4082 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4083 | { |
592d1631 L |
4084 | { Bad_Opcode }, |
4085 | { Bad_Opcode }, | |
4086 | { Bad_Opcode }, | |
1ceb70f8 | 4087 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4088 | }, |
4089 | ||
1ceb70f8 | 4090 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4091 | { |
507bd325 | 4092 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4093 | { Bad_Opcode }, |
507bd325 | 4094 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4095 | }, |
42903f7f | 4096 | |
1ceb70f8 | 4097 | /* PREFIX_0F3810 */ |
42903f7f | 4098 | { |
592d1631 L |
4099 | { Bad_Opcode }, |
4100 | { Bad_Opcode }, | |
507bd325 | 4101 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4102 | }, |
4103 | ||
1ceb70f8 | 4104 | /* PREFIX_0F3814 */ |
42903f7f | 4105 | { |
592d1631 L |
4106 | { Bad_Opcode }, |
4107 | { Bad_Opcode }, | |
507bd325 | 4108 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4109 | }, |
4110 | ||
1ceb70f8 | 4111 | /* PREFIX_0F3815 */ |
42903f7f | 4112 | { |
592d1631 L |
4113 | { Bad_Opcode }, |
4114 | { Bad_Opcode }, | |
507bd325 | 4115 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4116 | }, |
4117 | ||
1ceb70f8 | 4118 | /* PREFIX_0F3817 */ |
42903f7f | 4119 | { |
592d1631 L |
4120 | { Bad_Opcode }, |
4121 | { Bad_Opcode }, | |
507bd325 | 4122 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4123 | }, |
4124 | ||
1ceb70f8 | 4125 | /* PREFIX_0F3820 */ |
42903f7f | 4126 | { |
592d1631 L |
4127 | { Bad_Opcode }, |
4128 | { Bad_Opcode }, | |
507bd325 | 4129 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4130 | }, |
4131 | ||
1ceb70f8 | 4132 | /* PREFIX_0F3821 */ |
42903f7f | 4133 | { |
592d1631 L |
4134 | { Bad_Opcode }, |
4135 | { Bad_Opcode }, | |
507bd325 | 4136 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4137 | }, |
4138 | ||
1ceb70f8 | 4139 | /* PREFIX_0F3822 */ |
42903f7f | 4140 | { |
592d1631 L |
4141 | { Bad_Opcode }, |
4142 | { Bad_Opcode }, | |
507bd325 | 4143 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4144 | }, |
4145 | ||
1ceb70f8 | 4146 | /* PREFIX_0F3823 */ |
42903f7f | 4147 | { |
592d1631 L |
4148 | { Bad_Opcode }, |
4149 | { Bad_Opcode }, | |
507bd325 | 4150 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4151 | }, |
4152 | ||
1ceb70f8 | 4153 | /* PREFIX_0F3824 */ |
42903f7f | 4154 | { |
592d1631 L |
4155 | { Bad_Opcode }, |
4156 | { Bad_Opcode }, | |
507bd325 | 4157 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4158 | }, |
4159 | ||
1ceb70f8 | 4160 | /* PREFIX_0F3825 */ |
42903f7f | 4161 | { |
592d1631 L |
4162 | { Bad_Opcode }, |
4163 | { Bad_Opcode }, | |
507bd325 | 4164 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4165 | }, |
4166 | ||
1ceb70f8 | 4167 | /* PREFIX_0F3828 */ |
42903f7f | 4168 | { |
592d1631 L |
4169 | { Bad_Opcode }, |
4170 | { Bad_Opcode }, | |
507bd325 | 4171 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4172 | }, |
4173 | ||
1ceb70f8 | 4174 | /* PREFIX_0F3829 */ |
42903f7f | 4175 | { |
592d1631 L |
4176 | { Bad_Opcode }, |
4177 | { Bad_Opcode }, | |
507bd325 | 4178 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4179 | }, |
4180 | ||
1ceb70f8 | 4181 | /* PREFIX_0F382A */ |
42903f7f | 4182 | { |
592d1631 L |
4183 | { Bad_Opcode }, |
4184 | { Bad_Opcode }, | |
75c135a8 | 4185 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4186 | }, |
4187 | ||
1ceb70f8 | 4188 | /* PREFIX_0F382B */ |
42903f7f | 4189 | { |
592d1631 L |
4190 | { Bad_Opcode }, |
4191 | { Bad_Opcode }, | |
507bd325 | 4192 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4193 | }, |
4194 | ||
1ceb70f8 | 4195 | /* PREFIX_0F3830 */ |
42903f7f | 4196 | { |
592d1631 L |
4197 | { Bad_Opcode }, |
4198 | { Bad_Opcode }, | |
507bd325 | 4199 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4200 | }, |
4201 | ||
1ceb70f8 | 4202 | /* PREFIX_0F3831 */ |
42903f7f | 4203 | { |
592d1631 L |
4204 | { Bad_Opcode }, |
4205 | { Bad_Opcode }, | |
507bd325 | 4206 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4207 | }, |
4208 | ||
1ceb70f8 | 4209 | /* PREFIX_0F3832 */ |
42903f7f | 4210 | { |
592d1631 L |
4211 | { Bad_Opcode }, |
4212 | { Bad_Opcode }, | |
507bd325 | 4213 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4214 | }, |
4215 | ||
1ceb70f8 | 4216 | /* PREFIX_0F3833 */ |
42903f7f | 4217 | { |
592d1631 L |
4218 | { Bad_Opcode }, |
4219 | { Bad_Opcode }, | |
507bd325 | 4220 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4221 | }, |
4222 | ||
1ceb70f8 | 4223 | /* PREFIX_0F3834 */ |
42903f7f | 4224 | { |
592d1631 L |
4225 | { Bad_Opcode }, |
4226 | { Bad_Opcode }, | |
507bd325 | 4227 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4228 | }, |
4229 | ||
1ceb70f8 | 4230 | /* PREFIX_0F3835 */ |
42903f7f | 4231 | { |
592d1631 L |
4232 | { Bad_Opcode }, |
4233 | { Bad_Opcode }, | |
507bd325 | 4234 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4235 | }, |
4236 | ||
1ceb70f8 | 4237 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4238 | { |
592d1631 L |
4239 | { Bad_Opcode }, |
4240 | { Bad_Opcode }, | |
507bd325 | 4241 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4242 | }, |
4243 | ||
1ceb70f8 | 4244 | /* PREFIX_0F3838 */ |
42903f7f | 4245 | { |
592d1631 L |
4246 | { Bad_Opcode }, |
4247 | { Bad_Opcode }, | |
507bd325 | 4248 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4249 | }, |
4250 | ||
1ceb70f8 | 4251 | /* PREFIX_0F3839 */ |
42903f7f | 4252 | { |
592d1631 L |
4253 | { Bad_Opcode }, |
4254 | { Bad_Opcode }, | |
507bd325 | 4255 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4256 | }, |
4257 | ||
1ceb70f8 | 4258 | /* PREFIX_0F383A */ |
42903f7f | 4259 | { |
592d1631 L |
4260 | { Bad_Opcode }, |
4261 | { Bad_Opcode }, | |
507bd325 | 4262 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4263 | }, |
4264 | ||
1ceb70f8 | 4265 | /* PREFIX_0F383B */ |
42903f7f | 4266 | { |
592d1631 L |
4267 | { Bad_Opcode }, |
4268 | { Bad_Opcode }, | |
507bd325 | 4269 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4270 | }, |
4271 | ||
1ceb70f8 | 4272 | /* PREFIX_0F383C */ |
42903f7f | 4273 | { |
592d1631 L |
4274 | { Bad_Opcode }, |
4275 | { Bad_Opcode }, | |
507bd325 | 4276 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4277 | }, |
4278 | ||
1ceb70f8 | 4279 | /* PREFIX_0F383D */ |
42903f7f | 4280 | { |
592d1631 L |
4281 | { Bad_Opcode }, |
4282 | { Bad_Opcode }, | |
507bd325 | 4283 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4284 | }, |
4285 | ||
1ceb70f8 | 4286 | /* PREFIX_0F383E */ |
42903f7f | 4287 | { |
592d1631 L |
4288 | { Bad_Opcode }, |
4289 | { Bad_Opcode }, | |
507bd325 | 4290 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4291 | }, |
4292 | ||
1ceb70f8 | 4293 | /* PREFIX_0F383F */ |
42903f7f | 4294 | { |
592d1631 L |
4295 | { Bad_Opcode }, |
4296 | { Bad_Opcode }, | |
507bd325 | 4297 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4298 | }, |
4299 | ||
1ceb70f8 | 4300 | /* PREFIX_0F3840 */ |
42903f7f | 4301 | { |
592d1631 L |
4302 | { Bad_Opcode }, |
4303 | { Bad_Opcode }, | |
507bd325 | 4304 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4305 | }, |
4306 | ||
1ceb70f8 | 4307 | /* PREFIX_0F3841 */ |
42903f7f | 4308 | { |
592d1631 L |
4309 | { Bad_Opcode }, |
4310 | { Bad_Opcode }, | |
507bd325 | 4311 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4312 | }, |
4313 | ||
f1f8f695 L |
4314 | /* PREFIX_0F3880 */ |
4315 | { | |
592d1631 L |
4316 | { Bad_Opcode }, |
4317 | { Bad_Opcode }, | |
507bd325 | 4318 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4319 | }, |
4320 | ||
4321 | /* PREFIX_0F3881 */ | |
4322 | { | |
592d1631 L |
4323 | { Bad_Opcode }, |
4324 | { Bad_Opcode }, | |
507bd325 | 4325 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4326 | }, |
4327 | ||
6c30d220 L |
4328 | /* PREFIX_0F3882 */ |
4329 | { | |
4330 | { Bad_Opcode }, | |
4331 | { Bad_Opcode }, | |
507bd325 | 4332 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4333 | }, |
4334 | ||
a0046408 L |
4335 | /* PREFIX_0F38C8 */ |
4336 | { | |
507bd325 | 4337 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4338 | }, |
4339 | ||
4340 | /* PREFIX_0F38C9 */ | |
4341 | { | |
507bd325 | 4342 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4343 | }, |
4344 | ||
4345 | /* PREFIX_0F38CA */ | |
4346 | { | |
507bd325 | 4347 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4348 | }, |
4349 | ||
4350 | /* PREFIX_0F38CB */ | |
4351 | { | |
507bd325 | 4352 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4353 | }, |
4354 | ||
4355 | /* PREFIX_0F38CC */ | |
4356 | { | |
507bd325 | 4357 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4358 | }, |
4359 | ||
4360 | /* PREFIX_0F38CD */ | |
4361 | { | |
507bd325 | 4362 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4363 | }, |
4364 | ||
48521003 IT |
4365 | /* PREFIX_0F38CF */ |
4366 | { | |
4367 | { Bad_Opcode }, | |
4368 | { Bad_Opcode }, | |
4369 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4370 | }, | |
4371 | ||
c0f3af97 L |
4372 | /* PREFIX_0F38DB */ |
4373 | { | |
592d1631 L |
4374 | { Bad_Opcode }, |
4375 | { Bad_Opcode }, | |
507bd325 | 4376 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4377 | }, |
4378 | ||
4379 | /* PREFIX_0F38DC */ | |
4380 | { | |
592d1631 L |
4381 | { Bad_Opcode }, |
4382 | { Bad_Opcode }, | |
507bd325 | 4383 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4384 | }, |
4385 | ||
4386 | /* PREFIX_0F38DD */ | |
4387 | { | |
592d1631 L |
4388 | { Bad_Opcode }, |
4389 | { Bad_Opcode }, | |
507bd325 | 4390 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4391 | }, |
4392 | ||
4393 | /* PREFIX_0F38DE */ | |
4394 | { | |
592d1631 L |
4395 | { Bad_Opcode }, |
4396 | { Bad_Opcode }, | |
507bd325 | 4397 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4398 | }, |
4399 | ||
4400 | /* PREFIX_0F38DF */ | |
4401 | { | |
592d1631 L |
4402 | { Bad_Opcode }, |
4403 | { Bad_Opcode }, | |
507bd325 | 4404 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4405 | }, |
4406 | ||
1ceb70f8 | 4407 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4408 | { |
507bd325 | 4409 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4410 | { Bad_Opcode }, |
507bd325 L |
4411 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4412 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4413 | }, |
4414 | ||
1ceb70f8 | 4415 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4416 | { |
507bd325 | 4417 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4418 | { Bad_Opcode }, |
507bd325 L |
4419 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4420 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4421 | }, |
4422 | ||
603555e5 | 4423 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4424 | { |
4425 | { Bad_Opcode }, | |
603555e5 L |
4426 | { Bad_Opcode }, |
4427 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4428 | }, | |
4429 | ||
4430 | /* PREFIX_0F38F6 */ | |
4431 | { | |
4432 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4433 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4434 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4435 | { Bad_Opcode }, |
4436 | }, | |
4437 | ||
c0a30a9f L |
4438 | /* PREFIX_0F38F8 */ |
4439 | { | |
4440 | { Bad_Opcode }, | |
5d79adc4 | 4441 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4442 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4443 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4444 | }, |
4445 | ||
4446 | /* PREFIX_0F38F9 */ | |
4447 | { | |
4448 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4449 | }, | |
4450 | ||
1ceb70f8 | 4451 | /* PREFIX_0F3A08 */ |
42903f7f | 4452 | { |
592d1631 L |
4453 | { Bad_Opcode }, |
4454 | { Bad_Opcode }, | |
507bd325 | 4455 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4456 | }, |
4457 | ||
1ceb70f8 | 4458 | /* PREFIX_0F3A09 */ |
42903f7f | 4459 | { |
592d1631 L |
4460 | { Bad_Opcode }, |
4461 | { Bad_Opcode }, | |
507bd325 | 4462 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4463 | }, |
4464 | ||
1ceb70f8 | 4465 | /* PREFIX_0F3A0A */ |
42903f7f | 4466 | { |
592d1631 L |
4467 | { Bad_Opcode }, |
4468 | { Bad_Opcode }, | |
507bd325 | 4469 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4470 | }, |
4471 | ||
1ceb70f8 | 4472 | /* PREFIX_0F3A0B */ |
42903f7f | 4473 | { |
592d1631 L |
4474 | { Bad_Opcode }, |
4475 | { Bad_Opcode }, | |
507bd325 | 4476 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4477 | }, |
4478 | ||
1ceb70f8 | 4479 | /* PREFIX_0F3A0C */ |
42903f7f | 4480 | { |
592d1631 L |
4481 | { Bad_Opcode }, |
4482 | { Bad_Opcode }, | |
507bd325 | 4483 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4484 | }, |
4485 | ||
1ceb70f8 | 4486 | /* PREFIX_0F3A0D */ |
42903f7f | 4487 | { |
592d1631 L |
4488 | { Bad_Opcode }, |
4489 | { Bad_Opcode }, | |
507bd325 | 4490 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4491 | }, |
4492 | ||
1ceb70f8 | 4493 | /* PREFIX_0F3A0E */ |
42903f7f | 4494 | { |
592d1631 L |
4495 | { Bad_Opcode }, |
4496 | { Bad_Opcode }, | |
507bd325 | 4497 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4498 | }, |
4499 | ||
1ceb70f8 | 4500 | /* PREFIX_0F3A14 */ |
42903f7f | 4501 | { |
592d1631 L |
4502 | { Bad_Opcode }, |
4503 | { Bad_Opcode }, | |
507bd325 | 4504 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4505 | }, |
4506 | ||
1ceb70f8 | 4507 | /* PREFIX_0F3A15 */ |
42903f7f | 4508 | { |
592d1631 L |
4509 | { Bad_Opcode }, |
4510 | { Bad_Opcode }, | |
507bd325 | 4511 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4512 | }, |
4513 | ||
1ceb70f8 | 4514 | /* PREFIX_0F3A16 */ |
42903f7f | 4515 | { |
592d1631 L |
4516 | { Bad_Opcode }, |
4517 | { Bad_Opcode }, | |
507bd325 | 4518 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4519 | }, |
4520 | ||
1ceb70f8 | 4521 | /* PREFIX_0F3A17 */ |
42903f7f | 4522 | { |
592d1631 L |
4523 | { Bad_Opcode }, |
4524 | { Bad_Opcode }, | |
507bd325 | 4525 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4526 | }, |
4527 | ||
1ceb70f8 | 4528 | /* PREFIX_0F3A20 */ |
42903f7f | 4529 | { |
592d1631 L |
4530 | { Bad_Opcode }, |
4531 | { Bad_Opcode }, | |
507bd325 | 4532 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4533 | }, |
4534 | ||
1ceb70f8 | 4535 | /* PREFIX_0F3A21 */ |
42903f7f | 4536 | { |
592d1631 L |
4537 | { Bad_Opcode }, |
4538 | { Bad_Opcode }, | |
507bd325 | 4539 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4540 | }, |
4541 | ||
1ceb70f8 | 4542 | /* PREFIX_0F3A22 */ |
42903f7f | 4543 | { |
592d1631 L |
4544 | { Bad_Opcode }, |
4545 | { Bad_Opcode }, | |
507bd325 | 4546 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4547 | }, |
4548 | ||
1ceb70f8 | 4549 | /* PREFIX_0F3A40 */ |
42903f7f | 4550 | { |
592d1631 L |
4551 | { Bad_Opcode }, |
4552 | { Bad_Opcode }, | |
507bd325 | 4553 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4554 | }, |
4555 | ||
1ceb70f8 | 4556 | /* PREFIX_0F3A41 */ |
42903f7f | 4557 | { |
592d1631 L |
4558 | { Bad_Opcode }, |
4559 | { Bad_Opcode }, | |
507bd325 | 4560 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4561 | }, |
4562 | ||
1ceb70f8 | 4563 | /* PREFIX_0F3A42 */ |
42903f7f | 4564 | { |
592d1631 L |
4565 | { Bad_Opcode }, |
4566 | { Bad_Opcode }, | |
507bd325 | 4567 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4568 | }, |
381d071f | 4569 | |
c0f3af97 L |
4570 | /* PREFIX_0F3A44 */ |
4571 | { | |
592d1631 L |
4572 | { Bad_Opcode }, |
4573 | { Bad_Opcode }, | |
507bd325 | 4574 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4575 | }, |
4576 | ||
1ceb70f8 | 4577 | /* PREFIX_0F3A60 */ |
381d071f | 4578 | { |
592d1631 L |
4579 | { Bad_Opcode }, |
4580 | { Bad_Opcode }, | |
15c7c1d8 | 4581 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4582 | }, |
4583 | ||
1ceb70f8 | 4584 | /* PREFIX_0F3A61 */ |
381d071f | 4585 | { |
592d1631 L |
4586 | { Bad_Opcode }, |
4587 | { Bad_Opcode }, | |
15c7c1d8 | 4588 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4589 | }, |
4590 | ||
1ceb70f8 | 4591 | /* PREFIX_0F3A62 */ |
381d071f | 4592 | { |
592d1631 L |
4593 | { Bad_Opcode }, |
4594 | { Bad_Opcode }, | |
507bd325 | 4595 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4596 | }, |
4597 | ||
1ceb70f8 | 4598 | /* PREFIX_0F3A63 */ |
381d071f | 4599 | { |
592d1631 L |
4600 | { Bad_Opcode }, |
4601 | { Bad_Opcode }, | |
507bd325 | 4602 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4603 | }, |
09a2c6cf | 4604 | |
a0046408 L |
4605 | /* PREFIX_0F3ACC */ |
4606 | { | |
507bd325 | 4607 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4608 | }, |
4609 | ||
48521003 IT |
4610 | /* PREFIX_0F3ACE */ |
4611 | { | |
4612 | { Bad_Opcode }, | |
4613 | { Bad_Opcode }, | |
4614 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4615 | }, | |
4616 | ||
4617 | /* PREFIX_0F3ACF */ | |
4618 | { | |
4619 | { Bad_Opcode }, | |
4620 | { Bad_Opcode }, | |
4621 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4622 | }, | |
4623 | ||
c0f3af97 | 4624 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4625 | { |
592d1631 L |
4626 | { Bad_Opcode }, |
4627 | { Bad_Opcode }, | |
507bd325 | 4628 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4629 | }, |
4630 | ||
592a252b | 4631 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4632 | { |
ec6f095a L |
4633 | { "vmovups", { XM, EXx }, 0 }, |
4634 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, | |
4635 | { "vmovupd", { XM, EXx }, 0 }, | |
4636 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, | |
09a2c6cf L |
4637 | }, |
4638 | ||
592a252b | 4639 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4640 | { |
ec6f095a L |
4641 | { "vmovups", { EXxS, XM }, 0 }, |
4642 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4643 | { "vmovupd", { EXxS, XM }, 0 }, | |
4644 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4645 | }, |
4646 | ||
592a252b | 4647 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4648 | { |
592a252b | 4649 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4650 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4651 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4652 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4653 | }, |
4654 | ||
592a252b | 4655 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4656 | { |
592a252b | 4657 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4658 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4659 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4660 | }, |
7c52e0e8 | 4661 | |
592a252b | 4662 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4663 | { |
592d1631 | 4664 | { Bad_Opcode }, |
2b7bcc87 | 4665 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4666 | { Bad_Opcode }, |
2b7bcc87 | 4667 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4668 | }, |
7c52e0e8 | 4669 | |
592a252b | 4670 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4671 | { |
592d1631 | 4672 | { Bad_Opcode }, |
2b7bcc87 | 4673 | { "vcvttss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4674 | { Bad_Opcode }, |
2b7bcc87 | 4675 | { "vcvttsd2si", { Gdq, EXqScalar }, 0 }, |
5f754f58 | 4676 | }, |
7c52e0e8 | 4677 | |
592a252b | 4678 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4679 | { |
592d1631 | 4680 | { Bad_Opcode }, |
2b7bcc87 | 4681 | { "vcvtss2si", { Gdq, EXdScalar }, 0 }, |
592d1631 | 4682 | { Bad_Opcode }, |
2b7bcc87 | 4683 | { "vcvtsd2si", { Gdq, EXqScalar }, 0 }, |
7c52e0e8 L |
4684 | }, |
4685 | ||
592a252b | 4686 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4687 | { |
ec6f095a | 4688 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4689 | { Bad_Opcode }, |
ec6f095a | 4690 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4691 | }, |
4692 | ||
592a252b | 4693 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4694 | { |
ec6f095a | 4695 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4696 | { Bad_Opcode }, |
ec6f095a | 4697 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4698 | }, |
4699 | ||
43234a1e L |
4700 | /* PREFIX_VEX_0F41 */ |
4701 | { | |
4702 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4703 | { Bad_Opcode }, |
4704 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4705 | }, |
4706 | ||
4707 | /* PREFIX_VEX_0F42 */ | |
4708 | { | |
4709 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4710 | { Bad_Opcode }, |
4711 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4712 | }, |
4713 | ||
4714 | /* PREFIX_VEX_0F44 */ | |
4715 | { | |
4716 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4717 | { Bad_Opcode }, |
4718 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4719 | }, |
4720 | ||
4721 | /* PREFIX_VEX_0F45 */ | |
4722 | { | |
4723 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4724 | { Bad_Opcode }, |
4725 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4726 | }, |
4727 | ||
4728 | /* PREFIX_VEX_0F46 */ | |
4729 | { | |
4730 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4731 | { Bad_Opcode }, |
4732 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4733 | }, |
4734 | ||
4735 | /* PREFIX_VEX_0F47 */ | |
4736 | { | |
4737 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4738 | { Bad_Opcode }, |
4739 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4740 | }, |
4741 | ||
1ba585e8 | 4742 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4743 | { |
1ba585e8 | 4744 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4745 | { Bad_Opcode }, |
1ba585e8 IT |
4746 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4747 | }, | |
4748 | ||
4749 | /* PREFIX_VEX_0F4B */ | |
4750 | { | |
4751 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4752 | { Bad_Opcode }, |
4753 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4754 | }, | |
4755 | ||
592a252b | 4756 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4757 | { |
ec6f095a L |
4758 | { "vsqrtps", { XM, EXx }, 0 }, |
4759 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4760 | { "vsqrtpd", { XM, EXx }, 0 }, | |
4761 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4762 | }, |
4763 | ||
592a252b | 4764 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4765 | { |
ec6f095a L |
4766 | { "vrsqrtps", { XM, EXx }, 0 }, |
4767 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4768 | }, |
4769 | ||
592a252b | 4770 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4771 | { |
ec6f095a L |
4772 | { "vrcpps", { XM, EXx }, 0 }, |
4773 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4774 | }, |
4775 | ||
592a252b | 4776 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4777 | { |
ec6f095a L |
4778 | { "vaddps", { XM, Vex, EXx }, 0 }, |
4779 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4780 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
4781 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4782 | }, |
4783 | ||
592a252b | 4784 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4785 | { |
ec6f095a L |
4786 | { "vmulps", { XM, Vex, EXx }, 0 }, |
4787 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4788 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
4789 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4790 | }, |
4791 | ||
592a252b | 4792 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4793 | { |
ec6f095a L |
4794 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
4795 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4796 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
4797 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4798 | }, |
4799 | ||
592a252b | 4800 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4801 | { |
ec6f095a L |
4802 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4803 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4804 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4805 | }, |
4806 | ||
592a252b | 4807 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4808 | { |
ec6f095a L |
4809 | { "vsubps", { XM, Vex, EXx }, 0 }, |
4810 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4811 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
4812 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4813 | }, |
4814 | ||
592a252b | 4815 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4816 | { |
ec6f095a L |
4817 | { "vminps", { XM, Vex, EXx }, 0 }, |
4818 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4819 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
4820 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4821 | }, |
4822 | ||
592a252b | 4823 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4824 | { |
ec6f095a L |
4825 | { "vdivps", { XM, Vex, EXx }, 0 }, |
4826 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4827 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
4828 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4829 | }, |
4830 | ||
592a252b | 4831 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4832 | { |
ec6f095a L |
4833 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
4834 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4835 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
4836 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4837 | }, |
4838 | ||
592a252b | 4839 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4840 | { |
592d1631 L |
4841 | { Bad_Opcode }, |
4842 | { Bad_Opcode }, | |
ec6f095a | 4843 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4844 | }, |
4845 | ||
592a252b | 4846 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4847 | { |
592d1631 L |
4848 | { Bad_Opcode }, |
4849 | { Bad_Opcode }, | |
ec6f095a | 4850 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4851 | }, |
4852 | ||
592a252b | 4853 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4854 | { |
592d1631 L |
4855 | { Bad_Opcode }, |
4856 | { Bad_Opcode }, | |
ec6f095a | 4857 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4858 | }, |
4859 | ||
592a252b | 4860 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4861 | { |
592d1631 L |
4862 | { Bad_Opcode }, |
4863 | { Bad_Opcode }, | |
ec6f095a | 4864 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4865 | }, |
4866 | ||
592a252b | 4867 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4868 | { |
592d1631 L |
4869 | { Bad_Opcode }, |
4870 | { Bad_Opcode }, | |
ec6f095a | 4871 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4872 | }, |
4873 | ||
592a252b | 4874 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4875 | { |
592d1631 L |
4876 | { Bad_Opcode }, |
4877 | { Bad_Opcode }, | |
ec6f095a | 4878 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4879 | }, |
4880 | ||
592a252b | 4881 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4882 | { |
592d1631 L |
4883 | { Bad_Opcode }, |
4884 | { Bad_Opcode }, | |
ec6f095a | 4885 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4886 | }, |
6439fc28 | 4887 | |
592a252b | 4888 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4889 | { |
592d1631 L |
4890 | { Bad_Opcode }, |
4891 | { Bad_Opcode }, | |
ec6f095a | 4892 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4893 | }, |
4894 | ||
592a252b | 4895 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4896 | { |
592d1631 L |
4897 | { Bad_Opcode }, |
4898 | { Bad_Opcode }, | |
ec6f095a | 4899 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4900 | }, |
4901 | ||
592a252b | 4902 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4903 | { |
592d1631 L |
4904 | { Bad_Opcode }, |
4905 | { Bad_Opcode }, | |
ec6f095a | 4906 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4907 | }, |
4908 | ||
592a252b | 4909 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4910 | { |
592d1631 L |
4911 | { Bad_Opcode }, |
4912 | { Bad_Opcode }, | |
ec6f095a | 4913 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4914 | }, |
4915 | ||
592a252b | 4916 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4917 | { |
592d1631 L |
4918 | { Bad_Opcode }, |
4919 | { Bad_Opcode }, | |
ec6f095a | 4920 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4921 | }, |
4922 | ||
592a252b | 4923 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4924 | { |
592d1631 L |
4925 | { Bad_Opcode }, |
4926 | { Bad_Opcode }, | |
ec6f095a | 4927 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4928 | }, |
4929 | ||
592a252b | 4930 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4931 | { |
592d1631 L |
4932 | { Bad_Opcode }, |
4933 | { Bad_Opcode }, | |
ec6f095a | 4934 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4935 | }, |
4936 | ||
592a252b | 4937 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4938 | { |
592d1631 L |
4939 | { Bad_Opcode }, |
4940 | { Bad_Opcode }, | |
592a252b | 4941 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4942 | }, |
4943 | ||
592a252b | 4944 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4945 | { |
592d1631 | 4946 | { Bad_Opcode }, |
ec6f095a L |
4947 | { "vmovdqu", { XM, EXx }, 0 }, |
4948 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4949 | }, |
4950 | ||
592a252b | 4951 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4952 | { |
592d1631 | 4953 | { Bad_Opcode }, |
ec6f095a L |
4954 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4955 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4956 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4957 | }, |
4958 | ||
592a252b | 4959 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4960 | { |
592d1631 L |
4961 | { Bad_Opcode }, |
4962 | { Bad_Opcode }, | |
ec6f095a | 4963 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4964 | }, |
4965 | ||
592a252b | 4966 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4967 | { |
592d1631 L |
4968 | { Bad_Opcode }, |
4969 | { Bad_Opcode }, | |
ec6f095a | 4970 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4971 | }, |
4972 | ||
592a252b | 4973 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4974 | { |
592d1631 L |
4975 | { Bad_Opcode }, |
4976 | { Bad_Opcode }, | |
ec6f095a | 4977 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4978 | }, |
4979 | ||
592a252b | 4980 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4981 | { |
592d1631 L |
4982 | { Bad_Opcode }, |
4983 | { Bad_Opcode }, | |
ec6f095a | 4984 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4985 | }, |
4986 | ||
592a252b | 4987 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4988 | { |
592d1631 L |
4989 | { Bad_Opcode }, |
4990 | { Bad_Opcode }, | |
ec6f095a | 4991 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4992 | }, |
4993 | ||
592a252b | 4994 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4995 | { |
592d1631 L |
4996 | { Bad_Opcode }, |
4997 | { Bad_Opcode }, | |
ec6f095a | 4998 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4999 | }, |
5000 | ||
592a252b | 5001 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5002 | { |
592d1631 L |
5003 | { Bad_Opcode }, |
5004 | { Bad_Opcode }, | |
ec6f095a | 5005 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5006 | }, |
5007 | ||
592a252b | 5008 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5009 | { |
592d1631 L |
5010 | { Bad_Opcode }, |
5011 | { Bad_Opcode }, | |
ec6f095a | 5012 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5013 | }, |
5014 | ||
592a252b | 5015 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5016 | { |
592d1631 L |
5017 | { Bad_Opcode }, |
5018 | { Bad_Opcode }, | |
ec6f095a | 5019 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5020 | }, |
5021 | ||
592a252b | 5022 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5023 | { |
592d1631 L |
5024 | { Bad_Opcode }, |
5025 | { Bad_Opcode }, | |
ec6f095a | 5026 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5027 | }, |
5028 | ||
592a252b | 5029 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5030 | { |
592d1631 L |
5031 | { Bad_Opcode }, |
5032 | { Bad_Opcode }, | |
ec6f095a | 5033 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5034 | }, |
5035 | ||
592a252b | 5036 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5037 | { |
592d1631 L |
5038 | { Bad_Opcode }, |
5039 | { Bad_Opcode }, | |
ec6f095a | 5040 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5041 | }, |
5042 | ||
592a252b | 5043 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5044 | { |
592d1631 L |
5045 | { Bad_Opcode }, |
5046 | { Bad_Opcode }, | |
ec6f095a | 5047 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5048 | }, |
5049 | ||
592a252b | 5050 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5051 | { |
ec6f095a | 5052 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5053 | }, |
5054 | ||
592a252b | 5055 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5056 | { |
592d1631 L |
5057 | { Bad_Opcode }, |
5058 | { Bad_Opcode }, | |
ec6f095a L |
5059 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5060 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5064 | { |
592d1631 L |
5065 | { Bad_Opcode }, |
5066 | { Bad_Opcode }, | |
ec6f095a L |
5067 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5068 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5069 | }, |
5070 | ||
592a252b | 5071 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5072 | { |
592d1631 | 5073 | { Bad_Opcode }, |
592a252b L |
5074 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5075 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5076 | }, |
5077 | ||
592a252b | 5078 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5079 | { |
592d1631 | 5080 | { Bad_Opcode }, |
ec6f095a L |
5081 | { "vmovdqu", { EXxS, XM }, 0 }, |
5082 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5083 | }, |
5084 | ||
43234a1e L |
5085 | /* PREFIX_VEX_0F90 */ |
5086 | { | |
5087 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5088 | { Bad_Opcode }, |
5089 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5090 | }, |
5091 | ||
5092 | /* PREFIX_VEX_0F91 */ | |
5093 | { | |
5094 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5095 | { Bad_Opcode }, |
5096 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5097 | }, |
5098 | ||
5099 | /* PREFIX_VEX_0F92 */ | |
5100 | { | |
5101 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5102 | { Bad_Opcode }, |
90a915bf | 5103 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5104 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5105 | }, |
5106 | ||
5107 | /* PREFIX_VEX_0F93 */ | |
5108 | { | |
5109 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5110 | { Bad_Opcode }, |
90a915bf | 5111 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5112 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5113 | }, |
5114 | ||
5115 | /* PREFIX_VEX_0F98 */ | |
5116 | { | |
5117 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5118 | { Bad_Opcode }, |
5119 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5120 | }, | |
5121 | ||
5122 | /* PREFIX_VEX_0F99 */ | |
5123 | { | |
5124 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5125 | { Bad_Opcode }, | |
5126 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5127 | }, |
5128 | ||
592a252b | 5129 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5130 | { |
ec6f095a L |
5131 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5132 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, | |
5133 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, | |
5134 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, | |
c0f3af97 L |
5135 | }, |
5136 | ||
592a252b | 5137 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5138 | { |
592d1631 L |
5139 | { Bad_Opcode }, |
5140 | { Bad_Opcode }, | |
592a252b | 5141 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5142 | }, |
5143 | ||
592a252b | 5144 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5145 | { |
592d1631 L |
5146 | { Bad_Opcode }, |
5147 | { Bad_Opcode }, | |
592a252b | 5148 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5149 | }, |
5150 | ||
592a252b | 5151 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5152 | { |
592d1631 L |
5153 | { Bad_Opcode }, |
5154 | { Bad_Opcode }, | |
ec6f095a L |
5155 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5156 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5157 | }, |
5158 | ||
592a252b | 5159 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5160 | { |
592d1631 L |
5161 | { Bad_Opcode }, |
5162 | { Bad_Opcode }, | |
ec6f095a | 5163 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5164 | }, |
5165 | ||
592a252b | 5166 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5167 | { |
592d1631 L |
5168 | { Bad_Opcode }, |
5169 | { Bad_Opcode }, | |
ec6f095a | 5170 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5171 | }, |
5172 | ||
592a252b | 5173 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5174 | { |
592d1631 L |
5175 | { Bad_Opcode }, |
5176 | { Bad_Opcode }, | |
ec6f095a | 5177 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5178 | }, |
5179 | ||
592a252b | 5180 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5181 | { |
592d1631 L |
5182 | { Bad_Opcode }, |
5183 | { Bad_Opcode }, | |
ec6f095a | 5184 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5185 | }, |
5186 | ||
592a252b | 5187 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5188 | { |
592d1631 L |
5189 | { Bad_Opcode }, |
5190 | { Bad_Opcode }, | |
ec6f095a | 5191 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5192 | }, |
5193 | ||
592a252b | 5194 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5195 | { |
592d1631 L |
5196 | { Bad_Opcode }, |
5197 | { Bad_Opcode }, | |
592a252b | 5198 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5199 | }, |
5200 | ||
592a252b | 5201 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5202 | { |
592d1631 L |
5203 | { Bad_Opcode }, |
5204 | { Bad_Opcode }, | |
592a252b | 5205 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5206 | }, |
5207 | ||
592a252b | 5208 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5209 | { |
592d1631 L |
5210 | { Bad_Opcode }, |
5211 | { Bad_Opcode }, | |
ec6f095a | 5212 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5213 | }, |
5214 | ||
592a252b | 5215 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5216 | { |
592d1631 L |
5217 | { Bad_Opcode }, |
5218 | { Bad_Opcode }, | |
ec6f095a | 5219 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5220 | }, |
5221 | ||
592a252b | 5222 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5223 | { |
592d1631 L |
5224 | { Bad_Opcode }, |
5225 | { Bad_Opcode }, | |
ec6f095a | 5226 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5227 | }, |
5228 | ||
592a252b | 5229 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5230 | { |
592d1631 L |
5231 | { Bad_Opcode }, |
5232 | { Bad_Opcode }, | |
ec6f095a | 5233 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5234 | }, |
5235 | ||
592a252b | 5236 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5237 | { |
592d1631 L |
5238 | { Bad_Opcode }, |
5239 | { Bad_Opcode }, | |
ec6f095a | 5240 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5241 | }, |
5242 | ||
592a252b | 5243 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5244 | { |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
ec6f095a | 5247 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5248 | }, |
5249 | ||
592a252b | 5250 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5251 | { |
592d1631 L |
5252 | { Bad_Opcode }, |
5253 | { Bad_Opcode }, | |
ec6f095a | 5254 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5255 | }, |
5256 | ||
592a252b | 5257 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5258 | { |
592d1631 L |
5259 | { Bad_Opcode }, |
5260 | { Bad_Opcode }, | |
ec6f095a | 5261 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5262 | }, |
5263 | ||
592a252b | 5264 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5265 | { |
592d1631 L |
5266 | { Bad_Opcode }, |
5267 | { Bad_Opcode }, | |
ec6f095a | 5268 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5269 | }, |
5270 | ||
592a252b | 5271 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5272 | { |
592d1631 L |
5273 | { Bad_Opcode }, |
5274 | { Bad_Opcode }, | |
ec6f095a | 5275 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5276 | }, |
5277 | ||
592a252b | 5278 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5279 | { |
592d1631 L |
5280 | { Bad_Opcode }, |
5281 | { Bad_Opcode }, | |
ec6f095a | 5282 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5283 | }, |
5284 | ||
592a252b | 5285 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5286 | { |
592d1631 L |
5287 | { Bad_Opcode }, |
5288 | { Bad_Opcode }, | |
ec6f095a | 5289 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5290 | }, |
5291 | ||
592a252b | 5292 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5293 | { |
592d1631 L |
5294 | { Bad_Opcode }, |
5295 | { Bad_Opcode }, | |
ec6f095a | 5296 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5297 | }, |
5298 | ||
592a252b | 5299 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5300 | { |
592d1631 L |
5301 | { Bad_Opcode }, |
5302 | { Bad_Opcode }, | |
ec6f095a | 5303 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5304 | }, |
5305 | ||
592a252b | 5306 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5307 | { |
592d1631 | 5308 | { Bad_Opcode }, |
ec6f095a L |
5309 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5310 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5311 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5312 | }, |
5313 | ||
592a252b | 5314 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5315 | { |
592d1631 L |
5316 | { Bad_Opcode }, |
5317 | { Bad_Opcode }, | |
592a252b | 5318 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5319 | }, |
5320 | ||
592a252b | 5321 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5322 | { |
592d1631 L |
5323 | { Bad_Opcode }, |
5324 | { Bad_Opcode }, | |
ec6f095a | 5325 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5326 | }, |
5327 | ||
592a252b | 5328 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5329 | { |
592d1631 L |
5330 | { Bad_Opcode }, |
5331 | { Bad_Opcode }, | |
ec6f095a | 5332 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5333 | }, |
5334 | ||
592a252b | 5335 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5336 | { |
592d1631 L |
5337 | { Bad_Opcode }, |
5338 | { Bad_Opcode }, | |
ec6f095a | 5339 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5340 | }, |
5341 | ||
592a252b | 5342 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5343 | { |
592d1631 L |
5344 | { Bad_Opcode }, |
5345 | { Bad_Opcode }, | |
ec6f095a | 5346 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5347 | }, |
5348 | ||
592a252b | 5349 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5350 | { |
592d1631 L |
5351 | { Bad_Opcode }, |
5352 | { Bad_Opcode }, | |
ec6f095a | 5353 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5354 | }, |
5355 | ||
592a252b | 5356 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5357 | { |
592d1631 L |
5358 | { Bad_Opcode }, |
5359 | { Bad_Opcode }, | |
ec6f095a | 5360 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5361 | }, |
5362 | ||
592a252b | 5363 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5364 | { |
592d1631 L |
5365 | { Bad_Opcode }, |
5366 | { Bad_Opcode }, | |
ec6f095a | 5367 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5368 | }, |
5369 | ||
592a252b | 5370 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5371 | { |
592d1631 L |
5372 | { Bad_Opcode }, |
5373 | { Bad_Opcode }, | |
ec6f095a | 5374 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5375 | }, |
5376 | ||
592a252b | 5377 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5378 | { |
592d1631 L |
5379 | { Bad_Opcode }, |
5380 | { Bad_Opcode }, | |
5381 | { Bad_Opcode }, | |
592a252b | 5382 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5383 | }, |
5384 | ||
592a252b | 5385 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5386 | { |
592d1631 L |
5387 | { Bad_Opcode }, |
5388 | { Bad_Opcode }, | |
ec6f095a | 5389 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5390 | }, |
5391 | ||
592a252b | 5392 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5393 | { |
592d1631 L |
5394 | { Bad_Opcode }, |
5395 | { Bad_Opcode }, | |
ec6f095a | 5396 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5397 | }, |
5398 | ||
592a252b | 5399 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5400 | { |
592d1631 L |
5401 | { Bad_Opcode }, |
5402 | { Bad_Opcode }, | |
ec6f095a | 5403 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5404 | }, |
5405 | ||
592a252b | 5406 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5407 | { |
592d1631 L |
5408 | { Bad_Opcode }, |
5409 | { Bad_Opcode }, | |
ec6f095a | 5410 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5411 | }, |
5412 | ||
592a252b | 5413 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5414 | { |
592d1631 L |
5415 | { Bad_Opcode }, |
5416 | { Bad_Opcode }, | |
ec6f095a | 5417 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5418 | }, |
5419 | ||
592a252b | 5420 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5421 | { |
592d1631 L |
5422 | { Bad_Opcode }, |
5423 | { Bad_Opcode }, | |
ec6f095a | 5424 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5425 | }, |
5426 | ||
592a252b | 5427 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5428 | { |
592d1631 L |
5429 | { Bad_Opcode }, |
5430 | { Bad_Opcode }, | |
592a252b | 5431 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5432 | }, |
5433 | ||
592a252b | 5434 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5435 | { |
592d1631 L |
5436 | { Bad_Opcode }, |
5437 | { Bad_Opcode }, | |
ec6f095a | 5438 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5439 | }, |
5440 | ||
592a252b | 5441 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5442 | { |
592d1631 L |
5443 | { Bad_Opcode }, |
5444 | { Bad_Opcode }, | |
ec6f095a | 5445 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5446 | }, |
5447 | ||
592a252b | 5448 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5449 | { |
592d1631 L |
5450 | { Bad_Opcode }, |
5451 | { Bad_Opcode }, | |
ec6f095a | 5452 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5453 | }, |
5454 | ||
592a252b | 5455 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5456 | { |
592d1631 L |
5457 | { Bad_Opcode }, |
5458 | { Bad_Opcode }, | |
ec6f095a | 5459 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5460 | }, |
5461 | ||
592a252b | 5462 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5463 | { |
592d1631 L |
5464 | { Bad_Opcode }, |
5465 | { Bad_Opcode }, | |
ec6f095a | 5466 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5467 | }, |
5468 | ||
592a252b | 5469 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5470 | { |
592d1631 L |
5471 | { Bad_Opcode }, |
5472 | { Bad_Opcode }, | |
ec6f095a | 5473 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5474 | }, |
5475 | ||
592a252b | 5476 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5477 | { |
592d1631 L |
5478 | { Bad_Opcode }, |
5479 | { Bad_Opcode }, | |
ec6f095a | 5480 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5481 | }, |
5482 | ||
592a252b | 5483 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5484 | { |
592d1631 L |
5485 | { Bad_Opcode }, |
5486 | { Bad_Opcode }, | |
ec6f095a | 5487 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5488 | }, |
5489 | ||
592a252b | 5490 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5491 | { |
592d1631 L |
5492 | { Bad_Opcode }, |
5493 | { Bad_Opcode }, | |
ec6f095a | 5494 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5495 | }, |
5496 | ||
592a252b | 5497 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5498 | { |
592d1631 L |
5499 | { Bad_Opcode }, |
5500 | { Bad_Opcode }, | |
ec6f095a | 5501 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5502 | }, |
5503 | ||
592a252b | 5504 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5505 | { |
592d1631 L |
5506 | { Bad_Opcode }, |
5507 | { Bad_Opcode }, | |
ec6f095a | 5508 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5509 | }, |
5510 | ||
592a252b | 5511 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5512 | { |
592d1631 L |
5513 | { Bad_Opcode }, |
5514 | { Bad_Opcode }, | |
ec6f095a | 5515 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5516 | }, |
5517 | ||
592a252b | 5518 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5519 | { |
592d1631 L |
5520 | { Bad_Opcode }, |
5521 | { Bad_Opcode }, | |
ec6f095a | 5522 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5523 | }, |
5524 | ||
592a252b | 5525 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5526 | { |
592d1631 L |
5527 | { Bad_Opcode }, |
5528 | { Bad_Opcode }, | |
ec6f095a | 5529 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5530 | }, |
5531 | ||
592a252b | 5532 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5533 | { |
592d1631 L |
5534 | { Bad_Opcode }, |
5535 | { Bad_Opcode }, | |
ec6f095a | 5536 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5537 | }, |
5538 | ||
592a252b | 5539 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5540 | { |
592d1631 L |
5541 | { Bad_Opcode }, |
5542 | { Bad_Opcode }, | |
ec6f095a | 5543 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5544 | }, |
5545 | ||
592a252b | 5546 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5547 | { |
592d1631 L |
5548 | { Bad_Opcode }, |
5549 | { Bad_Opcode }, | |
ec6f095a | 5550 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5551 | }, |
5552 | ||
592a252b | 5553 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5554 | { |
592d1631 L |
5555 | { Bad_Opcode }, |
5556 | { Bad_Opcode }, | |
ec6f095a | 5557 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5558 | }, |
5559 | ||
592a252b | 5560 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5561 | { |
592d1631 L |
5562 | { Bad_Opcode }, |
5563 | { Bad_Opcode }, | |
ec6f095a | 5564 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5565 | }, |
5566 | ||
592a252b | 5567 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5568 | { |
592d1631 L |
5569 | { Bad_Opcode }, |
5570 | { Bad_Opcode }, | |
592a252b | 5571 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5572 | }, |
5573 | ||
592a252b | 5574 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5575 | { |
592d1631 L |
5576 | { Bad_Opcode }, |
5577 | { Bad_Opcode }, | |
592a252b | 5578 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5579 | }, |
5580 | ||
592a252b | 5581 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5582 | { |
592d1631 L |
5583 | { Bad_Opcode }, |
5584 | { Bad_Opcode }, | |
592a252b | 5585 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5586 | }, |
5587 | ||
592a252b | 5588 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5589 | { |
592d1631 L |
5590 | { Bad_Opcode }, |
5591 | { Bad_Opcode }, | |
592a252b | 5592 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5593 | }, |
5594 | ||
592a252b | 5595 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5596 | { |
5597 | { Bad_Opcode }, | |
5598 | { Bad_Opcode }, | |
bf890a93 | 5599 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5600 | }, |
5601 | ||
6c30d220 L |
5602 | /* PREFIX_VEX_0F3816 */ |
5603 | { | |
5604 | { Bad_Opcode }, | |
5605 | { Bad_Opcode }, | |
5606 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5607 | }, | |
5608 | ||
592a252b | 5609 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5610 | { |
592d1631 L |
5611 | { Bad_Opcode }, |
5612 | { Bad_Opcode }, | |
ec6f095a | 5613 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5614 | }, |
5615 | ||
592a252b | 5616 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5617 | { |
592d1631 L |
5618 | { Bad_Opcode }, |
5619 | { Bad_Opcode }, | |
6c30d220 | 5620 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5621 | }, |
5622 | ||
592a252b | 5623 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5624 | { |
592d1631 L |
5625 | { Bad_Opcode }, |
5626 | { Bad_Opcode }, | |
6c30d220 | 5627 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5628 | }, |
5629 | ||
592a252b | 5630 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5631 | { |
592d1631 L |
5632 | { Bad_Opcode }, |
5633 | { Bad_Opcode }, | |
592a252b | 5634 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5635 | }, |
5636 | ||
592a252b | 5637 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5638 | { |
592d1631 L |
5639 | { Bad_Opcode }, |
5640 | { Bad_Opcode }, | |
ec6f095a | 5641 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5642 | }, |
5643 | ||
592a252b | 5644 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5645 | { |
592d1631 L |
5646 | { Bad_Opcode }, |
5647 | { Bad_Opcode }, | |
ec6f095a | 5648 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5649 | }, |
5650 | ||
592a252b | 5651 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5652 | { |
592d1631 L |
5653 | { Bad_Opcode }, |
5654 | { Bad_Opcode }, | |
ec6f095a | 5655 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5656 | }, |
5657 | ||
592a252b | 5658 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5659 | { |
592d1631 L |
5660 | { Bad_Opcode }, |
5661 | { Bad_Opcode }, | |
ec6f095a | 5662 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5663 | }, |
5664 | ||
592a252b | 5665 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5666 | { |
592d1631 L |
5667 | { Bad_Opcode }, |
5668 | { Bad_Opcode }, | |
ec6f095a | 5669 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5670 | }, |
5671 | ||
592a252b | 5672 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5673 | { |
592d1631 L |
5674 | { Bad_Opcode }, |
5675 | { Bad_Opcode }, | |
ec6f095a | 5676 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5677 | }, |
5678 | ||
592a252b | 5679 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5680 | { |
592d1631 L |
5681 | { Bad_Opcode }, |
5682 | { Bad_Opcode }, | |
ec6f095a | 5683 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5684 | }, |
5685 | ||
592a252b | 5686 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5687 | { |
592d1631 L |
5688 | { Bad_Opcode }, |
5689 | { Bad_Opcode }, | |
ec6f095a | 5690 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5691 | }, |
5692 | ||
592a252b | 5693 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5694 | { |
592d1631 L |
5695 | { Bad_Opcode }, |
5696 | { Bad_Opcode }, | |
ec6f095a | 5697 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5698 | }, |
5699 | ||
592a252b | 5700 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5701 | { |
592d1631 L |
5702 | { Bad_Opcode }, |
5703 | { Bad_Opcode }, | |
ec6f095a | 5704 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5705 | }, |
5706 | ||
592a252b | 5707 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5708 | { |
592d1631 L |
5709 | { Bad_Opcode }, |
5710 | { Bad_Opcode }, | |
ec6f095a | 5711 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5712 | }, |
5713 | ||
592a252b | 5714 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5715 | { |
592d1631 L |
5716 | { Bad_Opcode }, |
5717 | { Bad_Opcode }, | |
592a252b | 5718 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5719 | }, |
5720 | ||
592a252b | 5721 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5722 | { |
592d1631 L |
5723 | { Bad_Opcode }, |
5724 | { Bad_Opcode }, | |
ec6f095a | 5725 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5726 | }, |
5727 | ||
592a252b | 5728 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5729 | { |
592d1631 L |
5730 | { Bad_Opcode }, |
5731 | { Bad_Opcode }, | |
592a252b | 5732 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5733 | }, |
5734 | ||
592a252b | 5735 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5736 | { |
592d1631 L |
5737 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, | |
592a252b | 5739 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5740 | }, |
5741 | ||
592a252b | 5742 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5743 | { |
592d1631 L |
5744 | { Bad_Opcode }, |
5745 | { Bad_Opcode }, | |
592a252b | 5746 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5747 | }, |
5748 | ||
592a252b | 5749 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5750 | { |
592d1631 L |
5751 | { Bad_Opcode }, |
5752 | { Bad_Opcode }, | |
592a252b | 5753 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5754 | }, |
5755 | ||
592a252b | 5756 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5757 | { |
592d1631 L |
5758 | { Bad_Opcode }, |
5759 | { Bad_Opcode }, | |
ec6f095a | 5760 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5761 | }, |
5762 | ||
592a252b | 5763 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5764 | { |
592d1631 L |
5765 | { Bad_Opcode }, |
5766 | { Bad_Opcode }, | |
ec6f095a | 5767 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5768 | }, |
5769 | ||
592a252b | 5770 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5771 | { |
592d1631 L |
5772 | { Bad_Opcode }, |
5773 | { Bad_Opcode }, | |
ec6f095a | 5774 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5775 | }, |
5776 | ||
592a252b | 5777 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5778 | { |
592d1631 L |
5779 | { Bad_Opcode }, |
5780 | { Bad_Opcode }, | |
ec6f095a | 5781 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5782 | }, |
5783 | ||
592a252b | 5784 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5785 | { |
592d1631 L |
5786 | { Bad_Opcode }, |
5787 | { Bad_Opcode }, | |
ec6f095a | 5788 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5789 | }, |
5790 | ||
592a252b | 5791 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5792 | { |
592d1631 L |
5793 | { Bad_Opcode }, |
5794 | { Bad_Opcode }, | |
ec6f095a | 5795 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5796 | }, |
5797 | ||
5798 | /* PREFIX_VEX_0F3836 */ | |
5799 | { | |
5800 | { Bad_Opcode }, | |
5801 | { Bad_Opcode }, | |
5802 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5803 | }, |
5804 | ||
592a252b | 5805 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5806 | { |
592d1631 L |
5807 | { Bad_Opcode }, |
5808 | { Bad_Opcode }, | |
ec6f095a | 5809 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5810 | }, |
5811 | ||
592a252b | 5812 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5813 | { |
592d1631 L |
5814 | { Bad_Opcode }, |
5815 | { Bad_Opcode }, | |
ec6f095a | 5816 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5817 | }, |
5818 | ||
592a252b | 5819 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5820 | { |
592d1631 L |
5821 | { Bad_Opcode }, |
5822 | { Bad_Opcode }, | |
ec6f095a | 5823 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5824 | }, |
5825 | ||
592a252b | 5826 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5827 | { |
592d1631 L |
5828 | { Bad_Opcode }, |
5829 | { Bad_Opcode }, | |
ec6f095a | 5830 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5831 | }, |
5832 | ||
592a252b | 5833 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5834 | { |
592d1631 L |
5835 | { Bad_Opcode }, |
5836 | { Bad_Opcode }, | |
ec6f095a | 5837 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5838 | }, |
5839 | ||
592a252b | 5840 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5841 | { |
592d1631 L |
5842 | { Bad_Opcode }, |
5843 | { Bad_Opcode }, | |
ec6f095a | 5844 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5845 | }, |
5846 | ||
592a252b | 5847 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5848 | { |
592d1631 L |
5849 | { Bad_Opcode }, |
5850 | { Bad_Opcode }, | |
ec6f095a | 5851 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5852 | }, |
5853 | ||
592a252b | 5854 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5855 | { |
592d1631 L |
5856 | { Bad_Opcode }, |
5857 | { Bad_Opcode }, | |
ec6f095a | 5858 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5859 | }, |
5860 | ||
592a252b | 5861 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5862 | { |
592d1631 L |
5863 | { Bad_Opcode }, |
5864 | { Bad_Opcode }, | |
ec6f095a | 5865 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5866 | }, |
5867 | ||
592a252b | 5868 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5869 | { |
592d1631 L |
5870 | { Bad_Opcode }, |
5871 | { Bad_Opcode }, | |
ec6f095a | 5872 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5873 | }, |
5874 | ||
592a252b | 5875 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5876 | { |
592d1631 L |
5877 | { Bad_Opcode }, |
5878 | { Bad_Opcode }, | |
592a252b | 5879 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5880 | }, |
5881 | ||
6c30d220 L |
5882 | /* PREFIX_VEX_0F3845 */ |
5883 | { | |
5884 | { Bad_Opcode }, | |
5885 | { Bad_Opcode }, | |
bf890a93 | 5886 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5887 | }, |
5888 | ||
5889 | /* PREFIX_VEX_0F3846 */ | |
5890 | { | |
5891 | { Bad_Opcode }, | |
5892 | { Bad_Opcode }, | |
5893 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5894 | }, | |
5895 | ||
5896 | /* PREFIX_VEX_0F3847 */ | |
5897 | { | |
5898 | { Bad_Opcode }, | |
5899 | { Bad_Opcode }, | |
bf890a93 | 5900 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5901 | }, |
5902 | ||
5903 | /* PREFIX_VEX_0F3858 */ | |
5904 | { | |
5905 | { Bad_Opcode }, | |
5906 | { Bad_Opcode }, | |
5907 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5908 | }, | |
5909 | ||
5910 | /* PREFIX_VEX_0F3859 */ | |
5911 | { | |
5912 | { Bad_Opcode }, | |
5913 | { Bad_Opcode }, | |
5914 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5915 | }, | |
5916 | ||
5917 | /* PREFIX_VEX_0F385A */ | |
5918 | { | |
5919 | { Bad_Opcode }, | |
5920 | { Bad_Opcode }, | |
5921 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5922 | }, | |
5923 | ||
5924 | /* PREFIX_VEX_0F3878 */ | |
5925 | { | |
5926 | { Bad_Opcode }, | |
5927 | { Bad_Opcode }, | |
5928 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5929 | }, | |
5930 | ||
5931 | /* PREFIX_VEX_0F3879 */ | |
5932 | { | |
5933 | { Bad_Opcode }, | |
5934 | { Bad_Opcode }, | |
5935 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5936 | }, | |
5937 | ||
5938 | /* PREFIX_VEX_0F388C */ | |
5939 | { | |
5940 | { Bad_Opcode }, | |
5941 | { Bad_Opcode }, | |
f7002f42 | 5942 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5943 | }, |
5944 | ||
5945 | /* PREFIX_VEX_0F388E */ | |
5946 | { | |
5947 | { Bad_Opcode }, | |
5948 | { Bad_Opcode }, | |
f7002f42 | 5949 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5950 | }, |
5951 | ||
5952 | /* PREFIX_VEX_0F3890 */ | |
5953 | { | |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
bf890a93 | 5956 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5957 | }, |
5958 | ||
5959 | /* PREFIX_VEX_0F3891 */ | |
5960 | { | |
5961 | { Bad_Opcode }, | |
5962 | { Bad_Opcode }, | |
bf890a93 | 5963 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5964 | }, |
5965 | ||
5966 | /* PREFIX_VEX_0F3892 */ | |
5967 | { | |
5968 | { Bad_Opcode }, | |
5969 | { Bad_Opcode }, | |
bf890a93 | 5970 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5971 | }, |
5972 | ||
5973 | /* PREFIX_VEX_0F3893 */ | |
5974 | { | |
5975 | { Bad_Opcode }, | |
5976 | { Bad_Opcode }, | |
bf890a93 | 5977 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5978 | }, |
5979 | ||
592a252b | 5980 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5981 | { |
592d1631 L |
5982 | { Bad_Opcode }, |
5983 | { Bad_Opcode }, | |
bf890a93 | 5984 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5985 | }, |
5986 | ||
592a252b | 5987 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5988 | { |
592d1631 L |
5989 | { Bad_Opcode }, |
5990 | { Bad_Opcode }, | |
bf890a93 | 5991 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5992 | }, |
5993 | ||
592a252b | 5994 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5995 | { |
592d1631 L |
5996 | { Bad_Opcode }, |
5997 | { Bad_Opcode }, | |
bf890a93 | 5998 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5999 | }, |
6000 | ||
592a252b | 6001 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6002 | { |
592d1631 L |
6003 | { Bad_Opcode }, |
6004 | { Bad_Opcode }, | |
bf890a93 | 6005 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6006 | }, |
6007 | ||
592a252b | 6008 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6009 | { |
592d1631 L |
6010 | { Bad_Opcode }, |
6011 | { Bad_Opcode }, | |
bf890a93 | 6012 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6013 | }, |
6014 | ||
592a252b | 6015 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6016 | { |
592d1631 L |
6017 | { Bad_Opcode }, |
6018 | { Bad_Opcode }, | |
bf890a93 | 6019 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6020 | }, |
6021 | ||
592a252b | 6022 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6023 | { |
592d1631 L |
6024 | { Bad_Opcode }, |
6025 | { Bad_Opcode }, | |
bf890a93 | 6026 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6027 | }, |
6028 | ||
592a252b | 6029 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6030 | { |
592d1631 L |
6031 | { Bad_Opcode }, |
6032 | { Bad_Opcode }, | |
bf890a93 | 6033 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6034 | }, |
6035 | ||
592a252b | 6036 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6037 | { |
592d1631 L |
6038 | { Bad_Opcode }, |
6039 | { Bad_Opcode }, | |
bf890a93 | 6040 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6041 | }, |
6042 | ||
592a252b | 6043 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6044 | { |
592d1631 L |
6045 | { Bad_Opcode }, |
6046 | { Bad_Opcode }, | |
bf890a93 | 6047 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6048 | }, |
6049 | ||
592a252b | 6050 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6051 | { |
592d1631 L |
6052 | { Bad_Opcode }, |
6053 | { Bad_Opcode }, | |
bf890a93 | 6054 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6055 | { Bad_Opcode }, |
c0f3af97 L |
6056 | }, |
6057 | ||
592a252b | 6058 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6059 | { |
592d1631 L |
6060 | { Bad_Opcode }, |
6061 | { Bad_Opcode }, | |
bf890a93 | 6062 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6063 | }, |
6064 | ||
592a252b | 6065 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6066 | { |
592d1631 L |
6067 | { Bad_Opcode }, |
6068 | { Bad_Opcode }, | |
bf890a93 | 6069 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6070 | }, |
6071 | ||
592a252b | 6072 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6073 | { |
592d1631 L |
6074 | { Bad_Opcode }, |
6075 | { Bad_Opcode }, | |
bf890a93 | 6076 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6077 | }, |
6078 | ||
592a252b | 6079 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6080 | { |
592d1631 L |
6081 | { Bad_Opcode }, |
6082 | { Bad_Opcode }, | |
bf890a93 | 6083 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6084 | }, |
6085 | ||
592a252b | 6086 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6087 | { |
592d1631 L |
6088 | { Bad_Opcode }, |
6089 | { Bad_Opcode }, | |
bf890a93 | 6090 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6091 | }, |
6092 | ||
592a252b | 6093 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6094 | { |
592d1631 L |
6095 | { Bad_Opcode }, |
6096 | { Bad_Opcode }, | |
bf890a93 | 6097 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6098 | }, |
6099 | ||
592a252b | 6100 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6101 | { |
592d1631 L |
6102 | { Bad_Opcode }, |
6103 | { Bad_Opcode }, | |
bf890a93 | 6104 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6105 | }, |
6106 | ||
592a252b | 6107 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6108 | { |
592d1631 L |
6109 | { Bad_Opcode }, |
6110 | { Bad_Opcode }, | |
bf890a93 | 6111 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6112 | }, |
6113 | ||
592a252b | 6114 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6115 | { |
592d1631 L |
6116 | { Bad_Opcode }, |
6117 | { Bad_Opcode }, | |
bf890a93 | 6118 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6119 | }, |
6120 | ||
592a252b | 6121 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6122 | { |
592d1631 L |
6123 | { Bad_Opcode }, |
6124 | { Bad_Opcode }, | |
bf890a93 | 6125 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6126 | }, |
6127 | ||
592a252b | 6128 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6129 | { |
592d1631 L |
6130 | { Bad_Opcode }, |
6131 | { Bad_Opcode }, | |
bf890a93 | 6132 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6133 | }, |
6134 | ||
592a252b | 6135 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6136 | { |
592d1631 L |
6137 | { Bad_Opcode }, |
6138 | { Bad_Opcode }, | |
bf890a93 | 6139 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6140 | }, |
6141 | ||
592a252b | 6142 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6143 | { |
592d1631 L |
6144 | { Bad_Opcode }, |
6145 | { Bad_Opcode }, | |
bf890a93 | 6146 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6147 | }, |
6148 | ||
592a252b | 6149 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6150 | { |
592d1631 L |
6151 | { Bad_Opcode }, |
6152 | { Bad_Opcode }, | |
bf890a93 | 6153 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6154 | }, |
6155 | ||
592a252b | 6156 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6157 | { |
592d1631 L |
6158 | { Bad_Opcode }, |
6159 | { Bad_Opcode }, | |
bf890a93 | 6160 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6161 | }, |
6162 | ||
592a252b | 6163 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6164 | { |
592d1631 L |
6165 | { Bad_Opcode }, |
6166 | { Bad_Opcode }, | |
bf890a93 | 6167 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6168 | }, |
6169 | ||
592a252b | 6170 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6171 | { |
592d1631 L |
6172 | { Bad_Opcode }, |
6173 | { Bad_Opcode }, | |
bf890a93 | 6174 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6175 | }, |
6176 | ||
592a252b | 6177 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6178 | { |
592d1631 L |
6179 | { Bad_Opcode }, |
6180 | { Bad_Opcode }, | |
bf890a93 | 6181 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6182 | }, |
6183 | ||
592a252b | 6184 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6185 | { |
592d1631 L |
6186 | { Bad_Opcode }, |
6187 | { Bad_Opcode }, | |
bf890a93 | 6188 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6189 | }, |
6190 | ||
48521003 IT |
6191 | /* PREFIX_VEX_0F38CF */ |
6192 | { | |
6193 | { Bad_Opcode }, | |
6194 | { Bad_Opcode }, | |
6195 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6196 | }, | |
6197 | ||
592a252b | 6198 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6199 | { |
592d1631 L |
6200 | { Bad_Opcode }, |
6201 | { Bad_Opcode }, | |
592a252b | 6202 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6203 | }, |
6204 | ||
592a252b | 6205 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6206 | { |
592d1631 L |
6207 | { Bad_Opcode }, |
6208 | { Bad_Opcode }, | |
8dcf1fad | 6209 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6210 | }, |
6211 | ||
592a252b | 6212 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6213 | { |
592d1631 L |
6214 | { Bad_Opcode }, |
6215 | { Bad_Opcode }, | |
8dcf1fad | 6216 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6217 | }, |
6218 | ||
592a252b | 6219 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6220 | { |
592d1631 L |
6221 | { Bad_Opcode }, |
6222 | { Bad_Opcode }, | |
8dcf1fad | 6223 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6224 | }, |
6225 | ||
592a252b | 6226 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6227 | { |
592d1631 L |
6228 | { Bad_Opcode }, |
6229 | { Bad_Opcode }, | |
8dcf1fad | 6230 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6231 | }, |
6232 | ||
f12dc422 L |
6233 | /* PREFIX_VEX_0F38F2 */ |
6234 | { | |
6235 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6236 | }, | |
6237 | ||
6238 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6239 | { | |
6240 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6241 | }, | |
6242 | ||
6243 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6244 | { | |
6245 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6246 | }, | |
6247 | ||
6248 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6249 | { | |
6250 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6251 | }, | |
6252 | ||
6c30d220 L |
6253 | /* PREFIX_VEX_0F38F5 */ |
6254 | { | |
6255 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6256 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6257 | { Bad_Opcode }, | |
6258 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6259 | }, | |
6260 | ||
6261 | /* PREFIX_VEX_0F38F6 */ | |
6262 | { | |
6263 | { Bad_Opcode }, | |
6264 | { Bad_Opcode }, | |
6265 | { Bad_Opcode }, | |
6266 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6267 | }, | |
6268 | ||
f12dc422 L |
6269 | /* PREFIX_VEX_0F38F7 */ |
6270 | { | |
6271 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6272 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6273 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6274 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6275 | }, | |
6276 | ||
6277 | /* PREFIX_VEX_0F3A00 */ | |
6278 | { | |
6279 | { Bad_Opcode }, | |
6280 | { Bad_Opcode }, | |
6281 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6282 | }, | |
6283 | ||
6284 | /* PREFIX_VEX_0F3A01 */ | |
6285 | { | |
6286 | { Bad_Opcode }, | |
6287 | { Bad_Opcode }, | |
6288 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6289 | }, | |
6290 | ||
6291 | /* PREFIX_VEX_0F3A02 */ | |
6292 | { | |
6293 | { Bad_Opcode }, | |
6294 | { Bad_Opcode }, | |
6295 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6296 | }, |
6297 | ||
592a252b | 6298 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6299 | { |
592d1631 L |
6300 | { Bad_Opcode }, |
6301 | { Bad_Opcode }, | |
592a252b | 6302 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6303 | }, |
6304 | ||
592a252b | 6305 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6306 | { |
592d1631 L |
6307 | { Bad_Opcode }, |
6308 | { Bad_Opcode }, | |
592a252b | 6309 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6310 | }, |
6311 | ||
592a252b | 6312 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6313 | { |
592d1631 L |
6314 | { Bad_Opcode }, |
6315 | { Bad_Opcode }, | |
592a252b | 6316 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6317 | }, |
6318 | ||
592a252b | 6319 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6320 | { |
592d1631 L |
6321 | { Bad_Opcode }, |
6322 | { Bad_Opcode }, | |
ec6f095a | 6323 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6324 | }, |
6325 | ||
592a252b | 6326 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6327 | { |
592d1631 L |
6328 | { Bad_Opcode }, |
6329 | { Bad_Opcode }, | |
ec6f095a | 6330 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6331 | }, |
6332 | ||
592a252b | 6333 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6334 | { |
592d1631 L |
6335 | { Bad_Opcode }, |
6336 | { Bad_Opcode }, | |
ec6f095a | 6337 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
0bfee649 L |
6338 | }, |
6339 | ||
592a252b | 6340 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6341 | { |
592d1631 L |
6342 | { Bad_Opcode }, |
6343 | { Bad_Opcode }, | |
ec6f095a | 6344 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
0bfee649 L |
6345 | }, |
6346 | ||
592a252b | 6347 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6348 | { |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
ec6f095a | 6351 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6352 | }, |
6353 | ||
592a252b | 6354 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6355 | { |
592d1631 L |
6356 | { Bad_Opcode }, |
6357 | { Bad_Opcode }, | |
ec6f095a | 6358 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6359 | }, |
6360 | ||
592a252b | 6361 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6362 | { |
592d1631 L |
6363 | { Bad_Opcode }, |
6364 | { Bad_Opcode }, | |
ec6f095a | 6365 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6366 | }, |
6367 | ||
592a252b | 6368 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6369 | { |
592d1631 L |
6370 | { Bad_Opcode }, |
6371 | { Bad_Opcode }, | |
ec6f095a | 6372 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6373 | }, |
6374 | ||
592a252b | 6375 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6376 | { |
592d1631 L |
6377 | { Bad_Opcode }, |
6378 | { Bad_Opcode }, | |
592a252b | 6379 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6380 | }, |
6381 | ||
592a252b | 6382 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6383 | { |
592d1631 L |
6384 | { Bad_Opcode }, |
6385 | { Bad_Opcode }, | |
592a252b | 6386 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6387 | }, |
6388 | ||
592a252b | 6389 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6390 | { |
592d1631 L |
6391 | { Bad_Opcode }, |
6392 | { Bad_Opcode }, | |
592a252b | 6393 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6394 | }, |
6395 | ||
592a252b | 6396 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6397 | { |
592d1631 L |
6398 | { Bad_Opcode }, |
6399 | { Bad_Opcode }, | |
592a252b | 6400 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6401 | }, |
6402 | ||
592a252b | 6403 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6404 | { |
592d1631 L |
6405 | { Bad_Opcode }, |
6406 | { Bad_Opcode }, | |
592a252b | 6407 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6408 | }, |
6409 | ||
592a252b | 6410 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6411 | { |
592d1631 L |
6412 | { Bad_Opcode }, |
6413 | { Bad_Opcode }, | |
592a252b | 6414 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6415 | }, |
6416 | ||
592a252b | 6417 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6418 | { |
6419 | { Bad_Opcode }, | |
6420 | { Bad_Opcode }, | |
bf890a93 | 6421 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6422 | }, |
6423 | ||
592a252b | 6424 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6425 | { |
592d1631 L |
6426 | { Bad_Opcode }, |
6427 | { Bad_Opcode }, | |
592a252b | 6428 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6429 | }, |
6430 | ||
592a252b | 6431 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6432 | { |
592d1631 L |
6433 | { Bad_Opcode }, |
6434 | { Bad_Opcode }, | |
592a252b | 6435 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6436 | }, |
6437 | ||
592a252b | 6438 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6439 | { |
592d1631 L |
6440 | { Bad_Opcode }, |
6441 | { Bad_Opcode }, | |
592a252b | 6442 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6443 | }, |
6444 | ||
43234a1e L |
6445 | /* PREFIX_VEX_0F3A30 */ |
6446 | { | |
6447 | { Bad_Opcode }, | |
6448 | { Bad_Opcode }, | |
6449 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6450 | }, | |
6451 | ||
1ba585e8 IT |
6452 | /* PREFIX_VEX_0F3A31 */ |
6453 | { | |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6457 | }, | |
6458 | ||
43234a1e L |
6459 | /* PREFIX_VEX_0F3A32 */ |
6460 | { | |
6461 | { Bad_Opcode }, | |
6462 | { Bad_Opcode }, | |
6463 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6464 | }, | |
6465 | ||
1ba585e8 IT |
6466 | /* PREFIX_VEX_0F3A33 */ |
6467 | { | |
6468 | { Bad_Opcode }, | |
6469 | { Bad_Opcode }, | |
6470 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6471 | }, | |
6472 | ||
6c30d220 L |
6473 | /* PREFIX_VEX_0F3A38 */ |
6474 | { | |
6475 | { Bad_Opcode }, | |
6476 | { Bad_Opcode }, | |
6477 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6478 | }, | |
6479 | ||
6480 | /* PREFIX_VEX_0F3A39 */ | |
6481 | { | |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6484 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6485 | }, | |
6486 | ||
592a252b | 6487 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6488 | { |
592d1631 L |
6489 | { Bad_Opcode }, |
6490 | { Bad_Opcode }, | |
ec6f095a | 6491 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6492 | }, |
6493 | ||
592a252b | 6494 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6495 | { |
592d1631 L |
6496 | { Bad_Opcode }, |
6497 | { Bad_Opcode }, | |
592a252b | 6498 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6499 | }, |
6500 | ||
592a252b | 6501 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6502 | { |
592d1631 L |
6503 | { Bad_Opcode }, |
6504 | { Bad_Opcode }, | |
ec6f095a | 6505 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6506 | }, |
6507 | ||
592a252b | 6508 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6509 | { |
592d1631 L |
6510 | { Bad_Opcode }, |
6511 | { Bad_Opcode }, | |
ff1982d5 | 6512 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6513 | }, |
6514 | ||
6c30d220 L |
6515 | /* PREFIX_VEX_0F3A46 */ |
6516 | { | |
6517 | { Bad_Opcode }, | |
6518 | { Bad_Opcode }, | |
6519 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6520 | }, | |
6521 | ||
592a252b | 6522 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6523 | { |
6524 | { Bad_Opcode }, | |
6525 | { Bad_Opcode }, | |
592a252b | 6526 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6527 | }, |
6528 | ||
592a252b | 6529 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6530 | { |
6531 | { Bad_Opcode }, | |
6532 | { Bad_Opcode }, | |
592a252b | 6533 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6534 | }, |
6535 | ||
592a252b | 6536 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6537 | { |
592d1631 L |
6538 | { Bad_Opcode }, |
6539 | { Bad_Opcode }, | |
592a252b | 6540 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6541 | }, |
6542 | ||
592a252b | 6543 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6544 | { |
592d1631 L |
6545 | { Bad_Opcode }, |
6546 | { Bad_Opcode }, | |
592a252b | 6547 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6548 | }, |
6549 | ||
592a252b | 6550 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6551 | { |
592d1631 L |
6552 | { Bad_Opcode }, |
6553 | { Bad_Opcode }, | |
6c30d220 | 6554 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6555 | }, |
6556 | ||
592a252b | 6557 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6558 | { |
592d1631 L |
6559 | { Bad_Opcode }, |
6560 | { Bad_Opcode }, | |
3a2430e0 | 6561 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6562 | }, |
6563 | ||
592a252b | 6564 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6565 | { |
592d1631 L |
6566 | { Bad_Opcode }, |
6567 | { Bad_Opcode }, | |
3a2430e0 | 6568 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6569 | }, |
6570 | ||
592a252b | 6571 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6572 | { |
592d1631 L |
6573 | { Bad_Opcode }, |
6574 | { Bad_Opcode }, | |
3a2430e0 | 6575 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6576 | }, |
6577 | ||
592a252b | 6578 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6579 | { |
592d1631 L |
6580 | { Bad_Opcode }, |
6581 | { Bad_Opcode }, | |
3a2430e0 | 6582 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6583 | }, |
6584 | ||
592a252b | 6585 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6586 | { |
592d1631 L |
6587 | { Bad_Opcode }, |
6588 | { Bad_Opcode }, | |
592a252b | 6589 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6590 | { Bad_Opcode }, |
c0f3af97 L |
6591 | }, |
6592 | ||
592a252b | 6593 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6594 | { |
592d1631 L |
6595 | { Bad_Opcode }, |
6596 | { Bad_Opcode }, | |
592a252b | 6597 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6598 | }, |
6599 | ||
592a252b | 6600 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6601 | { |
592d1631 L |
6602 | { Bad_Opcode }, |
6603 | { Bad_Opcode }, | |
592a252b | 6604 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6605 | }, |
6606 | ||
592a252b | 6607 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6608 | { |
592d1631 L |
6609 | { Bad_Opcode }, |
6610 | { Bad_Opcode }, | |
592a252b | 6611 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6612 | }, |
a5ff0eb2 | 6613 | |
592a252b | 6614 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6615 | { |
592d1631 L |
6616 | { Bad_Opcode }, |
6617 | { Bad_Opcode }, | |
3a2430e0 | 6618 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6619 | }, |
6620 | ||
592a252b | 6621 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6622 | { |
592d1631 L |
6623 | { Bad_Opcode }, |
6624 | { Bad_Opcode }, | |
3a2430e0 | 6625 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6626 | }, |
6627 | ||
592a252b | 6628 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6629 | { |
592d1631 L |
6630 | { Bad_Opcode }, |
6631 | { Bad_Opcode }, | |
592a252b | 6632 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6633 | }, |
6634 | ||
592a252b | 6635 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6636 | { |
592d1631 L |
6637 | { Bad_Opcode }, |
6638 | { Bad_Opcode }, | |
592a252b | 6639 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6640 | }, |
6641 | ||
592a252b | 6642 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6643 | { |
592d1631 L |
6644 | { Bad_Opcode }, |
6645 | { Bad_Opcode }, | |
3a2430e0 | 6646 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6647 | }, |
6648 | ||
592a252b | 6649 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6650 | { |
592d1631 L |
6651 | { Bad_Opcode }, |
6652 | { Bad_Opcode }, | |
3a2430e0 | 6653 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6654 | }, |
6655 | ||
592a252b | 6656 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6657 | { |
592d1631 L |
6658 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, | |
592a252b | 6660 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6661 | }, |
6662 | ||
592a252b | 6663 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6664 | { |
592d1631 L |
6665 | { Bad_Opcode }, |
6666 | { Bad_Opcode }, | |
592a252b | 6667 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6668 | }, |
6669 | ||
592a252b | 6670 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6671 | { |
592d1631 L |
6672 | { Bad_Opcode }, |
6673 | { Bad_Opcode }, | |
3a2430e0 | 6674 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6675 | }, |
6676 | ||
592a252b | 6677 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6678 | { |
592d1631 L |
6679 | { Bad_Opcode }, |
6680 | { Bad_Opcode }, | |
3a2430e0 | 6681 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6682 | }, |
6683 | ||
592a252b | 6684 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6685 | { |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
592a252b | 6688 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6689 | }, |
6690 | ||
592a252b | 6691 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6692 | { |
592d1631 L |
6693 | { Bad_Opcode }, |
6694 | { Bad_Opcode }, | |
592a252b | 6695 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6696 | }, |
6697 | ||
592a252b | 6698 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6699 | { |
592d1631 L |
6700 | { Bad_Opcode }, |
6701 | { Bad_Opcode }, | |
3a2430e0 | 6702 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6703 | { Bad_Opcode }, |
922d8de8 DR |
6704 | }, |
6705 | ||
592a252b | 6706 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6707 | { |
592d1631 L |
6708 | { Bad_Opcode }, |
6709 | { Bad_Opcode }, | |
3a2430e0 | 6710 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6711 | }, |
6712 | ||
592a252b | 6713 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6714 | { |
592d1631 L |
6715 | { Bad_Opcode }, |
6716 | { Bad_Opcode }, | |
592a252b | 6717 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6718 | }, |
6719 | ||
592a252b | 6720 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6721 | { |
592d1631 L |
6722 | { Bad_Opcode }, |
6723 | { Bad_Opcode }, | |
592a252b | 6724 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6725 | }, |
6726 | ||
48521003 IT |
6727 | /* PREFIX_VEX_0F3ACE */ |
6728 | { | |
6729 | { Bad_Opcode }, | |
6730 | { Bad_Opcode }, | |
6731 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6732 | }, | |
6733 | ||
6734 | /* PREFIX_VEX_0F3ACF */ | |
6735 | { | |
6736 | { Bad_Opcode }, | |
6737 | { Bad_Opcode }, | |
6738 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6739 | }, | |
6740 | ||
592a252b | 6741 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6742 | { |
592d1631 L |
6743 | { Bad_Opcode }, |
6744 | { Bad_Opcode }, | |
592a252b | 6745 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6746 | }, |
6c30d220 L |
6747 | |
6748 | /* PREFIX_VEX_0F3AF0 */ | |
6749 | { | |
6750 | { Bad_Opcode }, | |
6751 | { Bad_Opcode }, | |
6752 | { Bad_Opcode }, | |
6753 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6754 | }, | |
43234a1e | 6755 | |
ad692897 | 6756 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6757 | }; |
6758 | ||
6759 | static const struct dis386 x86_64_table[][2] = { | |
6760 | /* X86_64_06 */ | |
6761 | { | |
bf890a93 | 6762 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6763 | }, |
6764 | ||
6765 | /* X86_64_07 */ | |
6766 | { | |
bf890a93 | 6767 | { "popP", { es }, 0 }, |
c0f3af97 L |
6768 | }, |
6769 | ||
1673df32 | 6770 | /* X86_64_0E */ |
c0f3af97 | 6771 | { |
bf890a93 | 6772 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6773 | }, |
6774 | ||
6775 | /* X86_64_16 */ | |
6776 | { | |
bf890a93 | 6777 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6778 | }, |
6779 | ||
6780 | /* X86_64_17 */ | |
6781 | { | |
bf890a93 | 6782 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6783 | }, |
6784 | ||
6785 | /* X86_64_1E */ | |
6786 | { | |
bf890a93 | 6787 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6788 | }, |
6789 | ||
6790 | /* X86_64_1F */ | |
6791 | { | |
bf890a93 | 6792 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6793 | }, |
6794 | ||
6795 | /* X86_64_27 */ | |
6796 | { | |
bf890a93 | 6797 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6798 | }, |
6799 | ||
6800 | /* X86_64_2F */ | |
6801 | { | |
bf890a93 | 6802 | { "das", { XX }, 0 }, |
c0f3af97 L |
6803 | }, |
6804 | ||
6805 | /* X86_64_37 */ | |
6806 | { | |
bf890a93 | 6807 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6808 | }, |
6809 | ||
6810 | /* X86_64_3F */ | |
6811 | { | |
bf890a93 | 6812 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6813 | }, |
6814 | ||
6815 | /* X86_64_60 */ | |
6816 | { | |
bf890a93 | 6817 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6818 | }, |
6819 | ||
6820 | /* X86_64_61 */ | |
6821 | { | |
bf890a93 | 6822 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6823 | }, |
6824 | ||
6825 | /* X86_64_62 */ | |
6826 | { | |
6827 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6828 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6829 | }, |
6830 | ||
6831 | /* X86_64_63 */ | |
6832 | { | |
bf890a93 | 6833 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6834 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6835 | }, |
6836 | ||
6837 | /* X86_64_6D */ | |
6838 | { | |
bf890a93 IT |
6839 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6840 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6841 | }, |
6842 | ||
6843 | /* X86_64_6F */ | |
6844 | { | |
bf890a93 IT |
6845 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6846 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6847 | }, |
6848 | ||
d039fef3 | 6849 | /* X86_64_82 */ |
8b89fe14 | 6850 | { |
de194d85 | 6851 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6852 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6853 | }, |
6854 | ||
c0f3af97 L |
6855 | /* X86_64_9A */ |
6856 | { | |
bf890a93 | 6857 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6858 | }, |
6859 | ||
aeab2b26 JB |
6860 | /* X86_64_C2 */ |
6861 | { | |
6862 | { "retP", { Iw, BND }, 0 }, | |
6863 | { "ret@", { Iw, BND }, 0 }, | |
6864 | }, | |
6865 | ||
6866 | /* X86_64_C3 */ | |
6867 | { | |
6868 | { "retP", { BND }, 0 }, | |
6869 | { "ret@", { BND }, 0 }, | |
6870 | }, | |
6871 | ||
c0f3af97 L |
6872 | /* X86_64_C4 */ |
6873 | { | |
6874 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6875 | { VEX_C4_TABLE (VEX_0F) }, | |
6876 | }, | |
6877 | ||
6878 | /* X86_64_C5 */ | |
6879 | { | |
6880 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6881 | { VEX_C5_TABLE (VEX_0F) }, | |
6882 | }, | |
6883 | ||
6884 | /* X86_64_CE */ | |
6885 | { | |
bf890a93 | 6886 | { "into", { XX }, 0 }, |
c0f3af97 L |
6887 | }, |
6888 | ||
6889 | /* X86_64_D4 */ | |
6890 | { | |
bf890a93 | 6891 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6892 | }, |
6893 | ||
6894 | /* X86_64_D5 */ | |
6895 | { | |
bf890a93 | 6896 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6897 | }, |
6898 | ||
a72d2af2 L |
6899 | /* X86_64_E8 */ |
6900 | { | |
6901 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6902 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6903 | }, |
6904 | ||
6905 | /* X86_64_E9 */ | |
6906 | { | |
6907 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6908 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6909 | }, |
6910 | ||
c0f3af97 L |
6911 | /* X86_64_EA */ |
6912 | { | |
bf890a93 | 6913 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6914 | }, |
6915 | ||
6916 | /* X86_64_0F01_REG_0 */ | |
6917 | { | |
bf890a93 IT |
6918 | { "sgdt{Q|IQ}", { M }, 0 }, |
6919 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6920 | }, |
6921 | ||
6922 | /* X86_64_0F01_REG_1 */ | |
6923 | { | |
bf890a93 IT |
6924 | { "sidt{Q|IQ}", { M }, 0 }, |
6925 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6926 | }, |
6927 | ||
6928 | /* X86_64_0F01_REG_2 */ | |
6929 | { | |
bf890a93 IT |
6930 | { "lgdt{Q|Q}", { M }, 0 }, |
6931 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6932 | }, |
6933 | ||
6934 | /* X86_64_0F01_REG_3 */ | |
6935 | { | |
bf890a93 IT |
6936 | { "lidt{Q|Q}", { M }, 0 }, |
6937 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6938 | }, |
6939 | }; | |
6940 | ||
6941 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6942 | |
6943 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6944 | { |
6945 | /* 00 */ | |
507bd325 L |
6946 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6947 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6948 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6949 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6950 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6951 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6952 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6953 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6954 | /* 08 */ |
507bd325 L |
6955 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6956 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6957 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6958 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6959 | { Bad_Opcode }, |
6960 | { Bad_Opcode }, | |
6961 | { Bad_Opcode }, | |
6962 | { Bad_Opcode }, | |
f88c9eb0 SP |
6963 | /* 10 */ |
6964 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6965 | { Bad_Opcode }, |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
f88c9eb0 SP |
6968 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6969 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6970 | { Bad_Opcode }, |
f88c9eb0 SP |
6971 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6972 | /* 18 */ | |
592d1631 L |
6973 | { Bad_Opcode }, |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
507bd325 L |
6977 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6978 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6979 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6980 | { Bad_Opcode }, |
f88c9eb0 SP |
6981 | /* 20 */ |
6982 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6983 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6984 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6985 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6986 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6987 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6988 | { Bad_Opcode }, |
6989 | { Bad_Opcode }, | |
f88c9eb0 SP |
6990 | /* 28 */ |
6991 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6992 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6993 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6994 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6995 | { Bad_Opcode }, |
6996 | { Bad_Opcode }, | |
6997 | { Bad_Opcode }, | |
6998 | { Bad_Opcode }, | |
f88c9eb0 SP |
6999 | /* 30 */ |
7000 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
7001 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7002 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7003 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7004 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7005 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7006 | { Bad_Opcode }, |
f88c9eb0 SP |
7007 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7008 | /* 38 */ | |
7009 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7010 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7011 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7012 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7015 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7016 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7017 | /* 40 */ | |
7018 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7019 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7020 | { Bad_Opcode }, |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
7024 | { Bad_Opcode }, | |
7025 | { Bad_Opcode }, | |
f88c9eb0 | 7026 | /* 48 */ |
592d1631 L |
7027 | { Bad_Opcode }, |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
7033 | { Bad_Opcode }, | |
7034 | { Bad_Opcode }, | |
f88c9eb0 | 7035 | /* 50 */ |
592d1631 L |
7036 | { Bad_Opcode }, |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
7042 | { Bad_Opcode }, | |
7043 | { Bad_Opcode }, | |
f88c9eb0 | 7044 | /* 58 */ |
592d1631 L |
7045 | { Bad_Opcode }, |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
7051 | { Bad_Opcode }, | |
7052 | { Bad_Opcode }, | |
f88c9eb0 | 7053 | /* 60 */ |
592d1631 L |
7054 | { Bad_Opcode }, |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
7060 | { Bad_Opcode }, | |
7061 | { Bad_Opcode }, | |
f88c9eb0 | 7062 | /* 68 */ |
592d1631 L |
7063 | { Bad_Opcode }, |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
7069 | { Bad_Opcode }, | |
7070 | { Bad_Opcode }, | |
f88c9eb0 | 7071 | /* 70 */ |
592d1631 L |
7072 | { Bad_Opcode }, |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
7078 | { Bad_Opcode }, | |
7079 | { Bad_Opcode }, | |
f88c9eb0 | 7080 | /* 78 */ |
592d1631 L |
7081 | { Bad_Opcode }, |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
7087 | { Bad_Opcode }, | |
7088 | { Bad_Opcode }, | |
f88c9eb0 SP |
7089 | /* 80 */ |
7090 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7091 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7092 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7093 | { Bad_Opcode }, |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
7096 | { Bad_Opcode }, | |
7097 | { Bad_Opcode }, | |
f88c9eb0 | 7098 | /* 88 */ |
592d1631 L |
7099 | { Bad_Opcode }, |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
7105 | { Bad_Opcode }, | |
7106 | { Bad_Opcode }, | |
f88c9eb0 | 7107 | /* 90 */ |
592d1631 L |
7108 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
7114 | { Bad_Opcode }, | |
7115 | { Bad_Opcode }, | |
f88c9eb0 | 7116 | /* 98 */ |
592d1631 L |
7117 | { Bad_Opcode }, |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
7123 | { Bad_Opcode }, | |
7124 | { Bad_Opcode }, | |
f88c9eb0 | 7125 | /* a0 */ |
592d1631 L |
7126 | { Bad_Opcode }, |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
f88c9eb0 | 7134 | /* a8 */ |
592d1631 L |
7135 | { Bad_Opcode }, |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
7141 | { Bad_Opcode }, | |
7142 | { Bad_Opcode }, | |
f88c9eb0 | 7143 | /* b0 */ |
592d1631 L |
7144 | { Bad_Opcode }, |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
7150 | { Bad_Opcode }, | |
7151 | { Bad_Opcode }, | |
f88c9eb0 | 7152 | /* b8 */ |
592d1631 L |
7153 | { Bad_Opcode }, |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
f88c9eb0 | 7161 | /* c0 */ |
592d1631 L |
7162 | { Bad_Opcode }, |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
f88c9eb0 | 7170 | /* c8 */ |
a0046408 L |
7171 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7172 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7173 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7174 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7175 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7176 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7177 | { Bad_Opcode }, |
48521003 | 7178 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7179 | /* d0 */ |
592d1631 L |
7180 | { Bad_Opcode }, |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
f88c9eb0 | 7188 | /* d8 */ |
592d1631 L |
7189 | { Bad_Opcode }, |
7190 | { Bad_Opcode }, | |
7191 | { Bad_Opcode }, | |
f88c9eb0 SP |
7192 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7193 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7194 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7195 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7196 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7197 | /* e0 */ | |
592d1631 L |
7198 | { Bad_Opcode }, |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
7204 | { Bad_Opcode }, | |
7205 | { Bad_Opcode }, | |
f88c9eb0 | 7206 | /* e8 */ |
592d1631 L |
7207 | { Bad_Opcode }, |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
f88c9eb0 SP |
7215 | /* f0 */ |
7216 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7217 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7218 | { Bad_Opcode }, |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
603555e5 | 7221 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7222 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7223 | { Bad_Opcode }, |
f88c9eb0 | 7224 | /* f8 */ |
c0a30a9f L |
7225 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7226 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7227 | { Bad_Opcode }, |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
f88c9eb0 SP |
7233 | }, |
7234 | /* THREE_BYTE_0F3A */ | |
7235 | { | |
7236 | /* 00 */ | |
592d1631 L |
7237 | { Bad_Opcode }, |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
7243 | { Bad_Opcode }, | |
7244 | { Bad_Opcode }, | |
f88c9eb0 SP |
7245 | /* 08 */ |
7246 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7247 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7248 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7250 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7251 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7252 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7253 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7254 | /* 10 */ |
592d1631 L |
7255 | { Bad_Opcode }, |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
f88c9eb0 SP |
7259 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7260 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7261 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7262 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7263 | /* 18 */ | |
592d1631 L |
7264 | { Bad_Opcode }, |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
7270 | { Bad_Opcode }, | |
7271 | { Bad_Opcode }, | |
f88c9eb0 SP |
7272 | /* 20 */ |
7273 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7274 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7275 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7276 | { Bad_Opcode }, |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
7279 | { Bad_Opcode }, | |
7280 | { Bad_Opcode }, | |
f88c9eb0 | 7281 | /* 28 */ |
592d1631 L |
7282 | { Bad_Opcode }, |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
7288 | { Bad_Opcode }, | |
7289 | { Bad_Opcode }, | |
f88c9eb0 | 7290 | /* 30 */ |
592d1631 L |
7291 | { Bad_Opcode }, |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
7297 | { Bad_Opcode }, | |
7298 | { Bad_Opcode }, | |
f88c9eb0 | 7299 | /* 38 */ |
592d1631 L |
7300 | { Bad_Opcode }, |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
7306 | { Bad_Opcode }, | |
7307 | { Bad_Opcode }, | |
f88c9eb0 SP |
7308 | /* 40 */ |
7309 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7310 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7311 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7312 | { Bad_Opcode }, |
f88c9eb0 | 7313 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7314 | { Bad_Opcode }, |
7315 | { Bad_Opcode }, | |
7316 | { Bad_Opcode }, | |
f88c9eb0 | 7317 | /* 48 */ |
592d1631 L |
7318 | { Bad_Opcode }, |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
7324 | { Bad_Opcode }, | |
7325 | { Bad_Opcode }, | |
f88c9eb0 | 7326 | /* 50 */ |
592d1631 L |
7327 | { Bad_Opcode }, |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
7333 | { Bad_Opcode }, | |
7334 | { Bad_Opcode }, | |
f88c9eb0 | 7335 | /* 58 */ |
592d1631 L |
7336 | { Bad_Opcode }, |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
7342 | { Bad_Opcode }, | |
7343 | { Bad_Opcode }, | |
f88c9eb0 SP |
7344 | /* 60 */ |
7345 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7346 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7347 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7348 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7349 | { Bad_Opcode }, |
7350 | { Bad_Opcode }, | |
7351 | { Bad_Opcode }, | |
7352 | { Bad_Opcode }, | |
f88c9eb0 | 7353 | /* 68 */ |
592d1631 L |
7354 | { Bad_Opcode }, |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
7360 | { Bad_Opcode }, | |
7361 | { Bad_Opcode }, | |
f88c9eb0 | 7362 | /* 70 */ |
592d1631 L |
7363 | { Bad_Opcode }, |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
7369 | { Bad_Opcode }, | |
7370 | { Bad_Opcode }, | |
f88c9eb0 | 7371 | /* 78 */ |
592d1631 L |
7372 | { Bad_Opcode }, |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
7378 | { Bad_Opcode }, | |
7379 | { Bad_Opcode }, | |
f88c9eb0 | 7380 | /* 80 */ |
592d1631 L |
7381 | { Bad_Opcode }, |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
7387 | { Bad_Opcode }, | |
7388 | { Bad_Opcode }, | |
f88c9eb0 | 7389 | /* 88 */ |
592d1631 L |
7390 | { Bad_Opcode }, |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
7396 | { Bad_Opcode }, | |
7397 | { Bad_Opcode }, | |
f88c9eb0 | 7398 | /* 90 */ |
592d1631 L |
7399 | { Bad_Opcode }, |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
7405 | { Bad_Opcode }, | |
7406 | { Bad_Opcode }, | |
f88c9eb0 | 7407 | /* 98 */ |
592d1631 L |
7408 | { Bad_Opcode }, |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
7414 | { Bad_Opcode }, | |
7415 | { Bad_Opcode }, | |
f88c9eb0 | 7416 | /* a0 */ |
592d1631 L |
7417 | { Bad_Opcode }, |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
f88c9eb0 | 7425 | /* a8 */ |
592d1631 L |
7426 | { Bad_Opcode }, |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
f88c9eb0 | 7434 | /* b0 */ |
592d1631 L |
7435 | { Bad_Opcode }, |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
f88c9eb0 | 7443 | /* b8 */ |
592d1631 L |
7444 | { Bad_Opcode }, |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
f88c9eb0 | 7452 | /* c0 */ |
592d1631 L |
7453 | { Bad_Opcode }, |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
f88c9eb0 | 7461 | /* c8 */ |
592d1631 L |
7462 | { Bad_Opcode }, |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
7465 | { Bad_Opcode }, | |
a0046408 | 7466 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7467 | { Bad_Opcode }, |
48521003 IT |
7468 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7469 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7470 | /* d0 */ |
592d1631 L |
7471 | { Bad_Opcode }, |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
f88c9eb0 | 7479 | /* d8 */ |
592d1631 L |
7480 | { Bad_Opcode }, |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
f88c9eb0 SP |
7487 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7488 | /* e0 */ | |
592d1631 L |
7489 | { Bad_Opcode }, |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
7492 | { Bad_Opcode }, | |
7493 | { Bad_Opcode }, | |
592d1631 L |
7494 | { Bad_Opcode }, |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
85f10a01 | 7497 | /* e8 */ |
592d1631 L |
7498 | { Bad_Opcode }, |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
85f10a01 | 7506 | /* f0 */ |
592d1631 L |
7507 | { Bad_Opcode }, |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
85f10a01 | 7515 | /* f8 */ |
592d1631 L |
7516 | { Bad_Opcode }, |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
85f10a01 | 7524 | }, |
f88c9eb0 SP |
7525 | }; |
7526 | ||
7527 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7528 | /* XOP_08 */ |
85f10a01 MM |
7529 | { |
7530 | /* 00 */ | |
592d1631 L |
7531 | { Bad_Opcode }, |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
7537 | { Bad_Opcode }, | |
7538 | { Bad_Opcode }, | |
85f10a01 | 7539 | /* 08 */ |
592d1631 L |
7540 | { Bad_Opcode }, |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
7546 | { Bad_Opcode }, | |
7547 | { Bad_Opcode }, | |
85f10a01 | 7548 | /* 10 */ |
3929df09 | 7549 | { Bad_Opcode }, |
592d1631 L |
7550 | { Bad_Opcode }, |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
7555 | { Bad_Opcode }, | |
7556 | { Bad_Opcode }, | |
85f10a01 | 7557 | /* 18 */ |
592d1631 L |
7558 | { Bad_Opcode }, |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
7564 | { Bad_Opcode }, | |
7565 | { Bad_Opcode }, | |
85f10a01 | 7566 | /* 20 */ |
592d1631 L |
7567 | { Bad_Opcode }, |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
7573 | { Bad_Opcode }, | |
7574 | { Bad_Opcode }, | |
85f10a01 | 7575 | /* 28 */ |
592d1631 L |
7576 | { Bad_Opcode }, |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
7582 | { Bad_Opcode }, | |
7583 | { Bad_Opcode }, | |
c0f3af97 | 7584 | /* 30 */ |
592d1631 L |
7585 | { Bad_Opcode }, |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
7591 | { Bad_Opcode }, | |
7592 | { Bad_Opcode }, | |
c0f3af97 | 7593 | /* 38 */ |
592d1631 L |
7594 | { Bad_Opcode }, |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
7600 | { Bad_Opcode }, | |
7601 | { Bad_Opcode }, | |
c0f3af97 | 7602 | /* 40 */ |
592d1631 L |
7603 | { Bad_Opcode }, |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
7609 | { Bad_Opcode }, | |
7610 | { Bad_Opcode }, | |
85f10a01 | 7611 | /* 48 */ |
592d1631 L |
7612 | { Bad_Opcode }, |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
7618 | { Bad_Opcode }, | |
7619 | { Bad_Opcode }, | |
c0f3af97 | 7620 | /* 50 */ |
592d1631 L |
7621 | { Bad_Opcode }, |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
7627 | { Bad_Opcode }, | |
7628 | { Bad_Opcode }, | |
85f10a01 | 7629 | /* 58 */ |
592d1631 L |
7630 | { Bad_Opcode }, |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
7636 | { Bad_Opcode }, | |
7637 | { Bad_Opcode }, | |
c1e679ec | 7638 | /* 60 */ |
592d1631 L |
7639 | { Bad_Opcode }, |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
7645 | { Bad_Opcode }, | |
7646 | { Bad_Opcode }, | |
c0f3af97 | 7647 | /* 68 */ |
592d1631 L |
7648 | { Bad_Opcode }, |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
7654 | { Bad_Opcode }, | |
7655 | { Bad_Opcode }, | |
85f10a01 | 7656 | /* 70 */ |
592d1631 L |
7657 | { Bad_Opcode }, |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
7663 | { Bad_Opcode }, | |
7664 | { Bad_Opcode }, | |
85f10a01 | 7665 | /* 78 */ |
592d1631 L |
7666 | { Bad_Opcode }, |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
7672 | { Bad_Opcode }, | |
7673 | { Bad_Opcode }, | |
85f10a01 | 7674 | /* 80 */ |
592d1631 L |
7675 | { Bad_Opcode }, |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
3a2430e0 JB |
7680 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7681 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7682 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7683 | /* 88 */ |
592d1631 L |
7684 | { Bad_Opcode }, |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
7688 | { Bad_Opcode }, | |
7689 | { Bad_Opcode }, | |
3a2430e0 JB |
7690 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7691 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7692 | /* 90 */ |
592d1631 L |
7693 | { Bad_Opcode }, |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
3a2430e0 JB |
7698 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7699 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7700 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7701 | /* 98 */ |
592d1631 L |
7702 | { Bad_Opcode }, |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
3a2430e0 JB |
7708 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7709 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7710 | /* a0 */ |
592d1631 L |
7711 | { Bad_Opcode }, |
7712 | { Bad_Opcode }, | |
3a2430e0 JB |
7713 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7714 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7715 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, | |
3a2430e0 | 7717 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7718 | { Bad_Opcode }, |
5dd85c99 | 7719 | /* a8 */ |
592d1631 L |
7720 | { Bad_Opcode }, |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
5dd85c99 | 7728 | /* b0 */ |
592d1631 L |
7729 | { Bad_Opcode }, |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
7733 | { Bad_Opcode }, | |
7734 | { Bad_Opcode }, | |
3a2430e0 | 7735 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7736 | { Bad_Opcode }, |
5dd85c99 | 7737 | /* b8 */ |
592d1631 L |
7738 | { Bad_Opcode }, |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
5dd85c99 | 7746 | /* c0 */ |
bf890a93 IT |
7747 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7748 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7749 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7750 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7751 | { Bad_Opcode }, |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
5dd85c99 | 7755 | /* c8 */ |
592d1631 L |
7756 | { Bad_Opcode }, |
7757 | { Bad_Opcode }, | |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
ff688e1f L |
7760 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7761 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7762 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7763 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7764 | /* d0 */ |
592d1631 L |
7765 | { Bad_Opcode }, |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
5dd85c99 | 7773 | /* d8 */ |
592d1631 L |
7774 | { Bad_Opcode }, |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
5dd85c99 | 7782 | /* e0 */ |
592d1631 L |
7783 | { Bad_Opcode }, |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
5dd85c99 | 7791 | /* e8 */ |
592d1631 L |
7792 | { Bad_Opcode }, |
7793 | { Bad_Opcode }, | |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
ff688e1f L |
7796 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7797 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7798 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7799 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7800 | /* f0 */ |
592d1631 L |
7801 | { Bad_Opcode }, |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
5dd85c99 | 7809 | /* f8 */ |
592d1631 L |
7810 | { Bad_Opcode }, |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
5dd85c99 SP |
7818 | }, |
7819 | /* XOP_09 */ | |
7820 | { | |
7821 | /* 00 */ | |
592d1631 | 7822 | { Bad_Opcode }, |
2a2a0f38 QN |
7823 | { REG_TABLE (REG_XOP_TBM_01) }, |
7824 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7825 | { Bad_Opcode }, |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
7828 | { Bad_Opcode }, | |
7829 | { Bad_Opcode }, | |
5dd85c99 | 7830 | /* 08 */ |
592d1631 L |
7831 | { Bad_Opcode }, |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
7837 | { Bad_Opcode }, | |
7838 | { Bad_Opcode }, | |
5dd85c99 | 7839 | /* 10 */ |
592d1631 L |
7840 | { Bad_Opcode }, |
7841 | { Bad_Opcode }, | |
5dd85c99 | 7842 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7843 | { Bad_Opcode }, |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
7846 | { Bad_Opcode }, | |
7847 | { Bad_Opcode }, | |
5dd85c99 | 7848 | /* 18 */ |
592d1631 L |
7849 | { Bad_Opcode }, |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
7855 | { Bad_Opcode }, | |
7856 | { Bad_Opcode }, | |
5dd85c99 | 7857 | /* 20 */ |
592d1631 L |
7858 | { Bad_Opcode }, |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
7864 | { Bad_Opcode }, | |
7865 | { Bad_Opcode }, | |
5dd85c99 | 7866 | /* 28 */ |
592d1631 L |
7867 | { Bad_Opcode }, |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
7873 | { Bad_Opcode }, | |
7874 | { Bad_Opcode }, | |
5dd85c99 | 7875 | /* 30 */ |
592d1631 L |
7876 | { Bad_Opcode }, |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
7882 | { Bad_Opcode }, | |
7883 | { Bad_Opcode }, | |
5dd85c99 | 7884 | /* 38 */ |
592d1631 L |
7885 | { Bad_Opcode }, |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
7891 | { Bad_Opcode }, | |
7892 | { Bad_Opcode }, | |
5dd85c99 | 7893 | /* 40 */ |
592d1631 L |
7894 | { Bad_Opcode }, |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
7900 | { Bad_Opcode }, | |
7901 | { Bad_Opcode }, | |
5dd85c99 | 7902 | /* 48 */ |
592d1631 L |
7903 | { Bad_Opcode }, |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
7909 | { Bad_Opcode }, | |
7910 | { Bad_Opcode }, | |
5dd85c99 | 7911 | /* 50 */ |
592d1631 L |
7912 | { Bad_Opcode }, |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
7918 | { Bad_Opcode }, | |
7919 | { Bad_Opcode }, | |
5dd85c99 | 7920 | /* 58 */ |
592d1631 L |
7921 | { Bad_Opcode }, |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
7927 | { Bad_Opcode }, | |
7928 | { Bad_Opcode }, | |
5dd85c99 | 7929 | /* 60 */ |
592d1631 L |
7930 | { Bad_Opcode }, |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
7936 | { Bad_Opcode }, | |
7937 | { Bad_Opcode }, | |
5dd85c99 | 7938 | /* 68 */ |
592d1631 L |
7939 | { Bad_Opcode }, |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
7945 | { Bad_Opcode }, | |
7946 | { Bad_Opcode }, | |
5dd85c99 | 7947 | /* 70 */ |
592d1631 L |
7948 | { Bad_Opcode }, |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
7954 | { Bad_Opcode }, | |
7955 | { Bad_Opcode }, | |
5dd85c99 | 7956 | /* 78 */ |
592d1631 L |
7957 | { Bad_Opcode }, |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
7963 | { Bad_Opcode }, | |
7964 | { Bad_Opcode }, | |
5dd85c99 | 7965 | /* 80 */ |
592a252b L |
7966 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7967 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7968 | { "vfrczss", { XM, EXd }, 0 }, |
7969 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7970 | { Bad_Opcode }, |
7971 | { Bad_Opcode }, | |
7972 | { Bad_Opcode }, | |
7973 | { Bad_Opcode }, | |
5dd85c99 | 7974 | /* 88 */ |
592d1631 L |
7975 | { Bad_Opcode }, |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
7981 | { Bad_Opcode }, | |
7982 | { Bad_Opcode }, | |
5dd85c99 | 7983 | /* 90 */ |
bf890a93 IT |
7984 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7985 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7986 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7987 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7988 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7989 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7990 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7991 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7992 | /* 98 */ |
bf890a93 IT |
7993 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7994 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7995 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7996 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7997 | { Bad_Opcode }, |
7998 | { Bad_Opcode }, | |
7999 | { Bad_Opcode }, | |
8000 | { Bad_Opcode }, | |
5dd85c99 | 8001 | /* a0 */ |
592d1631 L |
8002 | { Bad_Opcode }, |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
5dd85c99 | 8010 | /* a8 */ |
592d1631 L |
8011 | { Bad_Opcode }, |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
5dd85c99 | 8019 | /* b0 */ |
592d1631 L |
8020 | { Bad_Opcode }, |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
5dd85c99 | 8028 | /* b8 */ |
592d1631 L |
8029 | { Bad_Opcode }, |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
5dd85c99 | 8037 | /* c0 */ |
592d1631 | 8038 | { Bad_Opcode }, |
bf890a93 IT |
8039 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8040 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8041 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8042 | { Bad_Opcode }, |
8043 | { Bad_Opcode }, | |
bf890a93 IT |
8044 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8045 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8046 | /* c8 */ |
592d1631 L |
8047 | { Bad_Opcode }, |
8048 | { Bad_Opcode }, | |
8049 | { Bad_Opcode }, | |
bf890a93 | 8050 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8051 | { Bad_Opcode }, |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
5dd85c99 | 8055 | /* d0 */ |
592d1631 | 8056 | { Bad_Opcode }, |
bf890a93 IT |
8057 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8058 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8059 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8060 | { Bad_Opcode }, |
8061 | { Bad_Opcode }, | |
bf890a93 IT |
8062 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8063 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8064 | /* d8 */ |
592d1631 L |
8065 | { Bad_Opcode }, |
8066 | { Bad_Opcode }, | |
8067 | { Bad_Opcode }, | |
bf890a93 | 8068 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8069 | { Bad_Opcode }, |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
5dd85c99 | 8073 | /* e0 */ |
592d1631 | 8074 | { Bad_Opcode }, |
bf890a93 IT |
8075 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8076 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8077 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8078 | { Bad_Opcode }, |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
4e7d34a6 | 8082 | /* e8 */ |
592d1631 L |
8083 | { Bad_Opcode }, |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
4e7d34a6 | 8091 | /* f0 */ |
592d1631 L |
8092 | { Bad_Opcode }, |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
4e7d34a6 | 8100 | /* f8 */ |
592d1631 L |
8101 | { Bad_Opcode }, |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
4e7d34a6 | 8109 | }, |
f88c9eb0 | 8110 | /* XOP_0A */ |
4e7d34a6 L |
8111 | { |
8112 | /* 00 */ | |
592d1631 L |
8113 | { Bad_Opcode }, |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
8119 | { Bad_Opcode }, | |
8120 | { Bad_Opcode }, | |
4e7d34a6 | 8121 | /* 08 */ |
592d1631 L |
8122 | { Bad_Opcode }, |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
8128 | { Bad_Opcode }, | |
8129 | { Bad_Opcode }, | |
4e7d34a6 | 8130 | /* 10 */ |
c1dc7af5 | 8131 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8132 | { Bad_Opcode }, |
f88c9eb0 | 8133 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8134 | { Bad_Opcode }, |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
8137 | { Bad_Opcode }, | |
8138 | { Bad_Opcode }, | |
4e7d34a6 | 8139 | /* 18 */ |
592d1631 L |
8140 | { Bad_Opcode }, |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
8146 | { Bad_Opcode }, | |
8147 | { Bad_Opcode }, | |
4e7d34a6 | 8148 | /* 20 */ |
592d1631 L |
8149 | { Bad_Opcode }, |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
8155 | { Bad_Opcode }, | |
8156 | { Bad_Opcode }, | |
4e7d34a6 | 8157 | /* 28 */ |
592d1631 L |
8158 | { Bad_Opcode }, |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
8164 | { Bad_Opcode }, | |
8165 | { Bad_Opcode }, | |
4e7d34a6 | 8166 | /* 30 */ |
592d1631 L |
8167 | { Bad_Opcode }, |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
8173 | { Bad_Opcode }, | |
8174 | { Bad_Opcode }, | |
c0f3af97 | 8175 | /* 38 */ |
592d1631 L |
8176 | { Bad_Opcode }, |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
8182 | { Bad_Opcode }, | |
8183 | { Bad_Opcode }, | |
c0f3af97 | 8184 | /* 40 */ |
592d1631 L |
8185 | { Bad_Opcode }, |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
8191 | { Bad_Opcode }, | |
8192 | { Bad_Opcode }, | |
c1e679ec | 8193 | /* 48 */ |
592d1631 L |
8194 | { Bad_Opcode }, |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
8200 | { Bad_Opcode }, | |
8201 | { Bad_Opcode }, | |
c1e679ec | 8202 | /* 50 */ |
592d1631 L |
8203 | { Bad_Opcode }, |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
8209 | { Bad_Opcode }, | |
8210 | { Bad_Opcode }, | |
4e7d34a6 | 8211 | /* 58 */ |
592d1631 L |
8212 | { Bad_Opcode }, |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
8218 | { Bad_Opcode }, | |
8219 | { Bad_Opcode }, | |
4e7d34a6 | 8220 | /* 60 */ |
592d1631 L |
8221 | { Bad_Opcode }, |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
8227 | { Bad_Opcode }, | |
8228 | { Bad_Opcode }, | |
4e7d34a6 | 8229 | /* 68 */ |
592d1631 L |
8230 | { Bad_Opcode }, |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
8236 | { Bad_Opcode }, | |
8237 | { Bad_Opcode }, | |
4e7d34a6 | 8238 | /* 70 */ |
592d1631 L |
8239 | { Bad_Opcode }, |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
8245 | { Bad_Opcode }, | |
8246 | { Bad_Opcode }, | |
4e7d34a6 | 8247 | /* 78 */ |
592d1631 L |
8248 | { Bad_Opcode }, |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
8254 | { Bad_Opcode }, | |
8255 | { Bad_Opcode }, | |
4e7d34a6 | 8256 | /* 80 */ |
592d1631 L |
8257 | { Bad_Opcode }, |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
8263 | { Bad_Opcode }, | |
8264 | { Bad_Opcode }, | |
4e7d34a6 | 8265 | /* 88 */ |
592d1631 L |
8266 | { Bad_Opcode }, |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
8272 | { Bad_Opcode }, | |
8273 | { Bad_Opcode }, | |
4e7d34a6 | 8274 | /* 90 */ |
592d1631 L |
8275 | { Bad_Opcode }, |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
8281 | { Bad_Opcode }, | |
8282 | { Bad_Opcode }, | |
4e7d34a6 | 8283 | /* 98 */ |
592d1631 L |
8284 | { Bad_Opcode }, |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
8290 | { Bad_Opcode }, | |
8291 | { Bad_Opcode }, | |
4e7d34a6 | 8292 | /* a0 */ |
592d1631 L |
8293 | { Bad_Opcode }, |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
4e7d34a6 | 8301 | /* a8 */ |
592d1631 L |
8302 | { Bad_Opcode }, |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
d5d7db8e | 8310 | /* b0 */ |
592d1631 L |
8311 | { Bad_Opcode }, |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
8317 | { Bad_Opcode }, | |
8318 | { Bad_Opcode }, | |
85f10a01 | 8319 | /* b8 */ |
592d1631 L |
8320 | { Bad_Opcode }, |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
85f10a01 | 8328 | /* c0 */ |
592d1631 L |
8329 | { Bad_Opcode }, |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
85f10a01 | 8337 | /* c8 */ |
592d1631 L |
8338 | { Bad_Opcode }, |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
8344 | { Bad_Opcode }, | |
8345 | { Bad_Opcode }, | |
85f10a01 | 8346 | /* d0 */ |
592d1631 L |
8347 | { Bad_Opcode }, |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
85f10a01 | 8355 | /* d8 */ |
592d1631 L |
8356 | { Bad_Opcode }, |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
85f10a01 | 8364 | /* e0 */ |
592d1631 L |
8365 | { Bad_Opcode }, |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
8371 | { Bad_Opcode }, | |
8372 | { Bad_Opcode }, | |
85f10a01 | 8373 | /* e8 */ |
592d1631 L |
8374 | { Bad_Opcode }, |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
8380 | { Bad_Opcode }, | |
8381 | { Bad_Opcode }, | |
85f10a01 | 8382 | /* f0 */ |
592d1631 L |
8383 | { Bad_Opcode }, |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
8389 | { Bad_Opcode }, | |
8390 | { Bad_Opcode }, | |
85f10a01 | 8391 | /* f8 */ |
592d1631 L |
8392 | { Bad_Opcode }, |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
8398 | { Bad_Opcode }, | |
8399 | { Bad_Opcode }, | |
85f10a01 | 8400 | }, |
c0f3af97 L |
8401 | }; |
8402 | ||
8403 | static const struct dis386 vex_table[][256] = { | |
8404 | /* VEX_0F */ | |
85f10a01 MM |
8405 | { |
8406 | /* 00 */ | |
592d1631 L |
8407 | { Bad_Opcode }, |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
8413 | { Bad_Opcode }, | |
8414 | { Bad_Opcode }, | |
85f10a01 | 8415 | /* 08 */ |
592d1631 L |
8416 | { Bad_Opcode }, |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
8422 | { Bad_Opcode }, | |
8423 | { Bad_Opcode }, | |
c0f3af97 | 8424 | /* 10 */ |
592a252b L |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8426 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8428 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8429 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8430 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8431 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8432 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8433 | /* 18 */ |
592d1631 L |
8434 | { Bad_Opcode }, |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
8440 | { Bad_Opcode }, | |
8441 | { Bad_Opcode }, | |
c0f3af97 | 8442 | /* 20 */ |
592d1631 L |
8443 | { Bad_Opcode }, |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
8449 | { Bad_Opcode }, | |
8450 | { Bad_Opcode }, | |
c0f3af97 | 8451 | /* 28 */ |
bf926894 JB |
8452 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8453 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8455 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8457 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8458 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8459 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8460 | /* 30 */ |
592d1631 L |
8461 | { Bad_Opcode }, |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
8467 | { Bad_Opcode }, | |
8468 | { Bad_Opcode }, | |
4e7d34a6 | 8469 | /* 38 */ |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
8476 | { Bad_Opcode }, | |
8477 | { Bad_Opcode }, | |
d5d7db8e | 8478 | /* 40 */ |
592d1631 | 8479 | { Bad_Opcode }, |
43234a1e L |
8480 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8481 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8482 | { Bad_Opcode }, |
43234a1e L |
8483 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8484 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8485 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8486 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8487 | /* 48 */ |
592d1631 L |
8488 | { Bad_Opcode }, |
8489 | { Bad_Opcode }, | |
1ba585e8 | 8490 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8491 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8492 | { Bad_Opcode }, |
8493 | { Bad_Opcode }, | |
8494 | { Bad_Opcode }, | |
8495 | { Bad_Opcode }, | |
d5d7db8e | 8496 | /* 50 */ |
592a252b L |
8497 | { MOD_TABLE (MOD_VEX_0F50) }, |
8498 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8499 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8500 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8501 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8502 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8503 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8504 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8505 | /* 58 */ |
592a252b L |
8506 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8507 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8508 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8509 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8510 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8511 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8512 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8514 | /* 60 */ |
592a252b L |
8515 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8516 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8517 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8518 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8519 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8520 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8521 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8522 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8523 | /* 68 */ |
592a252b L |
8524 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8525 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8529 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8530 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8531 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8532 | /* 70 */ |
592a252b L |
8533 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8534 | { REG_TABLE (REG_VEX_0F71) }, | |
8535 | { REG_TABLE (REG_VEX_0F72) }, | |
8536 | { REG_TABLE (REG_VEX_0F73) }, | |
8537 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8538 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8539 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8540 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8541 | /* 78 */ |
592d1631 L |
8542 | { Bad_Opcode }, |
8543 | { Bad_Opcode }, | |
8544 | { Bad_Opcode }, | |
8545 | { Bad_Opcode }, | |
592a252b L |
8546 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8547 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8548 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8549 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8550 | /* 80 */ |
592d1631 L |
8551 | { Bad_Opcode }, |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
8557 | { Bad_Opcode }, | |
8558 | { Bad_Opcode }, | |
c0f3af97 | 8559 | /* 88 */ |
592d1631 L |
8560 | { Bad_Opcode }, |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
8566 | { Bad_Opcode }, | |
8567 | { Bad_Opcode }, | |
c0f3af97 | 8568 | /* 90 */ |
43234a1e L |
8569 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8573 | { Bad_Opcode }, |
8574 | { Bad_Opcode }, | |
8575 | { Bad_Opcode }, | |
8576 | { Bad_Opcode }, | |
c0f3af97 | 8577 | /* 98 */ |
43234a1e | 8578 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8579 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8580 | { Bad_Opcode }, |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
8584 | { Bad_Opcode }, | |
8585 | { Bad_Opcode }, | |
c0f3af97 | 8586 | /* a0 */ |
592d1631 L |
8587 | { Bad_Opcode }, |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
8593 | { Bad_Opcode }, | |
8594 | { Bad_Opcode }, | |
c0f3af97 | 8595 | /* a8 */ |
592d1631 L |
8596 | { Bad_Opcode }, |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
8600 | { Bad_Opcode }, | |
8601 | { Bad_Opcode }, | |
592a252b | 8602 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8603 | { Bad_Opcode }, |
c0f3af97 | 8604 | /* b0 */ |
592d1631 L |
8605 | { Bad_Opcode }, |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
8611 | { Bad_Opcode }, | |
8612 | { Bad_Opcode }, | |
c0f3af97 | 8613 | /* b8 */ |
592d1631 L |
8614 | { Bad_Opcode }, |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
8620 | { Bad_Opcode }, | |
8621 | { Bad_Opcode }, | |
c0f3af97 | 8622 | /* c0 */ |
592d1631 L |
8623 | { Bad_Opcode }, |
8624 | { Bad_Opcode }, | |
592a252b | 8625 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8626 | { Bad_Opcode }, |
592a252b L |
8627 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8628 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8629 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8630 | { Bad_Opcode }, |
c0f3af97 | 8631 | /* c8 */ |
592d1631 L |
8632 | { Bad_Opcode }, |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
8638 | { Bad_Opcode }, | |
8639 | { Bad_Opcode }, | |
c0f3af97 | 8640 | /* d0 */ |
592a252b L |
8641 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8642 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8648 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8649 | /* d8 */ |
592a252b L |
8650 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8651 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8652 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8657 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8658 | /* e0 */ |
592a252b L |
8659 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8660 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8661 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8665 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8666 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8667 | /* e8 */ |
592a252b L |
8668 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8669 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8674 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8676 | /* f0 */ |
592a252b L |
8677 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8678 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8683 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8685 | /* f8 */ |
592a252b L |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8691 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8692 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8693 | { Bad_Opcode }, |
c0f3af97 L |
8694 | }, |
8695 | /* VEX_0F38 */ | |
8696 | { | |
8697 | /* 00 */ | |
592a252b L |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8704 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8706 | /* 08 */ |
592a252b L |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8708 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8713 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8714 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8715 | /* 10 */ |
592d1631 L |
8716 | { Bad_Opcode }, |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
592a252b | 8719 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8720 | { Bad_Opcode }, |
8721 | { Bad_Opcode }, | |
6c30d220 | 8722 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8723 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8724 | /* 18 */ |
592a252b L |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8726 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8728 | { Bad_Opcode }, |
592a252b L |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8730 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8731 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8732 | { Bad_Opcode }, |
c0f3af97 | 8733 | /* 20 */ |
592a252b L |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8738 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8739 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8740 | { Bad_Opcode }, |
8741 | { Bad_Opcode }, | |
c0f3af97 | 8742 | /* 28 */ |
592a252b L |
8743 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8744 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8749 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8751 | /* 30 */ |
592a252b L |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8758 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8759 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8760 | /* 38 */ |
592a252b L |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8767 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8769 | /* 40 */ |
592a252b L |
8770 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8771 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8772 | { Bad_Opcode }, |
8773 | { Bad_Opcode }, | |
8774 | { Bad_Opcode }, | |
6c30d220 L |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8776 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8778 | /* 48 */ |
592d1631 L |
8779 | { Bad_Opcode }, |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
8785 | { Bad_Opcode }, | |
8786 | { Bad_Opcode }, | |
c0f3af97 | 8787 | /* 50 */ |
592d1631 L |
8788 | { Bad_Opcode }, |
8789 | { Bad_Opcode }, | |
8790 | { Bad_Opcode }, | |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
8794 | { Bad_Opcode }, | |
8795 | { Bad_Opcode }, | |
c0f3af97 | 8796 | /* 58 */ |
6c30d220 L |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8800 | { Bad_Opcode }, |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
8803 | { Bad_Opcode }, | |
8804 | { Bad_Opcode }, | |
c0f3af97 | 8805 | /* 60 */ |
592d1631 L |
8806 | { Bad_Opcode }, |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
8812 | { Bad_Opcode }, | |
8813 | { Bad_Opcode }, | |
c0f3af97 | 8814 | /* 68 */ |
592d1631 L |
8815 | { Bad_Opcode }, |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
8821 | { Bad_Opcode }, | |
8822 | { Bad_Opcode }, | |
c0f3af97 | 8823 | /* 70 */ |
592d1631 L |
8824 | { Bad_Opcode }, |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
8830 | { Bad_Opcode }, | |
8831 | { Bad_Opcode }, | |
c0f3af97 | 8832 | /* 78 */ |
6c30d220 L |
8833 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8835 | { Bad_Opcode }, |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
8839 | { Bad_Opcode }, | |
8840 | { Bad_Opcode }, | |
c0f3af97 | 8841 | /* 80 */ |
592d1631 L |
8842 | { Bad_Opcode }, |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
8848 | { Bad_Opcode }, | |
8849 | { Bad_Opcode }, | |
c0f3af97 | 8850 | /* 88 */ |
592d1631 L |
8851 | { Bad_Opcode }, |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
6c30d220 | 8855 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8856 | { Bad_Opcode }, |
6c30d220 | 8857 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8858 | { Bad_Opcode }, |
c0f3af97 | 8859 | /* 90 */ |
6c30d220 L |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8862 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8864 | { Bad_Opcode }, |
8865 | { Bad_Opcode }, | |
592a252b L |
8866 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8867 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8868 | /* 98 */ |
592a252b L |
8869 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8870 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8875 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8876 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8877 | /* a0 */ |
592d1631 L |
8878 | { Bad_Opcode }, |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
8882 | { Bad_Opcode }, | |
8883 | { Bad_Opcode }, | |
592a252b L |
8884 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8885 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8886 | /* a8 */ |
592a252b L |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8895 | /* b0 */ |
592d1631 L |
8896 | { Bad_Opcode }, |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
8901 | { Bad_Opcode }, | |
592a252b L |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8904 | /* b8 */ |
592a252b L |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8911 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8912 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8913 | /* c0 */ |
592d1631 L |
8914 | { Bad_Opcode }, |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
8919 | { Bad_Opcode }, | |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
c0f3af97 | 8922 | /* c8 */ |
592d1631 L |
8923 | { Bad_Opcode }, |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
48521003 | 8930 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8931 | /* d0 */ |
592d1631 L |
8932 | { Bad_Opcode }, |
8933 | { Bad_Opcode }, | |
8934 | { Bad_Opcode }, | |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
8938 | { Bad_Opcode }, | |
8939 | { Bad_Opcode }, | |
c0f3af97 | 8940 | /* d8 */ |
592d1631 L |
8941 | { Bad_Opcode }, |
8942 | { Bad_Opcode }, | |
8943 | { Bad_Opcode }, | |
592a252b L |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8945 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8947 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8948 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8949 | /* e0 */ |
592d1631 L |
8950 | { Bad_Opcode }, |
8951 | { Bad_Opcode }, | |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
8956 | { Bad_Opcode }, | |
8957 | { Bad_Opcode }, | |
c0f3af97 | 8958 | /* e8 */ |
592d1631 L |
8959 | { Bad_Opcode }, |
8960 | { Bad_Opcode }, | |
8961 | { Bad_Opcode }, | |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
8965 | { Bad_Opcode }, | |
8966 | { Bad_Opcode }, | |
c0f3af97 | 8967 | /* f0 */ |
592d1631 L |
8968 | { Bad_Opcode }, |
8969 | { Bad_Opcode }, | |
f12dc422 L |
8970 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8971 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8972 | { Bad_Opcode }, |
6c30d220 L |
8973 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8974 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8975 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8976 | /* f8 */ |
592d1631 L |
8977 | { Bad_Opcode }, |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
8983 | { Bad_Opcode }, | |
8984 | { Bad_Opcode }, | |
c0f3af97 L |
8985 | }, |
8986 | /* VEX_0F3A */ | |
8987 | { | |
8988 | /* 00 */ | |
6c30d220 L |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8992 | { Bad_Opcode }, |
592a252b L |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8994 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8995 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8996 | { Bad_Opcode }, |
c0f3af97 | 8997 | /* 08 */ |
592a252b L |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9004 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9005 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9006 | /* 10 */ |
592d1631 L |
9007 | { Bad_Opcode }, |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
592a252b L |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9013 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9015 | /* 18 */ |
592a252b L |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9018 | { Bad_Opcode }, |
9019 | { Bad_Opcode }, | |
9020 | { Bad_Opcode }, | |
592a252b | 9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9022 | { Bad_Opcode }, |
9023 | { Bad_Opcode }, | |
c0f3af97 | 9024 | /* 20 */ |
592a252b L |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9026 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9027 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9028 | { Bad_Opcode }, |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
9031 | { Bad_Opcode }, | |
9032 | { Bad_Opcode }, | |
c0f3af97 | 9033 | /* 28 */ |
592d1631 L |
9034 | { Bad_Opcode }, |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
9040 | { Bad_Opcode }, | |
9041 | { Bad_Opcode }, | |
c0f3af97 | 9042 | /* 30 */ |
43234a1e | 9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9045 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9046 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9047 | { Bad_Opcode }, |
9048 | { Bad_Opcode }, | |
9049 | { Bad_Opcode }, | |
9050 | { Bad_Opcode }, | |
c0f3af97 | 9051 | /* 38 */ |
6c30d220 L |
9052 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9053 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9054 | { Bad_Opcode }, |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
9058 | { Bad_Opcode }, | |
9059 | { Bad_Opcode }, | |
c0f3af97 | 9060 | /* 40 */ |
592a252b L |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9062 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9063 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9064 | { Bad_Opcode }, |
592a252b | 9065 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9066 | { Bad_Opcode }, |
6c30d220 | 9067 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9068 | { Bad_Opcode }, |
c0f3af97 | 9069 | /* 48 */ |
592a252b L |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9073 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9074 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9075 | { Bad_Opcode }, |
9076 | { Bad_Opcode }, | |
9077 | { Bad_Opcode }, | |
c0f3af97 | 9078 | /* 50 */ |
592d1631 L |
9079 | { Bad_Opcode }, |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
9085 | { Bad_Opcode }, | |
9086 | { Bad_Opcode }, | |
c0f3af97 | 9087 | /* 58 */ |
592d1631 L |
9088 | { Bad_Opcode }, |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
592a252b L |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9094 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9096 | /* 60 */ |
592a252b L |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9099 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9100 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9101 | { Bad_Opcode }, |
9102 | { Bad_Opcode }, | |
9103 | { Bad_Opcode }, | |
9104 | { Bad_Opcode }, | |
c0f3af97 | 9105 | /* 68 */ |
592a252b L |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9112 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9113 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9114 | /* 70 */ |
592d1631 L |
9115 | { Bad_Opcode }, |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
9121 | { Bad_Opcode }, | |
9122 | { Bad_Opcode }, | |
c0f3af97 | 9123 | /* 78 */ |
592a252b L |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9130 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9131 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9132 | /* 80 */ |
592d1631 L |
9133 | { Bad_Opcode }, |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
9139 | { Bad_Opcode }, | |
9140 | { Bad_Opcode }, | |
c0f3af97 | 9141 | /* 88 */ |
592d1631 L |
9142 | { Bad_Opcode }, |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
9148 | { Bad_Opcode }, | |
9149 | { Bad_Opcode }, | |
c0f3af97 | 9150 | /* 90 */ |
592d1631 L |
9151 | { Bad_Opcode }, |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
9157 | { Bad_Opcode }, | |
9158 | { Bad_Opcode }, | |
c0f3af97 | 9159 | /* 98 */ |
592d1631 L |
9160 | { Bad_Opcode }, |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
9166 | { Bad_Opcode }, | |
9167 | { Bad_Opcode }, | |
c0f3af97 | 9168 | /* a0 */ |
592d1631 L |
9169 | { Bad_Opcode }, |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
9175 | { Bad_Opcode }, | |
9176 | { Bad_Opcode }, | |
c0f3af97 | 9177 | /* a8 */ |
592d1631 L |
9178 | { Bad_Opcode }, |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
9184 | { Bad_Opcode }, | |
9185 | { Bad_Opcode }, | |
c0f3af97 | 9186 | /* b0 */ |
592d1631 L |
9187 | { Bad_Opcode }, |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
9193 | { Bad_Opcode }, | |
9194 | { Bad_Opcode }, | |
c0f3af97 | 9195 | /* b8 */ |
592d1631 L |
9196 | { Bad_Opcode }, |
9197 | { Bad_Opcode }, | |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
9202 | { Bad_Opcode }, | |
9203 | { Bad_Opcode }, | |
c0f3af97 | 9204 | /* c0 */ |
592d1631 L |
9205 | { Bad_Opcode }, |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
9211 | { Bad_Opcode }, | |
9212 | { Bad_Opcode }, | |
c0f3af97 | 9213 | /* c8 */ |
592d1631 L |
9214 | { Bad_Opcode }, |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
9218 | { Bad_Opcode }, | |
9219 | { Bad_Opcode }, | |
48521003 IT |
9220 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9221 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9222 | /* d0 */ |
592d1631 L |
9223 | { Bad_Opcode }, |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
9229 | { Bad_Opcode }, | |
9230 | { Bad_Opcode }, | |
c0f3af97 | 9231 | /* d8 */ |
592d1631 L |
9232 | { Bad_Opcode }, |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
9237 | { Bad_Opcode }, | |
9238 | { Bad_Opcode }, | |
592a252b | 9239 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9240 | /* e0 */ |
592d1631 L |
9241 | { Bad_Opcode }, |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
9247 | { Bad_Opcode }, | |
9248 | { Bad_Opcode }, | |
c0f3af97 | 9249 | /* e8 */ |
592d1631 L |
9250 | { Bad_Opcode }, |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
9256 | { Bad_Opcode }, | |
9257 | { Bad_Opcode }, | |
c0f3af97 | 9258 | /* f0 */ |
6c30d220 | 9259 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9260 | { Bad_Opcode }, |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
9265 | { Bad_Opcode }, | |
9266 | { Bad_Opcode }, | |
c0f3af97 | 9267 | /* f8 */ |
592d1631 L |
9268 | { Bad_Opcode }, |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
9274 | { Bad_Opcode }, | |
9275 | { Bad_Opcode }, | |
c0f3af97 L |
9276 | }, |
9277 | }; | |
9278 | ||
43234a1e | 9279 | #include "i386-dis-evex.h" |
ad692897 | 9280 | |
c0f3af97 | 9281 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9282 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9283 | { |
18897deb | 9284 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9285 | }, |
9286 | ||
592a252b | 9287 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9288 | { |
ec6f095a | 9289 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9290 | }, |
9291 | ||
592a252b | 9292 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9293 | { |
bf926894 | 9294 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9295 | }, |
9296 | ||
18897deb | 9297 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9298 | { |
18897deb | 9299 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9300 | }, |
9301 | ||
592a252b | 9302 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9303 | { |
ec6f095a | 9304 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9305 | }, |
9306 | ||
592a252b | 9307 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9308 | { |
bf926894 | 9309 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9310 | }, |
9311 | ||
43234a1e L |
9312 | /* VEX_LEN_0F41_P_0 */ |
9313 | { | |
9314 | { Bad_Opcode }, | |
9315 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9316 | }, | |
1ba585e8 IT |
9317 | /* VEX_LEN_0F41_P_2 */ |
9318 | { | |
9319 | { Bad_Opcode }, | |
9320 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9321 | }, | |
43234a1e L |
9322 | /* VEX_LEN_0F42_P_0 */ |
9323 | { | |
9324 | { Bad_Opcode }, | |
9325 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9326 | }, | |
1ba585e8 IT |
9327 | /* VEX_LEN_0F42_P_2 */ |
9328 | { | |
9329 | { Bad_Opcode }, | |
9330 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9331 | }, | |
43234a1e L |
9332 | /* VEX_LEN_0F44_P_0 */ |
9333 | { | |
9334 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9335 | }, | |
1ba585e8 IT |
9336 | /* VEX_LEN_0F44_P_2 */ |
9337 | { | |
9338 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9339 | }, | |
43234a1e L |
9340 | /* VEX_LEN_0F45_P_0 */ |
9341 | { | |
9342 | { Bad_Opcode }, | |
9343 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9344 | }, | |
1ba585e8 IT |
9345 | /* VEX_LEN_0F45_P_2 */ |
9346 | { | |
9347 | { Bad_Opcode }, | |
9348 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9349 | }, | |
43234a1e L |
9350 | /* VEX_LEN_0F46_P_0 */ |
9351 | { | |
9352 | { Bad_Opcode }, | |
9353 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9354 | }, | |
1ba585e8 IT |
9355 | /* VEX_LEN_0F46_P_2 */ |
9356 | { | |
9357 | { Bad_Opcode }, | |
9358 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9359 | }, | |
43234a1e L |
9360 | /* VEX_LEN_0F47_P_0 */ |
9361 | { | |
9362 | { Bad_Opcode }, | |
9363 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9364 | }, | |
1ba585e8 IT |
9365 | /* VEX_LEN_0F47_P_2 */ |
9366 | { | |
9367 | { Bad_Opcode }, | |
9368 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9369 | }, | |
9370 | /* VEX_LEN_0F4A_P_0 */ | |
9371 | { | |
9372 | { Bad_Opcode }, | |
9373 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9374 | }, | |
9375 | /* VEX_LEN_0F4A_P_2 */ | |
9376 | { | |
9377 | { Bad_Opcode }, | |
9378 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9379 | }, | |
9380 | /* VEX_LEN_0F4B_P_0 */ | |
9381 | { | |
9382 | { Bad_Opcode }, | |
9383 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9384 | }, | |
43234a1e L |
9385 | /* VEX_LEN_0F4B_P_2 */ |
9386 | { | |
9387 | { Bad_Opcode }, | |
9388 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9389 | }, | |
9390 | ||
ec6f095a | 9391 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9392 | { |
ec6f095a | 9393 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9394 | }, |
9395 | ||
ec6f095a | 9396 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9397 | { |
ec6f095a L |
9398 | { "vzeroupper", { XX }, 0 }, |
9399 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9400 | }, |
9401 | ||
ec6f095a | 9402 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9403 | { |
ec6f095a | 9404 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
c0f3af97 L |
9405 | }, |
9406 | ||
ec6f095a | 9407 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9408 | { |
ec6f095a | 9409 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9410 | }, |
9411 | ||
ec6f095a | 9412 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9413 | { |
ec6f095a | 9414 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9415 | }, |
9416 | ||
ec6f095a | 9417 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9418 | { |
ec6f095a | 9419 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9420 | }, |
9421 | ||
ec6f095a | 9422 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9423 | { |
ec6f095a | 9424 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9425 | }, |
9426 | ||
ec6f095a | 9427 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9428 | { |
ec6f095a | 9429 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9430 | }, |
9431 | ||
ec6f095a | 9432 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9433 | { |
ec6f095a | 9434 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9435 | }, |
9436 | ||
ec6f095a | 9437 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9438 | { |
ec6f095a | 9439 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9440 | }, |
9441 | ||
ec6f095a | 9442 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9443 | { |
58a211d2 | 9444 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9445 | }, |
9446 | ||
ec6f095a | 9447 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9448 | { |
ec6f095a | 9449 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9450 | }, |
9451 | ||
ec6f095a | 9452 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9453 | { |
ec6f095a | 9454 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9455 | }, |
9456 | ||
ec6f095a | 9457 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9458 | { |
58a211d2 | 9459 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9460 | }, |
9461 | ||
ec6f095a | 9462 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9463 | { |
9464 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9465 | }, | |
9466 | ||
1ba585e8 IT |
9467 | /* VEX_LEN_0F98_P_2 */ |
9468 | { | |
9469 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9470 | }, | |
9471 | ||
9472 | /* VEX_LEN_0F99_P_0 */ | |
9473 | { | |
9474 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9475 | }, | |
9476 | ||
9477 | /* VEX_LEN_0F99_P_2 */ | |
9478 | { | |
9479 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9480 | }, | |
9481 | ||
6c30d220 | 9482 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9483 | { |
ec6f095a | 9484 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9485 | }, |
9486 | ||
6c30d220 | 9487 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9488 | { |
ec6f095a | 9489 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9490 | }, |
9491 | ||
6c30d220 | 9492 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9493 | { |
b50c9f31 | 9494 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9495 | }, |
9496 | ||
6c30d220 | 9497 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9498 | { |
b50c9f31 | 9499 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9500 | }, |
9501 | ||
6c30d220 | 9502 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9503 | { |
ec6f095a | 9504 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9505 | }, |
9506 | ||
6c30d220 | 9507 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9508 | { |
ec6f095a | 9509 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9510 | }, |
9511 | ||
6c30d220 | 9512 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9513 | { |
6c30d220 L |
9514 | { Bad_Opcode }, |
9515 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9516 | }, |
9517 | ||
6c30d220 | 9518 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9519 | { |
6c30d220 L |
9520 | { Bad_Opcode }, |
9521 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9522 | }, |
9523 | ||
6c30d220 | 9524 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9525 | { |
6c30d220 L |
9526 | { Bad_Opcode }, |
9527 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9528 | }, |
9529 | ||
6c30d220 | 9530 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9531 | { |
6c30d220 L |
9532 | { Bad_Opcode }, |
9533 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9534 | }, |
9535 | ||
592a252b | 9536 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9537 | { |
ec6f095a | 9538 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9539 | }, |
9540 | ||
6c30d220 L |
9541 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9542 | { | |
9543 | { Bad_Opcode }, | |
9544 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9545 | }, | |
9546 | ||
592a252b | 9547 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9548 | { |
ec6f095a | 9549 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9550 | }, |
9551 | ||
f12dc422 L |
9552 | /* VEX_LEN_0F38F2_P_0 */ |
9553 | { | |
bf890a93 | 9554 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9555 | }, |
9556 | ||
9557 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9558 | { | |
bf890a93 | 9559 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9560 | }, |
9561 | ||
9562 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9563 | { | |
bf890a93 | 9564 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9565 | }, |
9566 | ||
9567 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9568 | { | |
bf890a93 | 9569 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9570 | }, |
9571 | ||
6c30d220 L |
9572 | /* VEX_LEN_0F38F5_P_0 */ |
9573 | { | |
bf890a93 | 9574 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9575 | }, |
9576 | ||
9577 | /* VEX_LEN_0F38F5_P_1 */ | |
9578 | { | |
bf890a93 | 9579 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9580 | }, |
9581 | ||
9582 | /* VEX_LEN_0F38F5_P_3 */ | |
9583 | { | |
bf890a93 | 9584 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9585 | }, |
9586 | ||
9587 | /* VEX_LEN_0F38F6_P_3 */ | |
9588 | { | |
bf890a93 | 9589 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9590 | }, |
9591 | ||
f12dc422 L |
9592 | /* VEX_LEN_0F38F7_P_0 */ |
9593 | { | |
bf890a93 | 9594 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9595 | }, |
9596 | ||
6c30d220 L |
9597 | /* VEX_LEN_0F38F7_P_1 */ |
9598 | { | |
bf890a93 | 9599 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9600 | }, |
9601 | ||
9602 | /* VEX_LEN_0F38F7_P_2 */ | |
9603 | { | |
bf890a93 | 9604 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9605 | }, |
9606 | ||
9607 | /* VEX_LEN_0F38F7_P_3 */ | |
9608 | { | |
bf890a93 | 9609 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9610 | }, |
9611 | ||
9612 | /* VEX_LEN_0F3A00_P_2 */ | |
9613 | { | |
9614 | { Bad_Opcode }, | |
9615 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9616 | }, | |
9617 | ||
9618 | /* VEX_LEN_0F3A01_P_2 */ | |
9619 | { | |
9620 | { Bad_Opcode }, | |
9621 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9622 | }, | |
9623 | ||
592a252b | 9624 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9625 | { |
592d1631 | 9626 | { Bad_Opcode }, |
592a252b | 9627 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9628 | }, |
9629 | ||
592a252b | 9630 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9631 | { |
b50c9f31 | 9632 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9633 | }, |
9634 | ||
592a252b | 9635 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9636 | { |
b50c9f31 | 9637 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9638 | }, |
9639 | ||
592a252b | 9640 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9641 | { |
bf890a93 | 9642 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9643 | }, |
9644 | ||
592a252b | 9645 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9646 | { |
bf890a93 | 9647 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9648 | }, |
9649 | ||
592a252b | 9650 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9651 | { |
592d1631 | 9652 | { Bad_Opcode }, |
592a252b | 9653 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9654 | }, |
9655 | ||
592a252b | 9656 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9657 | { |
592d1631 | 9658 | { Bad_Opcode }, |
592a252b | 9659 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9660 | }, |
9661 | ||
592a252b | 9662 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9663 | { |
b50c9f31 | 9664 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9665 | }, |
9666 | ||
592a252b | 9667 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9668 | { |
ec6f095a | 9669 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9670 | }, |
9671 | ||
592a252b | 9672 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9673 | { |
bf890a93 | 9674 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9675 | }, |
9676 | ||
43234a1e L |
9677 | /* VEX_LEN_0F3A30_P_2 */ |
9678 | { | |
9679 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9680 | }, | |
9681 | ||
1ba585e8 IT |
9682 | /* VEX_LEN_0F3A31_P_2 */ |
9683 | { | |
9684 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9685 | }, | |
9686 | ||
43234a1e L |
9687 | /* VEX_LEN_0F3A32_P_2 */ |
9688 | { | |
9689 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9690 | }, | |
9691 | ||
1ba585e8 IT |
9692 | /* VEX_LEN_0F3A33_P_2 */ |
9693 | { | |
9694 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9695 | }, | |
9696 | ||
6c30d220 | 9697 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9698 | { |
6c30d220 L |
9699 | { Bad_Opcode }, |
9700 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9701 | }, |
9702 | ||
6c30d220 | 9703 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9704 | { |
6c30d220 L |
9705 | { Bad_Opcode }, |
9706 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9707 | }, | |
9708 | ||
9709 | /* VEX_LEN_0F3A41_P_2 */ | |
9710 | { | |
ec6f095a | 9711 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9712 | }, |
9713 | ||
6c30d220 | 9714 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9715 | { |
6c30d220 L |
9716 | { Bad_Opcode }, |
9717 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9718 | }, |
9719 | ||
592a252b | 9720 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9721 | { |
15c7c1d8 | 9722 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9723 | }, |
9724 | ||
592a252b | 9725 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9726 | { |
15c7c1d8 | 9727 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9728 | }, |
9729 | ||
592a252b | 9730 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9731 | { |
ec6f095a | 9732 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9733 | }, |
9734 | ||
592a252b | 9735 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9736 | { |
ec6f095a | 9737 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9738 | }, |
9739 | ||
592a252b | 9740 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9741 | { |
3a2430e0 | 9742 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9743 | }, |
9744 | ||
592a252b | 9745 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9746 | { |
3a2430e0 | 9747 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9748 | }, |
9749 | ||
592a252b | 9750 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9751 | { |
3a2430e0 | 9752 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9753 | }, |
9754 | ||
592a252b | 9755 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9756 | { |
3a2430e0 | 9757 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9758 | }, |
9759 | ||
592a252b | 9760 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9761 | { |
3a2430e0 | 9762 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9763 | }, |
9764 | ||
592a252b | 9765 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9766 | { |
3a2430e0 | 9767 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9768 | }, |
9769 | ||
592a252b | 9770 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9771 | { |
3a2430e0 | 9772 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9773 | }, |
9774 | ||
592a252b | 9775 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9776 | { |
3a2430e0 | 9777 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9778 | }, |
9779 | ||
592a252b | 9780 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9781 | { |
ec6f095a | 9782 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9783 | }, |
4c807e72 | 9784 | |
6c30d220 L |
9785 | /* VEX_LEN_0F3AF0_P_3 */ |
9786 | { | |
bf890a93 | 9787 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9788 | }, |
9789 | ||
ff688e1f L |
9790 | /* VEX_LEN_0FXOP_08_CC */ |
9791 | { | |
be92cb14 | 9792 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9793 | }, |
9794 | ||
9795 | /* VEX_LEN_0FXOP_08_CD */ | |
9796 | { | |
be92cb14 | 9797 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9798 | }, |
9799 | ||
9800 | /* VEX_LEN_0FXOP_08_CE */ | |
9801 | { | |
be92cb14 | 9802 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9803 | }, |
9804 | ||
9805 | /* VEX_LEN_0FXOP_08_CF */ | |
9806 | { | |
be92cb14 | 9807 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9808 | }, |
9809 | ||
9810 | /* VEX_LEN_0FXOP_08_EC */ | |
9811 | { | |
be92cb14 | 9812 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9813 | }, |
9814 | ||
9815 | /* VEX_LEN_0FXOP_08_ED */ | |
9816 | { | |
be92cb14 | 9817 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9818 | }, |
9819 | ||
9820 | /* VEX_LEN_0FXOP_08_EE */ | |
9821 | { | |
be92cb14 | 9822 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9823 | }, |
9824 | ||
9825 | /* VEX_LEN_0FXOP_08_EF */ | |
9826 | { | |
be92cb14 | 9827 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9828 | }, |
9829 | ||
592a252b | 9830 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9831 | { |
bf890a93 IT |
9832 | { "vfrczps", { XM, EXxmm }, 0 }, |
9833 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9834 | }, |
4c807e72 | 9835 | |
592a252b | 9836 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9837 | { |
bf890a93 IT |
9838 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9839 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9840 | }, |
331d2d0d L |
9841 | }; |
9842 | ||
ad692897 | 9843 | #include "i386-dis-evex-len.h" |
04e2a182 | 9844 | |
9e30b8e0 | 9845 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9846 | { |
9847 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9848 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9849 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9850 | }, |
9851 | { | |
9852 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9853 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9854 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9855 | }, |
9856 | { | |
9857 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9858 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9859 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9860 | }, |
9861 | { | |
9862 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9863 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9864 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9865 | }, |
9866 | { | |
9867 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9868 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9869 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9870 | }, |
9871 | { | |
9872 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9873 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9874 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9875 | }, |
9876 | { | |
ec6f095a L |
9877 | /* VEX_W_0F45_P_0_LEN_1 */ |
9878 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9879 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9880 | }, |
9881 | { | |
ec6f095a L |
9882 | /* VEX_W_0F45_P_2_LEN_1 */ |
9883 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9884 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9885 | }, |
9886 | { | |
ec6f095a L |
9887 | /* VEX_W_0F46_P_0_LEN_1 */ |
9888 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9889 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9890 | }, |
9891 | { | |
ec6f095a L |
9892 | /* VEX_W_0F46_P_2_LEN_1 */ |
9893 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9894 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9895 | }, |
9896 | { | |
ec6f095a L |
9897 | /* VEX_W_0F47_P_0_LEN_1 */ |
9898 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9899 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9900 | }, |
9901 | { | |
ec6f095a L |
9902 | /* VEX_W_0F47_P_2_LEN_1 */ |
9903 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9904 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9905 | }, |
9906 | { | |
ec6f095a L |
9907 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9908 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9909 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9910 | }, |
9911 | { | |
ec6f095a L |
9912 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9913 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9914 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9915 | }, |
9916 | { | |
ec6f095a L |
9917 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9918 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9919 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9920 | }, |
9921 | { | |
ec6f095a L |
9922 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9923 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9924 | }, |
9925 | { | |
ec6f095a L |
9926 | /* VEX_W_0F90_P_0_LEN_0 */ |
9927 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9928 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9929 | }, |
9930 | { | |
ec6f095a L |
9931 | /* VEX_W_0F90_P_2_LEN_0 */ |
9932 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9933 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9934 | }, |
9935 | { | |
ec6f095a L |
9936 | /* VEX_W_0F91_P_0_LEN_0 */ |
9937 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9938 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9939 | }, |
9940 | { | |
ec6f095a L |
9941 | /* VEX_W_0F91_P_2_LEN_0 */ |
9942 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9943 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9944 | }, |
9945 | { | |
ec6f095a L |
9946 | /* VEX_W_0F92_P_0_LEN_0 */ |
9947 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9948 | }, |
9949 | { | |
ec6f095a L |
9950 | /* VEX_W_0F92_P_2_LEN_0 */ |
9951 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9952 | }, |
9e30b8e0 | 9953 | { |
ec6f095a L |
9954 | /* VEX_W_0F93_P_0_LEN_0 */ |
9955 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9956 | }, |
9957 | { | |
ec6f095a L |
9958 | /* VEX_W_0F93_P_2_LEN_0 */ |
9959 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 9960 | }, |
9e30b8e0 | 9961 | { |
ec6f095a L |
9962 | /* VEX_W_0F98_P_0_LEN_0 */ |
9963 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
9964 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
9965 | }, |
9966 | { | |
ec6f095a L |
9967 | /* VEX_W_0F98_P_2_LEN_0 */ |
9968 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
9969 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
9970 | }, |
9971 | { | |
ec6f095a L |
9972 | /* VEX_W_0F99_P_0_LEN_0 */ |
9973 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
9974 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
9975 | }, |
9976 | { | |
ec6f095a L |
9977 | /* VEX_W_0F99_P_2_LEN_0 */ |
9978 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
9979 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 9980 | }, |
9e30b8e0 | 9981 | { |
592a252b | 9982 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 9983 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9984 | }, |
9985 | { | |
592a252b | 9986 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 9987 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9988 | }, |
9989 | { | |
592a252b | 9990 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 9991 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
9992 | }, |
9993 | { | |
592a252b | 9994 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 9995 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 9996 | }, |
6c30d220 L |
9997 | { |
9998 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 9999 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10000 | }, |
bcf2684f | 10001 | { |
6c30d220 | 10002 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10003 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10004 | }, |
9e30b8e0 | 10005 | { |
6c30d220 | 10006 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10007 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10008 | }, |
10009 | { | |
592a252b | 10010 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10011 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10012 | }, |
53aa04a0 | 10013 | { |
592a252b | 10014 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10015 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10016 | }, |
10017 | { | |
592a252b | 10018 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10019 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10020 | }, |
10021 | { | |
592a252b | 10022 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10023 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10024 | }, |
10025 | { | |
592a252b | 10026 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10027 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10028 | }, |
6c30d220 L |
10029 | { |
10030 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10031 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10032 | }, |
6c30d220 L |
10033 | { |
10034 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10035 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
10036 | }, |
10037 | { | |
10038 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10039 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10040 | }, |
10041 | { | |
10042 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10043 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10044 | }, |
10045 | { | |
10046 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10047 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
10048 | }, |
10049 | { | |
10050 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10051 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10052 | }, |
10053 | { | |
10054 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10055 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10056 | }, |
48521003 IT |
10057 | { |
10058 | /* VEX_W_0F38CF_P_2 */ | |
10059 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10060 | }, | |
6c30d220 L |
10061 | { |
10062 | /* VEX_W_0F3A00_P_2 */ | |
10063 | { Bad_Opcode }, | |
bf890a93 | 10064 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10065 | }, |
10066 | { | |
10067 | /* VEX_W_0F3A01_P_2 */ | |
10068 | { Bad_Opcode }, | |
bf890a93 | 10069 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10070 | }, |
10071 | { | |
10072 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10073 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10074 | }, |
9e30b8e0 | 10075 | { |
592a252b | 10076 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10077 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10078 | }, |
10079 | { | |
592a252b | 10080 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10081 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10082 | }, |
10083 | { | |
592a252b | 10084 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10085 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10086 | }, |
9e30b8e0 | 10087 | { |
592a252b | 10088 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10089 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10090 | }, |
10091 | { | |
592a252b | 10092 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10093 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10094 | }, |
43234a1e | 10095 | { |
1ba585e8 | 10096 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10097 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10098 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10099 | }, |
10100 | { | |
1ba585e8 | 10101 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10102 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10103 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10104 | }, |
10105 | { | |
10106 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10107 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10108 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10109 | }, |
1ba585e8 IT |
10110 | { |
10111 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10112 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10113 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10114 | }, |
6c30d220 L |
10115 | { |
10116 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10117 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10118 | }, |
10119 | { | |
10120 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10121 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10122 | }, |
6c30d220 L |
10123 | { |
10124 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10125 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10126 | }, |
a683cc34 | 10127 | { |
592a252b | 10128 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10129 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10130 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10131 | }, |
10132 | { | |
592a252b | 10133 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10134 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10135 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10136 | }, |
9e30b8e0 | 10137 | { |
592a252b | 10138 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10139 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10140 | }, |
10141 | { | |
592a252b | 10142 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10143 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10144 | }, |
10145 | { | |
592a252b | 10146 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10147 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10148 | }, |
48521003 IT |
10149 | { |
10150 | /* VEX_W_0F3ACE_P_2 */ | |
10151 | { Bad_Opcode }, | |
10152 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10153 | }, | |
10154 | { | |
10155 | /* VEX_W_0F3ACF_P_2 */ | |
10156 | { Bad_Opcode }, | |
10157 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10158 | }, | |
ad692897 L |
10159 | |
10160 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10161 | }; |
10162 | ||
10163 | static const struct dis386 mod_table[][2] = { | |
10164 | { | |
10165 | /* MOD_8D */ | |
bf890a93 | 10166 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10167 | }, |
42164a71 L |
10168 | { |
10169 | /* MOD_C6_REG_7 */ | |
10170 | { Bad_Opcode }, | |
10171 | { RM_TABLE (RM_C6_REG_7) }, | |
10172 | }, | |
10173 | { | |
10174 | /* MOD_C7_REG_7 */ | |
10175 | { Bad_Opcode }, | |
10176 | { RM_TABLE (RM_C7_REG_7) }, | |
10177 | }, | |
4a357820 MZ |
10178 | { |
10179 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 10180 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
10181 | }, |
10182 | { | |
10183 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 10184 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 10185 | }, |
9e30b8e0 L |
10186 | { |
10187 | /* MOD_0F01_REG_0 */ | |
10188 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10189 | { RM_TABLE (RM_0F01_REG_0) }, | |
10190 | }, | |
10191 | { | |
10192 | /* MOD_0F01_REG_1 */ | |
10193 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10194 | { RM_TABLE (RM_0F01_REG_1) }, | |
10195 | }, | |
10196 | { | |
10197 | /* MOD_0F01_REG_2 */ | |
10198 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10199 | { RM_TABLE (RM_0F01_REG_2) }, | |
10200 | }, | |
10201 | { | |
10202 | /* MOD_0F01_REG_3 */ | |
10203 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10204 | { RM_TABLE (RM_0F01_REG_3) }, | |
10205 | }, | |
8eab4136 L |
10206 | { |
10207 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10208 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10209 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10210 | }, |
9e30b8e0 L |
10211 | { |
10212 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10213 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10214 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10215 | }, |
10216 | { | |
10217 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10218 | { "movlpX", { XM, EXq }, 0 }, |
10219 | { "movhlps", { XM, EXq }, 0 }, | |
10220 | }, | |
10221 | { | |
10222 | /* MOD_0F12_PREFIX_2 */ | |
10223 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10224 | }, |
10225 | { | |
10226 | /* MOD_0F13 */ | |
507bd325 | 10227 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10228 | }, |
10229 | { | |
10230 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10231 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10232 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10233 | }, |
18897deb JB |
10234 | { |
10235 | /* MOD_0F16_PREFIX_2 */ | |
10236 | { "movhpX", { XM, EXq }, 0 }, | |
10237 | }, | |
9e30b8e0 L |
10238 | { |
10239 | /* MOD_0F17 */ | |
507bd325 | 10240 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10241 | }, |
10242 | { | |
10243 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10244 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10245 | }, |
10246 | { | |
10247 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10248 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10249 | }, |
10250 | { | |
10251 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10252 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10253 | }, |
10254 | { | |
10255 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10256 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10257 | }, |
d7189fa5 RM |
10258 | { |
10259 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10260 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10261 | }, |
10262 | { | |
10263 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10264 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10265 | }, |
10266 | { | |
10267 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10268 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10269 | }, |
10270 | { | |
10271 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10272 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10273 | }, |
7e8b059b L |
10274 | { |
10275 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10276 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10277 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10278 | }, |
10279 | { | |
10280 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10281 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10282 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10283 | }, |
10284 | { | |
10285 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10286 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10287 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10288 | }, |
c48935d7 IT |
10289 | { |
10290 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10291 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10292 | { "nopQ", { Ev }, 0 }, |
10293 | }, | |
603555e5 L |
10294 | { |
10295 | /* MOD_0F1E_PREFIX_1 */ | |
10296 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10297 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10298 | }, |
b844680a | 10299 | { |
92fddf8e | 10300 | /* MOD_0F24 */ |
7bb15c6f | 10301 | { Bad_Opcode }, |
bf890a93 | 10302 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10303 | }, |
10304 | { | |
92fddf8e | 10305 | /* MOD_0F26 */ |
592d1631 | 10306 | { Bad_Opcode }, |
bf890a93 | 10307 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10308 | }, |
75c135a8 L |
10309 | { |
10310 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10311 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10312 | }, |
10313 | { | |
10314 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10315 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10316 | }, |
10317 | { | |
10318 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10319 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10320 | }, |
10321 | { | |
10322 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10323 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10324 | }, |
10325 | { | |
a5aaedb9 | 10326 | /* MOD_0F50 */ |
592d1631 | 10327 | { Bad_Opcode }, |
507bd325 | 10328 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10329 | }, |
b844680a | 10330 | { |
1ceb70f8 | 10331 | /* MOD_0F71_REG_2 */ |
592d1631 | 10332 | { Bad_Opcode }, |
bf890a93 | 10333 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10334 | }, |
10335 | { | |
1ceb70f8 | 10336 | /* MOD_0F71_REG_4 */ |
592d1631 | 10337 | { Bad_Opcode }, |
bf890a93 | 10338 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10339 | }, |
10340 | { | |
1ceb70f8 | 10341 | /* MOD_0F71_REG_6 */ |
592d1631 | 10342 | { Bad_Opcode }, |
bf890a93 | 10343 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10344 | }, |
10345 | { | |
1ceb70f8 | 10346 | /* MOD_0F72_REG_2 */ |
592d1631 | 10347 | { Bad_Opcode }, |
bf890a93 | 10348 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10349 | }, |
10350 | { | |
1ceb70f8 | 10351 | /* MOD_0F72_REG_4 */ |
592d1631 | 10352 | { Bad_Opcode }, |
bf890a93 | 10353 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10354 | }, |
10355 | { | |
1ceb70f8 | 10356 | /* MOD_0F72_REG_6 */ |
592d1631 | 10357 | { Bad_Opcode }, |
bf890a93 | 10358 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10359 | }, |
10360 | { | |
1ceb70f8 | 10361 | /* MOD_0F73_REG_2 */ |
592d1631 | 10362 | { Bad_Opcode }, |
bf890a93 | 10363 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10364 | }, |
10365 | { | |
1ceb70f8 | 10366 | /* MOD_0F73_REG_3 */ |
592d1631 | 10367 | { Bad_Opcode }, |
c0f3af97 L |
10368 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10369 | }, | |
10370 | { | |
10371 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10372 | { Bad_Opcode }, |
bf890a93 | 10373 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10374 | }, |
10375 | { | |
10376 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10377 | { Bad_Opcode }, |
c0f3af97 L |
10378 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10379 | }, | |
10380 | { | |
10381 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10382 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10383 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10384 | }, |
10385 | { | |
10386 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10387 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10388 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10389 | }, |
10390 | { | |
10391 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10392 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10393 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10394 | }, |
10395 | { | |
10396 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10397 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10398 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10399 | }, |
10400 | { | |
10401 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10402 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10403 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10404 | }, |
10405 | { | |
10406 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10407 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10408 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10409 | }, |
10410 | { | |
10411 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10412 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10413 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10414 | }, |
10415 | { | |
10416 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10417 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10418 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10419 | }, |
10420 | { | |
10421 | /* MOD_0FB2 */ | |
bf890a93 | 10422 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10423 | }, |
10424 | { | |
10425 | /* MOD_0FB4 */ | |
bf890a93 | 10426 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10427 | }, |
10428 | { | |
10429 | /* MOD_0FB5 */ | |
bf890a93 | 10430 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10431 | }, |
a8484f96 L |
10432 | { |
10433 | /* MOD_0FC3 */ | |
f8687e93 | 10434 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10435 | }, |
963f3586 IT |
10436 | { |
10437 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10438 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10439 | }, |
10440 | { | |
10441 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10442 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10443 | }, |
10444 | { | |
10445 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10446 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10447 | }, |
c0f3af97 L |
10448 | { |
10449 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10450 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10451 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10452 | }, |
10453 | { | |
10454 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10455 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10456 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10457 | }, |
10458 | { | |
10459 | /* MOD_0FD7 */ | |
592d1631 | 10460 | { Bad_Opcode }, |
bf890a93 | 10461 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10462 | }, |
10463 | { | |
10464 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10465 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10466 | }, |
10467 | { | |
10468 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10469 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10470 | }, |
10471 | { | |
10472 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10473 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10474 | }, |
603555e5 L |
10475 | { |
10476 | /* MOD_0F38F5_PREFIX_2 */ | |
10477 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10478 | }, | |
10479 | { | |
10480 | /* MOD_0F38F6_PREFIX_0 */ | |
10481 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10482 | }, | |
5d79adc4 L |
10483 | { |
10484 | /* MOD_0F38F8_PREFIX_1 */ | |
10485 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10486 | }, | |
c0a30a9f L |
10487 | { |
10488 | /* MOD_0F38F8_PREFIX_2 */ | |
10489 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10490 | }, | |
5d79adc4 L |
10491 | { |
10492 | /* MOD_0F38F8_PREFIX_3 */ | |
10493 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10494 | }, | |
c0a30a9f L |
10495 | { |
10496 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10497 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10498 | }, |
c0f3af97 L |
10499 | { |
10500 | /* MOD_62_32BIT */ | |
bf890a93 | 10501 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10502 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10503 | }, |
10504 | { | |
10505 | /* MOD_C4_32BIT */ | |
bf890a93 | 10506 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10507 | { VEX_C4_TABLE (VEX_0F) }, |
10508 | }, | |
10509 | { | |
10510 | /* MOD_C5_32BIT */ | |
bf890a93 | 10511 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10512 | { VEX_C5_TABLE (VEX_0F) }, |
10513 | }, | |
10514 | { | |
592a252b L |
10515 | /* MOD_VEX_0F12_PREFIX_0 */ |
10516 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10517 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 10518 | }, |
18897deb JB |
10519 | { |
10520 | /* MOD_VEX_0F12_PREFIX_2 */ | |
10521 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
10522 | }, | |
c0f3af97 | 10523 | { |
592a252b L |
10524 | /* MOD_VEX_0F13 */ |
10525 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10526 | }, |
10527 | { | |
592a252b L |
10528 | /* MOD_VEX_0F16_PREFIX_0 */ |
10529 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10530 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 10531 | }, |
18897deb JB |
10532 | { |
10533 | /* MOD_VEX_0F16_PREFIX_2 */ | |
10534 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
10535 | }, | |
c0f3af97 | 10536 | { |
592a252b L |
10537 | /* MOD_VEX_0F17 */ |
10538 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10539 | }, |
10540 | { | |
592a252b | 10541 | /* MOD_VEX_0F2B */ |
bf926894 | 10542 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 10543 | }, |
ab4e4ed5 AF |
10544 | { |
10545 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10546 | { Bad_Opcode }, | |
10547 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10548 | }, | |
10549 | { | |
10550 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10551 | { Bad_Opcode }, | |
10552 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10553 | }, | |
10554 | { | |
10555 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10556 | { Bad_Opcode }, | |
10557 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10558 | }, | |
10559 | { | |
10560 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10561 | { Bad_Opcode }, | |
10562 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10563 | }, | |
10564 | { | |
10565 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10566 | { Bad_Opcode }, | |
10567 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10568 | }, | |
10569 | { | |
10570 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10571 | { Bad_Opcode }, | |
10572 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10573 | }, | |
10574 | { | |
10575 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10576 | { Bad_Opcode }, | |
10577 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10578 | }, | |
10579 | { | |
10580 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10581 | { Bad_Opcode }, | |
10582 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10583 | }, | |
10584 | { | |
10585 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10586 | { Bad_Opcode }, | |
10587 | { "knotw", { MaskG, MaskR }, 0 }, | |
10588 | }, | |
10589 | { | |
10590 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10591 | { Bad_Opcode }, | |
10592 | { "knotq", { MaskG, MaskR }, 0 }, | |
10593 | }, | |
10594 | { | |
10595 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10596 | { Bad_Opcode }, | |
10597 | { "knotb", { MaskG, MaskR }, 0 }, | |
10598 | }, | |
10599 | { | |
10600 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10601 | { Bad_Opcode }, | |
10602 | { "knotd", { MaskG, MaskR }, 0 }, | |
10603 | }, | |
10604 | { | |
10605 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10606 | { Bad_Opcode }, | |
10607 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10608 | }, | |
10609 | { | |
10610 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10611 | { Bad_Opcode }, | |
10612 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10613 | }, | |
10614 | { | |
10615 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10616 | { Bad_Opcode }, | |
10617 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10618 | }, | |
10619 | { | |
10620 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10621 | { Bad_Opcode }, | |
10622 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10623 | }, | |
10624 | { | |
10625 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10626 | { Bad_Opcode }, | |
10627 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10628 | }, | |
10629 | { | |
10630 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10631 | { Bad_Opcode }, | |
10632 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10633 | }, | |
10634 | { | |
10635 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10636 | { Bad_Opcode }, | |
10637 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10638 | }, | |
10639 | { | |
10640 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10641 | { Bad_Opcode }, | |
10642 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10643 | }, | |
10644 | { | |
10645 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10646 | { Bad_Opcode }, | |
10647 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10648 | }, | |
10649 | { | |
10650 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10651 | { Bad_Opcode }, | |
10652 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10653 | }, | |
10654 | { | |
10655 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10656 | { Bad_Opcode }, | |
10657 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10658 | }, | |
10659 | { | |
10660 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10661 | { Bad_Opcode }, | |
10662 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10663 | }, | |
10664 | { | |
10665 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10666 | { Bad_Opcode }, | |
10667 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10668 | }, | |
10669 | { | |
10670 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10671 | { Bad_Opcode }, | |
10672 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10673 | }, | |
10674 | { | |
10675 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10676 | { Bad_Opcode }, | |
10677 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10678 | }, | |
10679 | { | |
10680 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10681 | { Bad_Opcode }, | |
10682 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10683 | }, | |
10684 | { | |
10685 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10686 | { Bad_Opcode }, | |
10687 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10688 | }, | |
10689 | { | |
10690 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10691 | { Bad_Opcode }, | |
10692 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10693 | }, | |
10694 | { | |
10695 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10696 | { Bad_Opcode }, | |
10697 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10698 | }, | |
c0f3af97 | 10699 | { |
592a252b | 10700 | /* MOD_VEX_0F50 */ |
592d1631 | 10701 | { Bad_Opcode }, |
bf926894 | 10702 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
10703 | }, |
10704 | { | |
592a252b | 10705 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10706 | { Bad_Opcode }, |
592a252b | 10707 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10708 | }, |
10709 | { | |
592a252b | 10710 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10711 | { Bad_Opcode }, |
592a252b | 10712 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10713 | }, |
10714 | { | |
592a252b | 10715 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10716 | { Bad_Opcode }, |
592a252b | 10717 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10718 | }, |
10719 | { | |
592a252b | 10720 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10721 | { Bad_Opcode }, |
592a252b | 10722 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10723 | }, |
d8faab4e | 10724 | { |
592a252b | 10725 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10726 | { Bad_Opcode }, |
592a252b | 10727 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10728 | }, |
10729 | { | |
592a252b | 10730 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10731 | { Bad_Opcode }, |
592a252b | 10732 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10733 | }, |
876d4bfa | 10734 | { |
592a252b | 10735 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10736 | { Bad_Opcode }, |
592a252b | 10737 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10738 | }, |
10739 | { | |
592a252b | 10740 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10741 | { Bad_Opcode }, |
592a252b | 10742 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10743 | }, |
10744 | { | |
592a252b | 10745 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10746 | { Bad_Opcode }, |
592a252b | 10747 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10748 | }, |
10749 | { | |
592a252b | 10750 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10751 | { Bad_Opcode }, |
592a252b | 10752 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10753 | }, |
ab4e4ed5 AF |
10754 | { |
10755 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10756 | { "kmovw", { Ew, MaskG }, 0 }, | |
10757 | { Bad_Opcode }, | |
10758 | }, | |
10759 | { | |
10760 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10761 | { "kmovq", { Eq, MaskG }, 0 }, | |
10762 | { Bad_Opcode }, | |
10763 | }, | |
10764 | { | |
10765 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10766 | { "kmovb", { Eb, MaskG }, 0 }, | |
10767 | { Bad_Opcode }, | |
10768 | }, | |
10769 | { | |
10770 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10771 | { "kmovd", { Ed, MaskG }, 0 }, | |
10772 | { Bad_Opcode }, | |
10773 | }, | |
10774 | { | |
10775 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10776 | { Bad_Opcode }, | |
10777 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10778 | }, | |
10779 | { | |
10780 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10781 | { Bad_Opcode }, | |
10782 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10783 | }, | |
10784 | { | |
58a211d2 | 10785 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10786 | { Bad_Opcode }, |
58a211d2 | 10787 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10788 | }, |
10789 | { | |
10790 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10791 | { Bad_Opcode }, | |
10792 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10793 | }, | |
10794 | { | |
10795 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10796 | { Bad_Opcode }, | |
10797 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10798 | }, | |
10799 | { | |
58a211d2 | 10800 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10801 | { Bad_Opcode }, |
58a211d2 | 10802 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10803 | }, |
10804 | { | |
10805 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10806 | { Bad_Opcode }, | |
10807 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10808 | }, | |
10809 | { | |
10810 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10811 | { Bad_Opcode }, | |
10812 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10813 | }, | |
10814 | { | |
10815 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10816 | { Bad_Opcode }, | |
10817 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10818 | }, | |
10819 | { | |
10820 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10821 | { Bad_Opcode }, | |
10822 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10823 | }, | |
10824 | { | |
10825 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10826 | { Bad_Opcode }, | |
10827 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10828 | }, | |
10829 | { | |
10830 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10831 | { Bad_Opcode }, | |
10832 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10833 | }, | |
10834 | { | |
10835 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10836 | { Bad_Opcode }, | |
10837 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10838 | }, | |
10839 | { | |
10840 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10841 | { Bad_Opcode }, | |
10842 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10843 | }, | |
876d4bfa | 10844 | { |
592a252b L |
10845 | /* MOD_VEX_0FAE_REG_2 */ |
10846 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10847 | }, |
bbedc832 | 10848 | { |
592a252b L |
10849 | /* MOD_VEX_0FAE_REG_3 */ |
10850 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10851 | }, |
144c41d9 | 10852 | { |
592a252b | 10853 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10854 | { Bad_Opcode }, |
ec6f095a | 10855 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10856 | }, |
1afd85e3 | 10857 | { |
592a252b | 10858 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10859 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10860 | }, |
10861 | { | |
592a252b | 10862 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10863 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10864 | }, |
75c135a8 | 10865 | { |
592a252b L |
10866 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10867 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10868 | }, |
1afd85e3 | 10869 | { |
592a252b | 10870 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10871 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10872 | }, |
75c135a8 | 10873 | { |
592a252b L |
10874 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10875 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10876 | }, |
1afd85e3 | 10877 | { |
592a252b L |
10878 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10879 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10880 | }, |
10881 | { | |
592a252b L |
10882 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10883 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10884 | }, |
10885 | { | |
592a252b L |
10886 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10887 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10888 | }, |
6c30d220 L |
10889 | { |
10890 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10891 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10892 | }, | |
10893 | { | |
10894 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10895 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10896 | }, |
10897 | { | |
10898 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10899 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10900 | }, |
ab4e4ed5 AF |
10901 | { |
10902 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10903 | { Bad_Opcode }, | |
10904 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10905 | }, | |
10906 | { | |
10907 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10908 | { Bad_Opcode }, | |
10909 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10910 | }, | |
10911 | { | |
10912 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10913 | { Bad_Opcode }, | |
10914 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10915 | }, | |
10916 | { | |
10917 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10918 | { Bad_Opcode }, | |
10919 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10920 | }, | |
10921 | { | |
10922 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10923 | { Bad_Opcode }, | |
10924 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10925 | }, | |
10926 | { | |
10927 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10928 | { Bad_Opcode }, | |
10929 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10930 | }, | |
10931 | { | |
10932 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10933 | { Bad_Opcode }, | |
10934 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10935 | }, | |
10936 | { | |
10937 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10938 | { Bad_Opcode }, | |
10939 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10940 | }, | |
ad692897 L |
10941 | |
10942 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10943 | }; |
10944 | ||
1ceb70f8 | 10945 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10946 | { |
10947 | /* RM_C6_REG_7 */ | |
bf890a93 | 10948 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10949 | }, |
10950 | { | |
10951 | /* RM_C7_REG_7 */ | |
376cd056 | 10952 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10953 | }, |
b844680a | 10954 | { |
1ceb70f8 | 10955 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10956 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10957 | { "vmcall", { Skip_MODRM }, 0 }, |
10958 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10959 | { "vmresume", { Skip_MODRM }, 0 }, | |
10960 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10961 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10962 | }, |
10963 | { | |
1ceb70f8 | 10964 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10965 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10966 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10967 | { "clac", { Skip_MODRM }, 0 }, | |
10968 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10969 | { Bad_Opcode }, |
10970 | { Bad_Opcode }, | |
10971 | { Bad_Opcode }, | |
bf890a93 | 10972 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10973 | }, |
475a2301 L |
10974 | { |
10975 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
10976 | { "xgetbv", { Skip_MODRM }, 0 }, |
10977 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
10978 | { Bad_Opcode }, |
10979 | { Bad_Opcode }, | |
bf890a93 IT |
10980 | { "vmfunc", { Skip_MODRM }, 0 }, |
10981 | { "xend", { Skip_MODRM }, 0 }, | |
10982 | { "xtest", { Skip_MODRM }, 0 }, | |
10983 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 10984 | }, |
b844680a | 10985 | { |
1ceb70f8 | 10986 | /* RM_0F01_REG_3 */ |
bf890a93 | 10987 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 10988 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
10989 | { "vmload", { Skip_MODRM }, 0 }, |
10990 | { "vmsave", { Skip_MODRM }, 0 }, | |
10991 | { "stgi", { Skip_MODRM }, 0 }, | |
10992 | { "clgi", { Skip_MODRM }, 0 }, | |
10993 | { "skinit", { Skip_MODRM }, 0 }, | |
10994 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 10995 | }, |
8eab4136 | 10996 | { |
f8687e93 JB |
10997 | /* RM_0F01_REG_5_MOD_3 */ |
10998 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 10999 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 11000 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
11001 | { Bad_Opcode }, |
11002 | { Bad_Opcode }, | |
11003 | { Bad_Opcode }, | |
11004 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11005 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11006 | }, | |
4e7d34a6 | 11007 | { |
f8687e93 | 11008 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
11009 | { "swapgs", { Skip_MODRM }, 0 }, |
11010 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
11011 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
11012 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 11013 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 11014 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 11015 | }, |
603555e5 | 11016 | { |
f8687e93 | 11017 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
11018 | { "nopQ", { Ev }, 0 }, |
11019 | { "nopQ", { Ev }, 0 }, | |
11020 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11021 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11022 | { "nopQ", { Ev }, 0 }, | |
11023 | { "nopQ", { Ev }, 0 }, | |
11024 | { "nopQ", { Ev }, 0 }, | |
11025 | { "nopQ", { Ev }, 0 }, | |
11026 | }, | |
b844680a | 11027 | { |
f8687e93 | 11028 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 11029 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11030 | }, |
bbedc832 | 11031 | { |
f8687e93 | 11032 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
11033 | { "sfence", { Skip_MODRM }, 0 }, |
11034 | ||
144c41d9 | 11035 | }, |
b844680a L |
11036 | }; |
11037 | ||
c608c12e AM |
11038 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11039 | ||
f16cd0d5 L |
11040 | /* We use the high bit to indicate different name for the same |
11041 | prefix. */ | |
f16cd0d5 | 11042 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11043 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11044 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11045 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11046 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 11047 | |
1d67fe3b TT |
11048 | /* Remember if the current op is a jump instruction. */ |
11049 | static bfd_boolean op_is_jump = FALSE; | |
11050 | ||
f16cd0d5 | 11051 | static int |
26ca5450 | 11052 | ckprefix (void) |
252b5132 | 11053 | { |
f16cd0d5 | 11054 | int newrex, i, length; |
52b15da3 | 11055 | rex = 0; |
252b5132 | 11056 | prefixes = 0; |
7d421014 | 11057 | used_prefixes = 0; |
52b15da3 | 11058 | rex_used = 0; |
f16cd0d5 L |
11059 | last_lock_prefix = -1; |
11060 | last_repz_prefix = -1; | |
11061 | last_repnz_prefix = -1; | |
11062 | last_data_prefix = -1; | |
11063 | last_addr_prefix = -1; | |
11064 | last_rex_prefix = -1; | |
11065 | last_seg_prefix = -1; | |
d9949a36 | 11066 | fwait_prefix = -1; |
285ca992 | 11067 | active_seg_prefix = 0; |
f310f33d L |
11068 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11069 | all_prefixes[i] = 0; | |
11070 | i = 0; | |
f16cd0d5 L |
11071 | length = 0; |
11072 | /* The maximum instruction length is 15bytes. */ | |
11073 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11074 | { |
11075 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11076 | newrex = 0; |
252b5132 RH |
11077 | switch (*codep) |
11078 | { | |
52b15da3 JH |
11079 | /* REX prefixes family. */ |
11080 | case 0x40: | |
11081 | case 0x41: | |
11082 | case 0x42: | |
11083 | case 0x43: | |
11084 | case 0x44: | |
11085 | case 0x45: | |
11086 | case 0x46: | |
11087 | case 0x47: | |
11088 | case 0x48: | |
11089 | case 0x49: | |
11090 | case 0x4a: | |
11091 | case 0x4b: | |
11092 | case 0x4c: | |
11093 | case 0x4d: | |
11094 | case 0x4e: | |
11095 | case 0x4f: | |
f16cd0d5 L |
11096 | if (address_mode == mode_64bit) |
11097 | newrex = *codep; | |
11098 | else | |
11099 | return 1; | |
11100 | last_rex_prefix = i; | |
52b15da3 | 11101 | break; |
252b5132 RH |
11102 | case 0xf3: |
11103 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11104 | last_repz_prefix = i; |
252b5132 RH |
11105 | break; |
11106 | case 0xf2: | |
11107 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11108 | last_repnz_prefix = i; |
252b5132 RH |
11109 | break; |
11110 | case 0xf0: | |
11111 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11112 | last_lock_prefix = i; |
252b5132 RH |
11113 | break; |
11114 | case 0x2e: | |
11115 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11116 | last_seg_prefix = i; |
285ca992 | 11117 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11118 | break; |
11119 | case 0x36: | |
11120 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11121 | last_seg_prefix = i; |
285ca992 | 11122 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11123 | break; |
11124 | case 0x3e: | |
11125 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11126 | last_seg_prefix = i; |
285ca992 | 11127 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11128 | break; |
11129 | case 0x26: | |
11130 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11131 | last_seg_prefix = i; |
285ca992 | 11132 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11133 | break; |
11134 | case 0x64: | |
11135 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11136 | last_seg_prefix = i; |
285ca992 | 11137 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11138 | break; |
11139 | case 0x65: | |
11140 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11141 | last_seg_prefix = i; |
285ca992 | 11142 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11143 | break; |
11144 | case 0x66: | |
11145 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11146 | last_data_prefix = i; |
252b5132 RH |
11147 | break; |
11148 | case 0x67: | |
11149 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11150 | last_addr_prefix = i; |
252b5132 | 11151 | break; |
5076851f | 11152 | case FWAIT_OPCODE: |
252b5132 RH |
11153 | /* fwait is really an instruction. If there are prefixes |
11154 | before the fwait, they belong to the fwait, *not* to the | |
11155 | following instruction. */ | |
d9949a36 | 11156 | fwait_prefix = i; |
3e7d61b2 | 11157 | if (prefixes || rex) |
252b5132 RH |
11158 | { |
11159 | prefixes |= PREFIX_FWAIT; | |
11160 | codep++; | |
6c067bbb RM |
11161 | /* This ensures that the previous REX prefixes are noticed |
11162 | as unused prefixes, as in the return case below. */ | |
11163 | rex_used = rex; | |
f16cd0d5 | 11164 | return 1; |
252b5132 RH |
11165 | } |
11166 | prefixes = PREFIX_FWAIT; | |
11167 | break; | |
11168 | default: | |
f16cd0d5 | 11169 | return 1; |
252b5132 | 11170 | } |
52b15da3 JH |
11171 | /* Rex is ignored when followed by another prefix. */ |
11172 | if (rex) | |
11173 | { | |
3e7d61b2 | 11174 | rex_used = rex; |
f16cd0d5 | 11175 | return 1; |
52b15da3 | 11176 | } |
f16cd0d5 | 11177 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11178 | all_prefixes[i++] = *codep; |
52b15da3 | 11179 | rex = newrex; |
252b5132 | 11180 | codep++; |
f16cd0d5 L |
11181 | length++; |
11182 | } | |
11183 | return 0; | |
11184 | } | |
11185 | ||
7d421014 ILT |
11186 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11187 | prefix byte. */ | |
11188 | ||
11189 | static const char * | |
26ca5450 | 11190 | prefix_name (int pref, int sizeflag) |
7d421014 | 11191 | { |
0003779b L |
11192 | static const char *rexes [16] = |
11193 | { | |
11194 | "rex", /* 0x40 */ | |
11195 | "rex.B", /* 0x41 */ | |
11196 | "rex.X", /* 0x42 */ | |
11197 | "rex.XB", /* 0x43 */ | |
11198 | "rex.R", /* 0x44 */ | |
11199 | "rex.RB", /* 0x45 */ | |
11200 | "rex.RX", /* 0x46 */ | |
11201 | "rex.RXB", /* 0x47 */ | |
11202 | "rex.W", /* 0x48 */ | |
11203 | "rex.WB", /* 0x49 */ | |
11204 | "rex.WX", /* 0x4a */ | |
11205 | "rex.WXB", /* 0x4b */ | |
11206 | "rex.WR", /* 0x4c */ | |
11207 | "rex.WRB", /* 0x4d */ | |
11208 | "rex.WRX", /* 0x4e */ | |
11209 | "rex.WRXB", /* 0x4f */ | |
11210 | }; | |
11211 | ||
7d421014 ILT |
11212 | switch (pref) |
11213 | { | |
52b15da3 JH |
11214 | /* REX prefixes family. */ |
11215 | case 0x40: | |
52b15da3 | 11216 | case 0x41: |
52b15da3 | 11217 | case 0x42: |
52b15da3 | 11218 | case 0x43: |
52b15da3 | 11219 | case 0x44: |
52b15da3 | 11220 | case 0x45: |
52b15da3 | 11221 | case 0x46: |
52b15da3 | 11222 | case 0x47: |
52b15da3 | 11223 | case 0x48: |
52b15da3 | 11224 | case 0x49: |
52b15da3 | 11225 | case 0x4a: |
52b15da3 | 11226 | case 0x4b: |
52b15da3 | 11227 | case 0x4c: |
52b15da3 | 11228 | case 0x4d: |
52b15da3 | 11229 | case 0x4e: |
52b15da3 | 11230 | case 0x4f: |
0003779b | 11231 | return rexes [pref - 0x40]; |
7d421014 ILT |
11232 | case 0xf3: |
11233 | return "repz"; | |
11234 | case 0xf2: | |
11235 | return "repnz"; | |
11236 | case 0xf0: | |
11237 | return "lock"; | |
11238 | case 0x2e: | |
11239 | return "cs"; | |
11240 | case 0x36: | |
11241 | return "ss"; | |
11242 | case 0x3e: | |
11243 | return "ds"; | |
11244 | case 0x26: | |
11245 | return "es"; | |
11246 | case 0x64: | |
11247 | return "fs"; | |
11248 | case 0x65: | |
11249 | return "gs"; | |
11250 | case 0x66: | |
11251 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11252 | case 0x67: | |
cb712a9e | 11253 | if (address_mode == mode_64bit) |
db6eb5be | 11254 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11255 | else |
2888cb7a | 11256 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11257 | case FWAIT_OPCODE: |
11258 | return "fwait"; | |
f16cd0d5 L |
11259 | case REP_PREFIX: |
11260 | return "rep"; | |
42164a71 L |
11261 | case XACQUIRE_PREFIX: |
11262 | return "xacquire"; | |
11263 | case XRELEASE_PREFIX: | |
11264 | return "xrelease"; | |
7e8b059b L |
11265 | case BND_PREFIX: |
11266 | return "bnd"; | |
04ef582a L |
11267 | case NOTRACK_PREFIX: |
11268 | return "notrack"; | |
7d421014 ILT |
11269 | default: |
11270 | return NULL; | |
11271 | } | |
11272 | } | |
11273 | ||
ce518a5f L |
11274 | static char op_out[MAX_OPERANDS][100]; |
11275 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11276 | static int two_source_ops; |
ce518a5f L |
11277 | static bfd_vma op_address[MAX_OPERANDS]; |
11278 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11279 | static bfd_vma start_pc; |
ce518a5f | 11280 | |
252b5132 RH |
11281 | /* |
11282 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11283 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11284 | * section of the "Virtual 8086 Mode" chapter.) | |
11285 | * 'pc' should be the address of this instruction, it will | |
11286 | * be used to print the target address if this is a relative jump or call | |
11287 | * The function returns the length of this instruction in bytes. | |
11288 | */ | |
11289 | ||
252b5132 | 11290 | static char intel_syntax; |
9d141669 | 11291 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11292 | static char open_char; |
11293 | static char close_char; | |
11294 | static char separator_char; | |
11295 | static char scale_char; | |
11296 | ||
5db04b09 L |
11297 | enum x86_64_isa |
11298 | { | |
d835a58b | 11299 | amd64 = 1, |
5db04b09 L |
11300 | intel64 |
11301 | }; | |
11302 | ||
11303 | static enum x86_64_isa isa64; | |
11304 | ||
e396998b AM |
11305 | /* Here for backwards compatibility. When gdb stops using |
11306 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11307 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11308 | int |
26ca5450 | 11309 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11310 | { |
11311 | intel_syntax = 0; | |
e396998b AM |
11312 | |
11313 | return print_insn (pc, info); | |
252b5132 RH |
11314 | } |
11315 | ||
11316 | int | |
26ca5450 | 11317 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11318 | { |
11319 | intel_syntax = 1; | |
e396998b AM |
11320 | |
11321 | return print_insn (pc, info); | |
252b5132 RH |
11322 | } |
11323 | ||
e396998b | 11324 | int |
26ca5450 | 11325 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11326 | { |
11327 | intel_syntax = -1; | |
11328 | ||
11329 | return print_insn (pc, info); | |
11330 | } | |
11331 | ||
f59a29b9 L |
11332 | void |
11333 | print_i386_disassembler_options (FILE *stream) | |
11334 | { | |
11335 | fprintf (stream, _("\n\ | |
11336 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11337 | with the -M switch (multiple options should be separated by commas):\n")); | |
11338 | ||
11339 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11340 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11341 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11342 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11343 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11344 | fprintf (stream, _(" att-mnemonic\n" |
11345 | " Display instruction in AT&T mnemonic\n")); | |
11346 | fprintf (stream, _(" intel-mnemonic\n" | |
11347 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11348 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11349 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11350 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11351 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11352 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11353 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11354 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11355 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11356 | } |
11357 | ||
592d1631 | 11358 | /* Bad opcode. */ |
bf890a93 | 11359 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11360 | |
b844680a L |
11361 | /* Get a pointer to struct dis386 with a valid name. */ |
11362 | ||
11363 | static const struct dis386 * | |
8bb15339 | 11364 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11365 | { |
91d6fa6a | 11366 | int vindex, vex_table_index; |
b844680a L |
11367 | |
11368 | if (dp->name != NULL) | |
11369 | return dp; | |
11370 | ||
11371 | switch (dp->op[0].bytemode) | |
11372 | { | |
1ceb70f8 L |
11373 | case USE_REG_TABLE: |
11374 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11375 | break; | |
11376 | ||
11377 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11378 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11379 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11380 | break; |
11381 | ||
11382 | case USE_RM_TABLE: | |
11383 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11384 | break; |
11385 | ||
4e7d34a6 | 11386 | case USE_PREFIX_TABLE: |
c0f3af97 | 11387 | if (need_vex) |
b844680a | 11388 | { |
c0f3af97 L |
11389 | /* The prefix in VEX is implicit. */ |
11390 | switch (vex.prefix) | |
11391 | { | |
11392 | case 0: | |
91d6fa6a | 11393 | vindex = 0; |
c0f3af97 L |
11394 | break; |
11395 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11396 | vindex = 1; |
c0f3af97 L |
11397 | break; |
11398 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11399 | vindex = 2; |
c0f3af97 L |
11400 | break; |
11401 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11402 | vindex = 3; |
c0f3af97 L |
11403 | break; |
11404 | default: | |
11405 | abort (); | |
11406 | break; | |
11407 | } | |
b844680a | 11408 | } |
7bb15c6f | 11409 | else |
b844680a | 11410 | { |
285ca992 L |
11411 | int last_prefix = -1; |
11412 | int prefix = 0; | |
91d6fa6a | 11413 | vindex = 0; |
285ca992 L |
11414 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11415 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11416 | last one wins. */ | |
11417 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11418 | { |
285ca992 | 11419 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11420 | { |
285ca992 L |
11421 | vindex = 1; |
11422 | prefix = PREFIX_REPZ; | |
11423 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11424 | } |
11425 | else | |
b844680a | 11426 | { |
285ca992 L |
11427 | vindex = 3; |
11428 | prefix = PREFIX_REPNZ; | |
11429 | last_prefix = last_repnz_prefix; | |
b844680a | 11430 | } |
285ca992 | 11431 | |
507bd325 L |
11432 | /* Check if prefix should be ignored. */ |
11433 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11434 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11435 | & prefix) != 0) | |
285ca992 L |
11436 | vindex = 0; |
11437 | } | |
11438 | ||
11439 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11440 | { | |
11441 | vindex = 2; | |
11442 | prefix = PREFIX_DATA; | |
11443 | last_prefix = last_data_prefix; | |
11444 | } | |
11445 | ||
11446 | if (vindex != 0) | |
11447 | { | |
11448 | used_prefixes |= prefix; | |
11449 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11450 | } |
11451 | } | |
91d6fa6a | 11452 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11453 | break; |
11454 | ||
4e7d34a6 | 11455 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11456 | vindex = address_mode == mode_64bit ? 1 : 0; |
11457 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11458 | break; |
11459 | ||
4e7d34a6 | 11460 | case USE_3BYTE_TABLE: |
8bb15339 | 11461 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11462 | vindex = *codep++; |
11463 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11464 | end_codep = codep; |
8bb15339 L |
11465 | modrm.mod = (*codep >> 6) & 3; |
11466 | modrm.reg = (*codep >> 3) & 7; | |
11467 | modrm.rm = *codep & 7; | |
11468 | break; | |
11469 | ||
c0f3af97 L |
11470 | case USE_VEX_LEN_TABLE: |
11471 | if (!need_vex) | |
11472 | abort (); | |
11473 | ||
11474 | switch (vex.length) | |
11475 | { | |
11476 | case 128: | |
91d6fa6a | 11477 | vindex = 0; |
c0f3af97 L |
11478 | break; |
11479 | case 256: | |
91d6fa6a | 11480 | vindex = 1; |
c0f3af97 L |
11481 | break; |
11482 | default: | |
11483 | abort (); | |
11484 | break; | |
11485 | } | |
11486 | ||
91d6fa6a | 11487 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11488 | break; |
11489 | ||
04e2a182 L |
11490 | case USE_EVEX_LEN_TABLE: |
11491 | if (!vex.evex) | |
11492 | abort (); | |
11493 | ||
11494 | switch (vex.length) | |
11495 | { | |
11496 | case 128: | |
11497 | vindex = 0; | |
11498 | break; | |
11499 | case 256: | |
11500 | vindex = 1; | |
11501 | break; | |
11502 | case 512: | |
11503 | vindex = 2; | |
11504 | break; | |
11505 | default: | |
11506 | abort (); | |
11507 | break; | |
11508 | } | |
11509 | ||
11510 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11511 | break; | |
11512 | ||
f88c9eb0 SP |
11513 | case USE_XOP_8F_TABLE: |
11514 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
11515 | rex = ~(*codep >> 5) & 0x7; |
11516 | ||
11517 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11518 | switch ((*codep & 0x1f)) | |
11519 | { | |
11520 | default: | |
f07af43e L |
11521 | dp = &bad_opcode; |
11522 | return dp; | |
5dd85c99 SP |
11523 | case 0x8: |
11524 | vex_table_index = XOP_08; | |
11525 | break; | |
f88c9eb0 SP |
11526 | case 0x9: |
11527 | vex_table_index = XOP_09; | |
11528 | break; | |
11529 | case 0xa: | |
11530 | vex_table_index = XOP_0A; | |
11531 | break; | |
11532 | } | |
11533 | codep++; | |
11534 | vex.w = *codep & 0x80; | |
11535 | if (vex.w && address_mode == mode_64bit) | |
11536 | rex |= REX_W; | |
11537 | ||
11538 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11539 | if (address_mode != mode_64bit) |
f07af43e | 11540 | { |
abfcb414 AP |
11541 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11542 | rex &= ~REX_B; | |
f07af43e | 11543 | } |
f88c9eb0 SP |
11544 | |
11545 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11546 | switch ((*codep & 0x3)) | |
11547 | { | |
11548 | case 0: | |
f88c9eb0 SP |
11549 | break; |
11550 | case 1: | |
11551 | vex.prefix = DATA_PREFIX_OPCODE; | |
11552 | break; | |
11553 | case 2: | |
11554 | vex.prefix = REPE_PREFIX_OPCODE; | |
11555 | break; | |
11556 | case 3: | |
11557 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11558 | break; | |
11559 | } | |
11560 | need_vex = 1; | |
11561 | need_vex_reg = 1; | |
11562 | codep++; | |
91d6fa6a NC |
11563 | vindex = *codep++; |
11564 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11565 | |
285ca992 | 11566 | end_codep = codep; |
c48244a5 SP |
11567 | FETCH_DATA (info, codep + 1); |
11568 | modrm.mod = (*codep >> 6) & 3; | |
11569 | modrm.reg = (*codep >> 3) & 7; | |
11570 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11571 | break; |
11572 | ||
c0f3af97 | 11573 | case USE_VEX_C4_TABLE: |
43234a1e | 11574 | /* VEX prefix. */ |
c0f3af97 | 11575 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
11576 | rex = ~(*codep >> 5) & 0x7; |
11577 | switch ((*codep & 0x1f)) | |
11578 | { | |
11579 | default: | |
f07af43e L |
11580 | dp = &bad_opcode; |
11581 | return dp; | |
c0f3af97 | 11582 | case 0x1: |
f88c9eb0 | 11583 | vex_table_index = VEX_0F; |
c0f3af97 L |
11584 | break; |
11585 | case 0x2: | |
f88c9eb0 | 11586 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11587 | break; |
11588 | case 0x3: | |
f88c9eb0 | 11589 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11590 | break; |
11591 | } | |
11592 | codep++; | |
11593 | vex.w = *codep & 0x80; | |
9889cbb1 | 11594 | if (address_mode == mode_64bit) |
f07af43e | 11595 | { |
9889cbb1 L |
11596 | if (vex.w) |
11597 | rex |= REX_W; | |
9889cbb1 L |
11598 | } |
11599 | else | |
11600 | { | |
11601 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11602 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11603 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11604 | rex = 0; |
f07af43e | 11605 | } |
5f847646 | 11606 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11607 | vex.length = (*codep & 0x4) ? 256 : 128; |
11608 | switch ((*codep & 0x3)) | |
11609 | { | |
11610 | case 0: | |
c0f3af97 L |
11611 | break; |
11612 | case 1: | |
11613 | vex.prefix = DATA_PREFIX_OPCODE; | |
11614 | break; | |
11615 | case 2: | |
11616 | vex.prefix = REPE_PREFIX_OPCODE; | |
11617 | break; | |
11618 | case 3: | |
11619 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11620 | break; | |
11621 | } | |
11622 | need_vex = 1; | |
11623 | need_vex_reg = 1; | |
11624 | codep++; | |
91d6fa6a NC |
11625 | vindex = *codep++; |
11626 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11627 | end_codep = codep; |
53c4d625 JB |
11628 | /* There is no MODRM byte for VEX0F 77. */ |
11629 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11630 | { |
11631 | FETCH_DATA (info, codep + 1); | |
11632 | modrm.mod = (*codep >> 6) & 3; | |
11633 | modrm.reg = (*codep >> 3) & 7; | |
11634 | modrm.rm = *codep & 7; | |
11635 | } | |
11636 | break; | |
11637 | ||
11638 | case USE_VEX_C5_TABLE: | |
43234a1e | 11639 | /* VEX prefix. */ |
c0f3af97 | 11640 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
11641 | rex = (*codep & 0x80) ? 0 : REX_R; |
11642 | ||
9889cbb1 L |
11643 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11644 | VEX.vvvv is 1. */ | |
c0f3af97 | 11645 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11646 | vex.length = (*codep & 0x4) ? 256 : 128; |
11647 | switch ((*codep & 0x3)) | |
11648 | { | |
11649 | case 0: | |
c0f3af97 L |
11650 | break; |
11651 | case 1: | |
11652 | vex.prefix = DATA_PREFIX_OPCODE; | |
11653 | break; | |
11654 | case 2: | |
11655 | vex.prefix = REPE_PREFIX_OPCODE; | |
11656 | break; | |
11657 | case 3: | |
11658 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11659 | break; | |
11660 | } | |
11661 | need_vex = 1; | |
11662 | need_vex_reg = 1; | |
11663 | codep++; | |
91d6fa6a NC |
11664 | vindex = *codep++; |
11665 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11666 | end_codep = codep; |
53c4d625 JB |
11667 | /* There is no MODRM byte for VEX 77. */ |
11668 | if (vindex != 0x77) | |
c0f3af97 L |
11669 | { |
11670 | FETCH_DATA (info, codep + 1); | |
11671 | modrm.mod = (*codep >> 6) & 3; | |
11672 | modrm.reg = (*codep >> 3) & 7; | |
11673 | modrm.rm = *codep & 7; | |
11674 | } | |
11675 | break; | |
11676 | ||
9e30b8e0 L |
11677 | case USE_VEX_W_TABLE: |
11678 | if (!need_vex) | |
11679 | abort (); | |
11680 | ||
11681 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11682 | break; | |
11683 | ||
43234a1e L |
11684 | case USE_EVEX_TABLE: |
11685 | two_source_ops = 0; | |
11686 | /* EVEX prefix. */ | |
11687 | vex.evex = 1; | |
11688 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
11689 | /* The first byte after 0x62. */ |
11690 | rex = ~(*codep >> 5) & 0x7; | |
11691 | vex.r = *codep & 0x10; | |
11692 | switch ((*codep & 0xf)) | |
11693 | { | |
11694 | default: | |
11695 | return &bad_opcode; | |
11696 | case 0x1: | |
11697 | vex_table_index = EVEX_0F; | |
11698 | break; | |
11699 | case 0x2: | |
11700 | vex_table_index = EVEX_0F38; | |
11701 | break; | |
11702 | case 0x3: | |
11703 | vex_table_index = EVEX_0F3A; | |
11704 | break; | |
11705 | } | |
11706 | ||
11707 | /* The second byte after 0x62. */ | |
11708 | codep++; | |
11709 | vex.w = *codep & 0x80; | |
11710 | if (vex.w && address_mode == mode_64bit) | |
11711 | rex |= REX_W; | |
11712 | ||
11713 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11714 | |
11715 | /* The U bit. */ | |
11716 | if (!(*codep & 0x4)) | |
11717 | return &bad_opcode; | |
11718 | ||
11719 | switch ((*codep & 0x3)) | |
11720 | { | |
11721 | case 0: | |
43234a1e L |
11722 | break; |
11723 | case 1: | |
11724 | vex.prefix = DATA_PREFIX_OPCODE; | |
11725 | break; | |
11726 | case 2: | |
11727 | vex.prefix = REPE_PREFIX_OPCODE; | |
11728 | break; | |
11729 | case 3: | |
11730 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11731 | break; | |
11732 | } | |
11733 | ||
11734 | /* The third byte after 0x62. */ | |
11735 | codep++; | |
11736 | ||
11737 | /* Remember the static rounding bits. */ | |
11738 | vex.ll = (*codep >> 5) & 3; | |
11739 | vex.b = (*codep & 0x10) != 0; | |
11740 | ||
11741 | vex.v = *codep & 0x8; | |
11742 | vex.mask_register_specifier = *codep & 0x7; | |
11743 | vex.zeroing = *codep & 0x80; | |
11744 | ||
5f847646 JB |
11745 | if (address_mode != mode_64bit) |
11746 | { | |
11747 | /* In 16/32-bit mode silently ignore following bits. */ | |
11748 | rex &= ~REX_B; | |
11749 | vex.r = 1; | |
11750 | vex.v = 1; | |
11751 | } | |
11752 | ||
43234a1e L |
11753 | need_vex = 1; |
11754 | need_vex_reg = 1; | |
11755 | codep++; | |
11756 | vindex = *codep++; | |
11757 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11758 | end_codep = codep; |
43234a1e L |
11759 | FETCH_DATA (info, codep + 1); |
11760 | modrm.mod = (*codep >> 6) & 3; | |
11761 | modrm.reg = (*codep >> 3) & 7; | |
11762 | modrm.rm = *codep & 7; | |
11763 | ||
11764 | /* Set vector length. */ | |
11765 | if (modrm.mod == 3 && vex.b) | |
11766 | vex.length = 512; | |
11767 | else | |
11768 | { | |
11769 | switch (vex.ll) | |
11770 | { | |
11771 | case 0x0: | |
11772 | vex.length = 128; | |
11773 | break; | |
11774 | case 0x1: | |
11775 | vex.length = 256; | |
11776 | break; | |
11777 | case 0x2: | |
11778 | vex.length = 512; | |
11779 | break; | |
11780 | default: | |
11781 | return &bad_opcode; | |
11782 | } | |
11783 | } | |
11784 | break; | |
11785 | ||
592d1631 L |
11786 | case 0: |
11787 | dp = &bad_opcode; | |
11788 | break; | |
11789 | ||
b844680a | 11790 | default: |
d34b5006 | 11791 | abort (); |
b844680a L |
11792 | } |
11793 | ||
11794 | if (dp->name != NULL) | |
11795 | return dp; | |
11796 | else | |
8bb15339 | 11797 | return get_valid_dis386 (dp, info); |
b844680a L |
11798 | } |
11799 | ||
dfc8cf43 | 11800 | static void |
55cf16e1 | 11801 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11802 | { |
11803 | /* If modrm.mod == 3, operand must be register. */ | |
11804 | if (need_modrm | |
55cf16e1 | 11805 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11806 | && modrm.mod != 3 |
11807 | && modrm.rm == 4) | |
11808 | { | |
11809 | FETCH_DATA (info, codep + 2); | |
11810 | sib.index = (codep [1] >> 3) & 7; | |
11811 | sib.scale = (codep [1] >> 6) & 3; | |
11812 | sib.base = codep [1] & 7; | |
11813 | } | |
11814 | } | |
11815 | ||
e396998b | 11816 | static int |
26ca5450 | 11817 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11818 | { |
2da11e11 | 11819 | const struct dis386 *dp; |
252b5132 | 11820 | int i; |
ce518a5f | 11821 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11822 | int needcomma; |
df18fdba | 11823 | int sizeflag, orig_sizeflag; |
e396998b | 11824 | const char *p; |
252b5132 | 11825 | struct dis_private priv; |
f16cd0d5 | 11826 | int prefix_length; |
252b5132 | 11827 | |
d7921315 L |
11828 | priv.orig_sizeflag = AFLAG | DFLAG; |
11829 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11830 | address_mode = mode_32bit; |
2da11e11 | 11831 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11832 | { |
11833 | address_mode = mode_16bit; | |
11834 | priv.orig_sizeflag = 0; | |
11835 | } | |
2da11e11 | 11836 | else |
d7921315 L |
11837 | address_mode = mode_64bit; |
11838 | ||
11839 | if (intel_syntax == (char) -1) | |
11840 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11841 | |
11842 | for (p = info->disassembler_options; p != NULL; ) | |
11843 | { | |
5db04b09 L |
11844 | if (CONST_STRNEQ (p, "amd64")) |
11845 | isa64 = amd64; | |
11846 | else if (CONST_STRNEQ (p, "intel64")) | |
11847 | isa64 = intel64; | |
11848 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11849 | { |
cb712a9e | 11850 | address_mode = mode_64bit; |
e396998b AM |
11851 | priv.orig_sizeflag = AFLAG | DFLAG; |
11852 | } | |
0112cd26 | 11853 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11854 | { |
cb712a9e | 11855 | address_mode = mode_32bit; |
e396998b AM |
11856 | priv.orig_sizeflag = AFLAG | DFLAG; |
11857 | } | |
0112cd26 | 11858 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11859 | { |
cb712a9e | 11860 | address_mode = mode_16bit; |
e396998b AM |
11861 | priv.orig_sizeflag = 0; |
11862 | } | |
0112cd26 | 11863 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11864 | { |
11865 | intel_syntax = 1; | |
9d141669 L |
11866 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11867 | intel_mnemonic = 1; | |
e396998b | 11868 | } |
0112cd26 | 11869 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11870 | { |
11871 | intel_syntax = 0; | |
9d141669 L |
11872 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11873 | intel_mnemonic = 0; | |
e396998b | 11874 | } |
0112cd26 | 11875 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11876 | { |
f59a29b9 L |
11877 | if (address_mode == mode_64bit) |
11878 | { | |
11879 | if (p[4] == '3' && p[5] == '2') | |
11880 | priv.orig_sizeflag &= ~AFLAG; | |
11881 | else if (p[4] == '6' && p[5] == '4') | |
11882 | priv.orig_sizeflag |= AFLAG; | |
11883 | } | |
11884 | else | |
11885 | { | |
11886 | if (p[4] == '1' && p[5] == '6') | |
11887 | priv.orig_sizeflag &= ~AFLAG; | |
11888 | else if (p[4] == '3' && p[5] == '2') | |
11889 | priv.orig_sizeflag |= AFLAG; | |
11890 | } | |
e396998b | 11891 | } |
0112cd26 | 11892 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11893 | { |
11894 | if (p[4] == '1' && p[5] == '6') | |
11895 | priv.orig_sizeflag &= ~DFLAG; | |
11896 | else if (p[4] == '3' && p[5] == '2') | |
11897 | priv.orig_sizeflag |= DFLAG; | |
11898 | } | |
0112cd26 | 11899 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11900 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11901 | ||
11902 | p = strchr (p, ','); | |
11903 | if (p != NULL) | |
11904 | p++; | |
11905 | } | |
11906 | ||
c0f92bf9 L |
11907 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11908 | { | |
11909 | (*info->fprintf_func) (info->stream, | |
11910 | _("64-bit address is disabled")); | |
11911 | return -1; | |
11912 | } | |
11913 | ||
e396998b AM |
11914 | if (intel_syntax) |
11915 | { | |
11916 | names64 = intel_names64; | |
11917 | names32 = intel_names32; | |
11918 | names16 = intel_names16; | |
11919 | names8 = intel_names8; | |
11920 | names8rex = intel_names8rex; | |
11921 | names_seg = intel_names_seg; | |
b9733481 | 11922 | names_mm = intel_names_mm; |
7e8b059b | 11923 | names_bnd = intel_names_bnd; |
b9733481 L |
11924 | names_xmm = intel_names_xmm; |
11925 | names_ymm = intel_names_ymm; | |
43234a1e | 11926 | names_zmm = intel_names_zmm; |
db51cc60 L |
11927 | index64 = intel_index64; |
11928 | index32 = intel_index32; | |
43234a1e | 11929 | names_mask = intel_names_mask; |
e396998b AM |
11930 | index16 = intel_index16; |
11931 | open_char = '['; | |
11932 | close_char = ']'; | |
11933 | separator_char = '+'; | |
11934 | scale_char = '*'; | |
11935 | } | |
11936 | else | |
11937 | { | |
11938 | names64 = att_names64; | |
11939 | names32 = att_names32; | |
11940 | names16 = att_names16; | |
11941 | names8 = att_names8; | |
11942 | names8rex = att_names8rex; | |
11943 | names_seg = att_names_seg; | |
b9733481 | 11944 | names_mm = att_names_mm; |
7e8b059b | 11945 | names_bnd = att_names_bnd; |
b9733481 L |
11946 | names_xmm = att_names_xmm; |
11947 | names_ymm = att_names_ymm; | |
43234a1e | 11948 | names_zmm = att_names_zmm; |
db51cc60 L |
11949 | index64 = att_index64; |
11950 | index32 = att_index32; | |
43234a1e | 11951 | names_mask = att_names_mask; |
e396998b AM |
11952 | index16 = att_index16; |
11953 | open_char = '('; | |
11954 | close_char = ')'; | |
11955 | separator_char = ','; | |
11956 | scale_char = ','; | |
11957 | } | |
2da11e11 | 11958 | |
4fe53c98 | 11959 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11960 | puts most long word instructions on a single line. Use 8 bytes |
11961 | for Intel L1OM. */ | |
d7921315 | 11962 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11963 | info->bytes_per_line = 8; |
11964 | else | |
11965 | info->bytes_per_line = 7; | |
252b5132 | 11966 | |
26ca5450 | 11967 | info->private_data = &priv; |
252b5132 RH |
11968 | priv.max_fetched = priv.the_buffer; |
11969 | priv.insn_start = pc; | |
252b5132 RH |
11970 | |
11971 | obuf[0] = 0; | |
ce518a5f L |
11972 | for (i = 0; i < MAX_OPERANDS; ++i) |
11973 | { | |
11974 | op_out[i][0] = 0; | |
11975 | op_index[i] = -1; | |
11976 | } | |
252b5132 RH |
11977 | |
11978 | the_info = info; | |
11979 | start_pc = pc; | |
e396998b AM |
11980 | start_codep = priv.the_buffer; |
11981 | codep = priv.the_buffer; | |
252b5132 | 11982 | |
8df14d78 | 11983 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 11984 | { |
7d421014 ILT |
11985 | const char *name; |
11986 | ||
5076851f | 11987 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11988 | means we have an incomplete instruction of some sort. Just |
11989 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11990 | if (codep > priv.the_buffer) | |
5076851f | 11991 | { |
e396998b | 11992 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11993 | if (name != NULL) |
11994 | (*info->fprintf_func) (info->stream, "%s", name); | |
11995 | else | |
5076851f | 11996 | { |
7d421014 ILT |
11997 | /* Just print the first byte as a .byte instruction. */ |
11998 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11999 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12000 | } |
5076851f | 12001 | |
7d421014 | 12002 | return 1; |
5076851f ILT |
12003 | } |
12004 | ||
12005 | return -1; | |
12006 | } | |
12007 | ||
52b15da3 | 12008 | obufp = obuf; |
f16cd0d5 L |
12009 | sizeflag = priv.orig_sizeflag; |
12010 | ||
12011 | if (!ckprefix () || rex_used) | |
12012 | { | |
12013 | /* Too many prefixes or unused REX prefixes. */ | |
12014 | for (i = 0; | |
f6dd4781 | 12015 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12016 | i++) |
de882298 | 12017 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12018 | i == 0 ? "" : " ", |
f16cd0d5 | 12019 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12020 | return i; |
f16cd0d5 | 12021 | } |
252b5132 RH |
12022 | |
12023 | insn_codep = codep; | |
12024 | ||
12025 | FETCH_DATA (info, codep + 1); | |
12026 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12027 | ||
3e7d61b2 | 12028 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12029 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12030 | { |
86a80a50 | 12031 | /* Handle prefixes before fwait. */ |
d9949a36 | 12032 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12033 | i++) |
12034 | (*info->fprintf_func) (info->stream, "%s ", | |
12035 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12036 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12037 | return i + 1; |
252b5132 RH |
12038 | } |
12039 | ||
252b5132 RH |
12040 | if (*codep == 0x0f) |
12041 | { | |
eec0f4ca | 12042 | unsigned char threebyte; |
5f40e14d JS |
12043 | |
12044 | codep++; | |
12045 | FETCH_DATA (info, codep + 1); | |
12046 | threebyte = *codep; | |
eec0f4ca | 12047 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12048 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12049 | codep++; |
252b5132 RH |
12050 | } |
12051 | else | |
12052 | { | |
6439fc28 | 12053 | dp = &dis386[*codep]; |
252b5132 | 12054 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12055 | codep++; |
252b5132 | 12056 | } |
246c51aa | 12057 | |
df18fdba L |
12058 | /* Save sizeflag for printing the extra prefixes later before updating |
12059 | it for mnemonic and operand processing. The prefix names depend | |
12060 | only on the address mode. */ | |
12061 | orig_sizeflag = sizeflag; | |
c608c12e | 12062 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12063 | sizeflag ^= AFLAG; |
b844680a | 12064 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12065 | sizeflag ^= DFLAG; |
3ffd33cf | 12066 | |
285ca992 | 12067 | end_codep = codep; |
8bb15339 | 12068 | if (need_modrm) |
252b5132 RH |
12069 | { |
12070 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12071 | modrm.mod = (*codep >> 6) & 3; |
12072 | modrm.reg = (*codep >> 3) & 7; | |
12073 | modrm.rm = *codep & 7; | |
252b5132 RH |
12074 | } |
12075 | ||
42d5f9c6 MS |
12076 | need_vex = 0; |
12077 | need_vex_reg = 0; | |
12078 | vex_w_done = 0; | |
caf0678c | 12079 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12080 | |
ce518a5f | 12081 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12082 | { |
55cf16e1 | 12083 | get_sib (info, sizeflag); |
252b5132 RH |
12084 | dofloat (sizeflag); |
12085 | } | |
12086 | else | |
12087 | { | |
8bb15339 | 12088 | dp = get_valid_dis386 (dp, info); |
b844680a | 12089 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12090 | { |
55cf16e1 | 12091 | get_sib (info, sizeflag); |
ce518a5f L |
12092 | for (i = 0; i < MAX_OPERANDS; ++i) |
12093 | { | |
246c51aa | 12094 | obufp = op_out[i]; |
ce518a5f L |
12095 | op_ad = MAX_OPERANDS - 1 - i; |
12096 | if (dp->op[i].rtn) | |
12097 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12098 | /* For EVEX instruction after the last operand masking |
12099 | should be printed. */ | |
12100 | if (i == 0 && vex.evex) | |
12101 | { | |
12102 | /* Don't print {%k0}. */ | |
12103 | if (vex.mask_register_specifier) | |
12104 | { | |
12105 | oappend ("{"); | |
12106 | oappend (names_mask[vex.mask_register_specifier]); | |
12107 | oappend ("}"); | |
12108 | } | |
12109 | if (vex.zeroing) | |
12110 | oappend ("{z}"); | |
12111 | } | |
ce518a5f | 12112 | } |
6439fc28 | 12113 | } |
252b5132 RH |
12114 | } |
12115 | ||
1d67fe3b TT |
12116 | /* Clear instruction information. */ |
12117 | if (the_info) | |
12118 | { | |
12119 | the_info->insn_info_valid = 0; | |
12120 | the_info->branch_delay_insns = 0; | |
12121 | the_info->data_size = 0; | |
12122 | the_info->insn_type = dis_noninsn; | |
12123 | the_info->target = 0; | |
12124 | the_info->target2 = 0; | |
12125 | } | |
12126 | ||
12127 | /* Reset jump operation indicator. */ | |
12128 | op_is_jump = FALSE; | |
12129 | ||
12130 | { | |
12131 | int jump_detection = 0; | |
12132 | ||
12133 | /* Extract flags. */ | |
12134 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12135 | { | |
12136 | if ((dp->op[i].rtn == OP_J) | |
12137 | || (dp->op[i].rtn == OP_indirE)) | |
12138 | jump_detection |= 1; | |
12139 | else if ((dp->op[i].rtn == BND_Fixup) | |
12140 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12141 | jump_detection |= 2; | |
12142 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12143 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12144 | jump_detection |= 4; | |
12145 | } | |
12146 | ||
12147 | /* Determine if this is a jump or branch. */ | |
12148 | if ((jump_detection & 0x3) == 0x3) | |
12149 | { | |
12150 | op_is_jump = TRUE; | |
12151 | if (jump_detection & 0x4) | |
12152 | the_info->insn_type = dis_condbranch; | |
12153 | else | |
12154 | the_info->insn_type = | |
12155 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12156 | ? dis_jsr : dis_branch; | |
12157 | } | |
12158 | } | |
12159 | ||
63c6fc6c L |
12160 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12161 | are all 0s in inverted form. */ | |
12162 | if (need_vex && vex.register_specifier != 0) | |
12163 | { | |
12164 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12165 | return end_codep - priv.the_buffer; | |
12166 | } | |
12167 | ||
d869730d | 12168 | /* Check if the REX prefix is used. */ |
73239888 | 12169 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12170 | all_prefixes[last_rex_prefix] = 0; |
12171 | ||
5e6718e4 | 12172 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12173 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12174 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12175 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12176 | all_prefixes[last_seg_prefix] = 0; |
12177 | ||
5e6718e4 | 12178 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12179 | if ((prefixes & PREFIX_ADDR) != 0 |
12180 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12181 | all_prefixes[last_addr_prefix] = 0; | |
12182 | ||
df18fdba L |
12183 | /* Check if the DATA prefix is used. */ |
12184 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12185 | && (used_prefixes & PREFIX_DATA) != 0 |
12186 | && !need_vex) | |
df18fdba | 12187 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12188 | |
df18fdba | 12189 | /* Print the extra prefixes. */ |
f16cd0d5 | 12190 | prefix_length = 0; |
f310f33d | 12191 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12192 | if (all_prefixes[i]) |
12193 | { | |
12194 | const char *name; | |
df18fdba | 12195 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12196 | if (name == NULL) |
12197 | abort (); | |
12198 | prefix_length += strlen (name) + 1; | |
12199 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12200 | } | |
b844680a | 12201 | |
285ca992 L |
12202 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12203 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12204 | used by putop and MMX/SSE operand and may be overriden by the | |
12205 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12206 | separately. */ | |
3888916d | 12207 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12208 | && (((need_vex |
12209 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12210 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12211 | : (prefixes | |
12212 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12213 | && (used_prefixes |
12214 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12215 | || (((need_vex |
12216 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12217 | : ((prefixes | |
12218 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12219 | == PREFIX_DATA)) | |
97e6786a JB |
12220 | && (used_prefixes & PREFIX_DATA) == 0)) |
12221 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12222 | { |
12223 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12224 | return end_codep - priv.the_buffer; | |
12225 | } | |
12226 | ||
f16cd0d5 L |
12227 | /* Check maximum code length. */ |
12228 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12229 | { | |
12230 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12231 | return MAX_CODE_LENGTH; | |
12232 | } | |
b844680a | 12233 | |
ea397f5b | 12234 | obufp = mnemonicendp; |
f16cd0d5 | 12235 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12236 | oappend (" "); |
12237 | oappend (" "); | |
12238 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12239 | ||
12240 | /* The enter and bound instructions are printed with operands in the same | |
12241 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12242 | if (intel_syntax || two_source_ops) |
252b5132 | 12243 | { |
185b1163 L |
12244 | bfd_vma riprel; |
12245 | ||
ce518a5f | 12246 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12247 | op_txt[i] = op_out[i]; |
246c51aa | 12248 | |
3a8547d2 JB |
12249 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12250 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12251 | { | |
12252 | op_txt[2] = op_out[3]; | |
12253 | op_txt[3] = op_out[2]; | |
12254 | } | |
12255 | ||
ce518a5f L |
12256 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12257 | { | |
6c067bbb RM |
12258 | op_ad = op_index[i]; |
12259 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12260 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12261 | riprel = op_riprel[i]; |
12262 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12263 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12264 | } |
252b5132 RH |
12265 | } |
12266 | else | |
12267 | { | |
ce518a5f | 12268 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12269 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12270 | } |
12271 | ||
ce518a5f L |
12272 | needcomma = 0; |
12273 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12274 | if (*op_txt[i]) | |
12275 | { | |
12276 | if (needcomma) | |
12277 | (*info->fprintf_func) (info->stream, ","); | |
12278 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12279 | { |
12280 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12281 | ||
12282 | if (the_info && op_is_jump) | |
12283 | { | |
12284 | the_info->insn_info_valid = 1; | |
12285 | the_info->branch_delay_insns = 0; | |
12286 | the_info->data_size = 0; | |
12287 | the_info->target = target; | |
12288 | the_info->target2 = 0; | |
12289 | } | |
12290 | (*info->print_address_func) (target, info); | |
12291 | } | |
ce518a5f L |
12292 | else |
12293 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12294 | needcomma = 1; | |
12295 | } | |
050dfa73 | 12296 | |
ce518a5f | 12297 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12298 | if (op_index[i] != -1 && op_riprel[i]) |
12299 | { | |
12300 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12301 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12302 | + op_address[op_index[i]]), info); |
185b1163 | 12303 | break; |
52b15da3 | 12304 | } |
e396998b | 12305 | return codep - priv.the_buffer; |
252b5132 RH |
12306 | } |
12307 | ||
6439fc28 | 12308 | static const char *float_mem[] = { |
252b5132 | 12309 | /* d8 */ |
7c52e0e8 L |
12310 | "fadd{s|}", |
12311 | "fmul{s|}", | |
12312 | "fcom{s|}", | |
12313 | "fcomp{s|}", | |
12314 | "fsub{s|}", | |
12315 | "fsubr{s|}", | |
12316 | "fdiv{s|}", | |
12317 | "fdivr{s|}", | |
db6eb5be | 12318 | /* d9 */ |
7c52e0e8 | 12319 | "fld{s|}", |
252b5132 | 12320 | "(bad)", |
7c52e0e8 L |
12321 | "fst{s|}", |
12322 | "fstp{s|}", | |
9306ca4a | 12323 | "fldenvIC", |
252b5132 | 12324 | "fldcw", |
9306ca4a | 12325 | "fNstenvIC", |
252b5132 RH |
12326 | "fNstcw", |
12327 | /* da */ | |
7c52e0e8 L |
12328 | "fiadd{l|}", |
12329 | "fimul{l|}", | |
12330 | "ficom{l|}", | |
12331 | "ficomp{l|}", | |
12332 | "fisub{l|}", | |
12333 | "fisubr{l|}", | |
12334 | "fidiv{l|}", | |
12335 | "fidivr{l|}", | |
252b5132 | 12336 | /* db */ |
7c52e0e8 L |
12337 | "fild{l|}", |
12338 | "fisttp{l|}", | |
12339 | "fist{l|}", | |
12340 | "fistp{l|}", | |
252b5132 | 12341 | "(bad)", |
6439fc28 | 12342 | "fld{t||t|}", |
252b5132 | 12343 | "(bad)", |
6439fc28 | 12344 | "fstp{t||t|}", |
252b5132 | 12345 | /* dc */ |
7c52e0e8 L |
12346 | "fadd{l|}", |
12347 | "fmul{l|}", | |
12348 | "fcom{l|}", | |
12349 | "fcomp{l|}", | |
12350 | "fsub{l|}", | |
12351 | "fsubr{l|}", | |
12352 | "fdiv{l|}", | |
12353 | "fdivr{l|}", | |
252b5132 | 12354 | /* dd */ |
7c52e0e8 L |
12355 | "fld{l|}", |
12356 | "fisttp{ll|}", | |
12357 | "fst{l||}", | |
12358 | "fstp{l|}", | |
9306ca4a | 12359 | "frstorIC", |
252b5132 | 12360 | "(bad)", |
9306ca4a | 12361 | "fNsaveIC", |
252b5132 RH |
12362 | "fNstsw", |
12363 | /* de */ | |
ac465521 JB |
12364 | "fiadd{s|}", |
12365 | "fimul{s|}", | |
12366 | "ficom{s|}", | |
12367 | "ficomp{s|}", | |
12368 | "fisub{s|}", | |
12369 | "fisubr{s|}", | |
12370 | "fidiv{s|}", | |
12371 | "fidivr{s|}", | |
252b5132 | 12372 | /* df */ |
ac465521 JB |
12373 | "fild{s|}", |
12374 | "fisttp{s|}", | |
12375 | "fist{s|}", | |
12376 | "fistp{s|}", | |
252b5132 | 12377 | "fbld", |
7c52e0e8 | 12378 | "fild{ll|}", |
252b5132 | 12379 | "fbstp", |
7c52e0e8 | 12380 | "fistp{ll|}", |
1d9f512f AM |
12381 | }; |
12382 | ||
12383 | static const unsigned char float_mem_mode[] = { | |
12384 | /* d8 */ | |
12385 | d_mode, | |
12386 | d_mode, | |
12387 | d_mode, | |
12388 | d_mode, | |
12389 | d_mode, | |
12390 | d_mode, | |
12391 | d_mode, | |
12392 | d_mode, | |
12393 | /* d9 */ | |
12394 | d_mode, | |
12395 | 0, | |
12396 | d_mode, | |
12397 | d_mode, | |
12398 | 0, | |
12399 | w_mode, | |
12400 | 0, | |
12401 | w_mode, | |
12402 | /* da */ | |
12403 | d_mode, | |
12404 | d_mode, | |
12405 | d_mode, | |
12406 | d_mode, | |
12407 | d_mode, | |
12408 | d_mode, | |
12409 | d_mode, | |
12410 | d_mode, | |
12411 | /* db */ | |
12412 | d_mode, | |
12413 | d_mode, | |
12414 | d_mode, | |
12415 | d_mode, | |
12416 | 0, | |
9306ca4a | 12417 | t_mode, |
1d9f512f | 12418 | 0, |
9306ca4a | 12419 | t_mode, |
1d9f512f AM |
12420 | /* dc */ |
12421 | q_mode, | |
12422 | q_mode, | |
12423 | q_mode, | |
12424 | q_mode, | |
12425 | q_mode, | |
12426 | q_mode, | |
12427 | q_mode, | |
12428 | q_mode, | |
12429 | /* dd */ | |
12430 | q_mode, | |
12431 | q_mode, | |
12432 | q_mode, | |
12433 | q_mode, | |
12434 | 0, | |
12435 | 0, | |
12436 | 0, | |
12437 | w_mode, | |
12438 | /* de */ | |
12439 | w_mode, | |
12440 | w_mode, | |
12441 | w_mode, | |
12442 | w_mode, | |
12443 | w_mode, | |
12444 | w_mode, | |
12445 | w_mode, | |
12446 | w_mode, | |
12447 | /* df */ | |
12448 | w_mode, | |
12449 | w_mode, | |
12450 | w_mode, | |
12451 | w_mode, | |
9306ca4a | 12452 | t_mode, |
1d9f512f | 12453 | q_mode, |
9306ca4a | 12454 | t_mode, |
1d9f512f | 12455 | q_mode |
252b5132 RH |
12456 | }; |
12457 | ||
ce518a5f L |
12458 | #define ST { OP_ST, 0 } |
12459 | #define STi { OP_STi, 0 } | |
252b5132 | 12460 | |
48c97fa1 L |
12461 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12462 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12463 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12464 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12465 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12466 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12467 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12468 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12469 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12470 | |
2da11e11 | 12471 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12472 | /* d8 */ |
12473 | { | |
bf890a93 IT |
12474 | { "fadd", { ST, STi }, 0 }, |
12475 | { "fmul", { ST, STi }, 0 }, | |
12476 | { "fcom", { STi }, 0 }, | |
12477 | { "fcomp", { STi }, 0 }, | |
12478 | { "fsub", { ST, STi }, 0 }, | |
12479 | { "fsubr", { ST, STi }, 0 }, | |
12480 | { "fdiv", { ST, STi }, 0 }, | |
12481 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12482 | }, |
12483 | /* d9 */ | |
12484 | { | |
bf890a93 IT |
12485 | { "fld", { STi }, 0 }, |
12486 | { "fxch", { STi }, 0 }, | |
252b5132 | 12487 | { FGRPd9_2 }, |
592d1631 | 12488 | { Bad_Opcode }, |
252b5132 RH |
12489 | { FGRPd9_4 }, |
12490 | { FGRPd9_5 }, | |
12491 | { FGRPd9_6 }, | |
12492 | { FGRPd9_7 }, | |
12493 | }, | |
12494 | /* da */ | |
12495 | { | |
bf890a93 IT |
12496 | { "fcmovb", { ST, STi }, 0 }, |
12497 | { "fcmove", { ST, STi }, 0 }, | |
12498 | { "fcmovbe",{ ST, STi }, 0 }, | |
12499 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12500 | { Bad_Opcode }, |
252b5132 | 12501 | { FGRPda_5 }, |
592d1631 L |
12502 | { Bad_Opcode }, |
12503 | { Bad_Opcode }, | |
252b5132 RH |
12504 | }, |
12505 | /* db */ | |
12506 | { | |
bf890a93 IT |
12507 | { "fcmovnb",{ ST, STi }, 0 }, |
12508 | { "fcmovne",{ ST, STi }, 0 }, | |
12509 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12510 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12511 | { FGRPdb_4 }, |
bf890a93 IT |
12512 | { "fucomi", { ST, STi }, 0 }, |
12513 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12514 | { Bad_Opcode }, |
252b5132 RH |
12515 | }, |
12516 | /* dc */ | |
12517 | { | |
bf890a93 IT |
12518 | { "fadd", { STi, ST }, 0 }, |
12519 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12520 | { Bad_Opcode }, |
12521 | { Bad_Opcode }, | |
d53e6b98 JB |
12522 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12523 | { "fsub{M|}", { STi, ST }, 0 }, | |
12524 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12525 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12526 | }, |
12527 | /* dd */ | |
12528 | { | |
bf890a93 | 12529 | { "ffree", { STi }, 0 }, |
592d1631 | 12530 | { Bad_Opcode }, |
bf890a93 IT |
12531 | { "fst", { STi }, 0 }, |
12532 | { "fstp", { STi }, 0 }, | |
12533 | { "fucom", { STi }, 0 }, | |
12534 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12535 | { Bad_Opcode }, |
12536 | { Bad_Opcode }, | |
252b5132 RH |
12537 | }, |
12538 | /* de */ | |
12539 | { | |
bf890a93 IT |
12540 | { "faddp", { STi, ST }, 0 }, |
12541 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12542 | { Bad_Opcode }, |
252b5132 | 12543 | { FGRPde_3 }, |
d53e6b98 JB |
12544 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12545 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12546 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12547 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12548 | }, |
12549 | /* df */ | |
12550 | { | |
bf890a93 | 12551 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12552 | { Bad_Opcode }, |
12553 | { Bad_Opcode }, | |
12554 | { Bad_Opcode }, | |
252b5132 | 12555 | { FGRPdf_4 }, |
bf890a93 IT |
12556 | { "fucomip", { ST, STi }, 0 }, |
12557 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12558 | { Bad_Opcode }, |
252b5132 RH |
12559 | }, |
12560 | }; | |
12561 | ||
252b5132 | 12562 | static char *fgrps[][8] = { |
48c97fa1 L |
12563 | /* Bad opcode 0 */ |
12564 | { | |
12565 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12566 | }, | |
12567 | ||
12568 | /* d9_2 1 */ | |
252b5132 RH |
12569 | { |
12570 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12571 | }, | |
12572 | ||
48c97fa1 | 12573 | /* d9_4 2 */ |
252b5132 RH |
12574 | { |
12575 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12576 | }, | |
12577 | ||
48c97fa1 | 12578 | /* d9_5 3 */ |
252b5132 RH |
12579 | { |
12580 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12581 | }, | |
12582 | ||
48c97fa1 | 12583 | /* d9_6 4 */ |
252b5132 RH |
12584 | { |
12585 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12586 | }, | |
12587 | ||
48c97fa1 | 12588 | /* d9_7 5 */ |
252b5132 RH |
12589 | { |
12590 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12591 | }, | |
12592 | ||
48c97fa1 | 12593 | /* da_5 6 */ |
252b5132 RH |
12594 | { |
12595 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12596 | }, | |
12597 | ||
48c97fa1 | 12598 | /* db_4 7 */ |
252b5132 | 12599 | { |
309d3373 JB |
12600 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12601 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12602 | }, |
12603 | ||
48c97fa1 | 12604 | /* de_3 8 */ |
252b5132 RH |
12605 | { |
12606 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12607 | }, | |
12608 | ||
48c97fa1 | 12609 | /* df_4 9 */ |
252b5132 RH |
12610 | { |
12611 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12612 | }, | |
12613 | }; | |
12614 | ||
b6169b20 L |
12615 | static void |
12616 | swap_operand (void) | |
12617 | { | |
12618 | mnemonicendp[0] = '.'; | |
12619 | mnemonicendp[1] = 's'; | |
12620 | mnemonicendp += 2; | |
12621 | } | |
12622 | ||
b844680a L |
12623 | static void |
12624 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12625 | int sizeflag ATTRIBUTE_UNUSED) | |
12626 | { | |
12627 | /* Skip mod/rm byte. */ | |
12628 | MODRM_CHECK; | |
12629 | codep++; | |
12630 | } | |
12631 | ||
252b5132 | 12632 | static void |
26ca5450 | 12633 | dofloat (int sizeflag) |
252b5132 | 12634 | { |
2da11e11 | 12635 | const struct dis386 *dp; |
252b5132 RH |
12636 | unsigned char floatop; |
12637 | ||
12638 | floatop = codep[-1]; | |
12639 | ||
7967e09e | 12640 | if (modrm.mod != 3) |
252b5132 | 12641 | { |
7967e09e | 12642 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12643 | |
12644 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12645 | obufp = op_out[0]; |
6e50d963 | 12646 | op_ad = 2; |
1d9f512f | 12647 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12648 | return; |
12649 | } | |
6608db57 | 12650 | /* Skip mod/rm byte. */ |
4bba6815 | 12651 | MODRM_CHECK; |
252b5132 RH |
12652 | codep++; |
12653 | ||
7967e09e | 12654 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12655 | if (dp->name == NULL) |
12656 | { | |
7967e09e | 12657 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12658 | |
6608db57 | 12659 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12660 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12661 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12662 | } |
12663 | else | |
12664 | { | |
12665 | putop (dp->name, sizeflag); | |
12666 | ||
ce518a5f | 12667 | obufp = op_out[0]; |
6e50d963 | 12668 | op_ad = 2; |
ce518a5f L |
12669 | if (dp->op[0].rtn) |
12670 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12671 | |
ce518a5f | 12672 | obufp = op_out[1]; |
6e50d963 | 12673 | op_ad = 1; |
ce518a5f L |
12674 | if (dp->op[1].rtn) |
12675 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12676 | } |
12677 | } | |
12678 | ||
9ce09ba2 RM |
12679 | /* Like oappend (below), but S is a string starting with '%'. |
12680 | In Intel syntax, the '%' is elided. */ | |
12681 | static void | |
12682 | oappend_maybe_intel (const char *s) | |
12683 | { | |
12684 | oappend (s + intel_syntax); | |
12685 | } | |
12686 | ||
252b5132 | 12687 | static void |
26ca5450 | 12688 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12689 | { |
9ce09ba2 | 12690 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12691 | } |
12692 | ||
252b5132 | 12693 | static void |
26ca5450 | 12694 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12695 | { |
7967e09e | 12696 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12697 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12698 | } |
12699 | ||
6608db57 | 12700 | /* Capital letters in template are macros. */ |
6439fc28 | 12701 | static int |
d3ce72d0 | 12702 | putop (const char *in_template, int sizeflag) |
252b5132 | 12703 | { |
2da11e11 | 12704 | const char *p; |
9306ca4a | 12705 | int alt = 0; |
9d141669 | 12706 | int cond = 1; |
98b528ac L |
12707 | unsigned int l = 0, len = 1; |
12708 | char last[4]; | |
12709 | ||
12710 | #define SAVE_LAST(c) \ | |
12711 | if (l < len && l < sizeof (last)) \ | |
12712 | last[l++] = c; \ | |
12713 | else \ | |
12714 | abort (); | |
252b5132 | 12715 | |
d3ce72d0 | 12716 | for (p = in_template; *p; p++) |
252b5132 RH |
12717 | { |
12718 | switch (*p) | |
12719 | { | |
12720 | default: | |
12721 | *obufp++ = *p; | |
12722 | break; | |
98b528ac L |
12723 | case '%': |
12724 | len++; | |
12725 | break; | |
9d141669 L |
12726 | case '!': |
12727 | cond = 0; | |
12728 | break; | |
6439fc28 | 12729 | case '{': |
6439fc28 | 12730 | if (intel_syntax) |
6439fc28 AM |
12731 | { |
12732 | while (*++p != '|') | |
7c52e0e8 L |
12733 | if (*p == '}' || *p == '\0') |
12734 | abort (); | |
6439fc28 | 12735 | } |
9306ca4a JB |
12736 | /* Fall through. */ |
12737 | case 'I': | |
12738 | alt = 1; | |
12739 | continue; | |
6439fc28 AM |
12740 | case '|': |
12741 | while (*++p != '}') | |
12742 | { | |
12743 | if (*p == '\0') | |
12744 | abort (); | |
12745 | } | |
12746 | break; | |
12747 | case '}': | |
12748 | break; | |
252b5132 | 12749 | case 'A': |
db6eb5be AM |
12750 | if (intel_syntax) |
12751 | break; | |
7967e09e | 12752 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12753 | *obufp++ = 'b'; |
12754 | break; | |
12755 | case 'B': | |
4b06377f L |
12756 | if (l == 0 && len == 1) |
12757 | { | |
dc1e8a47 | 12758 | case_B: |
4b06377f L |
12759 | if (intel_syntax) |
12760 | break; | |
12761 | if (sizeflag & SUFFIX_ALWAYS) | |
12762 | *obufp++ = 'b'; | |
12763 | } | |
12764 | else | |
12765 | { | |
12766 | if (l != 1 | |
12767 | || len != 2 | |
12768 | || last[0] != 'L') | |
12769 | { | |
12770 | SAVE_LAST (*p); | |
12771 | break; | |
12772 | } | |
12773 | ||
12774 | if (address_mode == mode_64bit | |
12775 | && !(prefixes & PREFIX_ADDR)) | |
12776 | { | |
12777 | *obufp++ = 'a'; | |
12778 | *obufp++ = 'b'; | |
12779 | *obufp++ = 's'; | |
12780 | } | |
12781 | ||
12782 | goto case_B; | |
12783 | } | |
252b5132 | 12784 | break; |
9306ca4a JB |
12785 | case 'C': |
12786 | if (intel_syntax && !alt) | |
12787 | break; | |
12788 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12789 | { | |
12790 | if (sizeflag & DFLAG) | |
12791 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12792 | else | |
12793 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12794 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12795 | } | |
12796 | break; | |
ed7841b3 JB |
12797 | case 'D': |
12798 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12799 | break; | |
161a04f6 | 12800 | USED_REX (REX_W); |
7967e09e | 12801 | if (modrm.mod == 3) |
ed7841b3 | 12802 | { |
161a04f6 | 12803 | if (rex & REX_W) |
ed7841b3 | 12804 | *obufp++ = 'q'; |
ed7841b3 | 12805 | else |
f16cd0d5 L |
12806 | { |
12807 | if (sizeflag & DFLAG) | |
12808 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12809 | else | |
12810 | *obufp++ = 'w'; | |
12811 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12812 | } | |
ed7841b3 JB |
12813 | } |
12814 | else | |
12815 | *obufp++ = 'w'; | |
12816 | break; | |
252b5132 | 12817 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12818 | if (address_mode == mode_64bit) |
c1a64871 JH |
12819 | { |
12820 | if (sizeflag & AFLAG) | |
12821 | *obufp++ = 'r'; | |
12822 | else | |
12823 | *obufp++ = 'e'; | |
12824 | } | |
12825 | else | |
12826 | if (sizeflag & AFLAG) | |
12827 | *obufp++ = 'e'; | |
3ffd33cf AM |
12828 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12829 | break; | |
12830 | case 'F': | |
db6eb5be AM |
12831 | if (intel_syntax) |
12832 | break; | |
e396998b | 12833 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12834 | { |
12835 | if (sizeflag & AFLAG) | |
cb712a9e | 12836 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12837 | else |
cb712a9e | 12838 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12839 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12840 | } | |
252b5132 | 12841 | break; |
52fd6d94 JB |
12842 | case 'G': |
12843 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12844 | break; | |
161a04f6 | 12845 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12846 | *obufp++ = 'l'; |
12847 | else | |
12848 | *obufp++ = 'w'; | |
161a04f6 | 12849 | if (!(rex & REX_W)) |
52fd6d94 JB |
12850 | used_prefixes |= (prefixes & PREFIX_DATA); |
12851 | break; | |
5dd0794d | 12852 | case 'H': |
db6eb5be AM |
12853 | if (intel_syntax) |
12854 | break; | |
5dd0794d AM |
12855 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12856 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12857 | { | |
12858 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12859 | *obufp++ = ','; | |
12860 | *obufp++ = 'p'; | |
12861 | if (prefixes & PREFIX_DS) | |
12862 | *obufp++ = 't'; | |
12863 | else | |
12864 | *obufp++ = 'n'; | |
12865 | } | |
12866 | break; | |
9306ca4a JB |
12867 | case 'J': |
12868 | if (intel_syntax) | |
12869 | break; | |
12870 | *obufp++ = 'l'; | |
12871 | break; | |
42903f7f L |
12872 | case 'K': |
12873 | USED_REX (REX_W); | |
12874 | if (rex & REX_W) | |
12875 | *obufp++ = 'q'; | |
12876 | else | |
12877 | *obufp++ = 'd'; | |
12878 | break; | |
6dd5059a | 12879 | case 'Z': |
04d824a4 JB |
12880 | if (l != 0 || len != 1) |
12881 | { | |
12882 | if (l != 1 || len != 2 || last[0] != 'X') | |
12883 | { | |
12884 | SAVE_LAST (*p); | |
12885 | break; | |
12886 | } | |
12887 | if (!need_vex || !vex.evex) | |
12888 | abort (); | |
12889 | if (intel_syntax | |
12890 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12891 | break; | |
12892 | switch (vex.length) | |
12893 | { | |
12894 | case 128: | |
12895 | *obufp++ = 'x'; | |
12896 | break; | |
12897 | case 256: | |
12898 | *obufp++ = 'y'; | |
12899 | break; | |
12900 | case 512: | |
12901 | *obufp++ = 'z'; | |
12902 | break; | |
12903 | default: | |
12904 | abort (); | |
12905 | } | |
12906 | break; | |
12907 | } | |
6dd5059a L |
12908 | if (intel_syntax) |
12909 | break; | |
12910 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12911 | { | |
12912 | *obufp++ = 'q'; | |
12913 | break; | |
12914 | } | |
12915 | /* Fall through. */ | |
98b528ac | 12916 | goto case_L; |
252b5132 | 12917 | case 'L': |
98b528ac L |
12918 | if (l != 0 || len != 1) |
12919 | { | |
12920 | SAVE_LAST (*p); | |
12921 | break; | |
12922 | } | |
dc1e8a47 | 12923 | case_L: |
db6eb5be AM |
12924 | if (intel_syntax) |
12925 | break; | |
252b5132 RH |
12926 | if (sizeflag & SUFFIX_ALWAYS) |
12927 | *obufp++ = 'l'; | |
252b5132 | 12928 | break; |
9d141669 L |
12929 | case 'M': |
12930 | if (intel_mnemonic != cond) | |
12931 | *obufp++ = 'r'; | |
12932 | break; | |
252b5132 RH |
12933 | case 'N': |
12934 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12935 | *obufp++ = 'n'; | |
7d421014 ILT |
12936 | else |
12937 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12938 | break; |
52b15da3 | 12939 | case 'O': |
161a04f6 L |
12940 | USED_REX (REX_W); |
12941 | if (rex & REX_W) | |
6439fc28 | 12942 | *obufp++ = 'o'; |
a35ca55a JB |
12943 | else if (intel_syntax && (sizeflag & DFLAG)) |
12944 | *obufp++ = 'q'; | |
52b15da3 JH |
12945 | else |
12946 | *obufp++ = 'd'; | |
161a04f6 | 12947 | if (!(rex & REX_W)) |
a35ca55a | 12948 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12949 | break; |
07f5af7d L |
12950 | case '&': |
12951 | if (!intel_syntax | |
12952 | && address_mode == mode_64bit | |
12953 | && isa64 == intel64) | |
12954 | { | |
12955 | *obufp++ = 'q'; | |
12956 | break; | |
12957 | } | |
12958 | /* Fall through. */ | |
6439fc28 | 12959 | case 'T': |
d9e3625e L |
12960 | if (!intel_syntax |
12961 | && address_mode == mode_64bit | |
7bb15c6f | 12962 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12963 | { |
12964 | *obufp++ = 'q'; | |
12965 | break; | |
12966 | } | |
6608db57 | 12967 | /* Fall through. */ |
4b4c407a | 12968 | goto case_P; |
252b5132 | 12969 | case 'P': |
4b4c407a | 12970 | if (l == 0 && len == 1) |
d9e3625e | 12971 | { |
dc1e8a47 | 12972 | case_P: |
4b4c407a | 12973 | if (intel_syntax) |
d9e3625e | 12974 | { |
4b4c407a L |
12975 | if ((rex & REX_W) == 0 |
12976 | && (prefixes & PREFIX_DATA)) | |
12977 | { | |
12978 | if ((sizeflag & DFLAG) == 0) | |
12979 | *obufp++ = 'w'; | |
12980 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12981 | } | |
12982 | break; | |
12983 | } | |
12984 | if ((prefixes & PREFIX_DATA) | |
12985 | || (rex & REX_W) | |
12986 | || (sizeflag & SUFFIX_ALWAYS)) | |
12987 | { | |
12988 | USED_REX (REX_W); | |
12989 | if (rex & REX_W) | |
12990 | *obufp++ = 'q'; | |
12991 | else | |
12992 | { | |
12993 | if (sizeflag & DFLAG) | |
12994 | *obufp++ = 'l'; | |
12995 | else | |
12996 | *obufp++ = 'w'; | |
12997 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12998 | } | |
d9e3625e | 12999 | } |
d9e3625e | 13000 | } |
4b4c407a | 13001 | else |
252b5132 | 13002 | { |
4b4c407a L |
13003 | if (l != 1 || len != 2 || last[0] != 'L') |
13004 | { | |
13005 | SAVE_LAST (*p); | |
13006 | break; | |
13007 | } | |
13008 | ||
13009 | if ((prefixes & PREFIX_DATA) | |
13010 | || (rex & REX_W) | |
13011 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13012 | { |
4b4c407a L |
13013 | USED_REX (REX_W); |
13014 | if (rex & REX_W) | |
13015 | *obufp++ = 'q'; | |
13016 | else | |
13017 | { | |
13018 | if (sizeflag & DFLAG) | |
13019 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13020 | else | |
13021 | *obufp++ = 'w'; | |
13022 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13023 | } | |
52b15da3 | 13024 | } |
252b5132 RH |
13025 | } |
13026 | break; | |
6439fc28 | 13027 | case 'U': |
db6eb5be AM |
13028 | if (intel_syntax) |
13029 | break; | |
7bb15c6f | 13030 | if (address_mode == mode_64bit |
6c067bbb | 13031 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13032 | { |
7967e09e | 13033 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13034 | *obufp++ = 'q'; |
6439fc28 AM |
13035 | break; |
13036 | } | |
6608db57 | 13037 | /* Fall through. */ |
98b528ac | 13038 | goto case_Q; |
252b5132 | 13039 | case 'Q': |
98b528ac | 13040 | if (l == 0 && len == 1) |
252b5132 | 13041 | { |
dc1e8a47 | 13042 | case_Q: |
98b528ac L |
13043 | if (intel_syntax && !alt) |
13044 | break; | |
13045 | USED_REX (REX_W); | |
13046 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13047 | { |
98b528ac L |
13048 | if (rex & REX_W) |
13049 | *obufp++ = 'q'; | |
52b15da3 | 13050 | else |
98b528ac L |
13051 | { |
13052 | if (sizeflag & DFLAG) | |
13053 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13054 | else | |
13055 | *obufp++ = 'w'; | |
f16cd0d5 | 13056 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13057 | } |
52b15da3 | 13058 | } |
98b528ac L |
13059 | } |
13060 | else | |
13061 | { | |
13062 | if (l != 1 || len != 2 || last[0] != 'L') | |
13063 | { | |
13064 | SAVE_LAST (*p); | |
13065 | break; | |
13066 | } | |
13067 | if (intel_syntax | |
13068 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13069 | break; | |
13070 | if ((rex & REX_W)) | |
13071 | { | |
13072 | USED_REX (REX_W); | |
13073 | *obufp++ = 'q'; | |
13074 | } | |
13075 | else | |
13076 | *obufp++ = 'l'; | |
252b5132 RH |
13077 | } |
13078 | break; | |
13079 | case 'R': | |
161a04f6 L |
13080 | USED_REX (REX_W); |
13081 | if (rex & REX_W) | |
a35ca55a JB |
13082 | *obufp++ = 'q'; |
13083 | else if (sizeflag & DFLAG) | |
c608c12e | 13084 | { |
a35ca55a | 13085 | if (intel_syntax) |
c608c12e | 13086 | *obufp++ = 'd'; |
c608c12e | 13087 | else |
a35ca55a | 13088 | *obufp++ = 'l'; |
c608c12e | 13089 | } |
252b5132 | 13090 | else |
a35ca55a JB |
13091 | *obufp++ = 'w'; |
13092 | if (intel_syntax && !p[1] | |
161a04f6 | 13093 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13094 | *obufp++ = 'e'; |
161a04f6 | 13095 | if (!(rex & REX_W)) |
52b15da3 | 13096 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13097 | break; |
1a114b12 | 13098 | case 'V': |
4b06377f | 13099 | if (l == 0 && len == 1) |
1a114b12 | 13100 | { |
4b06377f L |
13101 | if (intel_syntax) |
13102 | break; | |
7bb15c6f | 13103 | if (address_mode == mode_64bit |
6c067bbb | 13104 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13105 | { |
13106 | if (sizeflag & SUFFIX_ALWAYS) | |
13107 | *obufp++ = 'q'; | |
13108 | break; | |
13109 | } | |
13110 | } | |
13111 | else | |
13112 | { | |
13113 | if (l != 1 | |
13114 | || len != 2 | |
13115 | || last[0] != 'L') | |
13116 | { | |
13117 | SAVE_LAST (*p); | |
13118 | break; | |
13119 | } | |
13120 | ||
13121 | if (rex & REX_W) | |
13122 | { | |
13123 | *obufp++ = 'a'; | |
13124 | *obufp++ = 'b'; | |
13125 | *obufp++ = 's'; | |
13126 | } | |
1a114b12 JB |
13127 | } |
13128 | /* Fall through. */ | |
4b06377f | 13129 | goto case_S; |
252b5132 | 13130 | case 'S': |
4b06377f | 13131 | if (l == 0 && len == 1) |
252b5132 | 13132 | { |
dc1e8a47 | 13133 | case_S: |
4b06377f L |
13134 | if (intel_syntax) |
13135 | break; | |
13136 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13137 | { |
4b06377f L |
13138 | if (rex & REX_W) |
13139 | *obufp++ = 'q'; | |
52b15da3 | 13140 | else |
4b06377f L |
13141 | { |
13142 | if (sizeflag & DFLAG) | |
13143 | *obufp++ = 'l'; | |
13144 | else | |
13145 | *obufp++ = 'w'; | |
13146 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13147 | } | |
13148 | } | |
13149 | } | |
13150 | else | |
13151 | { | |
13152 | if (l != 1 | |
13153 | || len != 2 | |
13154 | || last[0] != 'L') | |
13155 | { | |
13156 | SAVE_LAST (*p); | |
13157 | break; | |
52b15da3 | 13158 | } |
4b06377f L |
13159 | |
13160 | if (address_mode == mode_64bit | |
13161 | && !(prefixes & PREFIX_ADDR)) | |
13162 | { | |
13163 | *obufp++ = 'a'; | |
13164 | *obufp++ = 'b'; | |
13165 | *obufp++ = 's'; | |
13166 | } | |
13167 | ||
13168 | goto case_S; | |
252b5132 | 13169 | } |
252b5132 | 13170 | break; |
041bd2e0 | 13171 | case 'X': |
c0f3af97 L |
13172 | if (l != 0 || len != 1) |
13173 | { | |
13174 | SAVE_LAST (*p); | |
13175 | break; | |
13176 | } | |
bf926894 JB |
13177 | if (need_vex |
13178 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13179 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13180 | { |
bf926894 JB |
13181 | *obufp++ = 'd'; |
13182 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13183 | } |
041bd2e0 | 13184 | else |
bf926894 | 13185 | *obufp++ = 's'; |
041bd2e0 | 13186 | break; |
76f227a5 | 13187 | case 'Y': |
c0f3af97 | 13188 | if (l == 0 && len == 1) |
9646c87b | 13189 | abort (); |
c0f3af97 L |
13190 | else |
13191 | { | |
13192 | if (l != 1 || len != 2 || last[0] != 'X') | |
13193 | { | |
13194 | SAVE_LAST (*p); | |
13195 | break; | |
13196 | } | |
13197 | if (!need_vex) | |
13198 | abort (); | |
13199 | if (intel_syntax | |
04d824a4 | 13200 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13201 | break; |
13202 | switch (vex.length) | |
13203 | { | |
13204 | case 128: | |
13205 | *obufp++ = 'x'; | |
13206 | break; | |
13207 | case 256: | |
13208 | *obufp++ = 'y'; | |
13209 | break; | |
04d824a4 JB |
13210 | case 512: |
13211 | if (!vex.evex) | |
c0f3af97 | 13212 | default: |
04d824a4 | 13213 | abort (); |
c0f3af97 | 13214 | } |
76f227a5 JH |
13215 | } |
13216 | break; | |
252b5132 | 13217 | case 'W': |
0bfee649 | 13218 | if (l == 0 && len == 1) |
a35ca55a | 13219 | { |
0bfee649 L |
13220 | /* operand size flag for cwtl, cbtw */ |
13221 | USED_REX (REX_W); | |
13222 | if (rex & REX_W) | |
13223 | { | |
13224 | if (intel_syntax) | |
13225 | *obufp++ = 'd'; | |
13226 | else | |
13227 | *obufp++ = 'l'; | |
13228 | } | |
13229 | else if (sizeflag & DFLAG) | |
13230 | *obufp++ = 'w'; | |
a35ca55a | 13231 | else |
0bfee649 L |
13232 | *obufp++ = 'b'; |
13233 | if (!(rex & REX_W)) | |
13234 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13235 | } |
252b5132 | 13236 | else |
0bfee649 | 13237 | { |
6c30d220 L |
13238 | if (l != 1 |
13239 | || len != 2 | |
13240 | || (last[0] != 'X' | |
13241 | && last[0] != 'L')) | |
0bfee649 L |
13242 | { |
13243 | SAVE_LAST (*p); | |
13244 | break; | |
13245 | } | |
13246 | if (!need_vex) | |
13247 | abort (); | |
6c30d220 L |
13248 | if (last[0] == 'X') |
13249 | *obufp++ = vex.w ? 'd': 's'; | |
13250 | else | |
13251 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13252 | } |
252b5132 | 13253 | break; |
a72d2af2 L |
13254 | case '^': |
13255 | if (intel_syntax) | |
13256 | break; | |
5990e377 JB |
13257 | if (isa64 == intel64 && (rex & REX_W)) |
13258 | { | |
13259 | USED_REX (REX_W); | |
13260 | *obufp++ = 'q'; | |
13261 | break; | |
13262 | } | |
a72d2af2 L |
13263 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13264 | { | |
13265 | if (sizeflag & DFLAG) | |
13266 | *obufp++ = 'l'; | |
13267 | else | |
13268 | *obufp++ = 'w'; | |
13269 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13270 | } | |
13271 | break; | |
5db04b09 L |
13272 | case '@': |
13273 | if (intel_syntax) | |
13274 | break; | |
13275 | if (address_mode == mode_64bit | |
13276 | && (isa64 == intel64 | |
13277 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13278 | *obufp++ = 'q'; | |
13279 | else if ((prefixes & PREFIX_DATA)) | |
13280 | { | |
13281 | if (!(sizeflag & DFLAG)) | |
13282 | *obufp++ = 'w'; | |
13283 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13284 | } | |
13285 | break; | |
252b5132 | 13286 | } |
9306ca4a | 13287 | alt = 0; |
252b5132 RH |
13288 | } |
13289 | *obufp = 0; | |
ea397f5b | 13290 | mnemonicendp = obufp; |
6439fc28 | 13291 | return 0; |
252b5132 RH |
13292 | } |
13293 | ||
13294 | static void | |
26ca5450 | 13295 | oappend (const char *s) |
252b5132 | 13296 | { |
ea397f5b | 13297 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13298 | } |
13299 | ||
13300 | static void | |
26ca5450 | 13301 | append_seg (void) |
252b5132 | 13302 | { |
285ca992 L |
13303 | /* Only print the active segment register. */ |
13304 | if (!active_seg_prefix) | |
13305 | return; | |
13306 | ||
13307 | used_prefixes |= active_seg_prefix; | |
13308 | switch (active_seg_prefix) | |
7d421014 | 13309 | { |
285ca992 | 13310 | case PREFIX_CS: |
9ce09ba2 | 13311 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13312 | break; |
13313 | case PREFIX_DS: | |
9ce09ba2 | 13314 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13315 | break; |
13316 | case PREFIX_SS: | |
9ce09ba2 | 13317 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13318 | break; |
13319 | case PREFIX_ES: | |
9ce09ba2 | 13320 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13321 | break; |
13322 | case PREFIX_FS: | |
9ce09ba2 | 13323 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13324 | break; |
13325 | case PREFIX_GS: | |
9ce09ba2 | 13326 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13327 | break; |
13328 | default: | |
13329 | break; | |
7d421014 | 13330 | } |
252b5132 RH |
13331 | } |
13332 | ||
13333 | static void | |
26ca5450 | 13334 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13335 | { |
13336 | if (!intel_syntax) | |
13337 | oappend ("*"); | |
13338 | OP_E (bytemode, sizeflag); | |
13339 | } | |
13340 | ||
52b15da3 | 13341 | static void |
26ca5450 | 13342 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13343 | { |
cb712a9e | 13344 | if (address_mode == mode_64bit) |
52b15da3 JH |
13345 | { |
13346 | if (hex) | |
13347 | { | |
13348 | char tmp[30]; | |
13349 | int i; | |
13350 | buf[0] = '0'; | |
13351 | buf[1] = 'x'; | |
13352 | sprintf_vma (tmp, disp); | |
6608db57 | 13353 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13354 | strcpy (buf + 2, tmp + i); |
13355 | } | |
13356 | else | |
13357 | { | |
13358 | bfd_signed_vma v = disp; | |
13359 | char tmp[30]; | |
13360 | int i; | |
13361 | if (v < 0) | |
13362 | { | |
13363 | *(buf++) = '-'; | |
13364 | v = -disp; | |
6608db57 | 13365 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13366 | if (v < 0) |
13367 | { | |
13368 | strcpy (buf, "9223372036854775808"); | |
13369 | return; | |
13370 | } | |
13371 | } | |
13372 | if (!v) | |
13373 | { | |
13374 | strcpy (buf, "0"); | |
13375 | return; | |
13376 | } | |
13377 | ||
13378 | i = 0; | |
13379 | tmp[29] = 0; | |
13380 | while (v) | |
13381 | { | |
6608db57 | 13382 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13383 | v /= 10; |
13384 | i++; | |
13385 | } | |
13386 | strcpy (buf, tmp + 29 - i); | |
13387 | } | |
13388 | } | |
13389 | else | |
13390 | { | |
13391 | if (hex) | |
13392 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13393 | else | |
13394 | sprintf (buf, "%d", (int) disp); | |
13395 | } | |
13396 | } | |
13397 | ||
5d669648 L |
13398 | /* Put DISP in BUF as signed hex number. */ |
13399 | ||
13400 | static void | |
13401 | print_displacement (char *buf, bfd_vma disp) | |
13402 | { | |
13403 | bfd_signed_vma val = disp; | |
13404 | char tmp[30]; | |
13405 | int i, j = 0; | |
13406 | ||
13407 | if (val < 0) | |
13408 | { | |
13409 | buf[j++] = '-'; | |
13410 | val = -disp; | |
13411 | ||
13412 | /* Check for possible overflow. */ | |
13413 | if (val < 0) | |
13414 | { | |
13415 | switch (address_mode) | |
13416 | { | |
13417 | case mode_64bit: | |
13418 | strcpy (buf + j, "0x8000000000000000"); | |
13419 | break; | |
13420 | case mode_32bit: | |
13421 | strcpy (buf + j, "0x80000000"); | |
13422 | break; | |
13423 | case mode_16bit: | |
13424 | strcpy (buf + j, "0x8000"); | |
13425 | break; | |
13426 | } | |
13427 | return; | |
13428 | } | |
13429 | } | |
13430 | ||
13431 | buf[j++] = '0'; | |
13432 | buf[j++] = 'x'; | |
13433 | ||
0af1713e | 13434 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13435 | for (i = 0; tmp[i] == '0'; i++) |
13436 | continue; | |
13437 | if (tmp[i] == '\0') | |
13438 | i--; | |
13439 | strcpy (buf + j, tmp + i); | |
13440 | } | |
13441 | ||
3f31e633 JB |
13442 | static void |
13443 | intel_operand_size (int bytemode, int sizeflag) | |
13444 | { | |
43234a1e L |
13445 | if (vex.evex |
13446 | && vex.b | |
13447 | && (bytemode == x_mode | |
13448 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13449 | { | |
13450 | if (vex.w) | |
13451 | oappend ("QWORD PTR "); | |
13452 | else | |
13453 | oappend ("DWORD PTR "); | |
13454 | return; | |
13455 | } | |
3f31e633 JB |
13456 | switch (bytemode) |
13457 | { | |
13458 | case b_mode: | |
b6169b20 | 13459 | case b_swap_mode: |
42903f7f | 13460 | case dqb_mode: |
1ba585e8 | 13461 | case db_mode: |
3f31e633 JB |
13462 | oappend ("BYTE PTR "); |
13463 | break; | |
13464 | case w_mode: | |
1ba585e8 | 13465 | case dw_mode: |
3f31e633 JB |
13466 | case dqw_mode: |
13467 | oappend ("WORD PTR "); | |
13468 | break; | |
07f5af7d L |
13469 | case indir_v_mode: |
13470 | if (address_mode == mode_64bit && isa64 == intel64) | |
13471 | { | |
13472 | oappend ("QWORD PTR "); | |
13473 | break; | |
13474 | } | |
1a0670f3 | 13475 | /* Fall through. */ |
1a114b12 | 13476 | case stack_v_mode: |
7bb15c6f | 13477 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13478 | { |
13479 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13480 | break; |
13481 | } | |
1a0670f3 | 13482 | /* Fall through. */ |
3f31e633 | 13483 | case v_mode: |
b6169b20 | 13484 | case v_swap_mode: |
3f31e633 | 13485 | case dq_mode: |
161a04f6 L |
13486 | USED_REX (REX_W); |
13487 | if (rex & REX_W) | |
3f31e633 | 13488 | oappend ("QWORD PTR "); |
3f31e633 | 13489 | else |
f16cd0d5 L |
13490 | { |
13491 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13492 | oappend ("DWORD PTR "); | |
13493 | else | |
13494 | oappend ("WORD PTR "); | |
13495 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13496 | } | |
3f31e633 | 13497 | break; |
52fd6d94 | 13498 | case z_mode: |
161a04f6 | 13499 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13500 | *obufp++ = 'D'; |
13501 | oappend ("WORD PTR "); | |
161a04f6 | 13502 | if (!(rex & REX_W)) |
52fd6d94 JB |
13503 | used_prefixes |= (prefixes & PREFIX_DATA); |
13504 | break; | |
34b772a6 JB |
13505 | case a_mode: |
13506 | if (sizeflag & DFLAG) | |
13507 | oappend ("QWORD PTR "); | |
13508 | else | |
13509 | oappend ("DWORD PTR "); | |
13510 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13511 | break; | |
bc31405e L |
13512 | case movsxd_mode: |
13513 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13514 | oappend ("WORD PTR "); | |
13515 | else | |
13516 | oappend ("DWORD PTR "); | |
13517 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13518 | break; | |
3f31e633 | 13519 | case d_mode: |
539f890d L |
13520 | case d_scalar_mode: |
13521 | case d_scalar_swap_mode: | |
fa99fab2 | 13522 | case d_swap_mode: |
42903f7f | 13523 | case dqd_mode: |
3f31e633 JB |
13524 | oappend ("DWORD PTR "); |
13525 | break; | |
13526 | case q_mode: | |
539f890d L |
13527 | case q_scalar_mode: |
13528 | case q_scalar_swap_mode: | |
b6169b20 | 13529 | case q_swap_mode: |
3f31e633 JB |
13530 | oappend ("QWORD PTR "); |
13531 | break; | |
13532 | case m_mode: | |
cb712a9e | 13533 | if (address_mode == mode_64bit) |
3f31e633 JB |
13534 | oappend ("QWORD PTR "); |
13535 | else | |
13536 | oappend ("DWORD PTR "); | |
13537 | break; | |
13538 | case f_mode: | |
13539 | if (sizeflag & DFLAG) | |
13540 | oappend ("FWORD PTR "); | |
13541 | else | |
13542 | oappend ("DWORD PTR "); | |
13543 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13544 | break; | |
13545 | case t_mode: | |
13546 | oappend ("TBYTE PTR "); | |
13547 | break; | |
13548 | case x_mode: | |
b6169b20 | 13549 | case x_swap_mode: |
43234a1e L |
13550 | case evex_x_gscat_mode: |
13551 | case evex_x_nobcst_mode: | |
53467f57 IT |
13552 | case b_scalar_mode: |
13553 | case w_scalar_mode: | |
c0f3af97 L |
13554 | if (need_vex) |
13555 | { | |
13556 | switch (vex.length) | |
13557 | { | |
13558 | case 128: | |
13559 | oappend ("XMMWORD PTR "); | |
13560 | break; | |
13561 | case 256: | |
13562 | oappend ("YMMWORD PTR "); | |
13563 | break; | |
43234a1e L |
13564 | case 512: |
13565 | oappend ("ZMMWORD PTR "); | |
13566 | break; | |
c0f3af97 L |
13567 | default: |
13568 | abort (); | |
13569 | } | |
13570 | } | |
13571 | else | |
13572 | oappend ("XMMWORD PTR "); | |
13573 | break; | |
13574 | case xmm_mode: | |
3f31e633 JB |
13575 | oappend ("XMMWORD PTR "); |
13576 | break; | |
43234a1e L |
13577 | case ymm_mode: |
13578 | oappend ("YMMWORD PTR "); | |
13579 | break; | |
c0f3af97 | 13580 | case xmmq_mode: |
43234a1e | 13581 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13582 | if (!need_vex) |
13583 | abort (); | |
13584 | ||
13585 | switch (vex.length) | |
13586 | { | |
13587 | case 128: | |
13588 | oappend ("QWORD PTR "); | |
13589 | break; | |
13590 | case 256: | |
13591 | oappend ("XMMWORD PTR "); | |
13592 | break; | |
43234a1e L |
13593 | case 512: |
13594 | oappend ("YMMWORD PTR "); | |
13595 | break; | |
c0f3af97 L |
13596 | default: |
13597 | abort (); | |
13598 | } | |
13599 | break; | |
6c30d220 L |
13600 | case xmm_mb_mode: |
13601 | if (!need_vex) | |
13602 | abort (); | |
13603 | ||
13604 | switch (vex.length) | |
13605 | { | |
13606 | case 128: | |
13607 | case 256: | |
43234a1e | 13608 | case 512: |
6c30d220 L |
13609 | oappend ("BYTE PTR "); |
13610 | break; | |
13611 | default: | |
13612 | abort (); | |
13613 | } | |
13614 | break; | |
13615 | case xmm_mw_mode: | |
13616 | if (!need_vex) | |
13617 | abort (); | |
13618 | ||
13619 | switch (vex.length) | |
13620 | { | |
13621 | case 128: | |
13622 | case 256: | |
43234a1e | 13623 | case 512: |
6c30d220 L |
13624 | oappend ("WORD PTR "); |
13625 | break; | |
13626 | default: | |
13627 | abort (); | |
13628 | } | |
13629 | break; | |
13630 | case xmm_md_mode: | |
13631 | if (!need_vex) | |
13632 | abort (); | |
13633 | ||
13634 | switch (vex.length) | |
13635 | { | |
13636 | case 128: | |
13637 | case 256: | |
43234a1e | 13638 | case 512: |
6c30d220 L |
13639 | oappend ("DWORD PTR "); |
13640 | break; | |
13641 | default: | |
13642 | abort (); | |
13643 | } | |
13644 | break; | |
13645 | case xmm_mq_mode: | |
13646 | if (!need_vex) | |
13647 | abort (); | |
13648 | ||
13649 | switch (vex.length) | |
13650 | { | |
13651 | case 128: | |
13652 | case 256: | |
43234a1e | 13653 | case 512: |
6c30d220 L |
13654 | oappend ("QWORD PTR "); |
13655 | break; | |
13656 | default: | |
13657 | abort (); | |
13658 | } | |
13659 | break; | |
13660 | case xmmdw_mode: | |
13661 | if (!need_vex) | |
13662 | abort (); | |
13663 | ||
13664 | switch (vex.length) | |
13665 | { | |
13666 | case 128: | |
13667 | oappend ("WORD PTR "); | |
13668 | break; | |
13669 | case 256: | |
13670 | oappend ("DWORD PTR "); | |
13671 | break; | |
43234a1e L |
13672 | case 512: |
13673 | oappend ("QWORD PTR "); | |
13674 | break; | |
6c30d220 L |
13675 | default: |
13676 | abort (); | |
13677 | } | |
13678 | break; | |
13679 | case xmmqd_mode: | |
13680 | if (!need_vex) | |
13681 | abort (); | |
13682 | ||
13683 | switch (vex.length) | |
13684 | { | |
13685 | case 128: | |
13686 | oappend ("DWORD PTR "); | |
13687 | break; | |
13688 | case 256: | |
13689 | oappend ("QWORD PTR "); | |
13690 | break; | |
43234a1e L |
13691 | case 512: |
13692 | oappend ("XMMWORD PTR "); | |
13693 | break; | |
6c30d220 L |
13694 | default: |
13695 | abort (); | |
13696 | } | |
13697 | break; | |
c0f3af97 L |
13698 | case ymmq_mode: |
13699 | if (!need_vex) | |
13700 | abort (); | |
13701 | ||
13702 | switch (vex.length) | |
13703 | { | |
13704 | case 128: | |
13705 | oappend ("QWORD PTR "); | |
13706 | break; | |
13707 | case 256: | |
13708 | oappend ("YMMWORD PTR "); | |
13709 | break; | |
43234a1e L |
13710 | case 512: |
13711 | oappend ("ZMMWORD PTR "); | |
13712 | break; | |
c0f3af97 L |
13713 | default: |
13714 | abort (); | |
13715 | } | |
13716 | break; | |
6c30d220 L |
13717 | case ymmxmm_mode: |
13718 | if (!need_vex) | |
13719 | abort (); | |
13720 | ||
13721 | switch (vex.length) | |
13722 | { | |
13723 | case 128: | |
13724 | case 256: | |
13725 | oappend ("XMMWORD PTR "); | |
13726 | break; | |
13727 | default: | |
13728 | abort (); | |
13729 | } | |
13730 | break; | |
fb9c77c7 L |
13731 | case o_mode: |
13732 | oappend ("OWORD PTR "); | |
13733 | break; | |
1c480963 | 13734 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13735 | if (!need_vex) |
13736 | abort (); | |
13737 | ||
13738 | if (vex.w) | |
13739 | oappend ("QWORD PTR "); | |
13740 | else | |
13741 | oappend ("DWORD PTR "); | |
13742 | break; | |
43234a1e L |
13743 | case vex_vsib_d_w_dq_mode: |
13744 | case vex_vsib_q_w_dq_mode: | |
13745 | if (!need_vex) | |
13746 | abort (); | |
13747 | ||
13748 | if (!vex.evex) | |
13749 | { | |
13750 | if (vex.w) | |
13751 | oappend ("QWORD PTR "); | |
13752 | else | |
13753 | oappend ("DWORD PTR "); | |
13754 | } | |
13755 | else | |
13756 | { | |
b28d1bda IT |
13757 | switch (vex.length) |
13758 | { | |
13759 | case 128: | |
13760 | oappend ("XMMWORD PTR "); | |
13761 | break; | |
13762 | case 256: | |
13763 | oappend ("YMMWORD PTR "); | |
13764 | break; | |
13765 | case 512: | |
13766 | oappend ("ZMMWORD PTR "); | |
13767 | break; | |
13768 | default: | |
13769 | abort (); | |
13770 | } | |
43234a1e L |
13771 | } |
13772 | break; | |
5fc35d96 IT |
13773 | case vex_vsib_q_w_d_mode: |
13774 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13775 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13776 | abort (); |
13777 | ||
b28d1bda IT |
13778 | switch (vex.length) |
13779 | { | |
13780 | case 128: | |
13781 | oappend ("QWORD PTR "); | |
13782 | break; | |
13783 | case 256: | |
13784 | oappend ("XMMWORD PTR "); | |
13785 | break; | |
13786 | case 512: | |
13787 | oappend ("YMMWORD PTR "); | |
13788 | break; | |
13789 | default: | |
13790 | abort (); | |
13791 | } | |
5fc35d96 IT |
13792 | |
13793 | break; | |
1ba585e8 IT |
13794 | case mask_bd_mode: |
13795 | if (!need_vex || vex.length != 128) | |
13796 | abort (); | |
13797 | if (vex.w) | |
13798 | oappend ("DWORD PTR "); | |
13799 | else | |
13800 | oappend ("BYTE PTR "); | |
13801 | break; | |
43234a1e L |
13802 | case mask_mode: |
13803 | if (!need_vex) | |
13804 | abort (); | |
1ba585e8 IT |
13805 | if (vex.w) |
13806 | oappend ("QWORD PTR "); | |
13807 | else | |
13808 | oappend ("WORD PTR "); | |
43234a1e | 13809 | break; |
6c75cc62 | 13810 | case v_bnd_mode: |
d276ec69 | 13811 | case v_bndmk_mode: |
3f31e633 JB |
13812 | default: |
13813 | break; | |
13814 | } | |
13815 | } | |
13816 | ||
252b5132 | 13817 | static void |
c0f3af97 | 13818 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13819 | { |
c0f3af97 L |
13820 | int reg = modrm.rm; |
13821 | const char **names; | |
252b5132 | 13822 | |
c0f3af97 L |
13823 | USED_REX (REX_B); |
13824 | if ((rex & REX_B)) | |
13825 | reg += 8; | |
252b5132 | 13826 | |
b6169b20 | 13827 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13828 | && (bytemode == b_swap_mode |
9f79e886 | 13829 | || bytemode == bnd_swap_mode |
60227d64 | 13830 | || bytemode == v_swap_mode)) |
b6169b20 L |
13831 | swap_operand (); |
13832 | ||
c0f3af97 | 13833 | switch (bytemode) |
252b5132 | 13834 | { |
c0f3af97 | 13835 | case b_mode: |
b6169b20 | 13836 | case b_swap_mode: |
c0f3af97 L |
13837 | USED_REX (0); |
13838 | if (rex) | |
13839 | names = names8rex; | |
13840 | else | |
13841 | names = names8; | |
13842 | break; | |
13843 | case w_mode: | |
13844 | names = names16; | |
13845 | break; | |
13846 | case d_mode: | |
1ba585e8 IT |
13847 | case dw_mode: |
13848 | case db_mode: | |
c0f3af97 L |
13849 | names = names32; |
13850 | break; | |
13851 | case q_mode: | |
13852 | names = names64; | |
13853 | break; | |
13854 | case m_mode: | |
6c75cc62 | 13855 | case v_bnd_mode: |
c0f3af97 L |
13856 | names = address_mode == mode_64bit ? names64 : names32; |
13857 | break; | |
7e8b059b | 13858 | case bnd_mode: |
9f79e886 | 13859 | case bnd_swap_mode: |
0d96e4df L |
13860 | if (reg > 0x3) |
13861 | { | |
13862 | oappend ("(bad)"); | |
13863 | return; | |
13864 | } | |
7e8b059b L |
13865 | names = names_bnd; |
13866 | break; | |
07f5af7d L |
13867 | case indir_v_mode: |
13868 | if (address_mode == mode_64bit && isa64 == intel64) | |
13869 | { | |
13870 | names = names64; | |
13871 | break; | |
13872 | } | |
1a0670f3 | 13873 | /* Fall through. */ |
c0f3af97 | 13874 | case stack_v_mode: |
7bb15c6f | 13875 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13876 | { |
c0f3af97 | 13877 | names = names64; |
252b5132 | 13878 | break; |
252b5132 | 13879 | } |
c0f3af97 | 13880 | bytemode = v_mode; |
1a0670f3 | 13881 | /* Fall through. */ |
c0f3af97 | 13882 | case v_mode: |
b6169b20 | 13883 | case v_swap_mode: |
c0f3af97 L |
13884 | case dq_mode: |
13885 | case dqb_mode: | |
13886 | case dqd_mode: | |
13887 | case dqw_mode: | |
13888 | USED_REX (REX_W); | |
13889 | if (rex & REX_W) | |
13890 | names = names64; | |
c0f3af97 | 13891 | else |
f16cd0d5 | 13892 | { |
7bb15c6f | 13893 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13894 | || (bytemode != v_mode |
13895 | && bytemode != v_swap_mode)) | |
13896 | names = names32; | |
13897 | else | |
13898 | names = names16; | |
13899 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13900 | } | |
c0f3af97 | 13901 | break; |
bc31405e L |
13902 | case movsxd_mode: |
13903 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13904 | names = names16; | |
13905 | else | |
13906 | names = names32; | |
13907 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13908 | break; | |
de89d0a3 IT |
13909 | case va_mode: |
13910 | names = (address_mode == mode_64bit | |
13911 | ? names64 : names32); | |
13912 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13913 | names = (address_mode == mode_16bit |
13914 | ? names16 : names); | |
de89d0a3 IT |
13915 | else |
13916 | { | |
13917 | /* Remove "addr16/addr32". */ | |
13918 | all_prefixes[last_addr_prefix] = 0; | |
13919 | names = (address_mode != mode_32bit | |
13920 | ? names32 : names16); | |
13921 | used_prefixes |= PREFIX_ADDR; | |
13922 | } | |
13923 | break; | |
1ba585e8 | 13924 | case mask_bd_mode: |
43234a1e | 13925 | case mask_mode: |
9889cbb1 L |
13926 | if (reg > 0x7) |
13927 | { | |
13928 | oappend ("(bad)"); | |
13929 | return; | |
13930 | } | |
43234a1e L |
13931 | names = names_mask; |
13932 | break; | |
c0f3af97 L |
13933 | case 0: |
13934 | return; | |
13935 | default: | |
13936 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13937 | return; |
13938 | } | |
c0f3af97 L |
13939 | oappend (names[reg]); |
13940 | } | |
13941 | ||
13942 | static void | |
c1e679ec | 13943 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13944 | { |
13945 | bfd_vma disp = 0; | |
13946 | int add = (rex & REX_B) ? 8 : 0; | |
13947 | int riprel = 0; | |
43234a1e L |
13948 | int shift; |
13949 | ||
13950 | if (vex.evex) | |
13951 | { | |
13952 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13953 | if (vex.b | |
13954 | && bytemode != x_mode | |
90a915bf | 13955 | && bytemode != xmmq_mode |
43234a1e L |
13956 | && bytemode != evex_half_bcst_xmmq_mode) |
13957 | { | |
13958 | BadOp (); | |
13959 | return; | |
13960 | } | |
13961 | switch (bytemode) | |
13962 | { | |
1ba585e8 IT |
13963 | case dqw_mode: |
13964 | case dw_mode: | |
1ba585e8 IT |
13965 | shift = 1; |
13966 | break; | |
13967 | case dqb_mode: | |
13968 | case db_mode: | |
13969 | shift = 0; | |
13970 | break; | |
b50c9f31 JB |
13971 | case dq_mode: |
13972 | if (address_mode != mode_64bit) | |
13973 | { | |
13974 | shift = 2; | |
13975 | break; | |
13976 | } | |
13977 | /* fall through */ | |
4102be5c | 13978 | case vex_scalar_w_dq_mode: |
43234a1e | 13979 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13980 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13981 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13982 | case vex_vsib_q_w_d_mode: |
43234a1e | 13983 | case evex_x_gscat_mode: |
43234a1e L |
13984 | shift = vex.w ? 3 : 2; |
13985 | break; | |
43234a1e L |
13986 | case x_mode: |
13987 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13988 | case xmmq_mode: |
43234a1e L |
13989 | if (vex.b) |
13990 | { | |
13991 | shift = vex.w ? 3 : 2; | |
13992 | break; | |
13993 | } | |
1a0670f3 | 13994 | /* Fall through. */ |
43234a1e L |
13995 | case xmmqd_mode: |
13996 | case xmmdw_mode: | |
43234a1e L |
13997 | case ymmq_mode: |
13998 | case evex_x_nobcst_mode: | |
13999 | case x_swap_mode: | |
14000 | switch (vex.length) | |
14001 | { | |
14002 | case 128: | |
14003 | shift = 4; | |
14004 | break; | |
14005 | case 256: | |
14006 | shift = 5; | |
14007 | break; | |
14008 | case 512: | |
14009 | shift = 6; | |
14010 | break; | |
14011 | default: | |
14012 | abort (); | |
14013 | } | |
14014 | break; | |
14015 | case ymm_mode: | |
14016 | shift = 5; | |
14017 | break; | |
14018 | case xmm_mode: | |
14019 | shift = 4; | |
14020 | break; | |
14021 | case xmm_mq_mode: | |
14022 | case q_mode: | |
14023 | case q_scalar_mode: | |
14024 | case q_swap_mode: | |
14025 | case q_scalar_swap_mode: | |
14026 | shift = 3; | |
14027 | break; | |
14028 | case dqd_mode: | |
14029 | case xmm_md_mode: | |
14030 | case d_mode: | |
14031 | case d_scalar_mode: | |
14032 | case d_swap_mode: | |
14033 | case d_scalar_swap_mode: | |
14034 | shift = 2; | |
14035 | break; | |
5074ad8a | 14036 | case w_scalar_mode: |
43234a1e L |
14037 | case xmm_mw_mode: |
14038 | shift = 1; | |
14039 | break; | |
5074ad8a | 14040 | case b_scalar_mode: |
43234a1e L |
14041 | case xmm_mb_mode: |
14042 | shift = 0; | |
14043 | break; | |
14044 | default: | |
14045 | abort (); | |
14046 | } | |
14047 | /* Make necessary corrections to shift for modes that need it. | |
14048 | For these modes we currently have shift 4, 5 or 6 depending on | |
14049 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14050 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14051 | xmmq_mode). In case of broadcast enabled the corrections | |
14052 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14053 | if (!vex.b |
14054 | && (bytemode == xmmq_mode | |
14055 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14056 | shift -= 1; |
14057 | else if (bytemode == xmmqd_mode) | |
14058 | shift -= 2; | |
14059 | else if (bytemode == xmmdw_mode) | |
14060 | shift -= 3; | |
b28d1bda IT |
14061 | else if (bytemode == ymmq_mode && vex.length == 128) |
14062 | shift -= 1; | |
43234a1e L |
14063 | } |
14064 | else | |
14065 | shift = 0; | |
252b5132 | 14066 | |
c0f3af97 | 14067 | USED_REX (REX_B); |
3f31e633 JB |
14068 | if (intel_syntax) |
14069 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14070 | append_seg (); |
14071 | ||
5d669648 | 14072 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14073 | { |
5d669648 L |
14074 | /* 32/64 bit address mode */ |
14075 | int havedisp; | |
252b5132 RH |
14076 | int havesib; |
14077 | int havebase; | |
0f7da397 | 14078 | int haveindex; |
20afcfb7 | 14079 | int needindex; |
1bc60e56 | 14080 | int needaddr32; |
82c18208 | 14081 | int base, rbase; |
91d6fa6a | 14082 | int vindex = 0; |
252b5132 | 14083 | int scale = 0; |
7e8b059b L |
14084 | int addr32flag = !((sizeflag & AFLAG) |
14085 | || bytemode == v_bnd_mode | |
d276ec69 | 14086 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14087 | || bytemode == bnd_mode |
14088 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14089 | const char **indexes64 = names64; |
14090 | const char **indexes32 = names32; | |
252b5132 RH |
14091 | |
14092 | havesib = 0; | |
14093 | havebase = 1; | |
0f7da397 | 14094 | haveindex = 0; |
7967e09e | 14095 | base = modrm.rm; |
252b5132 RH |
14096 | |
14097 | if (base == 4) | |
14098 | { | |
14099 | havesib = 1; | |
dfc8cf43 | 14100 | vindex = sib.index; |
161a04f6 L |
14101 | USED_REX (REX_X); |
14102 | if (rex & REX_X) | |
91d6fa6a | 14103 | vindex += 8; |
6c30d220 L |
14104 | switch (bytemode) |
14105 | { | |
14106 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14107 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14108 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14109 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14110 | if (!need_vex) |
14111 | abort (); | |
43234a1e L |
14112 | if (vex.evex) |
14113 | { | |
14114 | if (!vex.v) | |
14115 | vindex += 16; | |
14116 | } | |
6c30d220 L |
14117 | |
14118 | haveindex = 1; | |
14119 | switch (vex.length) | |
14120 | { | |
14121 | case 128: | |
7bb15c6f | 14122 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14123 | break; |
14124 | case 256: | |
5fc35d96 IT |
14125 | if (!vex.w |
14126 | || bytemode == vex_vsib_q_w_dq_mode | |
14127 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14128 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14129 | else |
7bb15c6f | 14130 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14131 | break; |
43234a1e | 14132 | case 512: |
5fc35d96 IT |
14133 | if (!vex.w |
14134 | || bytemode == vex_vsib_q_w_dq_mode | |
14135 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14136 | indexes64 = indexes32 = names_zmm; |
14137 | else | |
14138 | indexes64 = indexes32 = names_ymm; | |
14139 | break; | |
6c30d220 L |
14140 | default: |
14141 | abort (); | |
14142 | } | |
14143 | break; | |
14144 | default: | |
14145 | haveindex = vindex != 4; | |
14146 | break; | |
14147 | } | |
14148 | scale = sib.scale; | |
14149 | base = sib.base; | |
252b5132 RH |
14150 | codep++; |
14151 | } | |
82c18208 | 14152 | rbase = base + add; |
252b5132 | 14153 | |
7967e09e | 14154 | switch (modrm.mod) |
252b5132 RH |
14155 | { |
14156 | case 0: | |
82c18208 | 14157 | if (base == 5) |
252b5132 RH |
14158 | { |
14159 | havebase = 0; | |
cb712a9e | 14160 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14161 | riprel = 1; |
14162 | disp = get32s (); | |
d276ec69 JB |
14163 | if (riprel && bytemode == v_bndmk_mode) |
14164 | { | |
14165 | oappend ("(bad)"); | |
14166 | return; | |
14167 | } | |
252b5132 RH |
14168 | } |
14169 | break; | |
14170 | case 1: | |
14171 | FETCH_DATA (the_info, codep + 1); | |
14172 | disp = *codep++; | |
14173 | if ((disp & 0x80) != 0) | |
14174 | disp -= 0x100; | |
43234a1e L |
14175 | if (vex.evex && shift > 0) |
14176 | disp <<= shift; | |
252b5132 RH |
14177 | break; |
14178 | case 2: | |
52b15da3 | 14179 | disp = get32s (); |
252b5132 RH |
14180 | break; |
14181 | } | |
14182 | ||
1bc60e56 L |
14183 | needindex = 0; |
14184 | needaddr32 = 0; | |
14185 | if (havesib | |
14186 | && !havebase | |
14187 | && !haveindex | |
14188 | && address_mode != mode_16bit) | |
14189 | { | |
14190 | if (address_mode == mode_64bit) | |
14191 | { | |
14192 | /* Display eiz instead of addr32. */ | |
14193 | needindex = addr32flag; | |
14194 | needaddr32 = 1; | |
14195 | } | |
14196 | else | |
14197 | { | |
14198 | /* In 32-bit mode, we need index register to tell [offset] | |
14199 | from [eiz*1 + offset]. */ | |
14200 | needindex = 1; | |
14201 | } | |
14202 | } | |
14203 | ||
20afcfb7 L |
14204 | havedisp = (havebase |
14205 | || needindex | |
14206 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14207 | |
252b5132 | 14208 | if (!intel_syntax) |
82c18208 | 14209 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14210 | { |
5d669648 L |
14211 | if (havedisp || riprel) |
14212 | print_displacement (scratchbuf, disp); | |
14213 | else | |
14214 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14215 | oappend (scratchbuf); |
52b15da3 JH |
14216 | if (riprel) |
14217 | { | |
14218 | set_op (disp, 1); | |
28596323 | 14219 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14220 | } |
db6eb5be | 14221 | } |
2da11e11 | 14222 | |
c1dc7af5 | 14223 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14224 | && (address_mode != mode_64bit |
14225 | || ((bytemode != v_bnd_mode) | |
14226 | && (bytemode != v_bndmk_mode) | |
14227 | && (bytemode != bnd_mode) | |
14228 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14229 | used_prefixes |= PREFIX_ADDR; |
14230 | ||
5d669648 | 14231 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14232 | { |
252b5132 | 14233 | *obufp++ = open_char; |
52b15da3 | 14234 | if (intel_syntax && riprel) |
185b1163 L |
14235 | { |
14236 | set_op (disp, 1); | |
28596323 | 14237 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14238 | } |
db6eb5be | 14239 | *obufp = '\0'; |
252b5132 | 14240 | if (havebase) |
7e8b059b | 14241 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14242 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14243 | if (havesib) |
14244 | { | |
db51cc60 L |
14245 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14246 | print index to tell base + index from base. */ | |
14247 | if (scale != 0 | |
20afcfb7 | 14248 | || needindex |
db51cc60 L |
14249 | || haveindex |
14250 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14251 | { |
9306ca4a | 14252 | if (!intel_syntax || havebase) |
db6eb5be | 14253 | { |
9306ca4a JB |
14254 | *obufp++ = separator_char; |
14255 | *obufp = '\0'; | |
db6eb5be | 14256 | } |
db51cc60 | 14257 | if (haveindex) |
7e8b059b | 14258 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14259 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14260 | else |
7e8b059b | 14261 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14262 | ? index64 : index32); |
14263 | ||
db6eb5be AM |
14264 | *obufp++ = scale_char; |
14265 | *obufp = '\0'; | |
14266 | sprintf (scratchbuf, "%d", 1 << scale); | |
14267 | oappend (scratchbuf); | |
14268 | } | |
252b5132 | 14269 | } |
185b1163 | 14270 | if (intel_syntax |
82c18208 | 14271 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14272 | { |
db51cc60 | 14273 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14274 | { |
14275 | *obufp++ = '+'; | |
14276 | *obufp = '\0'; | |
14277 | } | |
05203043 | 14278 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14279 | { |
14280 | *obufp++ = '-'; | |
14281 | *obufp = '\0'; | |
14282 | disp = - (bfd_signed_vma) disp; | |
14283 | } | |
14284 | ||
db51cc60 L |
14285 | if (havedisp) |
14286 | print_displacement (scratchbuf, disp); | |
14287 | else | |
14288 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14289 | oappend (scratchbuf); |
14290 | } | |
252b5132 RH |
14291 | |
14292 | *obufp++ = close_char; | |
db6eb5be | 14293 | *obufp = '\0'; |
252b5132 RH |
14294 | } |
14295 | else if (intel_syntax) | |
db6eb5be | 14296 | { |
82c18208 | 14297 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14298 | { |
285ca992 | 14299 | if (!active_seg_prefix) |
252b5132 | 14300 | { |
d708bcba | 14301 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14302 | oappend (":"); |
14303 | } | |
52b15da3 | 14304 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14305 | oappend (scratchbuf); |
14306 | } | |
14307 | } | |
252b5132 | 14308 | } |
a23b33b3 JB |
14309 | else if (bytemode == v_bnd_mode |
14310 | || bytemode == v_bndmk_mode | |
14311 | || bytemode == bnd_mode | |
14312 | || bytemode == bnd_swap_mode) | |
14313 | { | |
14314 | oappend ("(bad)"); | |
14315 | return; | |
14316 | } | |
252b5132 | 14317 | else |
f16cd0d5 L |
14318 | { |
14319 | /* 16 bit address mode */ | |
14320 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14321 | switch (modrm.mod) |
252b5132 RH |
14322 | { |
14323 | case 0: | |
7967e09e | 14324 | if (modrm.rm == 6) |
252b5132 RH |
14325 | { |
14326 | disp = get16 (); | |
14327 | if ((disp & 0x8000) != 0) | |
14328 | disp -= 0x10000; | |
14329 | } | |
14330 | break; | |
14331 | case 1: | |
14332 | FETCH_DATA (the_info, codep + 1); | |
14333 | disp = *codep++; | |
14334 | if ((disp & 0x80) != 0) | |
14335 | disp -= 0x100; | |
65f3ed04 JB |
14336 | if (vex.evex && shift > 0) |
14337 | disp <<= shift; | |
252b5132 RH |
14338 | break; |
14339 | case 2: | |
14340 | disp = get16 (); | |
14341 | if ((disp & 0x8000) != 0) | |
14342 | disp -= 0x10000; | |
14343 | break; | |
14344 | } | |
14345 | ||
14346 | if (!intel_syntax) | |
7967e09e | 14347 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14348 | { |
5d669648 | 14349 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14350 | oappend (scratchbuf); |
14351 | } | |
252b5132 | 14352 | |
7967e09e | 14353 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14354 | { |
14355 | *obufp++ = open_char; | |
db6eb5be | 14356 | *obufp = '\0'; |
7967e09e | 14357 | oappend (index16[modrm.rm]); |
5d669648 L |
14358 | if (intel_syntax |
14359 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14360 | { |
5d669648 | 14361 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14362 | { |
14363 | *obufp++ = '+'; | |
14364 | *obufp = '\0'; | |
14365 | } | |
7967e09e | 14366 | else if (modrm.mod != 1) |
3d456fa1 JB |
14367 | { |
14368 | *obufp++ = '-'; | |
14369 | *obufp = '\0'; | |
14370 | disp = - (bfd_signed_vma) disp; | |
14371 | } | |
14372 | ||
5d669648 | 14373 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14374 | oappend (scratchbuf); |
14375 | } | |
14376 | ||
db6eb5be AM |
14377 | *obufp++ = close_char; |
14378 | *obufp = '\0'; | |
252b5132 | 14379 | } |
3d456fa1 JB |
14380 | else if (intel_syntax) |
14381 | { | |
285ca992 | 14382 | if (!active_seg_prefix) |
3d456fa1 JB |
14383 | { |
14384 | oappend (names_seg[ds_reg - es_reg]); | |
14385 | oappend (":"); | |
14386 | } | |
14387 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14388 | oappend (scratchbuf); | |
14389 | } | |
252b5132 | 14390 | } |
43234a1e L |
14391 | if (vex.evex && vex.b |
14392 | && (bytemode == x_mode | |
90a915bf | 14393 | || bytemode == xmmq_mode |
43234a1e L |
14394 | || bytemode == evex_half_bcst_xmmq_mode)) |
14395 | { | |
90a915bf IT |
14396 | if (vex.w |
14397 | || bytemode == xmmq_mode | |
14398 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14399 | { |
14400 | switch (vex.length) | |
14401 | { | |
14402 | case 128: | |
14403 | oappend ("{1to2}"); | |
14404 | break; | |
14405 | case 256: | |
14406 | oappend ("{1to4}"); | |
14407 | break; | |
14408 | case 512: | |
14409 | oappend ("{1to8}"); | |
14410 | break; | |
14411 | default: | |
14412 | abort (); | |
14413 | } | |
14414 | } | |
43234a1e | 14415 | else |
b28d1bda IT |
14416 | { |
14417 | switch (vex.length) | |
14418 | { | |
14419 | case 128: | |
14420 | oappend ("{1to4}"); | |
14421 | break; | |
14422 | case 256: | |
14423 | oappend ("{1to8}"); | |
14424 | break; | |
14425 | case 512: | |
14426 | oappend ("{1to16}"); | |
14427 | break; | |
14428 | default: | |
14429 | abort (); | |
14430 | } | |
14431 | } | |
43234a1e | 14432 | } |
252b5132 RH |
14433 | } |
14434 | ||
c0f3af97 | 14435 | static void |
8b3f93e7 | 14436 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14437 | { |
14438 | /* Skip mod/rm byte. */ | |
14439 | MODRM_CHECK; | |
14440 | codep++; | |
14441 | ||
14442 | if (modrm.mod == 3) | |
14443 | OP_E_register (bytemode, sizeflag); | |
14444 | else | |
c1e679ec | 14445 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14446 | } |
14447 | ||
252b5132 | 14448 | static void |
26ca5450 | 14449 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14450 | { |
52b15da3 | 14451 | int add = 0; |
c0a30a9f | 14452 | const char **names; |
161a04f6 L |
14453 | USED_REX (REX_R); |
14454 | if (rex & REX_R) | |
52b15da3 | 14455 | add += 8; |
252b5132 RH |
14456 | switch (bytemode) |
14457 | { | |
14458 | case b_mode: | |
52b15da3 JH |
14459 | USED_REX (0); |
14460 | if (rex) | |
7967e09e | 14461 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14462 | else |
7967e09e | 14463 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14464 | break; |
14465 | case w_mode: | |
7967e09e | 14466 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14467 | break; |
14468 | case d_mode: | |
1ba585e8 IT |
14469 | case db_mode: |
14470 | case dw_mode: | |
7967e09e | 14471 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14472 | break; |
14473 | case q_mode: | |
7967e09e | 14474 | oappend (names64[modrm.reg + add]); |
252b5132 | 14475 | break; |
7e8b059b | 14476 | case bnd_mode: |
0d96e4df L |
14477 | if (modrm.reg > 0x3) |
14478 | { | |
14479 | oappend ("(bad)"); | |
14480 | return; | |
14481 | } | |
7e8b059b L |
14482 | oappend (names_bnd[modrm.reg]); |
14483 | break; | |
252b5132 | 14484 | case v_mode: |
9306ca4a | 14485 | case dq_mode: |
42903f7f L |
14486 | case dqb_mode: |
14487 | case dqd_mode: | |
9306ca4a | 14488 | case dqw_mode: |
bc31405e | 14489 | case movsxd_mode: |
161a04f6 L |
14490 | USED_REX (REX_W); |
14491 | if (rex & REX_W) | |
7967e09e | 14492 | oappend (names64[modrm.reg + add]); |
252b5132 | 14493 | else |
f16cd0d5 | 14494 | { |
bc31405e L |
14495 | if ((sizeflag & DFLAG) |
14496 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14497 | oappend (names32[modrm.reg + add]); |
14498 | else | |
14499 | oappend (names16[modrm.reg + add]); | |
14500 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14501 | } | |
252b5132 | 14502 | break; |
c0a30a9f L |
14503 | case va_mode: |
14504 | names = (address_mode == mode_64bit | |
14505 | ? names64 : names32); | |
14506 | if (!(prefixes & PREFIX_ADDR)) | |
14507 | { | |
14508 | if (address_mode == mode_16bit) | |
14509 | names = names16; | |
14510 | } | |
14511 | else | |
14512 | { | |
14513 | /* Remove "addr16/addr32". */ | |
14514 | all_prefixes[last_addr_prefix] = 0; | |
14515 | names = (address_mode != mode_32bit | |
14516 | ? names32 : names16); | |
14517 | used_prefixes |= PREFIX_ADDR; | |
14518 | } | |
14519 | oappend (names[modrm.reg + add]); | |
14520 | break; | |
90700ea2 | 14521 | case m_mode: |
cb712a9e | 14522 | if (address_mode == mode_64bit) |
7967e09e | 14523 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14524 | else |
7967e09e | 14525 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14526 | break; |
1ba585e8 | 14527 | case mask_bd_mode: |
43234a1e | 14528 | case mask_mode: |
9889cbb1 L |
14529 | if ((modrm.reg + add) > 0x7) |
14530 | { | |
14531 | oappend ("(bad)"); | |
14532 | return; | |
14533 | } | |
43234a1e L |
14534 | oappend (names_mask[modrm.reg + add]); |
14535 | break; | |
252b5132 RH |
14536 | default: |
14537 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14538 | break; | |
14539 | } | |
14540 | } | |
14541 | ||
52b15da3 | 14542 | static bfd_vma |
26ca5450 | 14543 | get64 (void) |
52b15da3 | 14544 | { |
5dd0794d | 14545 | bfd_vma x; |
52b15da3 | 14546 | #ifdef BFD64 |
5dd0794d AM |
14547 | unsigned int a; |
14548 | unsigned int b; | |
14549 | ||
52b15da3 JH |
14550 | FETCH_DATA (the_info, codep + 8); |
14551 | a = *codep++ & 0xff; | |
14552 | a |= (*codep++ & 0xff) << 8; | |
14553 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14554 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14555 | b = *codep++ & 0xff; |
52b15da3 JH |
14556 | b |= (*codep++ & 0xff) << 8; |
14557 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14558 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14559 | x = a + ((bfd_vma) b << 32); |
14560 | #else | |
6608db57 | 14561 | abort (); |
5dd0794d | 14562 | x = 0; |
52b15da3 JH |
14563 | #endif |
14564 | return x; | |
14565 | } | |
14566 | ||
14567 | static bfd_signed_vma | |
26ca5450 | 14568 | get32 (void) |
252b5132 | 14569 | { |
52b15da3 | 14570 | bfd_signed_vma x = 0; |
252b5132 RH |
14571 | |
14572 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14573 | x = *codep++ & (bfd_signed_vma) 0xff; |
14574 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14575 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14576 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14577 | return x; | |
14578 | } | |
14579 | ||
14580 | static bfd_signed_vma | |
26ca5450 | 14581 | get32s (void) |
52b15da3 JH |
14582 | { |
14583 | bfd_signed_vma x = 0; | |
14584 | ||
14585 | FETCH_DATA (the_info, codep + 4); | |
14586 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14587 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14588 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14589 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14590 | ||
14591 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14592 | ||
252b5132 RH |
14593 | return x; |
14594 | } | |
14595 | ||
14596 | static int | |
26ca5450 | 14597 | get16 (void) |
252b5132 RH |
14598 | { |
14599 | int x = 0; | |
14600 | ||
14601 | FETCH_DATA (the_info, codep + 2); | |
14602 | x = *codep++ & 0xff; | |
14603 | x |= (*codep++ & 0xff) << 8; | |
14604 | return x; | |
14605 | } | |
14606 | ||
14607 | static void | |
26ca5450 | 14608 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14609 | { |
14610 | op_index[op_ad] = op_ad; | |
cb712a9e | 14611 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14612 | { |
14613 | op_address[op_ad] = op; | |
14614 | op_riprel[op_ad] = riprel; | |
14615 | } | |
14616 | else | |
14617 | { | |
14618 | /* Mask to get a 32-bit address. */ | |
14619 | op_address[op_ad] = op & 0xffffffff; | |
14620 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14621 | } | |
252b5132 RH |
14622 | } |
14623 | ||
14624 | static void | |
26ca5450 | 14625 | OP_REG (int code, int sizeflag) |
252b5132 | 14626 | { |
2da11e11 | 14627 | const char *s; |
9b60702d | 14628 | int add; |
de882298 RM |
14629 | |
14630 | switch (code) | |
14631 | { | |
14632 | case es_reg: case ss_reg: case cs_reg: | |
14633 | case ds_reg: case fs_reg: case gs_reg: | |
14634 | oappend (names_seg[code - es_reg]); | |
14635 | return; | |
14636 | } | |
14637 | ||
161a04f6 L |
14638 | USED_REX (REX_B); |
14639 | if (rex & REX_B) | |
52b15da3 | 14640 | add = 8; |
9b60702d L |
14641 | else |
14642 | add = 0; | |
52b15da3 JH |
14643 | |
14644 | switch (code) | |
14645 | { | |
52b15da3 JH |
14646 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14647 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14648 | s = names16[code - ax_reg + add]; | |
14649 | break; | |
52b15da3 JH |
14650 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14651 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14652 | USED_REX (0); | |
14653 | if (rex) | |
14654 | s = names8rex[code - al_reg + add]; | |
14655 | else | |
14656 | s = names8[code - al_reg]; | |
14657 | break; | |
6439fc28 AM |
14658 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14659 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14660 | if (address_mode == mode_64bit |
6c067bbb | 14661 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14662 | { |
14663 | s = names64[code - rAX_reg + add]; | |
14664 | break; | |
14665 | } | |
14666 | code += eAX_reg - rAX_reg; | |
6608db57 | 14667 | /* Fall through. */ |
52b15da3 JH |
14668 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14669 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14670 | USED_REX (REX_W); |
14671 | if (rex & REX_W) | |
52b15da3 | 14672 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14673 | else |
f16cd0d5 L |
14674 | { |
14675 | if (sizeflag & DFLAG) | |
14676 | s = names32[code - eAX_reg + add]; | |
14677 | else | |
14678 | s = names16[code - eAX_reg + add]; | |
14679 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14680 | } | |
52b15da3 | 14681 | break; |
52b15da3 JH |
14682 | default: |
14683 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14684 | break; | |
14685 | } | |
14686 | oappend (s); | |
14687 | } | |
14688 | ||
14689 | static void | |
26ca5450 | 14690 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14691 | { |
14692 | const char *s; | |
252b5132 RH |
14693 | |
14694 | switch (code) | |
14695 | { | |
14696 | case indir_dx_reg: | |
d708bcba | 14697 | if (intel_syntax) |
52fd6d94 | 14698 | s = "dx"; |
d708bcba | 14699 | else |
db6eb5be | 14700 | s = "(%dx)"; |
252b5132 RH |
14701 | break; |
14702 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14703 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14704 | s = names16[code - ax_reg]; | |
14705 | break; | |
14706 | case es_reg: case ss_reg: case cs_reg: | |
14707 | case ds_reg: case fs_reg: case gs_reg: | |
14708 | s = names_seg[code - es_reg]; | |
14709 | break; | |
14710 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14711 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14712 | USED_REX (0); |
14713 | if (rex) | |
14714 | s = names8rex[code - al_reg]; | |
14715 | else | |
14716 | s = names8[code - al_reg]; | |
252b5132 RH |
14717 | break; |
14718 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14719 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14720 | USED_REX (REX_W); |
14721 | if (rex & REX_W) | |
52b15da3 | 14722 | s = names64[code - eAX_reg]; |
252b5132 | 14723 | else |
f16cd0d5 L |
14724 | { |
14725 | if (sizeflag & DFLAG) | |
14726 | s = names32[code - eAX_reg]; | |
14727 | else | |
14728 | s = names16[code - eAX_reg]; | |
14729 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14730 | } | |
252b5132 | 14731 | break; |
52fd6d94 | 14732 | case z_mode_ax_reg: |
161a04f6 | 14733 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14734 | s = *names32; |
14735 | else | |
14736 | s = *names16; | |
161a04f6 | 14737 | if (!(rex & REX_W)) |
52fd6d94 JB |
14738 | used_prefixes |= (prefixes & PREFIX_DATA); |
14739 | break; | |
252b5132 RH |
14740 | default: |
14741 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14742 | break; | |
14743 | } | |
14744 | oappend (s); | |
14745 | } | |
14746 | ||
14747 | static void | |
26ca5450 | 14748 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14749 | { |
52b15da3 JH |
14750 | bfd_signed_vma op; |
14751 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14752 | |
14753 | switch (bytemode) | |
14754 | { | |
14755 | case b_mode: | |
14756 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14757 | op = *codep++; |
14758 | mask = 0xff; | |
14759 | break; | |
252b5132 | 14760 | case v_mode: |
161a04f6 L |
14761 | USED_REX (REX_W); |
14762 | if (rex & REX_W) | |
52b15da3 | 14763 | op = get32s (); |
252b5132 | 14764 | else |
52b15da3 | 14765 | { |
f16cd0d5 L |
14766 | if (sizeflag & DFLAG) |
14767 | { | |
14768 | op = get32 (); | |
14769 | mask = 0xffffffff; | |
14770 | } | |
14771 | else | |
14772 | { | |
14773 | op = get16 (); | |
14774 | mask = 0xfffff; | |
14775 | } | |
14776 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14777 | } |
252b5132 | 14778 | break; |
c1dc7af5 JB |
14779 | case d_mode: |
14780 | mask = 0xffffffff; | |
14781 | op = get32 (); | |
14782 | break; | |
252b5132 | 14783 | case w_mode: |
52b15da3 | 14784 | mask = 0xfffff; |
252b5132 RH |
14785 | op = get16 (); |
14786 | break; | |
9306ca4a JB |
14787 | case const_1_mode: |
14788 | if (intel_syntax) | |
6c067bbb | 14789 | oappend ("1"); |
9306ca4a | 14790 | return; |
252b5132 RH |
14791 | default: |
14792 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14793 | return; | |
14794 | } | |
14795 | ||
52b15da3 JH |
14796 | op &= mask; |
14797 | scratchbuf[0] = '$'; | |
d708bcba | 14798 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14799 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14800 | scratchbuf[0] = '\0'; |
14801 | } | |
14802 | ||
14803 | static void | |
26ca5450 | 14804 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14805 | { |
a280ab8e | 14806 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14807 | { |
14808 | OP_I (bytemode, sizeflag); | |
14809 | return; | |
14810 | } | |
14811 | ||
a280ab8e | 14812 | USED_REX (REX_W); |
52b15da3 | 14813 | |
52b15da3 | 14814 | scratchbuf[0] = '$'; |
a280ab8e | 14815 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14816 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14817 | scratchbuf[0] = '\0'; |
14818 | } | |
14819 | ||
14820 | static void | |
26ca5450 | 14821 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14822 | { |
52b15da3 | 14823 | bfd_signed_vma op; |
252b5132 RH |
14824 | |
14825 | switch (bytemode) | |
14826 | { | |
14827 | case b_mode: | |
e3949f17 | 14828 | case b_T_mode: |
252b5132 RH |
14829 | FETCH_DATA (the_info, codep + 1); |
14830 | op = *codep++; | |
14831 | if ((op & 0x80) != 0) | |
14832 | op -= 0x100; | |
e3949f17 L |
14833 | if (bytemode == b_T_mode) |
14834 | { | |
14835 | if (address_mode != mode_64bit | |
7bb15c6f | 14836 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14837 | { |
6c067bbb RM |
14838 | /* The operand-size prefix is overridden by a REX prefix. */ |
14839 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14840 | op &= 0xffffffff; |
14841 | else | |
14842 | op &= 0xffff; | |
14843 | } | |
14844 | } | |
14845 | else | |
14846 | { | |
14847 | if (!(rex & REX_W)) | |
14848 | { | |
14849 | if (sizeflag & DFLAG) | |
14850 | op &= 0xffffffff; | |
14851 | else | |
14852 | op &= 0xffff; | |
14853 | } | |
14854 | } | |
252b5132 RH |
14855 | break; |
14856 | case v_mode: | |
7bb15c6f RM |
14857 | /* The operand-size prefix is overridden by a REX prefix. */ |
14858 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14859 | op = get32s (); |
252b5132 | 14860 | else |
d9e3625e | 14861 | op = get16 (); |
252b5132 RH |
14862 | break; |
14863 | default: | |
14864 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14865 | return; | |
14866 | } | |
52b15da3 JH |
14867 | |
14868 | scratchbuf[0] = '$'; | |
14869 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14870 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14871 | } |
14872 | ||
14873 | static void | |
26ca5450 | 14874 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14875 | { |
52b15da3 | 14876 | bfd_vma disp; |
7081ff04 | 14877 | bfd_vma mask = -1; |
65ca155d | 14878 | bfd_vma segment = 0; |
252b5132 RH |
14879 | |
14880 | switch (bytemode) | |
14881 | { | |
14882 | case b_mode: | |
14883 | FETCH_DATA (the_info, codep + 1); | |
14884 | disp = *codep++; | |
14885 | if ((disp & 0x80) != 0) | |
14886 | disp -= 0x100; | |
14887 | break; | |
14888 | case v_mode: | |
d835a58b | 14889 | if (isa64 != intel64) |
376cd056 | 14890 | case dqw_mode: |
5db04b09 L |
14891 | USED_REX (REX_W); |
14892 | if ((sizeflag & DFLAG) | |
14893 | || (address_mode == mode_64bit | |
d835a58b | 14894 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14895 | || (rex & REX_W)))) |
52b15da3 | 14896 | disp = get32s (); |
252b5132 RH |
14897 | else |
14898 | { | |
14899 | disp = get16 (); | |
206717e8 L |
14900 | if ((disp & 0x8000) != 0) |
14901 | disp -= 0x10000; | |
65ca155d L |
14902 | /* In 16bit mode, address is wrapped around at 64k within |
14903 | the same segment. Otherwise, a data16 prefix on a jump | |
14904 | instruction means that the pc is masked to 16 bits after | |
14905 | the displacement is added! */ | |
14906 | mask = 0xffff; | |
14907 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14908 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14909 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14910 | } |
5db04b09 | 14911 | if (address_mode != mode_64bit |
d835a58b | 14912 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14913 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14914 | break; |
14915 | default: | |
14916 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14917 | return; | |
14918 | } | |
42d5f9c6 | 14919 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14920 | set_op (disp, 0); |
14921 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14922 | oappend (scratchbuf); |
14923 | } | |
14924 | ||
252b5132 | 14925 | static void |
ed7841b3 | 14926 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14927 | { |
ed7841b3 | 14928 | if (bytemode == w_mode) |
7967e09e | 14929 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14930 | else |
7967e09e | 14931 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14932 | } |
14933 | ||
14934 | static void | |
26ca5450 | 14935 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14936 | { |
14937 | int seg, offset; | |
14938 | ||
c608c12e | 14939 | if (sizeflag & DFLAG) |
252b5132 | 14940 | { |
c608c12e AM |
14941 | offset = get32 (); |
14942 | seg = get16 (); | |
252b5132 | 14943 | } |
c608c12e AM |
14944 | else |
14945 | { | |
14946 | offset = get16 (); | |
14947 | seg = get16 (); | |
14948 | } | |
7d421014 | 14949 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14950 | if (intel_syntax) |
3f31e633 | 14951 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14952 | else |
14953 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14954 | oappend (scratchbuf); |
252b5132 RH |
14955 | } |
14956 | ||
252b5132 | 14957 | static void |
3f31e633 | 14958 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14959 | { |
52b15da3 | 14960 | bfd_vma off; |
252b5132 | 14961 | |
3f31e633 JB |
14962 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14963 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14964 | append_seg (); |
14965 | ||
cb712a9e | 14966 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14967 | off = get32 (); |
14968 | else | |
14969 | off = get16 (); | |
14970 | ||
14971 | if (intel_syntax) | |
14972 | { | |
285ca992 | 14973 | if (!active_seg_prefix) |
252b5132 | 14974 | { |
d708bcba | 14975 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14976 | oappend (":"); |
14977 | } | |
14978 | } | |
52b15da3 JH |
14979 | print_operand_value (scratchbuf, 1, off); |
14980 | oappend (scratchbuf); | |
14981 | } | |
6439fc28 | 14982 | |
52b15da3 | 14983 | static void |
3f31e633 | 14984 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14985 | { |
14986 | bfd_vma off; | |
14987 | ||
539e75ad L |
14988 | if (address_mode != mode_64bit |
14989 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14990 | { |
14991 | OP_OFF (bytemode, sizeflag); | |
14992 | return; | |
14993 | } | |
14994 | ||
3f31e633 JB |
14995 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14996 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14997 | append_seg (); |
14998 | ||
6608db57 | 14999 | off = get64 (); |
52b15da3 JH |
15000 | |
15001 | if (intel_syntax) | |
15002 | { | |
285ca992 | 15003 | if (!active_seg_prefix) |
52b15da3 | 15004 | { |
d708bcba | 15005 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
15006 | oappend (":"); |
15007 | } | |
15008 | } | |
15009 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15010 | oappend (scratchbuf); |
15011 | } | |
15012 | ||
15013 | static void | |
26ca5450 | 15014 | ptr_reg (int code, int sizeflag) |
252b5132 | 15015 | { |
2da11e11 | 15016 | const char *s; |
d708bcba | 15017 | |
1d9f512f | 15018 | *obufp++ = open_char; |
20f0a1fc | 15019 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15020 | if (address_mode == mode_64bit) |
c1a64871 JH |
15021 | { |
15022 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15023 | s = names32[code - eAX_reg]; |
c1a64871 | 15024 | else |
db6eb5be | 15025 | s = names64[code - eAX_reg]; |
c1a64871 | 15026 | } |
52b15da3 | 15027 | else if (sizeflag & AFLAG) |
252b5132 RH |
15028 | s = names32[code - eAX_reg]; |
15029 | else | |
15030 | s = names16[code - eAX_reg]; | |
15031 | oappend (s); | |
1d9f512f AM |
15032 | *obufp++ = close_char; |
15033 | *obufp = 0; | |
252b5132 RH |
15034 | } |
15035 | ||
15036 | static void | |
26ca5450 | 15037 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15038 | { |
9306ca4a | 15039 | if (intel_syntax) |
52fd6d94 JB |
15040 | { |
15041 | switch (codep[-1]) | |
15042 | { | |
15043 | case 0x6d: /* insw/insl */ | |
15044 | intel_operand_size (z_mode, sizeflag); | |
15045 | break; | |
15046 | case 0xa5: /* movsw/movsl/movsq */ | |
15047 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15048 | case 0xab: /* stosw/stosl */ | |
15049 | case 0xaf: /* scasw/scasl */ | |
15050 | intel_operand_size (v_mode, sizeflag); | |
15051 | break; | |
15052 | default: | |
15053 | intel_operand_size (b_mode, sizeflag); | |
15054 | } | |
15055 | } | |
9ce09ba2 | 15056 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15057 | ptr_reg (code, sizeflag); |
15058 | } | |
15059 | ||
15060 | static void | |
26ca5450 | 15061 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15062 | { |
9306ca4a | 15063 | if (intel_syntax) |
52fd6d94 JB |
15064 | { |
15065 | switch (codep[-1]) | |
15066 | { | |
15067 | case 0x6f: /* outsw/outsl */ | |
15068 | intel_operand_size (z_mode, sizeflag); | |
15069 | break; | |
15070 | case 0xa5: /* movsw/movsl/movsq */ | |
15071 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15072 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15073 | intel_operand_size (v_mode, sizeflag); | |
15074 | break; | |
15075 | default: | |
15076 | intel_operand_size (b_mode, sizeflag); | |
15077 | } | |
15078 | } | |
285ca992 L |
15079 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15080 | default segment register DS is printed. */ | |
15081 | if (!active_seg_prefix) | |
15082 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15083 | append_seg (); |
252b5132 RH |
15084 | ptr_reg (code, sizeflag); |
15085 | } | |
15086 | ||
252b5132 | 15087 | static void |
26ca5450 | 15088 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15089 | { |
9b60702d | 15090 | int add; |
161a04f6 | 15091 | if (rex & REX_R) |
c4a530c5 | 15092 | { |
161a04f6 | 15093 | USED_REX (REX_R); |
c4a530c5 JB |
15094 | add = 8; |
15095 | } | |
cb712a9e | 15096 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15097 | { |
f16cd0d5 | 15098 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15099 | used_prefixes |= PREFIX_LOCK; |
15100 | add = 8; | |
15101 | } | |
9b60702d L |
15102 | else |
15103 | add = 0; | |
7967e09e | 15104 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15105 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15106 | } |
15107 | ||
252b5132 | 15108 | static void |
26ca5450 | 15109 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15110 | { |
9b60702d | 15111 | int add; |
161a04f6 L |
15112 | USED_REX (REX_R); |
15113 | if (rex & REX_R) | |
52b15da3 | 15114 | add = 8; |
9b60702d L |
15115 | else |
15116 | add = 0; | |
d708bcba | 15117 | if (intel_syntax) |
7967e09e | 15118 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15119 | else |
7967e09e | 15120 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15121 | oappend (scratchbuf); |
15122 | } | |
15123 | ||
252b5132 | 15124 | static void |
26ca5450 | 15125 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15126 | { |
7967e09e | 15127 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15128 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15129 | } |
15130 | ||
15131 | static void | |
6f74c397 | 15132 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15133 | { |
68f34464 L |
15134 | /* Skip mod/rm byte. */ |
15135 | MODRM_CHECK; | |
15136 | codep++; | |
15137 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15138 | } |
15139 | ||
15140 | static void | |
26ca5450 | 15141 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15142 | { |
b9733481 L |
15143 | int reg = modrm.reg; |
15144 | const char **names; | |
15145 | ||
041bd2e0 JH |
15146 | used_prefixes |= (prefixes & PREFIX_DATA); |
15147 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15148 | { |
b9733481 | 15149 | names = names_xmm; |
161a04f6 L |
15150 | USED_REX (REX_R); |
15151 | if (rex & REX_R) | |
b9733481 | 15152 | reg += 8; |
20f0a1fc | 15153 | } |
041bd2e0 | 15154 | else |
b9733481 L |
15155 | names = names_mm; |
15156 | oappend (names[reg]); | |
252b5132 RH |
15157 | } |
15158 | ||
c608c12e | 15159 | static void |
c0f3af97 | 15160 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15161 | { |
b9733481 L |
15162 | int reg = modrm.reg; |
15163 | const char **names; | |
15164 | ||
161a04f6 L |
15165 | USED_REX (REX_R); |
15166 | if (rex & REX_R) | |
b9733481 | 15167 | reg += 8; |
43234a1e L |
15168 | if (vex.evex) |
15169 | { | |
15170 | if (!vex.r) | |
15171 | reg += 16; | |
15172 | } | |
15173 | ||
539f890d L |
15174 | if (need_vex |
15175 | && bytemode != xmm_mode | |
43234a1e L |
15176 | && bytemode != xmmq_mode |
15177 | && bytemode != evex_half_bcst_xmmq_mode | |
15178 | && bytemode != ymm_mode | |
539f890d | 15179 | && bytemode != scalar_mode) |
c0f3af97 L |
15180 | { |
15181 | switch (vex.length) | |
15182 | { | |
15183 | case 128: | |
b9733481 | 15184 | names = names_xmm; |
c0f3af97 L |
15185 | break; |
15186 | case 256: | |
5fc35d96 IT |
15187 | if (vex.w |
15188 | || (bytemode != vex_vsib_q_w_dq_mode | |
15189 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15190 | names = names_ymm; |
15191 | else | |
15192 | names = names_xmm; | |
c0f3af97 | 15193 | break; |
43234a1e L |
15194 | case 512: |
15195 | names = names_zmm; | |
15196 | break; | |
c0f3af97 L |
15197 | default: |
15198 | abort (); | |
15199 | } | |
15200 | } | |
43234a1e L |
15201 | else if (bytemode == xmmq_mode |
15202 | || bytemode == evex_half_bcst_xmmq_mode) | |
15203 | { | |
15204 | switch (vex.length) | |
15205 | { | |
15206 | case 128: | |
15207 | case 256: | |
15208 | names = names_xmm; | |
15209 | break; | |
15210 | case 512: | |
15211 | names = names_ymm; | |
15212 | break; | |
15213 | default: | |
15214 | abort (); | |
15215 | } | |
15216 | } | |
15217 | else if (bytemode == ymm_mode) | |
15218 | names = names_ymm; | |
c0f3af97 | 15219 | else |
b9733481 L |
15220 | names = names_xmm; |
15221 | oappend (names[reg]); | |
c608c12e AM |
15222 | } |
15223 | ||
252b5132 | 15224 | static void |
26ca5450 | 15225 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15226 | { |
b9733481 L |
15227 | int reg; |
15228 | const char **names; | |
15229 | ||
7967e09e | 15230 | if (modrm.mod != 3) |
252b5132 | 15231 | { |
b6169b20 L |
15232 | if (intel_syntax |
15233 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15234 | { |
15235 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15236 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15237 | } |
252b5132 RH |
15238 | OP_E (bytemode, sizeflag); |
15239 | return; | |
15240 | } | |
15241 | ||
b6169b20 L |
15242 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15243 | swap_operand (); | |
15244 | ||
6608db57 | 15245 | /* Skip mod/rm byte. */ |
4bba6815 | 15246 | MODRM_CHECK; |
252b5132 | 15247 | codep++; |
041bd2e0 | 15248 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15249 | reg = modrm.rm; |
041bd2e0 | 15250 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15251 | { |
b9733481 | 15252 | names = names_xmm; |
161a04f6 L |
15253 | USED_REX (REX_B); |
15254 | if (rex & REX_B) | |
b9733481 | 15255 | reg += 8; |
20f0a1fc | 15256 | } |
041bd2e0 | 15257 | else |
b9733481 L |
15258 | names = names_mm; |
15259 | oappend (names[reg]); | |
252b5132 RH |
15260 | } |
15261 | ||
246c51aa L |
15262 | /* cvt* are the only instructions in sse2 which have |
15263 | both SSE and MMX operands and also have 0x66 prefix | |
15264 | in their opcode. 0x66 was originally used to differentiate | |
15265 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15266 | cvt* separately using OP_EMC and OP_MXC */ |
15267 | static void | |
15268 | OP_EMC (int bytemode, int sizeflag) | |
15269 | { | |
7967e09e | 15270 | if (modrm.mod != 3) |
4d9567e0 MM |
15271 | { |
15272 | if (intel_syntax && bytemode == v_mode) | |
15273 | { | |
15274 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15275 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15276 | } |
4d9567e0 MM |
15277 | OP_E (bytemode, sizeflag); |
15278 | return; | |
15279 | } | |
246c51aa | 15280 | |
4d9567e0 MM |
15281 | /* Skip mod/rm byte. */ |
15282 | MODRM_CHECK; | |
15283 | codep++; | |
15284 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15285 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15286 | } |
15287 | ||
15288 | static void | |
15289 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15290 | { | |
15291 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15292 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15293 | } |
15294 | ||
c608c12e | 15295 | static void |
26ca5450 | 15296 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15297 | { |
b9733481 L |
15298 | int reg; |
15299 | const char **names; | |
d6f574e0 L |
15300 | |
15301 | /* Skip mod/rm byte. */ | |
15302 | MODRM_CHECK; | |
15303 | codep++; | |
15304 | ||
7967e09e | 15305 | if (modrm.mod != 3) |
c608c12e | 15306 | { |
c1e679ec | 15307 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15308 | return; |
15309 | } | |
d6f574e0 | 15310 | |
b9733481 | 15311 | reg = modrm.rm; |
161a04f6 L |
15312 | USED_REX (REX_B); |
15313 | if (rex & REX_B) | |
b9733481 | 15314 | reg += 8; |
43234a1e L |
15315 | if (vex.evex) |
15316 | { | |
15317 | USED_REX (REX_X); | |
15318 | if ((rex & REX_X)) | |
15319 | reg += 16; | |
15320 | } | |
c608c12e | 15321 | |
b6169b20 | 15322 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15323 | && (bytemode == x_swap_mode |
15324 | || bytemode == d_swap_mode | |
7bb15c6f | 15325 | || bytemode == d_scalar_swap_mode |
539f890d L |
15326 | || bytemode == q_swap_mode |
15327 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15328 | swap_operand (); |
15329 | ||
c0f3af97 L |
15330 | if (need_vex |
15331 | && bytemode != xmm_mode | |
6c30d220 L |
15332 | && bytemode != xmmdw_mode |
15333 | && bytemode != xmmqd_mode | |
15334 | && bytemode != xmm_mb_mode | |
15335 | && bytemode != xmm_mw_mode | |
15336 | && bytemode != xmm_md_mode | |
15337 | && bytemode != xmm_mq_mode | |
539f890d | 15338 | && bytemode != xmmq_mode |
43234a1e L |
15339 | && bytemode != evex_half_bcst_xmmq_mode |
15340 | && bytemode != ymm_mode | |
539f890d | 15341 | && bytemode != d_scalar_mode |
7bb15c6f | 15342 | && bytemode != d_scalar_swap_mode |
539f890d | 15343 | && bytemode != q_scalar_mode |
1c480963 L |
15344 | && bytemode != q_scalar_swap_mode |
15345 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15346 | { |
15347 | switch (vex.length) | |
15348 | { | |
15349 | case 128: | |
b9733481 | 15350 | names = names_xmm; |
c0f3af97 L |
15351 | break; |
15352 | case 256: | |
b9733481 | 15353 | names = names_ymm; |
c0f3af97 | 15354 | break; |
43234a1e L |
15355 | case 512: |
15356 | names = names_zmm; | |
15357 | break; | |
c0f3af97 L |
15358 | default: |
15359 | abort (); | |
15360 | } | |
15361 | } | |
43234a1e L |
15362 | else if (bytemode == xmmq_mode |
15363 | || bytemode == evex_half_bcst_xmmq_mode) | |
15364 | { | |
15365 | switch (vex.length) | |
15366 | { | |
15367 | case 128: | |
15368 | case 256: | |
15369 | names = names_xmm; | |
15370 | break; | |
15371 | case 512: | |
15372 | names = names_ymm; | |
15373 | break; | |
15374 | default: | |
15375 | abort (); | |
15376 | } | |
15377 | } | |
15378 | else if (bytemode == ymm_mode) | |
15379 | names = names_ymm; | |
c0f3af97 | 15380 | else |
b9733481 L |
15381 | names = names_xmm; |
15382 | oappend (names[reg]); | |
c608c12e AM |
15383 | } |
15384 | ||
252b5132 | 15385 | static void |
26ca5450 | 15386 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15387 | { |
7967e09e | 15388 | if (modrm.mod == 3) |
2da11e11 AM |
15389 | OP_EM (bytemode, sizeflag); |
15390 | else | |
6608db57 | 15391 | BadOp (); |
252b5132 RH |
15392 | } |
15393 | ||
992aaec9 | 15394 | static void |
26ca5450 | 15395 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15396 | { |
7967e09e | 15397 | if (modrm.mod == 3) |
992aaec9 AM |
15398 | OP_EX (bytemode, sizeflag); |
15399 | else | |
6608db57 | 15400 | BadOp (); |
992aaec9 AM |
15401 | } |
15402 | ||
cc0ec051 AM |
15403 | static void |
15404 | OP_M (int bytemode, int sizeflag) | |
15405 | { | |
7967e09e | 15406 | if (modrm.mod == 3) |
75413a22 L |
15407 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15408 | BadOp (); | |
cc0ec051 AM |
15409 | else |
15410 | OP_E (bytemode, sizeflag); | |
15411 | } | |
15412 | ||
15413 | static void | |
15414 | OP_0f07 (int bytemode, int sizeflag) | |
15415 | { | |
7967e09e | 15416 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15417 | BadOp (); |
15418 | else | |
15419 | OP_E (bytemode, sizeflag); | |
15420 | } | |
15421 | ||
46e883c5 | 15422 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15423 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15424 | |
cc0ec051 | 15425 | static void |
46e883c5 | 15426 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15427 | { |
8b38ad71 L |
15428 | if ((prefixes & PREFIX_DATA) != 0 |
15429 | || (rex != 0 | |
15430 | && rex != 0x48 | |
15431 | && address_mode == mode_64bit)) | |
46e883c5 L |
15432 | OP_REG (bytemode, sizeflag); |
15433 | else | |
15434 | strcpy (obuf, "nop"); | |
15435 | } | |
15436 | ||
15437 | static void | |
15438 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15439 | { | |
8b38ad71 L |
15440 | if ((prefixes & PREFIX_DATA) != 0 |
15441 | || (rex != 0 | |
15442 | && rex != 0x48 | |
15443 | && address_mode == mode_64bit)) | |
46e883c5 | 15444 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15445 | } |
15446 | ||
84037f8c | 15447 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15448 | /* 00 */ NULL, NULL, NULL, NULL, |
15449 | /* 04 */ NULL, NULL, NULL, NULL, | |
15450 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15451 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15452 | /* 10 */ NULL, NULL, NULL, NULL, |
15453 | /* 14 */ NULL, NULL, NULL, NULL, | |
15454 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15455 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15456 | /* 20 */ NULL, NULL, NULL, NULL, |
15457 | /* 24 */ NULL, NULL, NULL, NULL, | |
15458 | /* 28 */ NULL, NULL, NULL, NULL, | |
15459 | /* 2C */ NULL, NULL, NULL, NULL, | |
15460 | /* 30 */ NULL, NULL, NULL, NULL, | |
15461 | /* 34 */ NULL, NULL, NULL, NULL, | |
15462 | /* 38 */ NULL, NULL, NULL, NULL, | |
15463 | /* 3C */ NULL, NULL, NULL, NULL, | |
15464 | /* 40 */ NULL, NULL, NULL, NULL, | |
15465 | /* 44 */ NULL, NULL, NULL, NULL, | |
15466 | /* 48 */ NULL, NULL, NULL, NULL, | |
15467 | /* 4C */ NULL, NULL, NULL, NULL, | |
15468 | /* 50 */ NULL, NULL, NULL, NULL, | |
15469 | /* 54 */ NULL, NULL, NULL, NULL, | |
15470 | /* 58 */ NULL, NULL, NULL, NULL, | |
15471 | /* 5C */ NULL, NULL, NULL, NULL, | |
15472 | /* 60 */ NULL, NULL, NULL, NULL, | |
15473 | /* 64 */ NULL, NULL, NULL, NULL, | |
15474 | /* 68 */ NULL, NULL, NULL, NULL, | |
15475 | /* 6C */ NULL, NULL, NULL, NULL, | |
15476 | /* 70 */ NULL, NULL, NULL, NULL, | |
15477 | /* 74 */ NULL, NULL, NULL, NULL, | |
15478 | /* 78 */ NULL, NULL, NULL, NULL, | |
15479 | /* 7C */ NULL, NULL, NULL, NULL, | |
15480 | /* 80 */ NULL, NULL, NULL, NULL, | |
15481 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15482 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15483 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15484 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15485 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15486 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15487 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15488 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15489 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15490 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15491 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15492 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15493 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15494 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15495 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15496 | /* C0 */ NULL, NULL, NULL, NULL, | |
15497 | /* C4 */ NULL, NULL, NULL, NULL, | |
15498 | /* C8 */ NULL, NULL, NULL, NULL, | |
15499 | /* CC */ NULL, NULL, NULL, NULL, | |
15500 | /* D0 */ NULL, NULL, NULL, NULL, | |
15501 | /* D4 */ NULL, NULL, NULL, NULL, | |
15502 | /* D8 */ NULL, NULL, NULL, NULL, | |
15503 | /* DC */ NULL, NULL, NULL, NULL, | |
15504 | /* E0 */ NULL, NULL, NULL, NULL, | |
15505 | /* E4 */ NULL, NULL, NULL, NULL, | |
15506 | /* E8 */ NULL, NULL, NULL, NULL, | |
15507 | /* EC */ NULL, NULL, NULL, NULL, | |
15508 | /* F0 */ NULL, NULL, NULL, NULL, | |
15509 | /* F4 */ NULL, NULL, NULL, NULL, | |
15510 | /* F8 */ NULL, NULL, NULL, NULL, | |
15511 | /* FC */ NULL, NULL, NULL, NULL, | |
15512 | }; | |
15513 | ||
15514 | static void | |
26ca5450 | 15515 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15516 | { |
15517 | const char *mnemonic; | |
15518 | ||
15519 | FETCH_DATA (the_info, codep + 1); | |
15520 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15521 | place where an 8-bit immediate would normally go. ie. the last | |
15522 | byte of the instruction. */ | |
ea397f5b | 15523 | obufp = mnemonicendp; |
c608c12e | 15524 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15525 | if (mnemonic) |
2da11e11 | 15526 | oappend (mnemonic); |
252b5132 RH |
15527 | else |
15528 | { | |
15529 | /* Since a variable sized modrm/sib chunk is between the start | |
15530 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15531 | all the modrm processing first, and don't know until now that | |
15532 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15533 | op_out[0][0] = '\0'; |
15534 | op_out[1][0] = '\0'; | |
6608db57 | 15535 | BadOp (); |
252b5132 | 15536 | } |
ea397f5b | 15537 | mnemonicendp = obufp; |
252b5132 | 15538 | } |
c608c12e | 15539 | |
ea397f5b L |
15540 | static struct op simd_cmp_op[] = |
15541 | { | |
15542 | { STRING_COMMA_LEN ("eq") }, | |
15543 | { STRING_COMMA_LEN ("lt") }, | |
15544 | { STRING_COMMA_LEN ("le") }, | |
15545 | { STRING_COMMA_LEN ("unord") }, | |
15546 | { STRING_COMMA_LEN ("neq") }, | |
15547 | { STRING_COMMA_LEN ("nlt") }, | |
15548 | { STRING_COMMA_LEN ("nle") }, | |
15549 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15550 | }; |
15551 | ||
15552 | static void | |
ad19981d | 15553 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15554 | { |
15555 | unsigned int cmp_type; | |
15556 | ||
15557 | FETCH_DATA (the_info, codep + 1); | |
15558 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15559 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15560 | { |
ad19981d | 15561 | char suffix [3]; |
ea397f5b | 15562 | char *p = mnemonicendp - 2; |
ad19981d L |
15563 | suffix[0] = p[0]; |
15564 | suffix[1] = p[1]; | |
15565 | suffix[2] = '\0'; | |
ea397f5b L |
15566 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15567 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15568 | } |
15569 | else | |
15570 | { | |
ad19981d L |
15571 | /* We have a reserved extension byte. Output it directly. */ |
15572 | scratchbuf[0] = '$'; | |
15573 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15574 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15575 | scratchbuf[0] = '\0'; |
c608c12e AM |
15576 | } |
15577 | } | |
15578 | ||
9916071f | 15579 | static void |
7abb8d81 | 15580 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15581 | { |
7abb8d81 | 15582 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15583 | if (!intel_syntax) |
15584 | { | |
081e283f JB |
15585 | strcpy (op_out[0], names32[0]); |
15586 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15587 | if (bytemode == eBX_reg) |
081e283f | 15588 | strcpy (op_out[2], names32[3]); |
b844680a L |
15589 | two_source_ops = 1; |
15590 | } | |
15591 | /* Skip mod/rm byte. */ | |
15592 | MODRM_CHECK; | |
15593 | codep++; | |
15594 | } | |
15595 | ||
15596 | static void | |
15597 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15598 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15599 | { |
081e283f | 15600 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15601 | if (!intel_syntax) |
ca164297 | 15602 | { |
cb712a9e L |
15603 | const char **names = (address_mode == mode_64bit |
15604 | ? names64 : names32); | |
1d9f512f | 15605 | |
081e283f | 15606 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15607 | { |
b844680a | 15608 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15609 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15610 | names = (address_mode != mode_32bit |
15611 | ? names32 : names16); | |
b844680a | 15612 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15613 | } |
081e283f JB |
15614 | else if (address_mode == mode_16bit) |
15615 | names = names16; | |
15616 | strcpy (op_out[0], names[0]); | |
15617 | strcpy (op_out[1], names32[1]); | |
15618 | strcpy (op_out[2], names32[2]); | |
b844680a | 15619 | two_source_ops = 1; |
ca164297 | 15620 | } |
b844680a L |
15621 | /* Skip mod/rm byte. */ |
15622 | MODRM_CHECK; | |
15623 | codep++; | |
30123838 JB |
15624 | } |
15625 | ||
6608db57 KH |
15626 | static void |
15627 | BadOp (void) | |
2da11e11 | 15628 | { |
6608db57 KH |
15629 | /* Throw away prefixes and 1st. opcode byte. */ |
15630 | codep = insn_codep + 1; | |
2da11e11 AM |
15631 | oappend ("(bad)"); |
15632 | } | |
4cc91dba | 15633 | |
35c52694 L |
15634 | static void |
15635 | REP_Fixup (int bytemode, int sizeflag) | |
15636 | { | |
15637 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15638 | lods and stos. */ | |
35c52694 | 15639 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15640 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15641 | |
15642 | switch (bytemode) | |
15643 | { | |
15644 | case al_reg: | |
15645 | case eAX_reg: | |
15646 | case indir_dx_reg: | |
15647 | OP_IMREG (bytemode, sizeflag); | |
15648 | break; | |
15649 | case eDI_reg: | |
15650 | OP_ESreg (bytemode, sizeflag); | |
15651 | break; | |
15652 | case eSI_reg: | |
15653 | OP_DSreg (bytemode, sizeflag); | |
15654 | break; | |
15655 | default: | |
15656 | abort (); | |
15657 | break; | |
15658 | } | |
15659 | } | |
f5804c90 | 15660 | |
d835a58b JB |
15661 | static void |
15662 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15663 | { | |
15664 | if ( isa64 != amd64 ) | |
15665 | return; | |
15666 | ||
15667 | obufp = obuf; | |
15668 | BadOp (); | |
15669 | mnemonicendp = obufp; | |
15670 | ++codep; | |
15671 | } | |
15672 | ||
7e8b059b L |
15673 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15674 | "bnd". */ | |
15675 | ||
15676 | static void | |
15677 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15678 | { | |
15679 | if (prefixes & PREFIX_REPNZ) | |
15680 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15681 | } | |
15682 | ||
04ef582a L |
15683 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15684 | "notrack". */ | |
15685 | ||
15686 | static void | |
15687 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15688 | int sizeflag ATTRIBUTE_UNUSED) | |
15689 | { | |
9fef80d6 | 15690 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15691 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15692 | { | |
4e9ac44a | 15693 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15694 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15695 | active_seg_prefix = 0; |
15696 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15697 | } | |
15698 | } | |
15699 | ||
42164a71 L |
15700 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15701 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15702 | */ | |
15703 | ||
15704 | static void | |
15705 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15706 | { | |
15707 | if (modrm.mod != 3 | |
15708 | && (prefixes & PREFIX_LOCK) != 0) | |
15709 | { | |
15710 | if (prefixes & PREFIX_REPZ) | |
15711 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15712 | if (prefixes & PREFIX_REPNZ) | |
15713 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15714 | } | |
15715 | ||
15716 | OP_E (bytemode, sizeflag); | |
15717 | } | |
15718 | ||
15719 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15720 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15721 | */ | |
15722 | ||
15723 | static void | |
15724 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15725 | { | |
15726 | if (modrm.mod != 3) | |
15727 | { | |
15728 | if (prefixes & PREFIX_REPZ) | |
15729 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15730 | if (prefixes & PREFIX_REPNZ) | |
15731 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15732 | } | |
15733 | ||
15734 | OP_E (bytemode, sizeflag); | |
15735 | } | |
15736 | ||
15737 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15738 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15739 | ||
15740 | static void | |
15741 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15742 | { | |
15743 | if (modrm.mod != 3 | |
15744 | && last_repz_prefix > last_repnz_prefix | |
15745 | && (prefixes & PREFIX_REPZ) != 0) | |
15746 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15747 | ||
15748 | OP_E (bytemode, sizeflag); | |
15749 | } | |
15750 | ||
f5804c90 L |
15751 | static void |
15752 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15753 | { | |
161a04f6 L |
15754 | USED_REX (REX_W); |
15755 | if (rex & REX_W) | |
f5804c90 L |
15756 | { |
15757 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15758 | char *p = mnemonicendp - 2; |
15759 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15760 | bytemode = o_mode; |
f5804c90 | 15761 | } |
42164a71 L |
15762 | else if ((prefixes & PREFIX_LOCK) != 0) |
15763 | { | |
15764 | if (prefixes & PREFIX_REPZ) | |
15765 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15766 | if (prefixes & PREFIX_REPNZ) | |
15767 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15768 | } | |
15769 | ||
f5804c90 L |
15770 | OP_M (bytemode, sizeflag); |
15771 | } | |
42903f7f L |
15772 | |
15773 | static void | |
15774 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15775 | { | |
b9733481 L |
15776 | const char **names; |
15777 | ||
c0f3af97 L |
15778 | if (need_vex) |
15779 | { | |
15780 | switch (vex.length) | |
15781 | { | |
15782 | case 128: | |
b9733481 | 15783 | names = names_xmm; |
c0f3af97 L |
15784 | break; |
15785 | case 256: | |
b9733481 | 15786 | names = names_ymm; |
c0f3af97 L |
15787 | break; |
15788 | default: | |
15789 | abort (); | |
15790 | } | |
15791 | } | |
15792 | else | |
b9733481 L |
15793 | names = names_xmm; |
15794 | oappend (names[reg]); | |
42903f7f | 15795 | } |
381d071f L |
15796 | |
15797 | static void | |
15798 | CRC32_Fixup (int bytemode, int sizeflag) | |
15799 | { | |
15800 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15801 | char *p = mnemonicendp; |
381d071f L |
15802 | |
15803 | switch (bytemode) | |
15804 | { | |
15805 | case b_mode: | |
20592a94 | 15806 | if (intel_syntax) |
ea397f5b | 15807 | goto skip; |
20592a94 | 15808 | |
381d071f L |
15809 | *p++ = 'b'; |
15810 | break; | |
15811 | case v_mode: | |
20592a94 | 15812 | if (intel_syntax) |
ea397f5b | 15813 | goto skip; |
20592a94 | 15814 | |
381d071f L |
15815 | USED_REX (REX_W); |
15816 | if (rex & REX_W) | |
15817 | *p++ = 'q'; | |
7bb15c6f | 15818 | else |
f16cd0d5 L |
15819 | { |
15820 | if (sizeflag & DFLAG) | |
15821 | *p++ = 'l'; | |
15822 | else | |
15823 | *p++ = 'w'; | |
15824 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15825 | } | |
381d071f L |
15826 | break; |
15827 | default: | |
15828 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15829 | break; | |
15830 | } | |
ea397f5b | 15831 | mnemonicendp = p; |
381d071f L |
15832 | *p = '\0'; |
15833 | ||
dc1e8a47 | 15834 | skip: |
381d071f L |
15835 | if (modrm.mod == 3) |
15836 | { | |
15837 | int add; | |
15838 | ||
15839 | /* Skip mod/rm byte. */ | |
15840 | MODRM_CHECK; | |
15841 | codep++; | |
15842 | ||
15843 | USED_REX (REX_B); | |
15844 | add = (rex & REX_B) ? 8 : 0; | |
15845 | if (bytemode == b_mode) | |
15846 | { | |
15847 | USED_REX (0); | |
15848 | if (rex) | |
15849 | oappend (names8rex[modrm.rm + add]); | |
15850 | else | |
15851 | oappend (names8[modrm.rm + add]); | |
15852 | } | |
15853 | else | |
15854 | { | |
15855 | USED_REX (REX_W); | |
15856 | if (rex & REX_W) | |
15857 | oappend (names64[modrm.rm + add]); | |
15858 | else if ((prefixes & PREFIX_DATA)) | |
15859 | oappend (names16[modrm.rm + add]); | |
15860 | else | |
15861 | oappend (names32[modrm.rm + add]); | |
15862 | } | |
15863 | } | |
15864 | else | |
9344ff29 | 15865 | OP_E (bytemode, sizeflag); |
381d071f | 15866 | } |
85f10a01 | 15867 | |
eacc9c89 L |
15868 | static void |
15869 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15870 | { | |
15871 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15872 | USED_REX (REX_W); | |
15873 | if (rex & REX_W) | |
15874 | { | |
15875 | char *p = mnemonicendp; | |
15876 | *p++ = '6'; | |
15877 | *p++ = '4'; | |
15878 | *p = '\0'; | |
15879 | mnemonicendp = p; | |
15880 | } | |
15881 | OP_M (bytemode, sizeflag); | |
15882 | } | |
15883 | ||
15c7c1d8 JB |
15884 | static void |
15885 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15886 | { | |
15887 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15888 | if (!intel_syntax) | |
15889 | { | |
15890 | char *p = mnemonicendp; | |
15891 | ||
15892 | USED_REX (REX_W); | |
15893 | if (rex & REX_W) | |
15894 | *p++ = 'q'; | |
15895 | else if (sizeflag & SUFFIX_ALWAYS) | |
15896 | *p++ = 'l'; | |
15897 | ||
15898 | *p = '\0'; | |
15899 | mnemonicendp = p; | |
15900 | } | |
15901 | ||
15902 | OP_EX (bytemode, sizeflag); | |
15903 | } | |
15904 | ||
c0f3af97 L |
15905 | /* Display the destination register operand for instructions with |
15906 | VEX. */ | |
15907 | ||
15908 | static void | |
15909 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15910 | { | |
539f890d | 15911 | int reg; |
b9733481 L |
15912 | const char **names; |
15913 | ||
c0f3af97 L |
15914 | if (!need_vex) |
15915 | abort (); | |
15916 | ||
15917 | if (!need_vex_reg) | |
15918 | return; | |
15919 | ||
539f890d | 15920 | reg = vex.register_specifier; |
63c6fc6c | 15921 | vex.register_specifier = 0; |
5f847646 JB |
15922 | if (address_mode != mode_64bit) |
15923 | reg &= 7; | |
15924 | else if (vex.evex && !vex.v) | |
15925 | reg += 16; | |
43234a1e | 15926 | |
539f890d L |
15927 | if (bytemode == vex_scalar_mode) |
15928 | { | |
15929 | oappend (names_xmm[reg]); | |
15930 | return; | |
15931 | } | |
15932 | ||
c0f3af97 L |
15933 | switch (vex.length) |
15934 | { | |
15935 | case 128: | |
15936 | switch (bytemode) | |
15937 | { | |
15938 | case vex_mode: | |
15939 | case vex128_mode: | |
6c30d220 | 15940 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15941 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15942 | names = names_xmm; |
15943 | break; | |
15944 | case dq_mode: | |
390a6789 | 15945 | if (rex & REX_W) |
cb21baef L |
15946 | names = names64; |
15947 | else | |
15948 | names = names32; | |
c0f3af97 | 15949 | break; |
1ba585e8 | 15950 | case mask_bd_mode: |
43234a1e | 15951 | case mask_mode: |
9889cbb1 L |
15952 | if (reg > 0x7) |
15953 | { | |
15954 | oappend ("(bad)"); | |
15955 | return; | |
15956 | } | |
43234a1e L |
15957 | names = names_mask; |
15958 | break; | |
c0f3af97 L |
15959 | default: |
15960 | abort (); | |
15961 | return; | |
15962 | } | |
c0f3af97 L |
15963 | break; |
15964 | case 256: | |
15965 | switch (bytemode) | |
15966 | { | |
15967 | case vex_mode: | |
15968 | case vex256_mode: | |
6c30d220 L |
15969 | names = names_ymm; |
15970 | break; | |
15971 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15972 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15973 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15974 | break; |
1ba585e8 | 15975 | case mask_bd_mode: |
43234a1e | 15976 | case mask_mode: |
9889cbb1 L |
15977 | if (reg > 0x7) |
15978 | { | |
15979 | oappend ("(bad)"); | |
15980 | return; | |
15981 | } | |
43234a1e L |
15982 | names = names_mask; |
15983 | break; | |
c0f3af97 | 15984 | default: |
a37a2806 NC |
15985 | /* See PR binutils/20893 for a reproducer. */ |
15986 | oappend ("(bad)"); | |
c0f3af97 L |
15987 | return; |
15988 | } | |
c0f3af97 | 15989 | break; |
43234a1e L |
15990 | case 512: |
15991 | names = names_zmm; | |
15992 | break; | |
c0f3af97 L |
15993 | default: |
15994 | abort (); | |
15995 | break; | |
15996 | } | |
539f890d | 15997 | oappend (names[reg]); |
c0f3af97 L |
15998 | } |
15999 | ||
922d8de8 DR |
16000 | /* Get the VEX immediate byte without moving codep. */ |
16001 | ||
16002 | static unsigned char | |
ccc5981b | 16003 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16004 | { |
16005 | int bytes_before_imm = 0; | |
16006 | ||
922d8de8 DR |
16007 | if (modrm.mod != 3) |
16008 | { | |
16009 | /* There are SIB/displacement bytes. */ | |
16010 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16011 | { |
922d8de8 | 16012 | /* 32/64 bit address mode */ |
6c067bbb | 16013 | int base = modrm.rm; |
922d8de8 DR |
16014 | |
16015 | /* Check SIB byte. */ | |
6c067bbb RM |
16016 | if (base == 4) |
16017 | { | |
16018 | FETCH_DATA (the_info, codep + 1); | |
16019 | base = *codep & 7; | |
16020 | /* When decoding the third source, don't increase | |
16021 | bytes_before_imm as this has already been incremented | |
16022 | by one in OP_E_memory while decoding the second | |
16023 | source operand. */ | |
16024 | if (opnum == 0) | |
16025 | bytes_before_imm++; | |
16026 | } | |
16027 | ||
16028 | /* Don't increase bytes_before_imm when decoding the third source, | |
16029 | it has already been incremented by OP_E_memory while decoding | |
16030 | the second source operand. */ | |
16031 | if (opnum == 0) | |
16032 | { | |
16033 | switch (modrm.mod) | |
16034 | { | |
16035 | case 0: | |
16036 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16037 | SIB == 5, there is a 4 byte displacement. */ | |
16038 | if (base != 5) | |
16039 | /* No displacement. */ | |
16040 | break; | |
1a0670f3 | 16041 | /* Fall through. */ |
6c067bbb RM |
16042 | case 2: |
16043 | /* 4 byte displacement. */ | |
16044 | bytes_before_imm += 4; | |
16045 | break; | |
16046 | case 1: | |
16047 | /* 1 byte displacement. */ | |
16048 | bytes_before_imm++; | |
16049 | break; | |
16050 | } | |
16051 | } | |
16052 | } | |
922d8de8 | 16053 | else |
02e647f9 SP |
16054 | { |
16055 | /* 16 bit address mode */ | |
6c067bbb RM |
16056 | /* Don't increase bytes_before_imm when decoding the third source, |
16057 | it has already been incremented by OP_E_memory while decoding | |
16058 | the second source operand. */ | |
16059 | if (opnum == 0) | |
16060 | { | |
02e647f9 SP |
16061 | switch (modrm.mod) |
16062 | { | |
16063 | case 0: | |
16064 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16065 | if (modrm.rm != 6) | |
16066 | /* No displacement. */ | |
16067 | break; | |
1a0670f3 | 16068 | /* Fall through. */ |
02e647f9 SP |
16069 | case 2: |
16070 | /* 2 byte displacement. */ | |
16071 | bytes_before_imm += 2; | |
16072 | break; | |
16073 | case 1: | |
16074 | /* 1 byte displacement: when decoding the third source, | |
16075 | don't increase bytes_before_imm as this has already | |
16076 | been incremented by one in OP_E_memory while decoding | |
16077 | the second source operand. */ | |
16078 | if (opnum == 0) | |
16079 | bytes_before_imm++; | |
ccc5981b | 16080 | |
02e647f9 SP |
16081 | break; |
16082 | } | |
922d8de8 DR |
16083 | } |
16084 | } | |
16085 | } | |
16086 | ||
16087 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16088 | return codep [bytes_before_imm]; | |
16089 | } | |
16090 | ||
16091 | static void | |
16092 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16093 | { | |
b9733481 L |
16094 | const char **names; |
16095 | ||
922d8de8 DR |
16096 | if (reg == -1 && modrm.mod != 3) |
16097 | { | |
16098 | OP_E_memory (bytemode, sizeflag); | |
16099 | return; | |
16100 | } | |
16101 | else | |
16102 | { | |
16103 | if (reg == -1) | |
16104 | { | |
16105 | reg = modrm.rm; | |
16106 | USED_REX (REX_B); | |
16107 | if (rex & REX_B) | |
16108 | reg += 8; | |
16109 | } | |
5f847646 JB |
16110 | if (address_mode != mode_64bit) |
16111 | reg &= 7; | |
922d8de8 DR |
16112 | } |
16113 | ||
16114 | switch (vex.length) | |
16115 | { | |
16116 | case 128: | |
b9733481 | 16117 | names = names_xmm; |
922d8de8 DR |
16118 | break; |
16119 | case 256: | |
b9733481 | 16120 | names = names_ymm; |
922d8de8 DR |
16121 | break; |
16122 | default: | |
16123 | abort (); | |
16124 | } | |
b9733481 | 16125 | oappend (names[reg]); |
922d8de8 DR |
16126 | } |
16127 | ||
a683cc34 SP |
16128 | static void |
16129 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16130 | { | |
16131 | int reg = -1; | |
16132 | static unsigned char vex_imm8; | |
16133 | ||
16134 | if (vex_w_done == 0) | |
16135 | { | |
16136 | vex_w_done = 1; | |
16137 | ||
16138 | /* Skip mod/rm byte. */ | |
16139 | MODRM_CHECK; | |
16140 | codep++; | |
16141 | ||
16142 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16143 | ||
16144 | if (vex.w) | |
16145 | reg = vex_imm8 >> 4; | |
16146 | ||
16147 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16148 | } | |
16149 | else if (vex_w_done == 1) | |
16150 | { | |
16151 | vex_w_done = 2; | |
16152 | ||
16153 | if (!vex.w) | |
16154 | reg = vex_imm8 >> 4; | |
16155 | ||
16156 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16157 | } | |
16158 | else | |
16159 | { | |
16160 | /* Output the imm8 directly. */ | |
16161 | scratchbuf[0] = '$'; | |
16162 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16163 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16164 | scratchbuf[0] = '\0'; |
16165 | codep++; | |
16166 | } | |
16167 | } | |
16168 | ||
5dd85c99 SP |
16169 | static void |
16170 | OP_Vex_2src (int bytemode, int sizeflag) | |
16171 | { | |
16172 | if (modrm.mod == 3) | |
16173 | { | |
b9733481 | 16174 | int reg = modrm.rm; |
5dd85c99 | 16175 | USED_REX (REX_B); |
b9733481 L |
16176 | if (rex & REX_B) |
16177 | reg += 8; | |
16178 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16179 | } |
16180 | else | |
16181 | { | |
16182 | if (intel_syntax | |
16183 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16184 | { | |
16185 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16186 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16187 | } | |
16188 | OP_E (bytemode, sizeflag); | |
16189 | } | |
16190 | } | |
16191 | ||
16192 | static void | |
16193 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16194 | { | |
16195 | if (modrm.mod == 3) | |
16196 | { | |
16197 | /* Skip mod/rm byte. */ | |
16198 | MODRM_CHECK; | |
16199 | codep++; | |
16200 | } | |
16201 | ||
16202 | if (vex.w) | |
5f847646 JB |
16203 | { |
16204 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16205 | vex.register_specifier = 0; |
5f847646 JB |
16206 | |
16207 | if (address_mode != mode_64bit) | |
16208 | reg &= 7; | |
16209 | oappend (names_xmm[reg]); | |
16210 | } | |
5dd85c99 SP |
16211 | else |
16212 | OP_Vex_2src (bytemode, sizeflag); | |
16213 | } | |
16214 | ||
16215 | static void | |
16216 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16217 | { | |
16218 | if (vex.w) | |
16219 | OP_Vex_2src (bytemode, sizeflag); | |
16220 | else | |
5f847646 JB |
16221 | { |
16222 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16223 | vex.register_specifier = 0; |
5f847646 JB |
16224 | |
16225 | if (address_mode != mode_64bit) | |
16226 | reg &= 7; | |
16227 | oappend (names_xmm[reg]); | |
16228 | } | |
5dd85c99 SP |
16229 | } |
16230 | ||
922d8de8 DR |
16231 | static void |
16232 | OP_EX_VexW (int bytemode, int sizeflag) | |
16233 | { | |
16234 | int reg = -1; | |
16235 | ||
16236 | if (!vex_w_done) | |
16237 | { | |
41effecb SP |
16238 | /* Skip mod/rm byte. */ |
16239 | MODRM_CHECK; | |
16240 | codep++; | |
16241 | ||
922d8de8 | 16242 | if (vex.w) |
ccc5981b | 16243 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16244 | } |
16245 | else | |
16246 | { | |
16247 | if (!vex.w) | |
ccc5981b | 16248 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16249 | } |
16250 | ||
16251 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16252 | |
3a2430e0 JB |
16253 | if (vex_w_done) |
16254 | codep++; | |
16255 | vex_w_done = 1; | |
922d8de8 DR |
16256 | } |
16257 | ||
c0f3af97 L |
16258 | static void |
16259 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16260 | { | |
16261 | int reg; | |
b9733481 L |
16262 | const char **names; |
16263 | ||
c0f3af97 L |
16264 | FETCH_DATA (the_info, codep + 1); |
16265 | reg = *codep++; | |
16266 | ||
16267 | if (bytemode != x_mode) | |
16268 | abort (); | |
16269 | ||
c0f3af97 | 16270 | reg >>= 4; |
5f847646 JB |
16271 | if (address_mode != mode_64bit) |
16272 | reg &= 7; | |
dae39acc | 16273 | |
c0f3af97 L |
16274 | switch (vex.length) |
16275 | { | |
16276 | case 128: | |
b9733481 | 16277 | names = names_xmm; |
c0f3af97 L |
16278 | break; |
16279 | case 256: | |
b9733481 | 16280 | names = names_ymm; |
c0f3af97 L |
16281 | break; |
16282 | default: | |
16283 | abort (); | |
16284 | } | |
b9733481 | 16285 | oappend (names[reg]); |
c0f3af97 L |
16286 | } |
16287 | ||
922d8de8 DR |
16288 | static void |
16289 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16290 | { | |
16291 | /* Turn off the REX.W bit since it is used for swapping operands | |
16292 | now. */ | |
16293 | rex &= ~REX_W; | |
16294 | OP_XMM (bytemode, sizeflag); | |
16295 | } | |
16296 | ||
c0f3af97 L |
16297 | static void |
16298 | OP_EX_Vex (int bytemode, int sizeflag) | |
16299 | { | |
16300 | if (modrm.mod != 3) | |
63c6fc6c | 16301 | need_vex_reg = 0; |
c0f3af97 L |
16302 | OP_EX (bytemode, sizeflag); |
16303 | } | |
16304 | ||
16305 | static void | |
16306 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16307 | { | |
16308 | if (modrm.mod != 3) | |
63c6fc6c | 16309 | need_vex_reg = 0; |
c0f3af97 L |
16310 | OP_XMM (bytemode, sizeflag); |
16311 | } | |
16312 | ||
ea397f5b L |
16313 | static struct op vex_cmp_op[] = |
16314 | { | |
16315 | { STRING_COMMA_LEN ("eq") }, | |
16316 | { STRING_COMMA_LEN ("lt") }, | |
16317 | { STRING_COMMA_LEN ("le") }, | |
16318 | { STRING_COMMA_LEN ("unord") }, | |
16319 | { STRING_COMMA_LEN ("neq") }, | |
16320 | { STRING_COMMA_LEN ("nlt") }, | |
16321 | { STRING_COMMA_LEN ("nle") }, | |
16322 | { STRING_COMMA_LEN ("ord") }, | |
16323 | { STRING_COMMA_LEN ("eq_uq") }, | |
16324 | { STRING_COMMA_LEN ("nge") }, | |
16325 | { STRING_COMMA_LEN ("ngt") }, | |
16326 | { STRING_COMMA_LEN ("false") }, | |
16327 | { STRING_COMMA_LEN ("neq_oq") }, | |
16328 | { STRING_COMMA_LEN ("ge") }, | |
16329 | { STRING_COMMA_LEN ("gt") }, | |
16330 | { STRING_COMMA_LEN ("true") }, | |
16331 | { STRING_COMMA_LEN ("eq_os") }, | |
16332 | { STRING_COMMA_LEN ("lt_oq") }, | |
16333 | { STRING_COMMA_LEN ("le_oq") }, | |
16334 | { STRING_COMMA_LEN ("unord_s") }, | |
16335 | { STRING_COMMA_LEN ("neq_us") }, | |
16336 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16337 | { STRING_COMMA_LEN ("nle_uq") }, | |
16338 | { STRING_COMMA_LEN ("ord_s") }, | |
16339 | { STRING_COMMA_LEN ("eq_us") }, | |
16340 | { STRING_COMMA_LEN ("nge_uq") }, | |
16341 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16342 | { STRING_COMMA_LEN ("false_os") }, | |
16343 | { STRING_COMMA_LEN ("neq_os") }, | |
16344 | { STRING_COMMA_LEN ("ge_oq") }, | |
16345 | { STRING_COMMA_LEN ("gt_oq") }, | |
16346 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16347 | }; |
16348 | ||
16349 | static void | |
16350 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16351 | { | |
16352 | unsigned int cmp_type; | |
16353 | ||
16354 | FETCH_DATA (the_info, codep + 1); | |
16355 | cmp_type = *codep++ & 0xff; | |
16356 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16357 | { | |
16358 | char suffix [3]; | |
ea397f5b | 16359 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16360 | suffix[0] = p[0]; |
16361 | suffix[1] = p[1]; | |
16362 | suffix[2] = '\0'; | |
ea397f5b L |
16363 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16364 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16365 | } |
16366 | else | |
16367 | { | |
16368 | /* We have a reserved extension byte. Output it directly. */ | |
16369 | scratchbuf[0] = '$'; | |
16370 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16371 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16372 | scratchbuf[0] = '\0'; |
16373 | } | |
16374 | } | |
16375 | ||
43234a1e L |
16376 | static void |
16377 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16378 | int sizeflag ATTRIBUTE_UNUSED) | |
16379 | { | |
16380 | unsigned int cmp_type; | |
16381 | ||
16382 | if (!vex.evex) | |
16383 | abort (); | |
16384 | ||
16385 | FETCH_DATA (the_info, codep + 1); | |
16386 | cmp_type = *codep++ & 0xff; | |
16387 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16388 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16389 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16390 | && cmp_type != 3 | |
16391 | && cmp_type != 7) | |
16392 | { | |
16393 | char suffix [3]; | |
16394 | char *p = mnemonicendp - 2; | |
16395 | ||
16396 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16397 | if (p[0] == 'p') | |
16398 | { | |
16399 | p++; | |
16400 | suffix[0] = p[0]; | |
16401 | suffix[1] = '\0'; | |
16402 | } | |
16403 | else | |
16404 | { | |
16405 | suffix[0] = p[0]; | |
16406 | suffix[1] = p[1]; | |
16407 | suffix[2] = '\0'; | |
16408 | } | |
16409 | ||
16410 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16411 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16412 | } | |
be92cb14 JB |
16413 | else |
16414 | { | |
16415 | /* We have a reserved extension byte. Output it directly. */ | |
16416 | scratchbuf[0] = '$'; | |
16417 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16418 | oappend_maybe_intel (scratchbuf); | |
16419 | scratchbuf[0] = '\0'; | |
16420 | } | |
16421 | } | |
16422 | ||
16423 | static const struct op xop_cmp_op[] = | |
16424 | { | |
16425 | { STRING_COMMA_LEN ("lt") }, | |
16426 | { STRING_COMMA_LEN ("le") }, | |
16427 | { STRING_COMMA_LEN ("gt") }, | |
16428 | { STRING_COMMA_LEN ("ge") }, | |
16429 | { STRING_COMMA_LEN ("eq") }, | |
16430 | { STRING_COMMA_LEN ("neq") }, | |
16431 | { STRING_COMMA_LEN ("false") }, | |
16432 | { STRING_COMMA_LEN ("true") } | |
16433 | }; | |
16434 | ||
16435 | static void | |
16436 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16437 | int sizeflag ATTRIBUTE_UNUSED) | |
16438 | { | |
16439 | unsigned int cmp_type; | |
16440 | ||
16441 | FETCH_DATA (the_info, codep + 1); | |
16442 | cmp_type = *codep++ & 0xff; | |
16443 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16444 | { | |
16445 | char suffix[3]; | |
16446 | char *p = mnemonicendp - 2; | |
16447 | ||
16448 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16449 | if (p[0] == 'm') | |
16450 | { | |
16451 | p++; | |
16452 | suffix[0] = p[0]; | |
16453 | suffix[1] = '\0'; | |
16454 | } | |
16455 | else | |
16456 | { | |
16457 | suffix[0] = p[0]; | |
16458 | suffix[1] = p[1]; | |
16459 | suffix[2] = '\0'; | |
16460 | } | |
16461 | ||
16462 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16463 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16464 | } | |
43234a1e L |
16465 | else |
16466 | { | |
16467 | /* We have a reserved extension byte. Output it directly. */ | |
16468 | scratchbuf[0] = '$'; | |
16469 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16470 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16471 | scratchbuf[0] = '\0'; |
16472 | } | |
16473 | } | |
16474 | ||
ea397f5b L |
16475 | static const struct op pclmul_op[] = |
16476 | { | |
16477 | { STRING_COMMA_LEN ("lql") }, | |
16478 | { STRING_COMMA_LEN ("hql") }, | |
16479 | { STRING_COMMA_LEN ("lqh") }, | |
16480 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16481 | }; |
16482 | ||
16483 | static void | |
16484 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16485 | int sizeflag ATTRIBUTE_UNUSED) | |
16486 | { | |
16487 | unsigned int pclmul_type; | |
16488 | ||
16489 | FETCH_DATA (the_info, codep + 1); | |
16490 | pclmul_type = *codep++ & 0xff; | |
16491 | switch (pclmul_type) | |
16492 | { | |
16493 | case 0x10: | |
16494 | pclmul_type = 2; | |
16495 | break; | |
16496 | case 0x11: | |
16497 | pclmul_type = 3; | |
16498 | break; | |
16499 | default: | |
16500 | break; | |
7bb15c6f | 16501 | } |
c0f3af97 L |
16502 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16503 | { | |
16504 | char suffix [4]; | |
ea397f5b | 16505 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16506 | suffix[0] = p[0]; |
16507 | suffix[1] = p[1]; | |
16508 | suffix[2] = p[2]; | |
16509 | suffix[3] = '\0'; | |
ea397f5b L |
16510 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16511 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16512 | } |
16513 | else | |
16514 | { | |
16515 | /* We have a reserved extension byte. Output it directly. */ | |
16516 | scratchbuf[0] = '$'; | |
16517 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16518 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16519 | scratchbuf[0] = '\0'; |
16520 | } | |
16521 | } | |
16522 | ||
f1f8f695 L |
16523 | static void |
16524 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16525 | { | |
16526 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16527 | char *p = mnemonicendp; |
f1f8f695 L |
16528 | |
16529 | switch (bytemode) | |
16530 | { | |
16531 | case v_mode: | |
16532 | if (intel_syntax) | |
ea397f5b | 16533 | goto skip; |
f1f8f695 L |
16534 | |
16535 | USED_REX (REX_W); | |
16536 | if (sizeflag & SUFFIX_ALWAYS) | |
16537 | { | |
16538 | if (rex & REX_W) | |
16539 | *p++ = 'q'; | |
f1f8f695 | 16540 | else |
f16cd0d5 L |
16541 | { |
16542 | if (sizeflag & DFLAG) | |
16543 | *p++ = 'l'; | |
16544 | else | |
16545 | *p++ = 'w'; | |
16546 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16547 | } | |
f1f8f695 | 16548 | } |
f1f8f695 L |
16549 | break; |
16550 | default: | |
16551 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16552 | break; | |
16553 | } | |
ea397f5b | 16554 | mnemonicendp = p; |
f1f8f695 L |
16555 | *p = '\0'; |
16556 | ||
dc1e8a47 | 16557 | skip: |
f1f8f695 L |
16558 | OP_M (bytemode, sizeflag); |
16559 | } | |
f88c9eb0 | 16560 | |
bc31405e L |
16561 | static void |
16562 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16563 | { | |
16564 | /* Add proper suffix to "movsxd". */ | |
16565 | char *p = mnemonicendp; | |
16566 | ||
16567 | switch (bytemode) | |
16568 | { | |
16569 | case movsxd_mode: | |
16570 | if (intel_syntax) | |
16571 | { | |
16572 | *p++ = 'x'; | |
16573 | *p++ = 'd'; | |
16574 | goto skip; | |
16575 | } | |
16576 | ||
16577 | USED_REX (REX_W); | |
16578 | if (rex & REX_W) | |
16579 | { | |
16580 | *p++ = 'l'; | |
16581 | *p++ = 'q'; | |
16582 | } | |
16583 | else | |
16584 | { | |
16585 | *p++ = 'x'; | |
16586 | *p++ = 'd'; | |
16587 | } | |
16588 | break; | |
16589 | default: | |
16590 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16591 | break; | |
16592 | } | |
16593 | ||
dc1e8a47 | 16594 | skip: |
bc31405e L |
16595 | mnemonicendp = p; |
16596 | *p = '\0'; | |
16597 | OP_E (bytemode, sizeflag); | |
16598 | } | |
16599 | ||
f88c9eb0 SP |
16600 | static void |
16601 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16602 | { | |
16603 | int reg; | |
16604 | const char **names; | |
16605 | ||
16606 | /* Skip mod/rm byte. */ | |
16607 | MODRM_CHECK; | |
16608 | codep++; | |
16609 | ||
390a6789 | 16610 | if (rex & REX_W) |
f88c9eb0 | 16611 | names = names64; |
f88c9eb0 | 16612 | else |
ce7d077e | 16613 | names = names32; |
f88c9eb0 SP |
16614 | |
16615 | reg = modrm.rm; | |
16616 | USED_REX (REX_B); | |
16617 | if (rex & REX_B) | |
16618 | reg += 8; | |
16619 | ||
16620 | oappend (names[reg]); | |
16621 | } | |
16622 | ||
16623 | static void | |
16624 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16625 | { | |
16626 | const char **names; | |
5f847646 | 16627 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16628 | vex.register_specifier = 0; |
f88c9eb0 | 16629 | |
390a6789 | 16630 | if (rex & REX_W) |
f88c9eb0 | 16631 | names = names64; |
f88c9eb0 | 16632 | else |
ce7d077e | 16633 | names = names32; |
f88c9eb0 | 16634 | |
5f847646 JB |
16635 | if (address_mode != mode_64bit) |
16636 | reg &= 7; | |
16637 | oappend (names[reg]); | |
f88c9eb0 | 16638 | } |
43234a1e L |
16639 | |
16640 | static void | |
16641 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16642 | { | |
16643 | if (!vex.evex | |
1ba585e8 | 16644 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16645 | abort (); |
16646 | ||
16647 | USED_REX (REX_R); | |
16648 | if ((rex & REX_R) != 0 || !vex.r) | |
16649 | { | |
16650 | BadOp (); | |
16651 | return; | |
16652 | } | |
16653 | ||
16654 | oappend (names_mask [modrm.reg]); | |
16655 | } | |
16656 | ||
16657 | static void | |
16658 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16659 | { | |
16660 | if (!vex.evex | |
16661 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 16662 | && bytemode != evex_rounding_64_mode |
43234a1e L |
16663 | && bytemode != evex_sae_mode)) |
16664 | abort (); | |
16665 | if (modrm.mod == 3 && vex.b) | |
16666 | switch (bytemode) | |
16667 | { | |
70df6fc9 L |
16668 | case evex_rounding_64_mode: |
16669 | if (address_mode != mode_64bit) | |
16670 | { | |
16671 | oappend ("(bad)"); | |
16672 | break; | |
16673 | } | |
16674 | /* Fall through. */ | |
43234a1e L |
16675 | case evex_rounding_mode: |
16676 | oappend (names_rounding[vex.ll]); | |
16677 | break; | |
16678 | case evex_sae_mode: | |
16679 | oappend ("{sae}"); | |
16680 | break; | |
16681 | default: | |
16682 | break; | |
16683 | } | |
16684 | } |