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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 | 89 | static void OP_VEX (int, int); |
41f5efc6 | 90 | static void OP_VexR (int, int); |
e6123d0c | 91 | static void OP_VexW (int, int); |
43234a1e | 92 | static void OP_Rounding (int, int); |
c0f3af97 | 93 | static void OP_REG_VexI4 (int, int); |
93abb146 | 94 | static void OP_VexI4 (int, int); |
c0f3af97 | 95 | static void PCLMUL_Fixup (int, int); |
43234a1e | 96 | static void VPCMP_Fixup (int, int); |
be92cb14 | 97 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 98 | static void OP_0f07 (int, int); |
b844680a L |
99 | static void OP_Monitor (int, int); |
100 | static void OP_Mwait (int, int); | |
46e883c5 L |
101 | static void NOP_Fixup1 (int, int); |
102 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 103 | static void OP_3DNowSuffix (int, int); |
ad19981d | 104 | static void CMP_Fixup (int, int); |
26ca5450 | 105 | static void BadOp (void); |
35c52694 | 106 | static void REP_Fixup (int, int); |
d835a58b | 107 | static void SEP_Fixup (int, int); |
7e8b059b | 108 | static void BND_Fixup (int, int); |
04ef582a | 109 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
110 | static void HLE_Fixup1 (int, int); |
111 | static void HLE_Fixup2 (int, int); | |
112 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 113 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 114 | static void XMM_Fixup (int, int); |
eacc9c89 | 115 | static void FXSAVE_Fixup (int, int); |
c1e679ec | 116 | |
bc31405e | 117 | static void MOVSXD_Fixup (int, int); |
252b5132 | 118 | |
43234a1e L |
119 | static void OP_Mask (int, int); |
120 | ||
6608db57 | 121 | struct dis_private { |
252b5132 RH |
122 | /* Points to first byte not fetched. */ |
123 | bfd_byte *max_fetched; | |
0b1cf022 | 124 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 125 | bfd_vma insn_start; |
e396998b | 126 | int orig_sizeflag; |
8df14d78 | 127 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
128 | }; |
129 | ||
cb712a9e L |
130 | enum address_mode |
131 | { | |
132 | mode_16bit, | |
133 | mode_32bit, | |
134 | mode_64bit | |
135 | }; | |
136 | ||
137 | enum address_mode address_mode; | |
52b15da3 | 138 | |
5076851f ILT |
139 | /* Flags for the prefixes for the current instruction. See below. */ |
140 | static int prefixes; | |
141 | ||
52b15da3 JH |
142 | /* REX prefix the current instruction. See below. */ |
143 | static int rex; | |
144 | /* Bits of REX we've already used. */ | |
145 | static int rex_used; | |
52b15da3 JH |
146 | /* Mark parts used in the REX prefix. When we are testing for |
147 | empty prefix (for 8bit register REX extension), just mask it | |
148 | out. Otherwise test for REX bit is excuse for existence of REX | |
149 | only in case value is nonzero. */ | |
150 | #define USED_REX(value) \ | |
151 | { \ | |
152 | if (value) \ | |
161a04f6 L |
153 | { \ |
154 | if ((rex & value)) \ | |
155 | rex_used |= (value) | REX_OPCODE; \ | |
156 | } \ | |
52b15da3 | 157 | else \ |
161a04f6 | 158 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
159 | } |
160 | ||
7d421014 ILT |
161 | /* Flags for prefixes which we somehow handled when printing the |
162 | current instruction. */ | |
163 | static int used_prefixes; | |
164 | ||
5076851f ILT |
165 | /* Flags stored in PREFIXES. */ |
166 | #define PREFIX_REPZ 1 | |
167 | #define PREFIX_REPNZ 2 | |
168 | #define PREFIX_LOCK 4 | |
169 | #define PREFIX_CS 8 | |
170 | #define PREFIX_SS 0x10 | |
171 | #define PREFIX_DS 0x20 | |
172 | #define PREFIX_ES 0x40 | |
173 | #define PREFIX_FS 0x80 | |
174 | #define PREFIX_GS 0x100 | |
175 | #define PREFIX_DATA 0x200 | |
176 | #define PREFIX_ADDR 0x400 | |
177 | #define PREFIX_FWAIT 0x800 | |
178 | ||
252b5132 RH |
179 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
180 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
181 | on error. */ | |
182 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 183 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
184 | ? 1 : fetch_data ((info), (addr))) |
185 | ||
186 | static int | |
26ca5450 | 187 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
188 | { |
189 | int status; | |
6608db57 | 190 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
191 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
192 | ||
0b1cf022 | 193 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
194 | status = (*info->read_memory_func) (start, |
195 | priv->max_fetched, | |
196 | addr - priv->max_fetched, | |
197 | info); | |
198 | else | |
199 | status = -1; | |
252b5132 RH |
200 | if (status != 0) |
201 | { | |
7d421014 | 202 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
203 | print_insn_i386 will do something sensible. Otherwise, print |
204 | an error. We do that here because this is where we know | |
205 | STATUS. */ | |
7d421014 | 206 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 207 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 208 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
209 | } |
210 | else | |
211 | priv->max_fetched = addr; | |
212 | return 1; | |
213 | } | |
214 | ||
bf890a93 | 215 | /* Possible values for prefix requirement. */ |
507bd325 L |
216 | #define PREFIX_IGNORED_SHIFT 16 |
217 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
218 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
219 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
220 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
221 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
222 | ||
223 | /* Opcode prefixes. */ | |
224 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
225 | | PREFIX_REPNZ \ | |
226 | | PREFIX_DATA) | |
227 | ||
228 | /* Prefixes ignored. */ | |
229 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
230 | | PREFIX_IGNORED_REPNZ \ | |
231 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 232 | |
ce518a5f | 233 | #define XX { NULL, 0 } |
507bd325 | 234 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
235 | |
236 | #define Eb { OP_E, b_mode } | |
7e8b059b | 237 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 238 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 239 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 240 | #define Ev { OP_E, v_mode } |
de89d0a3 | 241 | #define Eva { OP_E, va_mode } |
7e8b059b | 242 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 243 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
244 | #define Ed { OP_E, d_mode } |
245 | #define Edq { OP_E, dq_mode } | |
246 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 247 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
248 | #define Edb { OP_E, db_mode } |
249 | #define Edw { OP_E, dw_mode } | |
42903f7f | 250 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 251 | #define Eq { OP_E, q_mode } |
07f5af7d | 252 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
253 | #define indirEp { OP_indirE, f_mode } |
254 | #define stackEv { OP_E, stack_v_mode } | |
255 | #define Em { OP_E, m_mode } | |
256 | #define Ew { OP_E, w_mode } | |
257 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 258 | #define Ma { OP_M, a_mode } |
b844680a | 259 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 260 | #define Md { OP_M, d_mode } |
f1f8f695 | 261 | #define Mo { OP_M, o_mode } |
ce518a5f L |
262 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
263 | #define Mq { OP_M, q_mode } | |
9ab00b61 | 264 | #define Mv { OP_M, v_mode } |
d276ec69 | 265 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 266 | #define Mx { OP_M, x_mode } |
c0f3af97 | 267 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 268 | #define Gb { OP_G, b_mode } |
7e8b059b | 269 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
270 | #define Gv { OP_G, v_mode } |
271 | #define Gd { OP_G, d_mode } | |
272 | #define Gdq { OP_G, dq_mode } | |
273 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 274 | #define Gva { OP_G, va_mode } |
ce518a5f | 275 | #define Gw { OP_G, w_mode } |
ce518a5f L |
276 | #define Ib { OP_I, b_mode } |
277 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 278 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 279 | #define Iv { OP_I, v_mode } |
7bb15c6f | 280 | #define sIv { OP_sI, v_mode } |
ce518a5f | 281 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 282 | #define Id { OP_I, d_mode } |
ce518a5f L |
283 | #define Iw { OP_I, w_mode } |
284 | #define I1 { OP_I, const_1_mode } | |
285 | #define Jb { OP_J, b_mode } | |
286 | #define Jv { OP_J, v_mode } | |
376cd056 | 287 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
288 | #define Cm { OP_C, m_mode } |
289 | #define Dm { OP_D, m_mode } | |
290 | #define Td { OP_T, d_mode } | |
b844680a | 291 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
292 | |
293 | #define RMeAX { OP_REG, eAX_reg } | |
294 | #define RMeBX { OP_REG, eBX_reg } | |
295 | #define RMeCX { OP_REG, eCX_reg } | |
296 | #define RMeDX { OP_REG, eDX_reg } | |
297 | #define RMeSP { OP_REG, eSP_reg } | |
298 | #define RMeBP { OP_REG, eBP_reg } | |
299 | #define RMeSI { OP_REG, eSI_reg } | |
300 | #define RMeDI { OP_REG, eDI_reg } | |
301 | #define RMrAX { OP_REG, rAX_reg } | |
302 | #define RMrBX { OP_REG, rBX_reg } | |
303 | #define RMrCX { OP_REG, rCX_reg } | |
304 | #define RMrDX { OP_REG, rDX_reg } | |
305 | #define RMrSP { OP_REG, rSP_reg } | |
306 | #define RMrBP { OP_REG, rBP_reg } | |
307 | #define RMrSI { OP_REG, rSI_reg } | |
308 | #define RMrDI { OP_REG, rDI_reg } | |
309 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
310 | #define RMCL { OP_REG, cl_reg } |
311 | #define RMDL { OP_REG, dl_reg } | |
312 | #define RMBL { OP_REG, bl_reg } | |
313 | #define RMAH { OP_REG, ah_reg } | |
314 | #define RMCH { OP_REG, ch_reg } | |
315 | #define RMDH { OP_REG, dh_reg } | |
316 | #define RMBH { OP_REG, bh_reg } | |
317 | #define RMAX { OP_REG, ax_reg } | |
318 | #define RMDX { OP_REG, dx_reg } | |
319 | ||
320 | #define eAX { OP_IMREG, eAX_reg } | |
ce518a5f L |
321 | #define AL { OP_IMREG, al_reg } |
322 | #define CL { OP_IMREG, cl_reg } | |
ce518a5f L |
323 | #define zAX { OP_IMREG, z_mode_ax_reg } |
324 | #define indirDX { OP_IMREG, indir_dx_reg } | |
325 | ||
326 | #define Sw { OP_SEG, w_mode } | |
327 | #define Sv { OP_SEG, v_mode } | |
328 | #define Ap { OP_DIR, 0 } | |
329 | #define Ob { OP_OFF64, b_mode } | |
330 | #define Ov { OP_OFF64, v_mode } | |
331 | #define Xb { OP_DSreg, eSI_reg } | |
332 | #define Xv { OP_DSreg, eSI_reg } | |
333 | #define Xz { OP_DSreg, eSI_reg } | |
334 | #define Yb { OP_ESreg, eDI_reg } | |
335 | #define Yv { OP_ESreg, eDI_reg } | |
336 | #define DSBX { OP_DSreg, eBX_reg } | |
337 | ||
338 | #define es { OP_REG, es_reg } | |
339 | #define ss { OP_REG, ss_reg } | |
340 | #define cs { OP_REG, cs_reg } | |
341 | #define ds { OP_REG, ds_reg } | |
342 | #define fs { OP_REG, fs_reg } | |
343 | #define gs { OP_REG, gs_reg } | |
344 | ||
345 | #define MX { OP_MMX, 0 } | |
346 | #define XM { OP_XMM, 0 } | |
539f890d | 347 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 348 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 349 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 350 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 351 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 352 | #define EM { OP_EM, v_mode } |
b6169b20 | 353 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 354 | #define EMd { OP_EM, d_mode } |
14051056 | 355 | #define EMx { OP_EM, x_mode } |
4726e9a4 | 356 | #define EXbwUnit { OP_EX, bw_unit_mode } |
8976381e | 357 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 358 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 359 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 360 | #define EXq { OP_EX, q_mode } |
b6169b20 | 361 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 362 | #define EXx { OP_EX, x_mode } |
b6169b20 | 363 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 364 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 365 | #define EXymm { OP_EX, ymm_mode } |
260cd341 | 366 | #define EXtmm { OP_EX, tmm_mode } |
c0f3af97 | 367 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 368 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
369 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
370 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
371 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
372 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
373 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
374 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 375 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 376 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
377 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
378 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
379 | #define MS { OP_MS, v_mode } |
380 | #define XS { OP_XS, v_mode } | |
09335d05 | 381 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 382 | #define MXC { OP_MXC, 0 } |
ce518a5f | 383 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 384 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 385 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 386 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 387 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 388 | |
c0f3af97 | 389 | #define Vex { OP_VEX, vex_mode } |
e6123d0c | 390 | #define VexW { OP_VexW, vex_mode } |
539f890d | 391 | #define VexScalar { OP_VEX, vex_scalar_mode } |
41f5efc6 | 392 | #define VexScalarR { OP_VexR, vex_scalar_mode } |
6c30d220 | 393 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
cb21baef | 394 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 395 | #define VexTmm { OP_VEX, tmm_mode } |
c0f3af97 | 396 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 397 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 398 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 399 | #define PCLMUL { PCLMUL_Fixup, 0 } |
43234a1e | 400 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 401 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
402 | |
403 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 404 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
405 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
406 | ||
407 | #define XMask { OP_Mask, mask_mode } | |
408 | #define MaskG { OP_G, mask_mode } | |
409 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 410 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e | 411 | #define MaskVex { OP_VEX, mask_mode } |
c0f3af97 | 412 | |
6c30d220 | 413 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 414 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 415 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 416 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 417 | |
260cd341 LC |
418 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
419 | ||
35c52694 | 420 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
421 | #define Xbr { REP_Fixup, eSI_reg } |
422 | #define Xvr { REP_Fixup, eSI_reg } | |
423 | #define Ybr { REP_Fixup, eDI_reg } | |
424 | #define Yvr { REP_Fixup, eDI_reg } | |
425 | #define Yzr { REP_Fixup, eDI_reg } | |
426 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
427 | #define ALr { REP_Fixup, al_reg } | |
428 | #define eAXr { REP_Fixup, eAX_reg } | |
429 | ||
42164a71 L |
430 | /* Used handle HLE prefix for lockable instructions. */ |
431 | #define Ebh1 { HLE_Fixup1, b_mode } | |
432 | #define Evh1 { HLE_Fixup1, v_mode } | |
433 | #define Ebh2 { HLE_Fixup2, b_mode } | |
434 | #define Evh2 { HLE_Fixup2, v_mode } | |
435 | #define Ebh3 { HLE_Fixup3, b_mode } | |
436 | #define Evh3 { HLE_Fixup3, v_mode } | |
437 | ||
7e8b059b | 438 | #define BND { BND_Fixup, 0 } |
04ef582a | 439 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 440 | |
ce518a5f L |
441 | #define cond_jump_flag { NULL, cond_jump_mode } |
442 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 443 | |
252b5132 | 444 | /* bits in sizeflag */ |
252b5132 | 445 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
446 | #define AFLAG 2 |
447 | #define DFLAG 1 | |
448 | ||
51e7da1b L |
449 | enum |
450 | { | |
451 | /* byte operand */ | |
452 | b_mode = 1, | |
453 | /* byte operand with operand swapped */ | |
3873ba12 | 454 | b_swap_mode, |
e3949f17 L |
455 | /* byte operand, sign extend like 'T' suffix */ |
456 | b_T_mode, | |
51e7da1b | 457 | /* operand size depends on prefixes */ |
3873ba12 | 458 | v_mode, |
51e7da1b | 459 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 460 | v_swap_mode, |
de89d0a3 IT |
461 | /* operand size depends on address prefix */ |
462 | va_mode, | |
51e7da1b | 463 | /* word operand */ |
3873ba12 | 464 | w_mode, |
51e7da1b | 465 | /* double word operand */ |
3873ba12 | 466 | d_mode, |
51e7da1b | 467 | /* double word operand with operand swapped */ |
3873ba12 | 468 | d_swap_mode, |
51e7da1b | 469 | /* quad word operand */ |
3873ba12 | 470 | q_mode, |
51e7da1b | 471 | /* quad word operand with operand swapped */ |
3873ba12 | 472 | q_swap_mode, |
51e7da1b | 473 | /* ten-byte operand */ |
3873ba12 | 474 | t_mode, |
43234a1e L |
475 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
476 | broadcast enabled. */ | |
3873ba12 | 477 | x_mode, |
43234a1e L |
478 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
479 | evex_x_gscat_mode, | |
4726e9a4 JB |
480 | /* Similar to x_mode, but with yet different EVEX mem shifts. */ |
481 | bw_unit_mode, | |
43234a1e L |
482 | /* Similar to x_mode, but with disabled broadcast. */ |
483 | evex_x_nobcst_mode, | |
484 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
485 | in EVEX. */ | |
3873ba12 | 486 | x_swap_mode, |
51e7da1b | 487 | /* 16-byte XMM operand */ |
3873ba12 | 488 | xmm_mode, |
43234a1e L |
489 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
490 | memory operand (depending on vector length). Broadcast isn't | |
491 | allowed. */ | |
3873ba12 | 492 | xmmq_mode, |
43234a1e L |
493 | /* Same as xmmq_mode, but broadcast is allowed. */ |
494 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
495 | /* XMM register or byte memory operand */ |
496 | xmm_mb_mode, | |
497 | /* XMM register or word memory operand */ | |
498 | xmm_mw_mode, | |
499 | /* XMM register or double word memory operand */ | |
500 | xmm_md_mode, | |
501 | /* XMM register or quad word memory operand */ | |
502 | xmm_mq_mode, | |
43234a1e | 503 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 504 | xmmdw_mode, |
43234a1e | 505 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 506 | xmmqd_mode, |
43234a1e L |
507 | /* 32-byte YMM operand */ |
508 | ymm_mode, | |
509 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 510 | ymmq_mode, |
6c30d220 L |
511 | /* 32-byte YMM or 16-byte word operand */ |
512 | ymmxmm_mode, | |
260cd341 LC |
513 | /* TMM operand */ |
514 | tmm_mode, | |
51e7da1b | 515 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 516 | m_mode, |
51e7da1b | 517 | /* pair of v_mode operands */ |
3873ba12 L |
518 | a_mode, |
519 | cond_jump_mode, | |
520 | loop_jcxz_mode, | |
bc31405e | 521 | movsxd_mode, |
7e8b059b | 522 | v_bnd_mode, |
d276ec69 JB |
523 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
524 | v_bndmk_mode, | |
51e7da1b | 525 | /* operand size depends on REX prefixes. */ |
3873ba12 | 526 | dq_mode, |
376cd056 JB |
527 | /* registers like dq_mode, memory like w_mode, displacements like |
528 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 529 | dqw_mode, |
9f79e886 | 530 | /* bounds operand */ |
7e8b059b | 531 | bnd_mode, |
9f79e886 JB |
532 | /* bounds operand with operand swapped */ |
533 | bnd_swap_mode, | |
51e7da1b | 534 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
535 | f_mode, |
536 | const_1_mode, | |
07f5af7d L |
537 | /* v_mode for indirect branch opcodes. */ |
538 | indir_v_mode, | |
51e7da1b | 539 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 540 | stack_v_mode, |
51e7da1b | 541 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 542 | z_mode, |
51e7da1b | 543 | /* 16-byte operand */ |
3873ba12 | 544 | o_mode, |
51e7da1b | 545 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 546 | dqb_mode, |
1ba585e8 IT |
547 | /* registers like d_mode, memory like b_mode. */ |
548 | db_mode, | |
549 | /* registers like d_mode, memory like w_mode. */ | |
550 | dw_mode, | |
51e7da1b | 551 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 552 | dqd_mode, |
51e7da1b | 553 | /* normal vex mode */ |
3873ba12 | 554 | vex_mode, |
d55ee72f | 555 | |
825bd36c | 556 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 557 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
558 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
559 | vex_vsib_d_w_d_mode, | |
825bd36c | 560 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 561 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
562 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
563 | vex_vsib_q_w_d_mode, | |
260cd341 LC |
564 | /* mandatory non-vector SIB. */ |
565 | vex_sibmem_mode, | |
6c30d220 | 566 | |
539f890d L |
567 | /* scalar, ignore vector length. */ |
568 | scalar_mode, | |
539f890d L |
569 | /* like vex_mode, ignore vector length. */ |
570 | vex_scalar_mode, | |
825bd36c | 571 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 572 | vex_scalar_w_dq_mode, |
539f890d | 573 | |
43234a1e L |
574 | /* Static rounding. */ |
575 | evex_rounding_mode, | |
70df6fc9 L |
576 | /* Static rounding, 64-bit mode only. */ |
577 | evex_rounding_64_mode, | |
43234a1e L |
578 | /* Supress all exceptions. */ |
579 | evex_sae_mode, | |
580 | ||
581 | /* Mask register operand. */ | |
582 | mask_mode, | |
1ba585e8 IT |
583 | /* Mask register operand. */ |
584 | mask_bd_mode, | |
43234a1e | 585 | |
3873ba12 L |
586 | es_reg, |
587 | cs_reg, | |
588 | ss_reg, | |
589 | ds_reg, | |
590 | fs_reg, | |
591 | gs_reg, | |
d55ee72f | 592 | |
3873ba12 L |
593 | eAX_reg, |
594 | eCX_reg, | |
595 | eDX_reg, | |
596 | eBX_reg, | |
597 | eSP_reg, | |
598 | eBP_reg, | |
599 | eSI_reg, | |
600 | eDI_reg, | |
d55ee72f | 601 | |
3873ba12 L |
602 | al_reg, |
603 | cl_reg, | |
604 | dl_reg, | |
605 | bl_reg, | |
606 | ah_reg, | |
607 | ch_reg, | |
608 | dh_reg, | |
609 | bh_reg, | |
d55ee72f | 610 | |
3873ba12 L |
611 | ax_reg, |
612 | cx_reg, | |
613 | dx_reg, | |
614 | bx_reg, | |
615 | sp_reg, | |
616 | bp_reg, | |
617 | si_reg, | |
618 | di_reg, | |
d55ee72f | 619 | |
3873ba12 L |
620 | rAX_reg, |
621 | rCX_reg, | |
622 | rDX_reg, | |
623 | rBX_reg, | |
624 | rSP_reg, | |
625 | rBP_reg, | |
626 | rSI_reg, | |
627 | rDI_reg, | |
d55ee72f | 628 | |
3873ba12 L |
629 | z_mode_ax_reg, |
630 | indir_dx_reg | |
51e7da1b | 631 | }; |
252b5132 | 632 | |
51e7da1b L |
633 | enum |
634 | { | |
635 | FLOATCODE = 1, | |
3873ba12 L |
636 | USE_REG_TABLE, |
637 | USE_MOD_TABLE, | |
638 | USE_RM_TABLE, | |
639 | USE_PREFIX_TABLE, | |
640 | USE_X86_64_TABLE, | |
641 | USE_3BYTE_TABLE, | |
f88c9eb0 | 642 | USE_XOP_8F_TABLE, |
3873ba12 L |
643 | USE_VEX_C4_TABLE, |
644 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 645 | USE_VEX_LEN_TABLE, |
43234a1e | 646 | USE_VEX_W_TABLE, |
04e2a182 L |
647 | USE_EVEX_TABLE, |
648 | USE_EVEX_LEN_TABLE | |
51e7da1b | 649 | }; |
6439fc28 | 650 | |
bf890a93 | 651 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 652 | |
bf890a93 IT |
653 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
654 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
655 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
656 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
657 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
658 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
659 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
660 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 661 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 662 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
663 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
664 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
665 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 666 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 667 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 668 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 669 | |
51e7da1b L |
670 | enum |
671 | { | |
672 | REG_80 = 0, | |
3873ba12 | 673 | REG_81, |
7148c369 | 674 | REG_83, |
3873ba12 L |
675 | REG_8F, |
676 | REG_C0, | |
677 | REG_C1, | |
678 | REG_C6, | |
679 | REG_C7, | |
680 | REG_D0, | |
681 | REG_D1, | |
682 | REG_D2, | |
683 | REG_D3, | |
684 | REG_F6, | |
685 | REG_F7, | |
686 | REG_FE, | |
687 | REG_FF, | |
688 | REG_0F00, | |
689 | REG_0F01, | |
690 | REG_0F0D, | |
691 | REG_0F18, | |
f8687e93 JB |
692 | REG_0F1C_P_0_MOD_0, |
693 | REG_0F1E_P_1_MOD_3, | |
c4694f17 | 694 | REG_0F38D8_PREFIX_1, |
c1fa250a | 695 | REG_0F3A0F_PREFIX_1_MOD_3, |
3873ba12 L |
696 | REG_0F71, |
697 | REG_0F72, | |
698 | REG_0F73, | |
699 | REG_0FA6, | |
700 | REG_0FA7, | |
701 | REG_0FAE, | |
702 | REG_0FBA, | |
703 | REG_0FC7, | |
592a252b L |
704 | REG_VEX_0F71, |
705 | REG_VEX_0F72, | |
706 | REG_VEX_0F73, | |
707 | REG_VEX_0FAE, | |
260cd341 | 708 | REG_VEX_0F3849_X86_64_P_0_W_0_M_1, |
f12dc422 | 709 | REG_VEX_0F38F3, |
467bbef0 JB |
710 | |
711 | REG_0FXOP_09_01_L_0, | |
712 | REG_0FXOP_09_02_L_0, | |
713 | REG_0FXOP_09_12_M_1_L_0, | |
714 | REG_0FXOP_0A_12_L_0, | |
43234a1e | 715 | |
1ba585e8 | 716 | REG_EVEX_0F71, |
43234a1e L |
717 | REG_EVEX_0F72, |
718 | REG_EVEX_0F73, | |
719 | REG_EVEX_0F38C6, | |
720 | REG_EVEX_0F38C7 | |
51e7da1b | 721 | }; |
1ceb70f8 | 722 | |
51e7da1b L |
723 | enum |
724 | { | |
725 | MOD_8D = 0, | |
42164a71 L |
726 | MOD_C6_REG_7, |
727 | MOD_C7_REG_7, | |
4a357820 MZ |
728 | MOD_FF_REG_3, |
729 | MOD_FF_REG_5, | |
3873ba12 L |
730 | MOD_0F01_REG_0, |
731 | MOD_0F01_REG_1, | |
732 | MOD_0F01_REG_2, | |
733 | MOD_0F01_REG_3, | |
8eab4136 | 734 | MOD_0F01_REG_5, |
3873ba12 L |
735 | MOD_0F01_REG_7, |
736 | MOD_0F12_PREFIX_0, | |
18897deb | 737 | MOD_0F12_PREFIX_2, |
3873ba12 L |
738 | MOD_0F13, |
739 | MOD_0F16_PREFIX_0, | |
18897deb | 740 | MOD_0F16_PREFIX_2, |
3873ba12 L |
741 | MOD_0F17, |
742 | MOD_0F18_REG_0, | |
743 | MOD_0F18_REG_1, | |
744 | MOD_0F18_REG_2, | |
745 | MOD_0F18_REG_3, | |
d7189fa5 RM |
746 | MOD_0F18_REG_4, |
747 | MOD_0F18_REG_5, | |
748 | MOD_0F18_REG_6, | |
749 | MOD_0F18_REG_7, | |
7e8b059b L |
750 | MOD_0F1A_PREFIX_0, |
751 | MOD_0F1B_PREFIX_0, | |
752 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 753 | MOD_0F1C_PREFIX_0, |
603555e5 | 754 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
755 | MOD_0F2B_PREFIX_0, |
756 | MOD_0F2B_PREFIX_1, | |
757 | MOD_0F2B_PREFIX_2, | |
758 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 759 | MOD_0F50, |
3873ba12 L |
760 | MOD_0F71_REG_2, |
761 | MOD_0F71_REG_4, | |
762 | MOD_0F71_REG_6, | |
763 | MOD_0F72_REG_2, | |
764 | MOD_0F72_REG_4, | |
765 | MOD_0F72_REG_6, | |
766 | MOD_0F73_REG_2, | |
767 | MOD_0F73_REG_3, | |
768 | MOD_0F73_REG_6, | |
769 | MOD_0F73_REG_7, | |
770 | MOD_0FAE_REG_0, | |
771 | MOD_0FAE_REG_1, | |
772 | MOD_0FAE_REG_2, | |
773 | MOD_0FAE_REG_3, | |
774 | MOD_0FAE_REG_4, | |
775 | MOD_0FAE_REG_5, | |
776 | MOD_0FAE_REG_6, | |
777 | MOD_0FAE_REG_7, | |
778 | MOD_0FB2, | |
779 | MOD_0FB4, | |
780 | MOD_0FB5, | |
a8484f96 | 781 | MOD_0FC3, |
963f3586 IT |
782 | MOD_0FC7_REG_3, |
783 | MOD_0FC7_REG_4, | |
784 | MOD_0FC7_REG_5, | |
3873ba12 L |
785 | MOD_0FC7_REG_6, |
786 | MOD_0FC7_REG_7, | |
787 | MOD_0FD7, | |
788 | MOD_0FE7_PREFIX_2, | |
789 | MOD_0FF0_PREFIX_3, | |
7531c613 | 790 | MOD_0F382A, |
c4694f17 TG |
791 | MOD_0F38DC_PREFIX_1, |
792 | MOD_0F38DD_PREFIX_1, | |
793 | MOD_0F38DE_PREFIX_1, | |
794 | MOD_0F38DF_PREFIX_1, | |
7531c613 | 795 | MOD_0F38F5, |
603555e5 | 796 | MOD_0F38F6_PREFIX_0, |
5d79adc4 | 797 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 798 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 799 | MOD_0F38F8_PREFIX_3, |
035e7389 | 800 | MOD_0F38F9, |
c4694f17 TG |
801 | MOD_0F38FA_PREFIX_1, |
802 | MOD_0F38FB_PREFIX_1, | |
c1fa250a | 803 | MOD_0F3A0F_PREFIX_1, |
3873ba12 L |
804 | MOD_62_32BIT, |
805 | MOD_C4_32BIT, | |
806 | MOD_C5_32BIT, | |
592a252b | 807 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 808 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
809 | MOD_VEX_0F13, |
810 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 811 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
812 | MOD_VEX_0F17, |
813 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
814 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
815 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
816 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
817 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
818 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
819 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
820 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
821 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
822 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
823 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
824 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
825 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
826 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
827 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
828 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
829 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
830 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
831 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
832 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
833 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
834 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
835 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
836 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
837 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
838 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
839 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
840 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
841 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
842 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
843 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
844 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
845 | MOD_VEX_0F50, |
846 | MOD_VEX_0F71_REG_2, | |
847 | MOD_VEX_0F71_REG_4, | |
848 | MOD_VEX_0F71_REG_6, | |
849 | MOD_VEX_0F72_REG_2, | |
850 | MOD_VEX_0F72_REG_4, | |
851 | MOD_VEX_0F72_REG_6, | |
852 | MOD_VEX_0F73_REG_2, | |
853 | MOD_VEX_0F73_REG_3, | |
854 | MOD_VEX_0F73_REG_6, | |
855 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
856 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
857 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
858 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
859 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
860 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
861 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 862 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
863 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
864 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 865 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
866 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
867 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
868 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
869 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
870 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
871 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
872 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
873 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
874 | MOD_VEX_0FAE_REG_2, |
875 | MOD_VEX_0FAE_REG_3, | |
7531c613 JB |
876 | MOD_VEX_0FD7, |
877 | MOD_VEX_0FE7, | |
592a252b | 878 | MOD_VEX_0FF0_PREFIX_3, |
7531c613 JB |
879 | MOD_VEX_0F381A, |
880 | MOD_VEX_0F382A, | |
881 | MOD_VEX_0F382C, | |
882 | MOD_VEX_0F382D, | |
883 | MOD_VEX_0F382E, | |
884 | MOD_VEX_0F382F, | |
09d73035 CL |
885 | MOD_VEX_0F3849_X86_64_P_0_W_0, |
886 | MOD_VEX_0F3849_X86_64_P_2_W_0, | |
887 | MOD_VEX_0F3849_X86_64_P_3_W_0, | |
888 | MOD_VEX_0F384B_X86_64_P_1_W_0, | |
889 | MOD_VEX_0F384B_X86_64_P_2_W_0, | |
890 | MOD_VEX_0F384B_X86_64_P_3_W_0, | |
7531c613 | 891 | MOD_VEX_0F385A, |
09d73035 CL |
892 | MOD_VEX_0F385C_X86_64_P_1_W_0, |
893 | MOD_VEX_0F385E_X86_64_P_0_W_0, | |
894 | MOD_VEX_0F385E_X86_64_P_1_W_0, | |
895 | MOD_VEX_0F385E_X86_64_P_2_W_0, | |
896 | MOD_VEX_0F385E_X86_64_P_3_W_0, | |
7531c613 JB |
897 | MOD_VEX_0F388C, |
898 | MOD_VEX_0F388E, | |
bb5b3501 JB |
899 | MOD_VEX_0F3A30_L_0, |
900 | MOD_VEX_0F3A31_L_0, | |
901 | MOD_VEX_0F3A32_L_0, | |
902 | MOD_VEX_0F3A33_L_0, | |
43234a1e | 903 | |
467bbef0 JB |
904 | MOD_VEX_0FXOP_09_12, |
905 | ||
43234a1e | 906 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
907 | MOD_EVEX_0F12_PREFIX_2, |
908 | MOD_EVEX_0F13, | |
43234a1e | 909 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
910 | MOD_EVEX_0F16_PREFIX_2, |
911 | MOD_EVEX_0F17, | |
912 | MOD_EVEX_0F2B, | |
7531c613 JB |
913 | MOD_EVEX_0F381A_W_0, |
914 | MOD_EVEX_0F381A_W_1, | |
915 | MOD_EVEX_0F381B_W_0, | |
916 | MOD_EVEX_0F381B_W_1, | |
464d2b65 JB |
917 | MOD_EVEX_0F3828_P_1, |
918 | MOD_EVEX_0F382A_P_1_W_1, | |
919 | MOD_EVEX_0F3838_P_1, | |
920 | MOD_EVEX_0F383A_P_1_W_0, | |
7531c613 JB |
921 | MOD_EVEX_0F385A_W_0, |
922 | MOD_EVEX_0F385A_W_1, | |
923 | MOD_EVEX_0F385B_W_0, | |
924 | MOD_EVEX_0F385B_W_1, | |
464d2b65 JB |
925 | MOD_EVEX_0F387A_W_0, |
926 | MOD_EVEX_0F387B_W_0, | |
927 | MOD_EVEX_0F387C, | |
43234a1e L |
928 | MOD_EVEX_0F38C6_REG_1, |
929 | MOD_EVEX_0F38C6_REG_2, | |
930 | MOD_EVEX_0F38C6_REG_5, | |
931 | MOD_EVEX_0F38C6_REG_6, | |
932 | MOD_EVEX_0F38C7_REG_1, | |
933 | MOD_EVEX_0F38C7_REG_2, | |
934 | MOD_EVEX_0F38C7_REG_5, | |
935 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 936 | }; |
1ceb70f8 | 937 | |
51e7da1b L |
938 | enum |
939 | { | |
42164a71 L |
940 | RM_C6_REG_7 = 0, |
941 | RM_C7_REG_7, | |
942 | RM_0F01_REG_0, | |
3873ba12 L |
943 | RM_0F01_REG_1, |
944 | RM_0F01_REG_2, | |
945 | RM_0F01_REG_3, | |
f8687e93 JB |
946 | RM_0F01_REG_5_MOD_3, |
947 | RM_0F01_REG_7_MOD_3, | |
948 | RM_0F1E_P_1_MOD_3_REG_7, | |
c1fa250a | 949 | RM_0F3A0F_P_1_MOD_3_REG_0, |
f8687e93 JB |
950 | RM_0FAE_REG_6_MOD_3_P_0, |
951 | RM_0FAE_REG_7_MOD_3, | |
260cd341 | 952 | RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 |
51e7da1b | 953 | }; |
1ceb70f8 | 954 | |
51e7da1b L |
955 | enum |
956 | { | |
957 | PREFIX_90 = 0, | |
81d54bb7 CL |
958 | PREFIX_0F01_REG_1_RM_4, |
959 | PREFIX_0F01_REG_1_RM_5, | |
960 | PREFIX_0F01_REG_1_RM_6, | |
961 | PREFIX_0F01_REG_1_RM_7, | |
a847e322 | 962 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
963 | PREFIX_0F01_REG_5_MOD_0, |
964 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 965 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 966 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
f64c42a9 LC |
967 | PREFIX_0F01_REG_5_MOD_3_RM_4, |
968 | PREFIX_0F01_REG_5_MOD_3_RM_5, | |
969 | PREFIX_0F01_REG_5_MOD_3_RM_6, | |
970 | PREFIX_0F01_REG_5_MOD_3_RM_7, | |
267b8516 | 971 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
3233d7d0 | 972 | PREFIX_0F09, |
3873ba12 L |
973 | PREFIX_0F10, |
974 | PREFIX_0F11, | |
975 | PREFIX_0F12, | |
976 | PREFIX_0F16, | |
7e8b059b L |
977 | PREFIX_0F1A, |
978 | PREFIX_0F1B, | |
c48935d7 | 979 | PREFIX_0F1C, |
603555e5 | 980 | PREFIX_0F1E, |
3873ba12 L |
981 | PREFIX_0F2A, |
982 | PREFIX_0F2B, | |
983 | PREFIX_0F2C, | |
984 | PREFIX_0F2D, | |
985 | PREFIX_0F2E, | |
986 | PREFIX_0F2F, | |
987 | PREFIX_0F51, | |
988 | PREFIX_0F52, | |
989 | PREFIX_0F53, | |
990 | PREFIX_0F58, | |
991 | PREFIX_0F59, | |
992 | PREFIX_0F5A, | |
993 | PREFIX_0F5B, | |
994 | PREFIX_0F5C, | |
995 | PREFIX_0F5D, | |
996 | PREFIX_0F5E, | |
997 | PREFIX_0F5F, | |
998 | PREFIX_0F60, | |
999 | PREFIX_0F61, | |
1000 | PREFIX_0F62, | |
3873ba12 L |
1001 | PREFIX_0F6F, |
1002 | PREFIX_0F70, | |
3873ba12 L |
1003 | PREFIX_0F78, |
1004 | PREFIX_0F79, | |
1005 | PREFIX_0F7C, | |
1006 | PREFIX_0F7D, | |
1007 | PREFIX_0F7E, | |
1008 | PREFIX_0F7F, | |
f8687e93 JB |
1009 | PREFIX_0FAE_REG_0_MOD_3, |
1010 | PREFIX_0FAE_REG_1_MOD_3, | |
1011 | PREFIX_0FAE_REG_2_MOD_3, | |
1012 | PREFIX_0FAE_REG_3_MOD_3, | |
1013 | PREFIX_0FAE_REG_4_MOD_0, | |
1014 | PREFIX_0FAE_REG_4_MOD_3, | |
f8687e93 JB |
1015 | PREFIX_0FAE_REG_5_MOD_3, |
1016 | PREFIX_0FAE_REG_6_MOD_0, | |
1017 | PREFIX_0FAE_REG_6_MOD_3, | |
1018 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1019 | PREFIX_0FB8, |
f12dc422 | 1020 | PREFIX_0FBC, |
3873ba12 L |
1021 | PREFIX_0FBD, |
1022 | PREFIX_0FC2, | |
f8687e93 JB |
1023 | PREFIX_0FC7_REG_6_MOD_0, |
1024 | PREFIX_0FC7_REG_6_MOD_3, | |
1025 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1026 | PREFIX_0FD0, |
1027 | PREFIX_0FD6, | |
1028 | PREFIX_0FE6, | |
1029 | PREFIX_0FE7, | |
1030 | PREFIX_0FF0, | |
1031 | PREFIX_0FF7, | |
c4694f17 TG |
1032 | PREFIX_0F38D8, |
1033 | PREFIX_0F38DC, | |
1034 | PREFIX_0F38DD, | |
1035 | PREFIX_0F38DE, | |
1036 | PREFIX_0F38DF, | |
3873ba12 L |
1037 | PREFIX_0F38F0, |
1038 | PREFIX_0F38F1, | |
e2e1fcde | 1039 | PREFIX_0F38F6, |
c0a30a9f | 1040 | PREFIX_0F38F8, |
c4694f17 TG |
1041 | PREFIX_0F38FA, |
1042 | PREFIX_0F38FB, | |
c1fa250a | 1043 | PREFIX_0F3A0F, |
592a252b L |
1044 | PREFIX_VEX_0F10, |
1045 | PREFIX_VEX_0F11, | |
1046 | PREFIX_VEX_0F12, | |
1047 | PREFIX_VEX_0F16, | |
1048 | PREFIX_VEX_0F2A, | |
1049 | PREFIX_VEX_0F2C, | |
1050 | PREFIX_VEX_0F2D, | |
1051 | PREFIX_VEX_0F2E, | |
1052 | PREFIX_VEX_0F2F, | |
43234a1e L |
1053 | PREFIX_VEX_0F41, |
1054 | PREFIX_VEX_0F42, | |
1055 | PREFIX_VEX_0F44, | |
1056 | PREFIX_VEX_0F45, | |
1057 | PREFIX_VEX_0F46, | |
1058 | PREFIX_VEX_0F47, | |
1ba585e8 | 1059 | PREFIX_VEX_0F4A, |
43234a1e | 1060 | PREFIX_VEX_0F4B, |
592a252b L |
1061 | PREFIX_VEX_0F51, |
1062 | PREFIX_VEX_0F52, | |
1063 | PREFIX_VEX_0F53, | |
1064 | PREFIX_VEX_0F58, | |
1065 | PREFIX_VEX_0F59, | |
1066 | PREFIX_VEX_0F5A, | |
1067 | PREFIX_VEX_0F5B, | |
1068 | PREFIX_VEX_0F5C, | |
1069 | PREFIX_VEX_0F5D, | |
1070 | PREFIX_VEX_0F5E, | |
1071 | PREFIX_VEX_0F5F, | |
592a252b L |
1072 | PREFIX_VEX_0F6F, |
1073 | PREFIX_VEX_0F70, | |
592a252b L |
1074 | PREFIX_VEX_0F7C, |
1075 | PREFIX_VEX_0F7D, | |
1076 | PREFIX_VEX_0F7E, | |
1077 | PREFIX_VEX_0F7F, | |
43234a1e L |
1078 | PREFIX_VEX_0F90, |
1079 | PREFIX_VEX_0F91, | |
1080 | PREFIX_VEX_0F92, | |
1081 | PREFIX_VEX_0F93, | |
1082 | PREFIX_VEX_0F98, | |
1ba585e8 | 1083 | PREFIX_VEX_0F99, |
592a252b | 1084 | PREFIX_VEX_0FC2, |
592a252b | 1085 | PREFIX_VEX_0FD0, |
592a252b | 1086 | PREFIX_VEX_0FE6, |
592a252b | 1087 | PREFIX_VEX_0FF0, |
260cd341 LC |
1088 | PREFIX_VEX_0F3849_X86_64, |
1089 | PREFIX_VEX_0F384B_X86_64, | |
260cd341 LC |
1090 | PREFIX_VEX_0F385C_X86_64, |
1091 | PREFIX_VEX_0F385E_X86_64, | |
6c30d220 L |
1092 | PREFIX_VEX_0F38F5, |
1093 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1094 | PREFIX_VEX_0F38F7, |
43234a1e L |
1095 | PREFIX_VEX_0F3AF0, |
1096 | ||
1097 | PREFIX_EVEX_0F10, | |
1098 | PREFIX_EVEX_0F11, | |
1099 | PREFIX_EVEX_0F12, | |
43234a1e | 1100 | PREFIX_EVEX_0F16, |
43234a1e | 1101 | PREFIX_EVEX_0F2A, |
43234a1e L |
1102 | PREFIX_EVEX_0F51, |
1103 | PREFIX_EVEX_0F58, | |
1104 | PREFIX_EVEX_0F59, | |
1105 | PREFIX_EVEX_0F5A, | |
1106 | PREFIX_EVEX_0F5B, | |
1107 | PREFIX_EVEX_0F5C, | |
1108 | PREFIX_EVEX_0F5D, | |
1109 | PREFIX_EVEX_0F5E, | |
1110 | PREFIX_EVEX_0F5F, | |
43234a1e L |
1111 | PREFIX_EVEX_0F6F, |
1112 | PREFIX_EVEX_0F70, | |
43234a1e L |
1113 | PREFIX_EVEX_0F78, |
1114 | PREFIX_EVEX_0F79, | |
1115 | PREFIX_EVEX_0F7A, | |
1116 | PREFIX_EVEX_0F7B, | |
1117 | PREFIX_EVEX_0F7E, | |
1118 | PREFIX_EVEX_0F7F, | |
1119 | PREFIX_EVEX_0FC2, | |
43234a1e | 1120 | PREFIX_EVEX_0FE6, |
1ba585e8 | 1121 | PREFIX_EVEX_0F3810, |
43234a1e L |
1122 | PREFIX_EVEX_0F3811, |
1123 | PREFIX_EVEX_0F3812, | |
1124 | PREFIX_EVEX_0F3813, | |
1125 | PREFIX_EVEX_0F3814, | |
1126 | PREFIX_EVEX_0F3815, | |
1ba585e8 | 1127 | PREFIX_EVEX_0F3820, |
43234a1e L |
1128 | PREFIX_EVEX_0F3821, |
1129 | PREFIX_EVEX_0F3822, | |
1130 | PREFIX_EVEX_0F3823, | |
1131 | PREFIX_EVEX_0F3824, | |
1132 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1133 | PREFIX_EVEX_0F3826, |
43234a1e L |
1134 | PREFIX_EVEX_0F3827, |
1135 | PREFIX_EVEX_0F3828, | |
1136 | PREFIX_EVEX_0F3829, | |
1137 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1138 | PREFIX_EVEX_0F3830, |
43234a1e L |
1139 | PREFIX_EVEX_0F3831, |
1140 | PREFIX_EVEX_0F3832, | |
1141 | PREFIX_EVEX_0F3833, | |
1142 | PREFIX_EVEX_0F3834, | |
1143 | PREFIX_EVEX_0F3835, | |
1ba585e8 | 1144 | PREFIX_EVEX_0F3838, |
43234a1e L |
1145 | PREFIX_EVEX_0F3839, |
1146 | PREFIX_EVEX_0F383A, | |
47acf0bd IT |
1147 | PREFIX_EVEX_0F3852, |
1148 | PREFIX_EVEX_0F3853, | |
9186c494 | 1149 | PREFIX_EVEX_0F3868, |
53467f57 | 1150 | PREFIX_EVEX_0F3872, |
43234a1e L |
1151 | PREFIX_EVEX_0F389A, |
1152 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1153 | PREFIX_EVEX_0F38AA, |
1154 | PREFIX_EVEX_0F38AB, | |
51e7da1b | 1155 | }; |
4e7d34a6 | 1156 | |
51e7da1b L |
1157 | enum |
1158 | { | |
1159 | X86_64_06 = 0, | |
3873ba12 | 1160 | X86_64_07, |
1673df32 | 1161 | X86_64_0E, |
3873ba12 L |
1162 | X86_64_16, |
1163 | X86_64_17, | |
1164 | X86_64_1E, | |
1165 | X86_64_1F, | |
1166 | X86_64_27, | |
1167 | X86_64_2F, | |
1168 | X86_64_37, | |
1169 | X86_64_3F, | |
1170 | X86_64_60, | |
1171 | X86_64_61, | |
1172 | X86_64_62, | |
1173 | X86_64_63, | |
1174 | X86_64_6D, | |
1175 | X86_64_6F, | |
d039fef3 | 1176 | X86_64_82, |
3873ba12 | 1177 | X86_64_9A, |
aeab2b26 JB |
1178 | X86_64_C2, |
1179 | X86_64_C3, | |
3873ba12 L |
1180 | X86_64_C4, |
1181 | X86_64_C5, | |
1182 | X86_64_CE, | |
1183 | X86_64_D4, | |
1184 | X86_64_D5, | |
a72d2af2 L |
1185 | X86_64_E8, |
1186 | X86_64_E9, | |
3873ba12 L |
1187 | X86_64_EA, |
1188 | X86_64_0F01_REG_0, | |
1189 | X86_64_0F01_REG_1, | |
81d54bb7 CL |
1190 | X86_64_0F01_REG_1_RM_5_PREFIX_2, |
1191 | X86_64_0F01_REG_1_RM_6_PREFIX_2, | |
1192 | X86_64_0F01_REG_1_RM_7_PREFIX_2, | |
3873ba12 | 1193 | X86_64_0F01_REG_2, |
260cd341 | 1194 | X86_64_0F01_REG_3, |
78467458 JB |
1195 | X86_64_0F24, |
1196 | X86_64_0F26, | |
260cd341 LC |
1197 | X86_64_VEX_0F3849, |
1198 | X86_64_VEX_0F384B, | |
1199 | X86_64_VEX_0F385C, | |
f64c42a9 LC |
1200 | X86_64_VEX_0F385E, |
1201 | X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, | |
1202 | X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, | |
1203 | X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, | |
1204 | X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, | |
1205 | X86_64_0FC7_REG_6_MOD_3_PREFIX_1 | |
51e7da1b | 1206 | }; |
4e7d34a6 | 1207 | |
51e7da1b L |
1208 | enum |
1209 | { | |
1210 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1211 | THREE_BYTE_0F3A |
51e7da1b | 1212 | }; |
4e7d34a6 | 1213 | |
f88c9eb0 SP |
1214 | enum |
1215 | { | |
5dd85c99 SP |
1216 | XOP_08 = 0, |
1217 | XOP_09, | |
f88c9eb0 SP |
1218 | XOP_0A |
1219 | }; | |
1220 | ||
51e7da1b L |
1221 | enum |
1222 | { | |
1223 | VEX_0F = 0, | |
3873ba12 L |
1224 | VEX_0F38, |
1225 | VEX_0F3A | |
51e7da1b | 1226 | }; |
c0f3af97 | 1227 | |
43234a1e L |
1228 | enum |
1229 | { | |
1230 | EVEX_0F = 0, | |
1231 | EVEX_0F38, | |
1232 | EVEX_0F3A | |
1233 | }; | |
1234 | ||
51e7da1b L |
1235 | enum |
1236 | { | |
ec6f095a | 1237 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1238 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1239 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1240 | VEX_LEN_0F13_M_0, |
1241 | VEX_LEN_0F16_P_0_M_0, | |
1242 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1243 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1244 | VEX_LEN_0F17_M_0, |
43234a1e | 1245 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1246 | VEX_LEN_0F41_P_2, |
43234a1e | 1247 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1248 | VEX_LEN_0F42_P_2, |
43234a1e | 1249 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1250 | VEX_LEN_0F44_P_2, |
43234a1e | 1251 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1252 | VEX_LEN_0F45_P_2, |
43234a1e | 1253 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1254 | VEX_LEN_0F46_P_2, |
43234a1e | 1255 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1256 | VEX_LEN_0F47_P_2, |
1257 | VEX_LEN_0F4A_P_0, | |
1258 | VEX_LEN_0F4A_P_2, | |
1259 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1260 | VEX_LEN_0F4B_P_2, |
7531c613 | 1261 | VEX_LEN_0F6E, |
035e7389 | 1262 | VEX_LEN_0F77, |
592a252b L |
1263 | VEX_LEN_0F7E_P_1, |
1264 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1265 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1266 | VEX_LEN_0F90_P_2, |
43234a1e | 1267 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1268 | VEX_LEN_0F91_P_2, |
43234a1e | 1269 | VEX_LEN_0F92_P_0, |
90a915bf | 1270 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1271 | VEX_LEN_0F92_P_3, |
43234a1e | 1272 | VEX_LEN_0F93_P_0, |
90a915bf | 1273 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1274 | VEX_LEN_0F93_P_3, |
43234a1e | 1275 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1276 | VEX_LEN_0F98_P_2, |
1277 | VEX_LEN_0F99_P_0, | |
1278 | VEX_LEN_0F99_P_2, | |
592a252b L |
1279 | VEX_LEN_0FAE_R_2_M_0, |
1280 | VEX_LEN_0FAE_R_3_M_0, | |
7531c613 JB |
1281 | VEX_LEN_0FC4, |
1282 | VEX_LEN_0FC5, | |
1283 | VEX_LEN_0FD6, | |
1284 | VEX_LEN_0FF7, | |
1285 | VEX_LEN_0F3816, | |
1286 | VEX_LEN_0F3819, | |
1287 | VEX_LEN_0F381A_M_0, | |
1288 | VEX_LEN_0F3836, | |
1289 | VEX_LEN_0F3841, | |
260cd341 LC |
1290 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_0, |
1291 | VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0, | |
1292 | VEX_LEN_0F3849_X86_64_P_2_W_0_M_0, | |
1293 | VEX_LEN_0F3849_X86_64_P_3_W_0_M_0, | |
1294 | VEX_LEN_0F384B_X86_64_P_1_W_0_M_0, | |
1295 | VEX_LEN_0F384B_X86_64_P_2_W_0_M_0, | |
1296 | VEX_LEN_0F384B_X86_64_P_3_W_0_M_0, | |
7531c613 | 1297 | VEX_LEN_0F385A_M_0, |
260cd341 LC |
1298 | VEX_LEN_0F385C_X86_64_P_1_W_0_M_0, |
1299 | VEX_LEN_0F385E_X86_64_P_0_W_0_M_0, | |
1300 | VEX_LEN_0F385E_X86_64_P_1_W_0_M_0, | |
1301 | VEX_LEN_0F385E_X86_64_P_2_W_0_M_0, | |
1302 | VEX_LEN_0F385E_X86_64_P_3_W_0_M_0, | |
7531c613 | 1303 | VEX_LEN_0F38DB, |
035e7389 JB |
1304 | VEX_LEN_0F38F2, |
1305 | VEX_LEN_0F38F3_R_1, | |
1306 | VEX_LEN_0F38F3_R_2, | |
1307 | VEX_LEN_0F38F3_R_3, | |
6c30d220 L |
1308 | VEX_LEN_0F38F5_P_0, |
1309 | VEX_LEN_0F38F5_P_1, | |
1310 | VEX_LEN_0F38F5_P_3, | |
1311 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1312 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1313 | VEX_LEN_0F38F7_P_1, |
1314 | VEX_LEN_0F38F7_P_2, | |
1315 | VEX_LEN_0F38F7_P_3, | |
7531c613 JB |
1316 | VEX_LEN_0F3A00, |
1317 | VEX_LEN_0F3A01, | |
1318 | VEX_LEN_0F3A06, | |
1319 | VEX_LEN_0F3A14, | |
1320 | VEX_LEN_0F3A15, | |
1321 | VEX_LEN_0F3A16, | |
1322 | VEX_LEN_0F3A17, | |
1323 | VEX_LEN_0F3A18, | |
1324 | VEX_LEN_0F3A19, | |
1325 | VEX_LEN_0F3A20, | |
1326 | VEX_LEN_0F3A21, | |
1327 | VEX_LEN_0F3A22, | |
1328 | VEX_LEN_0F3A30, | |
1329 | VEX_LEN_0F3A31, | |
1330 | VEX_LEN_0F3A32, | |
1331 | VEX_LEN_0F3A33, | |
1332 | VEX_LEN_0F3A38, | |
1333 | VEX_LEN_0F3A39, | |
1334 | VEX_LEN_0F3A41, | |
1335 | VEX_LEN_0F3A46, | |
1336 | VEX_LEN_0F3A60, | |
1337 | VEX_LEN_0F3A61, | |
1338 | VEX_LEN_0F3A62, | |
1339 | VEX_LEN_0F3A63, | |
1340 | VEX_LEN_0F3ADF, | |
6c30d220 | 1341 | VEX_LEN_0F3AF0_P_3, |
467bbef0 JB |
1342 | VEX_LEN_0FXOP_08_85, |
1343 | VEX_LEN_0FXOP_08_86, | |
1344 | VEX_LEN_0FXOP_08_87, | |
1345 | VEX_LEN_0FXOP_08_8E, | |
1346 | VEX_LEN_0FXOP_08_8F, | |
1347 | VEX_LEN_0FXOP_08_95, | |
1348 | VEX_LEN_0FXOP_08_96, | |
1349 | VEX_LEN_0FXOP_08_97, | |
1350 | VEX_LEN_0FXOP_08_9E, | |
1351 | VEX_LEN_0FXOP_08_9F, | |
1352 | VEX_LEN_0FXOP_08_A3, | |
1353 | VEX_LEN_0FXOP_08_A6, | |
1354 | VEX_LEN_0FXOP_08_B6, | |
1355 | VEX_LEN_0FXOP_08_C0, | |
1356 | VEX_LEN_0FXOP_08_C1, | |
1357 | VEX_LEN_0FXOP_08_C2, | |
1358 | VEX_LEN_0FXOP_08_C3, | |
ff688e1f L |
1359 | VEX_LEN_0FXOP_08_CC, |
1360 | VEX_LEN_0FXOP_08_CD, | |
1361 | VEX_LEN_0FXOP_08_CE, | |
1362 | VEX_LEN_0FXOP_08_CF, | |
1363 | VEX_LEN_0FXOP_08_EC, | |
1364 | VEX_LEN_0FXOP_08_ED, | |
1365 | VEX_LEN_0FXOP_08_EE, | |
1366 | VEX_LEN_0FXOP_08_EF, | |
467bbef0 JB |
1367 | VEX_LEN_0FXOP_09_01, |
1368 | VEX_LEN_0FXOP_09_02, | |
1369 | VEX_LEN_0FXOP_09_12_M_1, | |
b5b098c2 JB |
1370 | VEX_LEN_0FXOP_09_82_W_0, |
1371 | VEX_LEN_0FXOP_09_83_W_0, | |
467bbef0 JB |
1372 | VEX_LEN_0FXOP_09_90, |
1373 | VEX_LEN_0FXOP_09_91, | |
1374 | VEX_LEN_0FXOP_09_92, | |
1375 | VEX_LEN_0FXOP_09_93, | |
1376 | VEX_LEN_0FXOP_09_94, | |
1377 | VEX_LEN_0FXOP_09_95, | |
1378 | VEX_LEN_0FXOP_09_96, | |
1379 | VEX_LEN_0FXOP_09_97, | |
1380 | VEX_LEN_0FXOP_09_98, | |
1381 | VEX_LEN_0FXOP_09_99, | |
1382 | VEX_LEN_0FXOP_09_9A, | |
1383 | VEX_LEN_0FXOP_09_9B, | |
1384 | VEX_LEN_0FXOP_09_C1, | |
1385 | VEX_LEN_0FXOP_09_C2, | |
1386 | VEX_LEN_0FXOP_09_C3, | |
1387 | VEX_LEN_0FXOP_09_C6, | |
1388 | VEX_LEN_0FXOP_09_C7, | |
1389 | VEX_LEN_0FXOP_09_CB, | |
1390 | VEX_LEN_0FXOP_09_D1, | |
1391 | VEX_LEN_0FXOP_09_D2, | |
1392 | VEX_LEN_0FXOP_09_D3, | |
1393 | VEX_LEN_0FXOP_09_D6, | |
1394 | VEX_LEN_0FXOP_09_D7, | |
1395 | VEX_LEN_0FXOP_09_DB, | |
1396 | VEX_LEN_0FXOP_09_E1, | |
1397 | VEX_LEN_0FXOP_09_E2, | |
1398 | VEX_LEN_0FXOP_09_E3, | |
1399 | VEX_LEN_0FXOP_0A_12, | |
51e7da1b | 1400 | }; |
c0f3af97 | 1401 | |
04e2a182 L |
1402 | enum |
1403 | { | |
7531c613 | 1404 | EVEX_LEN_0F6E = 0, |
04e2a182 L |
1405 | EVEX_LEN_0F7E_P_1, |
1406 | EVEX_LEN_0F7E_P_2, | |
7531c613 JB |
1407 | EVEX_LEN_0FC4, |
1408 | EVEX_LEN_0FC5, | |
1409 | EVEX_LEN_0FD6, | |
1410 | EVEX_LEN_0F3816, | |
1411 | EVEX_LEN_0F3819_W_0, | |
1412 | EVEX_LEN_0F3819_W_1, | |
1413 | EVEX_LEN_0F381A_W_0_M_0, | |
1414 | EVEX_LEN_0F381A_W_1_M_0, | |
1415 | EVEX_LEN_0F381B_W_0_M_0, | |
1416 | EVEX_LEN_0F381B_W_1_M_0, | |
1417 | EVEX_LEN_0F3836, | |
1418 | EVEX_LEN_0F385A_W_0_M_0, | |
1419 | EVEX_LEN_0F385A_W_1_M_0, | |
1420 | EVEX_LEN_0F385B_W_0_M_0, | |
1421 | EVEX_LEN_0F385B_W_1_M_0, | |
1422 | EVEX_LEN_0F38C6_R_1_M_0, | |
1423 | EVEX_LEN_0F38C6_R_2_M_0, | |
1424 | EVEX_LEN_0F38C6_R_5_M_0, | |
1425 | EVEX_LEN_0F38C6_R_6_M_0, | |
1426 | EVEX_LEN_0F38C7_R_1_M_0_W_0, | |
1427 | EVEX_LEN_0F38C7_R_1_M_0_W_1, | |
1428 | EVEX_LEN_0F38C7_R_2_M_0_W_0, | |
1429 | EVEX_LEN_0F38C7_R_2_M_0_W_1, | |
1430 | EVEX_LEN_0F38C7_R_5_M_0_W_0, | |
1431 | EVEX_LEN_0F38C7_R_5_M_0_W_1, | |
1432 | EVEX_LEN_0F38C7_R_6_M_0_W_0, | |
1433 | EVEX_LEN_0F38C7_R_6_M_0_W_1, | |
1434 | EVEX_LEN_0F3A00_W_1, | |
1435 | EVEX_LEN_0F3A01_W_1, | |
1436 | EVEX_LEN_0F3A14, | |
1437 | EVEX_LEN_0F3A15, | |
1438 | EVEX_LEN_0F3A16, | |
1439 | EVEX_LEN_0F3A17, | |
1440 | EVEX_LEN_0F3A18_W_0, | |
1441 | EVEX_LEN_0F3A18_W_1, | |
1442 | EVEX_LEN_0F3A19_W_0, | |
1443 | EVEX_LEN_0F3A19_W_1, | |
1444 | EVEX_LEN_0F3A1A_W_0, | |
1445 | EVEX_LEN_0F3A1A_W_1, | |
1446 | EVEX_LEN_0F3A1B_W_0, | |
1447 | EVEX_LEN_0F3A1B_W_1, | |
1448 | EVEX_LEN_0F3A20, | |
1449 | EVEX_LEN_0F3A21_W_0, | |
1450 | EVEX_LEN_0F3A22, | |
1451 | EVEX_LEN_0F3A23_W_0, | |
1452 | EVEX_LEN_0F3A23_W_1, | |
1453 | EVEX_LEN_0F3A38_W_0, | |
1454 | EVEX_LEN_0F3A38_W_1, | |
1455 | EVEX_LEN_0F3A39_W_0, | |
1456 | EVEX_LEN_0F3A39_W_1, | |
1457 | EVEX_LEN_0F3A3A_W_0, | |
1458 | EVEX_LEN_0F3A3A_W_1, | |
1459 | EVEX_LEN_0F3A3B_W_0, | |
1460 | EVEX_LEN_0F3A3B_W_1, | |
1461 | EVEX_LEN_0F3A43_W_0, | |
1462 | EVEX_LEN_0F3A43_W_1 | |
04e2a182 L |
1463 | }; |
1464 | ||
9e30b8e0 L |
1465 | enum |
1466 | { | |
ec6f095a | 1467 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1468 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1469 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1470 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1471 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1472 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1473 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1474 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1475 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1476 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1477 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1478 | VEX_W_0F47_P_2_LEN_1, |
1479 | VEX_W_0F4A_P_0_LEN_1, | |
1480 | VEX_W_0F4A_P_2_LEN_1, | |
1481 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1482 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1483 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1484 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1485 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1486 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1487 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1488 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1489 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1490 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1491 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1492 | VEX_W_0F98_P_2_LEN_0, |
1493 | VEX_W_0F99_P_0_LEN_0, | |
1494 | VEX_W_0F99_P_2_LEN_0, | |
7531c613 JB |
1495 | VEX_W_0F380C, |
1496 | VEX_W_0F380D, | |
1497 | VEX_W_0F380E, | |
1498 | VEX_W_0F380F, | |
1499 | VEX_W_0F3813, | |
1500 | VEX_W_0F3816_L_1, | |
1501 | VEX_W_0F3818, | |
1502 | VEX_W_0F3819_L_1, | |
1503 | VEX_W_0F381A_M_0_L_1, | |
1504 | VEX_W_0F382C_M_0, | |
1505 | VEX_W_0F382D_M_0, | |
1506 | VEX_W_0F382E_M_0, | |
1507 | VEX_W_0F382F_M_0, | |
1508 | VEX_W_0F3836, | |
1509 | VEX_W_0F3846, | |
260cd341 LC |
1510 | VEX_W_0F3849_X86_64_P_0, |
1511 | VEX_W_0F3849_X86_64_P_2, | |
1512 | VEX_W_0F3849_X86_64_P_3, | |
1513 | VEX_W_0F384B_X86_64_P_1, | |
1514 | VEX_W_0F384B_X86_64_P_2, | |
1515 | VEX_W_0F384B_X86_64_P_3, | |
58bf9b6a L |
1516 | VEX_W_0F3850, |
1517 | VEX_W_0F3851, | |
1518 | VEX_W_0F3852, | |
1519 | VEX_W_0F3853, | |
7531c613 JB |
1520 | VEX_W_0F3858, |
1521 | VEX_W_0F3859, | |
1522 | VEX_W_0F385A_M_0_L_0, | |
260cd341 LC |
1523 | VEX_W_0F385C_X86_64_P_1, |
1524 | VEX_W_0F385E_X86_64_P_0, | |
1525 | VEX_W_0F385E_X86_64_P_1, | |
1526 | VEX_W_0F385E_X86_64_P_2, | |
1527 | VEX_W_0F385E_X86_64_P_3, | |
7531c613 JB |
1528 | VEX_W_0F3878, |
1529 | VEX_W_0F3879, | |
1530 | VEX_W_0F38CF, | |
1531 | VEX_W_0F3A00_L_1, | |
1532 | VEX_W_0F3A01_L_1, | |
1533 | VEX_W_0F3A02, | |
1534 | VEX_W_0F3A04, | |
1535 | VEX_W_0F3A05, | |
1536 | VEX_W_0F3A06_L_1, | |
1537 | VEX_W_0F3A18_L_1, | |
1538 | VEX_W_0F3A19_L_1, | |
1539 | VEX_W_0F3A1D, | |
7531c613 JB |
1540 | VEX_W_0F3A38_L_1, |
1541 | VEX_W_0F3A39_L_1, | |
1542 | VEX_W_0F3A46_L_1, | |
1543 | VEX_W_0F3A4A, | |
1544 | VEX_W_0F3A4B, | |
1545 | VEX_W_0F3A4C, | |
1546 | VEX_W_0F3ACE, | |
1547 | VEX_W_0F3ACF, | |
43234a1e | 1548 | |
467bbef0 JB |
1549 | VEX_W_0FXOP_08_85_L_0, |
1550 | VEX_W_0FXOP_08_86_L_0, | |
1551 | VEX_W_0FXOP_08_87_L_0, | |
1552 | VEX_W_0FXOP_08_8E_L_0, | |
1553 | VEX_W_0FXOP_08_8F_L_0, | |
1554 | VEX_W_0FXOP_08_95_L_0, | |
1555 | VEX_W_0FXOP_08_96_L_0, | |
1556 | VEX_W_0FXOP_08_97_L_0, | |
1557 | VEX_W_0FXOP_08_9E_L_0, | |
1558 | VEX_W_0FXOP_08_9F_L_0, | |
1559 | VEX_W_0FXOP_08_A6_L_0, | |
1560 | VEX_W_0FXOP_08_B6_L_0, | |
1561 | VEX_W_0FXOP_08_C0_L_0, | |
1562 | VEX_W_0FXOP_08_C1_L_0, | |
1563 | VEX_W_0FXOP_08_C2_L_0, | |
1564 | VEX_W_0FXOP_08_C3_L_0, | |
1565 | VEX_W_0FXOP_08_CC_L_0, | |
1566 | VEX_W_0FXOP_08_CD_L_0, | |
1567 | VEX_W_0FXOP_08_CE_L_0, | |
1568 | VEX_W_0FXOP_08_CF_L_0, | |
1569 | VEX_W_0FXOP_08_EC_L_0, | |
1570 | VEX_W_0FXOP_08_ED_L_0, | |
1571 | VEX_W_0FXOP_08_EE_L_0, | |
1572 | VEX_W_0FXOP_08_EF_L_0, | |
1573 | ||
b5b098c2 JB |
1574 | VEX_W_0FXOP_09_80, |
1575 | VEX_W_0FXOP_09_81, | |
1576 | VEX_W_0FXOP_09_82, | |
1577 | VEX_W_0FXOP_09_83, | |
467bbef0 JB |
1578 | VEX_W_0FXOP_09_C1_L_0, |
1579 | VEX_W_0FXOP_09_C2_L_0, | |
1580 | VEX_W_0FXOP_09_C3_L_0, | |
1581 | VEX_W_0FXOP_09_C6_L_0, | |
1582 | VEX_W_0FXOP_09_C7_L_0, | |
1583 | VEX_W_0FXOP_09_CB_L_0, | |
1584 | VEX_W_0FXOP_09_D1_L_0, | |
1585 | VEX_W_0FXOP_09_D2_L_0, | |
1586 | VEX_W_0FXOP_09_D3_L_0, | |
1587 | VEX_W_0FXOP_09_D6_L_0, | |
1588 | VEX_W_0FXOP_09_D7_L_0, | |
1589 | VEX_W_0FXOP_09_DB_L_0, | |
1590 | VEX_W_0FXOP_09_E1_L_0, | |
1591 | VEX_W_0FXOP_09_E2_L_0, | |
1592 | VEX_W_0FXOP_09_E3_L_0, | |
b5b098c2 | 1593 | |
36cc073e | 1594 | EVEX_W_0F10_P_1, |
36cc073e | 1595 | EVEX_W_0F10_P_3, |
36cc073e | 1596 | EVEX_W_0F11_P_1, |
36cc073e | 1597 | EVEX_W_0F11_P_3, |
43234a1e L |
1598 | EVEX_W_0F12_P_0_M_1, |
1599 | EVEX_W_0F12_P_1, | |
43234a1e | 1600 | EVEX_W_0F12_P_3, |
43234a1e L |
1601 | EVEX_W_0F16_P_0_M_1, |
1602 | EVEX_W_0F16_P_1, | |
43234a1e | 1603 | EVEX_W_0F2A_P_3, |
43234a1e | 1604 | EVEX_W_0F51_P_1, |
43234a1e | 1605 | EVEX_W_0F51_P_3, |
43234a1e | 1606 | EVEX_W_0F58_P_1, |
43234a1e | 1607 | EVEX_W_0F58_P_3, |
43234a1e | 1608 | EVEX_W_0F59_P_1, |
43234a1e L |
1609 | EVEX_W_0F59_P_3, |
1610 | EVEX_W_0F5A_P_0, | |
1611 | EVEX_W_0F5A_P_1, | |
1612 | EVEX_W_0F5A_P_2, | |
1613 | EVEX_W_0F5A_P_3, | |
1614 | EVEX_W_0F5B_P_0, | |
1615 | EVEX_W_0F5B_P_1, | |
1616 | EVEX_W_0F5B_P_2, | |
43234a1e | 1617 | EVEX_W_0F5C_P_1, |
43234a1e | 1618 | EVEX_W_0F5C_P_3, |
43234a1e | 1619 | EVEX_W_0F5D_P_1, |
43234a1e | 1620 | EVEX_W_0F5D_P_3, |
43234a1e | 1621 | EVEX_W_0F5E_P_1, |
43234a1e | 1622 | EVEX_W_0F5E_P_3, |
43234a1e | 1623 | EVEX_W_0F5F_P_1, |
43234a1e | 1624 | EVEX_W_0F5F_P_3, |
fedfb81e | 1625 | EVEX_W_0F62, |
7531c613 | 1626 | EVEX_W_0F66, |
fedfb81e JB |
1627 | EVEX_W_0F6A, |
1628 | EVEX_W_0F6B, | |
1629 | EVEX_W_0F6C, | |
1630 | EVEX_W_0F6D, | |
43234a1e L |
1631 | EVEX_W_0F6F_P_1, |
1632 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1633 | EVEX_W_0F6F_P_3, |
43234a1e | 1634 | EVEX_W_0F70_P_2, |
7531c613 JB |
1635 | EVEX_W_0F72_R_2, |
1636 | EVEX_W_0F72_R_6, | |
1637 | EVEX_W_0F73_R_2, | |
1638 | EVEX_W_0F73_R_6, | |
1639 | EVEX_W_0F76, | |
43234a1e | 1640 | EVEX_W_0F78_P_0, |
90a915bf | 1641 | EVEX_W_0F78_P_2, |
43234a1e | 1642 | EVEX_W_0F79_P_0, |
90a915bf | 1643 | EVEX_W_0F79_P_2, |
43234a1e | 1644 | EVEX_W_0F7A_P_1, |
90a915bf | 1645 | EVEX_W_0F7A_P_2, |
43234a1e | 1646 | EVEX_W_0F7A_P_3, |
90a915bf | 1647 | EVEX_W_0F7B_P_2, |
43234a1e L |
1648 | EVEX_W_0F7B_P_3, |
1649 | EVEX_W_0F7E_P_1, | |
43234a1e L |
1650 | EVEX_W_0F7F_P_1, |
1651 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 1652 | EVEX_W_0F7F_P_3, |
43234a1e | 1653 | EVEX_W_0FC2_P_1, |
43234a1e | 1654 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
1655 | EVEX_W_0FD2, |
1656 | EVEX_W_0FD3, | |
1657 | EVEX_W_0FD4, | |
7531c613 | 1658 | EVEX_W_0FD6_L_0, |
43234a1e L |
1659 | EVEX_W_0FE6_P_1, |
1660 | EVEX_W_0FE6_P_2, | |
1661 | EVEX_W_0FE6_P_3, | |
7531c613 | 1662 | EVEX_W_0FE7, |
fedfb81e JB |
1663 | EVEX_W_0FF2, |
1664 | EVEX_W_0FF3, | |
1665 | EVEX_W_0FF4, | |
1666 | EVEX_W_0FFA, | |
1667 | EVEX_W_0FFB, | |
1668 | EVEX_W_0FFE, | |
7531c613 | 1669 | EVEX_W_0F380D, |
1ba585e8 IT |
1670 | EVEX_W_0F3810_P_1, |
1671 | EVEX_W_0F3810_P_2, | |
43234a1e | 1672 | EVEX_W_0F3811_P_1, |
1ba585e8 | 1673 | EVEX_W_0F3811_P_2, |
43234a1e | 1674 | EVEX_W_0F3812_P_1, |
1ba585e8 | 1675 | EVEX_W_0F3812_P_2, |
43234a1e L |
1676 | EVEX_W_0F3813_P_1, |
1677 | EVEX_W_0F3813_P_2, | |
1678 | EVEX_W_0F3814_P_1, | |
1679 | EVEX_W_0F3815_P_1, | |
7531c613 JB |
1680 | EVEX_W_0F3819, |
1681 | EVEX_W_0F381A, | |
1682 | EVEX_W_0F381B, | |
1683 | EVEX_W_0F381E, | |
1684 | EVEX_W_0F381F, | |
1ba585e8 | 1685 | EVEX_W_0F3820_P_1, |
43234a1e L |
1686 | EVEX_W_0F3821_P_1, |
1687 | EVEX_W_0F3822_P_1, | |
1688 | EVEX_W_0F3823_P_1, | |
1689 | EVEX_W_0F3824_P_1, | |
1690 | EVEX_W_0F3825_P_1, | |
1691 | EVEX_W_0F3825_P_2, | |
1692 | EVEX_W_0F3828_P_2, | |
1693 | EVEX_W_0F3829_P_2, | |
1694 | EVEX_W_0F382A_P_1, | |
1695 | EVEX_W_0F382A_P_2, | |
fedfb81e | 1696 | EVEX_W_0F382B, |
1ba585e8 | 1697 | EVEX_W_0F3830_P_1, |
43234a1e L |
1698 | EVEX_W_0F3831_P_1, |
1699 | EVEX_W_0F3832_P_1, | |
1700 | EVEX_W_0F3833_P_1, | |
1701 | EVEX_W_0F3834_P_1, | |
1702 | EVEX_W_0F3835_P_1, | |
1703 | EVEX_W_0F3835_P_2, | |
7531c613 | 1704 | EVEX_W_0F3837, |
43234a1e | 1705 | EVEX_W_0F383A_P_1, |
d6aab7a1 | 1706 | EVEX_W_0F3852_P_1, |
7531c613 JB |
1707 | EVEX_W_0F3859, |
1708 | EVEX_W_0F385A, | |
1709 | EVEX_W_0F385B, | |
1710 | EVEX_W_0F3870, | |
d6aab7a1 | 1711 | EVEX_W_0F3872_P_1, |
53467f57 | 1712 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 1713 | EVEX_W_0F3872_P_3, |
7531c613 JB |
1714 | EVEX_W_0F387A, |
1715 | EVEX_W_0F387B, | |
1716 | EVEX_W_0F3883, | |
1717 | EVEX_W_0F3891, | |
1718 | EVEX_W_0F3893, | |
1719 | EVEX_W_0F38A1, | |
1720 | EVEX_W_0F38A3, | |
1721 | EVEX_W_0F38C7_R_1_M_0, | |
1722 | EVEX_W_0F38C7_R_2_M_0, | |
1723 | EVEX_W_0F38C7_R_5_M_0, | |
1724 | EVEX_W_0F38C7_R_6_M_0, | |
1725 | ||
1726 | EVEX_W_0F3A00, | |
1727 | EVEX_W_0F3A01, | |
1728 | EVEX_W_0F3A05, | |
1729 | EVEX_W_0F3A08, | |
1730 | EVEX_W_0F3A09, | |
1731 | EVEX_W_0F3A0A, | |
1732 | EVEX_W_0F3A0B, | |
1733 | EVEX_W_0F3A18, | |
1734 | EVEX_W_0F3A19, | |
1735 | EVEX_W_0F3A1A, | |
1736 | EVEX_W_0F3A1B, | |
1737 | EVEX_W_0F3A21, | |
1738 | EVEX_W_0F3A23, | |
1739 | EVEX_W_0F3A38, | |
1740 | EVEX_W_0F3A39, | |
1741 | EVEX_W_0F3A3A, | |
1742 | EVEX_W_0F3A3B, | |
1743 | EVEX_W_0F3A42, | |
1744 | EVEX_W_0F3A43, | |
1745 | EVEX_W_0F3A70, | |
1746 | EVEX_W_0F3A72, | |
9e30b8e0 L |
1747 | }; |
1748 | ||
26ca5450 | 1749 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
1750 | |
1751 | struct dis386 { | |
2da11e11 | 1752 | const char *name; |
ce518a5f L |
1753 | struct |
1754 | { | |
1755 | op_rtn rtn; | |
1756 | int bytemode; | |
1757 | } op[MAX_OPERANDS]; | |
bf890a93 | 1758 | unsigned int prefix_requirement; |
252b5132 RH |
1759 | }; |
1760 | ||
1761 | /* Upper case letters in the instruction names here are macros. | |
1762 | 'A' => print 'b' if no register operands or suffix_always is true | |
1763 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1764 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1765 | size prefix |
ed7841b3 | 1766 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1767 | suffix_always is true |
252b5132 | 1768 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1769 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1770 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1771 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 1772 | 'I' unused. |
8f570d62 | 1773 | 'J' unused. |
42903f7f | 1774 | 'K' => print 'd' or 'q' if rex prefix is present. |
78467458 | 1775 | 'L' unused. |
9d141669 | 1776 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1777 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1778 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
36938cab JB |
1779 | 'P' => behave as 'T' except with register operand outside of suffix_always |
1780 | mode | |
98b528ac L |
1781 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
1782 | is true | |
a35ca55a | 1783 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1784 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
36938cab JB |
1785 | 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size |
1786 | prefix or if suffix_always is true. | |
1787 | 'U' unused. | |
c3f5525f | 1788 | 'V' unused. |
a35ca55a | 1789 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1790 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 1791 | 'Y' unused. |
78467458 | 1792 | 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true. |
9d141669 | 1793 | '!' => change condition from true to false or from false to true. |
98b528ac | 1794 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
1795 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
1796 | prefix or suffix_always is true (lcall/ljmp). | |
36938cab JB |
1797 | '@' => in 64bit mode for Intel64 ISA or if instruction |
1798 | has no operand sizing prefix, print 'q' if suffix_always is true or | |
1799 | nothing otherwise; behave as 'P' in all other cases | |
98b528ac L |
1800 | |
1801 | 2 upper case letter macros: | |
04d824a4 JB |
1802 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
1803 | operands and no broadcast. | |
1804 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
1805 | register operands and no broadcast. | |
4b06377f | 1806 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
58bf9b6a | 1807 | "XV" => print "{vex3}" pseudo prefix |
b24d668c JB |
1808 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond |
1809 | being false, or no operand at all in 64bit mode, or if suffix_always | |
589958d6 | 1810 | is true. |
4b06377f L |
1811 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1812 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1813 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
492a76aa | 1814 | "DQ" => print 'd' or 'q' depending on the VEX.W bit |
bb5b3501 | 1815 | "BW" => print 'b' or 'w' depending on the VEX.W bit |
4b4c407a L |
1816 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
1817 | an operand size prefix, or suffix_always is true. print | |
1818 | 'q' if rex prefix is present. | |
52b15da3 | 1819 | |
6439fc28 AM |
1820 | Many of the above letters print nothing in Intel mode. See "putop" |
1821 | for the details. | |
52b15da3 | 1822 | |
6439fc28 | 1823 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1824 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1825 | |
6439fc28 | 1826 | static const struct dis386 dis386[] = { |
252b5132 | 1827 | /* 00 */ |
bf890a93 IT |
1828 | { "addB", { Ebh1, Gb }, 0 }, |
1829 | { "addS", { Evh1, Gv }, 0 }, | |
1830 | { "addB", { Gb, EbS }, 0 }, | |
1831 | { "addS", { Gv, EvS }, 0 }, | |
1832 | { "addB", { AL, Ib }, 0 }, | |
1833 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1834 | { X86_64_TABLE (X86_64_06) }, |
1835 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1836 | /* 08 */ |
bf890a93 IT |
1837 | { "orB", { Ebh1, Gb }, 0 }, |
1838 | { "orS", { Evh1, Gv }, 0 }, | |
1839 | { "orB", { Gb, EbS }, 0 }, | |
1840 | { "orS", { Gv, EvS }, 0 }, | |
1841 | { "orB", { AL, Ib }, 0 }, | |
1842 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 1843 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 1844 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1845 | /* 10 */ |
bf890a93 IT |
1846 | { "adcB", { Ebh1, Gb }, 0 }, |
1847 | { "adcS", { Evh1, Gv }, 0 }, | |
1848 | { "adcB", { Gb, EbS }, 0 }, | |
1849 | { "adcS", { Gv, EvS }, 0 }, | |
1850 | { "adcB", { AL, Ib }, 0 }, | |
1851 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1852 | { X86_64_TABLE (X86_64_16) }, |
1853 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1854 | /* 18 */ |
bf890a93 IT |
1855 | { "sbbB", { Ebh1, Gb }, 0 }, |
1856 | { "sbbS", { Evh1, Gv }, 0 }, | |
1857 | { "sbbB", { Gb, EbS }, 0 }, | |
1858 | { "sbbS", { Gv, EvS }, 0 }, | |
1859 | { "sbbB", { AL, Ib }, 0 }, | |
1860 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1861 | { X86_64_TABLE (X86_64_1E) }, |
1862 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1863 | /* 20 */ |
bf890a93 IT |
1864 | { "andB", { Ebh1, Gb }, 0 }, |
1865 | { "andS", { Evh1, Gv }, 0 }, | |
1866 | { "andB", { Gb, EbS }, 0 }, | |
1867 | { "andS", { Gv, EvS }, 0 }, | |
1868 | { "andB", { AL, Ib }, 0 }, | |
1869 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 1870 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1871 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1872 | /* 28 */ |
bf890a93 IT |
1873 | { "subB", { Ebh1, Gb }, 0 }, |
1874 | { "subS", { Evh1, Gv }, 0 }, | |
1875 | { "subB", { Gb, EbS }, 0 }, | |
1876 | { "subS", { Gv, EvS }, 0 }, | |
1877 | { "subB", { AL, Ib }, 0 }, | |
1878 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 1879 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1880 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1881 | /* 30 */ |
bf890a93 IT |
1882 | { "xorB", { Ebh1, Gb }, 0 }, |
1883 | { "xorS", { Evh1, Gv }, 0 }, | |
1884 | { "xorB", { Gb, EbS }, 0 }, | |
1885 | { "xorS", { Gv, EvS }, 0 }, | |
1886 | { "xorB", { AL, Ib }, 0 }, | |
1887 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 1888 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1889 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1890 | /* 38 */ |
bf890a93 IT |
1891 | { "cmpB", { Eb, Gb }, 0 }, |
1892 | { "cmpS", { Ev, Gv }, 0 }, | |
1893 | { "cmpB", { Gb, EbS }, 0 }, | |
1894 | { "cmpS", { Gv, EvS }, 0 }, | |
1895 | { "cmpB", { AL, Ib }, 0 }, | |
1896 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 1897 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1898 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1899 | /* 40 */ |
bf890a93 IT |
1900 | { "inc{S|}", { RMeAX }, 0 }, |
1901 | { "inc{S|}", { RMeCX }, 0 }, | |
1902 | { "inc{S|}", { RMeDX }, 0 }, | |
1903 | { "inc{S|}", { RMeBX }, 0 }, | |
1904 | { "inc{S|}", { RMeSP }, 0 }, | |
1905 | { "inc{S|}", { RMeBP }, 0 }, | |
1906 | { "inc{S|}", { RMeSI }, 0 }, | |
1907 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 1908 | /* 48 */ |
bf890a93 IT |
1909 | { "dec{S|}", { RMeAX }, 0 }, |
1910 | { "dec{S|}", { RMeCX }, 0 }, | |
1911 | { "dec{S|}", { RMeDX }, 0 }, | |
1912 | { "dec{S|}", { RMeBX }, 0 }, | |
1913 | { "dec{S|}", { RMeSP }, 0 }, | |
1914 | { "dec{S|}", { RMeBP }, 0 }, | |
1915 | { "dec{S|}", { RMeSI }, 0 }, | |
1916 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 1917 | /* 50 */ |
c3f5525f JB |
1918 | { "push{!P|}", { RMrAX }, 0 }, |
1919 | { "push{!P|}", { RMrCX }, 0 }, | |
1920 | { "push{!P|}", { RMrDX }, 0 }, | |
1921 | { "push{!P|}", { RMrBX }, 0 }, | |
1922 | { "push{!P|}", { RMrSP }, 0 }, | |
1923 | { "push{!P|}", { RMrBP }, 0 }, | |
1924 | { "push{!P|}", { RMrSI }, 0 }, | |
1925 | { "push{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1926 | /* 58 */ |
c3f5525f JB |
1927 | { "pop{!P|}", { RMrAX }, 0 }, |
1928 | { "pop{!P|}", { RMrCX }, 0 }, | |
1929 | { "pop{!P|}", { RMrDX }, 0 }, | |
1930 | { "pop{!P|}", { RMrBX }, 0 }, | |
1931 | { "pop{!P|}", { RMrSP }, 0 }, | |
1932 | { "pop{!P|}", { RMrBP }, 0 }, | |
1933 | { "pop{!P|}", { RMrSI }, 0 }, | |
1934 | { "pop{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1935 | /* 60 */ |
4e7d34a6 L |
1936 | { X86_64_TABLE (X86_64_60) }, |
1937 | { X86_64_TABLE (X86_64_61) }, | |
1938 | { X86_64_TABLE (X86_64_62) }, | |
1939 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1940 | { Bad_Opcode }, /* seg fs */ |
1941 | { Bad_Opcode }, /* seg gs */ | |
1942 | { Bad_Opcode }, /* op size prefix */ | |
1943 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1944 | /* 68 */ |
36938cab | 1945 | { "pushP", { sIv }, 0 }, |
bf890a93 | 1946 | { "imulS", { Gv, Ev, Iv }, 0 }, |
36938cab | 1947 | { "pushP", { sIbT }, 0 }, |
bf890a93 IT |
1948 | { "imulS", { Gv, Ev, sIb }, 0 }, |
1949 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 1950 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 1951 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 1952 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1953 | /* 70 */ |
bf890a93 IT |
1954 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
1955 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
1956 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
1957 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1958 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1959 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
1960 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1961 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1962 | /* 78 */ |
bf890a93 IT |
1963 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
1964 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
1965 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1966 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1967 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
1968 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1969 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
1970 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1971 | /* 80 */ |
1ceb70f8 L |
1972 | { REG_TABLE (REG_80) }, |
1973 | { REG_TABLE (REG_81) }, | |
d039fef3 | 1974 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 1975 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
1976 | { "testB", { Eb, Gb }, 0 }, |
1977 | { "testS", { Ev, Gv }, 0 }, | |
1978 | { "xchgB", { Ebh2, Gb }, 0 }, | |
1979 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 1980 | /* 88 */ |
bf890a93 IT |
1981 | { "movB", { Ebh3, Gb }, 0 }, |
1982 | { "movS", { Evh3, Gv }, 0 }, | |
1983 | { "movB", { Gb, EbS }, 0 }, | |
1984 | { "movS", { Gv, EvS }, 0 }, | |
1985 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 1986 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 1987 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 1988 | { REG_TABLE (REG_8F) }, |
252b5132 | 1989 | /* 90 */ |
1ceb70f8 | 1990 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
1991 | { "xchgS", { RMeCX, eAX }, 0 }, |
1992 | { "xchgS", { RMeDX, eAX }, 0 }, | |
1993 | { "xchgS", { RMeBX, eAX }, 0 }, | |
1994 | { "xchgS", { RMeSP, eAX }, 0 }, | |
1995 | { "xchgS", { RMeBP, eAX }, 0 }, | |
1996 | { "xchgS", { RMeSI, eAX }, 0 }, | |
1997 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 1998 | /* 98 */ |
bf890a93 IT |
1999 | { "cW{t|}R", { XX }, 0 }, |
2000 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2001 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2002 | { Bad_Opcode }, /* fwait */ |
36938cab JB |
2003 | { "pushfP", { XX }, 0 }, |
2004 | { "popfP", { XX }, 0 }, | |
bf890a93 IT |
2005 | { "sahf", { XX }, 0 }, |
2006 | { "lahf", { XX }, 0 }, | |
252b5132 | 2007 | /* a0 */ |
bf890a93 IT |
2008 | { "mov%LB", { AL, Ob }, 0 }, |
2009 | { "mov%LS", { eAX, Ov }, 0 }, | |
2010 | { "mov%LB", { Ob, AL }, 0 }, | |
2011 | { "mov%LS", { Ov, eAX }, 0 }, | |
2012 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2013 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2014 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2015 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2016 | /* a8 */ |
bf890a93 IT |
2017 | { "testB", { AL, Ib }, 0 }, |
2018 | { "testS", { eAX, Iv }, 0 }, | |
2019 | { "stosB", { Ybr, AL }, 0 }, | |
2020 | { "stosS", { Yvr, eAX }, 0 }, | |
2021 | { "lodsB", { ALr, Xb }, 0 }, | |
2022 | { "lodsS", { eAXr, Xv }, 0 }, | |
2023 | { "scasB", { AL, Yb }, 0 }, | |
2024 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2025 | /* b0 */ |
bf890a93 IT |
2026 | { "movB", { RMAL, Ib }, 0 }, |
2027 | { "movB", { RMCL, Ib }, 0 }, | |
2028 | { "movB", { RMDL, Ib }, 0 }, | |
2029 | { "movB", { RMBL, Ib }, 0 }, | |
2030 | { "movB", { RMAH, Ib }, 0 }, | |
2031 | { "movB", { RMCH, Ib }, 0 }, | |
2032 | { "movB", { RMDH, Ib }, 0 }, | |
2033 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2034 | /* b8 */ |
bf890a93 IT |
2035 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2036 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2037 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2038 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2039 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2040 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2041 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2042 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2043 | /* c0 */ |
1ceb70f8 L |
2044 | { REG_TABLE (REG_C0) }, |
2045 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2046 | { X86_64_TABLE (X86_64_C2) }, |
2047 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2048 | { X86_64_TABLE (X86_64_C4) }, |
2049 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2050 | { REG_TABLE (REG_C6) }, |
2051 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2052 | /* c8 */ |
36938cab JB |
2053 | { "enterP", { Iw, Ib }, 0 }, |
2054 | { "leaveP", { XX }, 0 }, | |
2055 | { "{l|}ret{|f}%LP", { Iw }, 0 }, | |
2056 | { "{l|}ret{|f}%LP", { XX }, 0 }, | |
bf890a93 IT |
2057 | { "int3", { XX }, 0 }, |
2058 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2059 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2060 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2061 | /* d0 */ |
1ceb70f8 L |
2062 | { REG_TABLE (REG_D0) }, |
2063 | { REG_TABLE (REG_D1) }, | |
2064 | { REG_TABLE (REG_D2) }, | |
2065 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2066 | { X86_64_TABLE (X86_64_D4) }, |
2067 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2068 | { Bad_Opcode }, |
bf890a93 | 2069 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2070 | /* d8 */ |
2071 | { FLOAT }, | |
2072 | { FLOAT }, | |
2073 | { FLOAT }, | |
2074 | { FLOAT }, | |
2075 | { FLOAT }, | |
2076 | { FLOAT }, | |
2077 | { FLOAT }, | |
2078 | { FLOAT }, | |
2079 | /* e0 */ | |
bf890a93 IT |
2080 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2081 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2082 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2083 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2084 | { "inB", { AL, Ib }, 0 }, | |
2085 | { "inG", { zAX, Ib }, 0 }, | |
2086 | { "outB", { Ib, AL }, 0 }, | |
2087 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2088 | /* e8 */ |
a72d2af2 L |
2089 | { X86_64_TABLE (X86_64_E8) }, |
2090 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2091 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2092 | { "jmp", { Jb, BND }, 0 }, |
2093 | { "inB", { AL, indirDX }, 0 }, | |
2094 | { "inG", { zAX, indirDX }, 0 }, | |
2095 | { "outB", { indirDX, AL }, 0 }, | |
2096 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2097 | /* f0 */ |
592d1631 | 2098 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2099 | { "icebp", { XX }, 0 }, |
592d1631 L |
2100 | { Bad_Opcode }, /* repne */ |
2101 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2102 | { "hlt", { XX }, 0 }, |
2103 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2104 | { REG_TABLE (REG_F6) }, |
2105 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2106 | /* f8 */ |
bf890a93 IT |
2107 | { "clc", { XX }, 0 }, |
2108 | { "stc", { XX }, 0 }, | |
2109 | { "cli", { XX }, 0 }, | |
2110 | { "sti", { XX }, 0 }, | |
2111 | { "cld", { XX }, 0 }, | |
2112 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2113 | { REG_TABLE (REG_FE) }, |
2114 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2115 | }; |
2116 | ||
6439fc28 | 2117 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2118 | /* 00 */ |
1ceb70f8 L |
2119 | { REG_TABLE (REG_0F00 ) }, |
2120 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2121 | { "larS", { Gv, Ew }, 0 }, |
2122 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2123 | { Bad_Opcode }, |
bf890a93 IT |
2124 | { "syscall", { XX }, 0 }, |
2125 | { "clts", { XX }, 0 }, | |
589958d6 | 2126 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2127 | /* 08 */ |
bf890a93 | 2128 | { "invd", { XX }, 0 }, |
3233d7d0 | 2129 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2130 | { Bad_Opcode }, |
bf890a93 | 2131 | { "ud2", { XX }, 0 }, |
592d1631 | 2132 | { Bad_Opcode }, |
b5b1fc4f | 2133 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2134 | { "femms", { XX }, 0 }, |
2135 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2136 | /* 10 */ |
1ceb70f8 L |
2137 | { PREFIX_TABLE (PREFIX_0F10) }, |
2138 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2139 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2140 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2141 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2142 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2143 | { PREFIX_TABLE (PREFIX_0F16) }, |
2144 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2145 | /* 18 */ |
1ceb70f8 | 2146 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2147 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2148 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2149 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2150 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2151 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2152 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2153 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2154 | /* 20 */ |
78467458 JB |
2155 | { "movZ", { Em, Cm }, 0 }, |
2156 | { "movZ", { Em, Dm }, 0 }, | |
2157 | { "movZ", { Cm, Em }, 0 }, | |
2158 | { "movZ", { Dm, Em }, 0 }, | |
2159 | { X86_64_TABLE (X86_64_0F24) }, | |
592d1631 | 2160 | { Bad_Opcode }, |
78467458 | 2161 | { X86_64_TABLE (X86_64_0F26) }, |
592d1631 | 2162 | { Bad_Opcode }, |
252b5132 | 2163 | /* 28 */ |
507bd325 L |
2164 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2165 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2166 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2167 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2168 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2169 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2170 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2171 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2172 | /* 30 */ |
bf890a93 IT |
2173 | { "wrmsr", { XX }, 0 }, |
2174 | { "rdtsc", { XX }, 0 }, | |
2175 | { "rdmsr", { XX }, 0 }, | |
2176 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2177 | { "sysenter", { SEP }, 0 }, |
2178 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2179 | { Bad_Opcode }, |
bf890a93 | 2180 | { "getsec", { XX }, 0 }, |
252b5132 | 2181 | /* 38 */ |
507bd325 | 2182 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2183 | { Bad_Opcode }, |
507bd325 | 2184 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2185 | { Bad_Opcode }, |
2186 | { Bad_Opcode }, | |
2187 | { Bad_Opcode }, | |
2188 | { Bad_Opcode }, | |
2189 | { Bad_Opcode }, | |
252b5132 | 2190 | /* 40 */ |
bf890a93 IT |
2191 | { "cmovoS", { Gv, Ev }, 0 }, |
2192 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2193 | { "cmovbS", { Gv, Ev }, 0 }, | |
2194 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2195 | { "cmoveS", { Gv, Ev }, 0 }, | |
2196 | { "cmovneS", { Gv, Ev }, 0 }, | |
2197 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2198 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2199 | /* 48 */ |
bf890a93 IT |
2200 | { "cmovsS", { Gv, Ev }, 0 }, |
2201 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2202 | { "cmovpS", { Gv, Ev }, 0 }, | |
2203 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2204 | { "cmovlS", { Gv, Ev }, 0 }, | |
2205 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2206 | { "cmovleS", { Gv, Ev }, 0 }, | |
2207 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2208 | /* 50 */ |
a5aaedb9 | 2209 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2210 | { PREFIX_TABLE (PREFIX_0F51) }, |
2211 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2212 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2213 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2214 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2215 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2216 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2217 | /* 58 */ |
1ceb70f8 L |
2218 | { PREFIX_TABLE (PREFIX_0F58) }, |
2219 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2220 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2221 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2222 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2223 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2224 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2225 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2226 | /* 60 */ |
1ceb70f8 L |
2227 | { PREFIX_TABLE (PREFIX_0F60) }, |
2228 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2229 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2230 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2231 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2232 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2233 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2234 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2235 | /* 68 */ |
507bd325 L |
2236 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2237 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2238 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2239 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
7531c613 JB |
2240 | { "punpcklqdq", { XM, EXx }, PREFIX_DATA }, |
2241 | { "punpckhqdq", { XM, EXx }, PREFIX_DATA }, | |
507bd325 | 2242 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2243 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2244 | /* 70 */ |
1ceb70f8 L |
2245 | { PREFIX_TABLE (PREFIX_0F70) }, |
2246 | { REG_TABLE (REG_0F71) }, | |
2247 | { REG_TABLE (REG_0F72) }, | |
2248 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2249 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2250 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2251 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2252 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2253 | /* 78 */ |
1ceb70f8 L |
2254 | { PREFIX_TABLE (PREFIX_0F78) }, |
2255 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2256 | { Bad_Opcode }, |
592d1631 | 2257 | { Bad_Opcode }, |
1ceb70f8 L |
2258 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2259 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2260 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2261 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2262 | /* 80 */ |
bf890a93 IT |
2263 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2264 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2265 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2266 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2267 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2268 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2269 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2270 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2271 | /* 88 */ |
bf890a93 IT |
2272 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2273 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2274 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2275 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2276 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2277 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2278 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2279 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2280 | /* 90 */ |
bf890a93 IT |
2281 | { "seto", { Eb }, 0 }, |
2282 | { "setno", { Eb }, 0 }, | |
2283 | { "setb", { Eb }, 0 }, | |
2284 | { "setae", { Eb }, 0 }, | |
2285 | { "sete", { Eb }, 0 }, | |
2286 | { "setne", { Eb }, 0 }, | |
2287 | { "setbe", { Eb }, 0 }, | |
2288 | { "seta", { Eb }, 0 }, | |
252b5132 | 2289 | /* 98 */ |
bf890a93 IT |
2290 | { "sets", { Eb }, 0 }, |
2291 | { "setns", { Eb }, 0 }, | |
2292 | { "setp", { Eb }, 0 }, | |
2293 | { "setnp", { Eb }, 0 }, | |
2294 | { "setl", { Eb }, 0 }, | |
2295 | { "setge", { Eb }, 0 }, | |
2296 | { "setle", { Eb }, 0 }, | |
2297 | { "setg", { Eb }, 0 }, | |
252b5132 | 2298 | /* a0 */ |
36938cab JB |
2299 | { "pushP", { fs }, 0 }, |
2300 | { "popP", { fs }, 0 }, | |
bf890a93 IT |
2301 | { "cpuid", { XX }, 0 }, |
2302 | { "btS", { Ev, Gv }, 0 }, | |
2303 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2304 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2305 | { REG_TABLE (REG_0FA6) }, |
2306 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2307 | /* a8 */ |
36938cab JB |
2308 | { "pushP", { gs }, 0 }, |
2309 | { "popP", { gs }, 0 }, | |
bf890a93 IT |
2310 | { "rsm", { XX }, 0 }, |
2311 | { "btsS", { Evh1, Gv }, 0 }, | |
2312 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2313 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2314 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2315 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2316 | /* b0 */ |
bf890a93 IT |
2317 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2318 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2319 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2320 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2321 | { MOD_TABLE (MOD_0FB4) }, |
2322 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2323 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2324 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2325 | /* b8 */ |
1ceb70f8 | 2326 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2327 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2328 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2329 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2330 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2331 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2332 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2333 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2334 | /* c0 */ |
bf890a93 IT |
2335 | { "xaddB", { Ebh1, Gb }, 0 }, |
2336 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2337 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2338 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2339 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2340 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2341 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2342 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2343 | /* c8 */ |
bf890a93 IT |
2344 | { "bswap", { RMeAX }, 0 }, |
2345 | { "bswap", { RMeCX }, 0 }, | |
2346 | { "bswap", { RMeDX }, 0 }, | |
2347 | { "bswap", { RMeBX }, 0 }, | |
2348 | { "bswap", { RMeSP }, 0 }, | |
2349 | { "bswap", { RMeBP }, 0 }, | |
2350 | { "bswap", { RMeSI }, 0 }, | |
2351 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2352 | /* d0 */ |
1ceb70f8 | 2353 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2354 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2355 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2356 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2357 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2358 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2359 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2360 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2361 | /* d8 */ |
507bd325 L |
2362 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2363 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2364 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2365 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2366 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2367 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2368 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2369 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2370 | /* e0 */ |
507bd325 L |
2371 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2372 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2373 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2374 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2375 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2376 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2377 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2378 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2379 | /* e8 */ |
507bd325 L |
2380 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2381 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2382 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2383 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2384 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2385 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2386 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2387 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2388 | /* f0 */ |
1ceb70f8 | 2389 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2390 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2391 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2392 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2393 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2394 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2395 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2396 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2397 | /* f8 */ |
507bd325 L |
2398 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2399 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2400 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2401 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2402 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2403 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2404 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2405 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2406 | }; |
2407 | ||
2408 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2409 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2410 | /* ------------------------------- */ | |
2411 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2412 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2413 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2414 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2415 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2416 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2417 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2418 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2419 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2420 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2421 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2422 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2423 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2424 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2425 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2426 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2427 | /* ------------------------------- */ | |
2428 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2429 | }; |
2430 | ||
2431 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2432 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2433 | /* ------------------------------- */ | |
252b5132 | 2434 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2435 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2436 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2437 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2438 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2439 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2440 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2441 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2442 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2443 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2444 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2445 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2446 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2447 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2448 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2449 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2450 | /* ------------------------------- */ |
2451 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2452 | }; | |
2453 | ||
252b5132 RH |
2454 | static char obuf[100]; |
2455 | static char *obufp; | |
ea397f5b | 2456 | static char *mnemonicendp; |
252b5132 RH |
2457 | static char scratchbuf[100]; |
2458 | static unsigned char *start_codep; | |
2459 | static unsigned char *insn_codep; | |
2460 | static unsigned char *codep; | |
285ca992 | 2461 | static unsigned char *end_codep; |
f16cd0d5 L |
2462 | static int last_lock_prefix; |
2463 | static int last_repz_prefix; | |
2464 | static int last_repnz_prefix; | |
2465 | static int last_data_prefix; | |
2466 | static int last_addr_prefix; | |
2467 | static int last_rex_prefix; | |
2468 | static int last_seg_prefix; | |
d9949a36 | 2469 | static int fwait_prefix; |
285ca992 L |
2470 | /* The active segment register prefix. */ |
2471 | static int active_seg_prefix; | |
f16cd0d5 L |
2472 | #define MAX_CODE_LENGTH 15 |
2473 | /* We can up to 14 prefixes since the maximum instruction length is | |
2474 | 15bytes. */ | |
2475 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2476 | static disassemble_info *the_info; |
7967e09e L |
2477 | static struct |
2478 | { | |
2479 | int mod; | |
7967e09e | 2480 | int reg; |
484c222e | 2481 | int rm; |
7967e09e L |
2482 | } |
2483 | modrm; | |
4bba6815 | 2484 | static unsigned char need_modrm; |
dfc8cf43 L |
2485 | static struct |
2486 | { | |
2487 | int scale; | |
2488 | int index; | |
2489 | int base; | |
2490 | } | |
2491 | sib; | |
c0f3af97 L |
2492 | static struct |
2493 | { | |
2494 | int register_specifier; | |
2495 | int length; | |
2496 | int prefix; | |
2497 | int w; | |
43234a1e L |
2498 | int evex; |
2499 | int r; | |
2500 | int v; | |
2501 | int mask_register_specifier; | |
2502 | int zeroing; | |
2503 | int ll; | |
2504 | int b; | |
c0f3af97 L |
2505 | } |
2506 | vex; | |
2507 | static unsigned char need_vex; | |
252b5132 | 2508 | |
ea397f5b L |
2509 | struct op |
2510 | { | |
2511 | const char *name; | |
2512 | unsigned int len; | |
2513 | }; | |
2514 | ||
4bba6815 AM |
2515 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2516 | values are stale. Hitting this abort likely indicates that you | |
2517 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2518 | #define MODRM_CHECK if (!need_modrm) abort () | |
2519 | ||
d708bcba AM |
2520 | static const char **names64; |
2521 | static const char **names32; | |
2522 | static const char **names16; | |
2523 | static const char **names8; | |
2524 | static const char **names8rex; | |
2525 | static const char **names_seg; | |
db51cc60 L |
2526 | static const char *index64; |
2527 | static const char *index32; | |
d708bcba | 2528 | static const char **index16; |
7e8b059b | 2529 | static const char **names_bnd; |
d708bcba AM |
2530 | |
2531 | static const char *intel_names64[] = { | |
2532 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2533 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2534 | }; | |
2535 | static const char *intel_names32[] = { | |
2536 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2537 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2538 | }; | |
2539 | static const char *intel_names16[] = { | |
2540 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2541 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2542 | }; | |
2543 | static const char *intel_names8[] = { | |
2544 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2545 | }; | |
2546 | static const char *intel_names8rex[] = { | |
2547 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2548 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2549 | }; | |
2550 | static const char *intel_names_seg[] = { | |
2551 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2552 | }; | |
db51cc60 L |
2553 | static const char *intel_index64 = "riz"; |
2554 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2555 | static const char *intel_index16[] = { |
2556 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2557 | }; | |
2558 | ||
2559 | static const char *att_names64[] = { | |
2560 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2561 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2562 | }; | |
d708bcba AM |
2563 | static const char *att_names32[] = { |
2564 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2565 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2566 | }; |
d708bcba AM |
2567 | static const char *att_names16[] = { |
2568 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2569 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2570 | }; |
d708bcba AM |
2571 | static const char *att_names8[] = { |
2572 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2573 | }; |
d708bcba AM |
2574 | static const char *att_names8rex[] = { |
2575 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2576 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2577 | }; | |
d708bcba AM |
2578 | static const char *att_names_seg[] = { |
2579 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2580 | }; |
db51cc60 L |
2581 | static const char *att_index64 = "%riz"; |
2582 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2583 | static const char *att_index16[] = { |
2584 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2585 | }; |
2586 | ||
b9733481 L |
2587 | static const char **names_mm; |
2588 | static const char *intel_names_mm[] = { | |
2589 | "mm0", "mm1", "mm2", "mm3", | |
2590 | "mm4", "mm5", "mm6", "mm7" | |
2591 | }; | |
2592 | static const char *att_names_mm[] = { | |
2593 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2594 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2595 | }; | |
2596 | ||
7e8b059b L |
2597 | static const char *intel_names_bnd[] = { |
2598 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2599 | }; | |
2600 | ||
2601 | static const char *att_names_bnd[] = { | |
2602 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2603 | }; | |
2604 | ||
b9733481 L |
2605 | static const char **names_xmm; |
2606 | static const char *intel_names_xmm[] = { | |
2607 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2608 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2609 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
2610 | "xmm12", "xmm13", "xmm14", "xmm15", |
2611 | "xmm16", "xmm17", "xmm18", "xmm19", | |
2612 | "xmm20", "xmm21", "xmm22", "xmm23", | |
2613 | "xmm24", "xmm25", "xmm26", "xmm27", | |
2614 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
2615 | }; |
2616 | static const char *att_names_xmm[] = { | |
2617 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2618 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2619 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
2620 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
2621 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
2622 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
2623 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
2624 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
2625 | }; |
2626 | ||
2627 | static const char **names_ymm; | |
2628 | static const char *intel_names_ymm[] = { | |
2629 | "ymm0", "ymm1", "ymm2", "ymm3", | |
2630 | "ymm4", "ymm5", "ymm6", "ymm7", | |
2631 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
2632 | "ymm12", "ymm13", "ymm14", "ymm15", |
2633 | "ymm16", "ymm17", "ymm18", "ymm19", | |
2634 | "ymm20", "ymm21", "ymm22", "ymm23", | |
2635 | "ymm24", "ymm25", "ymm26", "ymm27", | |
2636 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
2637 | }; |
2638 | static const char *att_names_ymm[] = { | |
2639 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
2640 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2641 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
2642 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
2643 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
2644 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
2645 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
2646 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
2647 | }; | |
2648 | ||
2649 | static const char **names_zmm; | |
2650 | static const char *intel_names_zmm[] = { | |
2651 | "zmm0", "zmm1", "zmm2", "zmm3", | |
2652 | "zmm4", "zmm5", "zmm6", "zmm7", | |
2653 | "zmm8", "zmm9", "zmm10", "zmm11", | |
2654 | "zmm12", "zmm13", "zmm14", "zmm15", | |
2655 | "zmm16", "zmm17", "zmm18", "zmm19", | |
2656 | "zmm20", "zmm21", "zmm22", "zmm23", | |
2657 | "zmm24", "zmm25", "zmm26", "zmm27", | |
2658 | "zmm28", "zmm29", "zmm30", "zmm31" | |
2659 | }; | |
2660 | static const char *att_names_zmm[] = { | |
2661 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
2662 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
2663 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
2664 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
2665 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
2666 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
2667 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
2668 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
2669 | }; | |
2670 | ||
260cd341 LC |
2671 | static const char **names_tmm; |
2672 | static const char *intel_names_tmm[] = { | |
2673 | "tmm0", "tmm1", "tmm2", "tmm3", | |
2674 | "tmm4", "tmm5", "tmm6", "tmm7" | |
2675 | }; | |
2676 | static const char *att_names_tmm[] = { | |
2677 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", | |
2678 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
2679 | }; | |
2680 | ||
43234a1e L |
2681 | static const char **names_mask; |
2682 | static const char *intel_names_mask[] = { | |
2683 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
2684 | }; | |
2685 | static const char *att_names_mask[] = { | |
2686 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
2687 | }; | |
2688 | ||
2689 | static const char *names_rounding[] = | |
2690 | { | |
2691 | "{rn-sae}", | |
2692 | "{rd-sae}", | |
2693 | "{ru-sae}", | |
2694 | "{rz-sae}" | |
b9733481 L |
2695 | }; |
2696 | ||
1ceb70f8 L |
2697 | static const struct dis386 reg_table[][8] = { |
2698 | /* REG_80 */ | |
252b5132 | 2699 | { |
bf890a93 IT |
2700 | { "addA", { Ebh1, Ib }, 0 }, |
2701 | { "orA", { Ebh1, Ib }, 0 }, | |
2702 | { "adcA", { Ebh1, Ib }, 0 }, | |
2703 | { "sbbA", { Ebh1, Ib }, 0 }, | |
2704 | { "andA", { Ebh1, Ib }, 0 }, | |
2705 | { "subA", { Ebh1, Ib }, 0 }, | |
2706 | { "xorA", { Ebh1, Ib }, 0 }, | |
2707 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 2708 | }, |
1ceb70f8 | 2709 | /* REG_81 */ |
252b5132 | 2710 | { |
bf890a93 IT |
2711 | { "addQ", { Evh1, Iv }, 0 }, |
2712 | { "orQ", { Evh1, Iv }, 0 }, | |
2713 | { "adcQ", { Evh1, Iv }, 0 }, | |
2714 | { "sbbQ", { Evh1, Iv }, 0 }, | |
2715 | { "andQ", { Evh1, Iv }, 0 }, | |
2716 | { "subQ", { Evh1, Iv }, 0 }, | |
2717 | { "xorQ", { Evh1, Iv }, 0 }, | |
2718 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 2719 | }, |
7148c369 | 2720 | /* REG_83 */ |
252b5132 | 2721 | { |
bf890a93 IT |
2722 | { "addQ", { Evh1, sIb }, 0 }, |
2723 | { "orQ", { Evh1, sIb }, 0 }, | |
2724 | { "adcQ", { Evh1, sIb }, 0 }, | |
2725 | { "sbbQ", { Evh1, sIb }, 0 }, | |
2726 | { "andQ", { Evh1, sIb }, 0 }, | |
2727 | { "subQ", { Evh1, sIb }, 0 }, | |
2728 | { "xorQ", { Evh1, sIb }, 0 }, | |
2729 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 2730 | }, |
1ceb70f8 | 2731 | /* REG_8F */ |
4e7d34a6 | 2732 | { |
36938cab | 2733 | { "pop{P|}", { stackEv }, 0 }, |
c48244a5 | 2734 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
2735 | { Bad_Opcode }, |
2736 | { Bad_Opcode }, | |
2737 | { Bad_Opcode }, | |
f88c9eb0 | 2738 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 2739 | }, |
1ceb70f8 | 2740 | /* REG_C0 */ |
252b5132 | 2741 | { |
bf890a93 IT |
2742 | { "rolA", { Eb, Ib }, 0 }, |
2743 | { "rorA", { Eb, Ib }, 0 }, | |
2744 | { "rclA", { Eb, Ib }, 0 }, | |
2745 | { "rcrA", { Eb, Ib }, 0 }, | |
2746 | { "shlA", { Eb, Ib }, 0 }, | |
2747 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 2748 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 2749 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 2750 | }, |
1ceb70f8 | 2751 | /* REG_C1 */ |
252b5132 | 2752 | { |
bf890a93 IT |
2753 | { "rolQ", { Ev, Ib }, 0 }, |
2754 | { "rorQ", { Ev, Ib }, 0 }, | |
2755 | { "rclQ", { Ev, Ib }, 0 }, | |
2756 | { "rcrQ", { Ev, Ib }, 0 }, | |
2757 | { "shlQ", { Ev, Ib }, 0 }, | |
2758 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 2759 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 2760 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 2761 | }, |
1ceb70f8 | 2762 | /* REG_C6 */ |
4e7d34a6 | 2763 | { |
bf890a93 | 2764 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
2765 | { Bad_Opcode }, |
2766 | { Bad_Opcode }, | |
2767 | { Bad_Opcode }, | |
2768 | { Bad_Opcode }, | |
2769 | { Bad_Opcode }, | |
2770 | { Bad_Opcode }, | |
2771 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 2772 | }, |
1ceb70f8 | 2773 | /* REG_C7 */ |
4e7d34a6 | 2774 | { |
bf890a93 | 2775 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
2776 | { Bad_Opcode }, |
2777 | { Bad_Opcode }, | |
2778 | { Bad_Opcode }, | |
2779 | { Bad_Opcode }, | |
2780 | { Bad_Opcode }, | |
2781 | { Bad_Opcode }, | |
2782 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 2783 | }, |
1ceb70f8 | 2784 | /* REG_D0 */ |
252b5132 | 2785 | { |
bf890a93 IT |
2786 | { "rolA", { Eb, I1 }, 0 }, |
2787 | { "rorA", { Eb, I1 }, 0 }, | |
2788 | { "rclA", { Eb, I1 }, 0 }, | |
2789 | { "rcrA", { Eb, I1 }, 0 }, | |
2790 | { "shlA", { Eb, I1 }, 0 }, | |
2791 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 2792 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 2793 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 2794 | }, |
1ceb70f8 | 2795 | /* REG_D1 */ |
252b5132 | 2796 | { |
bf890a93 IT |
2797 | { "rolQ", { Ev, I1 }, 0 }, |
2798 | { "rorQ", { Ev, I1 }, 0 }, | |
2799 | { "rclQ", { Ev, I1 }, 0 }, | |
2800 | { "rcrQ", { Ev, I1 }, 0 }, | |
2801 | { "shlQ", { Ev, I1 }, 0 }, | |
2802 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 2803 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 2804 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 2805 | }, |
1ceb70f8 | 2806 | /* REG_D2 */ |
252b5132 | 2807 | { |
bf890a93 IT |
2808 | { "rolA", { Eb, CL }, 0 }, |
2809 | { "rorA", { Eb, CL }, 0 }, | |
2810 | { "rclA", { Eb, CL }, 0 }, | |
2811 | { "rcrA", { Eb, CL }, 0 }, | |
2812 | { "shlA", { Eb, CL }, 0 }, | |
2813 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 2814 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 2815 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 2816 | }, |
1ceb70f8 | 2817 | /* REG_D3 */ |
252b5132 | 2818 | { |
bf890a93 IT |
2819 | { "rolQ", { Ev, CL }, 0 }, |
2820 | { "rorQ", { Ev, CL }, 0 }, | |
2821 | { "rclQ", { Ev, CL }, 0 }, | |
2822 | { "rcrQ", { Ev, CL }, 0 }, | |
2823 | { "shlQ", { Ev, CL }, 0 }, | |
2824 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 2825 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 2826 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 2827 | }, |
1ceb70f8 | 2828 | /* REG_F6 */ |
252b5132 | 2829 | { |
bf890a93 | 2830 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 2831 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
2832 | { "notA", { Ebh1 }, 0 }, |
2833 | { "negA", { Ebh1 }, 0 }, | |
2834 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
2835 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
2836 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
2837 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 2838 | }, |
1ceb70f8 | 2839 | /* REG_F7 */ |
252b5132 | 2840 | { |
bf890a93 | 2841 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 2842 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
2843 | { "notQ", { Evh1 }, 0 }, |
2844 | { "negQ", { Evh1 }, 0 }, | |
2845 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
2846 | { "imulQ", { Ev }, 0 }, | |
2847 | { "divQ", { Ev }, 0 }, | |
2848 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 2849 | }, |
1ceb70f8 | 2850 | /* REG_FE */ |
252b5132 | 2851 | { |
bf890a93 IT |
2852 | { "incA", { Ebh1 }, 0 }, |
2853 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 2854 | }, |
1ceb70f8 | 2855 | /* REG_FF */ |
252b5132 | 2856 | { |
bf890a93 IT |
2857 | { "incQ", { Evh1 }, 0 }, |
2858 | { "decQ", { Evh1 }, 0 }, | |
36938cab | 2859 | { "call{@|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 2860 | { MOD_TABLE (MOD_FF_REG_3) }, |
36938cab | 2861 | { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 2862 | { MOD_TABLE (MOD_FF_REG_5) }, |
36938cab | 2863 | { "push{P|}", { stackEv }, 0 }, |
592d1631 | 2864 | { Bad_Opcode }, |
252b5132 | 2865 | }, |
1ceb70f8 | 2866 | /* REG_0F00 */ |
252b5132 | 2867 | { |
bf890a93 IT |
2868 | { "sldtD", { Sv }, 0 }, |
2869 | { "strD", { Sv }, 0 }, | |
2870 | { "lldt", { Ew }, 0 }, | |
2871 | { "ltr", { Ew }, 0 }, | |
2872 | { "verr", { Ew }, 0 }, | |
2873 | { "verw", { Ew }, 0 }, | |
592d1631 L |
2874 | { Bad_Opcode }, |
2875 | { Bad_Opcode }, | |
252b5132 | 2876 | }, |
1ceb70f8 | 2877 | /* REG_0F01 */ |
252b5132 | 2878 | { |
1ceb70f8 L |
2879 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2880 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2881 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2882 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 2883 | { "smswD", { Sv }, 0 }, |
8eab4136 | 2884 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 2885 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 2886 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2887 | }, |
b5b1fc4f | 2888 | /* REG_0F0D */ |
252b5132 | 2889 | { |
bf890a93 IT |
2890 | { "prefetch", { Mb }, 0 }, |
2891 | { "prefetchw", { Mb }, 0 }, | |
2892 | { "prefetchwt1", { Mb }, 0 }, | |
2893 | { "prefetch", { Mb }, 0 }, | |
2894 | { "prefetch", { Mb }, 0 }, | |
2895 | { "prefetch", { Mb }, 0 }, | |
2896 | { "prefetch", { Mb }, 0 }, | |
2897 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 2898 | }, |
1ceb70f8 | 2899 | /* REG_0F18 */ |
252b5132 | 2900 | { |
1ceb70f8 L |
2901 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2902 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2903 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2904 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
2905 | { MOD_TABLE (MOD_0F18_REG_4) }, |
2906 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
2907 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
2908 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 2909 | }, |
f8687e93 | 2910 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
2911 | { |
2912 | { "cldemote", { Mb }, 0 }, | |
2913 | { "nopQ", { Ev }, 0 }, | |
2914 | { "nopQ", { Ev }, 0 }, | |
2915 | { "nopQ", { Ev }, 0 }, | |
2916 | { "nopQ", { Ev }, 0 }, | |
2917 | { "nopQ", { Ev }, 0 }, | |
2918 | { "nopQ", { Ev }, 0 }, | |
2919 | { "nopQ", { Ev }, 0 }, | |
2920 | }, | |
f8687e93 | 2921 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
2922 | { |
2923 | { "nopQ", { Ev }, 0 }, | |
464d2b65 | 2924 | { "rdsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
2925 | { "nopQ", { Ev }, 0 }, |
2926 | { "nopQ", { Ev }, 0 }, | |
2927 | { "nopQ", { Ev }, 0 }, | |
2928 | { "nopQ", { Ev }, 0 }, | |
2929 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 2930 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 2931 | }, |
c4694f17 TG |
2932 | /* REG_0F38D8_PREFIX_1 */ |
2933 | { | |
2934 | { "aesencwide128kl", { M }, 0 }, | |
2935 | { "aesdecwide128kl", { M }, 0 }, | |
2936 | { "aesencwide256kl", { M }, 0 }, | |
2937 | { "aesdecwide256kl", { M }, 0 }, | |
2938 | }, | |
c1fa250a LC |
2939 | /* REG_0F3A0F_PREFIX_1_MOD_3 */ |
2940 | { | |
2941 | { RM_TABLE (RM_0F3A0F_P_1_MOD_3_REG_0) }, | |
2942 | }, | |
1ceb70f8 | 2943 | /* REG_0F71 */ |
a6bd098c | 2944 | { |
592d1631 L |
2945 | { Bad_Opcode }, |
2946 | { Bad_Opcode }, | |
1ceb70f8 | 2947 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 2948 | { Bad_Opcode }, |
1ceb70f8 | 2949 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 2950 | { Bad_Opcode }, |
1ceb70f8 | 2951 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 2952 | }, |
1ceb70f8 | 2953 | /* REG_0F72 */ |
a6bd098c | 2954 | { |
592d1631 L |
2955 | { Bad_Opcode }, |
2956 | { Bad_Opcode }, | |
1ceb70f8 | 2957 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 2958 | { Bad_Opcode }, |
1ceb70f8 | 2959 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 2960 | { Bad_Opcode }, |
1ceb70f8 | 2961 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 2962 | }, |
1ceb70f8 | 2963 | /* REG_0F73 */ |
252b5132 | 2964 | { |
592d1631 L |
2965 | { Bad_Opcode }, |
2966 | { Bad_Opcode }, | |
1ceb70f8 L |
2967 | { MOD_TABLE (MOD_0F73_REG_2) }, |
2968 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
2969 | { Bad_Opcode }, |
2970 | { Bad_Opcode }, | |
1ceb70f8 L |
2971 | { MOD_TABLE (MOD_0F73_REG_6) }, |
2972 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 2973 | }, |
1ceb70f8 | 2974 | /* REG_0FA6 */ |
252b5132 | 2975 | { |
bf890a93 IT |
2976 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
2977 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
2978 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2979 | }, |
1ceb70f8 | 2980 | /* REG_0FA7 */ |
4e7d34a6 | 2981 | { |
bf890a93 IT |
2982 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
2983 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
2984 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
2985 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
2986 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
2987 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2988 | }, |
1ceb70f8 | 2989 | /* REG_0FAE */ |
4e7d34a6 | 2990 | { |
1ceb70f8 L |
2991 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2992 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2993 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2994 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2995 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2996 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2997 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2998 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2999 | }, |
1ceb70f8 | 3000 | /* REG_0FBA */ |
252b5132 | 3001 | { |
592d1631 L |
3002 | { Bad_Opcode }, |
3003 | { Bad_Opcode }, | |
3004 | { Bad_Opcode }, | |
3005 | { Bad_Opcode }, | |
bf890a93 IT |
3006 | { "btQ", { Ev, Ib }, 0 }, |
3007 | { "btsQ", { Evh1, Ib }, 0 }, | |
3008 | { "btrQ", { Evh1, Ib }, 0 }, | |
3009 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3010 | }, |
1ceb70f8 | 3011 | /* REG_0FC7 */ |
c608c12e | 3012 | { |
592d1631 | 3013 | { Bad_Opcode }, |
bf890a93 | 3014 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3015 | { Bad_Opcode }, |
963f3586 IT |
3016 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3017 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3018 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3019 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3020 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3021 | }, |
592a252b | 3022 | /* REG_VEX_0F71 */ |
c0f3af97 | 3023 | { |
592d1631 L |
3024 | { Bad_Opcode }, |
3025 | { Bad_Opcode }, | |
592a252b | 3026 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3027 | { Bad_Opcode }, |
592a252b | 3028 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3029 | { Bad_Opcode }, |
592a252b | 3030 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3031 | }, |
592a252b | 3032 | /* REG_VEX_0F72 */ |
c0f3af97 | 3033 | { |
592d1631 L |
3034 | { Bad_Opcode }, |
3035 | { Bad_Opcode }, | |
592a252b | 3036 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3037 | { Bad_Opcode }, |
592a252b | 3038 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3039 | { Bad_Opcode }, |
592a252b | 3040 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3041 | }, |
592a252b | 3042 | /* REG_VEX_0F73 */ |
c0f3af97 | 3043 | { |
592d1631 L |
3044 | { Bad_Opcode }, |
3045 | { Bad_Opcode }, | |
592a252b L |
3046 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3047 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3048 | { Bad_Opcode }, |
3049 | { Bad_Opcode }, | |
592a252b L |
3050 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3051 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3052 | }, |
592a252b | 3053 | /* REG_VEX_0FAE */ |
c0f3af97 | 3054 | { |
592d1631 L |
3055 | { Bad_Opcode }, |
3056 | { Bad_Opcode }, | |
592a252b L |
3057 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3058 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3059 | }, |
260cd341 LC |
3060 | /* REG_VEX_0F3849_X86_64_P_0_W_0_M_1 */ |
3061 | { | |
3062 | { RM_TABLE (RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0) }, | |
3063 | }, | |
f12dc422 L |
3064 | /* REG_VEX_0F38F3 */ |
3065 | { | |
3066 | { Bad_Opcode }, | |
035e7389 JB |
3067 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1) }, |
3068 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2) }, | |
3069 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3) }, | |
f12dc422 | 3070 | }, |
467bbef0 | 3071 | /* REG_0FXOP_09_01_L_0 */ |
2a2a0f38 QN |
3072 | { |
3073 | { Bad_Opcode }, | |
467bbef0 JB |
3074 | { "blcfill", { VexGdq, Edq }, 0 }, |
3075 | { "blsfill", { VexGdq, Edq }, 0 }, | |
3076 | { "blcs", { VexGdq, Edq }, 0 }, | |
3077 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
3078 | { "blcic", { VexGdq, Edq }, 0 }, | |
3079 | { "blsic", { VexGdq, Edq }, 0 }, | |
3080 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 3081 | }, |
467bbef0 | 3082 | /* REG_0FXOP_09_02_L_0 */ |
2a2a0f38 QN |
3083 | { |
3084 | { Bad_Opcode }, | |
467bbef0 | 3085 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
3086 | { Bad_Opcode }, |
3087 | { Bad_Opcode }, | |
3088 | { Bad_Opcode }, | |
3089 | { Bad_Opcode }, | |
467bbef0 JB |
3090 | { "blci", { VexGdq, Edq }, 0 }, |
3091 | }, | |
3092 | /* REG_0FXOP_09_12_M_1_L_0 */ | |
3093 | { | |
3094 | { "llwpcb", { Edq }, 0 }, | |
3095 | { "slwpcb", { Edq }, 0 }, | |
3096 | }, | |
3097 | /* REG_0FXOP_0A_12_L_0 */ | |
3098 | { | |
3099 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
3100 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 3101 | }, |
ad692897 L |
3102 | |
3103 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3104 | }; |
3105 | ||
1ceb70f8 L |
3106 | static const struct dis386 prefix_table[][4] = { |
3107 | /* PREFIX_90 */ | |
252b5132 | 3108 | { |
bf890a93 IT |
3109 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3110 | { "pause", { XX }, 0 }, | |
3111 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3112 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3113 | }, |
4e7d34a6 | 3114 | |
81d54bb7 CL |
3115 | /* PREFIX_0F01_REG_1_RM_4 */ |
3116 | { | |
3117 | { Bad_Opcode }, | |
3118 | { Bad_Opcode }, | |
3119 | { "tdcall", { Skip_MODRM }, 0 }, | |
3120 | { Bad_Opcode }, | |
3121 | }, | |
3122 | ||
3123 | /* PREFIX_0F01_REG_1_RM_5 */ | |
3124 | { | |
3125 | { Bad_Opcode }, | |
3126 | { Bad_Opcode }, | |
3127 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) }, | |
3128 | { Bad_Opcode }, | |
3129 | }, | |
3130 | ||
3131 | /* PREFIX_0F01_REG_1_RM_6 */ | |
3132 | { | |
3133 | { Bad_Opcode }, | |
3134 | { Bad_Opcode }, | |
3135 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) }, | |
3136 | { Bad_Opcode }, | |
3137 | }, | |
3138 | ||
3139 | /* PREFIX_0F01_REG_1_RM_7 */ | |
3140 | { | |
3141 | { "encls", { Skip_MODRM }, 0 }, | |
3142 | { Bad_Opcode }, | |
3143 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) }, | |
3144 | { Bad_Opcode }, | |
3145 | }, | |
3146 | ||
f9630fa6 | 3147 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3148 | { |
3149 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3150 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3151 | { Bad_Opcode }, |
3152 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3153 | }, |
3154 | ||
f8687e93 | 3155 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3156 | { |
3157 | { Bad_Opcode }, | |
3158 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3159 | }, | |
3160 | ||
f8687e93 | 3161 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3162 | { |
4b27d27c | 3163 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3164 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3165 | { Bad_Opcode }, |
efe30057 | 3166 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3167 | }, |
3168 | ||
3169 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3170 | { | |
3171 | { Bad_Opcode }, | |
3172 | { Bad_Opcode }, | |
3173 | { Bad_Opcode }, | |
3174 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3175 | }, |
3176 | ||
f8687e93 | 3177 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3178 | { |
3179 | { Bad_Opcode }, | |
c2f76402 | 3180 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3181 | }, |
3182 | ||
f64c42a9 LC |
3183 | /* PREFIX_0F01_REG_5_MOD_3_RM_4 */ |
3184 | { | |
3185 | { Bad_Opcode }, | |
3186 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) }, | |
3187 | }, | |
3188 | ||
3189 | /* PREFIX_0F01_REG_5_MOD_3_RM_5 */ | |
3190 | { | |
3191 | { Bad_Opcode }, | |
3192 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) }, | |
3193 | }, | |
3194 | ||
3195 | /* PREFIX_0F01_REG_5_MOD_3_RM_6 */ | |
3196 | { | |
3197 | { "rdpkru", { Skip_MODRM }, 0 }, | |
3198 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) }, | |
3199 | }, | |
3200 | ||
3201 | /* PREFIX_0F01_REG_5_MOD_3_RM_7 */ | |
3202 | { | |
3203 | { "wrpkru", { Skip_MODRM }, 0 }, | |
3204 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) }, | |
3205 | }, | |
3206 | ||
267b8516 JB |
3207 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3208 | { | |
3209 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3210 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3211 | }, |
3212 | ||
3233d7d0 IT |
3213 | /* PREFIX_0F09 */ |
3214 | { | |
3215 | { "wbinvd", { XX }, 0 }, | |
3216 | { "wbnoinvd", { XX }, 0 }, | |
3217 | }, | |
3218 | ||
1ceb70f8 | 3219 | /* PREFIX_0F10 */ |
cc0ec051 | 3220 | { |
507bd325 L |
3221 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3222 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3223 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3224 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3225 | }, |
4e7d34a6 | 3226 | |
1ceb70f8 | 3227 | /* PREFIX_0F11 */ |
30d1c836 | 3228 | { |
507bd325 L |
3229 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3230 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3231 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3232 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3233 | }, |
252b5132 | 3234 | |
1ceb70f8 | 3235 | /* PREFIX_0F12 */ |
c608c12e | 3236 | { |
1ceb70f8 | 3237 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3238 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3239 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3240 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3241 | }, |
4e7d34a6 | 3242 | |
1ceb70f8 | 3243 | /* PREFIX_0F16 */ |
c608c12e | 3244 | { |
1ceb70f8 | 3245 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3246 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3247 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3248 | }, |
4e7d34a6 | 3249 | |
7e8b059b L |
3250 | /* PREFIX_0F1A */ |
3251 | { | |
3252 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3253 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3254 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3255 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3256 | }, |
3257 | ||
3258 | /* PREFIX_0F1B */ | |
3259 | { | |
3260 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3261 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3262 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3263 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3264 | }, |
3265 | ||
c48935d7 IT |
3266 | /* PREFIX_0F1C */ |
3267 | { | |
3268 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3269 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3270 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3271 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3272 | }, | |
3273 | ||
603555e5 L |
3274 | /* PREFIX_0F1E */ |
3275 | { | |
3276 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3277 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3278 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3279 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3280 | }, | |
3281 | ||
1ceb70f8 | 3282 | /* PREFIX_0F2A */ |
c608c12e | 3283 | { |
507bd325 | 3284 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3285 | { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3286 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3287 | { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, |
c608c12e | 3288 | }, |
4e7d34a6 | 3289 | |
1ceb70f8 | 3290 | /* PREFIX_0F2B */ |
c608c12e | 3291 | { |
75c135a8 L |
3292 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3293 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3294 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3295 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3296 | }, |
4e7d34a6 | 3297 | |
1ceb70f8 | 3298 | /* PREFIX_0F2C */ |
c608c12e | 3299 | { |
507bd325 | 3300 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3301 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3302 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3303 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3304 | }, |
4e7d34a6 | 3305 | |
1ceb70f8 | 3306 | /* PREFIX_0F2D */ |
c608c12e | 3307 | { |
507bd325 | 3308 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3309 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3310 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3311 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3312 | }, |
4e7d34a6 | 3313 | |
1ceb70f8 | 3314 | /* PREFIX_0F2E */ |
c608c12e | 3315 | { |
bf890a93 | 3316 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3317 | { Bad_Opcode }, |
bf890a93 | 3318 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3319 | }, |
4e7d34a6 | 3320 | |
1ceb70f8 | 3321 | /* PREFIX_0F2F */ |
c608c12e | 3322 | { |
bf890a93 | 3323 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3324 | { Bad_Opcode }, |
bf890a93 | 3325 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3326 | }, |
4e7d34a6 | 3327 | |
1ceb70f8 | 3328 | /* PREFIX_0F51 */ |
c608c12e | 3329 | { |
507bd325 L |
3330 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3331 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3332 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3333 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3334 | }, |
4e7d34a6 | 3335 | |
1ceb70f8 | 3336 | /* PREFIX_0F52 */ |
c608c12e | 3337 | { |
507bd325 L |
3338 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3339 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3340 | }, |
4e7d34a6 | 3341 | |
1ceb70f8 | 3342 | /* PREFIX_0F53 */ |
c608c12e | 3343 | { |
507bd325 L |
3344 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3345 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3346 | }, |
4e7d34a6 | 3347 | |
1ceb70f8 | 3348 | /* PREFIX_0F58 */ |
c608c12e | 3349 | { |
507bd325 L |
3350 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3351 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3352 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3353 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3354 | }, |
4e7d34a6 | 3355 | |
1ceb70f8 | 3356 | /* PREFIX_0F59 */ |
c608c12e | 3357 | { |
507bd325 L |
3358 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3359 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3360 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3361 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3362 | }, |
4e7d34a6 | 3363 | |
1ceb70f8 | 3364 | /* PREFIX_0F5A */ |
041bd2e0 | 3365 | { |
507bd325 L |
3366 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3367 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3368 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3369 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3370 | }, |
4e7d34a6 | 3371 | |
1ceb70f8 | 3372 | /* PREFIX_0F5B */ |
041bd2e0 | 3373 | { |
507bd325 L |
3374 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3375 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3376 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3377 | }, |
4e7d34a6 | 3378 | |
1ceb70f8 | 3379 | /* PREFIX_0F5C */ |
041bd2e0 | 3380 | { |
507bd325 L |
3381 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3382 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3383 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3384 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3385 | }, |
4e7d34a6 | 3386 | |
1ceb70f8 | 3387 | /* PREFIX_0F5D */ |
041bd2e0 | 3388 | { |
507bd325 L |
3389 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3390 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3391 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3392 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3393 | }, |
4e7d34a6 | 3394 | |
1ceb70f8 | 3395 | /* PREFIX_0F5E */ |
041bd2e0 | 3396 | { |
507bd325 L |
3397 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3398 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3399 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3400 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3401 | }, |
4e7d34a6 | 3402 | |
1ceb70f8 | 3403 | /* PREFIX_0F5F */ |
041bd2e0 | 3404 | { |
507bd325 L |
3405 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3406 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3407 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3408 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3409 | }, |
4e7d34a6 | 3410 | |
1ceb70f8 | 3411 | /* PREFIX_0F60 */ |
041bd2e0 | 3412 | { |
507bd325 | 3413 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3414 | { Bad_Opcode }, |
507bd325 | 3415 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3416 | }, |
4e7d34a6 | 3417 | |
1ceb70f8 | 3418 | /* PREFIX_0F61 */ |
041bd2e0 | 3419 | { |
507bd325 | 3420 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3421 | { Bad_Opcode }, |
507bd325 | 3422 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3423 | }, |
4e7d34a6 | 3424 | |
1ceb70f8 | 3425 | /* PREFIX_0F62 */ |
041bd2e0 | 3426 | { |
507bd325 | 3427 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3428 | { Bad_Opcode }, |
507bd325 | 3429 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3430 | }, |
4e7d34a6 | 3431 | |
1ceb70f8 | 3432 | /* PREFIX_0F6F */ |
ca164297 | 3433 | { |
507bd325 L |
3434 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3435 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3436 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3437 | }, |
4e7d34a6 | 3438 | |
1ceb70f8 | 3439 | /* PREFIX_0F70 */ |
4e7d34a6 | 3440 | { |
507bd325 L |
3441 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3442 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3443 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3444 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3445 | }, |
3446 | ||
1ceb70f8 | 3447 | /* PREFIX_0F78 */ |
4e7d34a6 | 3448 | { |
bf890a93 | 3449 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3450 | { Bad_Opcode }, |
bf890a93 IT |
3451 | {"extrq", { XS, Ib, Ib }, 0 }, |
3452 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3453 | }, |
3454 | ||
1ceb70f8 | 3455 | /* PREFIX_0F79 */ |
4e7d34a6 | 3456 | { |
bf890a93 | 3457 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3458 | { Bad_Opcode }, |
bf890a93 IT |
3459 | {"extrq", { XM, XS }, 0 }, |
3460 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3461 | }, |
3462 | ||
1ceb70f8 | 3463 | /* PREFIX_0F7C */ |
ca164297 | 3464 | { |
592d1631 L |
3465 | { Bad_Opcode }, |
3466 | { Bad_Opcode }, | |
507bd325 L |
3467 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3468 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3469 | }, |
4e7d34a6 | 3470 | |
1ceb70f8 | 3471 | /* PREFIX_0F7D */ |
ca164297 | 3472 | { |
592d1631 L |
3473 | { Bad_Opcode }, |
3474 | { Bad_Opcode }, | |
507bd325 L |
3475 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3476 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3477 | }, |
4e7d34a6 | 3478 | |
1ceb70f8 | 3479 | /* PREFIX_0F7E */ |
ca164297 | 3480 | { |
507bd325 L |
3481 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3482 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3483 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3484 | }, |
4e7d34a6 | 3485 | |
1ceb70f8 | 3486 | /* PREFIX_0F7F */ |
ca164297 | 3487 | { |
507bd325 L |
3488 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3489 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3490 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3491 | }, |
4e7d34a6 | 3492 | |
f8687e93 | 3493 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3494 | { |
3495 | { Bad_Opcode }, | |
bf890a93 | 3496 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3497 | }, |
3498 | ||
f8687e93 | 3499 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3500 | { |
3501 | { Bad_Opcode }, | |
bf890a93 | 3502 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3503 | }, |
3504 | ||
f8687e93 | 3505 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3506 | { |
3507 | { Bad_Opcode }, | |
bf890a93 | 3508 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3509 | }, |
3510 | ||
f8687e93 | 3511 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3512 | { |
3513 | { Bad_Opcode }, | |
bf890a93 | 3514 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3515 | }, |
3516 | ||
f8687e93 | 3517 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3518 | { |
3519 | { "xsave", { FXSAVE }, 0 }, | |
b24d668c | 3520 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3521 | }, |
3522 | ||
f8687e93 | 3523 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3524 | { |
3525 | { Bad_Opcode }, | |
b24d668c | 3526 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3527 | }, |
3528 | ||
f8687e93 | 3529 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3530 | { |
3531 | { "lfence", { Skip_MODRM }, 0 }, | |
464d2b65 | 3532 | { "incsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
3533 | }, |
3534 | ||
f8687e93 | 3535 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3536 | { |
603555e5 L |
3537 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3538 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3539 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3540 | }, |
3541 | ||
f8687e93 | 3542 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3543 | { |
f8687e93 | 3544 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3545 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3546 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3547 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3548 | }, |
3549 | ||
f8687e93 | 3550 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3551 | { |
bf890a93 | 3552 | { "clflush", { Mb }, 0 }, |
963f3586 | 3553 | { Bad_Opcode }, |
bf890a93 | 3554 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3555 | }, |
3556 | ||
1ceb70f8 | 3557 | /* PREFIX_0FB8 */ |
ca164297 | 3558 | { |
592d1631 | 3559 | { Bad_Opcode }, |
bf890a93 | 3560 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3561 | }, |
4e7d34a6 | 3562 | |
f12dc422 L |
3563 | /* PREFIX_0FBC */ |
3564 | { | |
bf890a93 IT |
3565 | { "bsfS", { Gv, Ev }, 0 }, |
3566 | { "tzcntS", { Gv, Ev }, 0 }, | |
3567 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3568 | }, |
3569 | ||
1ceb70f8 | 3570 | /* PREFIX_0FBD */ |
050dfa73 | 3571 | { |
bf890a93 IT |
3572 | { "bsrS", { Gv, Ev }, 0 }, |
3573 | { "lzcntS", { Gv, Ev }, 0 }, | |
3574 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3575 | }, |
3576 | ||
1ceb70f8 | 3577 | /* PREFIX_0FC2 */ |
050dfa73 | 3578 | { |
507bd325 L |
3579 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3580 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3581 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3582 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3583 | }, |
246c51aa | 3584 | |
f8687e93 | 3585 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3586 | { |
bf890a93 IT |
3587 | { "vmptrld",{ Mq }, 0 }, |
3588 | { "vmxon", { Mq }, 0 }, | |
3589 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3590 | }, |
3591 | ||
f8687e93 | 3592 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3593 | { |
3594 | { "rdrand", { Ev }, 0 }, | |
f64c42a9 | 3595 | { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) }, |
f24bcbaa L |
3596 | { "rdrand", { Ev }, 0 } |
3597 | }, | |
3598 | ||
f8687e93 | 3599 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3600 | { |
3601 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3602 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3603 | { "rdseed", { Ev }, 0 }, |
3604 | }, | |
3605 | ||
1ceb70f8 | 3606 | /* PREFIX_0FD0 */ |
050dfa73 | 3607 | { |
592d1631 L |
3608 | { Bad_Opcode }, |
3609 | { Bad_Opcode }, | |
bf890a93 IT |
3610 | { "addsubpd", { XM, EXx }, 0 }, |
3611 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3612 | }, |
050dfa73 | 3613 | |
1ceb70f8 | 3614 | /* PREFIX_0FD6 */ |
050dfa73 | 3615 | { |
592d1631 | 3616 | { Bad_Opcode }, |
bf890a93 IT |
3617 | { "movq2dq",{ XM, MS }, 0 }, |
3618 | { "movq", { EXqS, XM }, 0 }, | |
3619 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3620 | }, |
3621 | ||
1ceb70f8 | 3622 | /* PREFIX_0FE6 */ |
7918206c | 3623 | { |
592d1631 | 3624 | { Bad_Opcode }, |
507bd325 L |
3625 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3626 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3627 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3628 | }, |
8b38ad71 | 3629 | |
1ceb70f8 | 3630 | /* PREFIX_0FE7 */ |
8b38ad71 | 3631 | { |
507bd325 | 3632 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3633 | { Bad_Opcode }, |
75c135a8 | 3634 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3635 | }, |
3636 | ||
1ceb70f8 | 3637 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3638 | { |
592d1631 L |
3639 | { Bad_Opcode }, |
3640 | { Bad_Opcode }, | |
3641 | { Bad_Opcode }, | |
1ceb70f8 | 3642 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3643 | }, |
3644 | ||
1ceb70f8 | 3645 | /* PREFIX_0FF7 */ |
4e7d34a6 | 3646 | { |
507bd325 | 3647 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 3648 | { Bad_Opcode }, |
507bd325 | 3649 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 3650 | }, |
42903f7f | 3651 | |
c4694f17 TG |
3652 | /* PREFIX_0F38D8 */ |
3653 | { | |
3654 | { Bad_Opcode }, | |
3655 | { REG_TABLE (REG_0F38D8_PREFIX_1) }, | |
3656 | }, | |
3657 | ||
3658 | /* PREFIX_0F38DC */ | |
3659 | { | |
3660 | { Bad_Opcode }, | |
3661 | { MOD_TABLE (MOD_0F38DC_PREFIX_1) }, | |
3662 | { "aesenc", { XM, EXx }, 0 }, | |
3663 | }, | |
3664 | ||
3665 | /* PREFIX_0F38DD */ | |
3666 | { | |
3667 | { Bad_Opcode }, | |
3668 | { MOD_TABLE (MOD_0F38DD_PREFIX_1) }, | |
3669 | { "aesenclast", { XM, EXx }, 0 }, | |
3670 | }, | |
3671 | ||
3672 | /* PREFIX_0F38DE */ | |
3673 | { | |
3674 | { Bad_Opcode }, | |
3675 | { MOD_TABLE (MOD_0F38DE_PREFIX_1) }, | |
3676 | { "aesdec", { XM, EXx }, 0 }, | |
3677 | }, | |
3678 | ||
3679 | /* PREFIX_0F38DF */ | |
3680 | { | |
3681 | { Bad_Opcode }, | |
3682 | { MOD_TABLE (MOD_0F38DF_PREFIX_1) }, | |
3683 | { "aesdeclast", { XM, EXx }, 0 }, | |
3684 | }, | |
3685 | ||
1ceb70f8 | 3686 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3687 | { |
9ab00b61 | 3688 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
592d1631 | 3689 | { Bad_Opcode }, |
9ab00b61 | 3690 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
2875b28a | 3691 | { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, |
4e7d34a6 L |
3692 | }, |
3693 | ||
1ceb70f8 | 3694 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3695 | { |
9ab00b61 | 3696 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
592d1631 | 3697 | { Bad_Opcode }, |
9ab00b61 | 3698 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
2875b28a | 3699 | { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, |
4e7d34a6 L |
3700 | }, |
3701 | ||
603555e5 L |
3702 | /* PREFIX_0F38F6 */ |
3703 | { | |
3704 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
3705 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
3706 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
3707 | { Bad_Opcode }, |
3708 | }, | |
3709 | ||
c0a30a9f L |
3710 | /* PREFIX_0F38F8 */ |
3711 | { | |
3712 | { Bad_Opcode }, | |
5d79adc4 | 3713 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 3714 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 3715 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f | 3716 | }, |
c4694f17 TG |
3717 | /* PREFIX_0F38FA */ |
3718 | { | |
3719 | { Bad_Opcode }, | |
3720 | { MOD_TABLE (MOD_0F38FA_PREFIX_1) }, | |
3721 | }, | |
3722 | ||
3723 | /* PREFIX_0F38FB */ | |
3724 | { | |
3725 | { Bad_Opcode }, | |
3726 | { MOD_TABLE (MOD_0F38FB_PREFIX_1) }, | |
3727 | }, | |
c0a30a9f | 3728 | |
c1fa250a LC |
3729 | /* PREFIX_0F3A0F */ |
3730 | { | |
3731 | { Bad_Opcode }, | |
3732 | { MOD_TABLE (MOD_0F3A0F_PREFIX_1)}, | |
3733 | }, | |
3734 | ||
7531c613 | 3735 | /* PREFIX_VEX_0F10 */ |
42903f7f | 3736 | { |
7531c613 JB |
3737 | { "vmovups", { XM, EXx }, 0 }, |
3738 | { "vmovss", { XMScalar, VexScalarR, EXxmm_md }, 0 }, | |
3739 | { "vmovupd", { XM, EXx }, 0 }, | |
3740 | { "vmovsd", { XMScalar, VexScalarR, EXxmm_mq }, 0 }, | |
42903f7f L |
3741 | }, |
3742 | ||
7531c613 | 3743 | /* PREFIX_VEX_0F11 */ |
42903f7f | 3744 | { |
7531c613 JB |
3745 | { "vmovups", { EXxS, XM }, 0 }, |
3746 | { "vmovss", { EXdS, VexScalarR, XMScalar }, 0 }, | |
3747 | { "vmovupd", { EXxS, XM }, 0 }, | |
3748 | { "vmovsd", { EXqS, VexScalarR, XMScalar }, 0 }, | |
42903f7f L |
3749 | }, |
3750 | ||
7531c613 | 3751 | /* PREFIX_VEX_0F12 */ |
42903f7f | 3752 | { |
7531c613 JB |
3753 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
3754 | { "vmovsldup", { XM, EXx }, 0 }, | |
3755 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, | |
3756 | { "vmovddup", { XM, EXymmq }, 0 }, | |
42903f7f L |
3757 | }, |
3758 | ||
7531c613 | 3759 | /* PREFIX_VEX_0F16 */ |
42903f7f | 3760 | { |
7531c613 JB |
3761 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
3762 | { "vmovshdup", { XM, EXx }, 0 }, | |
3763 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, | |
5f754f58 | 3764 | }, |
7c52e0e8 | 3765 | |
592a252b | 3766 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 3767 | { |
592d1631 | 3768 | { Bad_Opcode }, |
b24d668c | 3769 | { "vcvtsi2ss{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 3770 | { Bad_Opcode }, |
b24d668c | 3771 | { "vcvtsi2sd{%LQ|}", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 3772 | }, |
7c52e0e8 | 3773 | |
592a252b | 3774 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 3775 | { |
592d1631 | 3776 | { Bad_Opcode }, |
17d3c7ec | 3777 | { "vcvttss2si", { Gdq, EXxmm_md, EXxEVexS }, 0 }, |
592d1631 | 3778 | { Bad_Opcode }, |
17d3c7ec | 3779 | { "vcvttsd2si", { Gdq, EXxmm_mq, EXxEVexS }, 0 }, |
5f754f58 | 3780 | }, |
7c52e0e8 | 3781 | |
592a252b | 3782 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 3783 | { |
592d1631 | 3784 | { Bad_Opcode }, |
17d3c7ec | 3785 | { "vcvtss2si", { Gdq, EXxmm_md, EXxEVexR }, 0 }, |
592d1631 | 3786 | { Bad_Opcode }, |
17d3c7ec | 3787 | { "vcvtsd2si", { Gdq, EXxmm_mq, EXxEVexR }, 0 }, |
7c52e0e8 L |
3788 | }, |
3789 | ||
592a252b | 3790 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 3791 | { |
17d3c7ec | 3792 | { "vucomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 3793 | { Bad_Opcode }, |
17d3c7ec | 3794 | { "vucomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
3795 | }, |
3796 | ||
592a252b | 3797 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 3798 | { |
17d3c7ec | 3799 | { "vcomisX", { XMScalar, EXxmm_md, EXxEVexS }, PREFIX_OPCODE }, |
592d1631 | 3800 | { Bad_Opcode }, |
17d3c7ec | 3801 | { "vcomisX", { XMScalar, EXxmm_mq, EXxEVexS }, PREFIX_OPCODE }, |
7c52e0e8 L |
3802 | }, |
3803 | ||
43234a1e L |
3804 | /* PREFIX_VEX_0F41 */ |
3805 | { | |
3806 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
3807 | { Bad_Opcode }, |
3808 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
3809 | }, |
3810 | ||
3811 | /* PREFIX_VEX_0F42 */ | |
3812 | { | |
3813 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
3814 | { Bad_Opcode }, |
3815 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
3816 | }, |
3817 | ||
7531c613 | 3818 | /* PREFIX_VEX_0F44 */ |
c0f3af97 | 3819 | { |
7531c613 | 3820 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, |
592d1631 | 3821 | { Bad_Opcode }, |
7531c613 | 3822 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, |
c0f3af97 L |
3823 | }, |
3824 | ||
7531c613 | 3825 | /* PREFIX_VEX_0F45 */ |
0bfee649 | 3826 | { |
7531c613 | 3827 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, |
592d1631 | 3828 | { Bad_Opcode }, |
7531c613 | 3829 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, |
0bfee649 L |
3830 | }, |
3831 | ||
7531c613 | 3832 | /* PREFIX_VEX_0F46 */ |
43234a1e | 3833 | { |
7531c613 | 3834 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, |
43234a1e | 3835 | { Bad_Opcode }, |
7531c613 | 3836 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, |
43234a1e L |
3837 | }, |
3838 | ||
7531c613 | 3839 | /* PREFIX_VEX_0F47 */ |
1ba585e8 | 3840 | { |
7531c613 | 3841 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, |
1ba585e8 | 3842 | { Bad_Opcode }, |
7531c613 | 3843 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, |
1ba585e8 IT |
3844 | }, |
3845 | ||
7531c613 | 3846 | /* PREFIX_VEX_0F4A */ |
43234a1e | 3847 | { |
7531c613 | 3848 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 3849 | { Bad_Opcode }, |
7531c613 | 3850 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
43234a1e L |
3851 | }, |
3852 | ||
7531c613 | 3853 | /* PREFIX_VEX_0F4B */ |
1ba585e8 | 3854 | { |
7531c613 | 3855 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, |
1ba585e8 | 3856 | { Bad_Opcode }, |
7531c613 | 3857 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, |
1ba585e8 IT |
3858 | }, |
3859 | ||
7531c613 | 3860 | /* PREFIX_VEX_0F51 */ |
6c30d220 | 3861 | { |
7531c613 JB |
3862 | { "vsqrtps", { XM, EXx }, 0 }, |
3863 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3864 | { "vsqrtpd", { XM, EXx }, 0 }, | |
3865 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
6c30d220 L |
3866 | }, |
3867 | ||
7531c613 | 3868 | /* PREFIX_VEX_0F52 */ |
6c30d220 | 3869 | { |
7531c613 JB |
3870 | { "vrsqrtps", { XM, EXx }, 0 }, |
3871 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
6c30d220 L |
3872 | }, |
3873 | ||
7531c613 | 3874 | /* PREFIX_VEX_0F53 */ |
c0f3af97 | 3875 | { |
7531c613 JB |
3876 | { "vrcpps", { XM, EXx }, 0 }, |
3877 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
c0f3af97 L |
3878 | }, |
3879 | ||
7531c613 | 3880 | /* PREFIX_VEX_0F58 */ |
c0f3af97 | 3881 | { |
7531c613 JB |
3882 | { "vaddps", { XM, Vex, EXx }, 0 }, |
3883 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3884 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
3885 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3886 | }, |
3887 | ||
7531c613 | 3888 | /* PREFIX_VEX_0F59 */ |
c0f3af97 | 3889 | { |
7531c613 JB |
3890 | { "vmulps", { XM, Vex, EXx }, 0 }, |
3891 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3892 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
3893 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3894 | }, |
3895 | ||
7531c613 | 3896 | /* PREFIX_VEX_0F5A */ |
ce2f5b3c | 3897 | { |
7531c613 JB |
3898 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
3899 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3900 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
3901 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
ce2f5b3c L |
3902 | }, |
3903 | ||
7531c613 | 3904 | /* PREFIX_VEX_0F5B */ |
6c30d220 | 3905 | { |
7531c613 JB |
3906 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
3907 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
3908 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
6c30d220 L |
3909 | }, |
3910 | ||
7531c613 | 3911 | /* PREFIX_VEX_0F5C */ |
a683cc34 | 3912 | { |
7531c613 JB |
3913 | { "vsubps", { XM, Vex, EXx }, 0 }, |
3914 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3915 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
3916 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
a683cc34 SP |
3917 | }, |
3918 | ||
7531c613 | 3919 | /* PREFIX_VEX_0F5D */ |
a683cc34 | 3920 | { |
7531c613 JB |
3921 | { "vminps", { XM, Vex, EXx }, 0 }, |
3922 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3923 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
3924 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
a683cc34 SP |
3925 | }, |
3926 | ||
7531c613 | 3927 | /* PREFIX_VEX_0F5E */ |
c0f3af97 | 3928 | { |
7531c613 JB |
3929 | { "vdivps", { XM, Vex, EXx }, 0 }, |
3930 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3931 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
3932 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3933 | }, |
3934 | ||
7531c613 | 3935 | /* PREFIX_VEX_0F5F */ |
c0f3af97 | 3936 | { |
7531c613 JB |
3937 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
3938 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, | |
3939 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
3940 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, | |
c0f3af97 L |
3941 | }, |
3942 | ||
7531c613 | 3943 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 3944 | { |
592d1631 | 3945 | { Bad_Opcode }, |
7531c613 JB |
3946 | { "vmovdqu", { XM, EXx }, 0 }, |
3947 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
3948 | }, |
3949 | ||
7531c613 | 3950 | /* PREFIX_VEX_0F70 */ |
922d8de8 | 3951 | { |
592d1631 | 3952 | { Bad_Opcode }, |
7531c613 JB |
3953 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
3954 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
3955 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
922d8de8 DR |
3956 | }, |
3957 | ||
7531c613 | 3958 | /* PREFIX_VEX_0F7C */ |
922d8de8 | 3959 | { |
592d1631 L |
3960 | { Bad_Opcode }, |
3961 | { Bad_Opcode }, | |
7531c613 JB |
3962 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
3963 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3964 | }, |
3965 | ||
7531c613 | 3966 | /* PREFIX_VEX_0F7D */ |
922d8de8 | 3967 | { |
592d1631 L |
3968 | { Bad_Opcode }, |
3969 | { Bad_Opcode }, | |
7531c613 JB |
3970 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
3971 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
3972 | }, |
3973 | ||
7531c613 | 3974 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 3975 | { |
592d1631 | 3976 | { Bad_Opcode }, |
7531c613 JB |
3977 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
3978 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
3979 | }, |
3980 | ||
7531c613 | 3981 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 3982 | { |
592d1631 | 3983 | { Bad_Opcode }, |
7531c613 JB |
3984 | { "vmovdqu", { EXxS, XM }, 0 }, |
3985 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
3986 | }, |
3987 | ||
7531c613 | 3988 | /* PREFIX_VEX_0F90 */ |
c0f3af97 | 3989 | { |
7531c613 | 3990 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, |
592d1631 | 3991 | { Bad_Opcode }, |
7531c613 | 3992 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, |
c0f3af97 L |
3993 | }, |
3994 | ||
7531c613 | 3995 | /* PREFIX_VEX_0F91 */ |
c0f3af97 | 3996 | { |
7531c613 | 3997 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, |
592d1631 | 3998 | { Bad_Opcode }, |
7531c613 | 3999 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, |
c0f3af97 | 4000 | }, |
a5ff0eb2 | 4001 | |
7531c613 | 4002 | /* PREFIX_VEX_0F92 */ |
922d8de8 | 4003 | { |
7531c613 | 4004 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, |
592d1631 | 4005 | { Bad_Opcode }, |
7531c613 JB |
4006 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
4007 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, | |
922d8de8 DR |
4008 | }, |
4009 | ||
7531c613 | 4010 | /* PREFIX_VEX_0F93 */ |
922d8de8 | 4011 | { |
7531c613 | 4012 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, |
592d1631 | 4013 | { Bad_Opcode }, |
7531c613 JB |
4014 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
4015 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, | |
922d8de8 DR |
4016 | }, |
4017 | ||
7531c613 | 4018 | /* PREFIX_VEX_0F98 */ |
922d8de8 | 4019 | { |
7531c613 | 4020 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, |
592d1631 | 4021 | { Bad_Opcode }, |
7531c613 | 4022 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, |
922d8de8 DR |
4023 | }, |
4024 | ||
7531c613 | 4025 | /* PREFIX_VEX_0F99 */ |
922d8de8 | 4026 | { |
7531c613 | 4027 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, |
592d1631 | 4028 | { Bad_Opcode }, |
7531c613 | 4029 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, |
922d8de8 DR |
4030 | }, |
4031 | ||
7531c613 | 4032 | /* PREFIX_VEX_0FC2 */ |
922d8de8 | 4033 | { |
7531c613 JB |
4034 | { "vcmpps", { XM, Vex, EXx, CMP }, 0 }, |
4035 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, CMP }, 0 }, | |
4036 | { "vcmppd", { XM, Vex, EXx, CMP }, 0 }, | |
4037 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, CMP }, 0 }, | |
922d8de8 DR |
4038 | }, |
4039 | ||
7531c613 | 4040 | /* PREFIX_VEX_0FD0 */ |
922d8de8 | 4041 | { |
592d1631 L |
4042 | { Bad_Opcode }, |
4043 | { Bad_Opcode }, | |
7531c613 JB |
4044 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
4045 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
922d8de8 DR |
4046 | }, |
4047 | ||
7531c613 | 4048 | /* PREFIX_VEX_0FE6 */ |
922d8de8 | 4049 | { |
592d1631 | 4050 | { Bad_Opcode }, |
7531c613 JB |
4051 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
4052 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
4053 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
922d8de8 DR |
4054 | }, |
4055 | ||
7531c613 | 4056 | /* PREFIX_VEX_0FF0 */ |
922d8de8 | 4057 | { |
592d1631 L |
4058 | { Bad_Opcode }, |
4059 | { Bad_Opcode }, | |
7531c613 JB |
4060 | { Bad_Opcode }, |
4061 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, | |
922d8de8 DR |
4062 | }, |
4063 | ||
7531c613 | 4064 | /* PREFIX_VEX_0F3849_X86_64 */ |
922d8de8 | 4065 | { |
7531c613 | 4066 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_0) }, |
592d1631 | 4067 | { Bad_Opcode }, |
7531c613 JB |
4068 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_2) }, |
4069 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_P_3) }, | |
922d8de8 DR |
4070 | }, |
4071 | ||
7531c613 | 4072 | /* PREFIX_VEX_0F384B_X86_64 */ |
922d8de8 | 4073 | { |
592d1631 | 4074 | { Bad_Opcode }, |
7531c613 JB |
4075 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_1) }, |
4076 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_2) }, | |
4077 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_P_3) }, | |
922d8de8 DR |
4078 | }, |
4079 | ||
7531c613 | 4080 | /* PREFIX_VEX_0F385C_X86_64 */ |
922d8de8 | 4081 | { |
592d1631 | 4082 | { Bad_Opcode }, |
7531c613 | 4083 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_P_1) }, |
592d1631 | 4084 | { Bad_Opcode }, |
922d8de8 DR |
4085 | }, |
4086 | ||
7531c613 | 4087 | /* PREFIX_VEX_0F385E_X86_64 */ |
922d8de8 | 4088 | { |
7531c613 JB |
4089 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_0) }, |
4090 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_1) }, | |
4091 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_2) }, | |
4092 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_P_3) }, | |
922d8de8 DR |
4093 | }, |
4094 | ||
7531c613 | 4095 | /* PREFIX_VEX_0F38F5 */ |
48521003 | 4096 | { |
7531c613 JB |
4097 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, |
4098 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
48521003 | 4099 | { Bad_Opcode }, |
7531c613 | 4100 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, |
48521003 IT |
4101 | }, |
4102 | ||
7531c613 | 4103 | /* PREFIX_VEX_0F38F6 */ |
48521003 IT |
4104 | { |
4105 | { Bad_Opcode }, | |
4106 | { Bad_Opcode }, | |
7531c613 JB |
4107 | { Bad_Opcode }, |
4108 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
48521003 IT |
4109 | }, |
4110 | ||
7531c613 | 4111 | /* PREFIX_VEX_0F38F7 */ |
a5ff0eb2 | 4112 | { |
7531c613 JB |
4113 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, |
4114 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, | |
4115 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
4116 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
a5ff0eb2 | 4117 | }, |
6c30d220 L |
4118 | |
4119 | /* PREFIX_VEX_0F3AF0 */ | |
4120 | { | |
4121 | { Bad_Opcode }, | |
4122 | { Bad_Opcode }, | |
4123 | { Bad_Opcode }, | |
4124 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
4125 | }, | |
43234a1e | 4126 | |
ad692897 | 4127 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
4128 | }; |
4129 | ||
4130 | static const struct dis386 x86_64_table[][2] = { | |
4131 | /* X86_64_06 */ | |
4132 | { | |
bf890a93 | 4133 | { "pushP", { es }, 0 }, |
c0f3af97 L |
4134 | }, |
4135 | ||
4136 | /* X86_64_07 */ | |
4137 | { | |
bf890a93 | 4138 | { "popP", { es }, 0 }, |
c0f3af97 L |
4139 | }, |
4140 | ||
1673df32 | 4141 | /* X86_64_0E */ |
c0f3af97 | 4142 | { |
bf890a93 | 4143 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
4144 | }, |
4145 | ||
4146 | /* X86_64_16 */ | |
4147 | { | |
bf890a93 | 4148 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
4149 | }, |
4150 | ||
4151 | /* X86_64_17 */ | |
4152 | { | |
bf890a93 | 4153 | { "popP", { ss }, 0 }, |
c0f3af97 L |
4154 | }, |
4155 | ||
4156 | /* X86_64_1E */ | |
4157 | { | |
bf890a93 | 4158 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
4159 | }, |
4160 | ||
4161 | /* X86_64_1F */ | |
4162 | { | |
bf890a93 | 4163 | { "popP", { ds }, 0 }, |
c0f3af97 L |
4164 | }, |
4165 | ||
4166 | /* X86_64_27 */ | |
4167 | { | |
bf890a93 | 4168 | { "daa", { XX }, 0 }, |
c0f3af97 L |
4169 | }, |
4170 | ||
4171 | /* X86_64_2F */ | |
4172 | { | |
bf890a93 | 4173 | { "das", { XX }, 0 }, |
c0f3af97 L |
4174 | }, |
4175 | ||
4176 | /* X86_64_37 */ | |
4177 | { | |
bf890a93 | 4178 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
4179 | }, |
4180 | ||
4181 | /* X86_64_3F */ | |
4182 | { | |
bf890a93 | 4183 | { "aas", { XX }, 0 }, |
c0f3af97 L |
4184 | }, |
4185 | ||
4186 | /* X86_64_60 */ | |
4187 | { | |
bf890a93 | 4188 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
4189 | }, |
4190 | ||
4191 | /* X86_64_61 */ | |
4192 | { | |
bf890a93 | 4193 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
4194 | }, |
4195 | ||
4196 | /* X86_64_62 */ | |
4197 | { | |
4198 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 4199 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
4200 | }, |
4201 | ||
4202 | /* X86_64_63 */ | |
4203 | { | |
bf890a93 | 4204 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 4205 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
4206 | }, |
4207 | ||
4208 | /* X86_64_6D */ | |
4209 | { | |
bf890a93 IT |
4210 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
4211 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
4212 | }, |
4213 | ||
4214 | /* X86_64_6F */ | |
4215 | { | |
bf890a93 IT |
4216 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
4217 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
4218 | }, |
4219 | ||
d039fef3 | 4220 | /* X86_64_82 */ |
8b89fe14 | 4221 | { |
de194d85 | 4222 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 4223 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
4224 | }, |
4225 | ||
c0f3af97 L |
4226 | /* X86_64_9A */ |
4227 | { | |
36938cab | 4228 | { "{l|}call{P|}", { Ap }, 0 }, |
c0f3af97 L |
4229 | }, |
4230 | ||
aeab2b26 JB |
4231 | /* X86_64_C2 */ |
4232 | { | |
4233 | { "retP", { Iw, BND }, 0 }, | |
4234 | { "ret@", { Iw, BND }, 0 }, | |
4235 | }, | |
4236 | ||
4237 | /* X86_64_C3 */ | |
4238 | { | |
4239 | { "retP", { BND }, 0 }, | |
4240 | { "ret@", { BND }, 0 }, | |
4241 | }, | |
4242 | ||
c0f3af97 L |
4243 | /* X86_64_C4 */ |
4244 | { | |
4245 | { MOD_TABLE (MOD_C4_32BIT) }, | |
4246 | { VEX_C4_TABLE (VEX_0F) }, | |
4247 | }, | |
4248 | ||
4249 | /* X86_64_C5 */ | |
4250 | { | |
4251 | { MOD_TABLE (MOD_C5_32BIT) }, | |
4252 | { VEX_C5_TABLE (VEX_0F) }, | |
4253 | }, | |
4254 | ||
4255 | /* X86_64_CE */ | |
4256 | { | |
bf890a93 | 4257 | { "into", { XX }, 0 }, |
c0f3af97 L |
4258 | }, |
4259 | ||
4260 | /* X86_64_D4 */ | |
4261 | { | |
bf890a93 | 4262 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
4263 | }, |
4264 | ||
4265 | /* X86_64_D5 */ | |
4266 | { | |
bf890a93 | 4267 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
4268 | }, |
4269 | ||
a72d2af2 L |
4270 | /* X86_64_E8 */ |
4271 | { | |
4272 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 4273 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
4274 | }, |
4275 | ||
4276 | /* X86_64_E9 */ | |
4277 | { | |
4278 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 4279 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
4280 | }, |
4281 | ||
c0f3af97 L |
4282 | /* X86_64_EA */ |
4283 | { | |
36938cab | 4284 | { "{l|}jmp{P|}", { Ap }, 0 }, |
c0f3af97 L |
4285 | }, |
4286 | ||
4287 | /* X86_64_0F01_REG_0 */ | |
4288 | { | |
d1c36125 | 4289 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 4290 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
4291 | }, |
4292 | ||
4293 | /* X86_64_0F01_REG_1 */ | |
4294 | { | |
d1c36125 | 4295 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 4296 | { "sidt", { M }, 0 }, |
c0f3af97 L |
4297 | }, |
4298 | ||
81d54bb7 CL |
4299 | /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ |
4300 | { | |
4301 | { Bad_Opcode }, | |
4302 | { "seamret", { Skip_MODRM }, 0 }, | |
4303 | }, | |
4304 | ||
4305 | /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */ | |
4306 | { | |
4307 | { Bad_Opcode }, | |
4308 | { "seamops", { Skip_MODRM }, 0 }, | |
4309 | }, | |
4310 | ||
4311 | /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */ | |
4312 | { | |
4313 | { Bad_Opcode }, | |
4314 | { "seamcall", { Skip_MODRM }, 0 }, | |
4315 | }, | |
4316 | ||
c0f3af97 L |
4317 | /* X86_64_0F01_REG_2 */ |
4318 | { | |
bf890a93 IT |
4319 | { "lgdt{Q|Q}", { M }, 0 }, |
4320 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
4321 | }, |
4322 | ||
4323 | /* X86_64_0F01_REG_3 */ | |
4324 | { | |
bf890a93 IT |
4325 | { "lidt{Q|Q}", { M }, 0 }, |
4326 | { "lidt", { M }, 0 }, | |
c0f3af97 | 4327 | }, |
260cd341 | 4328 | |
78467458 JB |
4329 | { |
4330 | /* X86_64_0F24 */ | |
4331 | { "movZ", { Em, Td }, 0 }, | |
4332 | }, | |
4333 | ||
4334 | { | |
4335 | /* X86_64_0F26 */ | |
4336 | { "movZ", { Td, Em }, 0 }, | |
4337 | }, | |
4338 | ||
260cd341 LC |
4339 | /* X86_64_VEX_0F3849 */ |
4340 | { | |
4341 | { Bad_Opcode }, | |
4342 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64) }, | |
4343 | }, | |
4344 | ||
4345 | /* X86_64_VEX_0F384B */ | |
4346 | { | |
4347 | { Bad_Opcode }, | |
4348 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64) }, | |
4349 | }, | |
4350 | ||
4351 | /* X86_64_VEX_0F385C */ | |
4352 | { | |
4353 | { Bad_Opcode }, | |
4354 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64) }, | |
4355 | }, | |
4356 | ||
4357 | /* X86_64_VEX_0F385E */ | |
4358 | { | |
4359 | { Bad_Opcode }, | |
4360 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64) }, | |
4361 | }, | |
f64c42a9 LC |
4362 | |
4363 | /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */ | |
4364 | { | |
4365 | { Bad_Opcode }, | |
4366 | { "uiret", { Skip_MODRM }, 0 }, | |
4367 | }, | |
4368 | ||
4369 | /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */ | |
4370 | { | |
4371 | { Bad_Opcode }, | |
4372 | { "testui", { Skip_MODRM }, 0 }, | |
4373 | }, | |
4374 | ||
4375 | /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */ | |
4376 | { | |
4377 | { Bad_Opcode }, | |
4378 | { "clui", { Skip_MODRM }, 0 }, | |
4379 | }, | |
4380 | ||
4381 | /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */ | |
4382 | { | |
4383 | { Bad_Opcode }, | |
4384 | { "stui", { Skip_MODRM }, 0 }, | |
4385 | }, | |
4386 | ||
4387 | /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ | |
4388 | { | |
4389 | { Bad_Opcode }, | |
4390 | { "senduipi", { Eq }, 0 }, | |
4391 | }, | |
c0f3af97 L |
4392 | }; |
4393 | ||
4394 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
4395 | |
4396 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
4397 | { |
4398 | /* 00 */ | |
507bd325 L |
4399 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
4400 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
4401 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
4402 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
4403 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
4404 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
4405 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
4406 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 4407 | /* 08 */ |
507bd325 L |
4408 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
4409 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
4410 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
4411 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
4412 | { Bad_Opcode }, |
4413 | { Bad_Opcode }, | |
4414 | { Bad_Opcode }, | |
4415 | { Bad_Opcode }, | |
f88c9eb0 | 4416 | /* 10 */ |
7531c613 | 4417 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA }, |
592d1631 L |
4418 | { Bad_Opcode }, |
4419 | { Bad_Opcode }, | |
4420 | { Bad_Opcode }, | |
7531c613 JB |
4421 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA }, |
4422 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA }, | |
592d1631 | 4423 | { Bad_Opcode }, |
7531c613 | 4424 | { "ptest", { XM, EXx }, PREFIX_DATA }, |
f88c9eb0 | 4425 | /* 18 */ |
592d1631 L |
4426 | { Bad_Opcode }, |
4427 | { Bad_Opcode }, | |
4428 | { Bad_Opcode }, | |
4429 | { Bad_Opcode }, | |
507bd325 L |
4430 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
4431 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
4432 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 4433 | { Bad_Opcode }, |
f88c9eb0 | 4434 | /* 20 */ |
7531c613 JB |
4435 | { "pmovsxbw", { XM, EXq }, PREFIX_DATA }, |
4436 | { "pmovsxbd", { XM, EXd }, PREFIX_DATA }, | |
4437 | { "pmovsxbq", { XM, EXw }, PREFIX_DATA }, | |
4438 | { "pmovsxwd", { XM, EXq }, PREFIX_DATA }, | |
4439 | { "pmovsxwq", { XM, EXd }, PREFIX_DATA }, | |
4440 | { "pmovsxdq", { XM, EXq }, PREFIX_DATA }, | |
592d1631 L |
4441 | { Bad_Opcode }, |
4442 | { Bad_Opcode }, | |
f88c9eb0 | 4443 | /* 28 */ |
7531c613 JB |
4444 | { "pmuldq", { XM, EXx }, PREFIX_DATA }, |
4445 | { "pcmpeqq", { XM, EXx }, PREFIX_DATA }, | |
4446 | { MOD_TABLE (MOD_0F382A) }, | |
4447 | { "packusdw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4448 | { Bad_Opcode }, |
4449 | { Bad_Opcode }, | |
4450 | { Bad_Opcode }, | |
4451 | { Bad_Opcode }, | |
f88c9eb0 | 4452 | /* 30 */ |
7531c613 JB |
4453 | { "pmovzxbw", { XM, EXq }, PREFIX_DATA }, |
4454 | { "pmovzxbd", { XM, EXd }, PREFIX_DATA }, | |
4455 | { "pmovzxbq", { XM, EXw }, PREFIX_DATA }, | |
4456 | { "pmovzxwd", { XM, EXq }, PREFIX_DATA }, | |
4457 | { "pmovzxwq", { XM, EXd }, PREFIX_DATA }, | |
4458 | { "pmovzxdq", { XM, EXq }, PREFIX_DATA }, | |
4459 | { Bad_Opcode }, | |
4460 | { "pcmpgtq", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4461 | /* 38 */ |
7531c613 JB |
4462 | { "pminsb", { XM, EXx }, PREFIX_DATA }, |
4463 | { "pminsd", { XM, EXx }, PREFIX_DATA }, | |
4464 | { "pminuw", { XM, EXx }, PREFIX_DATA }, | |
4465 | { "pminud", { XM, EXx }, PREFIX_DATA }, | |
4466 | { "pmaxsb", { XM, EXx }, PREFIX_DATA }, | |
4467 | { "pmaxsd", { XM, EXx }, PREFIX_DATA }, | |
4468 | { "pmaxuw", { XM, EXx }, PREFIX_DATA }, | |
4469 | { "pmaxud", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4470 | /* 40 */ |
7531c613 JB |
4471 | { "pmulld", { XM, EXx }, PREFIX_DATA }, |
4472 | { "phminposuw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4473 | { Bad_Opcode }, |
4474 | { Bad_Opcode }, | |
4475 | { Bad_Opcode }, | |
4476 | { Bad_Opcode }, | |
4477 | { Bad_Opcode }, | |
4478 | { Bad_Opcode }, | |
f88c9eb0 | 4479 | /* 48 */ |
592d1631 L |
4480 | { Bad_Opcode }, |
4481 | { Bad_Opcode }, | |
4482 | { Bad_Opcode }, | |
4483 | { Bad_Opcode }, | |
4484 | { Bad_Opcode }, | |
4485 | { Bad_Opcode }, | |
4486 | { Bad_Opcode }, | |
4487 | { Bad_Opcode }, | |
f88c9eb0 | 4488 | /* 50 */ |
592d1631 L |
4489 | { Bad_Opcode }, |
4490 | { Bad_Opcode }, | |
4491 | { Bad_Opcode }, | |
4492 | { Bad_Opcode }, | |
4493 | { Bad_Opcode }, | |
4494 | { Bad_Opcode }, | |
4495 | { Bad_Opcode }, | |
4496 | { Bad_Opcode }, | |
f88c9eb0 | 4497 | /* 58 */ |
592d1631 L |
4498 | { Bad_Opcode }, |
4499 | { Bad_Opcode }, | |
4500 | { Bad_Opcode }, | |
4501 | { Bad_Opcode }, | |
4502 | { Bad_Opcode }, | |
4503 | { Bad_Opcode }, | |
4504 | { Bad_Opcode }, | |
4505 | { Bad_Opcode }, | |
f88c9eb0 | 4506 | /* 60 */ |
592d1631 L |
4507 | { Bad_Opcode }, |
4508 | { Bad_Opcode }, | |
4509 | { Bad_Opcode }, | |
4510 | { Bad_Opcode }, | |
4511 | { Bad_Opcode }, | |
4512 | { Bad_Opcode }, | |
4513 | { Bad_Opcode }, | |
4514 | { Bad_Opcode }, | |
f88c9eb0 | 4515 | /* 68 */ |
592d1631 L |
4516 | { Bad_Opcode }, |
4517 | { Bad_Opcode }, | |
4518 | { Bad_Opcode }, | |
4519 | { Bad_Opcode }, | |
4520 | { Bad_Opcode }, | |
4521 | { Bad_Opcode }, | |
4522 | { Bad_Opcode }, | |
4523 | { Bad_Opcode }, | |
f88c9eb0 | 4524 | /* 70 */ |
592d1631 L |
4525 | { Bad_Opcode }, |
4526 | { Bad_Opcode }, | |
4527 | { Bad_Opcode }, | |
4528 | { Bad_Opcode }, | |
4529 | { Bad_Opcode }, | |
4530 | { Bad_Opcode }, | |
4531 | { Bad_Opcode }, | |
4532 | { Bad_Opcode }, | |
f88c9eb0 | 4533 | /* 78 */ |
592d1631 L |
4534 | { Bad_Opcode }, |
4535 | { Bad_Opcode }, | |
4536 | { Bad_Opcode }, | |
4537 | { Bad_Opcode }, | |
4538 | { Bad_Opcode }, | |
4539 | { Bad_Opcode }, | |
4540 | { Bad_Opcode }, | |
4541 | { Bad_Opcode }, | |
f88c9eb0 | 4542 | /* 80 */ |
7531c613 JB |
4543 | { "invept", { Gm, Mo }, PREFIX_DATA }, |
4544 | { "invvpid", { Gm, Mo }, PREFIX_DATA }, | |
4545 | { "invpcid", { Gm, M }, PREFIX_DATA }, | |
592d1631 L |
4546 | { Bad_Opcode }, |
4547 | { Bad_Opcode }, | |
4548 | { Bad_Opcode }, | |
4549 | { Bad_Opcode }, | |
4550 | { Bad_Opcode }, | |
f88c9eb0 | 4551 | /* 88 */ |
592d1631 L |
4552 | { Bad_Opcode }, |
4553 | { Bad_Opcode }, | |
4554 | { Bad_Opcode }, | |
4555 | { Bad_Opcode }, | |
4556 | { Bad_Opcode }, | |
4557 | { Bad_Opcode }, | |
4558 | { Bad_Opcode }, | |
4559 | { Bad_Opcode }, | |
f88c9eb0 | 4560 | /* 90 */ |
592d1631 L |
4561 | { Bad_Opcode }, |
4562 | { Bad_Opcode }, | |
4563 | { Bad_Opcode }, | |
4564 | { Bad_Opcode }, | |
4565 | { Bad_Opcode }, | |
4566 | { Bad_Opcode }, | |
4567 | { Bad_Opcode }, | |
4568 | { Bad_Opcode }, | |
f88c9eb0 | 4569 | /* 98 */ |
592d1631 L |
4570 | { Bad_Opcode }, |
4571 | { Bad_Opcode }, | |
4572 | { Bad_Opcode }, | |
4573 | { Bad_Opcode }, | |
4574 | { Bad_Opcode }, | |
4575 | { Bad_Opcode }, | |
4576 | { Bad_Opcode }, | |
4577 | { Bad_Opcode }, | |
f88c9eb0 | 4578 | /* a0 */ |
592d1631 L |
4579 | { Bad_Opcode }, |
4580 | { Bad_Opcode }, | |
4581 | { Bad_Opcode }, | |
4582 | { Bad_Opcode }, | |
4583 | { Bad_Opcode }, | |
4584 | { Bad_Opcode }, | |
4585 | { Bad_Opcode }, | |
4586 | { Bad_Opcode }, | |
f88c9eb0 | 4587 | /* a8 */ |
592d1631 L |
4588 | { Bad_Opcode }, |
4589 | { Bad_Opcode }, | |
4590 | { Bad_Opcode }, | |
4591 | { Bad_Opcode }, | |
4592 | { Bad_Opcode }, | |
4593 | { Bad_Opcode }, | |
4594 | { Bad_Opcode }, | |
4595 | { Bad_Opcode }, | |
f88c9eb0 | 4596 | /* b0 */ |
592d1631 L |
4597 | { Bad_Opcode }, |
4598 | { Bad_Opcode }, | |
4599 | { Bad_Opcode }, | |
4600 | { Bad_Opcode }, | |
4601 | { Bad_Opcode }, | |
4602 | { Bad_Opcode }, | |
4603 | { Bad_Opcode }, | |
4604 | { Bad_Opcode }, | |
f88c9eb0 | 4605 | /* b8 */ |
592d1631 L |
4606 | { Bad_Opcode }, |
4607 | { Bad_Opcode }, | |
4608 | { Bad_Opcode }, | |
4609 | { Bad_Opcode }, | |
4610 | { Bad_Opcode }, | |
4611 | { Bad_Opcode }, | |
4612 | { Bad_Opcode }, | |
4613 | { Bad_Opcode }, | |
f88c9eb0 | 4614 | /* c0 */ |
592d1631 L |
4615 | { Bad_Opcode }, |
4616 | { Bad_Opcode }, | |
4617 | { Bad_Opcode }, | |
4618 | { Bad_Opcode }, | |
4619 | { Bad_Opcode }, | |
4620 | { Bad_Opcode }, | |
4621 | { Bad_Opcode }, | |
4622 | { Bad_Opcode }, | |
f88c9eb0 | 4623 | /* c8 */ |
035e7389 JB |
4624 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
4625 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4626 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
4627 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, | |
4628 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4629 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
592d1631 | 4630 | { Bad_Opcode }, |
7531c613 | 4631 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA }, |
f88c9eb0 | 4632 | /* d0 */ |
592d1631 L |
4633 | { Bad_Opcode }, |
4634 | { Bad_Opcode }, | |
4635 | { Bad_Opcode }, | |
4636 | { Bad_Opcode }, | |
4637 | { Bad_Opcode }, | |
4638 | { Bad_Opcode }, | |
4639 | { Bad_Opcode }, | |
4640 | { Bad_Opcode }, | |
f88c9eb0 | 4641 | /* d8 */ |
c4694f17 | 4642 | { PREFIX_TABLE (PREFIX_0F38D8) }, |
592d1631 L |
4643 | { Bad_Opcode }, |
4644 | { Bad_Opcode }, | |
7531c613 | 4645 | { "aesimc", { XM, EXx }, PREFIX_DATA }, |
c4694f17 TG |
4646 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
4647 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
4648 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
4649 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
f88c9eb0 | 4650 | /* e0 */ |
592d1631 L |
4651 | { Bad_Opcode }, |
4652 | { Bad_Opcode }, | |
4653 | { Bad_Opcode }, | |
4654 | { Bad_Opcode }, | |
4655 | { Bad_Opcode }, | |
4656 | { Bad_Opcode }, | |
4657 | { Bad_Opcode }, | |
4658 | { Bad_Opcode }, | |
f88c9eb0 | 4659 | /* e8 */ |
592d1631 L |
4660 | { Bad_Opcode }, |
4661 | { Bad_Opcode }, | |
4662 | { Bad_Opcode }, | |
4663 | { Bad_Opcode }, | |
4664 | { Bad_Opcode }, | |
4665 | { Bad_Opcode }, | |
4666 | { Bad_Opcode }, | |
4667 | { Bad_Opcode }, | |
f88c9eb0 SP |
4668 | /* f0 */ |
4669 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
4670 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
4671 | { Bad_Opcode }, |
4672 | { Bad_Opcode }, | |
4673 | { Bad_Opcode }, | |
7531c613 | 4674 | { MOD_TABLE (MOD_0F38F5) }, |
e2e1fcde | 4675 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 4676 | { Bad_Opcode }, |
f88c9eb0 | 4677 | /* f8 */ |
c0a30a9f | 4678 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
035e7389 | 4679 | { MOD_TABLE (MOD_0F38F9) }, |
c4694f17 TG |
4680 | { PREFIX_TABLE (PREFIX_0F38FA) }, |
4681 | { PREFIX_TABLE (PREFIX_0F38FB) }, | |
592d1631 L |
4682 | { Bad_Opcode }, |
4683 | { Bad_Opcode }, | |
4684 | { Bad_Opcode }, | |
4685 | { Bad_Opcode }, | |
f88c9eb0 SP |
4686 | }, |
4687 | /* THREE_BYTE_0F3A */ | |
4688 | { | |
4689 | /* 00 */ | |
592d1631 L |
4690 | { Bad_Opcode }, |
4691 | { Bad_Opcode }, | |
4692 | { Bad_Opcode }, | |
4693 | { Bad_Opcode }, | |
4694 | { Bad_Opcode }, | |
4695 | { Bad_Opcode }, | |
4696 | { Bad_Opcode }, | |
4697 | { Bad_Opcode }, | |
f88c9eb0 | 4698 | /* 08 */ |
7531c613 JB |
4699 | { "roundps", { XM, EXx, Ib }, PREFIX_DATA }, |
4700 | { "roundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4701 | { "roundss", { XM, EXd, Ib }, PREFIX_DATA }, | |
4702 | { "roundsd", { XM, EXq, Ib }, PREFIX_DATA }, | |
4703 | { "blendps", { XM, EXx, Ib }, PREFIX_DATA }, | |
4704 | { "blendpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4705 | { "pblendw", { XM, EXx, Ib }, PREFIX_DATA }, | |
507bd325 | 4706 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 4707 | /* 10 */ |
592d1631 L |
4708 | { Bad_Opcode }, |
4709 | { Bad_Opcode }, | |
4710 | { Bad_Opcode }, | |
4711 | { Bad_Opcode }, | |
7531c613 JB |
4712 | { "pextrb", { Edqb, XM, Ib }, PREFIX_DATA }, |
4713 | { "pextrw", { Edqw, XM, Ib }, PREFIX_DATA }, | |
4714 | { "pextrK", { Edq, XM, Ib }, PREFIX_DATA }, | |
4715 | { "extractps", { Edqd, XM, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4716 | /* 18 */ |
592d1631 L |
4717 | { Bad_Opcode }, |
4718 | { Bad_Opcode }, | |
4719 | { Bad_Opcode }, | |
4720 | { Bad_Opcode }, | |
4721 | { Bad_Opcode }, | |
4722 | { Bad_Opcode }, | |
4723 | { Bad_Opcode }, | |
4724 | { Bad_Opcode }, | |
f88c9eb0 | 4725 | /* 20 */ |
7531c613 JB |
4726 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_DATA }, |
4727 | { "insertps", { XM, EXd, Ib }, PREFIX_DATA }, | |
4728 | { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA }, | |
592d1631 L |
4729 | { Bad_Opcode }, |
4730 | { Bad_Opcode }, | |
4731 | { Bad_Opcode }, | |
4732 | { Bad_Opcode }, | |
4733 | { Bad_Opcode }, | |
f88c9eb0 | 4734 | /* 28 */ |
592d1631 L |
4735 | { Bad_Opcode }, |
4736 | { Bad_Opcode }, | |
4737 | { Bad_Opcode }, | |
4738 | { Bad_Opcode }, | |
4739 | { Bad_Opcode }, | |
4740 | { Bad_Opcode }, | |
4741 | { Bad_Opcode }, | |
4742 | { Bad_Opcode }, | |
f88c9eb0 | 4743 | /* 30 */ |
592d1631 L |
4744 | { Bad_Opcode }, |
4745 | { Bad_Opcode }, | |
4746 | { Bad_Opcode }, | |
4747 | { Bad_Opcode }, | |
4748 | { Bad_Opcode }, | |
4749 | { Bad_Opcode }, | |
4750 | { Bad_Opcode }, | |
4751 | { Bad_Opcode }, | |
f88c9eb0 | 4752 | /* 38 */ |
592d1631 L |
4753 | { Bad_Opcode }, |
4754 | { Bad_Opcode }, | |
4755 | { Bad_Opcode }, | |
4756 | { Bad_Opcode }, | |
4757 | { Bad_Opcode }, | |
4758 | { Bad_Opcode }, | |
4759 | { Bad_Opcode }, | |
4760 | { Bad_Opcode }, | |
f88c9eb0 | 4761 | /* 40 */ |
7531c613 JB |
4762 | { "dpps", { XM, EXx, Ib }, PREFIX_DATA }, |
4763 | { "dppd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4764 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 4765 | { Bad_Opcode }, |
7531c613 | 4766 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 L |
4767 | { Bad_Opcode }, |
4768 | { Bad_Opcode }, | |
4769 | { Bad_Opcode }, | |
f88c9eb0 | 4770 | /* 48 */ |
592d1631 L |
4771 | { Bad_Opcode }, |
4772 | { Bad_Opcode }, | |
4773 | { Bad_Opcode }, | |
4774 | { Bad_Opcode }, | |
4775 | { Bad_Opcode }, | |
4776 | { Bad_Opcode }, | |
4777 | { Bad_Opcode }, | |
4778 | { Bad_Opcode }, | |
f88c9eb0 | 4779 | /* 50 */ |
592d1631 L |
4780 | { Bad_Opcode }, |
4781 | { Bad_Opcode }, | |
4782 | { Bad_Opcode }, | |
4783 | { Bad_Opcode }, | |
4784 | { Bad_Opcode }, | |
4785 | { Bad_Opcode }, | |
4786 | { Bad_Opcode }, | |
4787 | { Bad_Opcode }, | |
f88c9eb0 | 4788 | /* 58 */ |
592d1631 L |
4789 | { Bad_Opcode }, |
4790 | { Bad_Opcode }, | |
4791 | { Bad_Opcode }, | |
4792 | { Bad_Opcode }, | |
4793 | { Bad_Opcode }, | |
4794 | { Bad_Opcode }, | |
4795 | { Bad_Opcode }, | |
4796 | { Bad_Opcode }, | |
f88c9eb0 | 4797 | /* 60 */ |
7531c613 JB |
4798 | { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
4799 | { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, | |
4800 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, | |
4801 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 L |
4802 | { Bad_Opcode }, |
4803 | { Bad_Opcode }, | |
4804 | { Bad_Opcode }, | |
4805 | { Bad_Opcode }, | |
f88c9eb0 | 4806 | /* 68 */ |
592d1631 L |
4807 | { Bad_Opcode }, |
4808 | { Bad_Opcode }, | |
4809 | { Bad_Opcode }, | |
4810 | { Bad_Opcode }, | |
4811 | { Bad_Opcode }, | |
4812 | { Bad_Opcode }, | |
4813 | { Bad_Opcode }, | |
4814 | { Bad_Opcode }, | |
f88c9eb0 | 4815 | /* 70 */ |
592d1631 L |
4816 | { Bad_Opcode }, |
4817 | { Bad_Opcode }, | |
4818 | { Bad_Opcode }, | |
4819 | { Bad_Opcode }, | |
4820 | { Bad_Opcode }, | |
4821 | { Bad_Opcode }, | |
4822 | { Bad_Opcode }, | |
4823 | { Bad_Opcode }, | |
f88c9eb0 | 4824 | /* 78 */ |
592d1631 L |
4825 | { Bad_Opcode }, |
4826 | { Bad_Opcode }, | |
4827 | { Bad_Opcode }, | |
4828 | { Bad_Opcode }, | |
4829 | { Bad_Opcode }, | |
4830 | { Bad_Opcode }, | |
4831 | { Bad_Opcode }, | |
4832 | { Bad_Opcode }, | |
f88c9eb0 | 4833 | /* 80 */ |
592d1631 L |
4834 | { Bad_Opcode }, |
4835 | { Bad_Opcode }, | |
4836 | { Bad_Opcode }, | |
4837 | { Bad_Opcode }, | |
4838 | { Bad_Opcode }, | |
4839 | { Bad_Opcode }, | |
4840 | { Bad_Opcode }, | |
4841 | { Bad_Opcode }, | |
f88c9eb0 | 4842 | /* 88 */ |
592d1631 L |
4843 | { Bad_Opcode }, |
4844 | { Bad_Opcode }, | |
4845 | { Bad_Opcode }, | |
4846 | { Bad_Opcode }, | |
4847 | { Bad_Opcode }, | |
4848 | { Bad_Opcode }, | |
4849 | { Bad_Opcode }, | |
4850 | { Bad_Opcode }, | |
f88c9eb0 | 4851 | /* 90 */ |
592d1631 L |
4852 | { Bad_Opcode }, |
4853 | { Bad_Opcode }, | |
4854 | { Bad_Opcode }, | |
4855 | { Bad_Opcode }, | |
4856 | { Bad_Opcode }, | |
4857 | { Bad_Opcode }, | |
4858 | { Bad_Opcode }, | |
4859 | { Bad_Opcode }, | |
f88c9eb0 | 4860 | /* 98 */ |
592d1631 L |
4861 | { Bad_Opcode }, |
4862 | { Bad_Opcode }, | |
4863 | { Bad_Opcode }, | |
4864 | { Bad_Opcode }, | |
4865 | { Bad_Opcode }, | |
4866 | { Bad_Opcode }, | |
4867 | { Bad_Opcode }, | |
4868 | { Bad_Opcode }, | |
f88c9eb0 | 4869 | /* a0 */ |
592d1631 L |
4870 | { Bad_Opcode }, |
4871 | { Bad_Opcode }, | |
4872 | { Bad_Opcode }, | |
4873 | { Bad_Opcode }, | |
4874 | { Bad_Opcode }, | |
4875 | { Bad_Opcode }, | |
4876 | { Bad_Opcode }, | |
4877 | { Bad_Opcode }, | |
f88c9eb0 | 4878 | /* a8 */ |
592d1631 L |
4879 | { Bad_Opcode }, |
4880 | { Bad_Opcode }, | |
4881 | { Bad_Opcode }, | |
4882 | { Bad_Opcode }, | |
4883 | { Bad_Opcode }, | |
4884 | { Bad_Opcode }, | |
4885 | { Bad_Opcode }, | |
4886 | { Bad_Opcode }, | |
f88c9eb0 | 4887 | /* b0 */ |
592d1631 L |
4888 | { Bad_Opcode }, |
4889 | { Bad_Opcode }, | |
4890 | { Bad_Opcode }, | |
4891 | { Bad_Opcode }, | |
4892 | { Bad_Opcode }, | |
4893 | { Bad_Opcode }, | |
4894 | { Bad_Opcode }, | |
4895 | { Bad_Opcode }, | |
f88c9eb0 | 4896 | /* b8 */ |
592d1631 L |
4897 | { Bad_Opcode }, |
4898 | { Bad_Opcode }, | |
4899 | { Bad_Opcode }, | |
4900 | { Bad_Opcode }, | |
4901 | { Bad_Opcode }, | |
4902 | { Bad_Opcode }, | |
4903 | { Bad_Opcode }, | |
4904 | { Bad_Opcode }, | |
f88c9eb0 | 4905 | /* c0 */ |
592d1631 L |
4906 | { Bad_Opcode }, |
4907 | { Bad_Opcode }, | |
4908 | { Bad_Opcode }, | |
4909 | { Bad_Opcode }, | |
4910 | { Bad_Opcode }, | |
4911 | { Bad_Opcode }, | |
4912 | { Bad_Opcode }, | |
4913 | { Bad_Opcode }, | |
f88c9eb0 | 4914 | /* c8 */ |
592d1631 L |
4915 | { Bad_Opcode }, |
4916 | { Bad_Opcode }, | |
4917 | { Bad_Opcode }, | |
4918 | { Bad_Opcode }, | |
035e7389 | 4919 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
592d1631 | 4920 | { Bad_Opcode }, |
7531c613 JB |
4921 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA }, |
4922 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4923 | /* d0 */ |
592d1631 L |
4924 | { Bad_Opcode }, |
4925 | { Bad_Opcode }, | |
4926 | { Bad_Opcode }, | |
4927 | { Bad_Opcode }, | |
4928 | { Bad_Opcode }, | |
4929 | { Bad_Opcode }, | |
4930 | { Bad_Opcode }, | |
4931 | { Bad_Opcode }, | |
f88c9eb0 | 4932 | /* d8 */ |
592d1631 L |
4933 | { Bad_Opcode }, |
4934 | { Bad_Opcode }, | |
4935 | { Bad_Opcode }, | |
4936 | { Bad_Opcode }, | |
4937 | { Bad_Opcode }, | |
4938 | { Bad_Opcode }, | |
4939 | { Bad_Opcode }, | |
7531c613 | 4940 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
f88c9eb0 | 4941 | /* e0 */ |
592d1631 L |
4942 | { Bad_Opcode }, |
4943 | { Bad_Opcode }, | |
4944 | { Bad_Opcode }, | |
4945 | { Bad_Opcode }, | |
4946 | { Bad_Opcode }, | |
592d1631 L |
4947 | { Bad_Opcode }, |
4948 | { Bad_Opcode }, | |
4949 | { Bad_Opcode }, | |
85f10a01 | 4950 | /* e8 */ |
592d1631 L |
4951 | { Bad_Opcode }, |
4952 | { Bad_Opcode }, | |
4953 | { Bad_Opcode }, | |
4954 | { Bad_Opcode }, | |
4955 | { Bad_Opcode }, | |
4956 | { Bad_Opcode }, | |
4957 | { Bad_Opcode }, | |
4958 | { Bad_Opcode }, | |
85f10a01 | 4959 | /* f0 */ |
c1fa250a | 4960 | { PREFIX_TABLE (PREFIX_0F3A0F) }, |
592d1631 L |
4961 | { Bad_Opcode }, |
4962 | { Bad_Opcode }, | |
4963 | { Bad_Opcode }, | |
4964 | { Bad_Opcode }, | |
4965 | { Bad_Opcode }, | |
4966 | { Bad_Opcode }, | |
4967 | { Bad_Opcode }, | |
85f10a01 | 4968 | /* f8 */ |
592d1631 L |
4969 | { Bad_Opcode }, |
4970 | { Bad_Opcode }, | |
4971 | { Bad_Opcode }, | |
4972 | { Bad_Opcode }, | |
4973 | { Bad_Opcode }, | |
4974 | { Bad_Opcode }, | |
4975 | { Bad_Opcode }, | |
4976 | { Bad_Opcode }, | |
85f10a01 | 4977 | }, |
f88c9eb0 SP |
4978 | }; |
4979 | ||
4980 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 4981 | /* XOP_08 */ |
85f10a01 MM |
4982 | { |
4983 | /* 00 */ | |
592d1631 L |
4984 | { Bad_Opcode }, |
4985 | { Bad_Opcode }, | |
4986 | { Bad_Opcode }, | |
4987 | { Bad_Opcode }, | |
4988 | { Bad_Opcode }, | |
4989 | { Bad_Opcode }, | |
4990 | { Bad_Opcode }, | |
4991 | { Bad_Opcode }, | |
85f10a01 | 4992 | /* 08 */ |
592d1631 L |
4993 | { Bad_Opcode }, |
4994 | { Bad_Opcode }, | |
4995 | { Bad_Opcode }, | |
4996 | { Bad_Opcode }, | |
4997 | { Bad_Opcode }, | |
4998 | { Bad_Opcode }, | |
4999 | { Bad_Opcode }, | |
5000 | { Bad_Opcode }, | |
85f10a01 | 5001 | /* 10 */ |
3929df09 | 5002 | { Bad_Opcode }, |
592d1631 L |
5003 | { Bad_Opcode }, |
5004 | { Bad_Opcode }, | |
5005 | { Bad_Opcode }, | |
5006 | { Bad_Opcode }, | |
5007 | { Bad_Opcode }, | |
5008 | { Bad_Opcode }, | |
5009 | { Bad_Opcode }, | |
85f10a01 | 5010 | /* 18 */ |
592d1631 L |
5011 | { Bad_Opcode }, |
5012 | { Bad_Opcode }, | |
5013 | { Bad_Opcode }, | |
5014 | { Bad_Opcode }, | |
5015 | { Bad_Opcode }, | |
5016 | { Bad_Opcode }, | |
5017 | { Bad_Opcode }, | |
5018 | { Bad_Opcode }, | |
85f10a01 | 5019 | /* 20 */ |
592d1631 L |
5020 | { Bad_Opcode }, |
5021 | { Bad_Opcode }, | |
5022 | { Bad_Opcode }, | |
5023 | { Bad_Opcode }, | |
5024 | { Bad_Opcode }, | |
5025 | { Bad_Opcode }, | |
5026 | { Bad_Opcode }, | |
5027 | { Bad_Opcode }, | |
85f10a01 | 5028 | /* 28 */ |
592d1631 L |
5029 | { Bad_Opcode }, |
5030 | { Bad_Opcode }, | |
5031 | { Bad_Opcode }, | |
5032 | { Bad_Opcode }, | |
5033 | { Bad_Opcode }, | |
5034 | { Bad_Opcode }, | |
5035 | { Bad_Opcode }, | |
5036 | { Bad_Opcode }, | |
c0f3af97 | 5037 | /* 30 */ |
592d1631 L |
5038 | { Bad_Opcode }, |
5039 | { Bad_Opcode }, | |
5040 | { Bad_Opcode }, | |
5041 | { Bad_Opcode }, | |
5042 | { Bad_Opcode }, | |
5043 | { Bad_Opcode }, | |
5044 | { Bad_Opcode }, | |
5045 | { Bad_Opcode }, | |
c0f3af97 | 5046 | /* 38 */ |
592d1631 L |
5047 | { Bad_Opcode }, |
5048 | { Bad_Opcode }, | |
5049 | { Bad_Opcode }, | |
5050 | { Bad_Opcode }, | |
5051 | { Bad_Opcode }, | |
5052 | { Bad_Opcode }, | |
5053 | { Bad_Opcode }, | |
5054 | { Bad_Opcode }, | |
c0f3af97 | 5055 | /* 40 */ |
592d1631 L |
5056 | { Bad_Opcode }, |
5057 | { Bad_Opcode }, | |
5058 | { Bad_Opcode }, | |
5059 | { Bad_Opcode }, | |
5060 | { Bad_Opcode }, | |
5061 | { Bad_Opcode }, | |
5062 | { Bad_Opcode }, | |
5063 | { Bad_Opcode }, | |
85f10a01 | 5064 | /* 48 */ |
592d1631 L |
5065 | { Bad_Opcode }, |
5066 | { Bad_Opcode }, | |
5067 | { Bad_Opcode }, | |
5068 | { Bad_Opcode }, | |
5069 | { Bad_Opcode }, | |
5070 | { Bad_Opcode }, | |
5071 | { Bad_Opcode }, | |
5072 | { Bad_Opcode }, | |
c0f3af97 | 5073 | /* 50 */ |
592d1631 L |
5074 | { Bad_Opcode }, |
5075 | { Bad_Opcode }, | |
5076 | { Bad_Opcode }, | |
5077 | { Bad_Opcode }, | |
5078 | { Bad_Opcode }, | |
5079 | { Bad_Opcode }, | |
5080 | { Bad_Opcode }, | |
5081 | { Bad_Opcode }, | |
85f10a01 | 5082 | /* 58 */ |
592d1631 L |
5083 | { Bad_Opcode }, |
5084 | { Bad_Opcode }, | |
5085 | { Bad_Opcode }, | |
5086 | { Bad_Opcode }, | |
5087 | { Bad_Opcode }, | |
5088 | { Bad_Opcode }, | |
5089 | { Bad_Opcode }, | |
5090 | { Bad_Opcode }, | |
c1e679ec | 5091 | /* 60 */ |
592d1631 L |
5092 | { Bad_Opcode }, |
5093 | { Bad_Opcode }, | |
5094 | { Bad_Opcode }, | |
5095 | { Bad_Opcode }, | |
5096 | { Bad_Opcode }, | |
5097 | { Bad_Opcode }, | |
5098 | { Bad_Opcode }, | |
5099 | { Bad_Opcode }, | |
c0f3af97 | 5100 | /* 68 */ |
592d1631 L |
5101 | { Bad_Opcode }, |
5102 | { Bad_Opcode }, | |
5103 | { Bad_Opcode }, | |
5104 | { Bad_Opcode }, | |
5105 | { Bad_Opcode }, | |
5106 | { Bad_Opcode }, | |
5107 | { Bad_Opcode }, | |
5108 | { Bad_Opcode }, | |
85f10a01 | 5109 | /* 70 */ |
592d1631 L |
5110 | { Bad_Opcode }, |
5111 | { Bad_Opcode }, | |
5112 | { Bad_Opcode }, | |
5113 | { Bad_Opcode }, | |
5114 | { Bad_Opcode }, | |
5115 | { Bad_Opcode }, | |
5116 | { Bad_Opcode }, | |
5117 | { Bad_Opcode }, | |
85f10a01 | 5118 | /* 78 */ |
592d1631 L |
5119 | { Bad_Opcode }, |
5120 | { Bad_Opcode }, | |
5121 | { Bad_Opcode }, | |
5122 | { Bad_Opcode }, | |
5123 | { Bad_Opcode }, | |
5124 | { Bad_Opcode }, | |
5125 | { Bad_Opcode }, | |
5126 | { Bad_Opcode }, | |
85f10a01 | 5127 | /* 80 */ |
592d1631 L |
5128 | { Bad_Opcode }, |
5129 | { Bad_Opcode }, | |
5130 | { Bad_Opcode }, | |
5131 | { Bad_Opcode }, | |
5132 | { Bad_Opcode }, | |
467bbef0 JB |
5133 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_85) }, |
5134 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_86) }, | |
5135 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_87) }, | |
5dd85c99 | 5136 | /* 88 */ |
592d1631 L |
5137 | { Bad_Opcode }, |
5138 | { Bad_Opcode }, | |
5139 | { Bad_Opcode }, | |
5140 | { Bad_Opcode }, | |
5141 | { Bad_Opcode }, | |
5142 | { Bad_Opcode }, | |
467bbef0 JB |
5143 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8E) }, |
5144 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_8F) }, | |
5dd85c99 | 5145 | /* 90 */ |
592d1631 L |
5146 | { Bad_Opcode }, |
5147 | { Bad_Opcode }, | |
5148 | { Bad_Opcode }, | |
5149 | { Bad_Opcode }, | |
5150 | { Bad_Opcode }, | |
467bbef0 JB |
5151 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_95) }, |
5152 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_96) }, | |
5153 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_97) }, | |
5dd85c99 | 5154 | /* 98 */ |
592d1631 L |
5155 | { Bad_Opcode }, |
5156 | { Bad_Opcode }, | |
5157 | { Bad_Opcode }, | |
5158 | { Bad_Opcode }, | |
5159 | { Bad_Opcode }, | |
5160 | { Bad_Opcode }, | |
467bbef0 JB |
5161 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9E) }, |
5162 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_9F) }, | |
5dd85c99 | 5163 | /* a0 */ |
592d1631 L |
5164 | { Bad_Opcode }, |
5165 | { Bad_Opcode }, | |
b13b1bc0 | 5166 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
467bbef0 | 5167 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A3) }, |
592d1631 L |
5168 | { Bad_Opcode }, |
5169 | { Bad_Opcode }, | |
467bbef0 | 5170 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_A6) }, |
592d1631 | 5171 | { Bad_Opcode }, |
5dd85c99 | 5172 | /* a8 */ |
592d1631 L |
5173 | { Bad_Opcode }, |
5174 | { Bad_Opcode }, | |
5175 | { Bad_Opcode }, | |
5176 | { Bad_Opcode }, | |
5177 | { Bad_Opcode }, | |
5178 | { Bad_Opcode }, | |
5179 | { Bad_Opcode }, | |
5180 | { Bad_Opcode }, | |
5dd85c99 | 5181 | /* b0 */ |
592d1631 L |
5182 | { Bad_Opcode }, |
5183 | { Bad_Opcode }, | |
5184 | { Bad_Opcode }, | |
5185 | { Bad_Opcode }, | |
5186 | { Bad_Opcode }, | |
5187 | { Bad_Opcode }, | |
467bbef0 | 5188 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_B6) }, |
592d1631 | 5189 | { Bad_Opcode }, |
5dd85c99 | 5190 | /* b8 */ |
592d1631 L |
5191 | { Bad_Opcode }, |
5192 | { Bad_Opcode }, | |
5193 | { Bad_Opcode }, | |
5194 | { Bad_Opcode }, | |
5195 | { Bad_Opcode }, | |
5196 | { Bad_Opcode }, | |
5197 | { Bad_Opcode }, | |
5198 | { Bad_Opcode }, | |
5dd85c99 | 5199 | /* c0 */ |
467bbef0 JB |
5200 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C0) }, |
5201 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C1) }, | |
5202 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C2) }, | |
5203 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_C3) }, | |
592d1631 L |
5204 | { Bad_Opcode }, |
5205 | { Bad_Opcode }, | |
5206 | { Bad_Opcode }, | |
5207 | { Bad_Opcode }, | |
5dd85c99 | 5208 | /* c8 */ |
592d1631 L |
5209 | { Bad_Opcode }, |
5210 | { Bad_Opcode }, | |
5211 | { Bad_Opcode }, | |
5212 | { Bad_Opcode }, | |
ff688e1f L |
5213 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
5214 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
5215 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
5216 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 5217 | /* d0 */ |
592d1631 L |
5218 | { Bad_Opcode }, |
5219 | { Bad_Opcode }, | |
5220 | { Bad_Opcode }, | |
5221 | { Bad_Opcode }, | |
5222 | { Bad_Opcode }, | |
5223 | { Bad_Opcode }, | |
5224 | { Bad_Opcode }, | |
5225 | { Bad_Opcode }, | |
5dd85c99 | 5226 | /* d8 */ |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
5229 | { Bad_Opcode }, | |
5230 | { Bad_Opcode }, | |
5231 | { Bad_Opcode }, | |
5232 | { Bad_Opcode }, | |
5233 | { Bad_Opcode }, | |
5234 | { Bad_Opcode }, | |
5dd85c99 | 5235 | /* e0 */ |
592d1631 L |
5236 | { Bad_Opcode }, |
5237 | { Bad_Opcode }, | |
5238 | { Bad_Opcode }, | |
5239 | { Bad_Opcode }, | |
5240 | { Bad_Opcode }, | |
5241 | { Bad_Opcode }, | |
5242 | { Bad_Opcode }, | |
5243 | { Bad_Opcode }, | |
5dd85c99 | 5244 | /* e8 */ |
592d1631 L |
5245 | { Bad_Opcode }, |
5246 | { Bad_Opcode }, | |
5247 | { Bad_Opcode }, | |
5248 | { Bad_Opcode }, | |
ff688e1f L |
5249 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
5250 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
5251 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
5252 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 5253 | /* f0 */ |
592d1631 L |
5254 | { Bad_Opcode }, |
5255 | { Bad_Opcode }, | |
5256 | { Bad_Opcode }, | |
5257 | { Bad_Opcode }, | |
5258 | { Bad_Opcode }, | |
5259 | { Bad_Opcode }, | |
5260 | { Bad_Opcode }, | |
5261 | { Bad_Opcode }, | |
5dd85c99 | 5262 | /* f8 */ |
592d1631 L |
5263 | { Bad_Opcode }, |
5264 | { Bad_Opcode }, | |
5265 | { Bad_Opcode }, | |
5266 | { Bad_Opcode }, | |
5267 | { Bad_Opcode }, | |
5268 | { Bad_Opcode }, | |
5269 | { Bad_Opcode }, | |
5270 | { Bad_Opcode }, | |
5dd85c99 SP |
5271 | }, |
5272 | /* XOP_09 */ | |
5273 | { | |
5274 | /* 00 */ | |
592d1631 | 5275 | { Bad_Opcode }, |
467bbef0 JB |
5276 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_01) }, |
5277 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_02) }, | |
592d1631 L |
5278 | { Bad_Opcode }, |
5279 | { Bad_Opcode }, | |
5280 | { Bad_Opcode }, | |
5281 | { Bad_Opcode }, | |
5282 | { Bad_Opcode }, | |
5dd85c99 | 5283 | /* 08 */ |
592d1631 L |
5284 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, | |
5286 | { Bad_Opcode }, | |
5287 | { Bad_Opcode }, | |
5288 | { Bad_Opcode }, | |
5289 | { Bad_Opcode }, | |
5290 | { Bad_Opcode }, | |
5291 | { Bad_Opcode }, | |
5dd85c99 | 5292 | /* 10 */ |
592d1631 L |
5293 | { Bad_Opcode }, |
5294 | { Bad_Opcode }, | |
467bbef0 | 5295 | { MOD_TABLE (MOD_VEX_0FXOP_09_12) }, |
592d1631 L |
5296 | { Bad_Opcode }, |
5297 | { Bad_Opcode }, | |
5298 | { Bad_Opcode }, | |
5299 | { Bad_Opcode }, | |
5300 | { Bad_Opcode }, | |
5dd85c99 | 5301 | /* 18 */ |
592d1631 L |
5302 | { Bad_Opcode }, |
5303 | { Bad_Opcode }, | |
5304 | { Bad_Opcode }, | |
5305 | { Bad_Opcode }, | |
5306 | { Bad_Opcode }, | |
5307 | { Bad_Opcode }, | |
5308 | { Bad_Opcode }, | |
5309 | { Bad_Opcode }, | |
5dd85c99 | 5310 | /* 20 */ |
592d1631 L |
5311 | { Bad_Opcode }, |
5312 | { Bad_Opcode }, | |
5313 | { Bad_Opcode }, | |
5314 | { Bad_Opcode }, | |
5315 | { Bad_Opcode }, | |
5316 | { Bad_Opcode }, | |
5317 | { Bad_Opcode }, | |
5318 | { Bad_Opcode }, | |
5dd85c99 | 5319 | /* 28 */ |
592d1631 L |
5320 | { Bad_Opcode }, |
5321 | { Bad_Opcode }, | |
5322 | { Bad_Opcode }, | |
5323 | { Bad_Opcode }, | |
5324 | { Bad_Opcode }, | |
5325 | { Bad_Opcode }, | |
5326 | { Bad_Opcode }, | |
5327 | { Bad_Opcode }, | |
5dd85c99 | 5328 | /* 30 */ |
592d1631 L |
5329 | { Bad_Opcode }, |
5330 | { Bad_Opcode }, | |
5331 | { Bad_Opcode }, | |
5332 | { Bad_Opcode }, | |
5333 | { Bad_Opcode }, | |
5334 | { Bad_Opcode }, | |
5335 | { Bad_Opcode }, | |
5336 | { Bad_Opcode }, | |
5dd85c99 | 5337 | /* 38 */ |
592d1631 L |
5338 | { Bad_Opcode }, |
5339 | { Bad_Opcode }, | |
5340 | { Bad_Opcode }, | |
5341 | { Bad_Opcode }, | |
5342 | { Bad_Opcode }, | |
5343 | { Bad_Opcode }, | |
5344 | { Bad_Opcode }, | |
5345 | { Bad_Opcode }, | |
5dd85c99 | 5346 | /* 40 */ |
592d1631 L |
5347 | { Bad_Opcode }, |
5348 | { Bad_Opcode }, | |
5349 | { Bad_Opcode }, | |
5350 | { Bad_Opcode }, | |
5351 | { Bad_Opcode }, | |
5352 | { Bad_Opcode }, | |
5353 | { Bad_Opcode }, | |
5354 | { Bad_Opcode }, | |
5dd85c99 | 5355 | /* 48 */ |
592d1631 L |
5356 | { Bad_Opcode }, |
5357 | { Bad_Opcode }, | |
5358 | { Bad_Opcode }, | |
5359 | { Bad_Opcode }, | |
5360 | { Bad_Opcode }, | |
5361 | { Bad_Opcode }, | |
5362 | { Bad_Opcode }, | |
5363 | { Bad_Opcode }, | |
5dd85c99 | 5364 | /* 50 */ |
592d1631 L |
5365 | { Bad_Opcode }, |
5366 | { Bad_Opcode }, | |
5367 | { Bad_Opcode }, | |
5368 | { Bad_Opcode }, | |
5369 | { Bad_Opcode }, | |
5370 | { Bad_Opcode }, | |
5371 | { Bad_Opcode }, | |
5372 | { Bad_Opcode }, | |
5dd85c99 | 5373 | /* 58 */ |
592d1631 L |
5374 | { Bad_Opcode }, |
5375 | { Bad_Opcode }, | |
5376 | { Bad_Opcode }, | |
5377 | { Bad_Opcode }, | |
5378 | { Bad_Opcode }, | |
5379 | { Bad_Opcode }, | |
5380 | { Bad_Opcode }, | |
5381 | { Bad_Opcode }, | |
5dd85c99 | 5382 | /* 60 */ |
592d1631 L |
5383 | { Bad_Opcode }, |
5384 | { Bad_Opcode }, | |
5385 | { Bad_Opcode }, | |
5386 | { Bad_Opcode }, | |
5387 | { Bad_Opcode }, | |
5388 | { Bad_Opcode }, | |
5389 | { Bad_Opcode }, | |
5390 | { Bad_Opcode }, | |
5dd85c99 | 5391 | /* 68 */ |
592d1631 L |
5392 | { Bad_Opcode }, |
5393 | { Bad_Opcode }, | |
5394 | { Bad_Opcode }, | |
5395 | { Bad_Opcode }, | |
5396 | { Bad_Opcode }, | |
5397 | { Bad_Opcode }, | |
5398 | { Bad_Opcode }, | |
5399 | { Bad_Opcode }, | |
5dd85c99 | 5400 | /* 70 */ |
592d1631 L |
5401 | { Bad_Opcode }, |
5402 | { Bad_Opcode }, | |
5403 | { Bad_Opcode }, | |
5404 | { Bad_Opcode }, | |
5405 | { Bad_Opcode }, | |
5406 | { Bad_Opcode }, | |
5407 | { Bad_Opcode }, | |
5408 | { Bad_Opcode }, | |
5dd85c99 | 5409 | /* 78 */ |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
5412 | { Bad_Opcode }, | |
5413 | { Bad_Opcode }, | |
5414 | { Bad_Opcode }, | |
5415 | { Bad_Opcode }, | |
5416 | { Bad_Opcode }, | |
5417 | { Bad_Opcode }, | |
5dd85c99 | 5418 | /* 80 */ |
b5b098c2 JB |
5419 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
5420 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
5421 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
5422 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
5423 | { Bad_Opcode }, |
5424 | { Bad_Opcode }, | |
5425 | { Bad_Opcode }, | |
5426 | { Bad_Opcode }, | |
5dd85c99 | 5427 | /* 88 */ |
592d1631 L |
5428 | { Bad_Opcode }, |
5429 | { Bad_Opcode }, | |
5430 | { Bad_Opcode }, | |
5431 | { Bad_Opcode }, | |
5432 | { Bad_Opcode }, | |
5433 | { Bad_Opcode }, | |
5434 | { Bad_Opcode }, | |
5435 | { Bad_Opcode }, | |
5dd85c99 | 5436 | /* 90 */ |
467bbef0 JB |
5437 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_90) }, |
5438 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_91) }, | |
5439 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_92) }, | |
5440 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_93) }, | |
5441 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_94) }, | |
5442 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_95) }, | |
5443 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_96) }, | |
5444 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_97) }, | |
5dd85c99 | 5445 | /* 98 */ |
467bbef0 JB |
5446 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_98) }, |
5447 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_99) }, | |
5448 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9A) }, | |
5449 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_9B) }, | |
592d1631 L |
5450 | { Bad_Opcode }, |
5451 | { Bad_Opcode }, | |
5452 | { Bad_Opcode }, | |
5453 | { Bad_Opcode }, | |
5dd85c99 | 5454 | /* a0 */ |
592d1631 L |
5455 | { Bad_Opcode }, |
5456 | { Bad_Opcode }, | |
5457 | { Bad_Opcode }, | |
5458 | { Bad_Opcode }, | |
5459 | { Bad_Opcode }, | |
5460 | { Bad_Opcode }, | |
5461 | { Bad_Opcode }, | |
5462 | { Bad_Opcode }, | |
5dd85c99 | 5463 | /* a8 */ |
592d1631 L |
5464 | { Bad_Opcode }, |
5465 | { Bad_Opcode }, | |
5466 | { Bad_Opcode }, | |
5467 | { Bad_Opcode }, | |
5468 | { Bad_Opcode }, | |
5469 | { Bad_Opcode }, | |
5470 | { Bad_Opcode }, | |
5471 | { Bad_Opcode }, | |
5dd85c99 | 5472 | /* b0 */ |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
5475 | { Bad_Opcode }, | |
5476 | { Bad_Opcode }, | |
5477 | { Bad_Opcode }, | |
5478 | { Bad_Opcode }, | |
5479 | { Bad_Opcode }, | |
5480 | { Bad_Opcode }, | |
5dd85c99 | 5481 | /* b8 */ |
592d1631 L |
5482 | { Bad_Opcode }, |
5483 | { Bad_Opcode }, | |
5484 | { Bad_Opcode }, | |
5485 | { Bad_Opcode }, | |
5486 | { Bad_Opcode }, | |
5487 | { Bad_Opcode }, | |
5488 | { Bad_Opcode }, | |
5489 | { Bad_Opcode }, | |
5dd85c99 | 5490 | /* c0 */ |
592d1631 | 5491 | { Bad_Opcode }, |
467bbef0 JB |
5492 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C1) }, |
5493 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C2) }, | |
5494 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C3) }, | |
592d1631 L |
5495 | { Bad_Opcode }, |
5496 | { Bad_Opcode }, | |
467bbef0 JB |
5497 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C6) }, |
5498 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_C7) }, | |
5dd85c99 | 5499 | /* c8 */ |
592d1631 L |
5500 | { Bad_Opcode }, |
5501 | { Bad_Opcode }, | |
5502 | { Bad_Opcode }, | |
467bbef0 | 5503 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_CB) }, |
592d1631 L |
5504 | { Bad_Opcode }, |
5505 | { Bad_Opcode }, | |
5506 | { Bad_Opcode }, | |
5507 | { Bad_Opcode }, | |
5dd85c99 | 5508 | /* d0 */ |
592d1631 | 5509 | { Bad_Opcode }, |
467bbef0 JB |
5510 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D1) }, |
5511 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D2) }, | |
5512 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D3) }, | |
592d1631 L |
5513 | { Bad_Opcode }, |
5514 | { Bad_Opcode }, | |
467bbef0 JB |
5515 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D6) }, |
5516 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_D7) }, | |
5dd85c99 | 5517 | /* d8 */ |
592d1631 L |
5518 | { Bad_Opcode }, |
5519 | { Bad_Opcode }, | |
5520 | { Bad_Opcode }, | |
467bbef0 | 5521 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_DB) }, |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
5524 | { Bad_Opcode }, | |
5525 | { Bad_Opcode }, | |
5dd85c99 | 5526 | /* e0 */ |
592d1631 | 5527 | { Bad_Opcode }, |
467bbef0 JB |
5528 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E1) }, |
5529 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E2) }, | |
5530 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_E3) }, | |
592d1631 L |
5531 | { Bad_Opcode }, |
5532 | { Bad_Opcode }, | |
5533 | { Bad_Opcode }, | |
5534 | { Bad_Opcode }, | |
4e7d34a6 | 5535 | /* e8 */ |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
5538 | { Bad_Opcode }, | |
5539 | { Bad_Opcode }, | |
5540 | { Bad_Opcode }, | |
5541 | { Bad_Opcode }, | |
5542 | { Bad_Opcode }, | |
5543 | { Bad_Opcode }, | |
4e7d34a6 | 5544 | /* f0 */ |
592d1631 L |
5545 | { Bad_Opcode }, |
5546 | { Bad_Opcode }, | |
5547 | { Bad_Opcode }, | |
5548 | { Bad_Opcode }, | |
5549 | { Bad_Opcode }, | |
5550 | { Bad_Opcode }, | |
5551 | { Bad_Opcode }, | |
5552 | { Bad_Opcode }, | |
4e7d34a6 | 5553 | /* f8 */ |
592d1631 L |
5554 | { Bad_Opcode }, |
5555 | { Bad_Opcode }, | |
5556 | { Bad_Opcode }, | |
5557 | { Bad_Opcode }, | |
5558 | { Bad_Opcode }, | |
5559 | { Bad_Opcode }, | |
5560 | { Bad_Opcode }, | |
5561 | { Bad_Opcode }, | |
4e7d34a6 | 5562 | }, |
f88c9eb0 | 5563 | /* XOP_0A */ |
4e7d34a6 L |
5564 | { |
5565 | /* 00 */ | |
592d1631 L |
5566 | { Bad_Opcode }, |
5567 | { Bad_Opcode }, | |
5568 | { Bad_Opcode }, | |
5569 | { Bad_Opcode }, | |
5570 | { Bad_Opcode }, | |
5571 | { Bad_Opcode }, | |
5572 | { Bad_Opcode }, | |
5573 | { Bad_Opcode }, | |
4e7d34a6 | 5574 | /* 08 */ |
592d1631 L |
5575 | { Bad_Opcode }, |
5576 | { Bad_Opcode }, | |
5577 | { Bad_Opcode }, | |
5578 | { Bad_Opcode }, | |
5579 | { Bad_Opcode }, | |
5580 | { Bad_Opcode }, | |
5581 | { Bad_Opcode }, | |
5582 | { Bad_Opcode }, | |
4e7d34a6 | 5583 | /* 10 */ |
c1dc7af5 | 5584 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 5585 | { Bad_Opcode }, |
467bbef0 | 5586 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_0A_12) }, |
592d1631 L |
5587 | { Bad_Opcode }, |
5588 | { Bad_Opcode }, | |
5589 | { Bad_Opcode }, | |
5590 | { Bad_Opcode }, | |
5591 | { Bad_Opcode }, | |
4e7d34a6 | 5592 | /* 18 */ |
592d1631 L |
5593 | { Bad_Opcode }, |
5594 | { Bad_Opcode }, | |
5595 | { Bad_Opcode }, | |
5596 | { Bad_Opcode }, | |
5597 | { Bad_Opcode }, | |
5598 | { Bad_Opcode }, | |
5599 | { Bad_Opcode }, | |
5600 | { Bad_Opcode }, | |
4e7d34a6 | 5601 | /* 20 */ |
592d1631 L |
5602 | { Bad_Opcode }, |
5603 | { Bad_Opcode }, | |
5604 | { Bad_Opcode }, | |
5605 | { Bad_Opcode }, | |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
5608 | { Bad_Opcode }, | |
5609 | { Bad_Opcode }, | |
4e7d34a6 | 5610 | /* 28 */ |
592d1631 L |
5611 | { Bad_Opcode }, |
5612 | { Bad_Opcode }, | |
5613 | { Bad_Opcode }, | |
5614 | { Bad_Opcode }, | |
5615 | { Bad_Opcode }, | |
5616 | { Bad_Opcode }, | |
5617 | { Bad_Opcode }, | |
5618 | { Bad_Opcode }, | |
4e7d34a6 | 5619 | /* 30 */ |
592d1631 L |
5620 | { Bad_Opcode }, |
5621 | { Bad_Opcode }, | |
5622 | { Bad_Opcode }, | |
5623 | { Bad_Opcode }, | |
5624 | { Bad_Opcode }, | |
5625 | { Bad_Opcode }, | |
5626 | { Bad_Opcode }, | |
5627 | { Bad_Opcode }, | |
c0f3af97 | 5628 | /* 38 */ |
592d1631 L |
5629 | { Bad_Opcode }, |
5630 | { Bad_Opcode }, | |
5631 | { Bad_Opcode }, | |
5632 | { Bad_Opcode }, | |
5633 | { Bad_Opcode }, | |
5634 | { Bad_Opcode }, | |
5635 | { Bad_Opcode }, | |
5636 | { Bad_Opcode }, | |
c0f3af97 | 5637 | /* 40 */ |
592d1631 L |
5638 | { Bad_Opcode }, |
5639 | { Bad_Opcode }, | |
5640 | { Bad_Opcode }, | |
5641 | { Bad_Opcode }, | |
5642 | { Bad_Opcode }, | |
5643 | { Bad_Opcode }, | |
5644 | { Bad_Opcode }, | |
5645 | { Bad_Opcode }, | |
c1e679ec | 5646 | /* 48 */ |
592d1631 L |
5647 | { Bad_Opcode }, |
5648 | { Bad_Opcode }, | |
5649 | { Bad_Opcode }, | |
5650 | { Bad_Opcode }, | |
5651 | { Bad_Opcode }, | |
5652 | { Bad_Opcode }, | |
5653 | { Bad_Opcode }, | |
5654 | { Bad_Opcode }, | |
c1e679ec | 5655 | /* 50 */ |
592d1631 L |
5656 | { Bad_Opcode }, |
5657 | { Bad_Opcode }, | |
5658 | { Bad_Opcode }, | |
5659 | { Bad_Opcode }, | |
5660 | { Bad_Opcode }, | |
5661 | { Bad_Opcode }, | |
5662 | { Bad_Opcode }, | |
5663 | { Bad_Opcode }, | |
4e7d34a6 | 5664 | /* 58 */ |
592d1631 L |
5665 | { Bad_Opcode }, |
5666 | { Bad_Opcode }, | |
5667 | { Bad_Opcode }, | |
5668 | { Bad_Opcode }, | |
5669 | { Bad_Opcode }, | |
5670 | { Bad_Opcode }, | |
5671 | { Bad_Opcode }, | |
5672 | { Bad_Opcode }, | |
4e7d34a6 | 5673 | /* 60 */ |
592d1631 L |
5674 | { Bad_Opcode }, |
5675 | { Bad_Opcode }, | |
5676 | { Bad_Opcode }, | |
5677 | { Bad_Opcode }, | |
5678 | { Bad_Opcode }, | |
5679 | { Bad_Opcode }, | |
5680 | { Bad_Opcode }, | |
5681 | { Bad_Opcode }, | |
4e7d34a6 | 5682 | /* 68 */ |
592d1631 L |
5683 | { Bad_Opcode }, |
5684 | { Bad_Opcode }, | |
5685 | { Bad_Opcode }, | |
5686 | { Bad_Opcode }, | |
5687 | { Bad_Opcode }, | |
5688 | { Bad_Opcode }, | |
5689 | { Bad_Opcode }, | |
5690 | { Bad_Opcode }, | |
4e7d34a6 | 5691 | /* 70 */ |
592d1631 L |
5692 | { Bad_Opcode }, |
5693 | { Bad_Opcode }, | |
5694 | { Bad_Opcode }, | |
5695 | { Bad_Opcode }, | |
5696 | { Bad_Opcode }, | |
5697 | { Bad_Opcode }, | |
5698 | { Bad_Opcode }, | |
5699 | { Bad_Opcode }, | |
4e7d34a6 | 5700 | /* 78 */ |
592d1631 L |
5701 | { Bad_Opcode }, |
5702 | { Bad_Opcode }, | |
5703 | { Bad_Opcode }, | |
5704 | { Bad_Opcode }, | |
5705 | { Bad_Opcode }, | |
5706 | { Bad_Opcode }, | |
5707 | { Bad_Opcode }, | |
5708 | { Bad_Opcode }, | |
4e7d34a6 | 5709 | /* 80 */ |
592d1631 L |
5710 | { Bad_Opcode }, |
5711 | { Bad_Opcode }, | |
5712 | { Bad_Opcode }, | |
5713 | { Bad_Opcode }, | |
5714 | { Bad_Opcode }, | |
5715 | { Bad_Opcode }, | |
5716 | { Bad_Opcode }, | |
5717 | { Bad_Opcode }, | |
4e7d34a6 | 5718 | /* 88 */ |
592d1631 L |
5719 | { Bad_Opcode }, |
5720 | { Bad_Opcode }, | |
5721 | { Bad_Opcode }, | |
5722 | { Bad_Opcode }, | |
5723 | { Bad_Opcode }, | |
5724 | { Bad_Opcode }, | |
5725 | { Bad_Opcode }, | |
5726 | { Bad_Opcode }, | |
4e7d34a6 | 5727 | /* 90 */ |
592d1631 L |
5728 | { Bad_Opcode }, |
5729 | { Bad_Opcode }, | |
5730 | { Bad_Opcode }, | |
5731 | { Bad_Opcode }, | |
5732 | { Bad_Opcode }, | |
5733 | { Bad_Opcode }, | |
5734 | { Bad_Opcode }, | |
5735 | { Bad_Opcode }, | |
4e7d34a6 | 5736 | /* 98 */ |
592d1631 L |
5737 | { Bad_Opcode }, |
5738 | { Bad_Opcode }, | |
5739 | { Bad_Opcode }, | |
5740 | { Bad_Opcode }, | |
5741 | { Bad_Opcode }, | |
5742 | { Bad_Opcode }, | |
5743 | { Bad_Opcode }, | |
5744 | { Bad_Opcode }, | |
4e7d34a6 | 5745 | /* a0 */ |
592d1631 L |
5746 | { Bad_Opcode }, |
5747 | { Bad_Opcode }, | |
5748 | { Bad_Opcode }, | |
5749 | { Bad_Opcode }, | |
5750 | { Bad_Opcode }, | |
5751 | { Bad_Opcode }, | |
5752 | { Bad_Opcode }, | |
5753 | { Bad_Opcode }, | |
4e7d34a6 | 5754 | /* a8 */ |
592d1631 L |
5755 | { Bad_Opcode }, |
5756 | { Bad_Opcode }, | |
5757 | { Bad_Opcode }, | |
5758 | { Bad_Opcode }, | |
5759 | { Bad_Opcode }, | |
5760 | { Bad_Opcode }, | |
5761 | { Bad_Opcode }, | |
5762 | { Bad_Opcode }, | |
d5d7db8e | 5763 | /* b0 */ |
592d1631 L |
5764 | { Bad_Opcode }, |
5765 | { Bad_Opcode }, | |
5766 | { Bad_Opcode }, | |
5767 | { Bad_Opcode }, | |
5768 | { Bad_Opcode }, | |
5769 | { Bad_Opcode }, | |
5770 | { Bad_Opcode }, | |
5771 | { Bad_Opcode }, | |
85f10a01 | 5772 | /* b8 */ |
592d1631 L |
5773 | { Bad_Opcode }, |
5774 | { Bad_Opcode }, | |
5775 | { Bad_Opcode }, | |
5776 | { Bad_Opcode }, | |
5777 | { Bad_Opcode }, | |
5778 | { Bad_Opcode }, | |
5779 | { Bad_Opcode }, | |
5780 | { Bad_Opcode }, | |
85f10a01 | 5781 | /* c0 */ |
592d1631 L |
5782 | { Bad_Opcode }, |
5783 | { Bad_Opcode }, | |
5784 | { Bad_Opcode }, | |
5785 | { Bad_Opcode }, | |
5786 | { Bad_Opcode }, | |
5787 | { Bad_Opcode }, | |
5788 | { Bad_Opcode }, | |
5789 | { Bad_Opcode }, | |
85f10a01 | 5790 | /* c8 */ |
592d1631 L |
5791 | { Bad_Opcode }, |
5792 | { Bad_Opcode }, | |
5793 | { Bad_Opcode }, | |
5794 | { Bad_Opcode }, | |
5795 | { Bad_Opcode }, | |
5796 | { Bad_Opcode }, | |
5797 | { Bad_Opcode }, | |
5798 | { Bad_Opcode }, | |
85f10a01 | 5799 | /* d0 */ |
592d1631 L |
5800 | { Bad_Opcode }, |
5801 | { Bad_Opcode }, | |
5802 | { Bad_Opcode }, | |
5803 | { Bad_Opcode }, | |
5804 | { Bad_Opcode }, | |
5805 | { Bad_Opcode }, | |
5806 | { Bad_Opcode }, | |
5807 | { Bad_Opcode }, | |
85f10a01 | 5808 | /* d8 */ |
592d1631 L |
5809 | { Bad_Opcode }, |
5810 | { Bad_Opcode }, | |
5811 | { Bad_Opcode }, | |
5812 | { Bad_Opcode }, | |
5813 | { Bad_Opcode }, | |
5814 | { Bad_Opcode }, | |
5815 | { Bad_Opcode }, | |
5816 | { Bad_Opcode }, | |
85f10a01 | 5817 | /* e0 */ |
592d1631 L |
5818 | { Bad_Opcode }, |
5819 | { Bad_Opcode }, | |
5820 | { Bad_Opcode }, | |
5821 | { Bad_Opcode }, | |
5822 | { Bad_Opcode }, | |
5823 | { Bad_Opcode }, | |
5824 | { Bad_Opcode }, | |
5825 | { Bad_Opcode }, | |
85f10a01 | 5826 | /* e8 */ |
592d1631 L |
5827 | { Bad_Opcode }, |
5828 | { Bad_Opcode }, | |
5829 | { Bad_Opcode }, | |
5830 | { Bad_Opcode }, | |
5831 | { Bad_Opcode }, | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
5834 | { Bad_Opcode }, | |
85f10a01 | 5835 | /* f0 */ |
592d1631 L |
5836 | { Bad_Opcode }, |
5837 | { Bad_Opcode }, | |
5838 | { Bad_Opcode }, | |
5839 | { Bad_Opcode }, | |
5840 | { Bad_Opcode }, | |
5841 | { Bad_Opcode }, | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
85f10a01 | 5844 | /* f8 */ |
592d1631 L |
5845 | { Bad_Opcode }, |
5846 | { Bad_Opcode }, | |
5847 | { Bad_Opcode }, | |
5848 | { Bad_Opcode }, | |
5849 | { Bad_Opcode }, | |
5850 | { Bad_Opcode }, | |
5851 | { Bad_Opcode }, | |
5852 | { Bad_Opcode }, | |
85f10a01 | 5853 | }, |
c0f3af97 L |
5854 | }; |
5855 | ||
5856 | static const struct dis386 vex_table[][256] = { | |
5857 | /* VEX_0F */ | |
85f10a01 MM |
5858 | { |
5859 | /* 00 */ | |
592d1631 L |
5860 | { Bad_Opcode }, |
5861 | { Bad_Opcode }, | |
5862 | { Bad_Opcode }, | |
5863 | { Bad_Opcode }, | |
5864 | { Bad_Opcode }, | |
5865 | { Bad_Opcode }, | |
5866 | { Bad_Opcode }, | |
5867 | { Bad_Opcode }, | |
85f10a01 | 5868 | /* 08 */ |
592d1631 L |
5869 | { Bad_Opcode }, |
5870 | { Bad_Opcode }, | |
5871 | { Bad_Opcode }, | |
5872 | { Bad_Opcode }, | |
5873 | { Bad_Opcode }, | |
5874 | { Bad_Opcode }, | |
5875 | { Bad_Opcode }, | |
5876 | { Bad_Opcode }, | |
c0f3af97 | 5877 | /* 10 */ |
592a252b L |
5878 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
5879 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
5880 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
5881 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
5882 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5883 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
5884 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
5885 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 5886 | /* 18 */ |
592d1631 L |
5887 | { Bad_Opcode }, |
5888 | { Bad_Opcode }, | |
5889 | { Bad_Opcode }, | |
5890 | { Bad_Opcode }, | |
5891 | { Bad_Opcode }, | |
5892 | { Bad_Opcode }, | |
5893 | { Bad_Opcode }, | |
5894 | { Bad_Opcode }, | |
c0f3af97 | 5895 | /* 20 */ |
592d1631 L |
5896 | { Bad_Opcode }, |
5897 | { Bad_Opcode }, | |
5898 | { Bad_Opcode }, | |
5899 | { Bad_Opcode }, | |
5900 | { Bad_Opcode }, | |
5901 | { Bad_Opcode }, | |
5902 | { Bad_Opcode }, | |
5903 | { Bad_Opcode }, | |
c0f3af97 | 5904 | /* 28 */ |
bf926894 JB |
5905 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
5906 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
5907 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
5908 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
5909 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
5910 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
5911 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
5912 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 5913 | /* 30 */ |
592d1631 L |
5914 | { Bad_Opcode }, |
5915 | { Bad_Opcode }, | |
5916 | { Bad_Opcode }, | |
5917 | { Bad_Opcode }, | |
5918 | { Bad_Opcode }, | |
5919 | { Bad_Opcode }, | |
5920 | { Bad_Opcode }, | |
5921 | { Bad_Opcode }, | |
4e7d34a6 | 5922 | /* 38 */ |
592d1631 L |
5923 | { Bad_Opcode }, |
5924 | { Bad_Opcode }, | |
5925 | { Bad_Opcode }, | |
5926 | { Bad_Opcode }, | |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
d5d7db8e | 5931 | /* 40 */ |
592d1631 | 5932 | { Bad_Opcode }, |
43234a1e L |
5933 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
5934 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 5935 | { Bad_Opcode }, |
43234a1e L |
5936 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
5937 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
5938 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
5939 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 5940 | /* 48 */ |
592d1631 L |
5941 | { Bad_Opcode }, |
5942 | { Bad_Opcode }, | |
1ba585e8 | 5943 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 5944 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
5945 | { Bad_Opcode }, |
5946 | { Bad_Opcode }, | |
5947 | { Bad_Opcode }, | |
5948 | { Bad_Opcode }, | |
d5d7db8e | 5949 | /* 50 */ |
592a252b L |
5950 | { MOD_TABLE (MOD_VEX_0F50) }, |
5951 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
5952 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
5953 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
5954 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5955 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
5956 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
5957 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 5958 | /* 58 */ |
592a252b L |
5959 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
5960 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
5961 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
5962 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
5963 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
5964 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
5965 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
5966 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 5967 | /* 60 */ |
7531c613 JB |
5968 | { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA }, |
5969 | { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5970 | { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5971 | { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5972 | { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA }, | |
5973 | { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5974 | { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5975 | { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 5976 | /* 68 */ |
7531c613 JB |
5977 | { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA }, |
5978 | { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
5979 | { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5980 | { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5981 | { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5982 | { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
5983 | { VEX_LEN_TABLE (VEX_LEN_0F6E) }, | |
592a252b | 5984 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
c0f3af97 | 5985 | /* 70 */ |
592a252b L |
5986 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
5987 | { REG_TABLE (REG_VEX_0F71) }, | |
5988 | { REG_TABLE (REG_VEX_0F72) }, | |
5989 | { REG_TABLE (REG_VEX_0F73) }, | |
7531c613 JB |
5990 | { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA }, |
5991 | { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA }, | |
5992 | { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA }, | |
035e7389 | 5993 | { VEX_LEN_TABLE (VEX_LEN_0F77) }, |
c0f3af97 | 5994 | /* 78 */ |
592d1631 L |
5995 | { Bad_Opcode }, |
5996 | { Bad_Opcode }, | |
5997 | { Bad_Opcode }, | |
5998 | { Bad_Opcode }, | |
592a252b L |
5999 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
6000 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
6001 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
6002 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 6003 | /* 80 */ |
592d1631 L |
6004 | { Bad_Opcode }, |
6005 | { Bad_Opcode }, | |
6006 | { Bad_Opcode }, | |
6007 | { Bad_Opcode }, | |
6008 | { Bad_Opcode }, | |
6009 | { Bad_Opcode }, | |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
c0f3af97 | 6012 | /* 88 */ |
592d1631 L |
6013 | { Bad_Opcode }, |
6014 | { Bad_Opcode }, | |
6015 | { Bad_Opcode }, | |
6016 | { Bad_Opcode }, | |
6017 | { Bad_Opcode }, | |
6018 | { Bad_Opcode }, | |
6019 | { Bad_Opcode }, | |
6020 | { Bad_Opcode }, | |
c0f3af97 | 6021 | /* 90 */ |
43234a1e L |
6022 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
6023 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
6024 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
6025 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
6026 | { Bad_Opcode }, |
6027 | { Bad_Opcode }, | |
6028 | { Bad_Opcode }, | |
6029 | { Bad_Opcode }, | |
c0f3af97 | 6030 | /* 98 */ |
43234a1e | 6031 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 6032 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
6033 | { Bad_Opcode }, |
6034 | { Bad_Opcode }, | |
6035 | { Bad_Opcode }, | |
6036 | { Bad_Opcode }, | |
6037 | { Bad_Opcode }, | |
6038 | { Bad_Opcode }, | |
c0f3af97 | 6039 | /* a0 */ |
592d1631 L |
6040 | { Bad_Opcode }, |
6041 | { Bad_Opcode }, | |
6042 | { Bad_Opcode }, | |
6043 | { Bad_Opcode }, | |
6044 | { Bad_Opcode }, | |
6045 | { Bad_Opcode }, | |
6046 | { Bad_Opcode }, | |
6047 | { Bad_Opcode }, | |
c0f3af97 | 6048 | /* a8 */ |
592d1631 L |
6049 | { Bad_Opcode }, |
6050 | { Bad_Opcode }, | |
6051 | { Bad_Opcode }, | |
6052 | { Bad_Opcode }, | |
6053 | { Bad_Opcode }, | |
6054 | { Bad_Opcode }, | |
592a252b | 6055 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 6056 | { Bad_Opcode }, |
c0f3af97 | 6057 | /* b0 */ |
592d1631 L |
6058 | { Bad_Opcode }, |
6059 | { Bad_Opcode }, | |
6060 | { Bad_Opcode }, | |
6061 | { Bad_Opcode }, | |
6062 | { Bad_Opcode }, | |
6063 | { Bad_Opcode }, | |
6064 | { Bad_Opcode }, | |
6065 | { Bad_Opcode }, | |
c0f3af97 | 6066 | /* b8 */ |
592d1631 L |
6067 | { Bad_Opcode }, |
6068 | { Bad_Opcode }, | |
6069 | { Bad_Opcode }, | |
6070 | { Bad_Opcode }, | |
6071 | { Bad_Opcode }, | |
6072 | { Bad_Opcode }, | |
6073 | { Bad_Opcode }, | |
6074 | { Bad_Opcode }, | |
c0f3af97 | 6075 | /* c0 */ |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
592a252b | 6078 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 6079 | { Bad_Opcode }, |
7531c613 JB |
6080 | { VEX_LEN_TABLE (VEX_LEN_0FC4) }, |
6081 | { VEX_LEN_TABLE (VEX_LEN_0FC5) }, | |
bf926894 | 6082 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 6083 | { Bad_Opcode }, |
c0f3af97 | 6084 | /* c8 */ |
592d1631 L |
6085 | { Bad_Opcode }, |
6086 | { Bad_Opcode }, | |
6087 | { Bad_Opcode }, | |
6088 | { Bad_Opcode }, | |
6089 | { Bad_Opcode }, | |
6090 | { Bad_Opcode }, | |
6091 | { Bad_Opcode }, | |
6092 | { Bad_Opcode }, | |
c0f3af97 | 6093 | /* d0 */ |
592a252b | 6094 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
7531c613 JB |
6095 | { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
6096 | { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6097 | { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6098 | { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6099 | { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6100 | { VEX_LEN_TABLE (VEX_LEN_0FD6) }, | |
6101 | { MOD_TABLE (MOD_VEX_0FD7) }, | |
c0f3af97 | 6102 | /* d8 */ |
7531c613 JB |
6103 | { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA }, |
6104 | { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6105 | { "vpminub", { XM, Vex, EXx }, PREFIX_DATA }, | |
6106 | { "vpand", { XM, Vex, EXx }, PREFIX_DATA }, | |
6107 | { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6108 | { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6109 | { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA }, | |
6110 | { "vpandn", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6111 | /* e0 */ |
7531c613 JB |
6112 | { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA }, |
6113 | { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6114 | { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6115 | { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6116 | { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6117 | { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA }, | |
592a252b | 6118 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, |
7531c613 | 6119 | { MOD_TABLE (MOD_VEX_0FE7) }, |
c0f3af97 | 6120 | /* e8 */ |
7531c613 JB |
6121 | { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6122 | { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6123 | { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6124 | { "vpor", { XM, Vex, EXx }, PREFIX_DATA }, | |
6125 | { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6126 | { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6127 | { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6128 | { "vpxor", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6129 | /* f0 */ |
592a252b | 6130 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
7531c613 JB |
6131 | { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
6132 | { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6133 | { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6134 | { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6135 | { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6136 | { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6137 | { VEX_LEN_TABLE (VEX_LEN_0FF7) }, | |
c0f3af97 | 6138 | /* f8 */ |
7531c613 JB |
6139 | { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA }, |
6140 | { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6141 | { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6142 | { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6143 | { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6144 | { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6145 | { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
592d1631 | 6146 | { Bad_Opcode }, |
c0f3af97 L |
6147 | }, |
6148 | /* VEX_0F38 */ | |
6149 | { | |
6150 | /* 00 */ | |
7531c613 JB |
6151 | { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA }, |
6152 | { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6153 | { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6154 | { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6155 | { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6156 | { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6157 | { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6158 | { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6159 | /* 08 */ |
7531c613 JB |
6160 | { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA }, |
6161 | { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6162 | { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6163 | { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6164 | { VEX_W_TABLE (VEX_W_0F380C) }, | |
6165 | { VEX_W_TABLE (VEX_W_0F380D) }, | |
6166 | { VEX_W_TABLE (VEX_W_0F380E) }, | |
6167 | { VEX_W_TABLE (VEX_W_0F380F) }, | |
c0f3af97 | 6168 | /* 10 */ |
592d1631 L |
6169 | { Bad_Opcode }, |
6170 | { Bad_Opcode }, | |
6171 | { Bad_Opcode }, | |
7531c613 | 6172 | { VEX_W_TABLE (VEX_W_0F3813) }, |
592d1631 L |
6173 | { Bad_Opcode }, |
6174 | { Bad_Opcode }, | |
7531c613 JB |
6175 | { VEX_LEN_TABLE (VEX_LEN_0F3816) }, |
6176 | { "vptest", { XM, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6177 | /* 18 */ |
7531c613 JB |
6178 | { VEX_W_TABLE (VEX_W_0F3818) }, |
6179 | { VEX_LEN_TABLE (VEX_LEN_0F3819) }, | |
6180 | { MOD_TABLE (MOD_VEX_0F381A) }, | |
592d1631 | 6181 | { Bad_Opcode }, |
7531c613 JB |
6182 | { "vpabsb", { XM, EXx }, PREFIX_DATA }, |
6183 | { "vpabsw", { XM, EXx }, PREFIX_DATA }, | |
6184 | { "vpabsd", { XM, EXx }, PREFIX_DATA }, | |
592d1631 | 6185 | { Bad_Opcode }, |
c0f3af97 | 6186 | /* 20 */ |
7531c613 JB |
6187 | { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6188 | { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6189 | { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6190 | { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6191 | { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6192 | { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
592d1631 L |
6193 | { Bad_Opcode }, |
6194 | { Bad_Opcode }, | |
c0f3af97 | 6195 | /* 28 */ |
7531c613 JB |
6196 | { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA }, |
6197 | { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6198 | { MOD_TABLE (MOD_VEX_0F382A) }, | |
6199 | { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6200 | { MOD_TABLE (MOD_VEX_0F382C) }, | |
6201 | { MOD_TABLE (MOD_VEX_0F382D) }, | |
6202 | { MOD_TABLE (MOD_VEX_0F382E) }, | |
6203 | { MOD_TABLE (MOD_VEX_0F382F) }, | |
c0f3af97 | 6204 | /* 30 */ |
7531c613 JB |
6205 | { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6206 | { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6207 | { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6208 | { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6209 | { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6210 | { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
6211 | { VEX_LEN_TABLE (VEX_LEN_0F3836) }, | |
6212 | { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6213 | /* 38 */ |
7531c613 JB |
6214 | { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6215 | { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6216 | { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6217 | { "vpminud", { XM, Vex, EXx }, PREFIX_DATA }, | |
6218 | { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6219 | { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6220 | { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6221 | { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6222 | /* 40 */ |
7531c613 JB |
6223 | { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA }, |
6224 | { VEX_LEN_TABLE (VEX_LEN_0F3841) }, | |
592d1631 L |
6225 | { Bad_Opcode }, |
6226 | { Bad_Opcode }, | |
6227 | { Bad_Opcode }, | |
7531c613 JB |
6228 | { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, |
6229 | { VEX_W_TABLE (VEX_W_0F3846) }, | |
6230 | { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6231 | /* 48 */ |
592d1631 | 6232 | { Bad_Opcode }, |
260cd341 | 6233 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 6234 | { Bad_Opcode }, |
260cd341 | 6235 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
6236 | { Bad_Opcode }, |
6237 | { Bad_Opcode }, | |
6238 | { Bad_Opcode }, | |
6239 | { Bad_Opcode }, | |
c0f3af97 | 6240 | /* 50 */ |
58bf9b6a L |
6241 | { VEX_W_TABLE (VEX_W_0F3850) }, |
6242 | { VEX_W_TABLE (VEX_W_0F3851) }, | |
6243 | { VEX_W_TABLE (VEX_W_0F3852) }, | |
6244 | { VEX_W_TABLE (VEX_W_0F3853) }, | |
592d1631 L |
6245 | { Bad_Opcode }, |
6246 | { Bad_Opcode }, | |
6247 | { Bad_Opcode }, | |
6248 | { Bad_Opcode }, | |
c0f3af97 | 6249 | /* 58 */ |
7531c613 JB |
6250 | { VEX_W_TABLE (VEX_W_0F3858) }, |
6251 | { VEX_W_TABLE (VEX_W_0F3859) }, | |
6252 | { MOD_TABLE (MOD_VEX_0F385A) }, | |
592d1631 | 6253 | { Bad_Opcode }, |
260cd341 | 6254 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 6255 | { Bad_Opcode }, |
260cd341 | 6256 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 6257 | { Bad_Opcode }, |
c0f3af97 | 6258 | /* 60 */ |
592d1631 L |
6259 | { Bad_Opcode }, |
6260 | { Bad_Opcode }, | |
6261 | { Bad_Opcode }, | |
6262 | { Bad_Opcode }, | |
6263 | { Bad_Opcode }, | |
6264 | { Bad_Opcode }, | |
6265 | { Bad_Opcode }, | |
6266 | { Bad_Opcode }, | |
c0f3af97 | 6267 | /* 68 */ |
592d1631 L |
6268 | { Bad_Opcode }, |
6269 | { Bad_Opcode }, | |
6270 | { Bad_Opcode }, | |
6271 | { Bad_Opcode }, | |
6272 | { Bad_Opcode }, | |
6273 | { Bad_Opcode }, | |
6274 | { Bad_Opcode }, | |
6275 | { Bad_Opcode }, | |
c0f3af97 | 6276 | /* 70 */ |
592d1631 L |
6277 | { Bad_Opcode }, |
6278 | { Bad_Opcode }, | |
6279 | { Bad_Opcode }, | |
6280 | { Bad_Opcode }, | |
6281 | { Bad_Opcode }, | |
6282 | { Bad_Opcode }, | |
6283 | { Bad_Opcode }, | |
6284 | { Bad_Opcode }, | |
c0f3af97 | 6285 | /* 78 */ |
7531c613 JB |
6286 | { VEX_W_TABLE (VEX_W_0F3878) }, |
6287 | { VEX_W_TABLE (VEX_W_0F3879) }, | |
592d1631 L |
6288 | { Bad_Opcode }, |
6289 | { Bad_Opcode }, | |
6290 | { Bad_Opcode }, | |
6291 | { Bad_Opcode }, | |
6292 | { Bad_Opcode }, | |
6293 | { Bad_Opcode }, | |
c0f3af97 | 6294 | /* 80 */ |
592d1631 L |
6295 | { Bad_Opcode }, |
6296 | { Bad_Opcode }, | |
6297 | { Bad_Opcode }, | |
6298 | { Bad_Opcode }, | |
6299 | { Bad_Opcode }, | |
6300 | { Bad_Opcode }, | |
6301 | { Bad_Opcode }, | |
6302 | { Bad_Opcode }, | |
c0f3af97 | 6303 | /* 88 */ |
592d1631 L |
6304 | { Bad_Opcode }, |
6305 | { Bad_Opcode }, | |
6306 | { Bad_Opcode }, | |
6307 | { Bad_Opcode }, | |
7531c613 | 6308 | { MOD_TABLE (MOD_VEX_0F388C) }, |
592d1631 | 6309 | { Bad_Opcode }, |
7531c613 | 6310 | { MOD_TABLE (MOD_VEX_0F388E) }, |
592d1631 | 6311 | { Bad_Opcode }, |
c0f3af97 | 6312 | /* 90 */ |
7531c613 JB |
6313 | { "vpgatherd%DQ", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA }, |
6314 | { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, | |
6315 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, PREFIX_DATA }, | |
6316 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, | |
592d1631 L |
6317 | { Bad_Opcode }, |
6318 | { Bad_Opcode }, | |
7531c613 JB |
6319 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6320 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6321 | /* 98 */ |
7531c613 JB |
6322 | { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6323 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6324 | { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6325 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6326 | { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6327 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6328 | { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6329 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6330 | /* a0 */ |
592d1631 L |
6331 | { Bad_Opcode }, |
6332 | { Bad_Opcode }, | |
6333 | { Bad_Opcode }, | |
6334 | { Bad_Opcode }, | |
6335 | { Bad_Opcode }, | |
6336 | { Bad_Opcode }, | |
7531c613 JB |
6337 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6338 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6339 | /* a8 */ |
7531c613 JB |
6340 | { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6341 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6342 | { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6343 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6344 | { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6345 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6346 | { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6347 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6348 | /* b0 */ |
592d1631 L |
6349 | { Bad_Opcode }, |
6350 | { Bad_Opcode }, | |
6351 | { Bad_Opcode }, | |
6352 | { Bad_Opcode }, | |
6353 | { Bad_Opcode }, | |
6354 | { Bad_Opcode }, | |
7531c613 JB |
6355 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6356 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6357 | /* b8 */ |
7531c613 JB |
6358 | { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6359 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6360 | { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6361 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6362 | { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6363 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
6364 | { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
6365 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, PREFIX_DATA }, | |
c0f3af97 | 6366 | /* c0 */ |
592d1631 L |
6367 | { Bad_Opcode }, |
6368 | { Bad_Opcode }, | |
6369 | { Bad_Opcode }, | |
6370 | { Bad_Opcode }, | |
6371 | { Bad_Opcode }, | |
6372 | { Bad_Opcode }, | |
6373 | { Bad_Opcode }, | |
6374 | { Bad_Opcode }, | |
c0f3af97 | 6375 | /* c8 */ |
592d1631 L |
6376 | { Bad_Opcode }, |
6377 | { Bad_Opcode }, | |
6378 | { Bad_Opcode }, | |
6379 | { Bad_Opcode }, | |
6380 | { Bad_Opcode }, | |
6381 | { Bad_Opcode }, | |
6382 | { Bad_Opcode }, | |
7531c613 | 6383 | { VEX_W_TABLE (VEX_W_0F38CF) }, |
c0f3af97 | 6384 | /* d0 */ |
592d1631 L |
6385 | { Bad_Opcode }, |
6386 | { Bad_Opcode }, | |
6387 | { Bad_Opcode }, | |
6388 | { Bad_Opcode }, | |
6389 | { Bad_Opcode }, | |
6390 | { Bad_Opcode }, | |
6391 | { Bad_Opcode }, | |
6392 | { Bad_Opcode }, | |
c0f3af97 | 6393 | /* d8 */ |
592d1631 L |
6394 | { Bad_Opcode }, |
6395 | { Bad_Opcode }, | |
6396 | { Bad_Opcode }, | |
7531c613 JB |
6397 | { VEX_LEN_TABLE (VEX_LEN_0F38DB) }, |
6398 | { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA }, | |
6399 | { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
6400 | { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, | |
6401 | { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6402 | /* e0 */ |
592d1631 L |
6403 | { Bad_Opcode }, |
6404 | { Bad_Opcode }, | |
6405 | { Bad_Opcode }, | |
6406 | { Bad_Opcode }, | |
6407 | { Bad_Opcode }, | |
6408 | { Bad_Opcode }, | |
6409 | { Bad_Opcode }, | |
6410 | { Bad_Opcode }, | |
c0f3af97 | 6411 | /* e8 */ |
592d1631 L |
6412 | { Bad_Opcode }, |
6413 | { Bad_Opcode }, | |
6414 | { Bad_Opcode }, | |
6415 | { Bad_Opcode }, | |
6416 | { Bad_Opcode }, | |
6417 | { Bad_Opcode }, | |
6418 | { Bad_Opcode }, | |
6419 | { Bad_Opcode }, | |
c0f3af97 | 6420 | /* f0 */ |
592d1631 L |
6421 | { Bad_Opcode }, |
6422 | { Bad_Opcode }, | |
035e7389 | 6423 | { VEX_LEN_TABLE (VEX_LEN_0F38F2) }, |
f12dc422 | 6424 | { REG_TABLE (REG_VEX_0F38F3) }, |
592d1631 | 6425 | { Bad_Opcode }, |
6c30d220 L |
6426 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
6427 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 6428 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 6429 | /* f8 */ |
592d1631 L |
6430 | { Bad_Opcode }, |
6431 | { Bad_Opcode }, | |
6432 | { Bad_Opcode }, | |
6433 | { Bad_Opcode }, | |
6434 | { Bad_Opcode }, | |
6435 | { Bad_Opcode }, | |
6436 | { Bad_Opcode }, | |
6437 | { Bad_Opcode }, | |
c0f3af97 L |
6438 | }, |
6439 | /* VEX_0F3A */ | |
6440 | { | |
6441 | /* 00 */ | |
7531c613 JB |
6442 | { VEX_LEN_TABLE (VEX_LEN_0F3A00) }, |
6443 | { VEX_LEN_TABLE (VEX_LEN_0F3A01) }, | |
6444 | { VEX_W_TABLE (VEX_W_0F3A02) }, | |
592d1631 | 6445 | { Bad_Opcode }, |
7531c613 JB |
6446 | { VEX_W_TABLE (VEX_W_0F3A04) }, |
6447 | { VEX_W_TABLE (VEX_W_0F3A05) }, | |
6448 | { VEX_LEN_TABLE (VEX_LEN_0F3A06) }, | |
592d1631 | 6449 | { Bad_Opcode }, |
c0f3af97 | 6450 | /* 08 */ |
7531c613 JB |
6451 | { "vroundps", { XM, EXx, Ib }, PREFIX_DATA }, |
6452 | { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
6453 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, PREFIX_DATA }, | |
6454 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, PREFIX_DATA }, | |
6455 | { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6456 | { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6457 | { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6458 | { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
c0f3af97 | 6459 | /* 10 */ |
592d1631 L |
6460 | { Bad_Opcode }, |
6461 | { Bad_Opcode }, | |
6462 | { Bad_Opcode }, | |
6463 | { Bad_Opcode }, | |
7531c613 JB |
6464 | { VEX_LEN_TABLE (VEX_LEN_0F3A14) }, |
6465 | { VEX_LEN_TABLE (VEX_LEN_0F3A15) }, | |
6466 | { VEX_LEN_TABLE (VEX_LEN_0F3A16) }, | |
6467 | { VEX_LEN_TABLE (VEX_LEN_0F3A17) }, | |
c0f3af97 | 6468 | /* 18 */ |
7531c613 JB |
6469 | { VEX_LEN_TABLE (VEX_LEN_0F3A18) }, |
6470 | { VEX_LEN_TABLE (VEX_LEN_0F3A19) }, | |
592d1631 L |
6471 | { Bad_Opcode }, |
6472 | { Bad_Opcode }, | |
6473 | { Bad_Opcode }, | |
7531c613 | 6474 | { VEX_W_TABLE (VEX_W_0F3A1D) }, |
592d1631 L |
6475 | { Bad_Opcode }, |
6476 | { Bad_Opcode }, | |
c0f3af97 | 6477 | /* 20 */ |
7531c613 JB |
6478 | { VEX_LEN_TABLE (VEX_LEN_0F3A20) }, |
6479 | { VEX_LEN_TABLE (VEX_LEN_0F3A21) }, | |
6480 | { VEX_LEN_TABLE (VEX_LEN_0F3A22) }, | |
592d1631 L |
6481 | { Bad_Opcode }, |
6482 | { Bad_Opcode }, | |
6483 | { Bad_Opcode }, | |
6484 | { Bad_Opcode }, | |
6485 | { Bad_Opcode }, | |
c0f3af97 | 6486 | /* 28 */ |
592d1631 L |
6487 | { Bad_Opcode }, |
6488 | { Bad_Opcode }, | |
6489 | { Bad_Opcode }, | |
6490 | { Bad_Opcode }, | |
6491 | { Bad_Opcode }, | |
6492 | { Bad_Opcode }, | |
6493 | { Bad_Opcode }, | |
6494 | { Bad_Opcode }, | |
c0f3af97 | 6495 | /* 30 */ |
7531c613 JB |
6496 | { VEX_LEN_TABLE (VEX_LEN_0F3A30) }, |
6497 | { VEX_LEN_TABLE (VEX_LEN_0F3A31) }, | |
6498 | { VEX_LEN_TABLE (VEX_LEN_0F3A32) }, | |
6499 | { VEX_LEN_TABLE (VEX_LEN_0F3A33) }, | |
592d1631 L |
6500 | { Bad_Opcode }, |
6501 | { Bad_Opcode }, | |
6502 | { Bad_Opcode }, | |
6503 | { Bad_Opcode }, | |
c0f3af97 | 6504 | /* 38 */ |
7531c613 JB |
6505 | { VEX_LEN_TABLE (VEX_LEN_0F3A38) }, |
6506 | { VEX_LEN_TABLE (VEX_LEN_0F3A39) }, | |
592d1631 L |
6507 | { Bad_Opcode }, |
6508 | { Bad_Opcode }, | |
6509 | { Bad_Opcode }, | |
6510 | { Bad_Opcode }, | |
6511 | { Bad_Opcode }, | |
6512 | { Bad_Opcode }, | |
c0f3af97 | 6513 | /* 40 */ |
7531c613 JB |
6514 | { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
6515 | { VEX_LEN_TABLE (VEX_LEN_0F3A41) }, | |
6516 | { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 6517 | { Bad_Opcode }, |
7531c613 | 6518 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 | 6519 | { Bad_Opcode }, |
7531c613 | 6520 | { VEX_LEN_TABLE (VEX_LEN_0F3A46) }, |
592d1631 | 6521 | { Bad_Opcode }, |
c0f3af97 | 6522 | /* 48 */ |
7531c613 JB |
6523 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, |
6524 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, | |
6525 | { VEX_W_TABLE (VEX_W_0F3A4A) }, | |
6526 | { VEX_W_TABLE (VEX_W_0F3A4B) }, | |
6527 | { VEX_W_TABLE (VEX_W_0F3A4C) }, | |
592d1631 L |
6528 | { Bad_Opcode }, |
6529 | { Bad_Opcode }, | |
6530 | { Bad_Opcode }, | |
c0f3af97 | 6531 | /* 50 */ |
592d1631 L |
6532 | { Bad_Opcode }, |
6533 | { Bad_Opcode }, | |
6534 | { Bad_Opcode }, | |
6535 | { Bad_Opcode }, | |
6536 | { Bad_Opcode }, | |
6537 | { Bad_Opcode }, | |
6538 | { Bad_Opcode }, | |
6539 | { Bad_Opcode }, | |
c0f3af97 | 6540 | /* 58 */ |
592d1631 L |
6541 | { Bad_Opcode }, |
6542 | { Bad_Opcode }, | |
6543 | { Bad_Opcode }, | |
6544 | { Bad_Opcode }, | |
7531c613 JB |
6545 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6546 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6547 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6548 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c0f3af97 | 6549 | /* 60 */ |
7531c613 JB |
6550 | { VEX_LEN_TABLE (VEX_LEN_0F3A60) }, |
6551 | { VEX_LEN_TABLE (VEX_LEN_0F3A61) }, | |
6552 | { VEX_LEN_TABLE (VEX_LEN_0F3A62) }, | |
6553 | { VEX_LEN_TABLE (VEX_LEN_0F3A63) }, | |
592d1631 L |
6554 | { Bad_Opcode }, |
6555 | { Bad_Opcode }, | |
6556 | { Bad_Opcode }, | |
6557 | { Bad_Opcode }, | |
c0f3af97 | 6558 | /* 68 */ |
7531c613 JB |
6559 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6560 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6561 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6562 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
6563 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6564 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6565 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6566 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6567 | /* 70 */ |
592d1631 L |
6568 | { Bad_Opcode }, |
6569 | { Bad_Opcode }, | |
6570 | { Bad_Opcode }, | |
6571 | { Bad_Opcode }, | |
6572 | { Bad_Opcode }, | |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
6575 | { Bad_Opcode }, | |
c0f3af97 | 6576 | /* 78 */ |
7531c613 JB |
6577 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6578 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6579 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6580 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
6581 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6582 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6583 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexScalarI4 }, PREFIX_DATA }, | |
6584 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6585 | /* 80 */ |
592d1631 L |
6586 | { Bad_Opcode }, |
6587 | { Bad_Opcode }, | |
6588 | { Bad_Opcode }, | |
6589 | { Bad_Opcode }, | |
6590 | { Bad_Opcode }, | |
6591 | { Bad_Opcode }, | |
6592 | { Bad_Opcode }, | |
6593 | { Bad_Opcode }, | |
c0f3af97 | 6594 | /* 88 */ |
592d1631 L |
6595 | { Bad_Opcode }, |
6596 | { Bad_Opcode }, | |
6597 | { Bad_Opcode }, | |
6598 | { Bad_Opcode }, | |
6599 | { Bad_Opcode }, | |
6600 | { Bad_Opcode }, | |
6601 | { Bad_Opcode }, | |
6602 | { Bad_Opcode }, | |
c0f3af97 | 6603 | /* 90 */ |
592d1631 L |
6604 | { Bad_Opcode }, |
6605 | { Bad_Opcode }, | |
6606 | { Bad_Opcode }, | |
6607 | { Bad_Opcode }, | |
6608 | { Bad_Opcode }, | |
6609 | { Bad_Opcode }, | |
6610 | { Bad_Opcode }, | |
6611 | { Bad_Opcode }, | |
c0f3af97 | 6612 | /* 98 */ |
592d1631 L |
6613 | { Bad_Opcode }, |
6614 | { Bad_Opcode }, | |
6615 | { Bad_Opcode }, | |
6616 | { Bad_Opcode }, | |
6617 | { Bad_Opcode }, | |
6618 | { Bad_Opcode }, | |
6619 | { Bad_Opcode }, | |
6620 | { Bad_Opcode }, | |
c0f3af97 | 6621 | /* a0 */ |
592d1631 L |
6622 | { Bad_Opcode }, |
6623 | { Bad_Opcode }, | |
6624 | { Bad_Opcode }, | |
6625 | { Bad_Opcode }, | |
6626 | { Bad_Opcode }, | |
6627 | { Bad_Opcode }, | |
6628 | { Bad_Opcode }, | |
6629 | { Bad_Opcode }, | |
c0f3af97 | 6630 | /* a8 */ |
592d1631 L |
6631 | { Bad_Opcode }, |
6632 | { Bad_Opcode }, | |
6633 | { Bad_Opcode }, | |
6634 | { Bad_Opcode }, | |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
c0f3af97 | 6639 | /* b0 */ |
592d1631 L |
6640 | { Bad_Opcode }, |
6641 | { Bad_Opcode }, | |
6642 | { Bad_Opcode }, | |
6643 | { Bad_Opcode }, | |
6644 | { Bad_Opcode }, | |
6645 | { Bad_Opcode }, | |
6646 | { Bad_Opcode }, | |
6647 | { Bad_Opcode }, | |
c0f3af97 | 6648 | /* b8 */ |
592d1631 L |
6649 | { Bad_Opcode }, |
6650 | { Bad_Opcode }, | |
6651 | { Bad_Opcode }, | |
6652 | { Bad_Opcode }, | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
c0f3af97 | 6657 | /* c0 */ |
592d1631 L |
6658 | { Bad_Opcode }, |
6659 | { Bad_Opcode }, | |
6660 | { Bad_Opcode }, | |
6661 | { Bad_Opcode }, | |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
c0f3af97 | 6666 | /* c8 */ |
592d1631 L |
6667 | { Bad_Opcode }, |
6668 | { Bad_Opcode }, | |
6669 | { Bad_Opcode }, | |
6670 | { Bad_Opcode }, | |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
7531c613 JB |
6673 | { VEX_W_TABLE (VEX_W_0F3ACE) }, |
6674 | { VEX_W_TABLE (VEX_W_0F3ACF) }, | |
c0f3af97 | 6675 | /* d0 */ |
592d1631 L |
6676 | { Bad_Opcode }, |
6677 | { Bad_Opcode }, | |
6678 | { Bad_Opcode }, | |
6679 | { Bad_Opcode }, | |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
c0f3af97 | 6684 | /* d8 */ |
592d1631 L |
6685 | { Bad_Opcode }, |
6686 | { Bad_Opcode }, | |
6687 | { Bad_Opcode }, | |
6688 | { Bad_Opcode }, | |
6689 | { Bad_Opcode }, | |
6690 | { Bad_Opcode }, | |
6691 | { Bad_Opcode }, | |
7531c613 | 6692 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF) }, |
c0f3af97 | 6693 | /* e0 */ |
592d1631 L |
6694 | { Bad_Opcode }, |
6695 | { Bad_Opcode }, | |
6696 | { Bad_Opcode }, | |
6697 | { Bad_Opcode }, | |
6698 | { Bad_Opcode }, | |
6699 | { Bad_Opcode }, | |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
c0f3af97 | 6702 | /* e8 */ |
592d1631 L |
6703 | { Bad_Opcode }, |
6704 | { Bad_Opcode }, | |
6705 | { Bad_Opcode }, | |
6706 | { Bad_Opcode }, | |
6707 | { Bad_Opcode }, | |
6708 | { Bad_Opcode }, | |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
c0f3af97 | 6711 | /* f0 */ |
6c30d220 | 6712 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
6713 | { Bad_Opcode }, |
6714 | { Bad_Opcode }, | |
6715 | { Bad_Opcode }, | |
6716 | { Bad_Opcode }, | |
6717 | { Bad_Opcode }, | |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
c0f3af97 | 6720 | /* f8 */ |
592d1631 L |
6721 | { Bad_Opcode }, |
6722 | { Bad_Opcode }, | |
6723 | { Bad_Opcode }, | |
6724 | { Bad_Opcode }, | |
6725 | { Bad_Opcode }, | |
6726 | { Bad_Opcode }, | |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
c0f3af97 L |
6729 | }, |
6730 | }; | |
6731 | ||
43234a1e | 6732 | #include "i386-dis-evex.h" |
ad692897 | 6733 | |
c0f3af97 | 6734 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 6735 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 6736 | { |
89e65d17 | 6737 | { "vmovlpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6738 | }, |
6739 | ||
592a252b | 6740 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 6741 | { |
89e65d17 | 6742 | { "vmovhlps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6743 | }, |
6744 | ||
592a252b | 6745 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 6746 | { |
bf926894 | 6747 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6748 | }, |
6749 | ||
18897deb | 6750 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 6751 | { |
89e65d17 | 6752 | { "vmovhpX", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6753 | }, |
6754 | ||
592a252b | 6755 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 6756 | { |
89e65d17 | 6757 | { "vmovlhps", { XM, Vex, EXq }, 0 }, |
c0f3af97 L |
6758 | }, |
6759 | ||
592a252b | 6760 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 6761 | { |
bf926894 | 6762 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6763 | }, |
6764 | ||
43234a1e L |
6765 | /* VEX_LEN_0F41_P_0 */ |
6766 | { | |
6767 | { Bad_Opcode }, | |
6768 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
6769 | }, | |
1ba585e8 IT |
6770 | /* VEX_LEN_0F41_P_2 */ |
6771 | { | |
6772 | { Bad_Opcode }, | |
6773 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
6774 | }, | |
43234a1e L |
6775 | /* VEX_LEN_0F42_P_0 */ |
6776 | { | |
6777 | { Bad_Opcode }, | |
6778 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
6779 | }, | |
1ba585e8 IT |
6780 | /* VEX_LEN_0F42_P_2 */ |
6781 | { | |
6782 | { Bad_Opcode }, | |
6783 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
6784 | }, | |
43234a1e L |
6785 | /* VEX_LEN_0F44_P_0 */ |
6786 | { | |
6787 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
6788 | }, | |
1ba585e8 IT |
6789 | /* VEX_LEN_0F44_P_2 */ |
6790 | { | |
6791 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
6792 | }, | |
43234a1e L |
6793 | /* VEX_LEN_0F45_P_0 */ |
6794 | { | |
6795 | { Bad_Opcode }, | |
6796 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
6797 | }, | |
1ba585e8 IT |
6798 | /* VEX_LEN_0F45_P_2 */ |
6799 | { | |
6800 | { Bad_Opcode }, | |
6801 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
6802 | }, | |
43234a1e L |
6803 | /* VEX_LEN_0F46_P_0 */ |
6804 | { | |
6805 | { Bad_Opcode }, | |
6806 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
6807 | }, | |
1ba585e8 IT |
6808 | /* VEX_LEN_0F46_P_2 */ |
6809 | { | |
6810 | { Bad_Opcode }, | |
6811 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
6812 | }, | |
43234a1e L |
6813 | /* VEX_LEN_0F47_P_0 */ |
6814 | { | |
6815 | { Bad_Opcode }, | |
6816 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
6817 | }, | |
1ba585e8 IT |
6818 | /* VEX_LEN_0F47_P_2 */ |
6819 | { | |
6820 | { Bad_Opcode }, | |
6821 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
6822 | }, | |
6823 | /* VEX_LEN_0F4A_P_0 */ | |
6824 | { | |
6825 | { Bad_Opcode }, | |
6826 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
6827 | }, | |
6828 | /* VEX_LEN_0F4A_P_2 */ | |
6829 | { | |
6830 | { Bad_Opcode }, | |
6831 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
6832 | }, | |
6833 | /* VEX_LEN_0F4B_P_0 */ | |
6834 | { | |
6835 | { Bad_Opcode }, | |
6836 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
6837 | }, | |
43234a1e L |
6838 | /* VEX_LEN_0F4B_P_2 */ |
6839 | { | |
6840 | { Bad_Opcode }, | |
6841 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
6842 | }, | |
6843 | ||
7531c613 | 6844 | /* VEX_LEN_0F6E */ |
c0f3af97 | 6845 | { |
7531c613 | 6846 | { "vmovK", { XMScalar, Edq }, PREFIX_DATA }, |
c0f3af97 L |
6847 | }, |
6848 | ||
035e7389 | 6849 | /* VEX_LEN_0F77 */ |
c0f3af97 | 6850 | { |
ec6f095a L |
6851 | { "vzeroupper", { XX }, 0 }, |
6852 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
6853 | }, |
6854 | ||
ec6f095a | 6855 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 6856 | { |
5b872f7d | 6857 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
6858 | }, |
6859 | ||
ec6f095a | 6860 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 6861 | { |
ec6f095a | 6862 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
6863 | }, |
6864 | ||
ec6f095a | 6865 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 6866 | { |
ec6f095a | 6867 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
6868 | }, |
6869 | ||
ec6f095a | 6870 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 6871 | { |
ec6f095a | 6872 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
6873 | }, |
6874 | ||
ec6f095a | 6875 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 6876 | { |
ec6f095a | 6877 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
6878 | }, |
6879 | ||
ec6f095a | 6880 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 6881 | { |
ec6f095a | 6882 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
6883 | }, |
6884 | ||
ec6f095a | 6885 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 6886 | { |
ec6f095a | 6887 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
6888 | }, |
6889 | ||
ec6f095a | 6890 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 6891 | { |
ec6f095a | 6892 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
6893 | }, |
6894 | ||
ec6f095a | 6895 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 6896 | { |
58a211d2 | 6897 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
6898 | }, |
6899 | ||
ec6f095a | 6900 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 6901 | { |
ec6f095a | 6902 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
6903 | }, |
6904 | ||
ec6f095a | 6905 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 6906 | { |
ec6f095a | 6907 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
6908 | }, |
6909 | ||
ec6f095a | 6910 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 6911 | { |
58a211d2 | 6912 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
6913 | }, |
6914 | ||
ec6f095a | 6915 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
6916 | { |
6917 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
6918 | }, | |
6919 | ||
1ba585e8 IT |
6920 | /* VEX_LEN_0F98_P_2 */ |
6921 | { | |
6922 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
6923 | }, | |
6924 | ||
6925 | /* VEX_LEN_0F99_P_0 */ | |
6926 | { | |
6927 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
6928 | }, | |
6929 | ||
6930 | /* VEX_LEN_0F99_P_2 */ | |
6931 | { | |
6932 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
6933 | }, | |
6934 | ||
6c30d220 | 6935 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 6936 | { |
ec6f095a | 6937 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
6938 | }, |
6939 | ||
6c30d220 | 6940 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 6941 | { |
ec6f095a | 6942 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
6943 | }, |
6944 | ||
7531c613 | 6945 | /* VEX_LEN_0FC4 */ |
c0f3af97 | 6946 | { |
7531c613 | 6947 | { "vpinsrw", { XM, Vex, Edqw, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6948 | }, |
6949 | ||
7531c613 | 6950 | /* VEX_LEN_0FC5 */ |
c0f3af97 | 6951 | { |
7531c613 | 6952 | { "vpextrw", { Gdq, XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6953 | }, |
6954 | ||
7531c613 | 6955 | /* VEX_LEN_0FD6 */ |
c0f3af97 | 6956 | { |
7531c613 | 6957 | { "vmovq", { EXqS, XMScalar }, PREFIX_DATA }, |
c0f3af97 L |
6958 | }, |
6959 | ||
7531c613 | 6960 | /* VEX_LEN_0FF7 */ |
c0f3af97 | 6961 | { |
7531c613 | 6962 | { "vmaskmovdqu", { XM, XS }, PREFIX_DATA }, |
c0f3af97 L |
6963 | }, |
6964 | ||
7531c613 | 6965 | /* VEX_LEN_0F3816 */ |
c0f3af97 | 6966 | { |
6c30d220 | 6967 | { Bad_Opcode }, |
7531c613 | 6968 | { VEX_W_TABLE (VEX_W_0F3816_L_1) }, |
c0f3af97 L |
6969 | }, |
6970 | ||
7531c613 | 6971 | /* VEX_LEN_0F3819 */ |
c0f3af97 | 6972 | { |
6c30d220 | 6973 | { Bad_Opcode }, |
7531c613 | 6974 | { VEX_W_TABLE (VEX_W_0F3819_L_1) }, |
c0f3af97 L |
6975 | }, |
6976 | ||
7531c613 | 6977 | /* VEX_LEN_0F381A_M_0 */ |
c0f3af97 | 6978 | { |
6c30d220 | 6979 | { Bad_Opcode }, |
7531c613 | 6980 | { VEX_W_TABLE (VEX_W_0F381A_M_0_L_1) }, |
c0f3af97 L |
6981 | }, |
6982 | ||
7531c613 | 6983 | /* VEX_LEN_0F3836 */ |
c0f3af97 | 6984 | { |
6c30d220 | 6985 | { Bad_Opcode }, |
7531c613 | 6986 | { VEX_W_TABLE (VEX_W_0F3836) }, |
c0f3af97 L |
6987 | }, |
6988 | ||
7531c613 | 6989 | /* VEX_LEN_0F3841 */ |
c0f3af97 | 6990 | { |
7531c613 | 6991 | { "vphminposuw", { XM, EXx }, PREFIX_DATA }, |
c0f3af97 L |
6992 | }, |
6993 | ||
260cd341 LC |
6994 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_0 */ |
6995 | { | |
6996 | { "ldtilecfg", { M }, 0 }, | |
6997 | }, | |
6998 | ||
6999 | /* VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0 */ | |
7000 | { | |
7001 | { "tilerelease", { Skip_MODRM }, 0 }, | |
7002 | }, | |
7003 | ||
7004 | /* VEX_LEN_0F3849_X86_64_P_2_W_0_M_0 */ | |
7005 | { | |
7006 | { "sttilecfg", { M }, 0 }, | |
7007 | }, | |
7008 | ||
7009 | /* VEX_LEN_0F3849_X86_64_P_3_W_0_M_0 */ | |
7010 | { | |
7011 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
7012 | }, | |
7013 | ||
7014 | /* VEX_LEN_0F384B_X86_64_P_1_W_0_M_0 */ | |
7015 | { | |
7016 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
7017 | }, | |
7018 | /* VEX_LEN_0F384B_X86_64_P_2_W_0_M_0 */ | |
7019 | { | |
7020 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
7021 | }, | |
7022 | ||
7023 | /* VEX_LEN_0F384B_X86_64_P_3_W_0_M_0 */ | |
7024 | { | |
7025 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
7026 | }, | |
7027 | ||
7531c613 | 7028 | /* VEX_LEN_0F385A_M_0 */ |
6c30d220 L |
7029 | { |
7030 | { Bad_Opcode }, | |
7531c613 | 7031 | { VEX_W_TABLE (VEX_W_0F385A_M_0_L_0) }, |
6c30d220 L |
7032 | }, |
7033 | ||
260cd341 LC |
7034 | /* VEX_LEN_0F385C_X86_64_P_1_W_0_M_0 */ |
7035 | { | |
7036 | { "tdpbf16ps", { TMM, EXtmm, VexTmm }, 0 }, | |
7037 | }, | |
7038 | ||
7039 | /* VEX_LEN_0F385E_X86_64_P_0_W_0_M_0 */ | |
7040 | { | |
7041 | { "tdpbuud", {TMM, EXtmm, VexTmm }, 0 }, | |
7042 | }, | |
7043 | ||
7044 | /* VEX_LEN_0F385E_X86_64_P_1_W_0_M_0 */ | |
7045 | { | |
7046 | { "tdpbsud", {TMM, EXtmm, VexTmm }, 0 }, | |
7047 | }, | |
7048 | ||
7049 | /* VEX_LEN_0F385E_X86_64_P_2_W_0_M_0 */ | |
7050 | { | |
7051 | { "tdpbusd", {TMM, EXtmm, VexTmm }, 0 }, | |
7052 | }, | |
7053 | ||
7054 | /* VEX_LEN_0F385E_X86_64_P_3_W_0_M_0 */ | |
7055 | { | |
7056 | { "tdpbssd", {TMM, EXtmm, VexTmm }, 0 }, | |
7057 | }, | |
7058 | ||
7531c613 | 7059 | /* VEX_LEN_0F38DB */ |
a5ff0eb2 | 7060 | { |
7531c613 | 7061 | { "vaesimc", { XM, EXx }, PREFIX_DATA }, |
a5ff0eb2 L |
7062 | }, |
7063 | ||
035e7389 | 7064 | /* VEX_LEN_0F38F2 */ |
f12dc422 | 7065 | { |
035e7389 | 7066 | { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7067 | }, |
7068 | ||
035e7389 | 7069 | /* VEX_LEN_0F38F3_R_1 */ |
f12dc422 | 7070 | { |
035e7389 | 7071 | { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7072 | }, |
7073 | ||
035e7389 | 7074 | /* VEX_LEN_0F38F3_R_2 */ |
f12dc422 | 7075 | { |
035e7389 | 7076 | { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7077 | }, |
7078 | ||
035e7389 | 7079 | /* VEX_LEN_0F38F3_R_3 */ |
f12dc422 | 7080 | { |
035e7389 | 7081 | { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7082 | }, |
7083 | ||
6c30d220 L |
7084 | /* VEX_LEN_0F38F5_P_0 */ |
7085 | { | |
bf890a93 | 7086 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7087 | }, |
7088 | ||
7089 | /* VEX_LEN_0F38F5_P_1 */ | |
7090 | { | |
bf890a93 | 7091 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
7092 | }, |
7093 | ||
7094 | /* VEX_LEN_0F38F5_P_3 */ | |
7095 | { | |
bf890a93 | 7096 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
7097 | }, |
7098 | ||
7099 | /* VEX_LEN_0F38F6_P_3 */ | |
7100 | { | |
bf890a93 | 7101 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
7102 | }, |
7103 | ||
f12dc422 L |
7104 | /* VEX_LEN_0F38F7_P_0 */ |
7105 | { | |
bf890a93 | 7106 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
7107 | }, |
7108 | ||
6c30d220 L |
7109 | /* VEX_LEN_0F38F7_P_1 */ |
7110 | { | |
bf890a93 | 7111 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7112 | }, |
7113 | ||
7114 | /* VEX_LEN_0F38F7_P_2 */ | |
7115 | { | |
bf890a93 | 7116 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7117 | }, |
7118 | ||
7119 | /* VEX_LEN_0F38F7_P_3 */ | |
7120 | { | |
bf890a93 | 7121 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
7122 | }, |
7123 | ||
7531c613 | 7124 | /* VEX_LEN_0F3A00 */ |
6c30d220 L |
7125 | { |
7126 | { Bad_Opcode }, | |
7531c613 | 7127 | { VEX_W_TABLE (VEX_W_0F3A00_L_1) }, |
6c30d220 L |
7128 | }, |
7129 | ||
7531c613 | 7130 | /* VEX_LEN_0F3A01 */ |
6c30d220 L |
7131 | { |
7132 | { Bad_Opcode }, | |
7531c613 | 7133 | { VEX_W_TABLE (VEX_W_0F3A01_L_1) }, |
6c30d220 L |
7134 | }, |
7135 | ||
7531c613 | 7136 | /* VEX_LEN_0F3A06 */ |
c0f3af97 | 7137 | { |
592d1631 | 7138 | { Bad_Opcode }, |
7531c613 | 7139 | { VEX_W_TABLE (VEX_W_0F3A06_L_1) }, |
c0f3af97 L |
7140 | }, |
7141 | ||
7531c613 | 7142 | /* VEX_LEN_0F3A14 */ |
c0f3af97 | 7143 | { |
7531c613 | 7144 | { "vpextrb", { Edqb, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7145 | }, |
7146 | ||
7531c613 | 7147 | /* VEX_LEN_0F3A15 */ |
c0f3af97 | 7148 | { |
7531c613 | 7149 | { "vpextrw", { Edqw, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7150 | }, |
7151 | ||
7531c613 | 7152 | /* VEX_LEN_0F3A16 */ |
c0f3af97 | 7153 | { |
7531c613 | 7154 | { "vpextrK", { Edq, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7155 | }, |
7156 | ||
7531c613 | 7157 | /* VEX_LEN_0F3A17 */ |
c0f3af97 | 7158 | { |
7531c613 | 7159 | { "vextractps", { Edqd, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7160 | }, |
7161 | ||
7531c613 | 7162 | /* VEX_LEN_0F3A18 */ |
c0f3af97 | 7163 | { |
592d1631 | 7164 | { Bad_Opcode }, |
7531c613 | 7165 | { VEX_W_TABLE (VEX_W_0F3A18_L_1) }, |
c0f3af97 L |
7166 | }, |
7167 | ||
7531c613 | 7168 | /* VEX_LEN_0F3A19 */ |
c0f3af97 | 7169 | { |
592d1631 | 7170 | { Bad_Opcode }, |
7531c613 | 7171 | { VEX_W_TABLE (VEX_W_0F3A19_L_1) }, |
c0f3af97 L |
7172 | }, |
7173 | ||
7531c613 | 7174 | /* VEX_LEN_0F3A20 */ |
c0f3af97 | 7175 | { |
7531c613 | 7176 | { "vpinsrb", { XM, Vex, Edqb, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7177 | }, |
7178 | ||
7531c613 | 7179 | /* VEX_LEN_0F3A21 */ |
c0f3af97 | 7180 | { |
7531c613 | 7181 | { "vinsertps", { XM, Vex, EXd, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7182 | }, |
7183 | ||
7531c613 | 7184 | /* VEX_LEN_0F3A22 */ |
c0f3af97 | 7185 | { |
7531c613 | 7186 | { "vpinsrK", { XM, Vex, Edq, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7187 | }, |
7188 | ||
7531c613 | 7189 | /* VEX_LEN_0F3A30 */ |
43234a1e | 7190 | { |
bb5b3501 | 7191 | { MOD_TABLE (MOD_VEX_0F3A30_L_0) }, |
43234a1e L |
7192 | }, |
7193 | ||
7531c613 | 7194 | /* VEX_LEN_0F3A31 */ |
1ba585e8 | 7195 | { |
bb5b3501 | 7196 | { MOD_TABLE (MOD_VEX_0F3A31_L_0) }, |
1ba585e8 IT |
7197 | }, |
7198 | ||
7531c613 | 7199 | /* VEX_LEN_0F3A32 */ |
43234a1e | 7200 | { |
bb5b3501 | 7201 | { MOD_TABLE (MOD_VEX_0F3A32_L_0) }, |
43234a1e L |
7202 | }, |
7203 | ||
7531c613 | 7204 | /* VEX_LEN_0F3A33 */ |
1ba585e8 | 7205 | { |
bb5b3501 | 7206 | { MOD_TABLE (MOD_VEX_0F3A33_L_0) }, |
1ba585e8 IT |
7207 | }, |
7208 | ||
7531c613 | 7209 | /* VEX_LEN_0F3A38 */ |
c0f3af97 | 7210 | { |
6c30d220 | 7211 | { Bad_Opcode }, |
7531c613 | 7212 | { VEX_W_TABLE (VEX_W_0F3A38_L_1) }, |
c0f3af97 L |
7213 | }, |
7214 | ||
7531c613 | 7215 | /* VEX_LEN_0F3A39 */ |
c0f3af97 | 7216 | { |
6c30d220 | 7217 | { Bad_Opcode }, |
7531c613 | 7218 | { VEX_W_TABLE (VEX_W_0F3A39_L_1) }, |
6c30d220 L |
7219 | }, |
7220 | ||
7531c613 | 7221 | /* VEX_LEN_0F3A41 */ |
6c30d220 | 7222 | { |
7531c613 | 7223 | { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7224 | }, |
7225 | ||
7531c613 | 7226 | /* VEX_LEN_0F3A46 */ |
c0f3af97 | 7227 | { |
6c30d220 | 7228 | { Bad_Opcode }, |
7531c613 | 7229 | { VEX_W_TABLE (VEX_W_0F3A46_L_1) }, |
c0f3af97 L |
7230 | }, |
7231 | ||
7531c613 | 7232 | /* VEX_LEN_0F3A60 */ |
c0f3af97 | 7233 | { |
7531c613 | 7234 | { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7235 | }, |
7236 | ||
7531c613 | 7237 | /* VEX_LEN_0F3A61 */ |
c0f3af97 | 7238 | { |
7531c613 | 7239 | { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7240 | }, |
7241 | ||
7531c613 | 7242 | /* VEX_LEN_0F3A62 */ |
c0f3af97 | 7243 | { |
7531c613 | 7244 | { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7245 | }, |
7246 | ||
7531c613 | 7247 | /* VEX_LEN_0F3A63 */ |
c0f3af97 | 7248 | { |
7531c613 | 7249 | { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7250 | }, |
7251 | ||
7531c613 | 7252 | /* VEX_LEN_0F3ADF */ |
a5ff0eb2 | 7253 | { |
7531c613 | 7254 | { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
a5ff0eb2 | 7255 | }, |
4c807e72 | 7256 | |
6c30d220 L |
7257 | /* VEX_LEN_0F3AF0_P_3 */ |
7258 | { | |
bf890a93 | 7259 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
7260 | }, |
7261 | ||
467bbef0 JB |
7262 | /* VEX_LEN_0FXOP_08_85 */ |
7263 | { | |
7264 | { VEX_W_TABLE (VEX_W_0FXOP_08_85_L_0) }, | |
7265 | }, | |
7266 | ||
7267 | /* VEX_LEN_0FXOP_08_86 */ | |
7268 | { | |
7269 | { VEX_W_TABLE (VEX_W_0FXOP_08_86_L_0) }, | |
7270 | }, | |
7271 | ||
7272 | /* VEX_LEN_0FXOP_08_87 */ | |
7273 | { | |
7274 | { VEX_W_TABLE (VEX_W_0FXOP_08_87_L_0) }, | |
7275 | }, | |
7276 | ||
7277 | /* VEX_LEN_0FXOP_08_8E */ | |
7278 | { | |
7279 | { VEX_W_TABLE (VEX_W_0FXOP_08_8E_L_0) }, | |
7280 | }, | |
7281 | ||
7282 | /* VEX_LEN_0FXOP_08_8F */ | |
7283 | { | |
7284 | { VEX_W_TABLE (VEX_W_0FXOP_08_8F_L_0) }, | |
7285 | }, | |
7286 | ||
7287 | /* VEX_LEN_0FXOP_08_95 */ | |
7288 | { | |
7289 | { VEX_W_TABLE (VEX_W_0FXOP_08_95_L_0) }, | |
7290 | }, | |
7291 | ||
7292 | /* VEX_LEN_0FXOP_08_96 */ | |
7293 | { | |
7294 | { VEX_W_TABLE (VEX_W_0FXOP_08_96_L_0) }, | |
7295 | }, | |
7296 | ||
7297 | /* VEX_LEN_0FXOP_08_97 */ | |
7298 | { | |
7299 | { VEX_W_TABLE (VEX_W_0FXOP_08_97_L_0) }, | |
7300 | }, | |
7301 | ||
7302 | /* VEX_LEN_0FXOP_08_9E */ | |
7303 | { | |
7304 | { VEX_W_TABLE (VEX_W_0FXOP_08_9E_L_0) }, | |
7305 | }, | |
7306 | ||
7307 | /* VEX_LEN_0FXOP_08_9F */ | |
7308 | { | |
7309 | { VEX_W_TABLE (VEX_W_0FXOP_08_9F_L_0) }, | |
7310 | }, | |
7311 | ||
7312 | /* VEX_LEN_0FXOP_08_A3 */ | |
7313 | { | |
7314 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7315 | }, | |
7316 | ||
7317 | /* VEX_LEN_0FXOP_08_A6 */ | |
7318 | { | |
7319 | { VEX_W_TABLE (VEX_W_0FXOP_08_A6_L_0) }, | |
7320 | }, | |
7321 | ||
7322 | /* VEX_LEN_0FXOP_08_B6 */ | |
7323 | { | |
7324 | { VEX_W_TABLE (VEX_W_0FXOP_08_B6_L_0) }, | |
7325 | }, | |
7326 | ||
7327 | /* VEX_LEN_0FXOP_08_C0 */ | |
7328 | { | |
7329 | { VEX_W_TABLE (VEX_W_0FXOP_08_C0_L_0) }, | |
7330 | }, | |
7331 | ||
7332 | /* VEX_LEN_0FXOP_08_C1 */ | |
7333 | { | |
7334 | { VEX_W_TABLE (VEX_W_0FXOP_08_C1_L_0) }, | |
7335 | }, | |
7336 | ||
7337 | /* VEX_LEN_0FXOP_08_C2 */ | |
7338 | { | |
7339 | { VEX_W_TABLE (VEX_W_0FXOP_08_C2_L_0) }, | |
7340 | }, | |
7341 | ||
7342 | /* VEX_LEN_0FXOP_08_C3 */ | |
7343 | { | |
7344 | { VEX_W_TABLE (VEX_W_0FXOP_08_C3_L_0) }, | |
7345 | }, | |
7346 | ||
ff688e1f L |
7347 | /* VEX_LEN_0FXOP_08_CC */ |
7348 | { | |
467bbef0 | 7349 | { VEX_W_TABLE (VEX_W_0FXOP_08_CC_L_0) }, |
ff688e1f L |
7350 | }, |
7351 | ||
7352 | /* VEX_LEN_0FXOP_08_CD */ | |
7353 | { | |
467bbef0 | 7354 | { VEX_W_TABLE (VEX_W_0FXOP_08_CD_L_0) }, |
ff688e1f L |
7355 | }, |
7356 | ||
7357 | /* VEX_LEN_0FXOP_08_CE */ | |
7358 | { | |
467bbef0 | 7359 | { VEX_W_TABLE (VEX_W_0FXOP_08_CE_L_0) }, |
ff688e1f L |
7360 | }, |
7361 | ||
7362 | /* VEX_LEN_0FXOP_08_CF */ | |
7363 | { | |
467bbef0 | 7364 | { VEX_W_TABLE (VEX_W_0FXOP_08_CF_L_0) }, |
ff688e1f L |
7365 | }, |
7366 | ||
7367 | /* VEX_LEN_0FXOP_08_EC */ | |
7368 | { | |
467bbef0 | 7369 | { VEX_W_TABLE (VEX_W_0FXOP_08_EC_L_0) }, |
ff688e1f L |
7370 | }, |
7371 | ||
7372 | /* VEX_LEN_0FXOP_08_ED */ | |
7373 | { | |
467bbef0 | 7374 | { VEX_W_TABLE (VEX_W_0FXOP_08_ED_L_0) }, |
ff688e1f L |
7375 | }, |
7376 | ||
7377 | /* VEX_LEN_0FXOP_08_EE */ | |
7378 | { | |
467bbef0 | 7379 | { VEX_W_TABLE (VEX_W_0FXOP_08_EE_L_0) }, |
ff688e1f L |
7380 | }, |
7381 | ||
7382 | /* VEX_LEN_0FXOP_08_EF */ | |
7383 | { | |
467bbef0 JB |
7384 | { VEX_W_TABLE (VEX_W_0FXOP_08_EF_L_0) }, |
7385 | }, | |
7386 | ||
7387 | /* VEX_LEN_0FXOP_09_01 */ | |
7388 | { | |
7389 | { REG_TABLE (REG_0FXOP_09_01_L_0) }, | |
7390 | }, | |
7391 | ||
7392 | /* VEX_LEN_0FXOP_09_02 */ | |
7393 | { | |
7394 | { REG_TABLE (REG_0FXOP_09_02_L_0) }, | |
7395 | }, | |
7396 | ||
7397 | /* VEX_LEN_0FXOP_09_12_M_1 */ | |
7398 | { | |
7399 | { REG_TABLE (REG_0FXOP_09_12_M_1_L_0) }, | |
ff688e1f L |
7400 | }, |
7401 | ||
b5b098c2 | 7402 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 7403 | { |
b5b098c2 | 7404 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 7405 | }, |
4c807e72 | 7406 | |
b5b098c2 | 7407 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 7408 | { |
b5b098c2 | 7409 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 7410 | }, |
467bbef0 JB |
7411 | |
7412 | /* VEX_LEN_0FXOP_09_90 */ | |
7413 | { | |
7414 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
7415 | }, | |
7416 | ||
7417 | /* VEX_LEN_0FXOP_09_91 */ | |
7418 | { | |
7419 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
7420 | }, | |
7421 | ||
7422 | /* VEX_LEN_0FXOP_09_92 */ | |
7423 | { | |
7424 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
7425 | }, | |
7426 | ||
7427 | /* VEX_LEN_0FXOP_09_93 */ | |
7428 | { | |
7429 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
7430 | }, | |
7431 | ||
7432 | /* VEX_LEN_0FXOP_09_94 */ | |
7433 | { | |
7434 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
7435 | }, | |
7436 | ||
7437 | /* VEX_LEN_0FXOP_09_95 */ | |
7438 | { | |
7439 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
7440 | }, | |
7441 | ||
7442 | /* VEX_LEN_0FXOP_09_96 */ | |
7443 | { | |
7444 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
7445 | }, | |
7446 | ||
7447 | /* VEX_LEN_0FXOP_09_97 */ | |
7448 | { | |
7449 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
7450 | }, | |
7451 | ||
7452 | /* VEX_LEN_0FXOP_09_98 */ | |
7453 | { | |
7454 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
7455 | }, | |
7456 | ||
7457 | /* VEX_LEN_0FXOP_09_99 */ | |
7458 | { | |
7459 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
7460 | }, | |
7461 | ||
7462 | /* VEX_LEN_0FXOP_09_9A */ | |
7463 | { | |
7464 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
7465 | }, | |
7466 | ||
7467 | /* VEX_LEN_0FXOP_09_9B */ | |
7468 | { | |
7469 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
7470 | }, | |
7471 | ||
7472 | /* VEX_LEN_0FXOP_09_C1 */ | |
7473 | { | |
7474 | { VEX_W_TABLE (VEX_W_0FXOP_09_C1_L_0) }, | |
7475 | }, | |
7476 | ||
7477 | /* VEX_LEN_0FXOP_09_C2 */ | |
7478 | { | |
7479 | { VEX_W_TABLE (VEX_W_0FXOP_09_C2_L_0) }, | |
7480 | }, | |
7481 | ||
7482 | /* VEX_LEN_0FXOP_09_C3 */ | |
7483 | { | |
7484 | { VEX_W_TABLE (VEX_W_0FXOP_09_C3_L_0) }, | |
7485 | }, | |
7486 | ||
7487 | /* VEX_LEN_0FXOP_09_C6 */ | |
7488 | { | |
7489 | { VEX_W_TABLE (VEX_W_0FXOP_09_C6_L_0) }, | |
7490 | }, | |
7491 | ||
7492 | /* VEX_LEN_0FXOP_09_C7 */ | |
7493 | { | |
7494 | { VEX_W_TABLE (VEX_W_0FXOP_09_C7_L_0) }, | |
7495 | }, | |
7496 | ||
7497 | /* VEX_LEN_0FXOP_09_CB */ | |
7498 | { | |
7499 | { VEX_W_TABLE (VEX_W_0FXOP_09_CB_L_0) }, | |
7500 | }, | |
7501 | ||
7502 | /* VEX_LEN_0FXOP_09_D1 */ | |
7503 | { | |
7504 | { VEX_W_TABLE (VEX_W_0FXOP_09_D1_L_0) }, | |
7505 | }, | |
7506 | ||
7507 | /* VEX_LEN_0FXOP_09_D2 */ | |
7508 | { | |
7509 | { VEX_W_TABLE (VEX_W_0FXOP_09_D2_L_0) }, | |
7510 | }, | |
7511 | ||
7512 | /* VEX_LEN_0FXOP_09_D3 */ | |
7513 | { | |
7514 | { VEX_W_TABLE (VEX_W_0FXOP_09_D3_L_0) }, | |
7515 | }, | |
7516 | ||
7517 | /* VEX_LEN_0FXOP_09_D6 */ | |
7518 | { | |
7519 | { VEX_W_TABLE (VEX_W_0FXOP_09_D6_L_0) }, | |
7520 | }, | |
7521 | ||
7522 | /* VEX_LEN_0FXOP_09_D7 */ | |
7523 | { | |
7524 | { VEX_W_TABLE (VEX_W_0FXOP_09_D7_L_0) }, | |
7525 | }, | |
7526 | ||
7527 | /* VEX_LEN_0FXOP_09_DB */ | |
7528 | { | |
7529 | { VEX_W_TABLE (VEX_W_0FXOP_09_DB_L_0) }, | |
7530 | }, | |
7531 | ||
7532 | /* VEX_LEN_0FXOP_09_E1 */ | |
7533 | { | |
7534 | { VEX_W_TABLE (VEX_W_0FXOP_09_E1_L_0) }, | |
7535 | }, | |
7536 | ||
7537 | /* VEX_LEN_0FXOP_09_E2 */ | |
7538 | { | |
7539 | { VEX_W_TABLE (VEX_W_0FXOP_09_E2_L_0) }, | |
7540 | }, | |
7541 | ||
7542 | /* VEX_LEN_0FXOP_09_E3 */ | |
7543 | { | |
7544 | { VEX_W_TABLE (VEX_W_0FXOP_09_E3_L_0) }, | |
7545 | }, | |
7546 | ||
7547 | /* VEX_LEN_0FXOP_0A_12 */ | |
7548 | { | |
7549 | { REG_TABLE (REG_0FXOP_0A_12_L_0) }, | |
7550 | }, | |
331d2d0d L |
7551 | }; |
7552 | ||
ad692897 | 7553 | #include "i386-dis-evex-len.h" |
04e2a182 | 7554 | |
9e30b8e0 | 7555 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
7556 | { |
7557 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
7558 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
7559 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
7560 | }, |
7561 | { | |
7562 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
7563 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
7564 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
7565 | }, |
7566 | { | |
7567 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
7568 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
7569 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
7570 | }, |
7571 | { | |
7572 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
7573 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
7574 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
7575 | }, |
7576 | { | |
7577 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
7578 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
7579 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
7580 | }, |
7581 | { | |
7582 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
7583 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
7584 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
7585 | }, |
7586 | { | |
ec6f095a L |
7587 | /* VEX_W_0F45_P_0_LEN_1 */ |
7588 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
7589 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
7590 | }, |
7591 | { | |
ec6f095a L |
7592 | /* VEX_W_0F45_P_2_LEN_1 */ |
7593 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
7594 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
7595 | }, |
7596 | { | |
ec6f095a L |
7597 | /* VEX_W_0F46_P_0_LEN_1 */ |
7598 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
7599 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
7600 | }, |
7601 | { | |
ec6f095a L |
7602 | /* VEX_W_0F46_P_2_LEN_1 */ |
7603 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
7604 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
7605 | }, |
7606 | { | |
ec6f095a L |
7607 | /* VEX_W_0F47_P_0_LEN_1 */ |
7608 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
7609 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
7610 | }, |
7611 | { | |
ec6f095a L |
7612 | /* VEX_W_0F47_P_2_LEN_1 */ |
7613 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
7614 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
7615 | }, |
7616 | { | |
ec6f095a L |
7617 | /* VEX_W_0F4A_P_0_LEN_1 */ |
7618 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
7619 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
7620 | }, |
7621 | { | |
ec6f095a L |
7622 | /* VEX_W_0F4A_P_2_LEN_1 */ |
7623 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
7624 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
7625 | }, |
7626 | { | |
ec6f095a L |
7627 | /* VEX_W_0F4B_P_0_LEN_1 */ |
7628 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
7629 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
7630 | }, |
7631 | { | |
ec6f095a L |
7632 | /* VEX_W_0F4B_P_2_LEN_1 */ |
7633 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
7634 | }, |
7635 | { | |
ec6f095a L |
7636 | /* VEX_W_0F90_P_0_LEN_0 */ |
7637 | { "kmovw", { MaskG, MaskE }, 0 }, | |
7638 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
7639 | }, |
7640 | { | |
ec6f095a L |
7641 | /* VEX_W_0F90_P_2_LEN_0 */ |
7642 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
7643 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
7644 | }, |
7645 | { | |
ec6f095a L |
7646 | /* VEX_W_0F91_P_0_LEN_0 */ |
7647 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
7648 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
7649 | }, |
7650 | { | |
ec6f095a L |
7651 | /* VEX_W_0F91_P_2_LEN_0 */ |
7652 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
7653 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
7654 | }, |
7655 | { | |
ec6f095a L |
7656 | /* VEX_W_0F92_P_0_LEN_0 */ |
7657 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
7658 | }, |
7659 | { | |
ec6f095a L |
7660 | /* VEX_W_0F92_P_2_LEN_0 */ |
7661 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 7662 | }, |
9e30b8e0 | 7663 | { |
ec6f095a L |
7664 | /* VEX_W_0F93_P_0_LEN_0 */ |
7665 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
7666 | }, |
7667 | { | |
ec6f095a L |
7668 | /* VEX_W_0F93_P_2_LEN_0 */ |
7669 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 7670 | }, |
9e30b8e0 | 7671 | { |
ec6f095a L |
7672 | /* VEX_W_0F98_P_0_LEN_0 */ |
7673 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
7674 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
7675 | }, |
7676 | { | |
ec6f095a L |
7677 | /* VEX_W_0F98_P_2_LEN_0 */ |
7678 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
7679 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
7680 | }, |
7681 | { | |
ec6f095a L |
7682 | /* VEX_W_0F99_P_0_LEN_0 */ |
7683 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
7684 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
7685 | }, |
7686 | { | |
ec6f095a L |
7687 | /* VEX_W_0F99_P_2_LEN_0 */ |
7688 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
7689 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 7690 | }, |
9e30b8e0 | 7691 | { |
7531c613 JB |
7692 | /* VEX_W_0F380C */ |
7693 | { "vpermilps", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7694 | }, |
7695 | { | |
7531c613 JB |
7696 | /* VEX_W_0F380D */ |
7697 | { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7698 | }, |
7699 | { | |
7531c613 JB |
7700 | /* VEX_W_0F380E */ |
7701 | { "vtestps", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7702 | }, |
7703 | { | |
7531c613 JB |
7704 | /* VEX_W_0F380F */ |
7705 | { "vtestpd", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7706 | }, |
6431c801 | 7707 | { |
7531c613 JB |
7708 | /* VEX_W_0F3813 */ |
7709 | { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA }, | |
6431c801 | 7710 | }, |
6c30d220 | 7711 | { |
7531c613 JB |
7712 | /* VEX_W_0F3816_L_1 */ |
7713 | { "vpermps", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7714 | }, |
bcf2684f | 7715 | { |
7531c613 JB |
7716 | /* VEX_W_0F3818 */ |
7717 | { "vbroadcastss", { XM, EXxmm_md }, PREFIX_DATA }, | |
bcf2684f | 7718 | }, |
9e30b8e0 | 7719 | { |
7531c613 JB |
7720 | /* VEX_W_0F3819_L_1 */ |
7721 | { "vbroadcastsd", { XM, EXxmm_mq }, PREFIX_DATA }, | |
9e30b8e0 L |
7722 | }, |
7723 | { | |
7531c613 JB |
7724 | /* VEX_W_0F381A_M_0_L_1 */ |
7725 | { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA }, | |
9e30b8e0 | 7726 | }, |
53aa04a0 | 7727 | { |
7531c613 JB |
7728 | /* VEX_W_0F382C_M_0 */ |
7729 | { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA }, | |
53aa04a0 L |
7730 | }, |
7731 | { | |
7531c613 JB |
7732 | /* VEX_W_0F382D_M_0 */ |
7733 | { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA }, | |
53aa04a0 L |
7734 | }, |
7735 | { | |
7531c613 JB |
7736 | /* VEX_W_0F382E_M_0 */ |
7737 | { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA }, | |
53aa04a0 L |
7738 | }, |
7739 | { | |
7531c613 JB |
7740 | /* VEX_W_0F382F_M_0 */ |
7741 | { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA }, | |
53aa04a0 | 7742 | }, |
6c30d220 | 7743 | { |
7531c613 JB |
7744 | /* VEX_W_0F3836 */ |
7745 | { "vpermd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7746 | }, |
6c30d220 | 7747 | { |
7531c613 JB |
7748 | /* VEX_W_0F3846 */ |
7749 | { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7750 | }, |
260cd341 LC |
7751 | { |
7752 | /* VEX_W_0F3849_X86_64_P_0 */ | |
7753 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_0_W_0) }, | |
7754 | }, | |
7755 | { | |
7756 | /* VEX_W_0F3849_X86_64_P_2 */ | |
7757 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_2_W_0) }, | |
7758 | }, | |
7759 | { | |
7760 | /* VEX_W_0F3849_X86_64_P_3 */ | |
7761 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_P_3_W_0) }, | |
7762 | }, | |
7763 | { | |
7764 | /* VEX_W_0F384B_X86_64_P_1 */ | |
7765 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_1_W_0) }, | |
7766 | }, | |
7767 | { | |
7768 | /* VEX_W_0F384B_X86_64_P_2 */ | |
7769 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_2_W_0) }, | |
7770 | }, | |
7771 | { | |
7772 | /* VEX_W_0F384B_X86_64_P_3 */ | |
7773 | { MOD_TABLE (MOD_VEX_0F384B_X86_64_P_3_W_0) }, | |
7774 | }, | |
58bf9b6a L |
7775 | { |
7776 | /* VEX_W_0F3850 */ | |
7777 | { "%XV vpdpbusd", { XM, Vex, EXx }, 0 }, | |
7778 | }, | |
7779 | { | |
7780 | /* VEX_W_0F3851 */ | |
7781 | { "%XV vpdpbusds", { XM, Vex, EXx }, 0 }, | |
7782 | }, | |
7783 | { | |
7784 | /* VEX_W_0F3852 */ | |
7785 | { "%XV vpdpwssd", { XM, Vex, EXx }, 0 }, | |
7786 | }, | |
7787 | { | |
7788 | /* VEX_W_0F3853 */ | |
7789 | { "%XV vpdpwssds", { XM, Vex, EXx }, 0 }, | |
7790 | }, | |
6c30d220 | 7791 | { |
7531c613 JB |
7792 | /* VEX_W_0F3858 */ |
7793 | { "vpbroadcastd", { XM, EXxmm_md }, PREFIX_DATA }, | |
6c30d220 L |
7794 | }, |
7795 | { | |
7531c613 JB |
7796 | /* VEX_W_0F3859 */ |
7797 | { "vpbroadcastq", { XM, EXxmm_mq }, PREFIX_DATA }, | |
6c30d220 L |
7798 | }, |
7799 | { | |
7531c613 JB |
7800 | /* VEX_W_0F385A_M_0_L_0 */ |
7801 | { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA }, | |
6c30d220 | 7802 | }, |
260cd341 LC |
7803 | { |
7804 | /* VEX_W_0F385C_X86_64_P_1 */ | |
7805 | { MOD_TABLE (MOD_VEX_0F385C_X86_64_P_1_W_0) }, | |
7806 | }, | |
7807 | { | |
7808 | /* VEX_W_0F385E_X86_64_P_0 */ | |
7809 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_0_W_0) }, | |
7810 | }, | |
7811 | { | |
7812 | /* VEX_W_0F385E_X86_64_P_1 */ | |
7813 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_1_W_0) }, | |
7814 | }, | |
7815 | { | |
7816 | /* VEX_W_0F385E_X86_64_P_2 */ | |
7817 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_2_W_0) }, | |
7818 | }, | |
7819 | { | |
7820 | /* VEX_W_0F385E_X86_64_P_3 */ | |
7821 | { MOD_TABLE (MOD_VEX_0F385E_X86_64_P_3_W_0) }, | |
7822 | }, | |
6c30d220 | 7823 | { |
7531c613 JB |
7824 | /* VEX_W_0F3878 */ |
7825 | { "vpbroadcastb", { XM, EXxmm_mb }, PREFIX_DATA }, | |
6c30d220 L |
7826 | }, |
7827 | { | |
7531c613 JB |
7828 | /* VEX_W_0F3879 */ |
7829 | { "vpbroadcastw", { XM, EXxmm_mw }, PREFIX_DATA }, | |
6c30d220 | 7830 | }, |
48521003 | 7831 | { |
7531c613 JB |
7832 | /* VEX_W_0F38CF */ |
7833 | { "vgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, | |
48521003 | 7834 | }, |
6c30d220 | 7835 | { |
7531c613 | 7836 | /* VEX_W_0F3A00_L_1 */ |
6c30d220 | 7837 | { Bad_Opcode }, |
7531c613 | 7838 | { "vpermq", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7839 | }, |
7840 | { | |
7531c613 | 7841 | /* VEX_W_0F3A01_L_1 */ |
6c30d220 | 7842 | { Bad_Opcode }, |
7531c613 | 7843 | { "vpermpd", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7844 | }, |
7845 | { | |
7531c613 JB |
7846 | /* VEX_W_0F3A02 */ |
7847 | { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7848 | }, |
9e30b8e0 | 7849 | { |
7531c613 JB |
7850 | /* VEX_W_0F3A04 */ |
7851 | { "vpermilps", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7852 | }, |
7853 | { | |
7531c613 JB |
7854 | /* VEX_W_0F3A05 */ |
7855 | { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7856 | }, |
7857 | { | |
7531c613 JB |
7858 | /* VEX_W_0F3A06_L_1 */ |
7859 | { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7860 | }, |
9e30b8e0 | 7861 | { |
7531c613 JB |
7862 | /* VEX_W_0F3A18_L_1 */ |
7863 | { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7864 | }, |
7865 | { | |
7531c613 JB |
7866 | /* VEX_W_0F3A19_L_1 */ |
7867 | { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7868 | }, |
6431c801 | 7869 | { |
7531c613 JB |
7870 | /* VEX_W_0F3A1D */ |
7871 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA }, | |
6431c801 | 7872 | }, |
6c30d220 | 7873 | { |
7531c613 JB |
7874 | /* VEX_W_0F3A38_L_1 */ |
7875 | { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
6c30d220 L |
7876 | }, |
7877 | { | |
7531c613 JB |
7878 | /* VEX_W_0F3A39_L_1 */ |
7879 | { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
6c30d220 | 7880 | }, |
6c30d220 | 7881 | { |
7531c613 JB |
7882 | /* VEX_W_0F3A46_L_1 */ |
7883 | { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7884 | }, |
9e30b8e0 | 7885 | { |
7531c613 JB |
7886 | /* VEX_W_0F3A4A */ |
7887 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7888 | }, |
7889 | { | |
7531c613 JB |
7890 | /* VEX_W_0F3A4B */ |
7891 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7892 | }, |
7893 | { | |
7531c613 JB |
7894 | /* VEX_W_0F3A4C */ |
7895 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 | 7896 | }, |
48521003 | 7897 | { |
7531c613 | 7898 | /* VEX_W_0F3ACE */ |
48521003 | 7899 | { Bad_Opcode }, |
7531c613 | 7900 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 IT |
7901 | }, |
7902 | { | |
7531c613 | 7903 | /* VEX_W_0F3ACF */ |
48521003 | 7904 | { Bad_Opcode }, |
7531c613 | 7905 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 | 7906 | }, |
467bbef0 JB |
7907 | /* VEX_W_0FXOP_08_85_L_0 */ |
7908 | { | |
7909 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7910 | }, | |
7911 | /* VEX_W_0FXOP_08_86_L_0 */ | |
7912 | { | |
7913 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7914 | }, | |
7915 | /* VEX_W_0FXOP_08_87_L_0 */ | |
7916 | { | |
7917 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7918 | }, | |
7919 | /* VEX_W_0FXOP_08_8E_L_0 */ | |
7920 | { | |
7921 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7922 | }, | |
7923 | /* VEX_W_0FXOP_08_8F_L_0 */ | |
7924 | { | |
7925 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7926 | }, | |
7927 | /* VEX_W_0FXOP_08_95_L_0 */ | |
7928 | { | |
7929 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7930 | }, | |
7931 | /* VEX_W_0FXOP_08_96_L_0 */ | |
7932 | { | |
7933 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7934 | }, | |
7935 | /* VEX_W_0FXOP_08_97_L_0 */ | |
7936 | { | |
7937 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7938 | }, | |
7939 | /* VEX_W_0FXOP_08_9E_L_0 */ | |
7940 | { | |
7941 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7942 | }, | |
7943 | /* VEX_W_0FXOP_08_9F_L_0 */ | |
7944 | { | |
7945 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7946 | }, | |
7947 | /* VEX_W_0FXOP_08_A6_L_0 */ | |
7948 | { | |
7949 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7950 | }, | |
7951 | /* VEX_W_0FXOP_08_B6_L_0 */ | |
7952 | { | |
7953 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7954 | }, | |
7955 | /* VEX_W_0FXOP_08_C0_L_0 */ | |
7956 | { | |
7957 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
7958 | }, | |
7959 | /* VEX_W_0FXOP_08_C1_L_0 */ | |
7960 | { | |
7961 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
7962 | }, | |
7963 | /* VEX_W_0FXOP_08_C2_L_0 */ | |
7964 | { | |
7965 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
7966 | }, | |
7967 | /* VEX_W_0FXOP_08_C3_L_0 */ | |
7968 | { | |
7969 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
7970 | }, | |
7971 | /* VEX_W_0FXOP_08_CC_L_0 */ | |
7972 | { | |
89e65d17 | 7973 | { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7974 | }, |
7975 | /* VEX_W_0FXOP_08_CD_L_0 */ | |
7976 | { | |
89e65d17 | 7977 | { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7978 | }, |
7979 | /* VEX_W_0FXOP_08_CE_L_0 */ | |
7980 | { | |
89e65d17 | 7981 | { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7982 | }, |
7983 | /* VEX_W_0FXOP_08_CF_L_0 */ | |
7984 | { | |
89e65d17 | 7985 | { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7986 | }, |
7987 | /* VEX_W_0FXOP_08_EC_L_0 */ | |
7988 | { | |
89e65d17 | 7989 | { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7990 | }, |
7991 | /* VEX_W_0FXOP_08_ED_L_0 */ | |
7992 | { | |
89e65d17 | 7993 | { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7994 | }, |
7995 | /* VEX_W_0FXOP_08_EE_L_0 */ | |
7996 | { | |
89e65d17 | 7997 | { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 JB |
7998 | }, |
7999 | /* VEX_W_0FXOP_08_EF_L_0 */ | |
8000 | { | |
89e65d17 | 8001 | { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 8002 | }, |
b5b098c2 JB |
8003 | /* VEX_W_0FXOP_09_80 */ |
8004 | { | |
8005 | { "vfrczps", { XM, EXx }, 0 }, | |
8006 | }, | |
8007 | /* VEX_W_0FXOP_09_81 */ | |
8008 | { | |
8009 | { "vfrczpd", { XM, EXx }, 0 }, | |
8010 | }, | |
8011 | /* VEX_W_0FXOP_09_82 */ | |
8012 | { | |
8013 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
8014 | }, | |
8015 | /* VEX_W_0FXOP_09_83 */ | |
8016 | { | |
8017 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
8018 | }, | |
467bbef0 JB |
8019 | /* VEX_W_0FXOP_09_C1_L_0 */ |
8020 | { | |
8021 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
8022 | }, | |
8023 | /* VEX_W_0FXOP_09_C2_L_0 */ | |
8024 | { | |
8025 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8026 | }, | |
8027 | /* VEX_W_0FXOP_09_C3_L_0 */ | |
8028 | { | |
8029 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
8030 | }, | |
8031 | /* VEX_W_0FXOP_09_C6_L_0 */ | |
8032 | { | |
8033 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
8034 | }, | |
8035 | /* VEX_W_0FXOP_09_C7_L_0 */ | |
8036 | { | |
8037 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
8038 | }, | |
8039 | /* VEX_W_0FXOP_09_CB_L_0 */ | |
8040 | { | |
8041 | { "vphadddq", { XM, EXxmm }, 0 }, | |
8042 | }, | |
8043 | /* VEX_W_0FXOP_09_D1_L_0 */ | |
8044 | { | |
8045 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
8046 | }, | |
8047 | /* VEX_W_0FXOP_09_D2_L_0 */ | |
8048 | { | |
8049 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8050 | }, | |
8051 | /* VEX_W_0FXOP_09_D3_L_0 */ | |
8052 | { | |
8053 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
8054 | }, | |
8055 | /* VEX_W_0FXOP_09_D6_L_0 */ | |
8056 | { | |
8057 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
8058 | }, | |
8059 | /* VEX_W_0FXOP_09_D7_L_0 */ | |
8060 | { | |
8061 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
8062 | }, | |
8063 | /* VEX_W_0FXOP_09_DB_L_0 */ | |
8064 | { | |
8065 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
8066 | }, | |
8067 | /* VEX_W_0FXOP_09_E1_L_0 */ | |
8068 | { | |
8069 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
8070 | }, | |
8071 | /* VEX_W_0FXOP_09_E2_L_0 */ | |
8072 | { | |
8073 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8074 | }, | |
8075 | /* VEX_W_0FXOP_09_E3_L_0 */ | |
8076 | { | |
8077 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
8078 | }, | |
ad692897 L |
8079 | |
8080 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
8081 | }; |
8082 | ||
8083 | static const struct dis386 mod_table[][2] = { | |
8084 | { | |
8085 | /* MOD_8D */ | |
bf890a93 | 8086 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 8087 | }, |
42164a71 L |
8088 | { |
8089 | /* MOD_C6_REG_7 */ | |
8090 | { Bad_Opcode }, | |
8091 | { RM_TABLE (RM_C6_REG_7) }, | |
8092 | }, | |
8093 | { | |
8094 | /* MOD_C7_REG_7 */ | |
8095 | { Bad_Opcode }, | |
8096 | { RM_TABLE (RM_C7_REG_7) }, | |
8097 | }, | |
4a357820 MZ |
8098 | { |
8099 | /* MOD_FF_REG_3 */ | |
8f570d62 | 8100 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
8101 | }, |
8102 | { | |
8103 | /* MOD_FF_REG_5 */ | |
8f570d62 | 8104 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 8105 | }, |
9e30b8e0 L |
8106 | { |
8107 | /* MOD_0F01_REG_0 */ | |
8108 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
8109 | { RM_TABLE (RM_0F01_REG_0) }, | |
8110 | }, | |
8111 | { | |
8112 | /* MOD_0F01_REG_1 */ | |
8113 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
8114 | { RM_TABLE (RM_0F01_REG_1) }, | |
8115 | }, | |
8116 | { | |
8117 | /* MOD_0F01_REG_2 */ | |
8118 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
8119 | { RM_TABLE (RM_0F01_REG_2) }, | |
8120 | }, | |
8121 | { | |
8122 | /* MOD_0F01_REG_3 */ | |
8123 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
8124 | { RM_TABLE (RM_0F01_REG_3) }, | |
8125 | }, | |
8eab4136 L |
8126 | { |
8127 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
8128 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
8129 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 8130 | }, |
9e30b8e0 L |
8131 | { |
8132 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 8133 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 8134 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
8135 | }, |
8136 | { | |
8137 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
8138 | { "movlpX", { XM, EXq }, 0 }, |
8139 | { "movhlps", { XM, EXq }, 0 }, | |
8140 | }, | |
8141 | { | |
8142 | /* MOD_0F12_PREFIX_2 */ | |
8143 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
8144 | }, |
8145 | { | |
8146 | /* MOD_0F13 */ | |
507bd325 | 8147 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
8148 | }, |
8149 | { | |
8150 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 8151 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 8152 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 8153 | }, |
18897deb JB |
8154 | { |
8155 | /* MOD_0F16_PREFIX_2 */ | |
8156 | { "movhpX", { XM, EXq }, 0 }, | |
8157 | }, | |
9e30b8e0 L |
8158 | { |
8159 | /* MOD_0F17 */ | |
507bd325 | 8160 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
8161 | }, |
8162 | { | |
8163 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 8164 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
8165 | }, |
8166 | { | |
8167 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 8168 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
8169 | }, |
8170 | { | |
8171 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 8172 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
8173 | }, |
8174 | { | |
8175 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 8176 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 8177 | }, |
d7189fa5 RM |
8178 | { |
8179 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 8180 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
8181 | }, |
8182 | { | |
8183 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 8184 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
8185 | }, |
8186 | { | |
8187 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 8188 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
8189 | }, |
8190 | { | |
8191 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 8192 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 8193 | }, |
7e8b059b L |
8194 | { |
8195 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 8196 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 8197 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
8198 | }, |
8199 | { | |
8200 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 8201 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 8202 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
8203 | }, |
8204 | { | |
8205 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 8206 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 8207 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 8208 | }, |
c48935d7 IT |
8209 | { |
8210 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 8211 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
8212 | { "nopQ", { Ev }, 0 }, |
8213 | }, | |
603555e5 L |
8214 | { |
8215 | /* MOD_0F1E_PREFIX_1 */ | |
8216 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 8217 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 8218 | }, |
75c135a8 L |
8219 | { |
8220 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 8221 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8222 | }, |
8223 | { | |
8224 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 8225 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8226 | }, |
8227 | { | |
8228 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 8229 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8230 | }, |
8231 | { | |
8232 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 8233 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
8234 | }, |
8235 | { | |
a5aaedb9 | 8236 | /* MOD_0F50 */ |
592d1631 | 8237 | { Bad_Opcode }, |
507bd325 | 8238 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 8239 | }, |
b844680a | 8240 | { |
1ceb70f8 | 8241 | /* MOD_0F71_REG_2 */ |
592d1631 | 8242 | { Bad_Opcode }, |
7531c613 | 8243 | { "psrlw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8244 | }, |
8245 | { | |
1ceb70f8 | 8246 | /* MOD_0F71_REG_4 */ |
592d1631 | 8247 | { Bad_Opcode }, |
7531c613 | 8248 | { "psraw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8249 | }, |
8250 | { | |
1ceb70f8 | 8251 | /* MOD_0F71_REG_6 */ |
592d1631 | 8252 | { Bad_Opcode }, |
7531c613 | 8253 | { "psllw", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8254 | }, |
8255 | { | |
1ceb70f8 | 8256 | /* MOD_0F72_REG_2 */ |
592d1631 | 8257 | { Bad_Opcode }, |
7531c613 | 8258 | { "psrld", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8259 | }, |
8260 | { | |
1ceb70f8 | 8261 | /* MOD_0F72_REG_4 */ |
592d1631 | 8262 | { Bad_Opcode }, |
7531c613 | 8263 | { "psrad", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8264 | }, |
8265 | { | |
1ceb70f8 | 8266 | /* MOD_0F72_REG_6 */ |
592d1631 | 8267 | { Bad_Opcode }, |
7531c613 | 8268 | { "pslld", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8269 | }, |
8270 | { | |
1ceb70f8 | 8271 | /* MOD_0F73_REG_2 */ |
592d1631 | 8272 | { Bad_Opcode }, |
7531c613 | 8273 | { "psrlq", { MS, Ib }, PREFIX_OPCODE }, |
b844680a L |
8274 | }, |
8275 | { | |
1ceb70f8 | 8276 | /* MOD_0F73_REG_3 */ |
592d1631 | 8277 | { Bad_Opcode }, |
7531c613 | 8278 | { "psrldq", { XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
8279 | }, |
8280 | { | |
8281 | /* MOD_0F73_REG_6 */ | |
592d1631 | 8282 | { Bad_Opcode }, |
7531c613 | 8283 | { "psllq", { MS, Ib }, PREFIX_OPCODE }, |
c0f3af97 L |
8284 | }, |
8285 | { | |
8286 | /* MOD_0F73_REG_7 */ | |
592d1631 | 8287 | { Bad_Opcode }, |
7531c613 | 8288 | { "pslldq", { XS, Ib }, PREFIX_DATA }, |
c0f3af97 L |
8289 | }, |
8290 | { | |
8291 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 8292 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 8293 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
8294 | }, |
8295 | { | |
8296 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 8297 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 8298 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
8299 | }, |
8300 | { | |
8301 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 8302 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 8303 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
8304 | }, |
8305 | { | |
8306 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 8307 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 8308 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
8309 | }, |
8310 | { | |
8311 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
8312 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
8313 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
8314 | }, |
8315 | { | |
8316 | /* MOD_0FAE_REG_5 */ | |
035e7389 | 8317 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, |
f8687e93 | 8318 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, |
c0f3af97 L |
8319 | }, |
8320 | { | |
8321 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
8322 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
8323 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
8324 | }, |
8325 | { | |
8326 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
8327 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
8328 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
8329 | }, |
8330 | { | |
8331 | /* MOD_0FB2 */ | |
bf890a93 | 8332 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8333 | }, |
8334 | { | |
8335 | /* MOD_0FB4 */ | |
bf890a93 | 8336 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8337 | }, |
8338 | { | |
8339 | /* MOD_0FB5 */ | |
bf890a93 | 8340 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 8341 | }, |
a8484f96 L |
8342 | { |
8343 | /* MOD_0FC3 */ | |
035e7389 | 8344 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
a8484f96 | 8345 | }, |
963f3586 IT |
8346 | { |
8347 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 8348 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
8349 | }, |
8350 | { | |
8351 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 8352 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
8353 | }, |
8354 | { | |
8355 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 8356 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 8357 | }, |
c0f3af97 L |
8358 | { |
8359 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
8360 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
8361 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
8362 | }, |
8363 | { | |
8364 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 8365 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 8366 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
8367 | }, |
8368 | { | |
8369 | /* MOD_0FD7 */ | |
592d1631 | 8370 | { Bad_Opcode }, |
bf890a93 | 8371 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
8372 | }, |
8373 | { | |
8374 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 8375 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
8376 | }, |
8377 | { | |
8378 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 8379 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
8380 | }, |
8381 | { | |
7531c613 JB |
8382 | /* MOD_0F382A */ |
8383 | { "movntdqa", { XM, Mx }, PREFIX_DATA }, | |
c0f3af97 | 8384 | }, |
c4694f17 TG |
8385 | { |
8386 | /* MOD_0F38DC_PREFIX_1 */ | |
8387 | { "aesenc128kl", { XM, M }, 0 }, | |
8388 | { "loadiwkey", { XM, EXx }, 0 }, | |
8389 | }, | |
8390 | { | |
8391 | /* MOD_0F38DD_PREFIX_1 */ | |
8392 | { "aesdec128kl", { XM, M }, 0 }, | |
8393 | }, | |
8394 | { | |
8395 | /* MOD_0F38DE_PREFIX_1 */ | |
8396 | { "aesenc256kl", { XM, M }, 0 }, | |
8397 | }, | |
8398 | { | |
8399 | /* MOD_0F38DF_PREFIX_1 */ | |
8400 | { "aesdec256kl", { XM, M }, 0 }, | |
8401 | }, | |
603555e5 | 8402 | { |
7531c613 JB |
8403 | /* MOD_0F38F5 */ |
8404 | { "wrussK", { M, Gdq }, PREFIX_DATA }, | |
603555e5 L |
8405 | }, |
8406 | { | |
8407 | /* MOD_0F38F6_PREFIX_0 */ | |
8408 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
8409 | }, | |
5d79adc4 L |
8410 | { |
8411 | /* MOD_0F38F8_PREFIX_1 */ | |
8412 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
8413 | }, | |
c0a30a9f L |
8414 | { |
8415 | /* MOD_0F38F8_PREFIX_2 */ | |
8416 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
8417 | }, | |
5d79adc4 L |
8418 | { |
8419 | /* MOD_0F38F8_PREFIX_3 */ | |
8420 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
8421 | }, | |
c0a30a9f | 8422 | { |
035e7389 JB |
8423 | /* MOD_0F38F9 */ |
8424 | { "movdiri", { Edq, Gdq }, PREFIX_OPCODE }, | |
c0a30a9f | 8425 | }, |
c4694f17 TG |
8426 | { |
8427 | /* MOD_0F38FA_PREFIX_1 */ | |
8428 | { Bad_Opcode }, | |
8429 | { "encodekey128", { Gd, Ed }, 0 }, | |
8430 | }, | |
8431 | { | |
8432 | /* MOD_0F38FB_PREFIX_1 */ | |
8433 | { Bad_Opcode }, | |
8434 | { "encodekey256", { Gd, Ed }, 0 }, | |
8435 | }, | |
c1fa250a LC |
8436 | { |
8437 | /* MOD_0F3A0F_PREFIX_1 */ | |
8438 | { Bad_Opcode }, | |
8439 | { REG_TABLE (REG_0F3A0F_PREFIX_1_MOD_3) }, | |
8440 | }, | |
c0f3af97 L |
8441 | { |
8442 | /* MOD_62_32BIT */ | |
bf890a93 | 8443 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 8444 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
8445 | }, |
8446 | { | |
8447 | /* MOD_C4_32BIT */ | |
bf890a93 | 8448 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8449 | { VEX_C4_TABLE (VEX_0F) }, |
8450 | }, | |
8451 | { | |
8452 | /* MOD_C5_32BIT */ | |
bf890a93 | 8453 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
8454 | { VEX_C5_TABLE (VEX_0F) }, |
8455 | }, | |
8456 | { | |
592a252b L |
8457 | /* MOD_VEX_0F12_PREFIX_0 */ |
8458 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
8459 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 8460 | }, |
18897deb JB |
8461 | { |
8462 | /* MOD_VEX_0F12_PREFIX_2 */ | |
8463 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
8464 | }, | |
c0f3af97 | 8465 | { |
592a252b L |
8466 | /* MOD_VEX_0F13 */ |
8467 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
8468 | }, |
8469 | { | |
592a252b L |
8470 | /* MOD_VEX_0F16_PREFIX_0 */ |
8471 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
8472 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 8473 | }, |
18897deb JB |
8474 | { |
8475 | /* MOD_VEX_0F16_PREFIX_2 */ | |
8476 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
8477 | }, | |
c0f3af97 | 8478 | { |
592a252b L |
8479 | /* MOD_VEX_0F17 */ |
8480 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
8481 | }, |
8482 | { | |
592a252b | 8483 | /* MOD_VEX_0F2B */ |
bf926894 | 8484 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 8485 | }, |
ab4e4ed5 AF |
8486 | { |
8487 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
8488 | { Bad_Opcode }, | |
464d2b65 | 8489 | { "kandw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8490 | }, |
8491 | { | |
8492 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
8493 | { Bad_Opcode }, | |
464d2b65 | 8494 | { "kandq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8495 | }, |
8496 | { | |
8497 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
8498 | { Bad_Opcode }, | |
464d2b65 | 8499 | { "kandb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8500 | }, |
8501 | { | |
8502 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
8503 | { Bad_Opcode }, | |
464d2b65 | 8504 | { "kandd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8505 | }, |
8506 | { | |
8507 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
8508 | { Bad_Opcode }, | |
464d2b65 | 8509 | { "kandnw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8510 | }, |
8511 | { | |
8512 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
8513 | { Bad_Opcode }, | |
464d2b65 | 8514 | { "kandnq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8515 | }, |
8516 | { | |
8517 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
8518 | { Bad_Opcode }, | |
464d2b65 | 8519 | { "kandnb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8520 | }, |
8521 | { | |
8522 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
8523 | { Bad_Opcode }, | |
464d2b65 | 8524 | { "kandnd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8525 | }, |
8526 | { | |
8527 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
8528 | { Bad_Opcode }, | |
464d2b65 | 8529 | { "knotw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8530 | }, |
8531 | { | |
8532 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
8533 | { Bad_Opcode }, | |
464d2b65 | 8534 | { "knotq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8535 | }, |
8536 | { | |
8537 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
8538 | { Bad_Opcode }, | |
464d2b65 | 8539 | { "knotb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8540 | }, |
8541 | { | |
8542 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
8543 | { Bad_Opcode }, | |
464d2b65 | 8544 | { "knotd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8545 | }, |
8546 | { | |
8547 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
8548 | { Bad_Opcode }, | |
464d2b65 | 8549 | { "korw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8550 | }, |
8551 | { | |
8552 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
8553 | { Bad_Opcode }, | |
464d2b65 | 8554 | { "korq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8555 | }, |
8556 | { | |
8557 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
8558 | { Bad_Opcode }, | |
464d2b65 | 8559 | { "korb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8560 | }, |
8561 | { | |
8562 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
8563 | { Bad_Opcode }, | |
464d2b65 | 8564 | { "kord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8565 | }, |
8566 | { | |
8567 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
8568 | { Bad_Opcode }, | |
464d2b65 | 8569 | { "kxnorw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8570 | }, |
8571 | { | |
8572 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
8573 | { Bad_Opcode }, | |
464d2b65 | 8574 | { "kxnorq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8575 | }, |
8576 | { | |
8577 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
8578 | { Bad_Opcode }, | |
464d2b65 | 8579 | { "kxnorb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8580 | }, |
8581 | { | |
8582 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
8583 | { Bad_Opcode }, | |
464d2b65 | 8584 | { "kxnord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8585 | }, |
8586 | { | |
8587 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
8588 | { Bad_Opcode }, | |
464d2b65 | 8589 | { "kxorw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8590 | }, |
8591 | { | |
8592 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
8593 | { Bad_Opcode }, | |
464d2b65 | 8594 | { "kxorq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8595 | }, |
8596 | { | |
8597 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
8598 | { Bad_Opcode }, | |
464d2b65 | 8599 | { "kxorb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8600 | }, |
8601 | { | |
8602 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
8603 | { Bad_Opcode }, | |
464d2b65 | 8604 | { "kxord", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8605 | }, |
8606 | { | |
8607 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
8608 | { Bad_Opcode }, | |
464d2b65 | 8609 | { "kaddw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8610 | }, |
8611 | { | |
8612 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
8613 | { Bad_Opcode }, | |
464d2b65 | 8614 | { "kaddq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8615 | }, |
8616 | { | |
8617 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
8618 | { Bad_Opcode }, | |
464d2b65 | 8619 | { "kaddb", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8620 | }, |
8621 | { | |
8622 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
8623 | { Bad_Opcode }, | |
464d2b65 | 8624 | { "kaddd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8625 | }, |
8626 | { | |
8627 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
8628 | { Bad_Opcode }, | |
464d2b65 | 8629 | { "kunpckwd", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8630 | }, |
8631 | { | |
8632 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
8633 | { Bad_Opcode }, | |
464d2b65 | 8634 | { "kunpckdq", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 AF |
8635 | }, |
8636 | { | |
8637 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
8638 | { Bad_Opcode }, | |
464d2b65 | 8639 | { "kunpckbw", { MaskG, MaskVex, MaskE }, 0 }, |
ab4e4ed5 | 8640 | }, |
c0f3af97 | 8641 | { |
592a252b | 8642 | /* MOD_VEX_0F50 */ |
592d1631 | 8643 | { Bad_Opcode }, |
bf926894 | 8644 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
8645 | }, |
8646 | { | |
592a252b | 8647 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 8648 | { Bad_Opcode }, |
7531c613 | 8649 | { "vpsrlw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8650 | }, |
8651 | { | |
592a252b | 8652 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 8653 | { Bad_Opcode }, |
7531c613 | 8654 | { "vpsraw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8655 | }, |
8656 | { | |
592a252b | 8657 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 8658 | { Bad_Opcode }, |
7531c613 | 8659 | { "vpsllw", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a L |
8660 | }, |
8661 | { | |
592a252b | 8662 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 8663 | { Bad_Opcode }, |
7531c613 | 8664 | { "vpsrld", { Vex, XS, Ib }, PREFIX_DATA }, |
b844680a | 8665 | }, |
d8faab4e | 8666 | { |
592a252b | 8667 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 8668 | { Bad_Opcode }, |
7531c613 | 8669 | { "vpsrad", { Vex, XS, Ib }, PREFIX_DATA }, |
d8faab4e L |
8670 | }, |
8671 | { | |
592a252b | 8672 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 8673 | { Bad_Opcode }, |
7531c613 | 8674 | { "vpslld", { Vex, XS, Ib }, PREFIX_DATA }, |
d8faab4e | 8675 | }, |
876d4bfa | 8676 | { |
592a252b | 8677 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 8678 | { Bad_Opcode }, |
7531c613 | 8679 | { "vpsrlq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa L |
8680 | }, |
8681 | { | |
592a252b | 8682 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 8683 | { Bad_Opcode }, |
7531c613 | 8684 | { "vpsrldq", { Vex, XS, Ib }, PREFIX_DATA }, |
475a2301 L |
8685 | }, |
8686 | { | |
592a252b | 8687 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 8688 | { Bad_Opcode }, |
7531c613 | 8689 | { "vpsllq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa L |
8690 | }, |
8691 | { | |
592a252b | 8692 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 8693 | { Bad_Opcode }, |
7531c613 | 8694 | { "vpslldq", { Vex, XS, Ib }, PREFIX_DATA }, |
876d4bfa | 8695 | }, |
ab4e4ed5 AF |
8696 | { |
8697 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
8698 | { "kmovw", { Ew, MaskG }, 0 }, | |
8699 | { Bad_Opcode }, | |
8700 | }, | |
8701 | { | |
8702 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
8703 | { "kmovq", { Eq, MaskG }, 0 }, | |
8704 | { Bad_Opcode }, | |
8705 | }, | |
8706 | { | |
8707 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
8708 | { "kmovb", { Eb, MaskG }, 0 }, | |
8709 | { Bad_Opcode }, | |
8710 | }, | |
8711 | { | |
8712 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
8713 | { "kmovd", { Ed, MaskG }, 0 }, | |
8714 | { Bad_Opcode }, | |
8715 | }, | |
8716 | { | |
8717 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
8718 | { Bad_Opcode }, | |
464d2b65 | 8719 | { "kmovw", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8720 | }, |
8721 | { | |
8722 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
8723 | { Bad_Opcode }, | |
464d2b65 | 8724 | { "kmovb", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8725 | }, |
8726 | { | |
58a211d2 | 8727 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 8728 | { Bad_Opcode }, |
464d2b65 | 8729 | { "kmovK", { MaskG, Edq }, 0 }, |
ab4e4ed5 AF |
8730 | }, |
8731 | { | |
8732 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
8733 | { Bad_Opcode }, | |
464d2b65 | 8734 | { "kmovw", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8735 | }, |
8736 | { | |
8737 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
8738 | { Bad_Opcode }, | |
464d2b65 | 8739 | { "kmovb", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8740 | }, |
8741 | { | |
58a211d2 | 8742 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 8743 | { Bad_Opcode }, |
464d2b65 | 8744 | { "kmovK", { Gdq, MaskE }, 0 }, |
ab4e4ed5 AF |
8745 | }, |
8746 | { | |
8747 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
8748 | { Bad_Opcode }, | |
464d2b65 | 8749 | { "kortestw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8750 | }, |
8751 | { | |
8752 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
8753 | { Bad_Opcode }, | |
464d2b65 | 8754 | { "kortestq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8755 | }, |
8756 | { | |
8757 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
8758 | { Bad_Opcode }, | |
464d2b65 | 8759 | { "kortestb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8760 | }, |
8761 | { | |
8762 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
8763 | { Bad_Opcode }, | |
464d2b65 | 8764 | { "kortestd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8765 | }, |
8766 | { | |
8767 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
8768 | { Bad_Opcode }, | |
464d2b65 | 8769 | { "ktestw", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8770 | }, |
8771 | { | |
8772 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
8773 | { Bad_Opcode }, | |
464d2b65 | 8774 | { "ktestq", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8775 | }, |
8776 | { | |
8777 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
8778 | { Bad_Opcode }, | |
464d2b65 | 8779 | { "ktestb", { MaskG, MaskE }, 0 }, |
ab4e4ed5 AF |
8780 | }, |
8781 | { | |
8782 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
8783 | { Bad_Opcode }, | |
464d2b65 | 8784 | { "ktestd", { MaskG, MaskE }, 0 }, |
ab4e4ed5 | 8785 | }, |
876d4bfa | 8786 | { |
592a252b L |
8787 | /* MOD_VEX_0FAE_REG_2 */ |
8788 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 8789 | }, |
bbedc832 | 8790 | { |
592a252b L |
8791 | /* MOD_VEX_0FAE_REG_3 */ |
8792 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 8793 | }, |
144c41d9 | 8794 | { |
7531c613 | 8795 | /* MOD_VEX_0FD7 */ |
592d1631 | 8796 | { Bad_Opcode }, |
7531c613 | 8797 | { "vpmovmskb", { Gdq, XS }, PREFIX_DATA }, |
144c41d9 | 8798 | }, |
1afd85e3 | 8799 | { |
7531c613 JB |
8800 | /* MOD_VEX_0FE7 */ |
8801 | { "vmovntdq", { Mx, XM }, PREFIX_DATA }, | |
1afd85e3 L |
8802 | }, |
8803 | { | |
592a252b | 8804 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 8805 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 8806 | }, |
75c135a8 | 8807 | { |
7531c613 JB |
8808 | /* MOD_VEX_0F381A */ |
8809 | { VEX_LEN_TABLE (VEX_LEN_0F381A_M_0) }, | |
75c135a8 | 8810 | }, |
1afd85e3 | 8811 | { |
7531c613 JB |
8812 | /* MOD_VEX_0F382A */ |
8813 | { "vmovntdqa", { XM, Mx }, PREFIX_DATA }, | |
1afd85e3 | 8814 | }, |
75c135a8 | 8815 | { |
7531c613 JB |
8816 | /* MOD_VEX_0F382C */ |
8817 | { VEX_W_TABLE (VEX_W_0F382C_M_0) }, | |
75c135a8 | 8818 | }, |
1afd85e3 | 8819 | { |
7531c613 JB |
8820 | /* MOD_VEX_0F382D */ |
8821 | { VEX_W_TABLE (VEX_W_0F382D_M_0) }, | |
1afd85e3 L |
8822 | }, |
8823 | { | |
7531c613 JB |
8824 | /* MOD_VEX_0F382E */ |
8825 | { VEX_W_TABLE (VEX_W_0F382E_M_0) }, | |
1afd85e3 L |
8826 | }, |
8827 | { | |
7531c613 JB |
8828 | /* MOD_VEX_0F382F */ |
8829 | { VEX_W_TABLE (VEX_W_0F382F_M_0) }, | |
1afd85e3 | 8830 | }, |
09d73035 CL |
8831 | { |
8832 | /* MOD_VEX_0F3849_X86_64_P_0_W_0 */ | |
8833 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_0) }, | |
8834 | { REG_TABLE (REG_VEX_0F3849_X86_64_P_0_W_0_M_1) }, | |
8835 | }, | |
8836 | { | |
8837 | /* MOD_VEX_0F3849_X86_64_P_2_W_0 */ | |
8838 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_2_W_0_M_0) }, | |
8839 | }, | |
8840 | { | |
8841 | /* MOD_VEX_0F3849_X86_64_P_3_W_0 */ | |
8842 | { Bad_Opcode }, | |
8843 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_3_W_0_M_0) }, | |
8844 | }, | |
8845 | { | |
8846 | /* MOD_VEX_0F384B_X86_64_P_1_W_0 */ | |
8847 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_1_W_0_M_0) }, | |
8848 | }, | |
8849 | { | |
8850 | /* MOD_VEX_0F384B_X86_64_P_2_W_0 */ | |
8851 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_2_W_0_M_0) }, | |
8852 | }, | |
8853 | { | |
8854 | /* MOD_VEX_0F384B_X86_64_P_3_W_0 */ | |
8855 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64_P_3_W_0_M_0) }, | |
8856 | }, | |
6c30d220 | 8857 | { |
7531c613 JB |
8858 | /* MOD_VEX_0F385A */ |
8859 | { VEX_LEN_TABLE (VEX_LEN_0F385A_M_0) }, | |
6c30d220 | 8860 | }, |
09d73035 CL |
8861 | { |
8862 | /* MOD_VEX_0F385C_X86_64_P_1_W_0 */ | |
8863 | { Bad_Opcode }, | |
8864 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64_P_1_W_0_M_0) }, | |
8865 | }, | |
8866 | { | |
8867 | /* MOD_VEX_0F385E_X86_64_P_0_W_0 */ | |
8868 | { Bad_Opcode }, | |
8869 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_0_W_0_M_0) }, | |
8870 | }, | |
8871 | { | |
8872 | /* MOD_VEX_0F385E_X86_64_P_1_W_0 */ | |
8873 | { Bad_Opcode }, | |
8874 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_1_W_0_M_0) }, | |
8875 | }, | |
8876 | { | |
8877 | /* MOD_VEX_0F385E_X86_64_P_2_W_0 */ | |
8878 | { Bad_Opcode }, | |
8879 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_2_W_0_M_0) }, | |
8880 | }, | |
8881 | { | |
8882 | /* MOD_VEX_0F385E_X86_64_P_3_W_0 */ | |
8883 | { Bad_Opcode }, | |
8884 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64_P_3_W_0_M_0) }, | |
8885 | }, | |
6c30d220 | 8886 | { |
7531c613 JB |
8887 | /* MOD_VEX_0F388C */ |
8888 | { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA }, | |
6c30d220 L |
8889 | }, |
8890 | { | |
7531c613 JB |
8891 | /* MOD_VEX_0F388E */ |
8892 | { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA }, | |
6c30d220 | 8893 | }, |
ab4e4ed5 | 8894 | { |
bb5b3501 | 8895 | /* MOD_VEX_0F3A30_L_0 */ |
ab4e4ed5 | 8896 | { Bad_Opcode }, |
464d2b65 | 8897 | { "kshiftr%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8898 | }, |
8899 | { | |
bb5b3501 | 8900 | /* MOD_VEX_0F3A31_L_0 */ |
ab4e4ed5 | 8901 | { Bad_Opcode }, |
464d2b65 | 8902 | { "kshiftr%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8903 | }, |
8904 | { | |
bb5b3501 | 8905 | /* MOD_VEX_0F3A32_L_0 */ |
ab4e4ed5 | 8906 | { Bad_Opcode }, |
464d2b65 | 8907 | { "kshiftl%BW", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 AF |
8908 | }, |
8909 | { | |
bb5b3501 | 8910 | /* MOD_VEX_0F3A33_L_0 */ |
ab4e4ed5 | 8911 | { Bad_Opcode }, |
464d2b65 | 8912 | { "kshiftl%DQ", { MaskG, MaskE, Ib }, PREFIX_DATA }, |
ab4e4ed5 | 8913 | }, |
467bbef0 JB |
8914 | { |
8915 | /* MOD_VEX_0FXOP_09_12 */ | |
8916 | { Bad_Opcode }, | |
8917 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_12_M_1) }, | |
8918 | }, | |
ad692897 L |
8919 | |
8920 | #include "i386-dis-evex-mod.h" | |
b844680a L |
8921 | }; |
8922 | ||
1ceb70f8 | 8923 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
8924 | { |
8925 | /* RM_C6_REG_7 */ | |
bf890a93 | 8926 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
8927 | }, |
8928 | { | |
8929 | /* RM_C7_REG_7 */ | |
376cd056 | 8930 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 8931 | }, |
b844680a | 8932 | { |
1ceb70f8 | 8933 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 8934 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
8935 | { "vmcall", { Skip_MODRM }, 0 }, |
8936 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
8937 | { "vmresume", { Skip_MODRM }, 0 }, | |
8938 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 8939 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
8940 | }, |
8941 | { | |
1ceb70f8 | 8942 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
8943 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
8944 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
8945 | { "clac", { Skip_MODRM }, 0 }, | |
8946 | { "stac", { Skip_MODRM }, 0 }, | |
81d54bb7 CL |
8947 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, |
8948 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, | |
8949 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) }, | |
8950 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) }, | |
b844680a | 8951 | }, |
475a2301 L |
8952 | { |
8953 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
8954 | { "xgetbv", { Skip_MODRM }, 0 }, |
8955 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
8956 | { Bad_Opcode }, |
8957 | { Bad_Opcode }, | |
bf890a93 IT |
8958 | { "vmfunc", { Skip_MODRM }, 0 }, |
8959 | { "xend", { Skip_MODRM }, 0 }, | |
8960 | { "xtest", { Skip_MODRM }, 0 }, | |
8961 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 8962 | }, |
b844680a | 8963 | { |
1ceb70f8 | 8964 | /* RM_0F01_REG_3 */ |
bf890a93 | 8965 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 8966 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
8967 | { "vmload", { Skip_MODRM }, 0 }, |
8968 | { "vmsave", { Skip_MODRM }, 0 }, | |
8969 | { "stgi", { Skip_MODRM }, 0 }, | |
8970 | { "clgi", { Skip_MODRM }, 0 }, | |
8971 | { "skinit", { Skip_MODRM }, 0 }, | |
8972 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 8973 | }, |
8eab4136 | 8974 | { |
f8687e93 JB |
8975 | /* RM_0F01_REG_5_MOD_3 */ |
8976 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 8977 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 8978 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 | 8979 | { Bad_Opcode }, |
f64c42a9 LC |
8980 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) }, |
8981 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) }, | |
8982 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) }, | |
8983 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) }, | |
8eab4136 | 8984 | }, |
4e7d34a6 | 8985 | { |
f8687e93 | 8986 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
8987 | { "swapgs", { Skip_MODRM }, 0 }, |
8988 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 | 8989 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
035e7389 | 8990 | { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, |
bf890a93 | 8991 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 8992 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 8993 | }, |
603555e5 | 8994 | { |
f8687e93 | 8995 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
8996 | { "nopQ", { Ev }, 0 }, |
8997 | { "nopQ", { Ev }, 0 }, | |
8998 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
8999 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
9000 | { "nopQ", { Ev }, 0 }, | |
9001 | { "nopQ", { Ev }, 0 }, | |
9002 | { "nopQ", { Ev }, 0 }, | |
9003 | { "nopQ", { Ev }, 0 }, | |
9004 | }, | |
c1fa250a LC |
9005 | { |
9006 | /* RM_0F3A0F_P_1_MOD_3_REG_0 */ | |
9007 | { "hreset", { Skip_MODRM, Ib }, 0 }, | |
9008 | }, | |
b844680a | 9009 | { |
f8687e93 | 9010 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 9011 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 9012 | }, |
bbedc832 | 9013 | { |
f8687e93 | 9014 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
9015 | { "sfence", { Skip_MODRM }, 0 }, |
9016 | ||
144c41d9 | 9017 | }, |
260cd341 LC |
9018 | { |
9019 | /* RM_VEX_0F3849_X86_64_P_0_W_0_M_1_R_0 */ | |
9020 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64_P_0_W_0_M_1_REG_0_RM_0) }, | |
9021 | }, | |
b844680a L |
9022 | }; |
9023 | ||
c608c12e AM |
9024 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
9025 | ||
f16cd0d5 L |
9026 | /* We use the high bit to indicate different name for the same |
9027 | prefix. */ | |
f16cd0d5 | 9028 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
9029 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
9030 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 9031 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 9032 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 9033 | |
1d67fe3b TT |
9034 | /* Remember if the current op is a jump instruction. */ |
9035 | static bfd_boolean op_is_jump = FALSE; | |
9036 | ||
f16cd0d5 | 9037 | static int |
26ca5450 | 9038 | ckprefix (void) |
252b5132 | 9039 | { |
f16cd0d5 | 9040 | int newrex, i, length; |
52b15da3 | 9041 | rex = 0; |
252b5132 | 9042 | prefixes = 0; |
7d421014 | 9043 | used_prefixes = 0; |
52b15da3 | 9044 | rex_used = 0; |
f16cd0d5 L |
9045 | last_lock_prefix = -1; |
9046 | last_repz_prefix = -1; | |
9047 | last_repnz_prefix = -1; | |
9048 | last_data_prefix = -1; | |
9049 | last_addr_prefix = -1; | |
9050 | last_rex_prefix = -1; | |
9051 | last_seg_prefix = -1; | |
d9949a36 | 9052 | fwait_prefix = -1; |
285ca992 | 9053 | active_seg_prefix = 0; |
f310f33d L |
9054 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
9055 | all_prefixes[i] = 0; | |
9056 | i = 0; | |
f16cd0d5 L |
9057 | length = 0; |
9058 | /* The maximum instruction length is 15bytes. */ | |
9059 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
9060 | { |
9061 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 9062 | newrex = 0; |
252b5132 RH |
9063 | switch (*codep) |
9064 | { | |
52b15da3 JH |
9065 | /* REX prefixes family. */ |
9066 | case 0x40: | |
9067 | case 0x41: | |
9068 | case 0x42: | |
9069 | case 0x43: | |
9070 | case 0x44: | |
9071 | case 0x45: | |
9072 | case 0x46: | |
9073 | case 0x47: | |
9074 | case 0x48: | |
9075 | case 0x49: | |
9076 | case 0x4a: | |
9077 | case 0x4b: | |
9078 | case 0x4c: | |
9079 | case 0x4d: | |
9080 | case 0x4e: | |
9081 | case 0x4f: | |
f16cd0d5 L |
9082 | if (address_mode == mode_64bit) |
9083 | newrex = *codep; | |
9084 | else | |
9085 | return 1; | |
9086 | last_rex_prefix = i; | |
52b15da3 | 9087 | break; |
252b5132 RH |
9088 | case 0xf3: |
9089 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 9090 | last_repz_prefix = i; |
252b5132 RH |
9091 | break; |
9092 | case 0xf2: | |
9093 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 9094 | last_repnz_prefix = i; |
252b5132 RH |
9095 | break; |
9096 | case 0xf0: | |
9097 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 9098 | last_lock_prefix = i; |
252b5132 RH |
9099 | break; |
9100 | case 0x2e: | |
9101 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 9102 | last_seg_prefix = i; |
285ca992 | 9103 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
9104 | break; |
9105 | case 0x36: | |
9106 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 9107 | last_seg_prefix = i; |
285ca992 | 9108 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
9109 | break; |
9110 | case 0x3e: | |
9111 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 9112 | last_seg_prefix = i; |
285ca992 | 9113 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
9114 | break; |
9115 | case 0x26: | |
9116 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 9117 | last_seg_prefix = i; |
285ca992 | 9118 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
9119 | break; |
9120 | case 0x64: | |
9121 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 9122 | last_seg_prefix = i; |
285ca992 | 9123 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
9124 | break; |
9125 | case 0x65: | |
9126 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 9127 | last_seg_prefix = i; |
285ca992 | 9128 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
9129 | break; |
9130 | case 0x66: | |
9131 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 9132 | last_data_prefix = i; |
252b5132 RH |
9133 | break; |
9134 | case 0x67: | |
9135 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 9136 | last_addr_prefix = i; |
252b5132 | 9137 | break; |
5076851f | 9138 | case FWAIT_OPCODE: |
252b5132 RH |
9139 | /* fwait is really an instruction. If there are prefixes |
9140 | before the fwait, they belong to the fwait, *not* to the | |
9141 | following instruction. */ | |
d9949a36 | 9142 | fwait_prefix = i; |
3e7d61b2 | 9143 | if (prefixes || rex) |
252b5132 RH |
9144 | { |
9145 | prefixes |= PREFIX_FWAIT; | |
9146 | codep++; | |
6c067bbb RM |
9147 | /* This ensures that the previous REX prefixes are noticed |
9148 | as unused prefixes, as in the return case below. */ | |
9149 | rex_used = rex; | |
f16cd0d5 | 9150 | return 1; |
252b5132 RH |
9151 | } |
9152 | prefixes = PREFIX_FWAIT; | |
9153 | break; | |
9154 | default: | |
f16cd0d5 | 9155 | return 1; |
252b5132 | 9156 | } |
52b15da3 JH |
9157 | /* Rex is ignored when followed by another prefix. */ |
9158 | if (rex) | |
9159 | { | |
3e7d61b2 | 9160 | rex_used = rex; |
f16cd0d5 | 9161 | return 1; |
52b15da3 | 9162 | } |
f16cd0d5 | 9163 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 9164 | all_prefixes[i++] = *codep; |
52b15da3 | 9165 | rex = newrex; |
252b5132 | 9166 | codep++; |
f16cd0d5 L |
9167 | length++; |
9168 | } | |
9169 | return 0; | |
9170 | } | |
9171 | ||
7d421014 ILT |
9172 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
9173 | prefix byte. */ | |
9174 | ||
9175 | static const char * | |
26ca5450 | 9176 | prefix_name (int pref, int sizeflag) |
7d421014 | 9177 | { |
0003779b L |
9178 | static const char *rexes [16] = |
9179 | { | |
9180 | "rex", /* 0x40 */ | |
9181 | "rex.B", /* 0x41 */ | |
9182 | "rex.X", /* 0x42 */ | |
9183 | "rex.XB", /* 0x43 */ | |
9184 | "rex.R", /* 0x44 */ | |
9185 | "rex.RB", /* 0x45 */ | |
9186 | "rex.RX", /* 0x46 */ | |
9187 | "rex.RXB", /* 0x47 */ | |
9188 | "rex.W", /* 0x48 */ | |
9189 | "rex.WB", /* 0x49 */ | |
9190 | "rex.WX", /* 0x4a */ | |
9191 | "rex.WXB", /* 0x4b */ | |
9192 | "rex.WR", /* 0x4c */ | |
9193 | "rex.WRB", /* 0x4d */ | |
9194 | "rex.WRX", /* 0x4e */ | |
9195 | "rex.WRXB", /* 0x4f */ | |
9196 | }; | |
9197 | ||
7d421014 ILT |
9198 | switch (pref) |
9199 | { | |
52b15da3 JH |
9200 | /* REX prefixes family. */ |
9201 | case 0x40: | |
52b15da3 | 9202 | case 0x41: |
52b15da3 | 9203 | case 0x42: |
52b15da3 | 9204 | case 0x43: |
52b15da3 | 9205 | case 0x44: |
52b15da3 | 9206 | case 0x45: |
52b15da3 | 9207 | case 0x46: |
52b15da3 | 9208 | case 0x47: |
52b15da3 | 9209 | case 0x48: |
52b15da3 | 9210 | case 0x49: |
52b15da3 | 9211 | case 0x4a: |
52b15da3 | 9212 | case 0x4b: |
52b15da3 | 9213 | case 0x4c: |
52b15da3 | 9214 | case 0x4d: |
52b15da3 | 9215 | case 0x4e: |
52b15da3 | 9216 | case 0x4f: |
0003779b | 9217 | return rexes [pref - 0x40]; |
7d421014 ILT |
9218 | case 0xf3: |
9219 | return "repz"; | |
9220 | case 0xf2: | |
9221 | return "repnz"; | |
9222 | case 0xf0: | |
9223 | return "lock"; | |
9224 | case 0x2e: | |
9225 | return "cs"; | |
9226 | case 0x36: | |
9227 | return "ss"; | |
9228 | case 0x3e: | |
9229 | return "ds"; | |
9230 | case 0x26: | |
9231 | return "es"; | |
9232 | case 0x64: | |
9233 | return "fs"; | |
9234 | case 0x65: | |
9235 | return "gs"; | |
9236 | case 0x66: | |
9237 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
9238 | case 0x67: | |
cb712a9e | 9239 | if (address_mode == mode_64bit) |
db6eb5be | 9240 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 9241 | else |
2888cb7a | 9242 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
9243 | case FWAIT_OPCODE: |
9244 | return "fwait"; | |
f16cd0d5 L |
9245 | case REP_PREFIX: |
9246 | return "rep"; | |
42164a71 L |
9247 | case XACQUIRE_PREFIX: |
9248 | return "xacquire"; | |
9249 | case XRELEASE_PREFIX: | |
9250 | return "xrelease"; | |
7e8b059b L |
9251 | case BND_PREFIX: |
9252 | return "bnd"; | |
04ef582a L |
9253 | case NOTRACK_PREFIX: |
9254 | return "notrack"; | |
7d421014 ILT |
9255 | default: |
9256 | return NULL; | |
9257 | } | |
9258 | } | |
9259 | ||
ce518a5f L |
9260 | static char op_out[MAX_OPERANDS][100]; |
9261 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 9262 | static int two_source_ops; |
ce518a5f L |
9263 | static bfd_vma op_address[MAX_OPERANDS]; |
9264 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 9265 | static bfd_vma start_pc; |
ce518a5f | 9266 | |
252b5132 RH |
9267 | /* |
9268 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
9269 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
9270 | * section of the "Virtual 8086 Mode" chapter.) | |
9271 | * 'pc' should be the address of this instruction, it will | |
9272 | * be used to print the target address if this is a relative jump or call | |
9273 | * The function returns the length of this instruction in bytes. | |
9274 | */ | |
9275 | ||
252b5132 | 9276 | static char intel_syntax; |
9d141669 | 9277 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
9278 | static char open_char; |
9279 | static char close_char; | |
9280 | static char separator_char; | |
9281 | static char scale_char; | |
9282 | ||
5db04b09 L |
9283 | enum x86_64_isa |
9284 | { | |
d835a58b | 9285 | amd64 = 1, |
5db04b09 L |
9286 | intel64 |
9287 | }; | |
9288 | ||
9289 | static enum x86_64_isa isa64; | |
9290 | ||
e396998b AM |
9291 | /* Here for backwards compatibility. When gdb stops using |
9292 | print_insn_i386_att and print_insn_i386_intel these functions can | |
9293 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 9294 | int |
26ca5450 | 9295 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9296 | { |
9297 | intel_syntax = 0; | |
e396998b AM |
9298 | |
9299 | return print_insn (pc, info); | |
252b5132 RH |
9300 | } |
9301 | ||
9302 | int | |
26ca5450 | 9303 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
9304 | { |
9305 | intel_syntax = 1; | |
e396998b AM |
9306 | |
9307 | return print_insn (pc, info); | |
252b5132 RH |
9308 | } |
9309 | ||
e396998b | 9310 | int |
26ca5450 | 9311 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
9312 | { |
9313 | intel_syntax = -1; | |
9314 | ||
9315 | return print_insn (pc, info); | |
9316 | } | |
9317 | ||
f59a29b9 L |
9318 | void |
9319 | print_i386_disassembler_options (FILE *stream) | |
9320 | { | |
9321 | fprintf (stream, _("\n\ | |
9322 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
9323 | with the -M switch (multiple options should be separated by commas):\n")); | |
9324 | ||
9325 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
9326 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
9327 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
9328 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
9329 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
9330 | fprintf (stream, _(" att-mnemonic\n" |
9331 | " Display instruction in AT&T mnemonic\n")); | |
9332 | fprintf (stream, _(" intel-mnemonic\n" | |
9333 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
9334 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
9335 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
9336 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
9337 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
9338 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
9339 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
9340 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
9341 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
9342 | } |
9343 | ||
592d1631 | 9344 | /* Bad opcode. */ |
bf890a93 | 9345 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 9346 | |
b844680a L |
9347 | /* Get a pointer to struct dis386 with a valid name. */ |
9348 | ||
9349 | static const struct dis386 * | |
8bb15339 | 9350 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 9351 | { |
91d6fa6a | 9352 | int vindex, vex_table_index; |
b844680a L |
9353 | |
9354 | if (dp->name != NULL) | |
9355 | return dp; | |
9356 | ||
9357 | switch (dp->op[0].bytemode) | |
9358 | { | |
1ceb70f8 L |
9359 | case USE_REG_TABLE: |
9360 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
9361 | break; | |
9362 | ||
9363 | case USE_MOD_TABLE: | |
91d6fa6a NC |
9364 | vindex = modrm.mod == 0x3 ? 1 : 0; |
9365 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
9366 | break; |
9367 | ||
9368 | case USE_RM_TABLE: | |
9369 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
9370 | break; |
9371 | ||
4e7d34a6 | 9372 | case USE_PREFIX_TABLE: |
c0f3af97 | 9373 | if (need_vex) |
b844680a | 9374 | { |
c0f3af97 L |
9375 | /* The prefix in VEX is implicit. */ |
9376 | switch (vex.prefix) | |
9377 | { | |
9378 | case 0: | |
91d6fa6a | 9379 | vindex = 0; |
c0f3af97 L |
9380 | break; |
9381 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 9382 | vindex = 1; |
c0f3af97 L |
9383 | break; |
9384 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 9385 | vindex = 2; |
c0f3af97 L |
9386 | break; |
9387 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 9388 | vindex = 3; |
c0f3af97 L |
9389 | break; |
9390 | default: | |
9391 | abort (); | |
9392 | break; | |
9393 | } | |
b844680a | 9394 | } |
7bb15c6f | 9395 | else |
b844680a | 9396 | { |
285ca992 L |
9397 | int last_prefix = -1; |
9398 | int prefix = 0; | |
91d6fa6a | 9399 | vindex = 0; |
285ca992 L |
9400 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
9401 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
9402 | last one wins. */ | |
9403 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 9404 | { |
285ca992 | 9405 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 9406 | { |
285ca992 L |
9407 | vindex = 1; |
9408 | prefix = PREFIX_REPZ; | |
9409 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
9410 | } |
9411 | else | |
b844680a | 9412 | { |
285ca992 L |
9413 | vindex = 3; |
9414 | prefix = PREFIX_REPNZ; | |
9415 | last_prefix = last_repnz_prefix; | |
b844680a | 9416 | } |
285ca992 | 9417 | |
507bd325 L |
9418 | /* Check if prefix should be ignored. */ |
9419 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
9420 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
9421 | & prefix) != 0) | |
285ca992 L |
9422 | vindex = 0; |
9423 | } | |
9424 | ||
9425 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
9426 | { | |
9427 | vindex = 2; | |
9428 | prefix = PREFIX_DATA; | |
9429 | last_prefix = last_data_prefix; | |
9430 | } | |
9431 | ||
9432 | if (vindex != 0) | |
9433 | { | |
9434 | used_prefixes |= prefix; | |
9435 | all_prefixes[last_prefix] = 0; | |
b844680a L |
9436 | } |
9437 | } | |
91d6fa6a | 9438 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
9439 | break; |
9440 | ||
4e7d34a6 | 9441 | case USE_X86_64_TABLE: |
91d6fa6a NC |
9442 | vindex = address_mode == mode_64bit ? 1 : 0; |
9443 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
9444 | break; |
9445 | ||
4e7d34a6 | 9446 | case USE_3BYTE_TABLE: |
8bb15339 | 9447 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
9448 | vindex = *codep++; |
9449 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 9450 | end_codep = codep; |
8bb15339 L |
9451 | modrm.mod = (*codep >> 6) & 3; |
9452 | modrm.reg = (*codep >> 3) & 7; | |
9453 | modrm.rm = *codep & 7; | |
9454 | break; | |
9455 | ||
c0f3af97 L |
9456 | case USE_VEX_LEN_TABLE: |
9457 | if (!need_vex) | |
9458 | abort (); | |
9459 | ||
9460 | switch (vex.length) | |
9461 | { | |
9462 | case 128: | |
91d6fa6a | 9463 | vindex = 0; |
c0f3af97 L |
9464 | break; |
9465 | case 256: | |
91d6fa6a | 9466 | vindex = 1; |
c0f3af97 L |
9467 | break; |
9468 | default: | |
9469 | abort (); | |
9470 | break; | |
9471 | } | |
9472 | ||
91d6fa6a | 9473 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
9474 | break; |
9475 | ||
04e2a182 L |
9476 | case USE_EVEX_LEN_TABLE: |
9477 | if (!vex.evex) | |
9478 | abort (); | |
9479 | ||
9480 | switch (vex.length) | |
9481 | { | |
9482 | case 128: | |
9483 | vindex = 0; | |
9484 | break; | |
9485 | case 256: | |
9486 | vindex = 1; | |
9487 | break; | |
9488 | case 512: | |
9489 | vindex = 2; | |
9490 | break; | |
9491 | default: | |
9492 | abort (); | |
9493 | break; | |
9494 | } | |
9495 | ||
9496 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
9497 | break; | |
9498 | ||
f88c9eb0 SP |
9499 | case USE_XOP_8F_TABLE: |
9500 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
9501 | rex = ~(*codep >> 5) & 0x7; |
9502 | ||
9503 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
9504 | switch ((*codep & 0x1f)) | |
9505 | { | |
9506 | default: | |
f07af43e L |
9507 | dp = &bad_opcode; |
9508 | return dp; | |
5dd85c99 SP |
9509 | case 0x8: |
9510 | vex_table_index = XOP_08; | |
9511 | break; | |
f88c9eb0 SP |
9512 | case 0x9: |
9513 | vex_table_index = XOP_09; | |
9514 | break; | |
9515 | case 0xa: | |
9516 | vex_table_index = XOP_0A; | |
9517 | break; | |
9518 | } | |
9519 | codep++; | |
9520 | vex.w = *codep & 0x80; | |
9521 | if (vex.w && address_mode == mode_64bit) | |
9522 | rex |= REX_W; | |
9523 | ||
9524 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 9525 | if (address_mode != mode_64bit) |
f07af43e | 9526 | { |
abfcb414 AP |
9527 | /* In 16/32-bit mode REX_B is silently ignored. */ |
9528 | rex &= ~REX_B; | |
f07af43e | 9529 | } |
f88c9eb0 SP |
9530 | |
9531 | vex.length = (*codep & 0x4) ? 256 : 128; | |
9532 | switch ((*codep & 0x3)) | |
9533 | { | |
9534 | case 0: | |
f88c9eb0 SP |
9535 | break; |
9536 | case 1: | |
9537 | vex.prefix = DATA_PREFIX_OPCODE; | |
9538 | break; | |
9539 | case 2: | |
9540 | vex.prefix = REPE_PREFIX_OPCODE; | |
9541 | break; | |
9542 | case 3: | |
9543 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9544 | break; | |
9545 | } | |
9546 | need_vex = 1; | |
f88c9eb0 | 9547 | codep++; |
91d6fa6a NC |
9548 | vindex = *codep++; |
9549 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 9550 | |
285ca992 | 9551 | end_codep = codep; |
c48244a5 SP |
9552 | FETCH_DATA (info, codep + 1); |
9553 | modrm.mod = (*codep >> 6) & 3; | |
9554 | modrm.reg = (*codep >> 3) & 7; | |
9555 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
9556 | |
9557 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
9558 | having to decode the bits for every otherwise valid encoding. */ | |
9559 | if (vex.prefix) | |
9560 | return &bad_opcode; | |
f88c9eb0 SP |
9561 | break; |
9562 | ||
c0f3af97 | 9563 | case USE_VEX_C4_TABLE: |
43234a1e | 9564 | /* VEX prefix. */ |
c0f3af97 | 9565 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
9566 | rex = ~(*codep >> 5) & 0x7; |
9567 | switch ((*codep & 0x1f)) | |
9568 | { | |
9569 | default: | |
f07af43e L |
9570 | dp = &bad_opcode; |
9571 | return dp; | |
c0f3af97 | 9572 | case 0x1: |
f88c9eb0 | 9573 | vex_table_index = VEX_0F; |
c0f3af97 L |
9574 | break; |
9575 | case 0x2: | |
f88c9eb0 | 9576 | vex_table_index = VEX_0F38; |
c0f3af97 L |
9577 | break; |
9578 | case 0x3: | |
f88c9eb0 | 9579 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
9580 | break; |
9581 | } | |
9582 | codep++; | |
9583 | vex.w = *codep & 0x80; | |
9889cbb1 | 9584 | if (address_mode == mode_64bit) |
f07af43e | 9585 | { |
9889cbb1 L |
9586 | if (vex.w) |
9587 | rex |= REX_W; | |
9889cbb1 L |
9588 | } |
9589 | else | |
9590 | { | |
9591 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
9592 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 9593 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 9594 | rex = 0; |
f07af43e | 9595 | } |
5f847646 | 9596 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
9597 | vex.length = (*codep & 0x4) ? 256 : 128; |
9598 | switch ((*codep & 0x3)) | |
9599 | { | |
9600 | case 0: | |
c0f3af97 L |
9601 | break; |
9602 | case 1: | |
9603 | vex.prefix = DATA_PREFIX_OPCODE; | |
9604 | break; | |
9605 | case 2: | |
9606 | vex.prefix = REPE_PREFIX_OPCODE; | |
9607 | break; | |
9608 | case 3: | |
9609 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9610 | break; | |
9611 | } | |
9612 | need_vex = 1; | |
c0f3af97 | 9613 | codep++; |
91d6fa6a NC |
9614 | vindex = *codep++; |
9615 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 9616 | end_codep = codep; |
53c4d625 JB |
9617 | /* There is no MODRM byte for VEX0F 77. */ |
9618 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
9619 | { |
9620 | FETCH_DATA (info, codep + 1); | |
9621 | modrm.mod = (*codep >> 6) & 3; | |
9622 | modrm.reg = (*codep >> 3) & 7; | |
9623 | modrm.rm = *codep & 7; | |
9624 | } | |
9625 | break; | |
9626 | ||
9627 | case USE_VEX_C5_TABLE: | |
43234a1e | 9628 | /* VEX prefix. */ |
c0f3af97 | 9629 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
9630 | rex = (*codep & 0x80) ? 0 : REX_R; |
9631 | ||
9889cbb1 L |
9632 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
9633 | VEX.vvvv is 1. */ | |
c0f3af97 | 9634 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
9635 | vex.length = (*codep & 0x4) ? 256 : 128; |
9636 | switch ((*codep & 0x3)) | |
9637 | { | |
9638 | case 0: | |
c0f3af97 L |
9639 | break; |
9640 | case 1: | |
9641 | vex.prefix = DATA_PREFIX_OPCODE; | |
9642 | break; | |
9643 | case 2: | |
9644 | vex.prefix = REPE_PREFIX_OPCODE; | |
9645 | break; | |
9646 | case 3: | |
9647 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9648 | break; | |
9649 | } | |
9650 | need_vex = 1; | |
c0f3af97 | 9651 | codep++; |
91d6fa6a NC |
9652 | vindex = *codep++; |
9653 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 9654 | end_codep = codep; |
53c4d625 JB |
9655 | /* There is no MODRM byte for VEX 77. */ |
9656 | if (vindex != 0x77) | |
c0f3af97 L |
9657 | { |
9658 | FETCH_DATA (info, codep + 1); | |
9659 | modrm.mod = (*codep >> 6) & 3; | |
9660 | modrm.reg = (*codep >> 3) & 7; | |
9661 | modrm.rm = *codep & 7; | |
9662 | } | |
9663 | break; | |
9664 | ||
9e30b8e0 L |
9665 | case USE_VEX_W_TABLE: |
9666 | if (!need_vex) | |
9667 | abort (); | |
9668 | ||
9669 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
9670 | break; | |
9671 | ||
43234a1e L |
9672 | case USE_EVEX_TABLE: |
9673 | two_source_ops = 0; | |
9674 | /* EVEX prefix. */ | |
9675 | vex.evex = 1; | |
9676 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
9677 | /* The first byte after 0x62. */ |
9678 | rex = ~(*codep >> 5) & 0x7; | |
9679 | vex.r = *codep & 0x10; | |
9680 | switch ((*codep & 0xf)) | |
9681 | { | |
9682 | default: | |
9683 | return &bad_opcode; | |
9684 | case 0x1: | |
9685 | vex_table_index = EVEX_0F; | |
9686 | break; | |
9687 | case 0x2: | |
9688 | vex_table_index = EVEX_0F38; | |
9689 | break; | |
9690 | case 0x3: | |
9691 | vex_table_index = EVEX_0F3A; | |
9692 | break; | |
9693 | } | |
9694 | ||
9695 | /* The second byte after 0x62. */ | |
9696 | codep++; | |
9697 | vex.w = *codep & 0x80; | |
9698 | if (vex.w && address_mode == mode_64bit) | |
9699 | rex |= REX_W; | |
9700 | ||
9701 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
9702 | |
9703 | /* The U bit. */ | |
9704 | if (!(*codep & 0x4)) | |
9705 | return &bad_opcode; | |
9706 | ||
9707 | switch ((*codep & 0x3)) | |
9708 | { | |
9709 | case 0: | |
43234a1e L |
9710 | break; |
9711 | case 1: | |
9712 | vex.prefix = DATA_PREFIX_OPCODE; | |
9713 | break; | |
9714 | case 2: | |
9715 | vex.prefix = REPE_PREFIX_OPCODE; | |
9716 | break; | |
9717 | case 3: | |
9718 | vex.prefix = REPNE_PREFIX_OPCODE; | |
9719 | break; | |
9720 | } | |
9721 | ||
9722 | /* The third byte after 0x62. */ | |
9723 | codep++; | |
9724 | ||
9725 | /* Remember the static rounding bits. */ | |
9726 | vex.ll = (*codep >> 5) & 3; | |
9727 | vex.b = (*codep & 0x10) != 0; | |
9728 | ||
9729 | vex.v = *codep & 0x8; | |
9730 | vex.mask_register_specifier = *codep & 0x7; | |
9731 | vex.zeroing = *codep & 0x80; | |
9732 | ||
5f847646 JB |
9733 | if (address_mode != mode_64bit) |
9734 | { | |
9735 | /* In 16/32-bit mode silently ignore following bits. */ | |
9736 | rex &= ~REX_B; | |
9737 | vex.r = 1; | |
9738 | vex.v = 1; | |
9739 | } | |
9740 | ||
43234a1e | 9741 | need_vex = 1; |
43234a1e L |
9742 | codep++; |
9743 | vindex = *codep++; | |
9744 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 9745 | end_codep = codep; |
43234a1e L |
9746 | FETCH_DATA (info, codep + 1); |
9747 | modrm.mod = (*codep >> 6) & 3; | |
9748 | modrm.reg = (*codep >> 3) & 7; | |
9749 | modrm.rm = *codep & 7; | |
9750 | ||
9751 | /* Set vector length. */ | |
9752 | if (modrm.mod == 3 && vex.b) | |
9753 | vex.length = 512; | |
9754 | else | |
9755 | { | |
9756 | switch (vex.ll) | |
9757 | { | |
9758 | case 0x0: | |
9759 | vex.length = 128; | |
9760 | break; | |
9761 | case 0x1: | |
9762 | vex.length = 256; | |
9763 | break; | |
9764 | case 0x2: | |
9765 | vex.length = 512; | |
9766 | break; | |
9767 | default: | |
9768 | return &bad_opcode; | |
9769 | } | |
9770 | } | |
9771 | break; | |
9772 | ||
592d1631 L |
9773 | case 0: |
9774 | dp = &bad_opcode; | |
9775 | break; | |
9776 | ||
b844680a | 9777 | default: |
d34b5006 | 9778 | abort (); |
b844680a L |
9779 | } |
9780 | ||
9781 | if (dp->name != NULL) | |
9782 | return dp; | |
9783 | else | |
8bb15339 | 9784 | return get_valid_dis386 (dp, info); |
b844680a L |
9785 | } |
9786 | ||
dfc8cf43 | 9787 | static void |
55cf16e1 | 9788 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
9789 | { |
9790 | /* If modrm.mod == 3, operand must be register. */ | |
9791 | if (need_modrm | |
55cf16e1 | 9792 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
9793 | && modrm.mod != 3 |
9794 | && modrm.rm == 4) | |
9795 | { | |
9796 | FETCH_DATA (info, codep + 2); | |
9797 | sib.index = (codep [1] >> 3) & 7; | |
9798 | sib.scale = (codep [1] >> 6) & 3; | |
9799 | sib.base = codep [1] & 7; | |
9800 | } | |
9801 | } | |
9802 | ||
e396998b | 9803 | static int |
26ca5450 | 9804 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 9805 | { |
2da11e11 | 9806 | const struct dis386 *dp; |
252b5132 | 9807 | int i; |
ce518a5f | 9808 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 9809 | int needcomma; |
df18fdba | 9810 | int sizeflag, orig_sizeflag; |
e396998b | 9811 | const char *p; |
252b5132 | 9812 | struct dis_private priv; |
f16cd0d5 | 9813 | int prefix_length; |
252b5132 | 9814 | |
d7921315 L |
9815 | priv.orig_sizeflag = AFLAG | DFLAG; |
9816 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 9817 | address_mode = mode_32bit; |
2da11e11 | 9818 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
9819 | { |
9820 | address_mode = mode_16bit; | |
9821 | priv.orig_sizeflag = 0; | |
9822 | } | |
2da11e11 | 9823 | else |
d7921315 L |
9824 | address_mode = mode_64bit; |
9825 | ||
9826 | if (intel_syntax == (char) -1) | |
9827 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
9828 | |
9829 | for (p = info->disassembler_options; p != NULL; ) | |
9830 | { | |
5db04b09 L |
9831 | if (CONST_STRNEQ (p, "amd64")) |
9832 | isa64 = amd64; | |
9833 | else if (CONST_STRNEQ (p, "intel64")) | |
9834 | isa64 = intel64; | |
9835 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 9836 | { |
cb712a9e | 9837 | address_mode = mode_64bit; |
2a1bb84c | 9838 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9839 | } |
0112cd26 | 9840 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 9841 | { |
cb712a9e | 9842 | address_mode = mode_32bit; |
2a1bb84c | 9843 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9844 | } |
0112cd26 | 9845 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 9846 | { |
cb712a9e | 9847 | address_mode = mode_16bit; |
2a1bb84c | 9848 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 9849 | } |
0112cd26 | 9850 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
9851 | { |
9852 | intel_syntax = 1; | |
9d141669 L |
9853 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
9854 | intel_mnemonic = 1; | |
e396998b | 9855 | } |
0112cd26 | 9856 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
9857 | { |
9858 | intel_syntax = 0; | |
9d141669 L |
9859 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
9860 | intel_mnemonic = 0; | |
e396998b | 9861 | } |
0112cd26 | 9862 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 9863 | { |
f59a29b9 L |
9864 | if (address_mode == mode_64bit) |
9865 | { | |
9866 | if (p[4] == '3' && p[5] == '2') | |
9867 | priv.orig_sizeflag &= ~AFLAG; | |
9868 | else if (p[4] == '6' && p[5] == '4') | |
9869 | priv.orig_sizeflag |= AFLAG; | |
9870 | } | |
9871 | else | |
9872 | { | |
9873 | if (p[4] == '1' && p[5] == '6') | |
9874 | priv.orig_sizeflag &= ~AFLAG; | |
9875 | else if (p[4] == '3' && p[5] == '2') | |
9876 | priv.orig_sizeflag |= AFLAG; | |
9877 | } | |
e396998b | 9878 | } |
0112cd26 | 9879 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
9880 | { |
9881 | if (p[4] == '1' && p[5] == '6') | |
9882 | priv.orig_sizeflag &= ~DFLAG; | |
9883 | else if (p[4] == '3' && p[5] == '2') | |
9884 | priv.orig_sizeflag |= DFLAG; | |
9885 | } | |
0112cd26 | 9886 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
9887 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
9888 | ||
9889 | p = strchr (p, ','); | |
9890 | if (p != NULL) | |
9891 | p++; | |
9892 | } | |
9893 | ||
c0f92bf9 L |
9894 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
9895 | { | |
9896 | (*info->fprintf_func) (info->stream, | |
9897 | _("64-bit address is disabled")); | |
9898 | return -1; | |
9899 | } | |
9900 | ||
e396998b AM |
9901 | if (intel_syntax) |
9902 | { | |
9903 | names64 = intel_names64; | |
9904 | names32 = intel_names32; | |
9905 | names16 = intel_names16; | |
9906 | names8 = intel_names8; | |
9907 | names8rex = intel_names8rex; | |
9908 | names_seg = intel_names_seg; | |
b9733481 | 9909 | names_mm = intel_names_mm; |
7e8b059b | 9910 | names_bnd = intel_names_bnd; |
b9733481 L |
9911 | names_xmm = intel_names_xmm; |
9912 | names_ymm = intel_names_ymm; | |
43234a1e | 9913 | names_zmm = intel_names_zmm; |
260cd341 | 9914 | names_tmm = intel_names_tmm; |
db51cc60 L |
9915 | index64 = intel_index64; |
9916 | index32 = intel_index32; | |
43234a1e | 9917 | names_mask = intel_names_mask; |
e396998b AM |
9918 | index16 = intel_index16; |
9919 | open_char = '['; | |
9920 | close_char = ']'; | |
9921 | separator_char = '+'; | |
9922 | scale_char = '*'; | |
9923 | } | |
9924 | else | |
9925 | { | |
9926 | names64 = att_names64; | |
9927 | names32 = att_names32; | |
9928 | names16 = att_names16; | |
9929 | names8 = att_names8; | |
9930 | names8rex = att_names8rex; | |
9931 | names_seg = att_names_seg; | |
b9733481 | 9932 | names_mm = att_names_mm; |
7e8b059b | 9933 | names_bnd = att_names_bnd; |
b9733481 L |
9934 | names_xmm = att_names_xmm; |
9935 | names_ymm = att_names_ymm; | |
43234a1e | 9936 | names_zmm = att_names_zmm; |
260cd341 | 9937 | names_tmm = att_names_tmm; |
db51cc60 L |
9938 | index64 = att_index64; |
9939 | index32 = att_index32; | |
43234a1e | 9940 | names_mask = att_names_mask; |
e396998b AM |
9941 | index16 = att_index16; |
9942 | open_char = '('; | |
9943 | close_char = ')'; | |
9944 | separator_char = ','; | |
9945 | scale_char = ','; | |
9946 | } | |
2da11e11 | 9947 | |
4fe53c98 | 9948 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
9949 | puts most long word instructions on a single line. Use 8 bytes |
9950 | for Intel L1OM. */ | |
d7921315 | 9951 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
9952 | info->bytes_per_line = 8; |
9953 | else | |
9954 | info->bytes_per_line = 7; | |
252b5132 | 9955 | |
26ca5450 | 9956 | info->private_data = &priv; |
252b5132 RH |
9957 | priv.max_fetched = priv.the_buffer; |
9958 | priv.insn_start = pc; | |
252b5132 RH |
9959 | |
9960 | obuf[0] = 0; | |
ce518a5f L |
9961 | for (i = 0; i < MAX_OPERANDS; ++i) |
9962 | { | |
9963 | op_out[i][0] = 0; | |
9964 | op_index[i] = -1; | |
9965 | } | |
252b5132 RH |
9966 | |
9967 | the_info = info; | |
9968 | start_pc = pc; | |
e396998b AM |
9969 | start_codep = priv.the_buffer; |
9970 | codep = priv.the_buffer; | |
252b5132 | 9971 | |
8df14d78 | 9972 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 9973 | { |
7d421014 ILT |
9974 | const char *name; |
9975 | ||
5076851f | 9976 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
9977 | means we have an incomplete instruction of some sort. Just |
9978 | print the first byte as a prefix or a .byte pseudo-op. */ | |
9979 | if (codep > priv.the_buffer) | |
5076851f | 9980 | { |
e396998b | 9981 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
9982 | if (name != NULL) |
9983 | (*info->fprintf_func) (info->stream, "%s", name); | |
9984 | else | |
5076851f | 9985 | { |
7d421014 ILT |
9986 | /* Just print the first byte as a .byte instruction. */ |
9987 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 9988 | (unsigned int) priv.the_buffer[0]); |
5076851f | 9989 | } |
5076851f | 9990 | |
7d421014 | 9991 | return 1; |
5076851f ILT |
9992 | } |
9993 | ||
9994 | return -1; | |
9995 | } | |
9996 | ||
52b15da3 | 9997 | obufp = obuf; |
f16cd0d5 L |
9998 | sizeflag = priv.orig_sizeflag; |
9999 | ||
10000 | if (!ckprefix () || rex_used) | |
10001 | { | |
10002 | /* Too many prefixes or unused REX prefixes. */ | |
10003 | for (i = 0; | |
f6dd4781 | 10004 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 10005 | i++) |
de882298 | 10006 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 10007 | i == 0 ? "" : " ", |
f16cd0d5 | 10008 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 10009 | return i; |
f16cd0d5 | 10010 | } |
252b5132 RH |
10011 | |
10012 | insn_codep = codep; | |
10013 | ||
10014 | FETCH_DATA (info, codep + 1); | |
10015 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
10016 | ||
3e7d61b2 | 10017 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 10018 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 10019 | { |
86a80a50 | 10020 | /* Handle prefixes before fwait. */ |
d9949a36 | 10021 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
10022 | i++) |
10023 | (*info->fprintf_func) (info->stream, "%s ", | |
10024 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 10025 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 10026 | return i + 1; |
252b5132 RH |
10027 | } |
10028 | ||
252b5132 RH |
10029 | if (*codep == 0x0f) |
10030 | { | |
eec0f4ca | 10031 | unsigned char threebyte; |
5f40e14d JS |
10032 | |
10033 | codep++; | |
10034 | FETCH_DATA (info, codep + 1); | |
10035 | threebyte = *codep; | |
eec0f4ca | 10036 | dp = &dis386_twobyte[threebyte]; |
0e9f3bf1 | 10037 | need_modrm = twobyte_has_modrm[threebyte]; |
eec0f4ca | 10038 | codep++; |
252b5132 RH |
10039 | } |
10040 | else | |
10041 | { | |
6439fc28 | 10042 | dp = &dis386[*codep]; |
252b5132 | 10043 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 10044 | codep++; |
252b5132 | 10045 | } |
246c51aa | 10046 | |
df18fdba L |
10047 | /* Save sizeflag for printing the extra prefixes later before updating |
10048 | it for mnemonic and operand processing. The prefix names depend | |
10049 | only on the address mode. */ | |
10050 | orig_sizeflag = sizeflag; | |
c608c12e | 10051 | if (prefixes & PREFIX_ADDR) |
df18fdba | 10052 | sizeflag ^= AFLAG; |
b844680a | 10053 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 10054 | sizeflag ^= DFLAG; |
3ffd33cf | 10055 | |
285ca992 | 10056 | end_codep = codep; |
8bb15339 | 10057 | if (need_modrm) |
252b5132 RH |
10058 | { |
10059 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
10060 | modrm.mod = (*codep >> 6) & 3; |
10061 | modrm.reg = (*codep >> 3) & 7; | |
10062 | modrm.rm = *codep & 7; | |
252b5132 | 10063 | } |
0e9f3bf1 L |
10064 | else |
10065 | memset (&modrm, 0, sizeof (modrm)); | |
252b5132 | 10066 | |
42d5f9c6 | 10067 | need_vex = 0; |
caf0678c | 10068 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 10069 | |
ce518a5f | 10070 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 10071 | { |
55cf16e1 | 10072 | get_sib (info, sizeflag); |
252b5132 RH |
10073 | dofloat (sizeflag); |
10074 | } | |
10075 | else | |
10076 | { | |
8bb15339 | 10077 | dp = get_valid_dis386 (dp, info); |
b844680a | 10078 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 10079 | { |
55cf16e1 | 10080 | get_sib (info, sizeflag); |
ce518a5f L |
10081 | for (i = 0; i < MAX_OPERANDS; ++i) |
10082 | { | |
246c51aa | 10083 | obufp = op_out[i]; |
ce518a5f L |
10084 | op_ad = MAX_OPERANDS - 1 - i; |
10085 | if (dp->op[i].rtn) | |
10086 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
10087 | /* For EVEX instruction after the last operand masking |
10088 | should be printed. */ | |
10089 | if (i == 0 && vex.evex) | |
10090 | { | |
10091 | /* Don't print {%k0}. */ | |
10092 | if (vex.mask_register_specifier) | |
10093 | { | |
10094 | oappend ("{"); | |
10095 | oappend (names_mask[vex.mask_register_specifier]); | |
10096 | oappend ("}"); | |
10097 | } | |
10098 | if (vex.zeroing) | |
10099 | oappend ("{z}"); | |
10100 | } | |
ce518a5f | 10101 | } |
6439fc28 | 10102 | } |
252b5132 RH |
10103 | } |
10104 | ||
1d67fe3b TT |
10105 | /* Clear instruction information. */ |
10106 | if (the_info) | |
10107 | { | |
10108 | the_info->insn_info_valid = 0; | |
10109 | the_info->branch_delay_insns = 0; | |
10110 | the_info->data_size = 0; | |
10111 | the_info->insn_type = dis_noninsn; | |
10112 | the_info->target = 0; | |
10113 | the_info->target2 = 0; | |
10114 | } | |
10115 | ||
10116 | /* Reset jump operation indicator. */ | |
10117 | op_is_jump = FALSE; | |
10118 | ||
10119 | { | |
10120 | int jump_detection = 0; | |
10121 | ||
10122 | /* Extract flags. */ | |
10123 | for (i = 0; i < MAX_OPERANDS; ++i) | |
10124 | { | |
10125 | if ((dp->op[i].rtn == OP_J) | |
10126 | || (dp->op[i].rtn == OP_indirE)) | |
10127 | jump_detection |= 1; | |
10128 | else if ((dp->op[i].rtn == BND_Fixup) | |
10129 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
10130 | jump_detection |= 2; | |
10131 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
10132 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
10133 | jump_detection |= 4; | |
10134 | } | |
10135 | ||
10136 | /* Determine if this is a jump or branch. */ | |
10137 | if ((jump_detection & 0x3) == 0x3) | |
10138 | { | |
10139 | op_is_jump = TRUE; | |
10140 | if (jump_detection & 0x4) | |
10141 | the_info->insn_type = dis_condbranch; | |
10142 | else | |
10143 | the_info->insn_type = | |
10144 | (dp->name && !strncmp(dp->name, "call", 4)) | |
10145 | ? dis_jsr : dis_branch; | |
10146 | } | |
10147 | } | |
10148 | ||
63c6fc6c L |
10149 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
10150 | are all 0s in inverted form. */ | |
10151 | if (need_vex && vex.register_specifier != 0) | |
10152 | { | |
10153 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10154 | return end_codep - priv.the_buffer; | |
10155 | } | |
10156 | ||
7531c613 JB |
10157 | switch (dp->prefix_requirement) |
10158 | { | |
10159 | case PREFIX_DATA: | |
10160 | /* If only the data prefix is marked as mandatory, its absence renders | |
10161 | the encoding invalid. Most other PREFIX_OPCODE rules still apply. */ | |
10162 | if (need_vex ? !vex.prefix : !(prefixes & PREFIX_DATA)) | |
10163 | { | |
10164 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10165 | return end_codep - priv.the_buffer; | |
10166 | } | |
10167 | used_prefixes |= PREFIX_DATA; | |
10168 | /* Fall through. */ | |
10169 | case PREFIX_OPCODE: | |
10170 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is | |
10171 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
10172 | used by putop and MMX/SSE operand and may be overridden by the | |
10173 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
10174 | separately. */ | |
10175 | if (((need_vex | |
10176 | ? vex.prefix == REPE_PREFIX_OPCODE | |
10177 | || vex.prefix == REPNE_PREFIX_OPCODE | |
10178 | : (prefixes | |
10179 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
10180 | && (used_prefixes | |
10181 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
10182 | || (((need_vex | |
10183 | ? vex.prefix == DATA_PREFIX_OPCODE | |
10184 | : ((prefixes | |
10185 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
10186 | == PREFIX_DATA)) | |
10187 | && (used_prefixes & PREFIX_DATA) == 0)) | |
10188 | || (vex.evex && dp->prefix_requirement != PREFIX_DATA | |
10189 | && !vex.w != !(used_prefixes & PREFIX_DATA))) | |
10190 | { | |
10191 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10192 | return end_codep - priv.the_buffer; | |
10193 | } | |
10194 | break; | |
10195 | } | |
10196 | ||
d869730d | 10197 | /* Check if the REX prefix is used. */ |
73239888 | 10198 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
10199 | all_prefixes[last_rex_prefix] = 0; |
10200 | ||
5e6718e4 | 10201 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
10202 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
10203 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 10204 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
10205 | all_prefixes[last_seg_prefix] = 0; |
10206 | ||
5e6718e4 | 10207 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
10208 | if ((prefixes & PREFIX_ADDR) != 0 |
10209 | && (used_prefixes & PREFIX_ADDR) != 0) | |
10210 | all_prefixes[last_addr_prefix] = 0; | |
10211 | ||
df18fdba L |
10212 | /* Check if the DATA prefix is used. */ |
10213 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
10214 | && (used_prefixes & PREFIX_DATA) != 0 |
10215 | && !need_vex) | |
df18fdba | 10216 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 10217 | |
df18fdba | 10218 | /* Print the extra prefixes. */ |
f16cd0d5 | 10219 | prefix_length = 0; |
f310f33d | 10220 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
10221 | if (all_prefixes[i]) |
10222 | { | |
10223 | const char *name; | |
df18fdba | 10224 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
10225 | if (name == NULL) |
10226 | abort (); | |
10227 | prefix_length += strlen (name) + 1; | |
10228 | (*info->fprintf_func) (info->stream, "%s ", name); | |
10229 | } | |
b844680a | 10230 | |
f16cd0d5 L |
10231 | /* Check maximum code length. */ |
10232 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
10233 | { | |
10234 | (*info->fprintf_func) (info->stream, "(bad)"); | |
10235 | return MAX_CODE_LENGTH; | |
10236 | } | |
b844680a | 10237 | |
ea397f5b | 10238 | obufp = mnemonicendp; |
f16cd0d5 | 10239 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
10240 | oappend (" "); |
10241 | oappend (" "); | |
10242 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
10243 | ||
10244 | /* The enter and bound instructions are printed with operands in the same | |
10245 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 10246 | if (intel_syntax || two_source_ops) |
252b5132 | 10247 | { |
185b1163 L |
10248 | bfd_vma riprel; |
10249 | ||
ce518a5f | 10250 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 10251 | op_txt[i] = op_out[i]; |
246c51aa | 10252 | |
3a8547d2 JB |
10253 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
10254 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
10255 | { | |
10256 | op_txt[2] = op_out[3]; | |
10257 | op_txt[3] = op_out[2]; | |
10258 | } | |
10259 | ||
ce518a5f L |
10260 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
10261 | { | |
6c067bbb RM |
10262 | op_ad = op_index[i]; |
10263 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
10264 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
10265 | riprel = op_riprel[i]; |
10266 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
10267 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 10268 | } |
252b5132 RH |
10269 | } |
10270 | else | |
10271 | { | |
ce518a5f | 10272 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 10273 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
10274 | } |
10275 | ||
ce518a5f L |
10276 | needcomma = 0; |
10277 | for (i = 0; i < MAX_OPERANDS; ++i) | |
10278 | if (*op_txt[i]) | |
10279 | { | |
10280 | if (needcomma) | |
10281 | (*info->fprintf_func) (info->stream, ","); | |
10282 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
10283 | { |
10284 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
10285 | ||
10286 | if (the_info && op_is_jump) | |
10287 | { | |
10288 | the_info->insn_info_valid = 1; | |
10289 | the_info->branch_delay_insns = 0; | |
10290 | the_info->data_size = 0; | |
10291 | the_info->target = target; | |
10292 | the_info->target2 = 0; | |
10293 | } | |
10294 | (*info->print_address_func) (target, info); | |
10295 | } | |
ce518a5f L |
10296 | else |
10297 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
10298 | needcomma = 1; | |
10299 | } | |
050dfa73 | 10300 | |
ce518a5f | 10301 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
10302 | if (op_index[i] != -1 && op_riprel[i]) |
10303 | { | |
10304 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 10305 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 10306 | + op_address[op_index[i]]), info); |
185b1163 | 10307 | break; |
52b15da3 | 10308 | } |
e396998b | 10309 | return codep - priv.the_buffer; |
252b5132 RH |
10310 | } |
10311 | ||
6439fc28 | 10312 | static const char *float_mem[] = { |
252b5132 | 10313 | /* d8 */ |
7c52e0e8 L |
10314 | "fadd{s|}", |
10315 | "fmul{s|}", | |
10316 | "fcom{s|}", | |
10317 | "fcomp{s|}", | |
10318 | "fsub{s|}", | |
10319 | "fsubr{s|}", | |
10320 | "fdiv{s|}", | |
10321 | "fdivr{s|}", | |
db6eb5be | 10322 | /* d9 */ |
7c52e0e8 | 10323 | "fld{s|}", |
252b5132 | 10324 | "(bad)", |
7c52e0e8 L |
10325 | "fst{s|}", |
10326 | "fstp{s|}", | |
d1c36125 | 10327 | "fldenv{C|C}", |
252b5132 | 10328 | "fldcw", |
d1c36125 | 10329 | "fNstenv{C|C}", |
252b5132 RH |
10330 | "fNstcw", |
10331 | /* da */ | |
7c52e0e8 L |
10332 | "fiadd{l|}", |
10333 | "fimul{l|}", | |
10334 | "ficom{l|}", | |
10335 | "ficomp{l|}", | |
10336 | "fisub{l|}", | |
10337 | "fisubr{l|}", | |
10338 | "fidiv{l|}", | |
10339 | "fidivr{l|}", | |
252b5132 | 10340 | /* db */ |
7c52e0e8 L |
10341 | "fild{l|}", |
10342 | "fisttp{l|}", | |
10343 | "fist{l|}", | |
10344 | "fistp{l|}", | |
252b5132 | 10345 | "(bad)", |
464dc4af | 10346 | "fld{t|}", |
252b5132 | 10347 | "(bad)", |
464dc4af | 10348 | "fstp{t|}", |
252b5132 | 10349 | /* dc */ |
7c52e0e8 L |
10350 | "fadd{l|}", |
10351 | "fmul{l|}", | |
10352 | "fcom{l|}", | |
10353 | "fcomp{l|}", | |
10354 | "fsub{l|}", | |
10355 | "fsubr{l|}", | |
10356 | "fdiv{l|}", | |
10357 | "fdivr{l|}", | |
252b5132 | 10358 | /* dd */ |
7c52e0e8 L |
10359 | "fld{l|}", |
10360 | "fisttp{ll|}", | |
10361 | "fst{l||}", | |
10362 | "fstp{l|}", | |
d1c36125 | 10363 | "frstor{C|C}", |
252b5132 | 10364 | "(bad)", |
d1c36125 | 10365 | "fNsave{C|C}", |
252b5132 RH |
10366 | "fNstsw", |
10367 | /* de */ | |
ac465521 JB |
10368 | "fiadd{s|}", |
10369 | "fimul{s|}", | |
10370 | "ficom{s|}", | |
10371 | "ficomp{s|}", | |
10372 | "fisub{s|}", | |
10373 | "fisubr{s|}", | |
10374 | "fidiv{s|}", | |
10375 | "fidivr{s|}", | |
252b5132 | 10376 | /* df */ |
ac465521 JB |
10377 | "fild{s|}", |
10378 | "fisttp{s|}", | |
10379 | "fist{s|}", | |
10380 | "fistp{s|}", | |
252b5132 | 10381 | "fbld", |
7c52e0e8 | 10382 | "fild{ll|}", |
252b5132 | 10383 | "fbstp", |
7c52e0e8 | 10384 | "fistp{ll|}", |
1d9f512f AM |
10385 | }; |
10386 | ||
10387 | static const unsigned char float_mem_mode[] = { | |
10388 | /* d8 */ | |
10389 | d_mode, | |
10390 | d_mode, | |
10391 | d_mode, | |
10392 | d_mode, | |
10393 | d_mode, | |
10394 | d_mode, | |
10395 | d_mode, | |
10396 | d_mode, | |
10397 | /* d9 */ | |
10398 | d_mode, | |
10399 | 0, | |
10400 | d_mode, | |
10401 | d_mode, | |
10402 | 0, | |
10403 | w_mode, | |
10404 | 0, | |
10405 | w_mode, | |
10406 | /* da */ | |
10407 | d_mode, | |
10408 | d_mode, | |
10409 | d_mode, | |
10410 | d_mode, | |
10411 | d_mode, | |
10412 | d_mode, | |
10413 | d_mode, | |
10414 | d_mode, | |
10415 | /* db */ | |
10416 | d_mode, | |
10417 | d_mode, | |
10418 | d_mode, | |
10419 | d_mode, | |
10420 | 0, | |
9306ca4a | 10421 | t_mode, |
1d9f512f | 10422 | 0, |
9306ca4a | 10423 | t_mode, |
1d9f512f AM |
10424 | /* dc */ |
10425 | q_mode, | |
10426 | q_mode, | |
10427 | q_mode, | |
10428 | q_mode, | |
10429 | q_mode, | |
10430 | q_mode, | |
10431 | q_mode, | |
10432 | q_mode, | |
10433 | /* dd */ | |
10434 | q_mode, | |
10435 | q_mode, | |
10436 | q_mode, | |
10437 | q_mode, | |
10438 | 0, | |
10439 | 0, | |
10440 | 0, | |
10441 | w_mode, | |
10442 | /* de */ | |
10443 | w_mode, | |
10444 | w_mode, | |
10445 | w_mode, | |
10446 | w_mode, | |
10447 | w_mode, | |
10448 | w_mode, | |
10449 | w_mode, | |
10450 | w_mode, | |
10451 | /* df */ | |
10452 | w_mode, | |
10453 | w_mode, | |
10454 | w_mode, | |
10455 | w_mode, | |
9306ca4a | 10456 | t_mode, |
1d9f512f | 10457 | q_mode, |
9306ca4a | 10458 | t_mode, |
1d9f512f | 10459 | q_mode |
252b5132 RH |
10460 | }; |
10461 | ||
ce518a5f L |
10462 | #define ST { OP_ST, 0 } |
10463 | #define STi { OP_STi, 0 } | |
252b5132 | 10464 | |
48c97fa1 L |
10465 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
10466 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
10467 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
10468 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
10469 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
10470 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
10471 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
10472 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
10473 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 10474 | |
2da11e11 | 10475 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
10476 | /* d8 */ |
10477 | { | |
bf890a93 IT |
10478 | { "fadd", { ST, STi }, 0 }, |
10479 | { "fmul", { ST, STi }, 0 }, | |
10480 | { "fcom", { STi }, 0 }, | |
10481 | { "fcomp", { STi }, 0 }, | |
10482 | { "fsub", { ST, STi }, 0 }, | |
10483 | { "fsubr", { ST, STi }, 0 }, | |
10484 | { "fdiv", { ST, STi }, 0 }, | |
10485 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
10486 | }, |
10487 | /* d9 */ | |
10488 | { | |
bf890a93 IT |
10489 | { "fld", { STi }, 0 }, |
10490 | { "fxch", { STi }, 0 }, | |
252b5132 | 10491 | { FGRPd9_2 }, |
592d1631 | 10492 | { Bad_Opcode }, |
252b5132 RH |
10493 | { FGRPd9_4 }, |
10494 | { FGRPd9_5 }, | |
10495 | { FGRPd9_6 }, | |
10496 | { FGRPd9_7 }, | |
10497 | }, | |
10498 | /* da */ | |
10499 | { | |
bf890a93 IT |
10500 | { "fcmovb", { ST, STi }, 0 }, |
10501 | { "fcmove", { ST, STi }, 0 }, | |
10502 | { "fcmovbe",{ ST, STi }, 0 }, | |
10503 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 10504 | { Bad_Opcode }, |
252b5132 | 10505 | { FGRPda_5 }, |
592d1631 L |
10506 | { Bad_Opcode }, |
10507 | { Bad_Opcode }, | |
252b5132 RH |
10508 | }, |
10509 | /* db */ | |
10510 | { | |
bf890a93 IT |
10511 | { "fcmovnb",{ ST, STi }, 0 }, |
10512 | { "fcmovne",{ ST, STi }, 0 }, | |
10513 | { "fcmovnbe",{ ST, STi }, 0 }, | |
10514 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 10515 | { FGRPdb_4 }, |
bf890a93 IT |
10516 | { "fucomi", { ST, STi }, 0 }, |
10517 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 10518 | { Bad_Opcode }, |
252b5132 RH |
10519 | }, |
10520 | /* dc */ | |
10521 | { | |
bf890a93 IT |
10522 | { "fadd", { STi, ST }, 0 }, |
10523 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
10524 | { Bad_Opcode }, |
10525 | { Bad_Opcode }, | |
d53e6b98 JB |
10526 | { "fsub{!M|r}", { STi, ST }, 0 }, |
10527 | { "fsub{M|}", { STi, ST }, 0 }, | |
10528 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
10529 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
10530 | }, |
10531 | /* dd */ | |
10532 | { | |
bf890a93 | 10533 | { "ffree", { STi }, 0 }, |
592d1631 | 10534 | { Bad_Opcode }, |
bf890a93 IT |
10535 | { "fst", { STi }, 0 }, |
10536 | { "fstp", { STi }, 0 }, | |
10537 | { "fucom", { STi }, 0 }, | |
10538 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
10539 | { Bad_Opcode }, |
10540 | { Bad_Opcode }, | |
252b5132 RH |
10541 | }, |
10542 | /* de */ | |
10543 | { | |
bf890a93 IT |
10544 | { "faddp", { STi, ST }, 0 }, |
10545 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 10546 | { Bad_Opcode }, |
252b5132 | 10547 | { FGRPde_3 }, |
d53e6b98 JB |
10548 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
10549 | { "fsub{M|}p", { STi, ST }, 0 }, | |
10550 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
10551 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
10552 | }, |
10553 | /* df */ | |
10554 | { | |
bf890a93 | 10555 | { "ffreep", { STi }, 0 }, |
592d1631 L |
10556 | { Bad_Opcode }, |
10557 | { Bad_Opcode }, | |
10558 | { Bad_Opcode }, | |
252b5132 | 10559 | { FGRPdf_4 }, |
bf890a93 IT |
10560 | { "fucomip", { ST, STi }, 0 }, |
10561 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 10562 | { Bad_Opcode }, |
252b5132 RH |
10563 | }, |
10564 | }; | |
10565 | ||
252b5132 | 10566 | static char *fgrps[][8] = { |
48c97fa1 L |
10567 | /* Bad opcode 0 */ |
10568 | { | |
10569 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10570 | }, | |
10571 | ||
10572 | /* d9_2 1 */ | |
252b5132 RH |
10573 | { |
10574 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10575 | }, | |
10576 | ||
48c97fa1 | 10577 | /* d9_4 2 */ |
252b5132 RH |
10578 | { |
10579 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
10580 | }, | |
10581 | ||
48c97fa1 | 10582 | /* d9_5 3 */ |
252b5132 RH |
10583 | { |
10584 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
10585 | }, | |
10586 | ||
48c97fa1 | 10587 | /* d9_6 4 */ |
252b5132 RH |
10588 | { |
10589 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
10590 | }, | |
10591 | ||
48c97fa1 | 10592 | /* d9_7 5 */ |
252b5132 RH |
10593 | { |
10594 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
10595 | }, | |
10596 | ||
48c97fa1 | 10597 | /* da_5 6 */ |
252b5132 RH |
10598 | { |
10599 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10600 | }, | |
10601 | ||
48c97fa1 | 10602 | /* db_4 7 */ |
252b5132 | 10603 | { |
309d3373 JB |
10604 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
10605 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
10606 | }, |
10607 | ||
48c97fa1 | 10608 | /* de_3 8 */ |
252b5132 RH |
10609 | { |
10610 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10611 | }, | |
10612 | ||
48c97fa1 | 10613 | /* df_4 9 */ |
252b5132 RH |
10614 | { |
10615 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
10616 | }, | |
10617 | }; | |
10618 | ||
b6169b20 L |
10619 | static void |
10620 | swap_operand (void) | |
10621 | { | |
10622 | mnemonicendp[0] = '.'; | |
10623 | mnemonicendp[1] = 's'; | |
10624 | mnemonicendp += 2; | |
10625 | } | |
10626 | ||
b844680a L |
10627 | static void |
10628 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
10629 | int sizeflag ATTRIBUTE_UNUSED) | |
10630 | { | |
10631 | /* Skip mod/rm byte. */ | |
10632 | MODRM_CHECK; | |
10633 | codep++; | |
10634 | } | |
10635 | ||
252b5132 | 10636 | static void |
26ca5450 | 10637 | dofloat (int sizeflag) |
252b5132 | 10638 | { |
2da11e11 | 10639 | const struct dis386 *dp; |
252b5132 RH |
10640 | unsigned char floatop; |
10641 | ||
10642 | floatop = codep[-1]; | |
10643 | ||
7967e09e | 10644 | if (modrm.mod != 3) |
252b5132 | 10645 | { |
7967e09e | 10646 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
10647 | |
10648 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 10649 | obufp = op_out[0]; |
6e50d963 | 10650 | op_ad = 2; |
1d9f512f | 10651 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
10652 | return; |
10653 | } | |
6608db57 | 10654 | /* Skip mod/rm byte. */ |
4bba6815 | 10655 | MODRM_CHECK; |
252b5132 RH |
10656 | codep++; |
10657 | ||
7967e09e | 10658 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
10659 | if (dp->name == NULL) |
10660 | { | |
7967e09e | 10661 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 10662 | |
6608db57 | 10663 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 10664 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 10665 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
10666 | } |
10667 | else | |
10668 | { | |
10669 | putop (dp->name, sizeflag); | |
10670 | ||
ce518a5f | 10671 | obufp = op_out[0]; |
6e50d963 | 10672 | op_ad = 2; |
ce518a5f L |
10673 | if (dp->op[0].rtn) |
10674 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 10675 | |
ce518a5f | 10676 | obufp = op_out[1]; |
6e50d963 | 10677 | op_ad = 1; |
ce518a5f L |
10678 | if (dp->op[1].rtn) |
10679 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
10680 | } |
10681 | } | |
10682 | ||
9ce09ba2 RM |
10683 | /* Like oappend (below), but S is a string starting with '%'. |
10684 | In Intel syntax, the '%' is elided. */ | |
10685 | static void | |
10686 | oappend_maybe_intel (const char *s) | |
10687 | { | |
10688 | oappend (s + intel_syntax); | |
10689 | } | |
10690 | ||
252b5132 | 10691 | static void |
26ca5450 | 10692 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10693 | { |
9ce09ba2 | 10694 | oappend_maybe_intel ("%st"); |
252b5132 RH |
10695 | } |
10696 | ||
252b5132 | 10697 | static void |
26ca5450 | 10698 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 10699 | { |
7967e09e | 10700 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 10701 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
10702 | } |
10703 | ||
6608db57 | 10704 | /* Capital letters in template are macros. */ |
6439fc28 | 10705 | static int |
d3ce72d0 | 10706 | putop (const char *in_template, int sizeflag) |
252b5132 | 10707 | { |
2da11e11 | 10708 | const char *p; |
9306ca4a | 10709 | int alt = 0; |
9d141669 | 10710 | int cond = 1; |
21a3faeb | 10711 | unsigned int l = 0, len = 0; |
98b528ac L |
10712 | char last[4]; |
10713 | ||
d3ce72d0 | 10714 | for (p = in_template; *p; p++) |
252b5132 | 10715 | { |
21a3faeb JB |
10716 | if (len > l) |
10717 | { | |
10718 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
10719 | abort (); | |
10720 | last[l++] = *p; | |
10721 | continue; | |
10722 | } | |
252b5132 RH |
10723 | switch (*p) |
10724 | { | |
10725 | default: | |
10726 | *obufp++ = *p; | |
10727 | break; | |
98b528ac L |
10728 | case '%': |
10729 | len++; | |
10730 | break; | |
9d141669 L |
10731 | case '!': |
10732 | cond = 0; | |
10733 | break; | |
6439fc28 | 10734 | case '{': |
6439fc28 | 10735 | if (intel_syntax) |
6439fc28 AM |
10736 | { |
10737 | while (*++p != '|') | |
7c52e0e8 L |
10738 | if (*p == '}' || *p == '\0') |
10739 | abort (); | |
d1c36125 | 10740 | alt = 1; |
6439fc28 | 10741 | } |
d1c36125 | 10742 | break; |
6439fc28 AM |
10743 | case '|': |
10744 | while (*++p != '}') | |
10745 | { | |
10746 | if (*p == '\0') | |
10747 | abort (); | |
10748 | } | |
10749 | break; | |
10750 | case '}': | |
d1c36125 | 10751 | alt = 0; |
6439fc28 | 10752 | break; |
252b5132 | 10753 | case 'A': |
db6eb5be AM |
10754 | if (intel_syntax) |
10755 | break; | |
0e9f3bf1 L |
10756 | if ((need_modrm && modrm.mod != 3) |
10757 | || (sizeflag & SUFFIX_ALWAYS)) | |
252b5132 RH |
10758 | *obufp++ = 'b'; |
10759 | break; | |
10760 | case 'B': | |
21a3faeb | 10761 | if (l == 0) |
4b06377f | 10762 | { |
dc1e8a47 | 10763 | case_B: |
4b06377f L |
10764 | if (intel_syntax) |
10765 | break; | |
10766 | if (sizeflag & SUFFIX_ALWAYS) | |
10767 | *obufp++ = 'b'; | |
10768 | } | |
21a3faeb | 10769 | else if (l == 1 && last[0] == 'L') |
4b06377f | 10770 | { |
4b06377f L |
10771 | if (address_mode == mode_64bit |
10772 | && !(prefixes & PREFIX_ADDR)) | |
10773 | { | |
10774 | *obufp++ = 'a'; | |
10775 | *obufp++ = 'b'; | |
10776 | *obufp++ = 's'; | |
10777 | } | |
10778 | ||
10779 | goto case_B; | |
10780 | } | |
21a3faeb JB |
10781 | else |
10782 | abort (); | |
252b5132 | 10783 | break; |
9306ca4a JB |
10784 | case 'C': |
10785 | if (intel_syntax && !alt) | |
10786 | break; | |
10787 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
10788 | { | |
10789 | if (sizeflag & DFLAG) | |
10790 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10791 | else | |
10792 | *obufp++ = intel_syntax ? 'w' : 's'; | |
10793 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10794 | } | |
10795 | break; | |
ed7841b3 JB |
10796 | case 'D': |
10797 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
10798 | break; | |
161a04f6 | 10799 | USED_REX (REX_W); |
7967e09e | 10800 | if (modrm.mod == 3) |
ed7841b3 | 10801 | { |
161a04f6 | 10802 | if (rex & REX_W) |
ed7841b3 | 10803 | *obufp++ = 'q'; |
ed7841b3 | 10804 | else |
f16cd0d5 L |
10805 | { |
10806 | if (sizeflag & DFLAG) | |
10807 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10808 | else | |
10809 | *obufp++ = 'w'; | |
10810 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10811 | } | |
ed7841b3 JB |
10812 | } |
10813 | else | |
10814 | *obufp++ = 'w'; | |
10815 | break; | |
252b5132 | 10816 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 10817 | if (address_mode == mode_64bit) |
c1a64871 JH |
10818 | { |
10819 | if (sizeflag & AFLAG) | |
10820 | *obufp++ = 'r'; | |
10821 | else | |
10822 | *obufp++ = 'e'; | |
10823 | } | |
10824 | else | |
10825 | if (sizeflag & AFLAG) | |
10826 | *obufp++ = 'e'; | |
3ffd33cf AM |
10827 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10828 | break; | |
10829 | case 'F': | |
db6eb5be AM |
10830 | if (intel_syntax) |
10831 | break; | |
e396998b | 10832 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
10833 | { |
10834 | if (sizeflag & AFLAG) | |
cb712a9e | 10835 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 10836 | else |
cb712a9e | 10837 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
10838 | used_prefixes |= (prefixes & PREFIX_ADDR); |
10839 | } | |
252b5132 | 10840 | break; |
52fd6d94 JB |
10841 | case 'G': |
10842 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
10843 | break; | |
161a04f6 | 10844 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
10845 | *obufp++ = 'l'; |
10846 | else | |
10847 | *obufp++ = 'w'; | |
161a04f6 | 10848 | if (!(rex & REX_W)) |
52fd6d94 JB |
10849 | used_prefixes |= (prefixes & PREFIX_DATA); |
10850 | break; | |
5dd0794d | 10851 | case 'H': |
db6eb5be AM |
10852 | if (intel_syntax) |
10853 | break; | |
5dd0794d AM |
10854 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
10855 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
10856 | { | |
10857 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
10858 | *obufp++ = ','; | |
10859 | *obufp++ = 'p'; | |
10860 | if (prefixes & PREFIX_DS) | |
10861 | *obufp++ = 't'; | |
10862 | else | |
10863 | *obufp++ = 'n'; | |
10864 | } | |
10865 | break; | |
42903f7f L |
10866 | case 'K': |
10867 | USED_REX (REX_W); | |
10868 | if (rex & REX_W) | |
10869 | *obufp++ = 'q'; | |
10870 | else | |
10871 | *obufp++ = 'd'; | |
10872 | break; | |
252b5132 | 10873 | case 'L': |
78467458 | 10874 | abort (); |
9d141669 L |
10875 | case 'M': |
10876 | if (intel_mnemonic != cond) | |
10877 | *obufp++ = 'r'; | |
10878 | break; | |
252b5132 RH |
10879 | case 'N': |
10880 | if ((prefixes & PREFIX_FWAIT) == 0) | |
10881 | *obufp++ = 'n'; | |
7d421014 ILT |
10882 | else |
10883 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 10884 | break; |
52b15da3 | 10885 | case 'O': |
161a04f6 L |
10886 | USED_REX (REX_W); |
10887 | if (rex & REX_W) | |
6439fc28 | 10888 | *obufp++ = 'o'; |
a35ca55a JB |
10889 | else if (intel_syntax && (sizeflag & DFLAG)) |
10890 | *obufp++ = 'q'; | |
52b15da3 JH |
10891 | else |
10892 | *obufp++ = 'd'; | |
161a04f6 | 10893 | if (!(rex & REX_W)) |
a35ca55a | 10894 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 10895 | break; |
36938cab JB |
10896 | case '@': |
10897 | if (address_mode == mode_64bit | |
10898 | && (isa64 == intel64 || (rex & REX_W) | |
10899 | || !(prefixes & PREFIX_DATA))) | |
6439fc28 | 10900 | { |
36938cab JB |
10901 | if (sizeflag & SUFFIX_ALWAYS) |
10902 | *obufp++ = 'q'; | |
6439fc28 AM |
10903 | break; |
10904 | } | |
6608db57 | 10905 | /* Fall through. */ |
252b5132 | 10906 | case 'P': |
21a3faeb | 10907 | if (l == 0) |
d9e3625e | 10908 | { |
0e9f3bf1 | 10909 | if ((modrm.mod == 3 || !cond) |
c3f5525f | 10910 | && !(sizeflag & SUFFIX_ALWAYS)) |
36938cab JB |
10911 | break; |
10912 | /* Fall through. */ | |
10913 | case 'T': | |
10914 | if ((!(rex & REX_W) && (prefixes & PREFIX_DATA)) | |
10915 | || ((sizeflag & SUFFIX_ALWAYS) | |
10916 | && address_mode != mode_64bit)) | |
4b4c407a | 10917 | { |
36938cab JB |
10918 | *obufp++ = (sizeflag & DFLAG) ? |
10919 | intel_syntax ? 'd' : 'l' : 'w'; | |
10920 | used_prefixes |= (prefixes & PREFIX_DATA); | |
d9e3625e | 10921 | } |
36938cab JB |
10922 | else if (sizeflag & SUFFIX_ALWAYS) |
10923 | *obufp++ = 'q'; | |
d9e3625e | 10924 | } |
21a3faeb | 10925 | else if (l == 1 && last[0] == 'L') |
252b5132 | 10926 | { |
4b4c407a L |
10927 | if ((prefixes & PREFIX_DATA) |
10928 | || (rex & REX_W) | |
10929 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10930 | { |
4b4c407a L |
10931 | USED_REX (REX_W); |
10932 | if (rex & REX_W) | |
10933 | *obufp++ = 'q'; | |
10934 | else | |
10935 | { | |
10936 | if (sizeflag & DFLAG) | |
10937 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10938 | else | |
10939 | *obufp++ = 'w'; | |
10940 | used_prefixes |= (prefixes & PREFIX_DATA); | |
10941 | } | |
52b15da3 | 10942 | } |
252b5132 | 10943 | } |
21a3faeb JB |
10944 | else |
10945 | abort (); | |
252b5132 RH |
10946 | break; |
10947 | case 'Q': | |
21a3faeb | 10948 | if (l == 0) |
252b5132 | 10949 | { |
98b528ac L |
10950 | if (intel_syntax && !alt) |
10951 | break; | |
10952 | USED_REX (REX_W); | |
0e9f3bf1 L |
10953 | if ((need_modrm && modrm.mod != 3) |
10954 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 10955 | { |
98b528ac L |
10956 | if (rex & REX_W) |
10957 | *obufp++ = 'q'; | |
52b15da3 | 10958 | else |
98b528ac L |
10959 | { |
10960 | if (sizeflag & DFLAG) | |
10961 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
10962 | else | |
10963 | *obufp++ = 'w'; | |
f16cd0d5 | 10964 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 10965 | } |
52b15da3 | 10966 | } |
98b528ac | 10967 | } |
492a76aa JB |
10968 | else if (l == 1 && last[0] == 'D') |
10969 | *obufp++ = vex.w ? 'q' : 'd'; | |
21a3faeb | 10970 | else if (l == 1 && last[0] == 'L') |
98b528ac | 10971 | { |
b24d668c JB |
10972 | if (cond ? modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) |
10973 | : address_mode != mode_64bit) | |
98b528ac L |
10974 | break; |
10975 | if ((rex & REX_W)) | |
10976 | { | |
10977 | USED_REX (REX_W); | |
10978 | *obufp++ = 'q'; | |
10979 | } | |
5b316d90 | 10980 | else if((address_mode == mode_64bit && cond) |
589958d6 JB |
10981 | || (sizeflag & SUFFIX_ALWAYS)) |
10982 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 10983 | } |
21a3faeb JB |
10984 | else |
10985 | abort (); | |
252b5132 RH |
10986 | break; |
10987 | case 'R': | |
161a04f6 L |
10988 | USED_REX (REX_W); |
10989 | if (rex & REX_W) | |
a35ca55a JB |
10990 | *obufp++ = 'q'; |
10991 | else if (sizeflag & DFLAG) | |
c608c12e | 10992 | { |
a35ca55a | 10993 | if (intel_syntax) |
c608c12e | 10994 | *obufp++ = 'd'; |
c608c12e | 10995 | else |
a35ca55a | 10996 | *obufp++ = 'l'; |
c608c12e | 10997 | } |
252b5132 | 10998 | else |
a35ca55a JB |
10999 | *obufp++ = 'w'; |
11000 | if (intel_syntax && !p[1] | |
161a04f6 | 11001 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 11002 | *obufp++ = 'e'; |
161a04f6 | 11003 | if (!(rex & REX_W)) |
52b15da3 | 11004 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
11005 | break; |
11006 | case 'S': | |
21a3faeb | 11007 | if (l == 0) |
252b5132 | 11008 | { |
dc1e8a47 | 11009 | case_S: |
4b06377f L |
11010 | if (intel_syntax) |
11011 | break; | |
11012 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 11013 | { |
4b06377f L |
11014 | if (rex & REX_W) |
11015 | *obufp++ = 'q'; | |
52b15da3 | 11016 | else |
4b06377f L |
11017 | { |
11018 | if (sizeflag & DFLAG) | |
11019 | *obufp++ = 'l'; | |
11020 | else | |
11021 | *obufp++ = 'w'; | |
11022 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11023 | } | |
11024 | } | |
11025 | } | |
21a3faeb | 11026 | else if (l == 1 && last[0] == 'L') |
4b06377f | 11027 | { |
4b06377f L |
11028 | if (address_mode == mode_64bit |
11029 | && !(prefixes & PREFIX_ADDR)) | |
11030 | { | |
11031 | *obufp++ = 'a'; | |
11032 | *obufp++ = 'b'; | |
11033 | *obufp++ = 's'; | |
11034 | } | |
11035 | ||
11036 | goto case_S; | |
252b5132 | 11037 | } |
21a3faeb JB |
11038 | else |
11039 | abort (); | |
252b5132 | 11040 | break; |
f0e8d0ba JB |
11041 | case 'V': |
11042 | if (l == 0) | |
11043 | abort (); | |
58bf9b6a L |
11044 | else if (l == 1 |
11045 | && (last[0] == 'L' || last[0] == 'X')) | |
f0e8d0ba | 11046 | { |
58bf9b6a L |
11047 | if (last[0] == 'X') |
11048 | { | |
11049 | *obufp++ = '{'; | |
11050 | *obufp++ = 'v'; | |
11051 | *obufp++ = 'e'; | |
11052 | *obufp++ = 'x'; | |
11053 | *obufp++ = '3'; | |
11054 | *obufp++ = '}'; | |
11055 | } | |
11056 | else if (rex & REX_W) | |
f0e8d0ba JB |
11057 | { |
11058 | *obufp++ = 'a'; | |
11059 | *obufp++ = 'b'; | |
11060 | *obufp++ = 's'; | |
11061 | } | |
11062 | } | |
11063 | else | |
11064 | abort (); | |
11065 | goto case_S; | |
11066 | case 'W': | |
11067 | if (l == 0) | |
11068 | { | |
11069 | /* operand size flag for cwtl, cbtw */ | |
11070 | USED_REX (REX_W); | |
11071 | if (rex & REX_W) | |
11072 | { | |
11073 | if (intel_syntax) | |
11074 | *obufp++ = 'd'; | |
11075 | else | |
11076 | *obufp++ = 'l'; | |
11077 | } | |
11078 | else if (sizeflag & DFLAG) | |
11079 | *obufp++ = 'w'; | |
11080 | else | |
11081 | *obufp++ = 'b'; | |
11082 | if (!(rex & REX_W)) | |
11083 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11084 | } | |
11085 | else if (l == 1) | |
11086 | { | |
11087 | if (!need_vex) | |
11088 | abort (); | |
11089 | if (last[0] == 'X') | |
11090 | *obufp++ = vex.w ? 'd': 's'; | |
11091 | else if (last[0] == 'B') | |
11092 | *obufp++ = vex.w ? 'w': 'b'; | |
11093 | else | |
11094 | abort (); | |
11095 | } | |
11096 | else | |
11097 | abort (); | |
11098 | break; | |
041bd2e0 | 11099 | case 'X': |
21a3faeb JB |
11100 | if (l != 0) |
11101 | abort (); | |
bf926894 JB |
11102 | if (need_vex |
11103 | ? vex.prefix == DATA_PREFIX_OPCODE | |
11104 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 11105 | { |
bf926894 JB |
11106 | *obufp++ = 'd'; |
11107 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 11108 | } |
041bd2e0 | 11109 | else |
bf926894 | 11110 | *obufp++ = 's'; |
041bd2e0 | 11111 | break; |
76f227a5 | 11112 | case 'Y': |
21a3faeb | 11113 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 11114 | { |
c0f3af97 L |
11115 | if (!need_vex) |
11116 | abort (); | |
11117 | if (intel_syntax | |
04d824a4 | 11118 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
11119 | break; |
11120 | switch (vex.length) | |
11121 | { | |
11122 | case 128: | |
11123 | *obufp++ = 'x'; | |
11124 | break; | |
11125 | case 256: | |
11126 | *obufp++ = 'y'; | |
11127 | break; | |
04d824a4 JB |
11128 | case 512: |
11129 | if (!vex.evex) | |
c0f3af97 | 11130 | default: |
04d824a4 | 11131 | abort (); |
c0f3af97 | 11132 | } |
76f227a5 | 11133 | } |
21a3faeb JB |
11134 | else |
11135 | abort (); | |
76f227a5 | 11136 | break; |
78467458 JB |
11137 | case 'Z': |
11138 | if (l == 0) | |
11139 | { | |
11140 | /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */ | |
11141 | modrm.mod = 3; | |
11142 | if (!intel_syntax && (sizeflag & SUFFIX_ALWAYS)) | |
11143 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; | |
11144 | } | |
11145 | else if (l == 1 && last[0] == 'X') | |
11146 | { | |
11147 | if (!need_vex || !vex.evex) | |
11148 | abort (); | |
11149 | if (intel_syntax | |
11150 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
11151 | break; | |
11152 | switch (vex.length) | |
11153 | { | |
11154 | case 128: | |
11155 | *obufp++ = 'x'; | |
11156 | break; | |
11157 | case 256: | |
11158 | *obufp++ = 'y'; | |
11159 | break; | |
11160 | case 512: | |
11161 | *obufp++ = 'z'; | |
11162 | break; | |
11163 | default: | |
11164 | abort (); | |
11165 | } | |
11166 | } | |
11167 | else | |
11168 | abort (); | |
11169 | break; | |
a72d2af2 L |
11170 | case '^': |
11171 | if (intel_syntax) | |
11172 | break; | |
5990e377 JB |
11173 | if (isa64 == intel64 && (rex & REX_W)) |
11174 | { | |
11175 | USED_REX (REX_W); | |
11176 | *obufp++ = 'q'; | |
11177 | break; | |
11178 | } | |
a72d2af2 L |
11179 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
11180 | { | |
11181 | if (sizeflag & DFLAG) | |
11182 | *obufp++ = 'l'; | |
11183 | else | |
11184 | *obufp++ = 'w'; | |
11185 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11186 | } | |
11187 | break; | |
252b5132 | 11188 | } |
21a3faeb JB |
11189 | |
11190 | if (len == l) | |
11191 | len = l = 0; | |
252b5132 RH |
11192 | } |
11193 | *obufp = 0; | |
ea397f5b | 11194 | mnemonicendp = obufp; |
6439fc28 | 11195 | return 0; |
252b5132 RH |
11196 | } |
11197 | ||
11198 | static void | |
26ca5450 | 11199 | oappend (const char *s) |
252b5132 | 11200 | { |
ea397f5b | 11201 | obufp = stpcpy (obufp, s); |
252b5132 RH |
11202 | } |
11203 | ||
11204 | static void | |
26ca5450 | 11205 | append_seg (void) |
252b5132 | 11206 | { |
285ca992 L |
11207 | /* Only print the active segment register. */ |
11208 | if (!active_seg_prefix) | |
11209 | return; | |
11210 | ||
11211 | used_prefixes |= active_seg_prefix; | |
11212 | switch (active_seg_prefix) | |
7d421014 | 11213 | { |
285ca992 | 11214 | case PREFIX_CS: |
9ce09ba2 | 11215 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
11216 | break; |
11217 | case PREFIX_DS: | |
9ce09ba2 | 11218 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
11219 | break; |
11220 | case PREFIX_SS: | |
9ce09ba2 | 11221 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
11222 | break; |
11223 | case PREFIX_ES: | |
9ce09ba2 | 11224 | oappend_maybe_intel ("%es:"); |
285ca992 L |
11225 | break; |
11226 | case PREFIX_FS: | |
9ce09ba2 | 11227 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
11228 | break; |
11229 | case PREFIX_GS: | |
9ce09ba2 | 11230 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
11231 | break; |
11232 | default: | |
11233 | break; | |
7d421014 | 11234 | } |
252b5132 RH |
11235 | } |
11236 | ||
11237 | static void | |
26ca5450 | 11238 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
11239 | { |
11240 | if (!intel_syntax) | |
11241 | oappend ("*"); | |
11242 | OP_E (bytemode, sizeflag); | |
11243 | } | |
11244 | ||
52b15da3 | 11245 | static void |
26ca5450 | 11246 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 11247 | { |
cb712a9e | 11248 | if (address_mode == mode_64bit) |
52b15da3 JH |
11249 | { |
11250 | if (hex) | |
11251 | { | |
11252 | char tmp[30]; | |
11253 | int i; | |
11254 | buf[0] = '0'; | |
11255 | buf[1] = 'x'; | |
11256 | sprintf_vma (tmp, disp); | |
6608db57 | 11257 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
11258 | strcpy (buf + 2, tmp + i); |
11259 | } | |
11260 | else | |
11261 | { | |
11262 | bfd_signed_vma v = disp; | |
11263 | char tmp[30]; | |
11264 | int i; | |
11265 | if (v < 0) | |
11266 | { | |
11267 | *(buf++) = '-'; | |
11268 | v = -disp; | |
6608db57 | 11269 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
11270 | if (v < 0) |
11271 | { | |
11272 | strcpy (buf, "9223372036854775808"); | |
11273 | return; | |
11274 | } | |
11275 | } | |
11276 | if (!v) | |
11277 | { | |
11278 | strcpy (buf, "0"); | |
11279 | return; | |
11280 | } | |
11281 | ||
11282 | i = 0; | |
11283 | tmp[29] = 0; | |
11284 | while (v) | |
11285 | { | |
6608db57 | 11286 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
11287 | v /= 10; |
11288 | i++; | |
11289 | } | |
11290 | strcpy (buf, tmp + 29 - i); | |
11291 | } | |
11292 | } | |
11293 | else | |
11294 | { | |
11295 | if (hex) | |
11296 | sprintf (buf, "0x%x", (unsigned int) disp); | |
11297 | else | |
11298 | sprintf (buf, "%d", (int) disp); | |
11299 | } | |
11300 | } | |
11301 | ||
5d669648 L |
11302 | /* Put DISP in BUF as signed hex number. */ |
11303 | ||
11304 | static void | |
11305 | print_displacement (char *buf, bfd_vma disp) | |
11306 | { | |
11307 | bfd_signed_vma val = disp; | |
11308 | char tmp[30]; | |
11309 | int i, j = 0; | |
11310 | ||
11311 | if (val < 0) | |
11312 | { | |
11313 | buf[j++] = '-'; | |
11314 | val = -disp; | |
11315 | ||
11316 | /* Check for possible overflow. */ | |
11317 | if (val < 0) | |
11318 | { | |
11319 | switch (address_mode) | |
11320 | { | |
11321 | case mode_64bit: | |
11322 | strcpy (buf + j, "0x8000000000000000"); | |
11323 | break; | |
11324 | case mode_32bit: | |
11325 | strcpy (buf + j, "0x80000000"); | |
11326 | break; | |
11327 | case mode_16bit: | |
11328 | strcpy (buf + j, "0x8000"); | |
11329 | break; | |
11330 | } | |
11331 | return; | |
11332 | } | |
11333 | } | |
11334 | ||
11335 | buf[j++] = '0'; | |
11336 | buf[j++] = 'x'; | |
11337 | ||
0af1713e | 11338 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
11339 | for (i = 0; tmp[i] == '0'; i++) |
11340 | continue; | |
11341 | if (tmp[i] == '\0') | |
11342 | i--; | |
11343 | strcpy (buf + j, tmp + i); | |
11344 | } | |
11345 | ||
3f31e633 JB |
11346 | static void |
11347 | intel_operand_size (int bytemode, int sizeflag) | |
11348 | { | |
43234a1e L |
11349 | if (vex.evex |
11350 | && vex.b | |
11351 | && (bytemode == x_mode | |
11352 | || bytemode == evex_half_bcst_xmmq_mode)) | |
11353 | { | |
11354 | if (vex.w) | |
11355 | oappend ("QWORD PTR "); | |
11356 | else | |
11357 | oappend ("DWORD PTR "); | |
11358 | return; | |
11359 | } | |
3f31e633 JB |
11360 | switch (bytemode) |
11361 | { | |
11362 | case b_mode: | |
b6169b20 | 11363 | case b_swap_mode: |
42903f7f | 11364 | case dqb_mode: |
1ba585e8 | 11365 | case db_mode: |
3f31e633 JB |
11366 | oappend ("BYTE PTR "); |
11367 | break; | |
11368 | case w_mode: | |
1ba585e8 | 11369 | case dw_mode: |
3f31e633 JB |
11370 | case dqw_mode: |
11371 | oappend ("WORD PTR "); | |
11372 | break; | |
07f5af7d L |
11373 | case indir_v_mode: |
11374 | if (address_mode == mode_64bit && isa64 == intel64) | |
11375 | { | |
11376 | oappend ("QWORD PTR "); | |
11377 | break; | |
11378 | } | |
1a0670f3 | 11379 | /* Fall through. */ |
1a114b12 | 11380 | case stack_v_mode: |
7bb15c6f | 11381 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
11382 | { |
11383 | oappend ("QWORD PTR "); | |
3f31e633 JB |
11384 | break; |
11385 | } | |
1a0670f3 | 11386 | /* Fall through. */ |
3f31e633 | 11387 | case v_mode: |
b6169b20 | 11388 | case v_swap_mode: |
3f31e633 | 11389 | case dq_mode: |
161a04f6 L |
11390 | USED_REX (REX_W); |
11391 | if (rex & REX_W) | |
3f31e633 | 11392 | oappend ("QWORD PTR "); |
035e7389 JB |
11393 | else if (bytemode == dq_mode) |
11394 | oappend ("DWORD PTR "); | |
3f31e633 | 11395 | else |
f16cd0d5 | 11396 | { |
035e7389 | 11397 | if (sizeflag & DFLAG) |
f16cd0d5 L |
11398 | oappend ("DWORD PTR "); |
11399 | else | |
11400 | oappend ("WORD PTR "); | |
11401 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11402 | } | |
3f31e633 | 11403 | break; |
52fd6d94 | 11404 | case z_mode: |
161a04f6 | 11405 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
11406 | *obufp++ = 'D'; |
11407 | oappend ("WORD PTR "); | |
161a04f6 | 11408 | if (!(rex & REX_W)) |
52fd6d94 JB |
11409 | used_prefixes |= (prefixes & PREFIX_DATA); |
11410 | break; | |
34b772a6 JB |
11411 | case a_mode: |
11412 | if (sizeflag & DFLAG) | |
11413 | oappend ("QWORD PTR "); | |
11414 | else | |
11415 | oappend ("DWORD PTR "); | |
11416 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11417 | break; | |
bc31405e L |
11418 | case movsxd_mode: |
11419 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
11420 | oappend ("WORD PTR "); | |
11421 | else | |
11422 | oappend ("DWORD PTR "); | |
11423 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11424 | break; | |
3f31e633 | 11425 | case d_mode: |
fa99fab2 | 11426 | case d_swap_mode: |
42903f7f | 11427 | case dqd_mode: |
3f31e633 JB |
11428 | oappend ("DWORD PTR "); |
11429 | break; | |
11430 | case q_mode: | |
b6169b20 | 11431 | case q_swap_mode: |
3f31e633 JB |
11432 | oappend ("QWORD PTR "); |
11433 | break; | |
11434 | case m_mode: | |
cb712a9e | 11435 | if (address_mode == mode_64bit) |
3f31e633 JB |
11436 | oappend ("QWORD PTR "); |
11437 | else | |
11438 | oappend ("DWORD PTR "); | |
11439 | break; | |
11440 | case f_mode: | |
11441 | if (sizeflag & DFLAG) | |
11442 | oappend ("FWORD PTR "); | |
11443 | else | |
11444 | oappend ("DWORD PTR "); | |
11445 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11446 | break; | |
11447 | case t_mode: | |
11448 | oappend ("TBYTE PTR "); | |
11449 | break; | |
11450 | case x_mode: | |
b6169b20 | 11451 | case x_swap_mode: |
43234a1e L |
11452 | case evex_x_gscat_mode: |
11453 | case evex_x_nobcst_mode: | |
4726e9a4 | 11454 | case bw_unit_mode: |
c0f3af97 L |
11455 | if (need_vex) |
11456 | { | |
11457 | switch (vex.length) | |
11458 | { | |
11459 | case 128: | |
11460 | oappend ("XMMWORD PTR "); | |
11461 | break; | |
11462 | case 256: | |
11463 | oappend ("YMMWORD PTR "); | |
11464 | break; | |
43234a1e L |
11465 | case 512: |
11466 | oappend ("ZMMWORD PTR "); | |
11467 | break; | |
c0f3af97 L |
11468 | default: |
11469 | abort (); | |
11470 | } | |
11471 | } | |
11472 | else | |
11473 | oappend ("XMMWORD PTR "); | |
11474 | break; | |
11475 | case xmm_mode: | |
3f31e633 JB |
11476 | oappend ("XMMWORD PTR "); |
11477 | break; | |
43234a1e L |
11478 | case ymm_mode: |
11479 | oappend ("YMMWORD PTR "); | |
11480 | break; | |
c0f3af97 | 11481 | case xmmq_mode: |
43234a1e | 11482 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
11483 | if (!need_vex) |
11484 | abort (); | |
11485 | ||
11486 | switch (vex.length) | |
11487 | { | |
11488 | case 128: | |
11489 | oappend ("QWORD PTR "); | |
11490 | break; | |
11491 | case 256: | |
11492 | oappend ("XMMWORD PTR "); | |
11493 | break; | |
43234a1e L |
11494 | case 512: |
11495 | oappend ("YMMWORD PTR "); | |
11496 | break; | |
c0f3af97 L |
11497 | default: |
11498 | abort (); | |
11499 | } | |
11500 | break; | |
6c30d220 L |
11501 | case xmm_mb_mode: |
11502 | if (!need_vex) | |
11503 | abort (); | |
11504 | ||
11505 | switch (vex.length) | |
11506 | { | |
11507 | case 128: | |
11508 | case 256: | |
43234a1e | 11509 | case 512: |
6c30d220 L |
11510 | oappend ("BYTE PTR "); |
11511 | break; | |
11512 | default: | |
11513 | abort (); | |
11514 | } | |
11515 | break; | |
11516 | case xmm_mw_mode: | |
11517 | if (!need_vex) | |
11518 | abort (); | |
11519 | ||
11520 | switch (vex.length) | |
11521 | { | |
11522 | case 128: | |
11523 | case 256: | |
43234a1e | 11524 | case 512: |
6c30d220 L |
11525 | oappend ("WORD PTR "); |
11526 | break; | |
11527 | default: | |
11528 | abort (); | |
11529 | } | |
11530 | break; | |
11531 | case xmm_md_mode: | |
11532 | if (!need_vex) | |
11533 | abort (); | |
11534 | ||
11535 | switch (vex.length) | |
11536 | { | |
11537 | case 128: | |
11538 | case 256: | |
43234a1e | 11539 | case 512: |
6c30d220 L |
11540 | oappend ("DWORD PTR "); |
11541 | break; | |
11542 | default: | |
11543 | abort (); | |
11544 | } | |
11545 | break; | |
11546 | case xmm_mq_mode: | |
11547 | if (!need_vex) | |
11548 | abort (); | |
11549 | ||
11550 | switch (vex.length) | |
11551 | { | |
11552 | case 128: | |
11553 | case 256: | |
43234a1e | 11554 | case 512: |
6c30d220 L |
11555 | oappend ("QWORD PTR "); |
11556 | break; | |
11557 | default: | |
11558 | abort (); | |
11559 | } | |
11560 | break; | |
11561 | case xmmdw_mode: | |
11562 | if (!need_vex) | |
11563 | abort (); | |
11564 | ||
11565 | switch (vex.length) | |
11566 | { | |
11567 | case 128: | |
11568 | oappend ("WORD PTR "); | |
11569 | break; | |
11570 | case 256: | |
11571 | oappend ("DWORD PTR "); | |
11572 | break; | |
43234a1e L |
11573 | case 512: |
11574 | oappend ("QWORD PTR "); | |
11575 | break; | |
6c30d220 L |
11576 | default: |
11577 | abort (); | |
11578 | } | |
11579 | break; | |
11580 | case xmmqd_mode: | |
11581 | if (!need_vex) | |
11582 | abort (); | |
11583 | ||
11584 | switch (vex.length) | |
11585 | { | |
11586 | case 128: | |
11587 | oappend ("DWORD PTR "); | |
11588 | break; | |
11589 | case 256: | |
11590 | oappend ("QWORD PTR "); | |
11591 | break; | |
43234a1e L |
11592 | case 512: |
11593 | oappend ("XMMWORD PTR "); | |
11594 | break; | |
6c30d220 L |
11595 | default: |
11596 | abort (); | |
11597 | } | |
11598 | break; | |
c0f3af97 L |
11599 | case ymmq_mode: |
11600 | if (!need_vex) | |
11601 | abort (); | |
11602 | ||
11603 | switch (vex.length) | |
11604 | { | |
11605 | case 128: | |
11606 | oappend ("QWORD PTR "); | |
11607 | break; | |
11608 | case 256: | |
11609 | oappend ("YMMWORD PTR "); | |
11610 | break; | |
43234a1e L |
11611 | case 512: |
11612 | oappend ("ZMMWORD PTR "); | |
11613 | break; | |
c0f3af97 L |
11614 | default: |
11615 | abort (); | |
11616 | } | |
11617 | break; | |
6c30d220 L |
11618 | case ymmxmm_mode: |
11619 | if (!need_vex) | |
11620 | abort (); | |
11621 | ||
11622 | switch (vex.length) | |
11623 | { | |
11624 | case 128: | |
11625 | case 256: | |
11626 | oappend ("XMMWORD PTR "); | |
11627 | break; | |
11628 | default: | |
11629 | abort (); | |
11630 | } | |
11631 | break; | |
fb9c77c7 L |
11632 | case o_mode: |
11633 | oappend ("OWORD PTR "); | |
11634 | break; | |
1c480963 | 11635 | case vex_scalar_w_dq_mode: |
0bfee649 L |
11636 | if (!need_vex) |
11637 | abort (); | |
11638 | ||
11639 | if (vex.w) | |
11640 | oappend ("QWORD PTR "); | |
11641 | else | |
11642 | oappend ("DWORD PTR "); | |
11643 | break; | |
43234a1e L |
11644 | case vex_vsib_d_w_dq_mode: |
11645 | case vex_vsib_q_w_dq_mode: | |
11646 | if (!need_vex) | |
11647 | abort (); | |
11648 | ||
11649 | if (!vex.evex) | |
11650 | { | |
11651 | if (vex.w) | |
11652 | oappend ("QWORD PTR "); | |
11653 | else | |
11654 | oappend ("DWORD PTR "); | |
11655 | } | |
11656 | else | |
11657 | { | |
b28d1bda IT |
11658 | switch (vex.length) |
11659 | { | |
11660 | case 128: | |
11661 | oappend ("XMMWORD PTR "); | |
11662 | break; | |
11663 | case 256: | |
11664 | oappend ("YMMWORD PTR "); | |
11665 | break; | |
11666 | case 512: | |
11667 | oappend ("ZMMWORD PTR "); | |
11668 | break; | |
11669 | default: | |
11670 | abort (); | |
11671 | } | |
43234a1e L |
11672 | } |
11673 | break; | |
5fc35d96 IT |
11674 | case vex_vsib_q_w_d_mode: |
11675 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 11676 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
11677 | abort (); |
11678 | ||
b28d1bda IT |
11679 | switch (vex.length) |
11680 | { | |
11681 | case 128: | |
11682 | oappend ("QWORD PTR "); | |
11683 | break; | |
11684 | case 256: | |
11685 | oappend ("XMMWORD PTR "); | |
11686 | break; | |
11687 | case 512: | |
11688 | oappend ("YMMWORD PTR "); | |
11689 | break; | |
11690 | default: | |
11691 | abort (); | |
11692 | } | |
5fc35d96 IT |
11693 | |
11694 | break; | |
1ba585e8 IT |
11695 | case mask_bd_mode: |
11696 | if (!need_vex || vex.length != 128) | |
11697 | abort (); | |
11698 | if (vex.w) | |
11699 | oappend ("DWORD PTR "); | |
11700 | else | |
11701 | oappend ("BYTE PTR "); | |
11702 | break; | |
43234a1e L |
11703 | case mask_mode: |
11704 | if (!need_vex) | |
11705 | abort (); | |
1ba585e8 IT |
11706 | if (vex.w) |
11707 | oappend ("QWORD PTR "); | |
11708 | else | |
11709 | oappend ("WORD PTR "); | |
43234a1e | 11710 | break; |
6c75cc62 | 11711 | case v_bnd_mode: |
d276ec69 | 11712 | case v_bndmk_mode: |
3f31e633 JB |
11713 | default: |
11714 | break; | |
11715 | } | |
11716 | } | |
11717 | ||
252b5132 | 11718 | static void |
c0f3af97 | 11719 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 11720 | { |
c0f3af97 L |
11721 | int reg = modrm.rm; |
11722 | const char **names; | |
252b5132 | 11723 | |
c0f3af97 L |
11724 | USED_REX (REX_B); |
11725 | if ((rex & REX_B)) | |
11726 | reg += 8; | |
252b5132 | 11727 | |
b6169b20 | 11728 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 11729 | && (bytemode == b_swap_mode |
9f79e886 | 11730 | || bytemode == bnd_swap_mode |
60227d64 | 11731 | || bytemode == v_swap_mode)) |
b6169b20 L |
11732 | swap_operand (); |
11733 | ||
c0f3af97 | 11734 | switch (bytemode) |
252b5132 | 11735 | { |
c0f3af97 | 11736 | case b_mode: |
b6169b20 | 11737 | case b_swap_mode: |
e184e611 JB |
11738 | if (reg & 4) |
11739 | USED_REX (0); | |
c0f3af97 L |
11740 | if (rex) |
11741 | names = names8rex; | |
11742 | else | |
11743 | names = names8; | |
11744 | break; | |
11745 | case w_mode: | |
11746 | names = names16; | |
11747 | break; | |
11748 | case d_mode: | |
1ba585e8 IT |
11749 | case dw_mode: |
11750 | case db_mode: | |
c0f3af97 L |
11751 | names = names32; |
11752 | break; | |
11753 | case q_mode: | |
11754 | names = names64; | |
11755 | break; | |
11756 | case m_mode: | |
6c75cc62 | 11757 | case v_bnd_mode: |
c0f3af97 L |
11758 | names = address_mode == mode_64bit ? names64 : names32; |
11759 | break; | |
7e8b059b | 11760 | case bnd_mode: |
9f79e886 | 11761 | case bnd_swap_mode: |
0d96e4df L |
11762 | if (reg > 0x3) |
11763 | { | |
11764 | oappend ("(bad)"); | |
11765 | return; | |
11766 | } | |
7e8b059b L |
11767 | names = names_bnd; |
11768 | break; | |
07f5af7d L |
11769 | case indir_v_mode: |
11770 | if (address_mode == mode_64bit && isa64 == intel64) | |
11771 | { | |
11772 | names = names64; | |
11773 | break; | |
11774 | } | |
1a0670f3 | 11775 | /* Fall through. */ |
c0f3af97 | 11776 | case stack_v_mode: |
7bb15c6f | 11777 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 11778 | { |
c0f3af97 | 11779 | names = names64; |
252b5132 | 11780 | break; |
252b5132 | 11781 | } |
c0f3af97 | 11782 | bytemode = v_mode; |
1a0670f3 | 11783 | /* Fall through. */ |
c0f3af97 | 11784 | case v_mode: |
b6169b20 | 11785 | case v_swap_mode: |
c0f3af97 L |
11786 | case dq_mode: |
11787 | case dqb_mode: | |
11788 | case dqd_mode: | |
11789 | case dqw_mode: | |
11790 | USED_REX (REX_W); | |
11791 | if (rex & REX_W) | |
11792 | names = names64; | |
035e7389 JB |
11793 | else if (bytemode != v_mode && bytemode != v_swap_mode) |
11794 | names = names32; | |
c0f3af97 | 11795 | else |
f16cd0d5 | 11796 | { |
035e7389 | 11797 | if (sizeflag & DFLAG) |
f16cd0d5 L |
11798 | names = names32; |
11799 | else | |
11800 | names = names16; | |
11801 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11802 | } | |
c0f3af97 | 11803 | break; |
bc31405e L |
11804 | case movsxd_mode: |
11805 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
11806 | names = names16; | |
11807 | else | |
11808 | names = names32; | |
11809 | used_prefixes |= (prefixes & PREFIX_DATA); | |
11810 | break; | |
de89d0a3 IT |
11811 | case va_mode: |
11812 | names = (address_mode == mode_64bit | |
11813 | ? names64 : names32); | |
11814 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
11815 | names = (address_mode == mode_16bit |
11816 | ? names16 : names); | |
de89d0a3 IT |
11817 | else |
11818 | { | |
11819 | /* Remove "addr16/addr32". */ | |
11820 | all_prefixes[last_addr_prefix] = 0; | |
11821 | names = (address_mode != mode_32bit | |
11822 | ? names32 : names16); | |
11823 | used_prefixes |= PREFIX_ADDR; | |
11824 | } | |
11825 | break; | |
1ba585e8 | 11826 | case mask_bd_mode: |
43234a1e | 11827 | case mask_mode: |
9889cbb1 L |
11828 | if (reg > 0x7) |
11829 | { | |
11830 | oappend ("(bad)"); | |
11831 | return; | |
11832 | } | |
43234a1e L |
11833 | names = names_mask; |
11834 | break; | |
c0f3af97 L |
11835 | case 0: |
11836 | return; | |
11837 | default: | |
11838 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
11839 | return; |
11840 | } | |
c0f3af97 L |
11841 | oappend (names[reg]); |
11842 | } | |
11843 | ||
11844 | static void | |
c1e679ec | 11845 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
11846 | { |
11847 | bfd_vma disp = 0; | |
11848 | int add = (rex & REX_B) ? 8 : 0; | |
11849 | int riprel = 0; | |
43234a1e L |
11850 | int shift; |
11851 | ||
11852 | if (vex.evex) | |
11853 | { | |
11854 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
11855 | if (vex.b | |
11856 | && bytemode != x_mode | |
90a915bf | 11857 | && bytemode != xmmq_mode |
43234a1e L |
11858 | && bytemode != evex_half_bcst_xmmq_mode) |
11859 | { | |
11860 | BadOp (); | |
11861 | return; | |
11862 | } | |
11863 | switch (bytemode) | |
11864 | { | |
1ba585e8 IT |
11865 | case dqw_mode: |
11866 | case dw_mode: | |
059edf8b | 11867 | case xmm_mw_mode: |
1ba585e8 IT |
11868 | shift = 1; |
11869 | break; | |
11870 | case dqb_mode: | |
11871 | case db_mode: | |
059edf8b | 11872 | case xmm_mb_mode: |
1ba585e8 IT |
11873 | shift = 0; |
11874 | break; | |
b50c9f31 JB |
11875 | case dq_mode: |
11876 | if (address_mode != mode_64bit) | |
11877 | { | |
059edf8b JB |
11878 | case dqd_mode: |
11879 | case xmm_md_mode: | |
11880 | case d_mode: | |
11881 | case d_swap_mode: | |
b50c9f31 JB |
11882 | shift = 2; |
11883 | break; | |
11884 | } | |
11885 | /* fall through */ | |
4102be5c | 11886 | case vex_scalar_w_dq_mode: |
43234a1e | 11887 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 11888 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 11889 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 11890 | case vex_vsib_q_w_d_mode: |
43234a1e | 11891 | case evex_x_gscat_mode: |
43234a1e L |
11892 | shift = vex.w ? 3 : 2; |
11893 | break; | |
43234a1e L |
11894 | case x_mode: |
11895 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 11896 | case xmmq_mode: |
43234a1e L |
11897 | if (vex.b) |
11898 | { | |
11899 | shift = vex.w ? 3 : 2; | |
11900 | break; | |
11901 | } | |
1a0670f3 | 11902 | /* Fall through. */ |
43234a1e L |
11903 | case xmmqd_mode: |
11904 | case xmmdw_mode: | |
43234a1e L |
11905 | case ymmq_mode: |
11906 | case evex_x_nobcst_mode: | |
11907 | case x_swap_mode: | |
11908 | switch (vex.length) | |
11909 | { | |
11910 | case 128: | |
11911 | shift = 4; | |
11912 | break; | |
11913 | case 256: | |
11914 | shift = 5; | |
11915 | break; | |
11916 | case 512: | |
11917 | shift = 6; | |
11918 | break; | |
11919 | default: | |
11920 | abort (); | |
11921 | } | |
059edf8b JB |
11922 | /* Make necessary corrections to shift for modes that need it. */ |
11923 | if (bytemode == xmmq_mode | |
11924 | || bytemode == evex_half_bcst_xmmq_mode | |
11925 | || (bytemode == ymmq_mode && vex.length == 128)) | |
11926 | shift -= 1; | |
11927 | else if (bytemode == xmmqd_mode) | |
11928 | shift -= 2; | |
11929 | else if (bytemode == xmmdw_mode) | |
11930 | shift -= 3; | |
43234a1e L |
11931 | break; |
11932 | case ymm_mode: | |
11933 | shift = 5; | |
11934 | break; | |
11935 | case xmm_mode: | |
11936 | shift = 4; | |
11937 | break; | |
11938 | case xmm_mq_mode: | |
11939 | case q_mode: | |
43234a1e | 11940 | case q_swap_mode: |
43234a1e L |
11941 | shift = 3; |
11942 | break; | |
4726e9a4 JB |
11943 | case bw_unit_mode: |
11944 | shift = vex.w ? 1 : 0; | |
11945 | break; | |
43234a1e L |
11946 | default: |
11947 | abort (); | |
11948 | } | |
43234a1e L |
11949 | } |
11950 | else | |
11951 | shift = 0; | |
252b5132 | 11952 | |
c0f3af97 | 11953 | USED_REX (REX_B); |
3f31e633 JB |
11954 | if (intel_syntax) |
11955 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
11956 | append_seg (); |
11957 | ||
5d669648 | 11958 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 11959 | { |
5d669648 L |
11960 | /* 32/64 bit address mode */ |
11961 | int havedisp; | |
252b5132 RH |
11962 | int havesib; |
11963 | int havebase; | |
0f7da397 | 11964 | int haveindex; |
20afcfb7 | 11965 | int needindex; |
1bc60e56 | 11966 | int needaddr32; |
82c18208 | 11967 | int base, rbase; |
91d6fa6a | 11968 | int vindex = 0; |
252b5132 | 11969 | int scale = 0; |
7e8b059b L |
11970 | int addr32flag = !((sizeflag & AFLAG) |
11971 | || bytemode == v_bnd_mode | |
d276ec69 | 11972 | || bytemode == v_bndmk_mode |
9f79e886 JB |
11973 | || bytemode == bnd_mode |
11974 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
11975 | const char **indexes64 = names64; |
11976 | const char **indexes32 = names32; | |
252b5132 RH |
11977 | |
11978 | havesib = 0; | |
11979 | havebase = 1; | |
0f7da397 | 11980 | haveindex = 0; |
7967e09e | 11981 | base = modrm.rm; |
252b5132 RH |
11982 | |
11983 | if (base == 4) | |
11984 | { | |
11985 | havesib = 1; | |
dfc8cf43 | 11986 | vindex = sib.index; |
161a04f6 L |
11987 | USED_REX (REX_X); |
11988 | if (rex & REX_X) | |
91d6fa6a | 11989 | vindex += 8; |
6c30d220 L |
11990 | switch (bytemode) |
11991 | { | |
11992 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 11993 | case vex_vsib_d_w_d_mode: |
6c30d220 | 11994 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 11995 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
11996 | if (!need_vex) |
11997 | abort (); | |
43234a1e L |
11998 | if (vex.evex) |
11999 | { | |
12000 | if (!vex.v) | |
12001 | vindex += 16; | |
12002 | } | |
6c30d220 L |
12003 | |
12004 | haveindex = 1; | |
12005 | switch (vex.length) | |
12006 | { | |
12007 | case 128: | |
7bb15c6f | 12008 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
12009 | break; |
12010 | case 256: | |
5fc35d96 IT |
12011 | if (!vex.w |
12012 | || bytemode == vex_vsib_q_w_dq_mode | |
12013 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 12014 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 12015 | else |
7bb15c6f | 12016 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 12017 | break; |
43234a1e | 12018 | case 512: |
5fc35d96 IT |
12019 | if (!vex.w |
12020 | || bytemode == vex_vsib_q_w_dq_mode | |
12021 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
12022 | indexes64 = indexes32 = names_zmm; |
12023 | else | |
12024 | indexes64 = indexes32 = names_ymm; | |
12025 | break; | |
6c30d220 L |
12026 | default: |
12027 | abort (); | |
12028 | } | |
12029 | break; | |
12030 | default: | |
12031 | haveindex = vindex != 4; | |
12032 | break; | |
12033 | } | |
12034 | scale = sib.scale; | |
12035 | base = sib.base; | |
252b5132 RH |
12036 | codep++; |
12037 | } | |
260cd341 LC |
12038 | else |
12039 | { | |
12040 | /* mandatory non-vector SIB must have sib */ | |
12041 | if (bytemode == vex_sibmem_mode) | |
12042 | { | |
12043 | oappend ("(bad)"); | |
12044 | return; | |
12045 | } | |
12046 | } | |
82c18208 | 12047 | rbase = base + add; |
252b5132 | 12048 | |
7967e09e | 12049 | switch (modrm.mod) |
252b5132 RH |
12050 | { |
12051 | case 0: | |
82c18208 | 12052 | if (base == 5) |
252b5132 RH |
12053 | { |
12054 | havebase = 0; | |
cb712a9e | 12055 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
12056 | riprel = 1; |
12057 | disp = get32s (); | |
d276ec69 JB |
12058 | if (riprel && bytemode == v_bndmk_mode) |
12059 | { | |
12060 | oappend ("(bad)"); | |
12061 | return; | |
12062 | } | |
252b5132 RH |
12063 | } |
12064 | break; | |
12065 | case 1: | |
12066 | FETCH_DATA (the_info, codep + 1); | |
12067 | disp = *codep++; | |
12068 | if ((disp & 0x80) != 0) | |
12069 | disp -= 0x100; | |
43234a1e L |
12070 | if (vex.evex && shift > 0) |
12071 | disp <<= shift; | |
252b5132 RH |
12072 | break; |
12073 | case 2: | |
52b15da3 | 12074 | disp = get32s (); |
252b5132 RH |
12075 | break; |
12076 | } | |
12077 | ||
1bc60e56 L |
12078 | needindex = 0; |
12079 | needaddr32 = 0; | |
12080 | if (havesib | |
12081 | && !havebase | |
12082 | && !haveindex | |
12083 | && address_mode != mode_16bit) | |
12084 | { | |
12085 | if (address_mode == mode_64bit) | |
12086 | { | |
8e58ef80 L |
12087 | if (addr32flag) |
12088 | { | |
12089 | /* Without base nor index registers, zero-extend the | |
12090 | lower 32-bit displacement to 64 bits. */ | |
12091 | disp = (unsigned int) disp; | |
bf4ba07c | 12092 | needindex = 1; |
8e58ef80 | 12093 | } |
1bc60e56 L |
12094 | needaddr32 = 1; |
12095 | } | |
12096 | else | |
12097 | { | |
12098 | /* In 32-bit mode, we need index register to tell [offset] | |
12099 | from [eiz*1 + offset]. */ | |
12100 | needindex = 1; | |
12101 | } | |
12102 | } | |
12103 | ||
20afcfb7 L |
12104 | havedisp = (havebase |
12105 | || needindex | |
12106 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 12107 | |
252b5132 | 12108 | if (!intel_syntax) |
82c18208 | 12109 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 12110 | { |
5d669648 L |
12111 | if (havedisp || riprel) |
12112 | print_displacement (scratchbuf, disp); | |
12113 | else | |
12114 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 12115 | oappend (scratchbuf); |
52b15da3 JH |
12116 | if (riprel) |
12117 | { | |
12118 | set_op (disp, 1); | |
28596323 | 12119 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 12120 | } |
db6eb5be | 12121 | } |
2da11e11 | 12122 | |
c1dc7af5 | 12123 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
12124 | && (address_mode != mode_64bit |
12125 | || ((bytemode != v_bnd_mode) | |
12126 | && (bytemode != v_bndmk_mode) | |
12127 | && (bytemode != bnd_mode) | |
12128 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
12129 | used_prefixes |= PREFIX_ADDR; |
12130 | ||
5d669648 | 12131 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 12132 | { |
252b5132 | 12133 | *obufp++ = open_char; |
52b15da3 | 12134 | if (intel_syntax && riprel) |
185b1163 L |
12135 | { |
12136 | set_op (disp, 1); | |
28596323 | 12137 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 12138 | } |
db6eb5be | 12139 | *obufp = '\0'; |
252b5132 | 12140 | if (havebase) |
7e8b059b | 12141 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 12142 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
12143 | if (havesib) |
12144 | { | |
db51cc60 L |
12145 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
12146 | print index to tell base + index from base. */ | |
12147 | if (scale != 0 | |
20afcfb7 | 12148 | || needindex |
db51cc60 L |
12149 | || haveindex |
12150 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 12151 | { |
9306ca4a | 12152 | if (!intel_syntax || havebase) |
db6eb5be | 12153 | { |
9306ca4a JB |
12154 | *obufp++ = separator_char; |
12155 | *obufp = '\0'; | |
db6eb5be | 12156 | } |
db51cc60 | 12157 | if (haveindex) |
7e8b059b | 12158 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 12159 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 12160 | else |
7e8b059b | 12161 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
12162 | ? index64 : index32); |
12163 | ||
db6eb5be AM |
12164 | *obufp++ = scale_char; |
12165 | *obufp = '\0'; | |
12166 | sprintf (scratchbuf, "%d", 1 << scale); | |
12167 | oappend (scratchbuf); | |
12168 | } | |
252b5132 | 12169 | } |
185b1163 | 12170 | if (intel_syntax |
82c18208 | 12171 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 12172 | { |
db51cc60 | 12173 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
12174 | { |
12175 | *obufp++ = '+'; | |
12176 | *obufp = '\0'; | |
12177 | } | |
05203043 | 12178 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
12179 | { |
12180 | *obufp++ = '-'; | |
12181 | *obufp = '\0'; | |
b4b39349 | 12182 | disp = -disp; |
3d456fa1 JB |
12183 | } |
12184 | ||
db51cc60 L |
12185 | if (havedisp) |
12186 | print_displacement (scratchbuf, disp); | |
12187 | else | |
12188 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
12189 | oappend (scratchbuf); |
12190 | } | |
252b5132 RH |
12191 | |
12192 | *obufp++ = close_char; | |
db6eb5be | 12193 | *obufp = '\0'; |
252b5132 RH |
12194 | } |
12195 | else if (intel_syntax) | |
db6eb5be | 12196 | { |
82c18208 | 12197 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 12198 | { |
285ca992 | 12199 | if (!active_seg_prefix) |
252b5132 | 12200 | { |
d708bcba | 12201 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
12202 | oappend (":"); |
12203 | } | |
52b15da3 | 12204 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
12205 | oappend (scratchbuf); |
12206 | } | |
12207 | } | |
252b5132 | 12208 | } |
a23b33b3 JB |
12209 | else if (bytemode == v_bnd_mode |
12210 | || bytemode == v_bndmk_mode | |
12211 | || bytemode == bnd_mode | |
12212 | || bytemode == bnd_swap_mode) | |
12213 | { | |
12214 | oappend ("(bad)"); | |
12215 | return; | |
12216 | } | |
252b5132 | 12217 | else |
f16cd0d5 L |
12218 | { |
12219 | /* 16 bit address mode */ | |
12220 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 12221 | switch (modrm.mod) |
252b5132 RH |
12222 | { |
12223 | case 0: | |
7967e09e | 12224 | if (modrm.rm == 6) |
252b5132 RH |
12225 | { |
12226 | disp = get16 (); | |
12227 | if ((disp & 0x8000) != 0) | |
12228 | disp -= 0x10000; | |
12229 | } | |
12230 | break; | |
12231 | case 1: | |
12232 | FETCH_DATA (the_info, codep + 1); | |
12233 | disp = *codep++; | |
12234 | if ((disp & 0x80) != 0) | |
12235 | disp -= 0x100; | |
65f3ed04 JB |
12236 | if (vex.evex && shift > 0) |
12237 | disp <<= shift; | |
252b5132 RH |
12238 | break; |
12239 | case 2: | |
12240 | disp = get16 (); | |
12241 | if ((disp & 0x8000) != 0) | |
12242 | disp -= 0x10000; | |
12243 | break; | |
12244 | } | |
12245 | ||
12246 | if (!intel_syntax) | |
7967e09e | 12247 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 12248 | { |
5d669648 | 12249 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
12250 | oappend (scratchbuf); |
12251 | } | |
252b5132 | 12252 | |
7967e09e | 12253 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
12254 | { |
12255 | *obufp++ = open_char; | |
db6eb5be | 12256 | *obufp = '\0'; |
7967e09e | 12257 | oappend (index16[modrm.rm]); |
5d669648 L |
12258 | if (intel_syntax |
12259 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 12260 | { |
5d669648 | 12261 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
12262 | { |
12263 | *obufp++ = '+'; | |
12264 | *obufp = '\0'; | |
12265 | } | |
7967e09e | 12266 | else if (modrm.mod != 1) |
3d456fa1 JB |
12267 | { |
12268 | *obufp++ = '-'; | |
12269 | *obufp = '\0'; | |
b4b39349 | 12270 | disp = -disp; |
3d456fa1 JB |
12271 | } |
12272 | ||
5d669648 | 12273 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
12274 | oappend (scratchbuf); |
12275 | } | |
12276 | ||
db6eb5be AM |
12277 | *obufp++ = close_char; |
12278 | *obufp = '\0'; | |
252b5132 | 12279 | } |
3d456fa1 JB |
12280 | else if (intel_syntax) |
12281 | { | |
285ca992 | 12282 | if (!active_seg_prefix) |
3d456fa1 JB |
12283 | { |
12284 | oappend (names_seg[ds_reg - es_reg]); | |
12285 | oappend (":"); | |
12286 | } | |
12287 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
12288 | oappend (scratchbuf); | |
12289 | } | |
252b5132 | 12290 | } |
43234a1e L |
12291 | if (vex.evex && vex.b |
12292 | && (bytemode == x_mode | |
90a915bf | 12293 | || bytemode == xmmq_mode |
43234a1e L |
12294 | || bytemode == evex_half_bcst_xmmq_mode)) |
12295 | { | |
90a915bf IT |
12296 | if (vex.w |
12297 | || bytemode == xmmq_mode | |
12298 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
12299 | { |
12300 | switch (vex.length) | |
12301 | { | |
12302 | case 128: | |
12303 | oappend ("{1to2}"); | |
12304 | break; | |
12305 | case 256: | |
12306 | oappend ("{1to4}"); | |
12307 | break; | |
12308 | case 512: | |
12309 | oappend ("{1to8}"); | |
12310 | break; | |
12311 | default: | |
12312 | abort (); | |
12313 | } | |
12314 | } | |
43234a1e | 12315 | else |
b28d1bda IT |
12316 | { |
12317 | switch (vex.length) | |
12318 | { | |
12319 | case 128: | |
12320 | oappend ("{1to4}"); | |
12321 | break; | |
12322 | case 256: | |
12323 | oappend ("{1to8}"); | |
12324 | break; | |
12325 | case 512: | |
12326 | oappend ("{1to16}"); | |
12327 | break; | |
12328 | default: | |
12329 | abort (); | |
12330 | } | |
12331 | } | |
43234a1e | 12332 | } |
252b5132 RH |
12333 | } |
12334 | ||
c0f3af97 | 12335 | static void |
8b3f93e7 | 12336 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
12337 | { |
12338 | /* Skip mod/rm byte. */ | |
12339 | MODRM_CHECK; | |
12340 | codep++; | |
12341 | ||
12342 | if (modrm.mod == 3) | |
12343 | OP_E_register (bytemode, sizeflag); | |
12344 | else | |
c1e679ec | 12345 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
12346 | } |
12347 | ||
252b5132 | 12348 | static void |
26ca5450 | 12349 | OP_G (int bytemode, int sizeflag) |
252b5132 | 12350 | { |
52b15da3 | 12351 | int add = 0; |
c0a30a9f | 12352 | const char **names; |
161a04f6 L |
12353 | USED_REX (REX_R); |
12354 | if (rex & REX_R) | |
52b15da3 | 12355 | add += 8; |
252b5132 RH |
12356 | switch (bytemode) |
12357 | { | |
12358 | case b_mode: | |
e184e611 JB |
12359 | if (modrm.reg & 4) |
12360 | USED_REX (0); | |
52b15da3 | 12361 | if (rex) |
7967e09e | 12362 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 12363 | else |
7967e09e | 12364 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
12365 | break; |
12366 | case w_mode: | |
7967e09e | 12367 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
12368 | break; |
12369 | case d_mode: | |
1ba585e8 IT |
12370 | case db_mode: |
12371 | case dw_mode: | |
7967e09e | 12372 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
12373 | break; |
12374 | case q_mode: | |
7967e09e | 12375 | oappend (names64[modrm.reg + add]); |
252b5132 | 12376 | break; |
7e8b059b | 12377 | case bnd_mode: |
0d96e4df L |
12378 | if (modrm.reg > 0x3) |
12379 | { | |
12380 | oappend ("(bad)"); | |
12381 | return; | |
12382 | } | |
7e8b059b L |
12383 | oappend (names_bnd[modrm.reg]); |
12384 | break; | |
252b5132 | 12385 | case v_mode: |
9306ca4a | 12386 | case dq_mode: |
42903f7f L |
12387 | case dqb_mode: |
12388 | case dqd_mode: | |
9306ca4a | 12389 | case dqw_mode: |
bc31405e | 12390 | case movsxd_mode: |
161a04f6 L |
12391 | USED_REX (REX_W); |
12392 | if (rex & REX_W) | |
7967e09e | 12393 | oappend (names64[modrm.reg + add]); |
035e7389 JB |
12394 | else if (bytemode != v_mode && bytemode != movsxd_mode) |
12395 | oappend (names32[modrm.reg + add]); | |
252b5132 | 12396 | else |
f16cd0d5 | 12397 | { |
035e7389 | 12398 | if (sizeflag & DFLAG) |
f16cd0d5 L |
12399 | oappend (names32[modrm.reg + add]); |
12400 | else | |
12401 | oappend (names16[modrm.reg + add]); | |
12402 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12403 | } | |
252b5132 | 12404 | break; |
c0a30a9f L |
12405 | case va_mode: |
12406 | names = (address_mode == mode_64bit | |
12407 | ? names64 : names32); | |
12408 | if (!(prefixes & PREFIX_ADDR)) | |
12409 | { | |
12410 | if (address_mode == mode_16bit) | |
12411 | names = names16; | |
12412 | } | |
12413 | else | |
12414 | { | |
12415 | /* Remove "addr16/addr32". */ | |
12416 | all_prefixes[last_addr_prefix] = 0; | |
12417 | names = (address_mode != mode_32bit | |
12418 | ? names32 : names16); | |
12419 | used_prefixes |= PREFIX_ADDR; | |
12420 | } | |
12421 | oappend (names[modrm.reg + add]); | |
12422 | break; | |
90700ea2 | 12423 | case m_mode: |
cb712a9e | 12424 | if (address_mode == mode_64bit) |
7967e09e | 12425 | oappend (names64[modrm.reg + add]); |
90700ea2 | 12426 | else |
7967e09e | 12427 | oappend (names32[modrm.reg + add]); |
90700ea2 | 12428 | break; |
1ba585e8 | 12429 | case mask_bd_mode: |
43234a1e | 12430 | case mask_mode: |
9889cbb1 L |
12431 | if ((modrm.reg + add) > 0x7) |
12432 | { | |
12433 | oappend ("(bad)"); | |
12434 | return; | |
12435 | } | |
43234a1e L |
12436 | oappend (names_mask[modrm.reg + add]); |
12437 | break; | |
252b5132 RH |
12438 | default: |
12439 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12440 | break; | |
12441 | } | |
12442 | } | |
12443 | ||
52b15da3 | 12444 | static bfd_vma |
26ca5450 | 12445 | get64 (void) |
52b15da3 | 12446 | { |
5dd0794d | 12447 | bfd_vma x; |
52b15da3 | 12448 | #ifdef BFD64 |
5dd0794d AM |
12449 | unsigned int a; |
12450 | unsigned int b; | |
12451 | ||
52b15da3 JH |
12452 | FETCH_DATA (the_info, codep + 8); |
12453 | a = *codep++ & 0xff; | |
12454 | a |= (*codep++ & 0xff) << 8; | |
12455 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 12456 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 12457 | b = *codep++ & 0xff; |
52b15da3 JH |
12458 | b |= (*codep++ & 0xff) << 8; |
12459 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 12460 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
12461 | x = a + ((bfd_vma) b << 32); |
12462 | #else | |
6608db57 | 12463 | abort (); |
5dd0794d | 12464 | x = 0; |
52b15da3 JH |
12465 | #endif |
12466 | return x; | |
12467 | } | |
12468 | ||
12469 | static bfd_signed_vma | |
26ca5450 | 12470 | get32 (void) |
252b5132 | 12471 | { |
b4b39349 | 12472 | bfd_vma x = 0; |
252b5132 RH |
12473 | |
12474 | FETCH_DATA (the_info, codep + 4); | |
b4b39349 AM |
12475 | x = *codep++ & (bfd_vma) 0xff; |
12476 | x |= (*codep++ & (bfd_vma) 0xff) << 8; | |
12477 | x |= (*codep++ & (bfd_vma) 0xff) << 16; | |
12478 | x |= (*codep++ & (bfd_vma) 0xff) << 24; | |
52b15da3 JH |
12479 | return x; |
12480 | } | |
12481 | ||
12482 | static bfd_signed_vma | |
26ca5450 | 12483 | get32s (void) |
52b15da3 | 12484 | { |
b4b39349 | 12485 | bfd_vma x = 0; |
52b15da3 JH |
12486 | |
12487 | FETCH_DATA (the_info, codep + 4); | |
b4b39349 AM |
12488 | x = *codep++ & (bfd_vma) 0xff; |
12489 | x |= (*codep++ & (bfd_vma) 0xff) << 8; | |
12490 | x |= (*codep++ & (bfd_vma) 0xff) << 16; | |
12491 | x |= (*codep++ & (bfd_vma) 0xff) << 24; | |
52b15da3 | 12492 | |
b4b39349 | 12493 | x = (x ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); |
52b15da3 | 12494 | |
252b5132 RH |
12495 | return x; |
12496 | } | |
12497 | ||
12498 | static int | |
26ca5450 | 12499 | get16 (void) |
252b5132 RH |
12500 | { |
12501 | int x = 0; | |
12502 | ||
12503 | FETCH_DATA (the_info, codep + 2); | |
12504 | x = *codep++ & 0xff; | |
12505 | x |= (*codep++ & 0xff) << 8; | |
12506 | return x; | |
12507 | } | |
12508 | ||
12509 | static void | |
26ca5450 | 12510 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
12511 | { |
12512 | op_index[op_ad] = op_ad; | |
cb712a9e | 12513 | if (address_mode == mode_64bit) |
7081ff04 AJ |
12514 | { |
12515 | op_address[op_ad] = op; | |
12516 | op_riprel[op_ad] = riprel; | |
12517 | } | |
12518 | else | |
12519 | { | |
12520 | /* Mask to get a 32-bit address. */ | |
12521 | op_address[op_ad] = op & 0xffffffff; | |
12522 | op_riprel[op_ad] = riprel & 0xffffffff; | |
12523 | } | |
252b5132 RH |
12524 | } |
12525 | ||
12526 | static void | |
26ca5450 | 12527 | OP_REG (int code, int sizeflag) |
252b5132 | 12528 | { |
2da11e11 | 12529 | const char *s; |
9b60702d | 12530 | int add; |
de882298 RM |
12531 | |
12532 | switch (code) | |
12533 | { | |
12534 | case es_reg: case ss_reg: case cs_reg: | |
12535 | case ds_reg: case fs_reg: case gs_reg: | |
12536 | oappend (names_seg[code - es_reg]); | |
12537 | return; | |
12538 | } | |
12539 | ||
161a04f6 L |
12540 | USED_REX (REX_B); |
12541 | if (rex & REX_B) | |
52b15da3 | 12542 | add = 8; |
9b60702d L |
12543 | else |
12544 | add = 0; | |
52b15da3 JH |
12545 | |
12546 | switch (code) | |
12547 | { | |
52b15da3 JH |
12548 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
12549 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
12550 | s = names16[code - ax_reg + add]; | |
12551 | break; | |
e184e611 | 12552 | case ah_reg: case ch_reg: case dh_reg: case bh_reg: |
52b15da3 | 12553 | USED_REX (0); |
e184e611 JB |
12554 | /* Fall through. */ |
12555 | case al_reg: case cl_reg: case dl_reg: case bl_reg: | |
52b15da3 JH |
12556 | if (rex) |
12557 | s = names8rex[code - al_reg + add]; | |
12558 | else | |
12559 | s = names8[code - al_reg]; | |
12560 | break; | |
6439fc28 AM |
12561 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
12562 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 12563 | if (address_mode == mode_64bit |
6c067bbb | 12564 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12565 | { |
12566 | s = names64[code - rAX_reg + add]; | |
12567 | break; | |
12568 | } | |
12569 | code += eAX_reg - rAX_reg; | |
6608db57 | 12570 | /* Fall through. */ |
52b15da3 JH |
12571 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
12572 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
12573 | USED_REX (REX_W); |
12574 | if (rex & REX_W) | |
52b15da3 | 12575 | s = names64[code - eAX_reg + add]; |
52b15da3 | 12576 | else |
f16cd0d5 L |
12577 | { |
12578 | if (sizeflag & DFLAG) | |
12579 | s = names32[code - eAX_reg + add]; | |
12580 | else | |
12581 | s = names16[code - eAX_reg + add]; | |
12582 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12583 | } | |
52b15da3 | 12584 | break; |
52b15da3 JH |
12585 | default: |
12586 | s = INTERNAL_DISASSEMBLER_ERROR; | |
12587 | break; | |
12588 | } | |
12589 | oappend (s); | |
12590 | } | |
12591 | ||
12592 | static void | |
26ca5450 | 12593 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
12594 | { |
12595 | const char *s; | |
252b5132 RH |
12596 | |
12597 | switch (code) | |
12598 | { | |
12599 | case indir_dx_reg: | |
d708bcba | 12600 | if (intel_syntax) |
52fd6d94 | 12601 | s = "dx"; |
d708bcba | 12602 | else |
db6eb5be | 12603 | s = "(%dx)"; |
252b5132 | 12604 | break; |
e8b5d5f9 JB |
12605 | case al_reg: case cl_reg: |
12606 | s = names8[code - al_reg]; | |
252b5132 | 12607 | break; |
e8b5d5f9 | 12608 | case eAX_reg: |
161a04f6 L |
12609 | USED_REX (REX_W); |
12610 | if (rex & REX_W) | |
f16cd0d5 | 12611 | { |
e8b5d5f9 JB |
12612 | s = *names64; |
12613 | break; | |
f16cd0d5 | 12614 | } |
e8b5d5f9 | 12615 | /* Fall through. */ |
52fd6d94 | 12616 | case z_mode_ax_reg: |
161a04f6 | 12617 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12618 | s = *names32; |
12619 | else | |
12620 | s = *names16; | |
161a04f6 | 12621 | if (!(rex & REX_W)) |
52fd6d94 JB |
12622 | used_prefixes |= (prefixes & PREFIX_DATA); |
12623 | break; | |
252b5132 RH |
12624 | default: |
12625 | s = INTERNAL_DISASSEMBLER_ERROR; | |
12626 | break; | |
12627 | } | |
12628 | oappend (s); | |
12629 | } | |
12630 | ||
12631 | static void | |
26ca5450 | 12632 | OP_I (int bytemode, int sizeflag) |
252b5132 | 12633 | { |
52b15da3 JH |
12634 | bfd_signed_vma op; |
12635 | bfd_signed_vma mask = -1; | |
252b5132 RH |
12636 | |
12637 | switch (bytemode) | |
12638 | { | |
12639 | case b_mode: | |
12640 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
12641 | op = *codep++; |
12642 | mask = 0xff; | |
12643 | break; | |
252b5132 | 12644 | case v_mode: |
161a04f6 L |
12645 | USED_REX (REX_W); |
12646 | if (rex & REX_W) | |
52b15da3 | 12647 | op = get32s (); |
252b5132 | 12648 | else |
52b15da3 | 12649 | { |
f16cd0d5 L |
12650 | if (sizeflag & DFLAG) |
12651 | { | |
12652 | op = get32 (); | |
12653 | mask = 0xffffffff; | |
12654 | } | |
12655 | else | |
12656 | { | |
12657 | op = get16 (); | |
12658 | mask = 0xfffff; | |
12659 | } | |
12660 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 12661 | } |
252b5132 | 12662 | break; |
c1dc7af5 JB |
12663 | case d_mode: |
12664 | mask = 0xffffffff; | |
12665 | op = get32 (); | |
12666 | break; | |
252b5132 | 12667 | case w_mode: |
52b15da3 | 12668 | mask = 0xfffff; |
252b5132 RH |
12669 | op = get16 (); |
12670 | break; | |
9306ca4a JB |
12671 | case const_1_mode: |
12672 | if (intel_syntax) | |
6c067bbb | 12673 | oappend ("1"); |
9306ca4a | 12674 | return; |
252b5132 RH |
12675 | default: |
12676 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12677 | return; | |
12678 | } | |
12679 | ||
52b15da3 JH |
12680 | op &= mask; |
12681 | scratchbuf[0] = '$'; | |
d708bcba | 12682 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 12683 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
12684 | scratchbuf[0] = '\0'; |
12685 | } | |
12686 | ||
12687 | static void | |
26ca5450 | 12688 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 12689 | { |
a280ab8e | 12690 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
12691 | { |
12692 | OP_I (bytemode, sizeflag); | |
12693 | return; | |
12694 | } | |
12695 | ||
a280ab8e | 12696 | USED_REX (REX_W); |
52b15da3 | 12697 | |
52b15da3 | 12698 | scratchbuf[0] = '$'; |
a280ab8e | 12699 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 12700 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12701 | scratchbuf[0] = '\0'; |
12702 | } | |
12703 | ||
12704 | static void | |
26ca5450 | 12705 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 12706 | { |
52b15da3 | 12707 | bfd_signed_vma op; |
252b5132 RH |
12708 | |
12709 | switch (bytemode) | |
12710 | { | |
12711 | case b_mode: | |
e3949f17 | 12712 | case b_T_mode: |
252b5132 RH |
12713 | FETCH_DATA (the_info, codep + 1); |
12714 | op = *codep++; | |
12715 | if ((op & 0x80) != 0) | |
12716 | op -= 0x100; | |
e3949f17 L |
12717 | if (bytemode == b_T_mode) |
12718 | { | |
12719 | if (address_mode != mode_64bit | |
7bb15c6f | 12720 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 12721 | { |
6c067bbb RM |
12722 | /* The operand-size prefix is overridden by a REX prefix. */ |
12723 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
12724 | op &= 0xffffffff; |
12725 | else | |
12726 | op &= 0xffff; | |
12727 | } | |
12728 | } | |
12729 | else | |
12730 | { | |
12731 | if (!(rex & REX_W)) | |
12732 | { | |
12733 | if (sizeflag & DFLAG) | |
12734 | op &= 0xffffffff; | |
12735 | else | |
12736 | op &= 0xffff; | |
12737 | } | |
12738 | } | |
252b5132 RH |
12739 | break; |
12740 | case v_mode: | |
7bb15c6f RM |
12741 | /* The operand-size prefix is overridden by a REX prefix. */ |
12742 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 12743 | op = get32s (); |
252b5132 | 12744 | else |
d9e3625e | 12745 | op = get16 (); |
252b5132 RH |
12746 | break; |
12747 | default: | |
12748 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12749 | return; | |
12750 | } | |
52b15da3 JH |
12751 | |
12752 | scratchbuf[0] = '$'; | |
12753 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 12754 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12755 | } |
12756 | ||
12757 | static void | |
26ca5450 | 12758 | OP_J (int bytemode, int sizeflag) |
252b5132 | 12759 | { |
52b15da3 | 12760 | bfd_vma disp; |
7081ff04 | 12761 | bfd_vma mask = -1; |
65ca155d | 12762 | bfd_vma segment = 0; |
252b5132 RH |
12763 | |
12764 | switch (bytemode) | |
12765 | { | |
12766 | case b_mode: | |
12767 | FETCH_DATA (the_info, codep + 1); | |
12768 | disp = *codep++; | |
12769 | if ((disp & 0x80) != 0) | |
12770 | disp -= 0x100; | |
12771 | break; | |
12772 | case v_mode: | |
376cd056 | 12773 | case dqw_mode: |
5db04b09 L |
12774 | if ((sizeflag & DFLAG) |
12775 | || (address_mode == mode_64bit | |
d835a58b | 12776 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 12777 | || (rex & REX_W)))) |
52b15da3 | 12778 | disp = get32s (); |
252b5132 RH |
12779 | else |
12780 | { | |
12781 | disp = get16 (); | |
206717e8 L |
12782 | if ((disp & 0x8000) != 0) |
12783 | disp -= 0x10000; | |
65ca155d L |
12784 | /* In 16bit mode, address is wrapped around at 64k within |
12785 | the same segment. Otherwise, a data16 prefix on a jump | |
12786 | instruction means that the pc is masked to 16 bits after | |
12787 | the displacement is added! */ | |
12788 | mask = 0xffff; | |
12789 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 12790 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 12791 | & ~((bfd_vma) 0xffff)); |
252b5132 | 12792 | } |
5db04b09 | 12793 | if (address_mode != mode_64bit |
d835a58b | 12794 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 12795 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
12796 | break; |
12797 | default: | |
12798 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
12799 | return; | |
12800 | } | |
42d5f9c6 | 12801 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
12802 | set_op (disp, 0); |
12803 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
12804 | oappend (scratchbuf); |
12805 | } | |
12806 | ||
252b5132 | 12807 | static void |
ed7841b3 | 12808 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 12809 | { |
ed7841b3 | 12810 | if (bytemode == w_mode) |
7967e09e | 12811 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 12812 | else |
7967e09e | 12813 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
12814 | } |
12815 | ||
12816 | static void | |
26ca5450 | 12817 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
12818 | { |
12819 | int seg, offset; | |
12820 | ||
c608c12e | 12821 | if (sizeflag & DFLAG) |
252b5132 | 12822 | { |
c608c12e AM |
12823 | offset = get32 (); |
12824 | seg = get16 (); | |
252b5132 | 12825 | } |
c608c12e AM |
12826 | else |
12827 | { | |
12828 | offset = get16 (); | |
12829 | seg = get16 (); | |
12830 | } | |
7d421014 | 12831 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 12832 | if (intel_syntax) |
3f31e633 | 12833 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
12834 | else |
12835 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 12836 | oappend (scratchbuf); |
252b5132 RH |
12837 | } |
12838 | ||
252b5132 | 12839 | static void |
3f31e633 | 12840 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 12841 | { |
52b15da3 | 12842 | bfd_vma off; |
252b5132 | 12843 | |
3f31e633 JB |
12844 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12845 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
12846 | append_seg (); |
12847 | ||
cb712a9e | 12848 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
12849 | off = get32 (); |
12850 | else | |
12851 | off = get16 (); | |
12852 | ||
12853 | if (intel_syntax) | |
12854 | { | |
285ca992 | 12855 | if (!active_seg_prefix) |
252b5132 | 12856 | { |
d708bcba | 12857 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
12858 | oappend (":"); |
12859 | } | |
12860 | } | |
52b15da3 JH |
12861 | print_operand_value (scratchbuf, 1, off); |
12862 | oappend (scratchbuf); | |
12863 | } | |
6439fc28 | 12864 | |
52b15da3 | 12865 | static void |
3f31e633 | 12866 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
12867 | { |
12868 | bfd_vma off; | |
12869 | ||
539e75ad L |
12870 | if (address_mode != mode_64bit |
12871 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
12872 | { |
12873 | OP_OFF (bytemode, sizeflag); | |
12874 | return; | |
12875 | } | |
12876 | ||
3f31e633 JB |
12877 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12878 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
12879 | append_seg (); |
12880 | ||
6608db57 | 12881 | off = get64 (); |
52b15da3 JH |
12882 | |
12883 | if (intel_syntax) | |
12884 | { | |
285ca992 | 12885 | if (!active_seg_prefix) |
52b15da3 | 12886 | { |
d708bcba | 12887 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
12888 | oappend (":"); |
12889 | } | |
12890 | } | |
12891 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
12892 | oappend (scratchbuf); |
12893 | } | |
12894 | ||
12895 | static void | |
26ca5450 | 12896 | ptr_reg (int code, int sizeflag) |
252b5132 | 12897 | { |
2da11e11 | 12898 | const char *s; |
d708bcba | 12899 | |
1d9f512f | 12900 | *obufp++ = open_char; |
20f0a1fc | 12901 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 12902 | if (address_mode == mode_64bit) |
c1a64871 JH |
12903 | { |
12904 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 12905 | s = names32[code - eAX_reg]; |
c1a64871 | 12906 | else |
db6eb5be | 12907 | s = names64[code - eAX_reg]; |
c1a64871 | 12908 | } |
52b15da3 | 12909 | else if (sizeflag & AFLAG) |
252b5132 RH |
12910 | s = names32[code - eAX_reg]; |
12911 | else | |
12912 | s = names16[code - eAX_reg]; | |
12913 | oappend (s); | |
1d9f512f AM |
12914 | *obufp++ = close_char; |
12915 | *obufp = 0; | |
252b5132 RH |
12916 | } |
12917 | ||
12918 | static void | |
26ca5450 | 12919 | OP_ESreg (int code, int sizeflag) |
252b5132 | 12920 | { |
9306ca4a | 12921 | if (intel_syntax) |
52fd6d94 JB |
12922 | { |
12923 | switch (codep[-1]) | |
12924 | { | |
12925 | case 0x6d: /* insw/insl */ | |
12926 | intel_operand_size (z_mode, sizeflag); | |
12927 | break; | |
12928 | case 0xa5: /* movsw/movsl/movsq */ | |
12929 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12930 | case 0xab: /* stosw/stosl */ | |
12931 | case 0xaf: /* scasw/scasl */ | |
12932 | intel_operand_size (v_mode, sizeflag); | |
12933 | break; | |
12934 | default: | |
12935 | intel_operand_size (b_mode, sizeflag); | |
12936 | } | |
12937 | } | |
9ce09ba2 | 12938 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
12939 | ptr_reg (code, sizeflag); |
12940 | } | |
12941 | ||
12942 | static void | |
26ca5450 | 12943 | OP_DSreg (int code, int sizeflag) |
252b5132 | 12944 | { |
9306ca4a | 12945 | if (intel_syntax) |
52fd6d94 JB |
12946 | { |
12947 | switch (codep[-1]) | |
12948 | { | |
12949 | case 0x6f: /* outsw/outsl */ | |
12950 | intel_operand_size (z_mode, sizeflag); | |
12951 | break; | |
12952 | case 0xa5: /* movsw/movsl/movsq */ | |
12953 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12954 | case 0xad: /* lodsw/lodsl/lodsq */ | |
12955 | intel_operand_size (v_mode, sizeflag); | |
12956 | break; | |
12957 | default: | |
12958 | intel_operand_size (b_mode, sizeflag); | |
12959 | } | |
12960 | } | |
285ca992 L |
12961 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
12962 | default segment register DS is printed. */ | |
12963 | if (!active_seg_prefix) | |
12964 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 12965 | append_seg (); |
252b5132 RH |
12966 | ptr_reg (code, sizeflag); |
12967 | } | |
12968 | ||
252b5132 | 12969 | static void |
26ca5450 | 12970 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12971 | { |
9b60702d | 12972 | int add; |
161a04f6 | 12973 | if (rex & REX_R) |
c4a530c5 | 12974 | { |
161a04f6 | 12975 | USED_REX (REX_R); |
c4a530c5 JB |
12976 | add = 8; |
12977 | } | |
cb712a9e | 12978 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 12979 | { |
f16cd0d5 | 12980 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
12981 | used_prefixes |= PREFIX_LOCK; |
12982 | add = 8; | |
12983 | } | |
9b60702d L |
12984 | else |
12985 | add = 0; | |
7967e09e | 12986 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 12987 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12988 | } |
12989 | ||
252b5132 | 12990 | static void |
26ca5450 | 12991 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12992 | { |
9b60702d | 12993 | int add; |
161a04f6 L |
12994 | USED_REX (REX_R); |
12995 | if (rex & REX_R) | |
52b15da3 | 12996 | add = 8; |
9b60702d L |
12997 | else |
12998 | add = 0; | |
d708bcba | 12999 | if (intel_syntax) |
bfbd9438 | 13000 | sprintf (scratchbuf, "dr%d", modrm.reg + add); |
d708bcba | 13001 | else |
7967e09e | 13002 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
13003 | oappend (scratchbuf); |
13004 | } | |
13005 | ||
252b5132 | 13006 | static void |
26ca5450 | 13007 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13008 | { |
7967e09e | 13009 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 13010 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
13011 | } |
13012 | ||
252b5132 | 13013 | static void |
26ca5450 | 13014 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 13015 | { |
b9733481 L |
13016 | int reg = modrm.reg; |
13017 | const char **names; | |
13018 | ||
041bd2e0 JH |
13019 | used_prefixes |= (prefixes & PREFIX_DATA); |
13020 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 13021 | { |
b9733481 | 13022 | names = names_xmm; |
161a04f6 L |
13023 | USED_REX (REX_R); |
13024 | if (rex & REX_R) | |
b9733481 | 13025 | reg += 8; |
20f0a1fc | 13026 | } |
041bd2e0 | 13027 | else |
b9733481 L |
13028 | names = names_mm; |
13029 | oappend (names[reg]); | |
252b5132 RH |
13030 | } |
13031 | ||
c608c12e | 13032 | static void |
c0f3af97 | 13033 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 13034 | { |
b9733481 L |
13035 | int reg = modrm.reg; |
13036 | const char **names; | |
13037 | ||
161a04f6 L |
13038 | USED_REX (REX_R); |
13039 | if (rex & REX_R) | |
b9733481 | 13040 | reg += 8; |
43234a1e L |
13041 | if (vex.evex) |
13042 | { | |
13043 | if (!vex.r) | |
13044 | reg += 16; | |
13045 | } | |
13046 | ||
539f890d L |
13047 | if (need_vex |
13048 | && bytemode != xmm_mode | |
43234a1e L |
13049 | && bytemode != xmmq_mode |
13050 | && bytemode != evex_half_bcst_xmmq_mode | |
13051 | && bytemode != ymm_mode | |
260cd341 | 13052 | && bytemode != tmm_mode |
539f890d | 13053 | && bytemode != scalar_mode) |
c0f3af97 L |
13054 | { |
13055 | switch (vex.length) | |
13056 | { | |
13057 | case 128: | |
b9733481 | 13058 | names = names_xmm; |
c0f3af97 L |
13059 | break; |
13060 | case 256: | |
5fc35d96 IT |
13061 | if (vex.w |
13062 | || (bytemode != vex_vsib_q_w_dq_mode | |
13063 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
13064 | names = names_ymm; |
13065 | else | |
13066 | names = names_xmm; | |
c0f3af97 | 13067 | break; |
43234a1e L |
13068 | case 512: |
13069 | names = names_zmm; | |
13070 | break; | |
c0f3af97 L |
13071 | default: |
13072 | abort (); | |
13073 | } | |
13074 | } | |
43234a1e L |
13075 | else if (bytemode == xmmq_mode |
13076 | || bytemode == evex_half_bcst_xmmq_mode) | |
13077 | { | |
13078 | switch (vex.length) | |
13079 | { | |
13080 | case 128: | |
13081 | case 256: | |
13082 | names = names_xmm; | |
13083 | break; | |
13084 | case 512: | |
13085 | names = names_ymm; | |
13086 | break; | |
13087 | default: | |
13088 | abort (); | |
13089 | } | |
13090 | } | |
260cd341 LC |
13091 | else if (bytemode == tmm_mode) |
13092 | { | |
13093 | modrm.reg = reg; | |
13094 | if (reg >= 8) | |
13095 | { | |
13096 | oappend ("(bad)"); | |
13097 | return; | |
13098 | } | |
13099 | names = names_tmm; | |
13100 | } | |
43234a1e L |
13101 | else if (bytemode == ymm_mode) |
13102 | names = names_ymm; | |
c0f3af97 | 13103 | else |
b9733481 L |
13104 | names = names_xmm; |
13105 | oappend (names[reg]); | |
c608c12e AM |
13106 | } |
13107 | ||
252b5132 | 13108 | static void |
26ca5450 | 13109 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 13110 | { |
b9733481 L |
13111 | int reg; |
13112 | const char **names; | |
13113 | ||
7967e09e | 13114 | if (modrm.mod != 3) |
252b5132 | 13115 | { |
b6169b20 L |
13116 | if (intel_syntax |
13117 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
13118 | { |
13119 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
13120 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 13121 | } |
252b5132 RH |
13122 | OP_E (bytemode, sizeflag); |
13123 | return; | |
13124 | } | |
13125 | ||
b6169b20 L |
13126 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
13127 | swap_operand (); | |
13128 | ||
6608db57 | 13129 | /* Skip mod/rm byte. */ |
4bba6815 | 13130 | MODRM_CHECK; |
252b5132 | 13131 | codep++; |
041bd2e0 | 13132 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 13133 | reg = modrm.rm; |
041bd2e0 | 13134 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 13135 | { |
b9733481 | 13136 | names = names_xmm; |
161a04f6 L |
13137 | USED_REX (REX_B); |
13138 | if (rex & REX_B) | |
b9733481 | 13139 | reg += 8; |
20f0a1fc | 13140 | } |
041bd2e0 | 13141 | else |
b9733481 L |
13142 | names = names_mm; |
13143 | oappend (names[reg]); | |
252b5132 RH |
13144 | } |
13145 | ||
246c51aa L |
13146 | /* cvt* are the only instructions in sse2 which have |
13147 | both SSE and MMX operands and also have 0x66 prefix | |
13148 | in their opcode. 0x66 was originally used to differentiate | |
13149 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
13150 | cvt* separately using OP_EMC and OP_MXC */ |
13151 | static void | |
13152 | OP_EMC (int bytemode, int sizeflag) | |
13153 | { | |
7967e09e | 13154 | if (modrm.mod != 3) |
4d9567e0 MM |
13155 | { |
13156 | if (intel_syntax && bytemode == v_mode) | |
13157 | { | |
13158 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
13159 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 13160 | } |
4d9567e0 MM |
13161 | OP_E (bytemode, sizeflag); |
13162 | return; | |
13163 | } | |
246c51aa | 13164 | |
4d9567e0 MM |
13165 | /* Skip mod/rm byte. */ |
13166 | MODRM_CHECK; | |
13167 | codep++; | |
13168 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 13169 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
13170 | } |
13171 | ||
13172 | static void | |
13173 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13174 | { | |
13175 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 13176 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
13177 | } |
13178 | ||
c608c12e | 13179 | static void |
26ca5450 | 13180 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 13181 | { |
b9733481 L |
13182 | int reg; |
13183 | const char **names; | |
d6f574e0 L |
13184 | |
13185 | /* Skip mod/rm byte. */ | |
13186 | MODRM_CHECK; | |
13187 | codep++; | |
13188 | ||
7967e09e | 13189 | if (modrm.mod != 3) |
c608c12e | 13190 | { |
c1e679ec | 13191 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
13192 | return; |
13193 | } | |
d6f574e0 | 13194 | |
b9733481 | 13195 | reg = modrm.rm; |
161a04f6 L |
13196 | USED_REX (REX_B); |
13197 | if (rex & REX_B) | |
b9733481 | 13198 | reg += 8; |
43234a1e L |
13199 | if (vex.evex) |
13200 | { | |
13201 | USED_REX (REX_X); | |
13202 | if ((rex & REX_X)) | |
13203 | reg += 16; | |
13204 | } | |
c608c12e | 13205 | |
b6169b20 | 13206 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
13207 | && (bytemode == x_swap_mode |
13208 | || bytemode == d_swap_mode | |
41f5efc6 | 13209 | || bytemode == q_swap_mode)) |
b6169b20 L |
13210 | swap_operand (); |
13211 | ||
c0f3af97 L |
13212 | if (need_vex |
13213 | && bytemode != xmm_mode | |
6c30d220 L |
13214 | && bytemode != xmmdw_mode |
13215 | && bytemode != xmmqd_mode | |
13216 | && bytemode != xmm_mb_mode | |
13217 | && bytemode != xmm_mw_mode | |
13218 | && bytemode != xmm_md_mode | |
13219 | && bytemode != xmm_mq_mode | |
539f890d | 13220 | && bytemode != xmmq_mode |
43234a1e L |
13221 | && bytemode != evex_half_bcst_xmmq_mode |
13222 | && bytemode != ymm_mode | |
260cd341 | 13223 | && bytemode != tmm_mode |
1c480963 | 13224 | && bytemode != vex_scalar_w_dq_mode) |
c0f3af97 L |
13225 | { |
13226 | switch (vex.length) | |
13227 | { | |
13228 | case 128: | |
b9733481 | 13229 | names = names_xmm; |
c0f3af97 L |
13230 | break; |
13231 | case 256: | |
b9733481 | 13232 | names = names_ymm; |
c0f3af97 | 13233 | break; |
43234a1e L |
13234 | case 512: |
13235 | names = names_zmm; | |
13236 | break; | |
c0f3af97 L |
13237 | default: |
13238 | abort (); | |
13239 | } | |
13240 | } | |
43234a1e L |
13241 | else if (bytemode == xmmq_mode |
13242 | || bytemode == evex_half_bcst_xmmq_mode) | |
13243 | { | |
13244 | switch (vex.length) | |
13245 | { | |
13246 | case 128: | |
13247 | case 256: | |
13248 | names = names_xmm; | |
13249 | break; | |
13250 | case 512: | |
13251 | names = names_ymm; | |
13252 | break; | |
13253 | default: | |
13254 | abort (); | |
13255 | } | |
13256 | } | |
260cd341 LC |
13257 | else if (bytemode == tmm_mode) |
13258 | { | |
13259 | modrm.rm = reg; | |
13260 | if (reg >= 8) | |
13261 | { | |
13262 | oappend ("(bad)"); | |
13263 | return; | |
13264 | } | |
13265 | names = names_tmm; | |
13266 | } | |
43234a1e L |
13267 | else if (bytemode == ymm_mode) |
13268 | names = names_ymm; | |
c0f3af97 | 13269 | else |
b9733481 L |
13270 | names = names_xmm; |
13271 | oappend (names[reg]); | |
c608c12e AM |
13272 | } |
13273 | ||
252b5132 | 13274 | static void |
26ca5450 | 13275 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 13276 | { |
7967e09e | 13277 | if (modrm.mod == 3) |
2da11e11 AM |
13278 | OP_EM (bytemode, sizeflag); |
13279 | else | |
6608db57 | 13280 | BadOp (); |
252b5132 RH |
13281 | } |
13282 | ||
992aaec9 | 13283 | static void |
26ca5450 | 13284 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 13285 | { |
7967e09e | 13286 | if (modrm.mod == 3) |
992aaec9 AM |
13287 | OP_EX (bytemode, sizeflag); |
13288 | else | |
6608db57 | 13289 | BadOp (); |
992aaec9 AM |
13290 | } |
13291 | ||
cc0ec051 AM |
13292 | static void |
13293 | OP_M (int bytemode, int sizeflag) | |
13294 | { | |
7967e09e | 13295 | if (modrm.mod == 3) |
75413a22 L |
13296 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
13297 | BadOp (); | |
cc0ec051 AM |
13298 | else |
13299 | OP_E (bytemode, sizeflag); | |
13300 | } | |
13301 | ||
13302 | static void | |
13303 | OP_0f07 (int bytemode, int sizeflag) | |
13304 | { | |
7967e09e | 13305 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
13306 | BadOp (); |
13307 | else | |
13308 | OP_E (bytemode, sizeflag); | |
13309 | } | |
13310 | ||
46e883c5 | 13311 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 13312 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 13313 | |
cc0ec051 | 13314 | static void |
46e883c5 | 13315 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 13316 | { |
8b38ad71 L |
13317 | if ((prefixes & PREFIX_DATA) != 0 |
13318 | || (rex != 0 | |
13319 | && rex != 0x48 | |
13320 | && address_mode == mode_64bit)) | |
46e883c5 L |
13321 | OP_REG (bytemode, sizeflag); |
13322 | else | |
13323 | strcpy (obuf, "nop"); | |
13324 | } | |
13325 | ||
13326 | static void | |
13327 | NOP_Fixup2 (int bytemode, int sizeflag) | |
13328 | { | |
8b38ad71 L |
13329 | if ((prefixes & PREFIX_DATA) != 0 |
13330 | || (rex != 0 | |
13331 | && rex != 0x48 | |
13332 | && address_mode == mode_64bit)) | |
46e883c5 | 13333 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
13334 | } |
13335 | ||
84037f8c | 13336 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
13337 | /* 00 */ NULL, NULL, NULL, NULL, |
13338 | /* 04 */ NULL, NULL, NULL, NULL, | |
13339 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13340 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
13341 | /* 10 */ NULL, NULL, NULL, NULL, |
13342 | /* 14 */ NULL, NULL, NULL, NULL, | |
13343 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 13344 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
13345 | /* 20 */ NULL, NULL, NULL, NULL, |
13346 | /* 24 */ NULL, NULL, NULL, NULL, | |
13347 | /* 28 */ NULL, NULL, NULL, NULL, | |
13348 | /* 2C */ NULL, NULL, NULL, NULL, | |
13349 | /* 30 */ NULL, NULL, NULL, NULL, | |
13350 | /* 34 */ NULL, NULL, NULL, NULL, | |
13351 | /* 38 */ NULL, NULL, NULL, NULL, | |
13352 | /* 3C */ NULL, NULL, NULL, NULL, | |
13353 | /* 40 */ NULL, NULL, NULL, NULL, | |
13354 | /* 44 */ NULL, NULL, NULL, NULL, | |
13355 | /* 48 */ NULL, NULL, NULL, NULL, | |
13356 | /* 4C */ NULL, NULL, NULL, NULL, | |
13357 | /* 50 */ NULL, NULL, NULL, NULL, | |
13358 | /* 54 */ NULL, NULL, NULL, NULL, | |
13359 | /* 58 */ NULL, NULL, NULL, NULL, | |
13360 | /* 5C */ NULL, NULL, NULL, NULL, | |
13361 | /* 60 */ NULL, NULL, NULL, NULL, | |
13362 | /* 64 */ NULL, NULL, NULL, NULL, | |
13363 | /* 68 */ NULL, NULL, NULL, NULL, | |
13364 | /* 6C */ NULL, NULL, NULL, NULL, | |
13365 | /* 70 */ NULL, NULL, NULL, NULL, | |
13366 | /* 74 */ NULL, NULL, NULL, NULL, | |
13367 | /* 78 */ NULL, NULL, NULL, NULL, | |
13368 | /* 7C */ NULL, NULL, NULL, NULL, | |
13369 | /* 80 */ NULL, NULL, NULL, NULL, | |
13370 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
13371 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
13372 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
13373 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
13374 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
13375 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
13376 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
13377 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
13378 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
13379 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
13380 | /* AC */ NULL, NULL, "pfacc", NULL, | |
13381 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 13382 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 13383 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
13384 | /* BC */ NULL, NULL, NULL, "pavgusb", |
13385 | /* C0 */ NULL, NULL, NULL, NULL, | |
13386 | /* C4 */ NULL, NULL, NULL, NULL, | |
13387 | /* C8 */ NULL, NULL, NULL, NULL, | |
13388 | /* CC */ NULL, NULL, NULL, NULL, | |
13389 | /* D0 */ NULL, NULL, NULL, NULL, | |
13390 | /* D4 */ NULL, NULL, NULL, NULL, | |
13391 | /* D8 */ NULL, NULL, NULL, NULL, | |
13392 | /* DC */ NULL, NULL, NULL, NULL, | |
13393 | /* E0 */ NULL, NULL, NULL, NULL, | |
13394 | /* E4 */ NULL, NULL, NULL, NULL, | |
13395 | /* E8 */ NULL, NULL, NULL, NULL, | |
13396 | /* EC */ NULL, NULL, NULL, NULL, | |
13397 | /* F0 */ NULL, NULL, NULL, NULL, | |
13398 | /* F4 */ NULL, NULL, NULL, NULL, | |
13399 | /* F8 */ NULL, NULL, NULL, NULL, | |
13400 | /* FC */ NULL, NULL, NULL, NULL, | |
13401 | }; | |
13402 | ||
13403 | static void | |
26ca5450 | 13404 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
13405 | { |
13406 | const char *mnemonic; | |
13407 | ||
13408 | FETCH_DATA (the_info, codep + 1); | |
13409 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
13410 | place where an 8-bit immediate would normally go. ie. the last | |
13411 | byte of the instruction. */ | |
ea397f5b | 13412 | obufp = mnemonicendp; |
c608c12e | 13413 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 13414 | if (mnemonic) |
2da11e11 | 13415 | oappend (mnemonic); |
252b5132 RH |
13416 | else |
13417 | { | |
13418 | /* Since a variable sized modrm/sib chunk is between the start | |
13419 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
13420 | all the modrm processing first, and don't know until now that | |
13421 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
13422 | op_out[0][0] = '\0'; |
13423 | op_out[1][0] = '\0'; | |
6608db57 | 13424 | BadOp (); |
252b5132 | 13425 | } |
ea397f5b | 13426 | mnemonicendp = obufp; |
252b5132 | 13427 | } |
c608c12e | 13428 | |
c4de7606 | 13429 | static const struct op simd_cmp_op[] = |
ea397f5b L |
13430 | { |
13431 | { STRING_COMMA_LEN ("eq") }, | |
13432 | { STRING_COMMA_LEN ("lt") }, | |
13433 | { STRING_COMMA_LEN ("le") }, | |
13434 | { STRING_COMMA_LEN ("unord") }, | |
13435 | { STRING_COMMA_LEN ("neq") }, | |
13436 | { STRING_COMMA_LEN ("nlt") }, | |
13437 | { STRING_COMMA_LEN ("nle") }, | |
13438 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
13439 | }; |
13440 | ||
c4de7606 JB |
13441 | static const struct op vex_cmp_op[] = |
13442 | { | |
13443 | { STRING_COMMA_LEN ("eq_uq") }, | |
13444 | { STRING_COMMA_LEN ("nge") }, | |
13445 | { STRING_COMMA_LEN ("ngt") }, | |
13446 | { STRING_COMMA_LEN ("false") }, | |
13447 | { STRING_COMMA_LEN ("neq_oq") }, | |
13448 | { STRING_COMMA_LEN ("ge") }, | |
13449 | { STRING_COMMA_LEN ("gt") }, | |
13450 | { STRING_COMMA_LEN ("true") }, | |
13451 | { STRING_COMMA_LEN ("eq_os") }, | |
13452 | { STRING_COMMA_LEN ("lt_oq") }, | |
13453 | { STRING_COMMA_LEN ("le_oq") }, | |
13454 | { STRING_COMMA_LEN ("unord_s") }, | |
13455 | { STRING_COMMA_LEN ("neq_us") }, | |
13456 | { STRING_COMMA_LEN ("nlt_uq") }, | |
13457 | { STRING_COMMA_LEN ("nle_uq") }, | |
13458 | { STRING_COMMA_LEN ("ord_s") }, | |
13459 | { STRING_COMMA_LEN ("eq_us") }, | |
13460 | { STRING_COMMA_LEN ("nge_uq") }, | |
13461 | { STRING_COMMA_LEN ("ngt_uq") }, | |
13462 | { STRING_COMMA_LEN ("false_os") }, | |
13463 | { STRING_COMMA_LEN ("neq_os") }, | |
13464 | { STRING_COMMA_LEN ("ge_oq") }, | |
13465 | { STRING_COMMA_LEN ("gt_oq") }, | |
13466 | { STRING_COMMA_LEN ("true_us") }, | |
13467 | }; | |
13468 | ||
c608c12e | 13469 | static void |
ad19981d | 13470 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
13471 | { |
13472 | unsigned int cmp_type; | |
13473 | ||
13474 | FETCH_DATA (the_info, codep + 1); | |
13475 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 13476 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 13477 | { |
ad19981d | 13478 | char suffix [3]; |
ea397f5b | 13479 | char *p = mnemonicendp - 2; |
ad19981d L |
13480 | suffix[0] = p[0]; |
13481 | suffix[1] = p[1]; | |
13482 | suffix[2] = '\0'; | |
ea397f5b L |
13483 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
13484 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e | 13485 | } |
c4de7606 JB |
13486 | else if (need_vex |
13487 | && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) | |
13488 | { | |
13489 | char suffix [3]; | |
13490 | char *p = mnemonicendp - 2; | |
13491 | suffix[0] = p[0]; | |
13492 | suffix[1] = p[1]; | |
13493 | suffix[2] = '\0'; | |
13494 | cmp_type -= ARRAY_SIZE (simd_cmp_op); | |
13495 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); | |
13496 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
13497 | } | |
c608c12e AM |
13498 | else |
13499 | { | |
ad19981d L |
13500 | /* We have a reserved extension byte. Output it directly. */ |
13501 | scratchbuf[0] = '$'; | |
13502 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 13503 | oappend_maybe_intel (scratchbuf); |
ad19981d | 13504 | scratchbuf[0] = '\0'; |
c608c12e AM |
13505 | } |
13506 | } | |
13507 | ||
9916071f | 13508 | static void |
7abb8d81 | 13509 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 13510 | { |
7abb8d81 | 13511 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
13512 | if (!intel_syntax) |
13513 | { | |
081e283f JB |
13514 | strcpy (op_out[0], names32[0]); |
13515 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 13516 | if (bytemode == eBX_reg) |
081e283f | 13517 | strcpy (op_out[2], names32[3]); |
b844680a L |
13518 | two_source_ops = 1; |
13519 | } | |
13520 | /* Skip mod/rm byte. */ | |
13521 | MODRM_CHECK; | |
13522 | codep++; | |
13523 | } | |
13524 | ||
13525 | static void | |
13526 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
13527 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 13528 | { |
081e283f | 13529 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 13530 | if (!intel_syntax) |
ca164297 | 13531 | { |
cb712a9e L |
13532 | const char **names = (address_mode == mode_64bit |
13533 | ? names64 : names32); | |
1d9f512f | 13534 | |
081e283f | 13535 | if (prefixes & PREFIX_ADDR) |
ca164297 | 13536 | { |
b844680a | 13537 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 13538 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
13539 | names = (address_mode != mode_32bit |
13540 | ? names32 : names16); | |
b844680a | 13541 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 13542 | } |
081e283f JB |
13543 | else if (address_mode == mode_16bit) |
13544 | names = names16; | |
13545 | strcpy (op_out[0], names[0]); | |
13546 | strcpy (op_out[1], names32[1]); | |
13547 | strcpy (op_out[2], names32[2]); | |
b844680a | 13548 | two_source_ops = 1; |
ca164297 | 13549 | } |
b844680a L |
13550 | /* Skip mod/rm byte. */ |
13551 | MODRM_CHECK; | |
13552 | codep++; | |
30123838 JB |
13553 | } |
13554 | ||
6608db57 KH |
13555 | static void |
13556 | BadOp (void) | |
2da11e11 | 13557 | { |
6608db57 KH |
13558 | /* Throw away prefixes and 1st. opcode byte. */ |
13559 | codep = insn_codep + 1; | |
2da11e11 AM |
13560 | oappend ("(bad)"); |
13561 | } | |
4cc91dba | 13562 | |
35c52694 L |
13563 | static void |
13564 | REP_Fixup (int bytemode, int sizeflag) | |
13565 | { | |
13566 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
13567 | lods and stos. */ | |
35c52694 | 13568 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 13569 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
13570 | |
13571 | switch (bytemode) | |
13572 | { | |
13573 | case al_reg: | |
13574 | case eAX_reg: | |
13575 | case indir_dx_reg: | |
13576 | OP_IMREG (bytemode, sizeflag); | |
13577 | break; | |
13578 | case eDI_reg: | |
13579 | OP_ESreg (bytemode, sizeflag); | |
13580 | break; | |
13581 | case eSI_reg: | |
13582 | OP_DSreg (bytemode, sizeflag); | |
13583 | break; | |
13584 | default: | |
13585 | abort (); | |
13586 | break; | |
13587 | } | |
13588 | } | |
f5804c90 | 13589 | |
d835a58b JB |
13590 | static void |
13591 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13592 | { | |
13593 | if ( isa64 != amd64 ) | |
13594 | return; | |
13595 | ||
13596 | obufp = obuf; | |
13597 | BadOp (); | |
13598 | mnemonicendp = obufp; | |
13599 | ++codep; | |
13600 | } | |
13601 | ||
7e8b059b L |
13602 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
13603 | "bnd". */ | |
13604 | ||
13605 | static void | |
13606 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
13607 | { | |
13608 | if (prefixes & PREFIX_REPNZ) | |
13609 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
13610 | } | |
13611 | ||
04ef582a L |
13612 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
13613 | "notrack". */ | |
13614 | ||
13615 | static void | |
13616 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13617 | int sizeflag ATTRIBUTE_UNUSED) | |
13618 | { | |
9fef80d6 | 13619 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
13620 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
13621 | { | |
4e9ac44a | 13622 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 13623 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
13624 | active_seg_prefix = 0; |
13625 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
13626 | } | |
13627 | } | |
13628 | ||
42164a71 L |
13629 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
13630 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
13631 | */ | |
13632 | ||
13633 | static void | |
13634 | HLE_Fixup1 (int bytemode, int sizeflag) | |
13635 | { | |
13636 | if (modrm.mod != 3 | |
13637 | && (prefixes & PREFIX_LOCK) != 0) | |
13638 | { | |
13639 | if (prefixes & PREFIX_REPZ) | |
13640 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13641 | if (prefixes & PREFIX_REPNZ) | |
13642 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13643 | } | |
13644 | ||
13645 | OP_E (bytemode, sizeflag); | |
13646 | } | |
13647 | ||
13648 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
13649 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
13650 | */ | |
13651 | ||
13652 | static void | |
13653 | HLE_Fixup2 (int bytemode, int sizeflag) | |
13654 | { | |
13655 | if (modrm.mod != 3) | |
13656 | { | |
13657 | if (prefixes & PREFIX_REPZ) | |
13658 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13659 | if (prefixes & PREFIX_REPNZ) | |
13660 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13661 | } | |
13662 | ||
13663 | OP_E (bytemode, sizeflag); | |
13664 | } | |
13665 | ||
13666 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
13667 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
13668 | ||
13669 | static void | |
13670 | HLE_Fixup3 (int bytemode, int sizeflag) | |
13671 | { | |
13672 | if (modrm.mod != 3 | |
13673 | && last_repz_prefix > last_repnz_prefix | |
13674 | && (prefixes & PREFIX_REPZ) != 0) | |
13675 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13676 | ||
13677 | OP_E (bytemode, sizeflag); | |
13678 | } | |
13679 | ||
f5804c90 L |
13680 | static void |
13681 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
13682 | { | |
161a04f6 L |
13683 | USED_REX (REX_W); |
13684 | if (rex & REX_W) | |
f5804c90 L |
13685 | { |
13686 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
13687 | char *p = mnemonicendp - 2; |
13688 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 13689 | bytemode = o_mode; |
f5804c90 | 13690 | } |
42164a71 L |
13691 | else if ((prefixes & PREFIX_LOCK) != 0) |
13692 | { | |
13693 | if (prefixes & PREFIX_REPZ) | |
13694 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
13695 | if (prefixes & PREFIX_REPNZ) | |
13696 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
13697 | } | |
13698 | ||
f5804c90 L |
13699 | OP_M (bytemode, sizeflag); |
13700 | } | |
42903f7f L |
13701 | |
13702 | static void | |
13703 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
13704 | { | |
b9733481 L |
13705 | const char **names; |
13706 | ||
c0f3af97 L |
13707 | if (need_vex) |
13708 | { | |
13709 | switch (vex.length) | |
13710 | { | |
13711 | case 128: | |
b9733481 | 13712 | names = names_xmm; |
c0f3af97 L |
13713 | break; |
13714 | case 256: | |
b9733481 | 13715 | names = names_ymm; |
c0f3af97 L |
13716 | break; |
13717 | default: | |
13718 | abort (); | |
13719 | } | |
13720 | } | |
13721 | else | |
b9733481 L |
13722 | names = names_xmm; |
13723 | oappend (names[reg]); | |
42903f7f | 13724 | } |
381d071f L |
13725 | |
13726 | static void | |
eacc9c89 L |
13727 | FXSAVE_Fixup (int bytemode, int sizeflag) |
13728 | { | |
13729 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
13730 | USED_REX (REX_W); | |
13731 | if (rex & REX_W) | |
13732 | { | |
13733 | char *p = mnemonicendp; | |
13734 | *p++ = '6'; | |
13735 | *p++ = '4'; | |
13736 | *p = '\0'; | |
13737 | mnemonicendp = p; | |
13738 | } | |
13739 | OP_M (bytemode, sizeflag); | |
15c7c1d8 JB |
13740 | } |
13741 | ||
c0f3af97 L |
13742 | /* Display the destination register operand for instructions with |
13743 | VEX. */ | |
13744 | ||
13745 | static void | |
13746 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13747 | { | |
539f890d | 13748 | int reg; |
b9733481 L |
13749 | const char **names; |
13750 | ||
c0f3af97 L |
13751 | if (!need_vex) |
13752 | abort (); | |
13753 | ||
539f890d | 13754 | reg = vex.register_specifier; |
63c6fc6c | 13755 | vex.register_specifier = 0; |
5f847646 JB |
13756 | if (address_mode != mode_64bit) |
13757 | reg &= 7; | |
13758 | else if (vex.evex && !vex.v) | |
13759 | reg += 16; | |
43234a1e | 13760 | |
539f890d L |
13761 | if (bytemode == vex_scalar_mode) |
13762 | { | |
13763 | oappend (names_xmm[reg]); | |
13764 | return; | |
13765 | } | |
13766 | ||
260cd341 LC |
13767 | if (bytemode == tmm_mode) |
13768 | { | |
13769 | /* All 3 TMM registers must be distinct. */ | |
13770 | if (reg >= 8) | |
13771 | oappend ("(bad)"); | |
13772 | else | |
13773 | { | |
13774 | /* This must be the 3rd operand. */ | |
13775 | if (obufp != op_out[2]) | |
13776 | abort (); | |
13777 | oappend (names_tmm[reg]); | |
13778 | if (reg == modrm.reg || reg == modrm.rm) | |
13779 | strcpy (obufp, "/(bad)"); | |
13780 | } | |
13781 | ||
13782 | if (modrm.reg == modrm.rm || modrm.reg == reg || modrm.rm == reg) | |
13783 | { | |
13784 | if (modrm.reg <= 8 | |
13785 | && (modrm.reg == modrm.rm || modrm.reg == reg)) | |
13786 | strcat (op_out[0], "/(bad)"); | |
13787 | if (modrm.rm <= 8 | |
13788 | && (modrm.rm == modrm.reg || modrm.rm == reg)) | |
13789 | strcat (op_out[1], "/(bad)"); | |
13790 | } | |
13791 | ||
13792 | return; | |
13793 | } | |
13794 | ||
c0f3af97 L |
13795 | switch (vex.length) |
13796 | { | |
13797 | case 128: | |
13798 | switch (bytemode) | |
13799 | { | |
13800 | case vex_mode: | |
6c30d220 | 13801 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13802 | case vex_vsib_q_w_d_mode: |
cb21baef L |
13803 | names = names_xmm; |
13804 | break; | |
13805 | case dq_mode: | |
390a6789 | 13806 | if (rex & REX_W) |
cb21baef L |
13807 | names = names64; |
13808 | else | |
13809 | names = names32; | |
c0f3af97 | 13810 | break; |
1ba585e8 | 13811 | case mask_bd_mode: |
43234a1e | 13812 | case mask_mode: |
9889cbb1 L |
13813 | if (reg > 0x7) |
13814 | { | |
13815 | oappend ("(bad)"); | |
13816 | return; | |
13817 | } | |
43234a1e L |
13818 | names = names_mask; |
13819 | break; | |
c0f3af97 L |
13820 | default: |
13821 | abort (); | |
13822 | return; | |
13823 | } | |
c0f3af97 L |
13824 | break; |
13825 | case 256: | |
13826 | switch (bytemode) | |
13827 | { | |
13828 | case vex_mode: | |
6c30d220 L |
13829 | names = names_ymm; |
13830 | break; | |
13831 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 13832 | case vex_vsib_q_w_d_mode: |
6c30d220 | 13833 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 13834 | break; |
1ba585e8 | 13835 | case mask_bd_mode: |
43234a1e | 13836 | case mask_mode: |
9889cbb1 L |
13837 | if (reg > 0x7) |
13838 | { | |
13839 | oappend ("(bad)"); | |
13840 | return; | |
13841 | } | |
43234a1e L |
13842 | names = names_mask; |
13843 | break; | |
c0f3af97 | 13844 | default: |
a37a2806 NC |
13845 | /* See PR binutils/20893 for a reproducer. */ |
13846 | oappend ("(bad)"); | |
c0f3af97 L |
13847 | return; |
13848 | } | |
c0f3af97 | 13849 | break; |
43234a1e L |
13850 | case 512: |
13851 | names = names_zmm; | |
13852 | break; | |
c0f3af97 L |
13853 | default: |
13854 | abort (); | |
13855 | break; | |
13856 | } | |
539f890d | 13857 | oappend (names[reg]); |
c0f3af97 L |
13858 | } |
13859 | ||
41f5efc6 JB |
13860 | static void |
13861 | OP_VexR (int bytemode, int sizeflag) | |
13862 | { | |
13863 | if (modrm.mod == 3) | |
13864 | OP_VEX (bytemode, sizeflag); | |
13865 | } | |
13866 | ||
5dd85c99 | 13867 | static void |
e6123d0c | 13868 | OP_VexW (int bytemode, int sizeflag) |
5dd85c99 | 13869 | { |
e6123d0c | 13870 | OP_VEX (bytemode, sizeflag); |
5dd85c99 | 13871 | |
5dd85c99 | 13872 | if (vex.w) |
5f847646 | 13873 | { |
e6123d0c JB |
13874 | /* Swap 2nd and 3rd operands. */ |
13875 | strcpy (scratchbuf, op_out[2]); | |
13876 | strcpy (op_out[2], op_out[1]); | |
13877 | strcpy (op_out[1], scratchbuf); | |
5f847646 | 13878 | } |
5dd85c99 SP |
13879 | } |
13880 | ||
c0f3af97 L |
13881 | static void |
13882 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
13883 | { | |
13884 | int reg; | |
6384fd9e | 13885 | const char **names = names_xmm; |
b9733481 | 13886 | |
c0f3af97 L |
13887 | FETCH_DATA (the_info, codep + 1); |
13888 | reg = *codep++; | |
13889 | ||
6384fd9e | 13890 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
13891 | abort (); |
13892 | ||
c0f3af97 | 13893 | reg >>= 4; |
5f847646 JB |
13894 | if (address_mode != mode_64bit) |
13895 | reg &= 7; | |
dae39acc | 13896 | |
6384fd9e JB |
13897 | if (bytemode == x_mode && vex.length == 256) |
13898 | names = names_ymm; | |
13899 | ||
b9733481 | 13900 | oappend (names[reg]); |
b13b1bc0 JB |
13901 | |
13902 | if (vex.w) | |
13903 | { | |
13904 | /* Swap 3rd and 4th operands. */ | |
13905 | strcpy (scratchbuf, op_out[3]); | |
13906 | strcpy (op_out[3], op_out[2]); | |
13907 | strcpy (op_out[2], scratchbuf); | |
13908 | } | |
c0f3af97 L |
13909 | } |
13910 | ||
922d8de8 | 13911 | static void |
93abb146 JB |
13912 | OP_VexI4 (int bytemode ATTRIBUTE_UNUSED, |
13913 | int sizeflag ATTRIBUTE_UNUSED) | |
922d8de8 | 13914 | { |
93abb146 JB |
13915 | scratchbuf[0] = '$'; |
13916 | print_operand_value (scratchbuf + 1, 1, codep[-1] & 0xf); | |
13917 | oappend_maybe_intel (scratchbuf); | |
922d8de8 DR |
13918 | } |
13919 | ||
43234a1e L |
13920 | static void |
13921 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13922 | int sizeflag ATTRIBUTE_UNUSED) | |
13923 | { | |
13924 | unsigned int cmp_type; | |
13925 | ||
13926 | if (!vex.evex) | |
13927 | abort (); | |
13928 | ||
13929 | FETCH_DATA (the_info, codep + 1); | |
13930 | cmp_type = *codep++ & 0xff; | |
13931 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
13932 | If it's the case, print suffix, otherwise - print the immediate. */ | |
13933 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
13934 | && cmp_type != 3 | |
13935 | && cmp_type != 7) | |
13936 | { | |
13937 | char suffix [3]; | |
13938 | char *p = mnemonicendp - 2; | |
13939 | ||
13940 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
13941 | if (p[0] == 'p') | |
13942 | { | |
13943 | p++; | |
13944 | suffix[0] = p[0]; | |
13945 | suffix[1] = '\0'; | |
13946 | } | |
13947 | else | |
13948 | { | |
13949 | suffix[0] = p[0]; | |
13950 | suffix[1] = p[1]; | |
13951 | suffix[2] = '\0'; | |
13952 | } | |
13953 | ||
13954 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
13955 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
13956 | } | |
be92cb14 JB |
13957 | else |
13958 | { | |
13959 | /* We have a reserved extension byte. Output it directly. */ | |
13960 | scratchbuf[0] = '$'; | |
13961 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
13962 | oappend_maybe_intel (scratchbuf); | |
13963 | scratchbuf[0] = '\0'; | |
13964 | } | |
13965 | } | |
13966 | ||
13967 | static const struct op xop_cmp_op[] = | |
13968 | { | |
13969 | { STRING_COMMA_LEN ("lt") }, | |
13970 | { STRING_COMMA_LEN ("le") }, | |
13971 | { STRING_COMMA_LEN ("gt") }, | |
13972 | { STRING_COMMA_LEN ("ge") }, | |
13973 | { STRING_COMMA_LEN ("eq") }, | |
13974 | { STRING_COMMA_LEN ("neq") }, | |
13975 | { STRING_COMMA_LEN ("false") }, | |
13976 | { STRING_COMMA_LEN ("true") } | |
13977 | }; | |
13978 | ||
13979 | static void | |
13980 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
13981 | int sizeflag ATTRIBUTE_UNUSED) | |
13982 | { | |
13983 | unsigned int cmp_type; | |
13984 | ||
13985 | FETCH_DATA (the_info, codep + 1); | |
13986 | cmp_type = *codep++ & 0xff; | |
13987 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
13988 | { | |
13989 | char suffix[3]; | |
13990 | char *p = mnemonicendp - 2; | |
13991 | ||
13992 | /* vpcom* can have both one- and two-lettered suffix. */ | |
13993 | if (p[0] == 'm') | |
13994 | { | |
13995 | p++; | |
13996 | suffix[0] = p[0]; | |
13997 | suffix[1] = '\0'; | |
13998 | } | |
13999 | else | |
14000 | { | |
14001 | suffix[0] = p[0]; | |
14002 | suffix[1] = p[1]; | |
14003 | suffix[2] = '\0'; | |
14004 | } | |
14005 | ||
14006 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
14007 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
14008 | } | |
43234a1e L |
14009 | else |
14010 | { | |
14011 | /* We have a reserved extension byte. Output it directly. */ | |
14012 | scratchbuf[0] = '$'; | |
14013 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 14014 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
14015 | scratchbuf[0] = '\0'; |
14016 | } | |
14017 | } | |
14018 | ||
ea397f5b L |
14019 | static const struct op pclmul_op[] = |
14020 | { | |
14021 | { STRING_COMMA_LEN ("lql") }, | |
14022 | { STRING_COMMA_LEN ("hql") }, | |
14023 | { STRING_COMMA_LEN ("lqh") }, | |
14024 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
14025 | }; |
14026 | ||
14027 | static void | |
14028 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
14029 | int sizeflag ATTRIBUTE_UNUSED) | |
14030 | { | |
14031 | unsigned int pclmul_type; | |
14032 | ||
14033 | FETCH_DATA (the_info, codep + 1); | |
14034 | pclmul_type = *codep++ & 0xff; | |
14035 | switch (pclmul_type) | |
14036 | { | |
14037 | case 0x10: | |
14038 | pclmul_type = 2; | |
14039 | break; | |
14040 | case 0x11: | |
14041 | pclmul_type = 3; | |
14042 | break; | |
14043 | default: | |
14044 | break; | |
7bb15c6f | 14045 | } |
c0f3af97 L |
14046 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
14047 | { | |
14048 | char suffix [4]; | |
ea397f5b | 14049 | char *p = mnemonicendp - 3; |
c0f3af97 L |
14050 | suffix[0] = p[0]; |
14051 | suffix[1] = p[1]; | |
14052 | suffix[2] = p[2]; | |
14053 | suffix[3] = '\0'; | |
ea397f5b L |
14054 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
14055 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
14056 | } |
14057 | else | |
14058 | { | |
14059 | /* We have a reserved extension byte. Output it directly. */ | |
14060 | scratchbuf[0] = '$'; | |
14061 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 14062 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
14063 | scratchbuf[0] = '\0'; |
14064 | } | |
14065 | } | |
14066 | ||
bc31405e L |
14067 | static void |
14068 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
14069 | { | |
14070 | /* Add proper suffix to "movsxd". */ | |
14071 | char *p = mnemonicendp; | |
14072 | ||
14073 | switch (bytemode) | |
14074 | { | |
14075 | case movsxd_mode: | |
14076 | if (intel_syntax) | |
14077 | { | |
14078 | *p++ = 'x'; | |
14079 | *p++ = 'd'; | |
14080 | goto skip; | |
14081 | } | |
14082 | ||
14083 | USED_REX (REX_W); | |
14084 | if (rex & REX_W) | |
14085 | { | |
14086 | *p++ = 'l'; | |
14087 | *p++ = 'q'; | |
14088 | } | |
14089 | else | |
14090 | { | |
14091 | *p++ = 'x'; | |
14092 | *p++ = 'd'; | |
14093 | } | |
14094 | break; | |
14095 | default: | |
14096 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14097 | break; | |
14098 | } | |
14099 | ||
dc1e8a47 | 14100 | skip: |
bc31405e L |
14101 | mnemonicendp = p; |
14102 | *p = '\0'; | |
14103 | OP_E (bytemode, sizeflag); | |
14104 | } | |
14105 | ||
43234a1e L |
14106 | static void |
14107 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14108 | { | |
14109 | if (!vex.evex | |
1ba585e8 | 14110 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
14111 | abort (); |
14112 | ||
14113 | USED_REX (REX_R); | |
14114 | if ((rex & REX_R) != 0 || !vex.r) | |
14115 | { | |
14116 | BadOp (); | |
14117 | return; | |
14118 | } | |
14119 | ||
14120 | oappend (names_mask [modrm.reg]); | |
14121 | } | |
14122 | ||
14123 | static void | |
14124 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
14125 | { | |
43234a1e L |
14126 | if (modrm.mod == 3 && vex.b) |
14127 | switch (bytemode) | |
14128 | { | |
70df6fc9 L |
14129 | case evex_rounding_64_mode: |
14130 | if (address_mode != mode_64bit) | |
14131 | { | |
14132 | oappend ("(bad)"); | |
14133 | break; | |
14134 | } | |
14135 | /* Fall through. */ | |
43234a1e L |
14136 | case evex_rounding_mode: |
14137 | oappend (names_rounding[vex.ll]); | |
14138 | break; | |
14139 | case evex_sae_mode: | |
14140 | oappend ("{sae}"); | |
14141 | break; | |
14142 | default: | |
6df22cf6 | 14143 | abort (); |
43234a1e L |
14144 | break; |
14145 | } | |
14146 | } |