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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
82704155 | 2 | Copyright (C) 1988-2019 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
252b5132 RH |
40 | |
41 | #include <setjmp.h> | |
42 | ||
26ca5450 AJ |
43 | static int print_insn (bfd_vma, disassemble_info *); |
44 | static void dofloat (int); | |
45 | static void OP_ST (int, int); | |
46 | static void OP_STi (int, int); | |
47 | static int putop (const char *, int); | |
48 | static void oappend (const char *); | |
49 | static void append_seg (void); | |
50 | static void OP_indirE (int, int); | |
51 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 52 | static void OP_E_register (int, int); |
c1e679ec | 53 | static void OP_E_memory (int, int); |
5d669648 | 54 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
55 | static void OP_E (int, int); |
56 | static void OP_G (int, int); | |
57 | static bfd_vma get64 (void); | |
58 | static bfd_signed_vma get32 (void); | |
59 | static bfd_signed_vma get32s (void); | |
60 | static int get16 (void); | |
61 | static void set_op (bfd_vma, int); | |
b844680a | 62 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
63 | static void OP_REG (int, int); |
64 | static void OP_IMREG (int, int); | |
65 | static void OP_I (int, int); | |
66 | static void OP_I64 (int, int); | |
67 | static void OP_sI (int, int); | |
68 | static void OP_J (int, int); | |
69 | static void OP_SEG (int, int); | |
70 | static void OP_DIR (int, int); | |
71 | static void OP_OFF (int, int); | |
72 | static void OP_OFF64 (int, int); | |
73 | static void ptr_reg (int, int); | |
74 | static void OP_ESreg (int, int); | |
75 | static void OP_DSreg (int, int); | |
76 | static void OP_C (int, int); | |
77 | static void OP_D (int, int); | |
78 | static void OP_T (int, int); | |
6f74c397 | 79 | static void OP_R (int, int); |
26ca5450 AJ |
80 | static void OP_MMX (int, int); |
81 | static void OP_XMM (int, int); | |
82 | static void OP_EM (int, int); | |
83 | static void OP_EX (int, int); | |
4d9567e0 MM |
84 | static void OP_EMC (int,int); |
85 | static void OP_MXC (int,int); | |
26ca5450 AJ |
86 | static void OP_MS (int, int); |
87 | static void OP_XS (int, int); | |
cc0ec051 | 88 | static void OP_M (int, int); |
c0f3af97 L |
89 | static void OP_VEX (int, int); |
90 | static void OP_EX_Vex (int, int); | |
922d8de8 | 91 | static void OP_EX_VexW (int, int); |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
9916071f | 104 | static void OP_Mwaitx (int, int); |
46e883c5 L |
105 | static void NOP_Fixup1 (int, int); |
106 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 107 | static void OP_3DNowSuffix (int, int); |
ad19981d | 108 | static void CMP_Fixup (int, int); |
26ca5450 | 109 | static void BadOp (void); |
35c52694 | 110 | static void REP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
252b5132 | 127 | |
43234a1e L |
128 | static void OP_Mask (int, int); |
129 | ||
6608db57 | 130 | struct dis_private { |
252b5132 RH |
131 | /* Points to first byte not fetched. */ |
132 | bfd_byte *max_fetched; | |
0b1cf022 | 133 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 134 | bfd_vma insn_start; |
e396998b | 135 | int orig_sizeflag; |
8df14d78 | 136 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
137 | }; |
138 | ||
cb712a9e L |
139 | enum address_mode |
140 | { | |
141 | mode_16bit, | |
142 | mode_32bit, | |
143 | mode_64bit | |
144 | }; | |
145 | ||
146 | enum address_mode address_mode; | |
52b15da3 | 147 | |
5076851f ILT |
148 | /* Flags for the prefixes for the current instruction. See below. */ |
149 | static int prefixes; | |
150 | ||
52b15da3 JH |
151 | /* REX prefix the current instruction. See below. */ |
152 | static int rex; | |
153 | /* Bits of REX we've already used. */ | |
154 | static int rex_used; | |
d869730d | 155 | /* REX bits in original REX prefix ignored. */ |
c0f3af97 | 156 | static int rex_ignored; |
52b15da3 JH |
157 | /* Mark parts used in the REX prefix. When we are testing for |
158 | empty prefix (for 8bit register REX extension), just mask it | |
159 | out. Otherwise test for REX bit is excuse for existence of REX | |
160 | only in case value is nonzero. */ | |
161 | #define USED_REX(value) \ | |
162 | { \ | |
163 | if (value) \ | |
161a04f6 L |
164 | { \ |
165 | if ((rex & value)) \ | |
166 | rex_used |= (value) | REX_OPCODE; \ | |
167 | } \ | |
52b15da3 | 168 | else \ |
161a04f6 | 169 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
170 | } |
171 | ||
7d421014 ILT |
172 | /* Flags for prefixes which we somehow handled when printing the |
173 | current instruction. */ | |
174 | static int used_prefixes; | |
175 | ||
5076851f ILT |
176 | /* Flags stored in PREFIXES. */ |
177 | #define PREFIX_REPZ 1 | |
178 | #define PREFIX_REPNZ 2 | |
179 | #define PREFIX_LOCK 4 | |
180 | #define PREFIX_CS 8 | |
181 | #define PREFIX_SS 0x10 | |
182 | #define PREFIX_DS 0x20 | |
183 | #define PREFIX_ES 0x40 | |
184 | #define PREFIX_FS 0x80 | |
185 | #define PREFIX_GS 0x100 | |
186 | #define PREFIX_DATA 0x200 | |
187 | #define PREFIX_ADDR 0x400 | |
188 | #define PREFIX_FWAIT 0x800 | |
189 | ||
252b5132 RH |
190 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
191 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
192 | on error. */ | |
193 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 194 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
195 | ? 1 : fetch_data ((info), (addr))) |
196 | ||
197 | static int | |
26ca5450 | 198 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
199 | { |
200 | int status; | |
6608db57 | 201 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
202 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
203 | ||
0b1cf022 | 204 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
205 | status = (*info->read_memory_func) (start, |
206 | priv->max_fetched, | |
207 | addr - priv->max_fetched, | |
208 | info); | |
209 | else | |
210 | status = -1; | |
252b5132 RH |
211 | if (status != 0) |
212 | { | |
7d421014 | 213 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
214 | print_insn_i386 will do something sensible. Otherwise, print |
215 | an error. We do that here because this is where we know | |
216 | STATUS. */ | |
7d421014 | 217 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 218 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 219 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
220 | } |
221 | else | |
222 | priv->max_fetched = addr; | |
223 | return 1; | |
224 | } | |
225 | ||
bf890a93 | 226 | /* Possible values for prefix requirement. */ |
507bd325 L |
227 | #define PREFIX_IGNORED_SHIFT 16 |
228 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
232 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
233 | ||
234 | /* Opcode prefixes. */ | |
235 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
236 | | PREFIX_REPNZ \ | |
237 | | PREFIX_DATA) | |
238 | ||
239 | /* Prefixes ignored. */ | |
240 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
241 | | PREFIX_IGNORED_REPNZ \ | |
242 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 243 | |
ce518a5f | 244 | #define XX { NULL, 0 } |
507bd325 | 245 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
246 | |
247 | #define Eb { OP_E, b_mode } | |
7e8b059b | 248 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 249 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 250 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 251 | #define Ev { OP_E, v_mode } |
de89d0a3 | 252 | #define Eva { OP_E, va_mode } |
7e8b059b | 253 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 254 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
255 | #define Ed { OP_E, d_mode } |
256 | #define Edq { OP_E, dq_mode } | |
257 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 258 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
259 | #define Edb { OP_E, db_mode } |
260 | #define Edw { OP_E, dw_mode } | |
42903f7f | 261 | #define Edqd { OP_E, dqd_mode } |
d20dee9e | 262 | #define Edqa { OP_E, dqa_mode } |
09335d05 | 263 | #define Eq { OP_E, q_mode } |
07f5af7d | 264 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
265 | #define indirEp { OP_indirE, f_mode } |
266 | #define stackEv { OP_E, stack_v_mode } | |
267 | #define Em { OP_E, m_mode } | |
268 | #define Ew { OP_E, w_mode } | |
269 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 270 | #define Ma { OP_M, a_mode } |
b844680a | 271 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 272 | #define Md { OP_M, d_mode } |
f1f8f695 | 273 | #define Mo { OP_M, o_mode } |
ce518a5f L |
274 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
275 | #define Mq { OP_M, q_mode } | |
d276ec69 | 276 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 277 | #define Mx { OP_M, x_mode } |
c0f3af97 | 278 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 279 | #define Gb { OP_G, b_mode } |
7e8b059b | 280 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
281 | #define Gv { OP_G, v_mode } |
282 | #define Gd { OP_G, d_mode } | |
283 | #define Gdq { OP_G, dq_mode } | |
284 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 285 | #define Gva { OP_G, va_mode } |
ce518a5f | 286 | #define Gw { OP_G, w_mode } |
6f74c397 | 287 | #define Rd { OP_R, d_mode } |
43234a1e | 288 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 289 | #define Rm { OP_R, m_mode } |
ce518a5f L |
290 | #define Ib { OP_I, b_mode } |
291 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 292 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 293 | #define Iv { OP_I, v_mode } |
7bb15c6f | 294 | #define sIv { OP_sI, v_mode } |
ce518a5f L |
295 | #define Iq { OP_I, q_mode } |
296 | #define Iv64 { OP_I64, v_mode } | |
297 | #define Iw { OP_I, w_mode } | |
298 | #define I1 { OP_I, const_1_mode } | |
299 | #define Jb { OP_J, b_mode } | |
300 | #define Jv { OP_J, v_mode } | |
301 | #define Cm { OP_C, m_mode } | |
302 | #define Dm { OP_D, m_mode } | |
303 | #define Td { OP_T, d_mode } | |
b844680a | 304 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
305 | |
306 | #define RMeAX { OP_REG, eAX_reg } | |
307 | #define RMeBX { OP_REG, eBX_reg } | |
308 | #define RMeCX { OP_REG, eCX_reg } | |
309 | #define RMeDX { OP_REG, eDX_reg } | |
310 | #define RMeSP { OP_REG, eSP_reg } | |
311 | #define RMeBP { OP_REG, eBP_reg } | |
312 | #define RMeSI { OP_REG, eSI_reg } | |
313 | #define RMeDI { OP_REG, eDI_reg } | |
314 | #define RMrAX { OP_REG, rAX_reg } | |
315 | #define RMrBX { OP_REG, rBX_reg } | |
316 | #define RMrCX { OP_REG, rCX_reg } | |
317 | #define RMrDX { OP_REG, rDX_reg } | |
318 | #define RMrSP { OP_REG, rSP_reg } | |
319 | #define RMrBP { OP_REG, rBP_reg } | |
320 | #define RMrSI { OP_REG, rSI_reg } | |
321 | #define RMrDI { OP_REG, rDI_reg } | |
322 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
323 | #define RMCL { OP_REG, cl_reg } |
324 | #define RMDL { OP_REG, dl_reg } | |
325 | #define RMBL { OP_REG, bl_reg } | |
326 | #define RMAH { OP_REG, ah_reg } | |
327 | #define RMCH { OP_REG, ch_reg } | |
328 | #define RMDH { OP_REG, dh_reg } | |
329 | #define RMBH { OP_REG, bh_reg } | |
330 | #define RMAX { OP_REG, ax_reg } | |
331 | #define RMDX { OP_REG, dx_reg } | |
332 | ||
333 | #define eAX { OP_IMREG, eAX_reg } | |
334 | #define eBX { OP_IMREG, eBX_reg } | |
335 | #define eCX { OP_IMREG, eCX_reg } | |
336 | #define eDX { OP_IMREG, eDX_reg } | |
337 | #define eSP { OP_IMREG, eSP_reg } | |
338 | #define eBP { OP_IMREG, eBP_reg } | |
339 | #define eSI { OP_IMREG, eSI_reg } | |
340 | #define eDI { OP_IMREG, eDI_reg } | |
341 | #define AL { OP_IMREG, al_reg } | |
342 | #define CL { OP_IMREG, cl_reg } | |
343 | #define DL { OP_IMREG, dl_reg } | |
344 | #define BL { OP_IMREG, bl_reg } | |
345 | #define AH { OP_IMREG, ah_reg } | |
346 | #define CH { OP_IMREG, ch_reg } | |
347 | #define DH { OP_IMREG, dh_reg } | |
348 | #define BH { OP_IMREG, bh_reg } | |
349 | #define AX { OP_IMREG, ax_reg } | |
350 | #define DX { OP_IMREG, dx_reg } | |
351 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
352 | #define indirDX { OP_IMREG, indir_dx_reg } | |
353 | ||
354 | #define Sw { OP_SEG, w_mode } | |
355 | #define Sv { OP_SEG, v_mode } | |
356 | #define Ap { OP_DIR, 0 } | |
357 | #define Ob { OP_OFF64, b_mode } | |
358 | #define Ov { OP_OFF64, v_mode } | |
359 | #define Xb { OP_DSreg, eSI_reg } | |
360 | #define Xv { OP_DSreg, eSI_reg } | |
361 | #define Xz { OP_DSreg, eSI_reg } | |
362 | #define Yb { OP_ESreg, eDI_reg } | |
363 | #define Yv { OP_ESreg, eDI_reg } | |
364 | #define DSBX { OP_DSreg, eBX_reg } | |
365 | ||
366 | #define es { OP_REG, es_reg } | |
367 | #define ss { OP_REG, ss_reg } | |
368 | #define cs { OP_REG, cs_reg } | |
369 | #define ds { OP_REG, ds_reg } | |
370 | #define fs { OP_REG, fs_reg } | |
371 | #define gs { OP_REG, gs_reg } | |
372 | ||
373 | #define MX { OP_MMX, 0 } | |
374 | #define XM { OP_XMM, 0 } | |
539f890d | 375 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 376 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 377 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 378 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 379 | #define EM { OP_EM, v_mode } |
b6169b20 | 380 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 381 | #define EMd { OP_EM, d_mode } |
14051056 | 382 | #define EMx { OP_EM, x_mode } |
53467f57 | 383 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 384 | #define EXw { OP_EX, w_mode } |
53467f57 | 385 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 386 | #define EXd { OP_EX, d_mode } |
539f890d | 387 | #define EXdScalar { OP_EX, d_scalar_mode } |
fa99fab2 | 388 | #define EXdS { OP_EX, d_swap_mode } |
43234a1e | 389 | #define EXdScalarS { OP_EX, d_scalar_swap_mode } |
09a2c6cf | 390 | #define EXq { OP_EX, q_mode } |
539f890d L |
391 | #define EXqScalar { OP_EX, q_scalar_mode } |
392 | #define EXqScalarS { OP_EX, q_scalar_swap_mode } | |
b6169b20 | 393 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 394 | #define EXx { OP_EX, x_mode } |
b6169b20 | 395 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 396 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 397 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 398 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 399 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
400 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
401 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
402 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
403 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
43234a1e | 404 | #define EXxmm_mdq { OP_EX, xmm_mdq_mode } |
6c30d220 L |
405 | #define EXxmmdw { OP_EX, xmmdw_mode } |
406 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 407 | #define EXymmq { OP_EX, ymmq_mode } |
0bfee649 | 408 | #define EXVexWdq { OP_EX, vex_w_dq_mode } |
1c480963 | 409 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
410 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
411 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
412 | #define MS { OP_MS, v_mode } |
413 | #define XS { OP_XS, v_mode } | |
09335d05 | 414 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 415 | #define MXC { OP_MXC, 0 } |
ce518a5f | 416 | #define OPSUF { OP_3DNowSuffix, 0 } |
ad19981d | 417 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 418 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 419 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
420 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
421 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 422 | |
c0f3af97 | 423 | #define Vex { OP_VEX, vex_mode } |
539f890d | 424 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 425 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
426 | #define Vex128 { OP_VEX, vex128_mode } |
427 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 428 | #define VexGdq { OP_VEX, dq_mode } |
c0f3af97 | 429 | #define EXdVex { OP_EX_Vex, d_mode } |
fa99fab2 | 430 | #define EXdVexS { OP_EX_Vex, d_swap_mode } |
539f890d | 431 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
c0f3af97 | 432 | #define EXqVex { OP_EX_Vex, q_mode } |
fa99fab2 | 433 | #define EXqVexS { OP_EX_Vex, q_swap_mode } |
539f890d | 434 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
922d8de8 DR |
435 | #define EXVexW { OP_EX_VexW, x_mode } |
436 | #define EXdVexW { OP_EX_VexW, d_mode } | |
437 | #define EXqVexW { OP_EX_VexW, q_mode } | |
a683cc34 | 438 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
c0f3af97 | 439 | #define XMVex { OP_XMM_Vex, 0 } |
539f890d | 440 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 441 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
442 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
443 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 444 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 445 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 446 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
447 | |
448 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 449 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
450 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
451 | ||
452 | #define XMask { OP_Mask, mask_mode } | |
453 | #define MaskG { OP_G, mask_mode } | |
454 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 455 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
456 | #define MaskR { OP_R, mask_mode } |
457 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 458 | |
6c30d220 | 459 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 460 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 461 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 462 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 463 | |
35c52694 | 464 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
465 | #define Xbr { REP_Fixup, eSI_reg } |
466 | #define Xvr { REP_Fixup, eSI_reg } | |
467 | #define Ybr { REP_Fixup, eDI_reg } | |
468 | #define Yvr { REP_Fixup, eDI_reg } | |
469 | #define Yzr { REP_Fixup, eDI_reg } | |
470 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
471 | #define ALr { REP_Fixup, al_reg } | |
472 | #define eAXr { REP_Fixup, eAX_reg } | |
473 | ||
42164a71 L |
474 | /* Used handle HLE prefix for lockable instructions. */ |
475 | #define Ebh1 { HLE_Fixup1, b_mode } | |
476 | #define Evh1 { HLE_Fixup1, v_mode } | |
477 | #define Ebh2 { HLE_Fixup2, b_mode } | |
478 | #define Evh2 { HLE_Fixup2, v_mode } | |
479 | #define Ebh3 { HLE_Fixup3, b_mode } | |
480 | #define Evh3 { HLE_Fixup3, v_mode } | |
481 | ||
7e8b059b | 482 | #define BND { BND_Fixup, 0 } |
04ef582a | 483 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 484 | |
ce518a5f L |
485 | #define cond_jump_flag { NULL, cond_jump_mode } |
486 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 487 | |
252b5132 | 488 | /* bits in sizeflag */ |
252b5132 | 489 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
490 | #define AFLAG 2 |
491 | #define DFLAG 1 | |
492 | ||
51e7da1b L |
493 | enum |
494 | { | |
495 | /* byte operand */ | |
496 | b_mode = 1, | |
497 | /* byte operand with operand swapped */ | |
3873ba12 | 498 | b_swap_mode, |
e3949f17 L |
499 | /* byte operand, sign extend like 'T' suffix */ |
500 | b_T_mode, | |
51e7da1b | 501 | /* operand size depends on prefixes */ |
3873ba12 | 502 | v_mode, |
51e7da1b | 503 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 504 | v_swap_mode, |
de89d0a3 IT |
505 | /* operand size depends on address prefix */ |
506 | va_mode, | |
51e7da1b | 507 | /* word operand */ |
3873ba12 | 508 | w_mode, |
51e7da1b | 509 | /* double word operand */ |
3873ba12 | 510 | d_mode, |
51e7da1b | 511 | /* double word operand with operand swapped */ |
3873ba12 | 512 | d_swap_mode, |
51e7da1b | 513 | /* quad word operand */ |
3873ba12 | 514 | q_mode, |
51e7da1b | 515 | /* quad word operand with operand swapped */ |
3873ba12 | 516 | q_swap_mode, |
51e7da1b | 517 | /* ten-byte operand */ |
3873ba12 | 518 | t_mode, |
43234a1e L |
519 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
520 | broadcast enabled. */ | |
3873ba12 | 521 | x_mode, |
43234a1e L |
522 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
523 | evex_x_gscat_mode, | |
524 | /* Similar to x_mode, but with disabled broadcast. */ | |
525 | evex_x_nobcst_mode, | |
526 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
527 | in EVEX. */ | |
3873ba12 | 528 | x_swap_mode, |
51e7da1b | 529 | /* 16-byte XMM operand */ |
3873ba12 | 530 | xmm_mode, |
43234a1e L |
531 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
532 | memory operand (depending on vector length). Broadcast isn't | |
533 | allowed. */ | |
3873ba12 | 534 | xmmq_mode, |
43234a1e L |
535 | /* Same as xmmq_mode, but broadcast is allowed. */ |
536 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
537 | /* XMM register or byte memory operand */ |
538 | xmm_mb_mode, | |
539 | /* XMM register or word memory operand */ | |
540 | xmm_mw_mode, | |
541 | /* XMM register or double word memory operand */ | |
542 | xmm_md_mode, | |
543 | /* XMM register or quad word memory operand */ | |
544 | xmm_mq_mode, | |
43234a1e L |
545 | /* XMM register or double/quad word memory operand, depending on |
546 | VEX.W. */ | |
547 | xmm_mdq_mode, | |
548 | /* 16-byte XMM, word, double word or quad word operand. */ | |
6c30d220 | 549 | xmmdw_mode, |
43234a1e | 550 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 551 | xmmqd_mode, |
43234a1e L |
552 | /* 32-byte YMM operand */ |
553 | ymm_mode, | |
554 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 555 | ymmq_mode, |
6c30d220 L |
556 | /* 32-byte YMM or 16-byte word operand */ |
557 | ymmxmm_mode, | |
51e7da1b | 558 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 559 | m_mode, |
51e7da1b | 560 | /* pair of v_mode operands */ |
3873ba12 L |
561 | a_mode, |
562 | cond_jump_mode, | |
563 | loop_jcxz_mode, | |
7e8b059b | 564 | v_bnd_mode, |
d276ec69 JB |
565 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
566 | v_bndmk_mode, | |
51e7da1b | 567 | /* operand size depends on REX prefixes. */ |
3873ba12 | 568 | dq_mode, |
51e7da1b | 569 | /* registers like dq_mode, memory like w_mode. */ |
3873ba12 | 570 | dqw_mode, |
9f79e886 | 571 | /* bounds operand */ |
7e8b059b | 572 | bnd_mode, |
9f79e886 JB |
573 | /* bounds operand with operand swapped */ |
574 | bnd_swap_mode, | |
51e7da1b | 575 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
576 | f_mode, |
577 | const_1_mode, | |
07f5af7d L |
578 | /* v_mode for indirect branch opcodes. */ |
579 | indir_v_mode, | |
51e7da1b | 580 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 581 | stack_v_mode, |
51e7da1b | 582 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 583 | z_mode, |
51e7da1b | 584 | /* 16-byte operand */ |
3873ba12 | 585 | o_mode, |
51e7da1b | 586 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 587 | dqb_mode, |
1ba585e8 IT |
588 | /* registers like d_mode, memory like b_mode. */ |
589 | db_mode, | |
590 | /* registers like d_mode, memory like w_mode. */ | |
591 | dw_mode, | |
51e7da1b | 592 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 593 | dqd_mode, |
d20dee9e L |
594 | /* operand size depends on the W bit as well as address mode. */ |
595 | dqa_mode, | |
51e7da1b | 596 | /* normal vex mode */ |
3873ba12 | 597 | vex_mode, |
51e7da1b | 598 | /* 128bit vex mode */ |
3873ba12 | 599 | vex128_mode, |
51e7da1b | 600 | /* 256bit vex mode */ |
3873ba12 | 601 | vex256_mode, |
51e7da1b | 602 | /* operand size depends on the VEX.W bit. */ |
3873ba12 | 603 | vex_w_dq_mode, |
d55ee72f | 604 | |
6c30d220 L |
605 | /* Similar to vex_w_dq_mode, with VSIB dword indices. */ |
606 | vex_vsib_d_w_dq_mode, | |
5fc35d96 IT |
607 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
608 | vex_vsib_d_w_d_mode, | |
6c30d220 L |
609 | /* Similar to vex_w_dq_mode, with VSIB qword indices. */ |
610 | vex_vsib_q_w_dq_mode, | |
5fc35d96 IT |
611 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
612 | vex_vsib_q_w_d_mode, | |
6c30d220 | 613 | |
539f890d L |
614 | /* scalar, ignore vector length. */ |
615 | scalar_mode, | |
53467f57 IT |
616 | /* like b_mode, ignore vector length. */ |
617 | b_scalar_mode, | |
618 | /* like w_mode, ignore vector length. */ | |
619 | w_scalar_mode, | |
539f890d L |
620 | /* like d_mode, ignore vector length. */ |
621 | d_scalar_mode, | |
622 | /* like d_swap_mode, ignore vector length. */ | |
623 | d_scalar_swap_mode, | |
624 | /* like q_mode, ignore vector length. */ | |
625 | q_scalar_mode, | |
626 | /* like q_swap_mode, ignore vector length. */ | |
627 | q_scalar_swap_mode, | |
628 | /* like vex_mode, ignore vector length. */ | |
629 | vex_scalar_mode, | |
1c480963 L |
630 | /* like vex_w_dq_mode, ignore vector length. */ |
631 | vex_scalar_w_dq_mode, | |
539f890d | 632 | |
43234a1e L |
633 | /* Static rounding. */ |
634 | evex_rounding_mode, | |
70df6fc9 L |
635 | /* Static rounding, 64-bit mode only. */ |
636 | evex_rounding_64_mode, | |
43234a1e L |
637 | /* Supress all exceptions. */ |
638 | evex_sae_mode, | |
639 | ||
640 | /* Mask register operand. */ | |
641 | mask_mode, | |
1ba585e8 IT |
642 | /* Mask register operand. */ |
643 | mask_bd_mode, | |
43234a1e | 644 | |
3873ba12 L |
645 | es_reg, |
646 | cs_reg, | |
647 | ss_reg, | |
648 | ds_reg, | |
649 | fs_reg, | |
650 | gs_reg, | |
d55ee72f | 651 | |
3873ba12 L |
652 | eAX_reg, |
653 | eCX_reg, | |
654 | eDX_reg, | |
655 | eBX_reg, | |
656 | eSP_reg, | |
657 | eBP_reg, | |
658 | eSI_reg, | |
659 | eDI_reg, | |
d55ee72f | 660 | |
3873ba12 L |
661 | al_reg, |
662 | cl_reg, | |
663 | dl_reg, | |
664 | bl_reg, | |
665 | ah_reg, | |
666 | ch_reg, | |
667 | dh_reg, | |
668 | bh_reg, | |
d55ee72f | 669 | |
3873ba12 L |
670 | ax_reg, |
671 | cx_reg, | |
672 | dx_reg, | |
673 | bx_reg, | |
674 | sp_reg, | |
675 | bp_reg, | |
676 | si_reg, | |
677 | di_reg, | |
d55ee72f | 678 | |
3873ba12 L |
679 | rAX_reg, |
680 | rCX_reg, | |
681 | rDX_reg, | |
682 | rBX_reg, | |
683 | rSP_reg, | |
684 | rBP_reg, | |
685 | rSI_reg, | |
686 | rDI_reg, | |
d55ee72f | 687 | |
3873ba12 L |
688 | z_mode_ax_reg, |
689 | indir_dx_reg | |
51e7da1b | 690 | }; |
252b5132 | 691 | |
51e7da1b L |
692 | enum |
693 | { | |
694 | FLOATCODE = 1, | |
3873ba12 L |
695 | USE_REG_TABLE, |
696 | USE_MOD_TABLE, | |
697 | USE_RM_TABLE, | |
698 | USE_PREFIX_TABLE, | |
699 | USE_X86_64_TABLE, | |
700 | USE_3BYTE_TABLE, | |
f88c9eb0 | 701 | USE_XOP_8F_TABLE, |
3873ba12 L |
702 | USE_VEX_C4_TABLE, |
703 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 704 | USE_VEX_LEN_TABLE, |
43234a1e | 705 | USE_VEX_W_TABLE, |
04e2a182 L |
706 | USE_EVEX_TABLE, |
707 | USE_EVEX_LEN_TABLE | |
51e7da1b | 708 | }; |
6439fc28 | 709 | |
bf890a93 | 710 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 711 | |
bf890a93 IT |
712 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
713 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
714 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
715 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
716 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
717 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
718 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
719 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 720 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 721 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
722 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
723 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
724 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 725 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 726 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 727 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 728 | |
51e7da1b L |
729 | enum |
730 | { | |
731 | REG_80 = 0, | |
3873ba12 | 732 | REG_81, |
7148c369 | 733 | REG_83, |
3873ba12 L |
734 | REG_8F, |
735 | REG_C0, | |
736 | REG_C1, | |
737 | REG_C6, | |
738 | REG_C7, | |
739 | REG_D0, | |
740 | REG_D1, | |
741 | REG_D2, | |
742 | REG_D3, | |
743 | REG_F6, | |
744 | REG_F7, | |
745 | REG_FE, | |
746 | REG_FF, | |
747 | REG_0F00, | |
748 | REG_0F01, | |
749 | REG_0F0D, | |
750 | REG_0F18, | |
c48935d7 | 751 | REG_0F1C_MOD_0, |
603555e5 | 752 | REG_0F1E_MOD_3, |
3873ba12 L |
753 | REG_0F71, |
754 | REG_0F72, | |
755 | REG_0F73, | |
756 | REG_0FA6, | |
757 | REG_0FA7, | |
758 | REG_0FAE, | |
759 | REG_0FBA, | |
760 | REG_0FC7, | |
592a252b L |
761 | REG_VEX_0F71, |
762 | REG_VEX_0F72, | |
763 | REG_VEX_0F73, | |
764 | REG_VEX_0FAE, | |
f12dc422 | 765 | REG_VEX_0F38F3, |
f88c9eb0 | 766 | REG_XOP_LWPCB, |
2a2a0f38 QN |
767 | REG_XOP_LWP, |
768 | REG_XOP_TBM_01, | |
43234a1e L |
769 | REG_XOP_TBM_02, |
770 | ||
1ba585e8 | 771 | REG_EVEX_0F71, |
43234a1e L |
772 | REG_EVEX_0F72, |
773 | REG_EVEX_0F73, | |
774 | REG_EVEX_0F38C6, | |
775 | REG_EVEX_0F38C7 | |
51e7da1b | 776 | }; |
1ceb70f8 | 777 | |
51e7da1b L |
778 | enum |
779 | { | |
780 | MOD_8D = 0, | |
42164a71 L |
781 | MOD_C6_REG_7, |
782 | MOD_C7_REG_7, | |
4a357820 MZ |
783 | MOD_FF_REG_3, |
784 | MOD_FF_REG_5, | |
3873ba12 L |
785 | MOD_0F01_REG_0, |
786 | MOD_0F01_REG_1, | |
787 | MOD_0F01_REG_2, | |
788 | MOD_0F01_REG_3, | |
8eab4136 | 789 | MOD_0F01_REG_5, |
3873ba12 L |
790 | MOD_0F01_REG_7, |
791 | MOD_0F12_PREFIX_0, | |
792 | MOD_0F13, | |
793 | MOD_0F16_PREFIX_0, | |
794 | MOD_0F17, | |
795 | MOD_0F18_REG_0, | |
796 | MOD_0F18_REG_1, | |
797 | MOD_0F18_REG_2, | |
798 | MOD_0F18_REG_3, | |
d7189fa5 RM |
799 | MOD_0F18_REG_4, |
800 | MOD_0F18_REG_5, | |
801 | MOD_0F18_REG_6, | |
802 | MOD_0F18_REG_7, | |
7e8b059b L |
803 | MOD_0F1A_PREFIX_0, |
804 | MOD_0F1B_PREFIX_0, | |
805 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 806 | MOD_0F1C_PREFIX_0, |
603555e5 | 807 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
808 | MOD_0F24, |
809 | MOD_0F26, | |
810 | MOD_0F2B_PREFIX_0, | |
811 | MOD_0F2B_PREFIX_1, | |
812 | MOD_0F2B_PREFIX_2, | |
813 | MOD_0F2B_PREFIX_3, | |
814 | MOD_0F51, | |
815 | MOD_0F71_REG_2, | |
816 | MOD_0F71_REG_4, | |
817 | MOD_0F71_REG_6, | |
818 | MOD_0F72_REG_2, | |
819 | MOD_0F72_REG_4, | |
820 | MOD_0F72_REG_6, | |
821 | MOD_0F73_REG_2, | |
822 | MOD_0F73_REG_3, | |
823 | MOD_0F73_REG_6, | |
824 | MOD_0F73_REG_7, | |
825 | MOD_0FAE_REG_0, | |
826 | MOD_0FAE_REG_1, | |
827 | MOD_0FAE_REG_2, | |
828 | MOD_0FAE_REG_3, | |
829 | MOD_0FAE_REG_4, | |
830 | MOD_0FAE_REG_5, | |
831 | MOD_0FAE_REG_6, | |
832 | MOD_0FAE_REG_7, | |
833 | MOD_0FB2, | |
834 | MOD_0FB4, | |
835 | MOD_0FB5, | |
a8484f96 | 836 | MOD_0FC3, |
963f3586 IT |
837 | MOD_0FC7_REG_3, |
838 | MOD_0FC7_REG_4, | |
839 | MOD_0FC7_REG_5, | |
3873ba12 L |
840 | MOD_0FC7_REG_6, |
841 | MOD_0FC7_REG_7, | |
842 | MOD_0FD7, | |
843 | MOD_0FE7_PREFIX_2, | |
844 | MOD_0FF0_PREFIX_3, | |
845 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
846 | MOD_0F38F5_PREFIX_2, |
847 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 848 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 849 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 850 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 851 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
852 | MOD_62_32BIT, |
853 | MOD_C4_32BIT, | |
854 | MOD_C5_32BIT, | |
592a252b L |
855 | MOD_VEX_0F12_PREFIX_0, |
856 | MOD_VEX_0F13, | |
857 | MOD_VEX_0F16_PREFIX_0, | |
858 | MOD_VEX_0F17, | |
859 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
860 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
861 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
862 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
863 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
864 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
865 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
866 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
867 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
868 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
869 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
870 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
871 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
872 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
873 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
874 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
875 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
876 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
877 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
878 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
879 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
880 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
881 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
882 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
883 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
884 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
885 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
886 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
887 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
888 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
889 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
890 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
891 | MOD_VEX_0F50, |
892 | MOD_VEX_0F71_REG_2, | |
893 | MOD_VEX_0F71_REG_4, | |
894 | MOD_VEX_0F71_REG_6, | |
895 | MOD_VEX_0F72_REG_2, | |
896 | MOD_VEX_0F72_REG_4, | |
897 | MOD_VEX_0F72_REG_6, | |
898 | MOD_VEX_0F73_REG_2, | |
899 | MOD_VEX_0F73_REG_3, | |
900 | MOD_VEX_0F73_REG_6, | |
901 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
902 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
903 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
904 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
905 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
906 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
907 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 908 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
909 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
910 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 911 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
912 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
913 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
914 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
915 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
916 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
917 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
918 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
919 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
920 | MOD_VEX_0FAE_REG_2, |
921 | MOD_VEX_0FAE_REG_3, | |
922 | MOD_VEX_0FD7_PREFIX_2, | |
923 | MOD_VEX_0FE7_PREFIX_2, | |
924 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
925 | MOD_VEX_0F381A_PREFIX_2, |
926 | MOD_VEX_0F382A_PREFIX_2, | |
927 | MOD_VEX_0F382C_PREFIX_2, | |
928 | MOD_VEX_0F382D_PREFIX_2, | |
929 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
930 | MOD_VEX_0F382F_PREFIX_2, |
931 | MOD_VEX_0F385A_PREFIX_2, | |
932 | MOD_VEX_0F388C_PREFIX_2, | |
933 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
934 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
935 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
936 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
937 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
938 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
939 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
940 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
941 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e L |
942 | |
943 | MOD_EVEX_0F10_PREFIX_1, | |
944 | MOD_EVEX_0F10_PREFIX_3, | |
945 | MOD_EVEX_0F11_PREFIX_1, | |
946 | MOD_EVEX_0F11_PREFIX_3, | |
947 | MOD_EVEX_0F12_PREFIX_0, | |
948 | MOD_EVEX_0F16_PREFIX_0, | |
949 | MOD_EVEX_0F38C6_REG_1, | |
950 | MOD_EVEX_0F38C6_REG_2, | |
951 | MOD_EVEX_0F38C6_REG_5, | |
952 | MOD_EVEX_0F38C6_REG_6, | |
953 | MOD_EVEX_0F38C7_REG_1, | |
954 | MOD_EVEX_0F38C7_REG_2, | |
955 | MOD_EVEX_0F38C7_REG_5, | |
956 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 957 | }; |
1ceb70f8 | 958 | |
51e7da1b L |
959 | enum |
960 | { | |
42164a71 L |
961 | RM_C6_REG_7 = 0, |
962 | RM_C7_REG_7, | |
963 | RM_0F01_REG_0, | |
3873ba12 L |
964 | RM_0F01_REG_1, |
965 | RM_0F01_REG_2, | |
966 | RM_0F01_REG_3, | |
8eab4136 | 967 | RM_0F01_REG_5, |
3873ba12 | 968 | RM_0F01_REG_7, |
603555e5 | 969 | RM_0F1E_MOD_3_REG_7, |
3873ba12 L |
970 | RM_0FAE_REG_6, |
971 | RM_0FAE_REG_7 | |
51e7da1b | 972 | }; |
1ceb70f8 | 973 | |
51e7da1b L |
974 | enum |
975 | { | |
976 | PREFIX_90 = 0, | |
603555e5 | 977 | PREFIX_MOD_0_0F01_REG_5, |
2234eee6 | 978 | PREFIX_MOD_3_0F01_REG_5_RM_0, |
603555e5 | 979 | PREFIX_MOD_3_0F01_REG_5_RM_2, |
3233d7d0 | 980 | PREFIX_0F09, |
3873ba12 L |
981 | PREFIX_0F10, |
982 | PREFIX_0F11, | |
983 | PREFIX_0F12, | |
984 | PREFIX_0F16, | |
7e8b059b L |
985 | PREFIX_0F1A, |
986 | PREFIX_0F1B, | |
c48935d7 | 987 | PREFIX_0F1C, |
603555e5 | 988 | PREFIX_0F1E, |
3873ba12 L |
989 | PREFIX_0F2A, |
990 | PREFIX_0F2B, | |
991 | PREFIX_0F2C, | |
992 | PREFIX_0F2D, | |
993 | PREFIX_0F2E, | |
994 | PREFIX_0F2F, | |
995 | PREFIX_0F51, | |
996 | PREFIX_0F52, | |
997 | PREFIX_0F53, | |
998 | PREFIX_0F58, | |
999 | PREFIX_0F59, | |
1000 | PREFIX_0F5A, | |
1001 | PREFIX_0F5B, | |
1002 | PREFIX_0F5C, | |
1003 | PREFIX_0F5D, | |
1004 | PREFIX_0F5E, | |
1005 | PREFIX_0F5F, | |
1006 | PREFIX_0F60, | |
1007 | PREFIX_0F61, | |
1008 | PREFIX_0F62, | |
1009 | PREFIX_0F6C, | |
1010 | PREFIX_0F6D, | |
1011 | PREFIX_0F6F, | |
1012 | PREFIX_0F70, | |
1013 | PREFIX_0F73_REG_3, | |
1014 | PREFIX_0F73_REG_7, | |
1015 | PREFIX_0F78, | |
1016 | PREFIX_0F79, | |
1017 | PREFIX_0F7C, | |
1018 | PREFIX_0F7D, | |
1019 | PREFIX_0F7E, | |
1020 | PREFIX_0F7F, | |
c7b8aa3a L |
1021 | PREFIX_0FAE_REG_0, |
1022 | PREFIX_0FAE_REG_1, | |
1023 | PREFIX_0FAE_REG_2, | |
1024 | PREFIX_0FAE_REG_3, | |
6b40c462 L |
1025 | PREFIX_MOD_0_0FAE_REG_4, |
1026 | PREFIX_MOD_3_0FAE_REG_4, | |
603555e5 | 1027 | PREFIX_MOD_0_0FAE_REG_5, |
2234eee6 | 1028 | PREFIX_MOD_3_0FAE_REG_5, |
de89d0a3 IT |
1029 | PREFIX_MOD_0_0FAE_REG_6, |
1030 | PREFIX_MOD_1_0FAE_REG_6, | |
963f3586 | 1031 | PREFIX_0FAE_REG_7, |
3873ba12 | 1032 | PREFIX_0FB8, |
f12dc422 | 1033 | PREFIX_0FBC, |
3873ba12 L |
1034 | PREFIX_0FBD, |
1035 | PREFIX_0FC2, | |
a8484f96 | 1036 | PREFIX_MOD_0_0FC3, |
f24bcbaa L |
1037 | PREFIX_MOD_0_0FC7_REG_6, |
1038 | PREFIX_MOD_3_0FC7_REG_6, | |
1039 | PREFIX_MOD_3_0FC7_REG_7, | |
3873ba12 L |
1040 | PREFIX_0FD0, |
1041 | PREFIX_0FD6, | |
1042 | PREFIX_0FE6, | |
1043 | PREFIX_0FE7, | |
1044 | PREFIX_0FF0, | |
1045 | PREFIX_0FF7, | |
1046 | PREFIX_0F3810, | |
1047 | PREFIX_0F3814, | |
1048 | PREFIX_0F3815, | |
1049 | PREFIX_0F3817, | |
1050 | PREFIX_0F3820, | |
1051 | PREFIX_0F3821, | |
1052 | PREFIX_0F3822, | |
1053 | PREFIX_0F3823, | |
1054 | PREFIX_0F3824, | |
1055 | PREFIX_0F3825, | |
1056 | PREFIX_0F3828, | |
1057 | PREFIX_0F3829, | |
1058 | PREFIX_0F382A, | |
1059 | PREFIX_0F382B, | |
1060 | PREFIX_0F3830, | |
1061 | PREFIX_0F3831, | |
1062 | PREFIX_0F3832, | |
1063 | PREFIX_0F3833, | |
1064 | PREFIX_0F3834, | |
1065 | PREFIX_0F3835, | |
1066 | PREFIX_0F3837, | |
1067 | PREFIX_0F3838, | |
1068 | PREFIX_0F3839, | |
1069 | PREFIX_0F383A, | |
1070 | PREFIX_0F383B, | |
1071 | PREFIX_0F383C, | |
1072 | PREFIX_0F383D, | |
1073 | PREFIX_0F383E, | |
1074 | PREFIX_0F383F, | |
1075 | PREFIX_0F3840, | |
1076 | PREFIX_0F3841, | |
1077 | PREFIX_0F3880, | |
1078 | PREFIX_0F3881, | |
6c30d220 | 1079 | PREFIX_0F3882, |
a0046408 L |
1080 | PREFIX_0F38C8, |
1081 | PREFIX_0F38C9, | |
1082 | PREFIX_0F38CA, | |
1083 | PREFIX_0F38CB, | |
1084 | PREFIX_0F38CC, | |
1085 | PREFIX_0F38CD, | |
48521003 | 1086 | PREFIX_0F38CF, |
3873ba12 L |
1087 | PREFIX_0F38DB, |
1088 | PREFIX_0F38DC, | |
1089 | PREFIX_0F38DD, | |
1090 | PREFIX_0F38DE, | |
1091 | PREFIX_0F38DF, | |
1092 | PREFIX_0F38F0, | |
1093 | PREFIX_0F38F1, | |
603555e5 | 1094 | PREFIX_0F38F5, |
e2e1fcde | 1095 | PREFIX_0F38F6, |
c0a30a9f L |
1096 | PREFIX_0F38F8, |
1097 | PREFIX_0F38F9, | |
3873ba12 L |
1098 | PREFIX_0F3A08, |
1099 | PREFIX_0F3A09, | |
1100 | PREFIX_0F3A0A, | |
1101 | PREFIX_0F3A0B, | |
1102 | PREFIX_0F3A0C, | |
1103 | PREFIX_0F3A0D, | |
1104 | PREFIX_0F3A0E, | |
1105 | PREFIX_0F3A14, | |
1106 | PREFIX_0F3A15, | |
1107 | PREFIX_0F3A16, | |
1108 | PREFIX_0F3A17, | |
1109 | PREFIX_0F3A20, | |
1110 | PREFIX_0F3A21, | |
1111 | PREFIX_0F3A22, | |
1112 | PREFIX_0F3A40, | |
1113 | PREFIX_0F3A41, | |
1114 | PREFIX_0F3A42, | |
1115 | PREFIX_0F3A44, | |
1116 | PREFIX_0F3A60, | |
1117 | PREFIX_0F3A61, | |
1118 | PREFIX_0F3A62, | |
1119 | PREFIX_0F3A63, | |
a0046408 | 1120 | PREFIX_0F3ACC, |
48521003 IT |
1121 | PREFIX_0F3ACE, |
1122 | PREFIX_0F3ACF, | |
3873ba12 | 1123 | PREFIX_0F3ADF, |
592a252b L |
1124 | PREFIX_VEX_0F10, |
1125 | PREFIX_VEX_0F11, | |
1126 | PREFIX_VEX_0F12, | |
1127 | PREFIX_VEX_0F16, | |
1128 | PREFIX_VEX_0F2A, | |
1129 | PREFIX_VEX_0F2C, | |
1130 | PREFIX_VEX_0F2D, | |
1131 | PREFIX_VEX_0F2E, | |
1132 | PREFIX_VEX_0F2F, | |
43234a1e L |
1133 | PREFIX_VEX_0F41, |
1134 | PREFIX_VEX_0F42, | |
1135 | PREFIX_VEX_0F44, | |
1136 | PREFIX_VEX_0F45, | |
1137 | PREFIX_VEX_0F46, | |
1138 | PREFIX_VEX_0F47, | |
1ba585e8 | 1139 | PREFIX_VEX_0F4A, |
43234a1e | 1140 | PREFIX_VEX_0F4B, |
592a252b L |
1141 | PREFIX_VEX_0F51, |
1142 | PREFIX_VEX_0F52, | |
1143 | PREFIX_VEX_0F53, | |
1144 | PREFIX_VEX_0F58, | |
1145 | PREFIX_VEX_0F59, | |
1146 | PREFIX_VEX_0F5A, | |
1147 | PREFIX_VEX_0F5B, | |
1148 | PREFIX_VEX_0F5C, | |
1149 | PREFIX_VEX_0F5D, | |
1150 | PREFIX_VEX_0F5E, | |
1151 | PREFIX_VEX_0F5F, | |
1152 | PREFIX_VEX_0F60, | |
1153 | PREFIX_VEX_0F61, | |
1154 | PREFIX_VEX_0F62, | |
1155 | PREFIX_VEX_0F63, | |
1156 | PREFIX_VEX_0F64, | |
1157 | PREFIX_VEX_0F65, | |
1158 | PREFIX_VEX_0F66, | |
1159 | PREFIX_VEX_0F67, | |
1160 | PREFIX_VEX_0F68, | |
1161 | PREFIX_VEX_0F69, | |
1162 | PREFIX_VEX_0F6A, | |
1163 | PREFIX_VEX_0F6B, | |
1164 | PREFIX_VEX_0F6C, | |
1165 | PREFIX_VEX_0F6D, | |
1166 | PREFIX_VEX_0F6E, | |
1167 | PREFIX_VEX_0F6F, | |
1168 | PREFIX_VEX_0F70, | |
1169 | PREFIX_VEX_0F71_REG_2, | |
1170 | PREFIX_VEX_0F71_REG_4, | |
1171 | PREFIX_VEX_0F71_REG_6, | |
1172 | PREFIX_VEX_0F72_REG_2, | |
1173 | PREFIX_VEX_0F72_REG_4, | |
1174 | PREFIX_VEX_0F72_REG_6, | |
1175 | PREFIX_VEX_0F73_REG_2, | |
1176 | PREFIX_VEX_0F73_REG_3, | |
1177 | PREFIX_VEX_0F73_REG_6, | |
1178 | PREFIX_VEX_0F73_REG_7, | |
1179 | PREFIX_VEX_0F74, | |
1180 | PREFIX_VEX_0F75, | |
1181 | PREFIX_VEX_0F76, | |
1182 | PREFIX_VEX_0F77, | |
1183 | PREFIX_VEX_0F7C, | |
1184 | PREFIX_VEX_0F7D, | |
1185 | PREFIX_VEX_0F7E, | |
1186 | PREFIX_VEX_0F7F, | |
43234a1e L |
1187 | PREFIX_VEX_0F90, |
1188 | PREFIX_VEX_0F91, | |
1189 | PREFIX_VEX_0F92, | |
1190 | PREFIX_VEX_0F93, | |
1191 | PREFIX_VEX_0F98, | |
1ba585e8 | 1192 | PREFIX_VEX_0F99, |
592a252b L |
1193 | PREFIX_VEX_0FC2, |
1194 | PREFIX_VEX_0FC4, | |
1195 | PREFIX_VEX_0FC5, | |
1196 | PREFIX_VEX_0FD0, | |
1197 | PREFIX_VEX_0FD1, | |
1198 | PREFIX_VEX_0FD2, | |
1199 | PREFIX_VEX_0FD3, | |
1200 | PREFIX_VEX_0FD4, | |
1201 | PREFIX_VEX_0FD5, | |
1202 | PREFIX_VEX_0FD6, | |
1203 | PREFIX_VEX_0FD7, | |
1204 | PREFIX_VEX_0FD8, | |
1205 | PREFIX_VEX_0FD9, | |
1206 | PREFIX_VEX_0FDA, | |
1207 | PREFIX_VEX_0FDB, | |
1208 | PREFIX_VEX_0FDC, | |
1209 | PREFIX_VEX_0FDD, | |
1210 | PREFIX_VEX_0FDE, | |
1211 | PREFIX_VEX_0FDF, | |
1212 | PREFIX_VEX_0FE0, | |
1213 | PREFIX_VEX_0FE1, | |
1214 | PREFIX_VEX_0FE2, | |
1215 | PREFIX_VEX_0FE3, | |
1216 | PREFIX_VEX_0FE4, | |
1217 | PREFIX_VEX_0FE5, | |
1218 | PREFIX_VEX_0FE6, | |
1219 | PREFIX_VEX_0FE7, | |
1220 | PREFIX_VEX_0FE8, | |
1221 | PREFIX_VEX_0FE9, | |
1222 | PREFIX_VEX_0FEA, | |
1223 | PREFIX_VEX_0FEB, | |
1224 | PREFIX_VEX_0FEC, | |
1225 | PREFIX_VEX_0FED, | |
1226 | PREFIX_VEX_0FEE, | |
1227 | PREFIX_VEX_0FEF, | |
1228 | PREFIX_VEX_0FF0, | |
1229 | PREFIX_VEX_0FF1, | |
1230 | PREFIX_VEX_0FF2, | |
1231 | PREFIX_VEX_0FF3, | |
1232 | PREFIX_VEX_0FF4, | |
1233 | PREFIX_VEX_0FF5, | |
1234 | PREFIX_VEX_0FF6, | |
1235 | PREFIX_VEX_0FF7, | |
1236 | PREFIX_VEX_0FF8, | |
1237 | PREFIX_VEX_0FF9, | |
1238 | PREFIX_VEX_0FFA, | |
1239 | PREFIX_VEX_0FFB, | |
1240 | PREFIX_VEX_0FFC, | |
1241 | PREFIX_VEX_0FFD, | |
1242 | PREFIX_VEX_0FFE, | |
1243 | PREFIX_VEX_0F3800, | |
1244 | PREFIX_VEX_0F3801, | |
1245 | PREFIX_VEX_0F3802, | |
1246 | PREFIX_VEX_0F3803, | |
1247 | PREFIX_VEX_0F3804, | |
1248 | PREFIX_VEX_0F3805, | |
1249 | PREFIX_VEX_0F3806, | |
1250 | PREFIX_VEX_0F3807, | |
1251 | PREFIX_VEX_0F3808, | |
1252 | PREFIX_VEX_0F3809, | |
1253 | PREFIX_VEX_0F380A, | |
1254 | PREFIX_VEX_0F380B, | |
1255 | PREFIX_VEX_0F380C, | |
1256 | PREFIX_VEX_0F380D, | |
1257 | PREFIX_VEX_0F380E, | |
1258 | PREFIX_VEX_0F380F, | |
1259 | PREFIX_VEX_0F3813, | |
6c30d220 | 1260 | PREFIX_VEX_0F3816, |
592a252b L |
1261 | PREFIX_VEX_0F3817, |
1262 | PREFIX_VEX_0F3818, | |
1263 | PREFIX_VEX_0F3819, | |
1264 | PREFIX_VEX_0F381A, | |
1265 | PREFIX_VEX_0F381C, | |
1266 | PREFIX_VEX_0F381D, | |
1267 | PREFIX_VEX_0F381E, | |
1268 | PREFIX_VEX_0F3820, | |
1269 | PREFIX_VEX_0F3821, | |
1270 | PREFIX_VEX_0F3822, | |
1271 | PREFIX_VEX_0F3823, | |
1272 | PREFIX_VEX_0F3824, | |
1273 | PREFIX_VEX_0F3825, | |
1274 | PREFIX_VEX_0F3828, | |
1275 | PREFIX_VEX_0F3829, | |
1276 | PREFIX_VEX_0F382A, | |
1277 | PREFIX_VEX_0F382B, | |
1278 | PREFIX_VEX_0F382C, | |
1279 | PREFIX_VEX_0F382D, | |
1280 | PREFIX_VEX_0F382E, | |
1281 | PREFIX_VEX_0F382F, | |
1282 | PREFIX_VEX_0F3830, | |
1283 | PREFIX_VEX_0F3831, | |
1284 | PREFIX_VEX_0F3832, | |
1285 | PREFIX_VEX_0F3833, | |
1286 | PREFIX_VEX_0F3834, | |
1287 | PREFIX_VEX_0F3835, | |
6c30d220 | 1288 | PREFIX_VEX_0F3836, |
592a252b L |
1289 | PREFIX_VEX_0F3837, |
1290 | PREFIX_VEX_0F3838, | |
1291 | PREFIX_VEX_0F3839, | |
1292 | PREFIX_VEX_0F383A, | |
1293 | PREFIX_VEX_0F383B, | |
1294 | PREFIX_VEX_0F383C, | |
1295 | PREFIX_VEX_0F383D, | |
1296 | PREFIX_VEX_0F383E, | |
1297 | PREFIX_VEX_0F383F, | |
1298 | PREFIX_VEX_0F3840, | |
1299 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1300 | PREFIX_VEX_0F3845, |
1301 | PREFIX_VEX_0F3846, | |
1302 | PREFIX_VEX_0F3847, | |
1303 | PREFIX_VEX_0F3858, | |
1304 | PREFIX_VEX_0F3859, | |
1305 | PREFIX_VEX_0F385A, | |
1306 | PREFIX_VEX_0F3878, | |
1307 | PREFIX_VEX_0F3879, | |
1308 | PREFIX_VEX_0F388C, | |
1309 | PREFIX_VEX_0F388E, | |
1310 | PREFIX_VEX_0F3890, | |
1311 | PREFIX_VEX_0F3891, | |
1312 | PREFIX_VEX_0F3892, | |
1313 | PREFIX_VEX_0F3893, | |
592a252b L |
1314 | PREFIX_VEX_0F3896, |
1315 | PREFIX_VEX_0F3897, | |
1316 | PREFIX_VEX_0F3898, | |
1317 | PREFIX_VEX_0F3899, | |
1318 | PREFIX_VEX_0F389A, | |
1319 | PREFIX_VEX_0F389B, | |
1320 | PREFIX_VEX_0F389C, | |
1321 | PREFIX_VEX_0F389D, | |
1322 | PREFIX_VEX_0F389E, | |
1323 | PREFIX_VEX_0F389F, | |
1324 | PREFIX_VEX_0F38A6, | |
1325 | PREFIX_VEX_0F38A7, | |
1326 | PREFIX_VEX_0F38A8, | |
1327 | PREFIX_VEX_0F38A9, | |
1328 | PREFIX_VEX_0F38AA, | |
1329 | PREFIX_VEX_0F38AB, | |
1330 | PREFIX_VEX_0F38AC, | |
1331 | PREFIX_VEX_0F38AD, | |
1332 | PREFIX_VEX_0F38AE, | |
1333 | PREFIX_VEX_0F38AF, | |
1334 | PREFIX_VEX_0F38B6, | |
1335 | PREFIX_VEX_0F38B7, | |
1336 | PREFIX_VEX_0F38B8, | |
1337 | PREFIX_VEX_0F38B9, | |
1338 | PREFIX_VEX_0F38BA, | |
1339 | PREFIX_VEX_0F38BB, | |
1340 | PREFIX_VEX_0F38BC, | |
1341 | PREFIX_VEX_0F38BD, | |
1342 | PREFIX_VEX_0F38BE, | |
1343 | PREFIX_VEX_0F38BF, | |
48521003 | 1344 | PREFIX_VEX_0F38CF, |
592a252b L |
1345 | PREFIX_VEX_0F38DB, |
1346 | PREFIX_VEX_0F38DC, | |
1347 | PREFIX_VEX_0F38DD, | |
1348 | PREFIX_VEX_0F38DE, | |
1349 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1350 | PREFIX_VEX_0F38F2, |
1351 | PREFIX_VEX_0F38F3_REG_1, | |
1352 | PREFIX_VEX_0F38F3_REG_2, | |
1353 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1354 | PREFIX_VEX_0F38F5, |
1355 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1356 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1357 | PREFIX_VEX_0F3A00, |
1358 | PREFIX_VEX_0F3A01, | |
1359 | PREFIX_VEX_0F3A02, | |
592a252b L |
1360 | PREFIX_VEX_0F3A04, |
1361 | PREFIX_VEX_0F3A05, | |
1362 | PREFIX_VEX_0F3A06, | |
1363 | PREFIX_VEX_0F3A08, | |
1364 | PREFIX_VEX_0F3A09, | |
1365 | PREFIX_VEX_0F3A0A, | |
1366 | PREFIX_VEX_0F3A0B, | |
1367 | PREFIX_VEX_0F3A0C, | |
1368 | PREFIX_VEX_0F3A0D, | |
1369 | PREFIX_VEX_0F3A0E, | |
1370 | PREFIX_VEX_0F3A0F, | |
1371 | PREFIX_VEX_0F3A14, | |
1372 | PREFIX_VEX_0F3A15, | |
1373 | PREFIX_VEX_0F3A16, | |
1374 | PREFIX_VEX_0F3A17, | |
1375 | PREFIX_VEX_0F3A18, | |
1376 | PREFIX_VEX_0F3A19, | |
1377 | PREFIX_VEX_0F3A1D, | |
1378 | PREFIX_VEX_0F3A20, | |
1379 | PREFIX_VEX_0F3A21, | |
1380 | PREFIX_VEX_0F3A22, | |
43234a1e | 1381 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1382 | PREFIX_VEX_0F3A31, |
43234a1e | 1383 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1384 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1385 | PREFIX_VEX_0F3A38, |
1386 | PREFIX_VEX_0F3A39, | |
592a252b L |
1387 | PREFIX_VEX_0F3A40, |
1388 | PREFIX_VEX_0F3A41, | |
1389 | PREFIX_VEX_0F3A42, | |
1390 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1391 | PREFIX_VEX_0F3A46, |
592a252b L |
1392 | PREFIX_VEX_0F3A48, |
1393 | PREFIX_VEX_0F3A49, | |
1394 | PREFIX_VEX_0F3A4A, | |
1395 | PREFIX_VEX_0F3A4B, | |
1396 | PREFIX_VEX_0F3A4C, | |
1397 | PREFIX_VEX_0F3A5C, | |
1398 | PREFIX_VEX_0F3A5D, | |
1399 | PREFIX_VEX_0F3A5E, | |
1400 | PREFIX_VEX_0F3A5F, | |
1401 | PREFIX_VEX_0F3A60, | |
1402 | PREFIX_VEX_0F3A61, | |
1403 | PREFIX_VEX_0F3A62, | |
1404 | PREFIX_VEX_0F3A63, | |
1405 | PREFIX_VEX_0F3A68, | |
1406 | PREFIX_VEX_0F3A69, | |
1407 | PREFIX_VEX_0F3A6A, | |
1408 | PREFIX_VEX_0F3A6B, | |
1409 | PREFIX_VEX_0F3A6C, | |
1410 | PREFIX_VEX_0F3A6D, | |
1411 | PREFIX_VEX_0F3A6E, | |
1412 | PREFIX_VEX_0F3A6F, | |
1413 | PREFIX_VEX_0F3A78, | |
1414 | PREFIX_VEX_0F3A79, | |
1415 | PREFIX_VEX_0F3A7A, | |
1416 | PREFIX_VEX_0F3A7B, | |
1417 | PREFIX_VEX_0F3A7C, | |
1418 | PREFIX_VEX_0F3A7D, | |
1419 | PREFIX_VEX_0F3A7E, | |
1420 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1421 | PREFIX_VEX_0F3ACE, |
1422 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1423 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1424 | PREFIX_VEX_0F3AF0, |
1425 | ||
1426 | PREFIX_EVEX_0F10, | |
1427 | PREFIX_EVEX_0F11, | |
1428 | PREFIX_EVEX_0F12, | |
1429 | PREFIX_EVEX_0F13, | |
1430 | PREFIX_EVEX_0F14, | |
1431 | PREFIX_EVEX_0F15, | |
1432 | PREFIX_EVEX_0F16, | |
1433 | PREFIX_EVEX_0F17, | |
1434 | PREFIX_EVEX_0F28, | |
1435 | PREFIX_EVEX_0F29, | |
1436 | PREFIX_EVEX_0F2A, | |
1437 | PREFIX_EVEX_0F2B, | |
1438 | PREFIX_EVEX_0F2C, | |
1439 | PREFIX_EVEX_0F2D, | |
1440 | PREFIX_EVEX_0F2E, | |
1441 | PREFIX_EVEX_0F2F, | |
1442 | PREFIX_EVEX_0F51, | |
90a915bf IT |
1443 | PREFIX_EVEX_0F54, |
1444 | PREFIX_EVEX_0F55, | |
1445 | PREFIX_EVEX_0F56, | |
1446 | PREFIX_EVEX_0F57, | |
43234a1e L |
1447 | PREFIX_EVEX_0F58, |
1448 | PREFIX_EVEX_0F59, | |
1449 | PREFIX_EVEX_0F5A, | |
1450 | PREFIX_EVEX_0F5B, | |
1451 | PREFIX_EVEX_0F5C, | |
1452 | PREFIX_EVEX_0F5D, | |
1453 | PREFIX_EVEX_0F5E, | |
1454 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1455 | PREFIX_EVEX_0F60, |
1456 | PREFIX_EVEX_0F61, | |
43234a1e | 1457 | PREFIX_EVEX_0F62, |
1ba585e8 IT |
1458 | PREFIX_EVEX_0F63, |
1459 | PREFIX_EVEX_0F64, | |
1460 | PREFIX_EVEX_0F65, | |
43234a1e | 1461 | PREFIX_EVEX_0F66, |
1ba585e8 IT |
1462 | PREFIX_EVEX_0F67, |
1463 | PREFIX_EVEX_0F68, | |
1464 | PREFIX_EVEX_0F69, | |
43234a1e | 1465 | PREFIX_EVEX_0F6A, |
1ba585e8 | 1466 | PREFIX_EVEX_0F6B, |
43234a1e L |
1467 | PREFIX_EVEX_0F6C, |
1468 | PREFIX_EVEX_0F6D, | |
1469 | PREFIX_EVEX_0F6E, | |
1470 | PREFIX_EVEX_0F6F, | |
1471 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1472 | PREFIX_EVEX_0F71_REG_2, |
1473 | PREFIX_EVEX_0F71_REG_4, | |
1474 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1475 | PREFIX_EVEX_0F72_REG_0, |
1476 | PREFIX_EVEX_0F72_REG_1, | |
1477 | PREFIX_EVEX_0F72_REG_2, | |
1478 | PREFIX_EVEX_0F72_REG_4, | |
1479 | PREFIX_EVEX_0F72_REG_6, | |
1480 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1481 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1482 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1483 | PREFIX_EVEX_0F73_REG_7, |
1484 | PREFIX_EVEX_0F74, | |
1485 | PREFIX_EVEX_0F75, | |
43234a1e L |
1486 | PREFIX_EVEX_0F76, |
1487 | PREFIX_EVEX_0F78, | |
1488 | PREFIX_EVEX_0F79, | |
1489 | PREFIX_EVEX_0F7A, | |
1490 | PREFIX_EVEX_0F7B, | |
1491 | PREFIX_EVEX_0F7E, | |
1492 | PREFIX_EVEX_0F7F, | |
1493 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1494 | PREFIX_EVEX_0FC4, |
1495 | PREFIX_EVEX_0FC5, | |
43234a1e | 1496 | PREFIX_EVEX_0FC6, |
1ba585e8 | 1497 | PREFIX_EVEX_0FD1, |
43234a1e L |
1498 | PREFIX_EVEX_0FD2, |
1499 | PREFIX_EVEX_0FD3, | |
1500 | PREFIX_EVEX_0FD4, | |
1ba585e8 | 1501 | PREFIX_EVEX_0FD5, |
43234a1e | 1502 | PREFIX_EVEX_0FD6, |
1ba585e8 IT |
1503 | PREFIX_EVEX_0FD8, |
1504 | PREFIX_EVEX_0FD9, | |
1505 | PREFIX_EVEX_0FDA, | |
43234a1e | 1506 | PREFIX_EVEX_0FDB, |
1ba585e8 IT |
1507 | PREFIX_EVEX_0FDC, |
1508 | PREFIX_EVEX_0FDD, | |
1509 | PREFIX_EVEX_0FDE, | |
43234a1e | 1510 | PREFIX_EVEX_0FDF, |
1ba585e8 IT |
1511 | PREFIX_EVEX_0FE0, |
1512 | PREFIX_EVEX_0FE1, | |
43234a1e | 1513 | PREFIX_EVEX_0FE2, |
1ba585e8 IT |
1514 | PREFIX_EVEX_0FE3, |
1515 | PREFIX_EVEX_0FE4, | |
1516 | PREFIX_EVEX_0FE5, | |
43234a1e L |
1517 | PREFIX_EVEX_0FE6, |
1518 | PREFIX_EVEX_0FE7, | |
1ba585e8 IT |
1519 | PREFIX_EVEX_0FE8, |
1520 | PREFIX_EVEX_0FE9, | |
1521 | PREFIX_EVEX_0FEA, | |
43234a1e | 1522 | PREFIX_EVEX_0FEB, |
1ba585e8 IT |
1523 | PREFIX_EVEX_0FEC, |
1524 | PREFIX_EVEX_0FED, | |
1525 | PREFIX_EVEX_0FEE, | |
43234a1e | 1526 | PREFIX_EVEX_0FEF, |
1ba585e8 | 1527 | PREFIX_EVEX_0FF1, |
43234a1e L |
1528 | PREFIX_EVEX_0FF2, |
1529 | PREFIX_EVEX_0FF3, | |
1530 | PREFIX_EVEX_0FF4, | |
1ba585e8 IT |
1531 | PREFIX_EVEX_0FF5, |
1532 | PREFIX_EVEX_0FF6, | |
1533 | PREFIX_EVEX_0FF8, | |
1534 | PREFIX_EVEX_0FF9, | |
43234a1e L |
1535 | PREFIX_EVEX_0FFA, |
1536 | PREFIX_EVEX_0FFB, | |
1ba585e8 IT |
1537 | PREFIX_EVEX_0FFC, |
1538 | PREFIX_EVEX_0FFD, | |
43234a1e | 1539 | PREFIX_EVEX_0FFE, |
1ba585e8 IT |
1540 | PREFIX_EVEX_0F3800, |
1541 | PREFIX_EVEX_0F3804, | |
1542 | PREFIX_EVEX_0F380B, | |
43234a1e L |
1543 | PREFIX_EVEX_0F380C, |
1544 | PREFIX_EVEX_0F380D, | |
1ba585e8 | 1545 | PREFIX_EVEX_0F3810, |
43234a1e L |
1546 | PREFIX_EVEX_0F3811, |
1547 | PREFIX_EVEX_0F3812, | |
1548 | PREFIX_EVEX_0F3813, | |
1549 | PREFIX_EVEX_0F3814, | |
1550 | PREFIX_EVEX_0F3815, | |
1551 | PREFIX_EVEX_0F3816, | |
1552 | PREFIX_EVEX_0F3818, | |
1553 | PREFIX_EVEX_0F3819, | |
1554 | PREFIX_EVEX_0F381A, | |
1555 | PREFIX_EVEX_0F381B, | |
1ba585e8 IT |
1556 | PREFIX_EVEX_0F381C, |
1557 | PREFIX_EVEX_0F381D, | |
43234a1e L |
1558 | PREFIX_EVEX_0F381E, |
1559 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1560 | PREFIX_EVEX_0F3820, |
43234a1e L |
1561 | PREFIX_EVEX_0F3821, |
1562 | PREFIX_EVEX_0F3822, | |
1563 | PREFIX_EVEX_0F3823, | |
1564 | PREFIX_EVEX_0F3824, | |
1565 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1566 | PREFIX_EVEX_0F3826, |
43234a1e L |
1567 | PREFIX_EVEX_0F3827, |
1568 | PREFIX_EVEX_0F3828, | |
1569 | PREFIX_EVEX_0F3829, | |
1570 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1571 | PREFIX_EVEX_0F382B, |
43234a1e L |
1572 | PREFIX_EVEX_0F382C, |
1573 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1574 | PREFIX_EVEX_0F3830, |
43234a1e L |
1575 | PREFIX_EVEX_0F3831, |
1576 | PREFIX_EVEX_0F3832, | |
1577 | PREFIX_EVEX_0F3833, | |
1578 | PREFIX_EVEX_0F3834, | |
1579 | PREFIX_EVEX_0F3835, | |
1580 | PREFIX_EVEX_0F3836, | |
1581 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1582 | PREFIX_EVEX_0F3838, |
43234a1e L |
1583 | PREFIX_EVEX_0F3839, |
1584 | PREFIX_EVEX_0F383A, | |
1585 | PREFIX_EVEX_0F383B, | |
1ba585e8 | 1586 | PREFIX_EVEX_0F383C, |
43234a1e | 1587 | PREFIX_EVEX_0F383D, |
1ba585e8 | 1588 | PREFIX_EVEX_0F383E, |
43234a1e L |
1589 | PREFIX_EVEX_0F383F, |
1590 | PREFIX_EVEX_0F3840, | |
1591 | PREFIX_EVEX_0F3842, | |
1592 | PREFIX_EVEX_0F3843, | |
1593 | PREFIX_EVEX_0F3844, | |
1594 | PREFIX_EVEX_0F3845, | |
1595 | PREFIX_EVEX_0F3846, | |
1596 | PREFIX_EVEX_0F3847, | |
1597 | PREFIX_EVEX_0F384C, | |
1598 | PREFIX_EVEX_0F384D, | |
1599 | PREFIX_EVEX_0F384E, | |
1600 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1601 | PREFIX_EVEX_0F3850, |
1602 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1603 | PREFIX_EVEX_0F3852, |
1604 | PREFIX_EVEX_0F3853, | |
ee6872be | 1605 | PREFIX_EVEX_0F3854, |
620214f7 | 1606 | PREFIX_EVEX_0F3855, |
43234a1e L |
1607 | PREFIX_EVEX_0F3858, |
1608 | PREFIX_EVEX_0F3859, | |
1609 | PREFIX_EVEX_0F385A, | |
1610 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1611 | PREFIX_EVEX_0F3862, |
1612 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1613 | PREFIX_EVEX_0F3864, |
1614 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1615 | PREFIX_EVEX_0F3866, |
53467f57 IT |
1616 | PREFIX_EVEX_0F3870, |
1617 | PREFIX_EVEX_0F3871, | |
1618 | PREFIX_EVEX_0F3872, | |
1619 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1620 | PREFIX_EVEX_0F3875, |
43234a1e L |
1621 | PREFIX_EVEX_0F3876, |
1622 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1623 | PREFIX_EVEX_0F3878, |
1624 | PREFIX_EVEX_0F3879, | |
1625 | PREFIX_EVEX_0F387A, | |
1626 | PREFIX_EVEX_0F387B, | |
43234a1e | 1627 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1628 | PREFIX_EVEX_0F387D, |
43234a1e L |
1629 | PREFIX_EVEX_0F387E, |
1630 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1631 | PREFIX_EVEX_0F3883, |
43234a1e L |
1632 | PREFIX_EVEX_0F3888, |
1633 | PREFIX_EVEX_0F3889, | |
1634 | PREFIX_EVEX_0F388A, | |
1635 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1636 | PREFIX_EVEX_0F388D, |
ee6872be | 1637 | PREFIX_EVEX_0F388F, |
43234a1e L |
1638 | PREFIX_EVEX_0F3890, |
1639 | PREFIX_EVEX_0F3891, | |
1640 | PREFIX_EVEX_0F3892, | |
1641 | PREFIX_EVEX_0F3893, | |
1642 | PREFIX_EVEX_0F3896, | |
1643 | PREFIX_EVEX_0F3897, | |
1644 | PREFIX_EVEX_0F3898, | |
1645 | PREFIX_EVEX_0F3899, | |
1646 | PREFIX_EVEX_0F389A, | |
1647 | PREFIX_EVEX_0F389B, | |
1648 | PREFIX_EVEX_0F389C, | |
1649 | PREFIX_EVEX_0F389D, | |
1650 | PREFIX_EVEX_0F389E, | |
1651 | PREFIX_EVEX_0F389F, | |
1652 | PREFIX_EVEX_0F38A0, | |
1653 | PREFIX_EVEX_0F38A1, | |
1654 | PREFIX_EVEX_0F38A2, | |
1655 | PREFIX_EVEX_0F38A3, | |
1656 | PREFIX_EVEX_0F38A6, | |
1657 | PREFIX_EVEX_0F38A7, | |
1658 | PREFIX_EVEX_0F38A8, | |
1659 | PREFIX_EVEX_0F38A9, | |
1660 | PREFIX_EVEX_0F38AA, | |
1661 | PREFIX_EVEX_0F38AB, | |
1662 | PREFIX_EVEX_0F38AC, | |
1663 | PREFIX_EVEX_0F38AD, | |
1664 | PREFIX_EVEX_0F38AE, | |
1665 | PREFIX_EVEX_0F38AF, | |
2cc1b5aa IT |
1666 | PREFIX_EVEX_0F38B4, |
1667 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1668 | PREFIX_EVEX_0F38B6, |
1669 | PREFIX_EVEX_0F38B7, | |
1670 | PREFIX_EVEX_0F38B8, | |
1671 | PREFIX_EVEX_0F38B9, | |
1672 | PREFIX_EVEX_0F38BA, | |
1673 | PREFIX_EVEX_0F38BB, | |
1674 | PREFIX_EVEX_0F38BC, | |
1675 | PREFIX_EVEX_0F38BD, | |
1676 | PREFIX_EVEX_0F38BE, | |
1677 | PREFIX_EVEX_0F38BF, | |
1678 | PREFIX_EVEX_0F38C4, | |
1679 | PREFIX_EVEX_0F38C6_REG_1, | |
1680 | PREFIX_EVEX_0F38C6_REG_2, | |
1681 | PREFIX_EVEX_0F38C6_REG_5, | |
1682 | PREFIX_EVEX_0F38C6_REG_6, | |
1683 | PREFIX_EVEX_0F38C7_REG_1, | |
1684 | PREFIX_EVEX_0F38C7_REG_2, | |
1685 | PREFIX_EVEX_0F38C7_REG_5, | |
1686 | PREFIX_EVEX_0F38C7_REG_6, | |
1687 | PREFIX_EVEX_0F38C8, | |
1688 | PREFIX_EVEX_0F38CA, | |
1689 | PREFIX_EVEX_0F38CB, | |
1690 | PREFIX_EVEX_0F38CC, | |
1691 | PREFIX_EVEX_0F38CD, | |
48521003 | 1692 | PREFIX_EVEX_0F38CF, |
8dcf1fad IT |
1693 | PREFIX_EVEX_0F38DC, |
1694 | PREFIX_EVEX_0F38DD, | |
1695 | PREFIX_EVEX_0F38DE, | |
1696 | PREFIX_EVEX_0F38DF, | |
43234a1e L |
1697 | |
1698 | PREFIX_EVEX_0F3A00, | |
1699 | PREFIX_EVEX_0F3A01, | |
1700 | PREFIX_EVEX_0F3A03, | |
1701 | PREFIX_EVEX_0F3A04, | |
1702 | PREFIX_EVEX_0F3A05, | |
1703 | PREFIX_EVEX_0F3A08, | |
1704 | PREFIX_EVEX_0F3A09, | |
1705 | PREFIX_EVEX_0F3A0A, | |
1706 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1707 | PREFIX_EVEX_0F3A0F, |
1708 | PREFIX_EVEX_0F3A14, | |
1709 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1710 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1711 | PREFIX_EVEX_0F3A17, |
1712 | PREFIX_EVEX_0F3A18, | |
1713 | PREFIX_EVEX_0F3A19, | |
1714 | PREFIX_EVEX_0F3A1A, | |
1715 | PREFIX_EVEX_0F3A1B, | |
1716 | PREFIX_EVEX_0F3A1D, | |
1717 | PREFIX_EVEX_0F3A1E, | |
1718 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1719 | PREFIX_EVEX_0F3A20, |
43234a1e | 1720 | PREFIX_EVEX_0F3A21, |
90a915bf | 1721 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1722 | PREFIX_EVEX_0F3A23, |
1723 | PREFIX_EVEX_0F3A25, | |
1724 | PREFIX_EVEX_0F3A26, | |
1725 | PREFIX_EVEX_0F3A27, | |
1726 | PREFIX_EVEX_0F3A38, | |
1727 | PREFIX_EVEX_0F3A39, | |
1728 | PREFIX_EVEX_0F3A3A, | |
1729 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1730 | PREFIX_EVEX_0F3A3E, |
1731 | PREFIX_EVEX_0F3A3F, | |
1732 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1733 | PREFIX_EVEX_0F3A43, |
ff1982d5 | 1734 | PREFIX_EVEX_0F3A44, |
90a915bf IT |
1735 | PREFIX_EVEX_0F3A50, |
1736 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1737 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1738 | PREFIX_EVEX_0F3A55, |
1739 | PREFIX_EVEX_0F3A56, | |
1740 | PREFIX_EVEX_0F3A57, | |
1741 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1742 | PREFIX_EVEX_0F3A67, |
1743 | PREFIX_EVEX_0F3A70, | |
1744 | PREFIX_EVEX_0F3A71, | |
1745 | PREFIX_EVEX_0F3A72, | |
48521003 IT |
1746 | PREFIX_EVEX_0F3A73, |
1747 | PREFIX_EVEX_0F3ACE, | |
1748 | PREFIX_EVEX_0F3ACF | |
51e7da1b | 1749 | }; |
4e7d34a6 | 1750 | |
51e7da1b L |
1751 | enum |
1752 | { | |
1753 | X86_64_06 = 0, | |
3873ba12 L |
1754 | X86_64_07, |
1755 | X86_64_0D, | |
1756 | X86_64_16, | |
1757 | X86_64_17, | |
1758 | X86_64_1E, | |
1759 | X86_64_1F, | |
1760 | X86_64_27, | |
1761 | X86_64_2F, | |
1762 | X86_64_37, | |
1763 | X86_64_3F, | |
1764 | X86_64_60, | |
1765 | X86_64_61, | |
1766 | X86_64_62, | |
1767 | X86_64_63, | |
1768 | X86_64_6D, | |
1769 | X86_64_6F, | |
d039fef3 | 1770 | X86_64_82, |
3873ba12 L |
1771 | X86_64_9A, |
1772 | X86_64_C4, | |
1773 | X86_64_C5, | |
1774 | X86_64_CE, | |
1775 | X86_64_D4, | |
1776 | X86_64_D5, | |
a72d2af2 L |
1777 | X86_64_E8, |
1778 | X86_64_E9, | |
3873ba12 L |
1779 | X86_64_EA, |
1780 | X86_64_0F01_REG_0, | |
1781 | X86_64_0F01_REG_1, | |
1782 | X86_64_0F01_REG_2, | |
1783 | X86_64_0F01_REG_3 | |
51e7da1b | 1784 | }; |
4e7d34a6 | 1785 | |
51e7da1b L |
1786 | enum |
1787 | { | |
1788 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1789 | THREE_BYTE_0F3A |
51e7da1b | 1790 | }; |
4e7d34a6 | 1791 | |
f88c9eb0 SP |
1792 | enum |
1793 | { | |
5dd85c99 SP |
1794 | XOP_08 = 0, |
1795 | XOP_09, | |
f88c9eb0 SP |
1796 | XOP_0A |
1797 | }; | |
1798 | ||
51e7da1b L |
1799 | enum |
1800 | { | |
1801 | VEX_0F = 0, | |
3873ba12 L |
1802 | VEX_0F38, |
1803 | VEX_0F3A | |
51e7da1b | 1804 | }; |
c0f3af97 | 1805 | |
43234a1e L |
1806 | enum |
1807 | { | |
1808 | EVEX_0F = 0, | |
1809 | EVEX_0F38, | |
1810 | EVEX_0F3A | |
1811 | }; | |
1812 | ||
51e7da1b L |
1813 | enum |
1814 | { | |
ec6f095a | 1815 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b L |
1816 | VEX_LEN_0F12_P_0_M_1, |
1817 | VEX_LEN_0F12_P_2, | |
1818 | VEX_LEN_0F13_M_0, | |
1819 | VEX_LEN_0F16_P_0_M_0, | |
1820 | VEX_LEN_0F16_P_0_M_1, | |
1821 | VEX_LEN_0F16_P_2, | |
1822 | VEX_LEN_0F17_M_0, | |
1823 | VEX_LEN_0F2A_P_1, | |
1824 | VEX_LEN_0F2A_P_3, | |
1825 | VEX_LEN_0F2C_P_1, | |
1826 | VEX_LEN_0F2C_P_3, | |
1827 | VEX_LEN_0F2D_P_1, | |
1828 | VEX_LEN_0F2D_P_3, | |
43234a1e | 1829 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1830 | VEX_LEN_0F41_P_2, |
43234a1e | 1831 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1832 | VEX_LEN_0F42_P_2, |
43234a1e | 1833 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1834 | VEX_LEN_0F44_P_2, |
43234a1e | 1835 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1836 | VEX_LEN_0F45_P_2, |
43234a1e | 1837 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1838 | VEX_LEN_0F46_P_2, |
43234a1e | 1839 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1840 | VEX_LEN_0F47_P_2, |
1841 | VEX_LEN_0F4A_P_0, | |
1842 | VEX_LEN_0F4A_P_2, | |
1843 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1844 | VEX_LEN_0F4B_P_2, |
592a252b | 1845 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1846 | VEX_LEN_0F77_P_0, |
592a252b L |
1847 | VEX_LEN_0F7E_P_1, |
1848 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1849 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1850 | VEX_LEN_0F90_P_2, |
43234a1e | 1851 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1852 | VEX_LEN_0F91_P_2, |
43234a1e | 1853 | VEX_LEN_0F92_P_0, |
90a915bf | 1854 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1855 | VEX_LEN_0F92_P_3, |
43234a1e | 1856 | VEX_LEN_0F93_P_0, |
90a915bf | 1857 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1858 | VEX_LEN_0F93_P_3, |
43234a1e | 1859 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1860 | VEX_LEN_0F98_P_2, |
1861 | VEX_LEN_0F99_P_0, | |
1862 | VEX_LEN_0F99_P_2, | |
592a252b L |
1863 | VEX_LEN_0FAE_R_2_M_0, |
1864 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1865 | VEX_LEN_0FC4_P_2, |
1866 | VEX_LEN_0FC5_P_2, | |
592a252b | 1867 | VEX_LEN_0FD6_P_2, |
592a252b | 1868 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1869 | VEX_LEN_0F3816_P_2, |
1870 | VEX_LEN_0F3819_P_2, | |
592a252b | 1871 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1872 | VEX_LEN_0F3836_P_2, |
592a252b | 1873 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1874 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1875 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1876 | VEX_LEN_0F38F2_P_0, |
1877 | VEX_LEN_0F38F3_R_1_P_0, | |
1878 | VEX_LEN_0F38F3_R_2_P_0, | |
1879 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1880 | VEX_LEN_0F38F5_P_0, |
1881 | VEX_LEN_0F38F5_P_1, | |
1882 | VEX_LEN_0F38F5_P_3, | |
1883 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1884 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1885 | VEX_LEN_0F38F7_P_1, |
1886 | VEX_LEN_0F38F7_P_2, | |
1887 | VEX_LEN_0F38F7_P_3, | |
1888 | VEX_LEN_0F3A00_P_2, | |
1889 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1890 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1891 | VEX_LEN_0F3A14_P_2, |
1892 | VEX_LEN_0F3A15_P_2, | |
1893 | VEX_LEN_0F3A16_P_2, | |
1894 | VEX_LEN_0F3A17_P_2, | |
1895 | VEX_LEN_0F3A18_P_2, | |
1896 | VEX_LEN_0F3A19_P_2, | |
1897 | VEX_LEN_0F3A20_P_2, | |
1898 | VEX_LEN_0F3A21_P_2, | |
1899 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1900 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1901 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1902 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1903 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1904 | VEX_LEN_0F3A38_P_2, |
1905 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1906 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1907 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1908 | VEX_LEN_0F3A60_P_2, |
1909 | VEX_LEN_0F3A61_P_2, | |
1910 | VEX_LEN_0F3A62_P_2, | |
1911 | VEX_LEN_0F3A63_P_2, | |
1912 | VEX_LEN_0F3A6A_P_2, | |
1913 | VEX_LEN_0F3A6B_P_2, | |
1914 | VEX_LEN_0F3A6E_P_2, | |
1915 | VEX_LEN_0F3A6F_P_2, | |
1916 | VEX_LEN_0F3A7A_P_2, | |
1917 | VEX_LEN_0F3A7B_P_2, | |
1918 | VEX_LEN_0F3A7E_P_2, | |
1919 | VEX_LEN_0F3A7F_P_2, | |
1920 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1921 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1922 | VEX_LEN_0FXOP_08_CC, |
1923 | VEX_LEN_0FXOP_08_CD, | |
1924 | VEX_LEN_0FXOP_08_CE, | |
1925 | VEX_LEN_0FXOP_08_CF, | |
1926 | VEX_LEN_0FXOP_08_EC, | |
1927 | VEX_LEN_0FXOP_08_ED, | |
1928 | VEX_LEN_0FXOP_08_EE, | |
1929 | VEX_LEN_0FXOP_08_EF, | |
592a252b L |
1930 | VEX_LEN_0FXOP_09_80, |
1931 | VEX_LEN_0FXOP_09_81 | |
51e7da1b | 1932 | }; |
c0f3af97 | 1933 | |
04e2a182 L |
1934 | enum |
1935 | { | |
1936 | EVEX_LEN_0F6E_P_2 = 0, | |
1937 | EVEX_LEN_0F7E_P_1, | |
1938 | EVEX_LEN_0F7E_P_2, | |
1939 | EVEX_LEN_0FD6_P_2 | |
1940 | }; | |
1941 | ||
9e30b8e0 L |
1942 | enum |
1943 | { | |
ec6f095a | 1944 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1945 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1946 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1947 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1948 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1949 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1950 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1951 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1952 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1953 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1954 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1955 | VEX_W_0F47_P_2_LEN_1, |
1956 | VEX_W_0F4A_P_0_LEN_1, | |
1957 | VEX_W_0F4A_P_2_LEN_1, | |
1958 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1959 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1960 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1961 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1962 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1963 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1964 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1965 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1966 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1967 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1968 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1969 | VEX_W_0F98_P_2_LEN_0, |
1970 | VEX_W_0F99_P_0_LEN_0, | |
1971 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1972 | VEX_W_0F380C_P_2, |
1973 | VEX_W_0F380D_P_2, | |
1974 | VEX_W_0F380E_P_2, | |
1975 | VEX_W_0F380F_P_2, | |
6c30d220 | 1976 | VEX_W_0F3816_P_2, |
6c30d220 L |
1977 | VEX_W_0F3818_P_2, |
1978 | VEX_W_0F3819_P_2, | |
592a252b | 1979 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1980 | VEX_W_0F382C_P_2_M_0, |
1981 | VEX_W_0F382D_P_2_M_0, | |
1982 | VEX_W_0F382E_P_2_M_0, | |
1983 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1984 | VEX_W_0F3836_P_2, |
6c30d220 L |
1985 | VEX_W_0F3846_P_2, |
1986 | VEX_W_0F3858_P_2, | |
1987 | VEX_W_0F3859_P_2, | |
1988 | VEX_W_0F385A_P_2_M_0, | |
1989 | VEX_W_0F3878_P_2, | |
1990 | VEX_W_0F3879_P_2, | |
48521003 | 1991 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1992 | VEX_W_0F3A00_P_2, |
1993 | VEX_W_0F3A01_P_2, | |
1994 | VEX_W_0F3A02_P_2, | |
592a252b L |
1995 | VEX_W_0F3A04_P_2, |
1996 | VEX_W_0F3A05_P_2, | |
1997 | VEX_W_0F3A06_P_2, | |
592a252b L |
1998 | VEX_W_0F3A18_P_2, |
1999 | VEX_W_0F3A19_P_2, | |
43234a1e | 2000 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 2001 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 2002 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 2003 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
2004 | VEX_W_0F3A38_P_2, |
2005 | VEX_W_0F3A39_P_2, | |
6c30d220 | 2006 | VEX_W_0F3A46_P_2, |
592a252b L |
2007 | VEX_W_0F3A48_P_2, |
2008 | VEX_W_0F3A49_P_2, | |
2009 | VEX_W_0F3A4A_P_2, | |
2010 | VEX_W_0F3A4B_P_2, | |
2011 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
2012 | VEX_W_0F3ACE_P_2, |
2013 | VEX_W_0F3ACF_P_2, | |
43234a1e L |
2014 | |
2015 | EVEX_W_0F10_P_0, | |
2016 | EVEX_W_0F10_P_1_M_0, | |
2017 | EVEX_W_0F10_P_1_M_1, | |
2018 | EVEX_W_0F10_P_2, | |
2019 | EVEX_W_0F10_P_3_M_0, | |
2020 | EVEX_W_0F10_P_3_M_1, | |
2021 | EVEX_W_0F11_P_0, | |
2022 | EVEX_W_0F11_P_1_M_0, | |
2023 | EVEX_W_0F11_P_1_M_1, | |
2024 | EVEX_W_0F11_P_2, | |
2025 | EVEX_W_0F11_P_3_M_0, | |
2026 | EVEX_W_0F11_P_3_M_1, | |
2027 | EVEX_W_0F12_P_0_M_0, | |
2028 | EVEX_W_0F12_P_0_M_1, | |
2029 | EVEX_W_0F12_P_1, | |
2030 | EVEX_W_0F12_P_2, | |
2031 | EVEX_W_0F12_P_3, | |
2032 | EVEX_W_0F13_P_0, | |
2033 | EVEX_W_0F13_P_2, | |
2034 | EVEX_W_0F14_P_0, | |
2035 | EVEX_W_0F14_P_2, | |
2036 | EVEX_W_0F15_P_0, | |
2037 | EVEX_W_0F15_P_2, | |
2038 | EVEX_W_0F16_P_0_M_0, | |
2039 | EVEX_W_0F16_P_0_M_1, | |
2040 | EVEX_W_0F16_P_1, | |
2041 | EVEX_W_0F16_P_2, | |
2042 | EVEX_W_0F17_P_0, | |
2043 | EVEX_W_0F17_P_2, | |
2044 | EVEX_W_0F28_P_0, | |
2045 | EVEX_W_0F28_P_2, | |
2046 | EVEX_W_0F29_P_0, | |
2047 | EVEX_W_0F29_P_2, | |
2048 | EVEX_W_0F2A_P_1, | |
2049 | EVEX_W_0F2A_P_3, | |
2050 | EVEX_W_0F2B_P_0, | |
2051 | EVEX_W_0F2B_P_2, | |
2052 | EVEX_W_0F2E_P_0, | |
2053 | EVEX_W_0F2E_P_2, | |
2054 | EVEX_W_0F2F_P_0, | |
2055 | EVEX_W_0F2F_P_2, | |
2056 | EVEX_W_0F51_P_0, | |
2057 | EVEX_W_0F51_P_1, | |
2058 | EVEX_W_0F51_P_2, | |
2059 | EVEX_W_0F51_P_3, | |
90a915bf IT |
2060 | EVEX_W_0F54_P_0, |
2061 | EVEX_W_0F54_P_2, | |
2062 | EVEX_W_0F55_P_0, | |
2063 | EVEX_W_0F55_P_2, | |
2064 | EVEX_W_0F56_P_0, | |
2065 | EVEX_W_0F56_P_2, | |
2066 | EVEX_W_0F57_P_0, | |
2067 | EVEX_W_0F57_P_2, | |
43234a1e L |
2068 | EVEX_W_0F58_P_0, |
2069 | EVEX_W_0F58_P_1, | |
2070 | EVEX_W_0F58_P_2, | |
2071 | EVEX_W_0F58_P_3, | |
2072 | EVEX_W_0F59_P_0, | |
2073 | EVEX_W_0F59_P_1, | |
2074 | EVEX_W_0F59_P_2, | |
2075 | EVEX_W_0F59_P_3, | |
2076 | EVEX_W_0F5A_P_0, | |
2077 | EVEX_W_0F5A_P_1, | |
2078 | EVEX_W_0F5A_P_2, | |
2079 | EVEX_W_0F5A_P_3, | |
2080 | EVEX_W_0F5B_P_0, | |
2081 | EVEX_W_0F5B_P_1, | |
2082 | EVEX_W_0F5B_P_2, | |
2083 | EVEX_W_0F5C_P_0, | |
2084 | EVEX_W_0F5C_P_1, | |
2085 | EVEX_W_0F5C_P_2, | |
2086 | EVEX_W_0F5C_P_3, | |
2087 | EVEX_W_0F5D_P_0, | |
2088 | EVEX_W_0F5D_P_1, | |
2089 | EVEX_W_0F5D_P_2, | |
2090 | EVEX_W_0F5D_P_3, | |
2091 | EVEX_W_0F5E_P_0, | |
2092 | EVEX_W_0F5E_P_1, | |
2093 | EVEX_W_0F5E_P_2, | |
2094 | EVEX_W_0F5E_P_3, | |
2095 | EVEX_W_0F5F_P_0, | |
2096 | EVEX_W_0F5F_P_1, | |
2097 | EVEX_W_0F5F_P_2, | |
2098 | EVEX_W_0F5F_P_3, | |
2099 | EVEX_W_0F62_P_2, | |
2100 | EVEX_W_0F66_P_2, | |
2101 | EVEX_W_0F6A_P_2, | |
1ba585e8 | 2102 | EVEX_W_0F6B_P_2, |
43234a1e L |
2103 | EVEX_W_0F6C_P_2, |
2104 | EVEX_W_0F6D_P_2, | |
43234a1e L |
2105 | EVEX_W_0F6F_P_1, |
2106 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 2107 | EVEX_W_0F6F_P_3, |
43234a1e L |
2108 | EVEX_W_0F70_P_2, |
2109 | EVEX_W_0F72_R_2_P_2, | |
2110 | EVEX_W_0F72_R_6_P_2, | |
2111 | EVEX_W_0F73_R_2_P_2, | |
2112 | EVEX_W_0F73_R_6_P_2, | |
2113 | EVEX_W_0F76_P_2, | |
2114 | EVEX_W_0F78_P_0, | |
90a915bf | 2115 | EVEX_W_0F78_P_2, |
43234a1e | 2116 | EVEX_W_0F79_P_0, |
90a915bf | 2117 | EVEX_W_0F79_P_2, |
43234a1e | 2118 | EVEX_W_0F7A_P_1, |
90a915bf | 2119 | EVEX_W_0F7A_P_2, |
43234a1e L |
2120 | EVEX_W_0F7A_P_3, |
2121 | EVEX_W_0F7B_P_1, | |
90a915bf | 2122 | EVEX_W_0F7B_P_2, |
43234a1e L |
2123 | EVEX_W_0F7B_P_3, |
2124 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2125 | EVEX_W_0F7F_P_1, |
2126 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2127 | EVEX_W_0F7F_P_3, |
43234a1e L |
2128 | EVEX_W_0FC2_P_0, |
2129 | EVEX_W_0FC2_P_1, | |
2130 | EVEX_W_0FC2_P_2, | |
2131 | EVEX_W_0FC2_P_3, | |
2132 | EVEX_W_0FC6_P_0, | |
2133 | EVEX_W_0FC6_P_2, | |
2134 | EVEX_W_0FD2_P_2, | |
2135 | EVEX_W_0FD3_P_2, | |
2136 | EVEX_W_0FD4_P_2, | |
2137 | EVEX_W_0FD6_P_2, | |
2138 | EVEX_W_0FE6_P_1, | |
2139 | EVEX_W_0FE6_P_2, | |
2140 | EVEX_W_0FE6_P_3, | |
2141 | EVEX_W_0FE7_P_2, | |
2142 | EVEX_W_0FF2_P_2, | |
2143 | EVEX_W_0FF3_P_2, | |
2144 | EVEX_W_0FF4_P_2, | |
2145 | EVEX_W_0FFA_P_2, | |
2146 | EVEX_W_0FFB_P_2, | |
2147 | EVEX_W_0FFE_P_2, | |
2148 | EVEX_W_0F380C_P_2, | |
2149 | EVEX_W_0F380D_P_2, | |
1ba585e8 IT |
2150 | EVEX_W_0F3810_P_1, |
2151 | EVEX_W_0F3810_P_2, | |
43234a1e | 2152 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2153 | EVEX_W_0F3811_P_2, |
43234a1e | 2154 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2155 | EVEX_W_0F3812_P_2, |
43234a1e L |
2156 | EVEX_W_0F3813_P_1, |
2157 | EVEX_W_0F3813_P_2, | |
2158 | EVEX_W_0F3814_P_1, | |
2159 | EVEX_W_0F3815_P_1, | |
2160 | EVEX_W_0F3818_P_2, | |
2161 | EVEX_W_0F3819_P_2, | |
2162 | EVEX_W_0F381A_P_2, | |
2163 | EVEX_W_0F381B_P_2, | |
2164 | EVEX_W_0F381E_P_2, | |
2165 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2166 | EVEX_W_0F3820_P_1, |
43234a1e L |
2167 | EVEX_W_0F3821_P_1, |
2168 | EVEX_W_0F3822_P_1, | |
2169 | EVEX_W_0F3823_P_1, | |
2170 | EVEX_W_0F3824_P_1, | |
2171 | EVEX_W_0F3825_P_1, | |
2172 | EVEX_W_0F3825_P_2, | |
1ba585e8 IT |
2173 | EVEX_W_0F3826_P_1, |
2174 | EVEX_W_0F3826_P_2, | |
2175 | EVEX_W_0F3828_P_1, | |
43234a1e | 2176 | EVEX_W_0F3828_P_2, |
1ba585e8 | 2177 | EVEX_W_0F3829_P_1, |
43234a1e L |
2178 | EVEX_W_0F3829_P_2, |
2179 | EVEX_W_0F382A_P_1, | |
2180 | EVEX_W_0F382A_P_2, | |
1ba585e8 IT |
2181 | EVEX_W_0F382B_P_2, |
2182 | EVEX_W_0F3830_P_1, | |
43234a1e L |
2183 | EVEX_W_0F3831_P_1, |
2184 | EVEX_W_0F3832_P_1, | |
2185 | EVEX_W_0F3833_P_1, | |
2186 | EVEX_W_0F3834_P_1, | |
2187 | EVEX_W_0F3835_P_1, | |
2188 | EVEX_W_0F3835_P_2, | |
2189 | EVEX_W_0F3837_P_2, | |
90a915bf IT |
2190 | EVEX_W_0F3838_P_1, |
2191 | EVEX_W_0F3839_P_1, | |
43234a1e L |
2192 | EVEX_W_0F383A_P_1, |
2193 | EVEX_W_0F3840_P_2, | |
d6aab7a1 | 2194 | EVEX_W_0F3852_P_1, |
ee6872be | 2195 | EVEX_W_0F3854_P_2, |
620214f7 | 2196 | EVEX_W_0F3855_P_2, |
43234a1e L |
2197 | EVEX_W_0F3858_P_2, |
2198 | EVEX_W_0F3859_P_2, | |
2199 | EVEX_W_0F385A_P_2, | |
2200 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2201 | EVEX_W_0F3862_P_2, |
2202 | EVEX_W_0F3863_P_2, | |
1ba585e8 | 2203 | EVEX_W_0F3866_P_2, |
53467f57 IT |
2204 | EVEX_W_0F3870_P_2, |
2205 | EVEX_W_0F3871_P_2, | |
d6aab7a1 | 2206 | EVEX_W_0F3872_P_1, |
53467f57 | 2207 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2208 | EVEX_W_0F3872_P_3, |
53467f57 | 2209 | EVEX_W_0F3873_P_2, |
1ba585e8 IT |
2210 | EVEX_W_0F3875_P_2, |
2211 | EVEX_W_0F3878_P_2, | |
2212 | EVEX_W_0F3879_P_2, | |
2213 | EVEX_W_0F387A_P_2, | |
2214 | EVEX_W_0F387B_P_2, | |
2215 | EVEX_W_0F387D_P_2, | |
14f195c9 | 2216 | EVEX_W_0F3883_P_2, |
1ba585e8 | 2217 | EVEX_W_0F388D_P_2, |
43234a1e L |
2218 | EVEX_W_0F3891_P_2, |
2219 | EVEX_W_0F3893_P_2, | |
2220 | EVEX_W_0F38A1_P_2, | |
2221 | EVEX_W_0F38A3_P_2, | |
2222 | EVEX_W_0F38C7_R_1_P_2, | |
2223 | EVEX_W_0F38C7_R_2_P_2, | |
2224 | EVEX_W_0F38C7_R_5_P_2, | |
2225 | EVEX_W_0F38C7_R_6_P_2, | |
2226 | ||
2227 | EVEX_W_0F3A00_P_2, | |
2228 | EVEX_W_0F3A01_P_2, | |
2229 | EVEX_W_0F3A04_P_2, | |
2230 | EVEX_W_0F3A05_P_2, | |
2231 | EVEX_W_0F3A08_P_2, | |
2232 | EVEX_W_0F3A09_P_2, | |
2233 | EVEX_W_0F3A0A_P_2, | |
2234 | EVEX_W_0F3A0B_P_2, | |
2235 | EVEX_W_0F3A18_P_2, | |
2236 | EVEX_W_0F3A19_P_2, | |
2237 | EVEX_W_0F3A1A_P_2, | |
2238 | EVEX_W_0F3A1B_P_2, | |
2239 | EVEX_W_0F3A1D_P_2, | |
2240 | EVEX_W_0F3A21_P_2, | |
2241 | EVEX_W_0F3A23_P_2, | |
2242 | EVEX_W_0F3A38_P_2, | |
2243 | EVEX_W_0F3A39_P_2, | |
2244 | EVEX_W_0F3A3A_P_2, | |
2245 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 IT |
2246 | EVEX_W_0F3A3E_P_2, |
2247 | EVEX_W_0F3A3F_P_2, | |
2248 | EVEX_W_0F3A42_P_2, | |
90a915bf IT |
2249 | EVEX_W_0F3A43_P_2, |
2250 | EVEX_W_0F3A50_P_2, | |
2251 | EVEX_W_0F3A51_P_2, | |
2252 | EVEX_W_0F3A56_P_2, | |
2253 | EVEX_W_0F3A57_P_2, | |
2254 | EVEX_W_0F3A66_P_2, | |
53467f57 IT |
2255 | EVEX_W_0F3A67_P_2, |
2256 | EVEX_W_0F3A70_P_2, | |
2257 | EVEX_W_0F3A71_P_2, | |
2258 | EVEX_W_0F3A72_P_2, | |
48521003 IT |
2259 | EVEX_W_0F3A73_P_2, |
2260 | EVEX_W_0F3ACE_P_2, | |
2261 | EVEX_W_0F3ACF_P_2 | |
9e30b8e0 L |
2262 | }; |
2263 | ||
26ca5450 | 2264 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2265 | |
2266 | struct dis386 { | |
2da11e11 | 2267 | const char *name; |
ce518a5f L |
2268 | struct |
2269 | { | |
2270 | op_rtn rtn; | |
2271 | int bytemode; | |
2272 | } op[MAX_OPERANDS]; | |
bf890a93 | 2273 | unsigned int prefix_requirement; |
252b5132 RH |
2274 | }; |
2275 | ||
2276 | /* Upper case letters in the instruction names here are macros. | |
2277 | 'A' => print 'b' if no register operands or suffix_always is true | |
2278 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2279 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2280 | size prefix |
ed7841b3 | 2281 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2282 | suffix_always is true |
252b5132 | 2283 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2284 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2285 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2286 | 'H' => print ",pt" or ",pn" branch hint |
9306ca4a | 2287 | 'I' => honor following macro letter even in Intel mode (implemented only |
98b528ac | 2288 | for some of the macro letters) |
9306ca4a | 2289 | 'J' => print 'l' |
42903f7f | 2290 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2291 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2292 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2293 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2294 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2295 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2296 | or suffix_always is true. print 'q' if rex prefix is present. |
2297 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2298 | is true | |
a35ca55a | 2299 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2300 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2301 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2302 | prefix and behave as 'P' otherwise | |
2303 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2304 | prefix and behave as 'Q' otherwise | |
2305 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2306 | prefix and behave as 'S' otherwise | |
a35ca55a | 2307 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2308 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2309 | 'Y' unused. |
6dd5059a | 2310 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2311 | '!' => change condition from true to false or from false to true. |
98b528ac | 2312 | '%' => add 1 upper case letter to the macro. |
a72d2af2 L |
2313 | '^' => print 'w' or 'l' depending on operand size prefix or |
2314 | suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2315 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2316 | on operand size prefix. | |
07f5af7d L |
2317 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2318 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2319 | otherwise | |
98b528ac L |
2320 | |
2321 | 2 upper case letter macros: | |
04d824a4 JB |
2322 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2323 | operands and no broadcast. | |
2324 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2325 | register operands and no broadcast. | |
4b06377f L |
2326 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
2327 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand | |
98b528ac | 2328 | or suffix_always is true |
4b06377f L |
2329 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2330 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2331 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2332 | "LW" => print 'd', 'q' depending on the VEX.W bit |
4b4c407a L |
2333 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2334 | an operand size prefix, or suffix_always is true. print | |
2335 | 'q' if rex prefix is present. | |
52b15da3 | 2336 | |
6439fc28 AM |
2337 | Many of the above letters print nothing in Intel mode. See "putop" |
2338 | for the details. | |
52b15da3 | 2339 | |
6439fc28 | 2340 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2341 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2342 | |
6439fc28 | 2343 | static const struct dis386 dis386[] = { |
252b5132 | 2344 | /* 00 */ |
bf890a93 IT |
2345 | { "addB", { Ebh1, Gb }, 0 }, |
2346 | { "addS", { Evh1, Gv }, 0 }, | |
2347 | { "addB", { Gb, EbS }, 0 }, | |
2348 | { "addS", { Gv, EvS }, 0 }, | |
2349 | { "addB", { AL, Ib }, 0 }, | |
2350 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2351 | { X86_64_TABLE (X86_64_06) }, |
2352 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2353 | /* 08 */ |
bf890a93 IT |
2354 | { "orB", { Ebh1, Gb }, 0 }, |
2355 | { "orS", { Evh1, Gv }, 0 }, | |
2356 | { "orB", { Gb, EbS }, 0 }, | |
2357 | { "orS", { Gv, EvS }, 0 }, | |
2358 | { "orB", { AL, Ib }, 0 }, | |
2359 | { "orS", { eAX, Iv }, 0 }, | |
4e7d34a6 | 2360 | { X86_64_TABLE (X86_64_0D) }, |
592d1631 | 2361 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2362 | /* 10 */ |
bf890a93 IT |
2363 | { "adcB", { Ebh1, Gb }, 0 }, |
2364 | { "adcS", { Evh1, Gv }, 0 }, | |
2365 | { "adcB", { Gb, EbS }, 0 }, | |
2366 | { "adcS", { Gv, EvS }, 0 }, | |
2367 | { "adcB", { AL, Ib }, 0 }, | |
2368 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2369 | { X86_64_TABLE (X86_64_16) }, |
2370 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2371 | /* 18 */ |
bf890a93 IT |
2372 | { "sbbB", { Ebh1, Gb }, 0 }, |
2373 | { "sbbS", { Evh1, Gv }, 0 }, | |
2374 | { "sbbB", { Gb, EbS }, 0 }, | |
2375 | { "sbbS", { Gv, EvS }, 0 }, | |
2376 | { "sbbB", { AL, Ib }, 0 }, | |
2377 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2378 | { X86_64_TABLE (X86_64_1E) }, |
2379 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2380 | /* 20 */ |
bf890a93 IT |
2381 | { "andB", { Ebh1, Gb }, 0 }, |
2382 | { "andS", { Evh1, Gv }, 0 }, | |
2383 | { "andB", { Gb, EbS }, 0 }, | |
2384 | { "andS", { Gv, EvS }, 0 }, | |
2385 | { "andB", { AL, Ib }, 0 }, | |
2386 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2387 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2388 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2389 | /* 28 */ |
bf890a93 IT |
2390 | { "subB", { Ebh1, Gb }, 0 }, |
2391 | { "subS", { Evh1, Gv }, 0 }, | |
2392 | { "subB", { Gb, EbS }, 0 }, | |
2393 | { "subS", { Gv, EvS }, 0 }, | |
2394 | { "subB", { AL, Ib }, 0 }, | |
2395 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2396 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2397 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2398 | /* 30 */ |
bf890a93 IT |
2399 | { "xorB", { Ebh1, Gb }, 0 }, |
2400 | { "xorS", { Evh1, Gv }, 0 }, | |
2401 | { "xorB", { Gb, EbS }, 0 }, | |
2402 | { "xorS", { Gv, EvS }, 0 }, | |
2403 | { "xorB", { AL, Ib }, 0 }, | |
2404 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2405 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2406 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2407 | /* 38 */ |
bf890a93 IT |
2408 | { "cmpB", { Eb, Gb }, 0 }, |
2409 | { "cmpS", { Ev, Gv }, 0 }, | |
2410 | { "cmpB", { Gb, EbS }, 0 }, | |
2411 | { "cmpS", { Gv, EvS }, 0 }, | |
2412 | { "cmpB", { AL, Ib }, 0 }, | |
2413 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2414 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2415 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2416 | /* 40 */ |
bf890a93 IT |
2417 | { "inc{S|}", { RMeAX }, 0 }, |
2418 | { "inc{S|}", { RMeCX }, 0 }, | |
2419 | { "inc{S|}", { RMeDX }, 0 }, | |
2420 | { "inc{S|}", { RMeBX }, 0 }, | |
2421 | { "inc{S|}", { RMeSP }, 0 }, | |
2422 | { "inc{S|}", { RMeBP }, 0 }, | |
2423 | { "inc{S|}", { RMeSI }, 0 }, | |
2424 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2425 | /* 48 */ |
bf890a93 IT |
2426 | { "dec{S|}", { RMeAX }, 0 }, |
2427 | { "dec{S|}", { RMeCX }, 0 }, | |
2428 | { "dec{S|}", { RMeDX }, 0 }, | |
2429 | { "dec{S|}", { RMeBX }, 0 }, | |
2430 | { "dec{S|}", { RMeSP }, 0 }, | |
2431 | { "dec{S|}", { RMeBP }, 0 }, | |
2432 | { "dec{S|}", { RMeSI }, 0 }, | |
2433 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2434 | /* 50 */ |
bf890a93 IT |
2435 | { "pushV", { RMrAX }, 0 }, |
2436 | { "pushV", { RMrCX }, 0 }, | |
2437 | { "pushV", { RMrDX }, 0 }, | |
2438 | { "pushV", { RMrBX }, 0 }, | |
2439 | { "pushV", { RMrSP }, 0 }, | |
2440 | { "pushV", { RMrBP }, 0 }, | |
2441 | { "pushV", { RMrSI }, 0 }, | |
2442 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2443 | /* 58 */ |
bf890a93 IT |
2444 | { "popV", { RMrAX }, 0 }, |
2445 | { "popV", { RMrCX }, 0 }, | |
2446 | { "popV", { RMrDX }, 0 }, | |
2447 | { "popV", { RMrBX }, 0 }, | |
2448 | { "popV", { RMrSP }, 0 }, | |
2449 | { "popV", { RMrBP }, 0 }, | |
2450 | { "popV", { RMrSI }, 0 }, | |
2451 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2452 | /* 60 */ |
4e7d34a6 L |
2453 | { X86_64_TABLE (X86_64_60) }, |
2454 | { X86_64_TABLE (X86_64_61) }, | |
2455 | { X86_64_TABLE (X86_64_62) }, | |
2456 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2457 | { Bad_Opcode }, /* seg fs */ |
2458 | { Bad_Opcode }, /* seg gs */ | |
2459 | { Bad_Opcode }, /* op size prefix */ | |
2460 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2461 | /* 68 */ |
bf890a93 IT |
2462 | { "pushT", { sIv }, 0 }, |
2463 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2464 | { "pushT", { sIbT }, 0 }, | |
2465 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2466 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2467 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2468 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2469 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2470 | /* 70 */ |
bf890a93 IT |
2471 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2472 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2473 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2474 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2475 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2476 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2477 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2478 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2479 | /* 78 */ |
bf890a93 IT |
2480 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2481 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2482 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2483 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2484 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2485 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2486 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2487 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2488 | /* 80 */ |
1ceb70f8 L |
2489 | { REG_TABLE (REG_80) }, |
2490 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2491 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2492 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2493 | { "testB", { Eb, Gb }, 0 }, |
2494 | { "testS", { Ev, Gv }, 0 }, | |
2495 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2496 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2497 | /* 88 */ |
bf890a93 IT |
2498 | { "movB", { Ebh3, Gb }, 0 }, |
2499 | { "movS", { Evh3, Gv }, 0 }, | |
2500 | { "movB", { Gb, EbS }, 0 }, | |
2501 | { "movS", { Gv, EvS }, 0 }, | |
2502 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2503 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2504 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2505 | { REG_TABLE (REG_8F) }, |
252b5132 | 2506 | /* 90 */ |
1ceb70f8 | 2507 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2508 | { "xchgS", { RMeCX, eAX }, 0 }, |
2509 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2510 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2511 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2512 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2513 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2514 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2515 | /* 98 */ |
bf890a93 IT |
2516 | { "cW{t|}R", { XX }, 0 }, |
2517 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2518 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2519 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2520 | { "pushfT", { XX }, 0 }, |
2521 | { "popfT", { XX }, 0 }, | |
2522 | { "sahf", { XX }, 0 }, | |
2523 | { "lahf", { XX }, 0 }, | |
252b5132 | 2524 | /* a0 */ |
bf890a93 IT |
2525 | { "mov%LB", { AL, Ob }, 0 }, |
2526 | { "mov%LS", { eAX, Ov }, 0 }, | |
2527 | { "mov%LB", { Ob, AL }, 0 }, | |
2528 | { "mov%LS", { Ov, eAX }, 0 }, | |
2529 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2530 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2531 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2532 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2533 | /* a8 */ |
bf890a93 IT |
2534 | { "testB", { AL, Ib }, 0 }, |
2535 | { "testS", { eAX, Iv }, 0 }, | |
2536 | { "stosB", { Ybr, AL }, 0 }, | |
2537 | { "stosS", { Yvr, eAX }, 0 }, | |
2538 | { "lodsB", { ALr, Xb }, 0 }, | |
2539 | { "lodsS", { eAXr, Xv }, 0 }, | |
2540 | { "scasB", { AL, Yb }, 0 }, | |
2541 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2542 | /* b0 */ |
bf890a93 IT |
2543 | { "movB", { RMAL, Ib }, 0 }, |
2544 | { "movB", { RMCL, Ib }, 0 }, | |
2545 | { "movB", { RMDL, Ib }, 0 }, | |
2546 | { "movB", { RMBL, Ib }, 0 }, | |
2547 | { "movB", { RMAH, Ib }, 0 }, | |
2548 | { "movB", { RMCH, Ib }, 0 }, | |
2549 | { "movB", { RMDH, Ib }, 0 }, | |
2550 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2551 | /* b8 */ |
bf890a93 IT |
2552 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2553 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2554 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2555 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2556 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2557 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2558 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2559 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2560 | /* c0 */ |
1ceb70f8 L |
2561 | { REG_TABLE (REG_C0) }, |
2562 | { REG_TABLE (REG_C1) }, | |
bf890a93 IT |
2563 | { "retT", { Iw, BND }, 0 }, |
2564 | { "retT", { BND }, 0 }, | |
4e7d34a6 L |
2565 | { X86_64_TABLE (X86_64_C4) }, |
2566 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2567 | { REG_TABLE (REG_C6) }, |
2568 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2569 | /* c8 */ |
bf890a93 IT |
2570 | { "enterT", { Iw, Ib }, 0 }, |
2571 | { "leaveT", { XX }, 0 }, | |
2572 | { "Jret{|f}P", { Iw }, 0 }, | |
2573 | { "Jret{|f}P", { XX }, 0 }, | |
2574 | { "int3", { XX }, 0 }, | |
2575 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2576 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2577 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2578 | /* d0 */ |
1ceb70f8 L |
2579 | { REG_TABLE (REG_D0) }, |
2580 | { REG_TABLE (REG_D1) }, | |
2581 | { REG_TABLE (REG_D2) }, | |
2582 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2583 | { X86_64_TABLE (X86_64_D4) }, |
2584 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2585 | { Bad_Opcode }, |
bf890a93 | 2586 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2587 | /* d8 */ |
2588 | { FLOAT }, | |
2589 | { FLOAT }, | |
2590 | { FLOAT }, | |
2591 | { FLOAT }, | |
2592 | { FLOAT }, | |
2593 | { FLOAT }, | |
2594 | { FLOAT }, | |
2595 | { FLOAT }, | |
2596 | /* e0 */ | |
bf890a93 IT |
2597 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2598 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2599 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2600 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2601 | { "inB", { AL, Ib }, 0 }, | |
2602 | { "inG", { zAX, Ib }, 0 }, | |
2603 | { "outB", { Ib, AL }, 0 }, | |
2604 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2605 | /* e8 */ |
a72d2af2 L |
2606 | { X86_64_TABLE (X86_64_E8) }, |
2607 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2608 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2609 | { "jmp", { Jb, BND }, 0 }, |
2610 | { "inB", { AL, indirDX }, 0 }, | |
2611 | { "inG", { zAX, indirDX }, 0 }, | |
2612 | { "outB", { indirDX, AL }, 0 }, | |
2613 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2614 | /* f0 */ |
592d1631 | 2615 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2616 | { "icebp", { XX }, 0 }, |
592d1631 L |
2617 | { Bad_Opcode }, /* repne */ |
2618 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2619 | { "hlt", { XX }, 0 }, |
2620 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2621 | { REG_TABLE (REG_F6) }, |
2622 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2623 | /* f8 */ |
bf890a93 IT |
2624 | { "clc", { XX }, 0 }, |
2625 | { "stc", { XX }, 0 }, | |
2626 | { "cli", { XX }, 0 }, | |
2627 | { "sti", { XX }, 0 }, | |
2628 | { "cld", { XX }, 0 }, | |
2629 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2630 | { REG_TABLE (REG_FE) }, |
2631 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2632 | }; |
2633 | ||
6439fc28 | 2634 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2635 | /* 00 */ |
1ceb70f8 L |
2636 | { REG_TABLE (REG_0F00 ) }, |
2637 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2638 | { "larS", { Gv, Ew }, 0 }, |
2639 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2640 | { Bad_Opcode }, |
bf890a93 IT |
2641 | { "syscall", { XX }, 0 }, |
2642 | { "clts", { XX }, 0 }, | |
2643 | { "sysret%LP", { XX }, 0 }, | |
252b5132 | 2644 | /* 08 */ |
bf890a93 | 2645 | { "invd", { XX }, 0 }, |
3233d7d0 | 2646 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2647 | { Bad_Opcode }, |
bf890a93 | 2648 | { "ud2", { XX }, 0 }, |
592d1631 | 2649 | { Bad_Opcode }, |
b5b1fc4f | 2650 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2651 | { "femms", { XX }, 0 }, |
2652 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2653 | /* 10 */ |
1ceb70f8 L |
2654 | { PREFIX_TABLE (PREFIX_0F10) }, |
2655 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2656 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2657 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2658 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2659 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2660 | { PREFIX_TABLE (PREFIX_0F16) }, |
2661 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2662 | /* 18 */ |
1ceb70f8 | 2663 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2664 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2665 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2666 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2667 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2668 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2669 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2670 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2671 | /* 20 */ |
bf890a93 IT |
2672 | { "movZ", { Rm, Cm }, 0 }, |
2673 | { "movZ", { Rm, Dm }, 0 }, | |
2674 | { "movZ", { Cm, Rm }, 0 }, | |
2675 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2676 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2677 | { Bad_Opcode }, |
1ceb70f8 | 2678 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2679 | { Bad_Opcode }, |
252b5132 | 2680 | /* 28 */ |
507bd325 L |
2681 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2682 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2683 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2684 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2685 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2686 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2687 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2688 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2689 | /* 30 */ |
bf890a93 IT |
2690 | { "wrmsr", { XX }, 0 }, |
2691 | { "rdtsc", { XX }, 0 }, | |
2692 | { "rdmsr", { XX }, 0 }, | |
2693 | { "rdpmc", { XX }, 0 }, | |
2694 | { "sysenter", { XX }, 0 }, | |
2695 | { "sysexit", { XX }, 0 }, | |
592d1631 | 2696 | { Bad_Opcode }, |
bf890a93 | 2697 | { "getsec", { XX }, 0 }, |
252b5132 | 2698 | /* 38 */ |
507bd325 | 2699 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2700 | { Bad_Opcode }, |
507bd325 | 2701 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2702 | { Bad_Opcode }, |
2703 | { Bad_Opcode }, | |
2704 | { Bad_Opcode }, | |
2705 | { Bad_Opcode }, | |
2706 | { Bad_Opcode }, | |
252b5132 | 2707 | /* 40 */ |
bf890a93 IT |
2708 | { "cmovoS", { Gv, Ev }, 0 }, |
2709 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2710 | { "cmovbS", { Gv, Ev }, 0 }, | |
2711 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2712 | { "cmoveS", { Gv, Ev }, 0 }, | |
2713 | { "cmovneS", { Gv, Ev }, 0 }, | |
2714 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2715 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2716 | /* 48 */ |
bf890a93 IT |
2717 | { "cmovsS", { Gv, Ev }, 0 }, |
2718 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2719 | { "cmovpS", { Gv, Ev }, 0 }, | |
2720 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2721 | { "cmovlS", { Gv, Ev }, 0 }, | |
2722 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2723 | { "cmovleS", { Gv, Ev }, 0 }, | |
2724 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2725 | /* 50 */ |
75c135a8 | 2726 | { MOD_TABLE (MOD_0F51) }, |
1ceb70f8 L |
2727 | { PREFIX_TABLE (PREFIX_0F51) }, |
2728 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2729 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2730 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2731 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2732 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2733 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2734 | /* 58 */ |
1ceb70f8 L |
2735 | { PREFIX_TABLE (PREFIX_0F58) }, |
2736 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2737 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2738 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2739 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2740 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2741 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2742 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2743 | /* 60 */ |
1ceb70f8 L |
2744 | { PREFIX_TABLE (PREFIX_0F60) }, |
2745 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2746 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2747 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2748 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2749 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2750 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2751 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2752 | /* 68 */ |
507bd325 L |
2753 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2754 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2755 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2756 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2757 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2758 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2759 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2760 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2761 | /* 70 */ |
1ceb70f8 L |
2762 | { PREFIX_TABLE (PREFIX_0F70) }, |
2763 | { REG_TABLE (REG_0F71) }, | |
2764 | { REG_TABLE (REG_0F72) }, | |
2765 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2766 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2767 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2768 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2769 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2770 | /* 78 */ |
1ceb70f8 L |
2771 | { PREFIX_TABLE (PREFIX_0F78) }, |
2772 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2773 | { Bad_Opcode }, |
592d1631 | 2774 | { Bad_Opcode }, |
1ceb70f8 L |
2775 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2776 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2777 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2778 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2779 | /* 80 */ |
bf890a93 IT |
2780 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2781 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2782 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2783 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2784 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2785 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2786 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2787 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2788 | /* 88 */ |
bf890a93 IT |
2789 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2790 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2791 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2792 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2793 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2794 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2795 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2796 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2797 | /* 90 */ |
bf890a93 IT |
2798 | { "seto", { Eb }, 0 }, |
2799 | { "setno", { Eb }, 0 }, | |
2800 | { "setb", { Eb }, 0 }, | |
2801 | { "setae", { Eb }, 0 }, | |
2802 | { "sete", { Eb }, 0 }, | |
2803 | { "setne", { Eb }, 0 }, | |
2804 | { "setbe", { Eb }, 0 }, | |
2805 | { "seta", { Eb }, 0 }, | |
252b5132 | 2806 | /* 98 */ |
bf890a93 IT |
2807 | { "sets", { Eb }, 0 }, |
2808 | { "setns", { Eb }, 0 }, | |
2809 | { "setp", { Eb }, 0 }, | |
2810 | { "setnp", { Eb }, 0 }, | |
2811 | { "setl", { Eb }, 0 }, | |
2812 | { "setge", { Eb }, 0 }, | |
2813 | { "setle", { Eb }, 0 }, | |
2814 | { "setg", { Eb }, 0 }, | |
252b5132 | 2815 | /* a0 */ |
bf890a93 IT |
2816 | { "pushT", { fs }, 0 }, |
2817 | { "popT", { fs }, 0 }, | |
2818 | { "cpuid", { XX }, 0 }, | |
2819 | { "btS", { Ev, Gv }, 0 }, | |
2820 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2821 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2822 | { REG_TABLE (REG_0FA6) }, |
2823 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2824 | /* a8 */ |
bf890a93 IT |
2825 | { "pushT", { gs }, 0 }, |
2826 | { "popT", { gs }, 0 }, | |
2827 | { "rsm", { XX }, 0 }, | |
2828 | { "btsS", { Evh1, Gv }, 0 }, | |
2829 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2830 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2831 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2832 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2833 | /* b0 */ |
bf890a93 IT |
2834 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2835 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2836 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2837 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2838 | { MOD_TABLE (MOD_0FB4) }, |
2839 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2840 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2841 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2842 | /* b8 */ |
1ceb70f8 | 2843 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2844 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2845 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2846 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2847 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2848 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2849 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2850 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2851 | /* c0 */ |
bf890a93 IT |
2852 | { "xaddB", { Ebh1, Gb }, 0 }, |
2853 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2854 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2855 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2856 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2857 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2858 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2859 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2860 | /* c8 */ |
bf890a93 IT |
2861 | { "bswap", { RMeAX }, 0 }, |
2862 | { "bswap", { RMeCX }, 0 }, | |
2863 | { "bswap", { RMeDX }, 0 }, | |
2864 | { "bswap", { RMeBX }, 0 }, | |
2865 | { "bswap", { RMeSP }, 0 }, | |
2866 | { "bswap", { RMeBP }, 0 }, | |
2867 | { "bswap", { RMeSI }, 0 }, | |
2868 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2869 | /* d0 */ |
1ceb70f8 | 2870 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2871 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2872 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2873 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2874 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2875 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2876 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2877 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2878 | /* d8 */ |
507bd325 L |
2879 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2880 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2881 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2882 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2883 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2884 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2885 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2886 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2887 | /* e0 */ |
507bd325 L |
2888 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2889 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2890 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2891 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2892 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2893 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2894 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2895 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2896 | /* e8 */ |
507bd325 L |
2897 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2898 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2899 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2900 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2901 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2902 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2903 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2904 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2905 | /* f0 */ |
1ceb70f8 | 2906 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2907 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2908 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2909 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2910 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2911 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2912 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2913 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2914 | /* f8 */ |
507bd325 L |
2915 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2916 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2917 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2918 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2919 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2920 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2921 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2922 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2923 | }; |
2924 | ||
2925 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2926 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2927 | /* ------------------------------- */ | |
2928 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2929 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2930 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2931 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2932 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2933 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2934 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2935 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2936 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2937 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2938 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2939 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2940 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2941 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2942 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2943 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2944 | /* ------------------------------- */ | |
2945 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2946 | }; |
2947 | ||
2948 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2949 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2950 | /* ------------------------------- */ | |
252b5132 | 2951 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2952 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2953 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2954 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2955 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2956 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2957 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2958 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2959 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2960 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2961 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2962 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2963 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2964 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2965 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2966 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2967 | /* ------------------------------- */ |
2968 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2969 | }; | |
2970 | ||
252b5132 RH |
2971 | static char obuf[100]; |
2972 | static char *obufp; | |
ea397f5b | 2973 | static char *mnemonicendp; |
252b5132 RH |
2974 | static char scratchbuf[100]; |
2975 | static unsigned char *start_codep; | |
2976 | static unsigned char *insn_codep; | |
2977 | static unsigned char *codep; | |
285ca992 | 2978 | static unsigned char *end_codep; |
f16cd0d5 L |
2979 | static int last_lock_prefix; |
2980 | static int last_repz_prefix; | |
2981 | static int last_repnz_prefix; | |
2982 | static int last_data_prefix; | |
2983 | static int last_addr_prefix; | |
2984 | static int last_rex_prefix; | |
2985 | static int last_seg_prefix; | |
d9949a36 | 2986 | static int fwait_prefix; |
285ca992 L |
2987 | /* The active segment register prefix. */ |
2988 | static int active_seg_prefix; | |
f16cd0d5 L |
2989 | #define MAX_CODE_LENGTH 15 |
2990 | /* We can up to 14 prefixes since the maximum instruction length is | |
2991 | 15bytes. */ | |
2992 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2993 | static disassemble_info *the_info; |
7967e09e L |
2994 | static struct |
2995 | { | |
2996 | int mod; | |
7967e09e | 2997 | int reg; |
484c222e | 2998 | int rm; |
7967e09e L |
2999 | } |
3000 | modrm; | |
4bba6815 | 3001 | static unsigned char need_modrm; |
dfc8cf43 L |
3002 | static struct |
3003 | { | |
3004 | int scale; | |
3005 | int index; | |
3006 | int base; | |
3007 | } | |
3008 | sib; | |
c0f3af97 L |
3009 | static struct |
3010 | { | |
3011 | int register_specifier; | |
3012 | int length; | |
3013 | int prefix; | |
3014 | int w; | |
43234a1e L |
3015 | int evex; |
3016 | int r; | |
3017 | int v; | |
3018 | int mask_register_specifier; | |
3019 | int zeroing; | |
3020 | int ll; | |
3021 | int b; | |
c0f3af97 L |
3022 | } |
3023 | vex; | |
3024 | static unsigned char need_vex; | |
3025 | static unsigned char need_vex_reg; | |
dae39acc | 3026 | static unsigned char vex_w_done; |
252b5132 | 3027 | |
ea397f5b L |
3028 | struct op |
3029 | { | |
3030 | const char *name; | |
3031 | unsigned int len; | |
3032 | }; | |
3033 | ||
4bba6815 AM |
3034 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
3035 | values are stale. Hitting this abort likely indicates that you | |
3036 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
3037 | #define MODRM_CHECK if (!need_modrm) abort () | |
3038 | ||
d708bcba AM |
3039 | static const char **names64; |
3040 | static const char **names32; | |
3041 | static const char **names16; | |
3042 | static const char **names8; | |
3043 | static const char **names8rex; | |
3044 | static const char **names_seg; | |
db51cc60 L |
3045 | static const char *index64; |
3046 | static const char *index32; | |
d708bcba | 3047 | static const char **index16; |
7e8b059b | 3048 | static const char **names_bnd; |
d708bcba AM |
3049 | |
3050 | static const char *intel_names64[] = { | |
3051 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
3052 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
3053 | }; | |
3054 | static const char *intel_names32[] = { | |
3055 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
3056 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
3057 | }; | |
3058 | static const char *intel_names16[] = { | |
3059 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
3060 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
3061 | }; | |
3062 | static const char *intel_names8[] = { | |
3063 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
3064 | }; | |
3065 | static const char *intel_names8rex[] = { | |
3066 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
3067 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
3068 | }; | |
3069 | static const char *intel_names_seg[] = { | |
3070 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
3071 | }; | |
db51cc60 L |
3072 | static const char *intel_index64 = "riz"; |
3073 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
3074 | static const char *intel_index16[] = { |
3075 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
3076 | }; | |
3077 | ||
3078 | static const char *att_names64[] = { | |
3079 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
3080 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
3081 | }; | |
d708bcba AM |
3082 | static const char *att_names32[] = { |
3083 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 3084 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 3085 | }; |
d708bcba AM |
3086 | static const char *att_names16[] = { |
3087 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 3088 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 3089 | }; |
d708bcba AM |
3090 | static const char *att_names8[] = { |
3091 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 3092 | }; |
d708bcba AM |
3093 | static const char *att_names8rex[] = { |
3094 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
3095 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
3096 | }; | |
d708bcba AM |
3097 | static const char *att_names_seg[] = { |
3098 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 3099 | }; |
db51cc60 L |
3100 | static const char *att_index64 = "%riz"; |
3101 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
3102 | static const char *att_index16[] = { |
3103 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
3104 | }; |
3105 | ||
b9733481 L |
3106 | static const char **names_mm; |
3107 | static const char *intel_names_mm[] = { | |
3108 | "mm0", "mm1", "mm2", "mm3", | |
3109 | "mm4", "mm5", "mm6", "mm7" | |
3110 | }; | |
3111 | static const char *att_names_mm[] = { | |
3112 | "%mm0", "%mm1", "%mm2", "%mm3", | |
3113 | "%mm4", "%mm5", "%mm6", "%mm7" | |
3114 | }; | |
3115 | ||
7e8b059b L |
3116 | static const char *intel_names_bnd[] = { |
3117 | "bnd0", "bnd1", "bnd2", "bnd3" | |
3118 | }; | |
3119 | ||
3120 | static const char *att_names_bnd[] = { | |
3121 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
3122 | }; | |
3123 | ||
b9733481 L |
3124 | static const char **names_xmm; |
3125 | static const char *intel_names_xmm[] = { | |
3126 | "xmm0", "xmm1", "xmm2", "xmm3", | |
3127 | "xmm4", "xmm5", "xmm6", "xmm7", | |
3128 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
3129 | "xmm12", "xmm13", "xmm14", "xmm15", |
3130 | "xmm16", "xmm17", "xmm18", "xmm19", | |
3131 | "xmm20", "xmm21", "xmm22", "xmm23", | |
3132 | "xmm24", "xmm25", "xmm26", "xmm27", | |
3133 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
3134 | }; |
3135 | static const char *att_names_xmm[] = { | |
3136 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
3137 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
3138 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
3139 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
3140 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
3141 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
3142 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
3143 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
3144 | }; |
3145 | ||
3146 | static const char **names_ymm; | |
3147 | static const char *intel_names_ymm[] = { | |
3148 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3149 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3150 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3151 | "ymm12", "ymm13", "ymm14", "ymm15", |
3152 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3153 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3154 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3155 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3156 | }; |
3157 | static const char *att_names_ymm[] = { | |
3158 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3159 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3160 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3161 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3162 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3163 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3164 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3165 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3166 | }; | |
3167 | ||
3168 | static const char **names_zmm; | |
3169 | static const char *intel_names_zmm[] = { | |
3170 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3171 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3172 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3173 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3174 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3175 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3176 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3177 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3178 | }; | |
3179 | static const char *att_names_zmm[] = { | |
3180 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3181 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3182 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3183 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3184 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3185 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3186 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3187 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3188 | }; | |
3189 | ||
3190 | static const char **names_mask; | |
3191 | static const char *intel_names_mask[] = { | |
3192 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3193 | }; | |
3194 | static const char *att_names_mask[] = { | |
3195 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3196 | }; | |
3197 | ||
3198 | static const char *names_rounding[] = | |
3199 | { | |
3200 | "{rn-sae}", | |
3201 | "{rd-sae}", | |
3202 | "{ru-sae}", | |
3203 | "{rz-sae}" | |
b9733481 L |
3204 | }; |
3205 | ||
1ceb70f8 L |
3206 | static const struct dis386 reg_table[][8] = { |
3207 | /* REG_80 */ | |
252b5132 | 3208 | { |
bf890a93 IT |
3209 | { "addA", { Ebh1, Ib }, 0 }, |
3210 | { "orA", { Ebh1, Ib }, 0 }, | |
3211 | { "adcA", { Ebh1, Ib }, 0 }, | |
3212 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3213 | { "andA", { Ebh1, Ib }, 0 }, | |
3214 | { "subA", { Ebh1, Ib }, 0 }, | |
3215 | { "xorA", { Ebh1, Ib }, 0 }, | |
3216 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3217 | }, |
1ceb70f8 | 3218 | /* REG_81 */ |
252b5132 | 3219 | { |
bf890a93 IT |
3220 | { "addQ", { Evh1, Iv }, 0 }, |
3221 | { "orQ", { Evh1, Iv }, 0 }, | |
3222 | { "adcQ", { Evh1, Iv }, 0 }, | |
3223 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3224 | { "andQ", { Evh1, Iv }, 0 }, | |
3225 | { "subQ", { Evh1, Iv }, 0 }, | |
3226 | { "xorQ", { Evh1, Iv }, 0 }, | |
3227 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3228 | }, |
7148c369 | 3229 | /* REG_83 */ |
252b5132 | 3230 | { |
bf890a93 IT |
3231 | { "addQ", { Evh1, sIb }, 0 }, |
3232 | { "orQ", { Evh1, sIb }, 0 }, | |
3233 | { "adcQ", { Evh1, sIb }, 0 }, | |
3234 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3235 | { "andQ", { Evh1, sIb }, 0 }, | |
3236 | { "subQ", { Evh1, sIb }, 0 }, | |
3237 | { "xorQ", { Evh1, sIb }, 0 }, | |
3238 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3239 | }, |
1ceb70f8 | 3240 | /* REG_8F */ |
4e7d34a6 | 3241 | { |
bf890a93 | 3242 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3243 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3244 | { Bad_Opcode }, |
3245 | { Bad_Opcode }, | |
3246 | { Bad_Opcode }, | |
f88c9eb0 | 3247 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3248 | }, |
1ceb70f8 | 3249 | /* REG_C0 */ |
252b5132 | 3250 | { |
bf890a93 IT |
3251 | { "rolA", { Eb, Ib }, 0 }, |
3252 | { "rorA", { Eb, Ib }, 0 }, | |
3253 | { "rclA", { Eb, Ib }, 0 }, | |
3254 | { "rcrA", { Eb, Ib }, 0 }, | |
3255 | { "shlA", { Eb, Ib }, 0 }, | |
3256 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3257 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3258 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3259 | }, |
1ceb70f8 | 3260 | /* REG_C1 */ |
252b5132 | 3261 | { |
bf890a93 IT |
3262 | { "rolQ", { Ev, Ib }, 0 }, |
3263 | { "rorQ", { Ev, Ib }, 0 }, | |
3264 | { "rclQ", { Ev, Ib }, 0 }, | |
3265 | { "rcrQ", { Ev, Ib }, 0 }, | |
3266 | { "shlQ", { Ev, Ib }, 0 }, | |
3267 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3268 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3269 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3270 | }, |
1ceb70f8 | 3271 | /* REG_C6 */ |
4e7d34a6 | 3272 | { |
bf890a93 | 3273 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3274 | { Bad_Opcode }, |
3275 | { Bad_Opcode }, | |
3276 | { Bad_Opcode }, | |
3277 | { Bad_Opcode }, | |
3278 | { Bad_Opcode }, | |
3279 | { Bad_Opcode }, | |
3280 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3281 | }, |
1ceb70f8 | 3282 | /* REG_C7 */ |
4e7d34a6 | 3283 | { |
bf890a93 | 3284 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3285 | { Bad_Opcode }, |
3286 | { Bad_Opcode }, | |
3287 | { Bad_Opcode }, | |
3288 | { Bad_Opcode }, | |
3289 | { Bad_Opcode }, | |
3290 | { Bad_Opcode }, | |
3291 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3292 | }, |
1ceb70f8 | 3293 | /* REG_D0 */ |
252b5132 | 3294 | { |
bf890a93 IT |
3295 | { "rolA", { Eb, I1 }, 0 }, |
3296 | { "rorA", { Eb, I1 }, 0 }, | |
3297 | { "rclA", { Eb, I1 }, 0 }, | |
3298 | { "rcrA", { Eb, I1 }, 0 }, | |
3299 | { "shlA", { Eb, I1 }, 0 }, | |
3300 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3301 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3302 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3303 | }, |
1ceb70f8 | 3304 | /* REG_D1 */ |
252b5132 | 3305 | { |
bf890a93 IT |
3306 | { "rolQ", { Ev, I1 }, 0 }, |
3307 | { "rorQ", { Ev, I1 }, 0 }, | |
3308 | { "rclQ", { Ev, I1 }, 0 }, | |
3309 | { "rcrQ", { Ev, I1 }, 0 }, | |
3310 | { "shlQ", { Ev, I1 }, 0 }, | |
3311 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3312 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3313 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3314 | }, |
1ceb70f8 | 3315 | /* REG_D2 */ |
252b5132 | 3316 | { |
bf890a93 IT |
3317 | { "rolA", { Eb, CL }, 0 }, |
3318 | { "rorA", { Eb, CL }, 0 }, | |
3319 | { "rclA", { Eb, CL }, 0 }, | |
3320 | { "rcrA", { Eb, CL }, 0 }, | |
3321 | { "shlA", { Eb, CL }, 0 }, | |
3322 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3323 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3324 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3325 | }, |
1ceb70f8 | 3326 | /* REG_D3 */ |
252b5132 | 3327 | { |
bf890a93 IT |
3328 | { "rolQ", { Ev, CL }, 0 }, |
3329 | { "rorQ", { Ev, CL }, 0 }, | |
3330 | { "rclQ", { Ev, CL }, 0 }, | |
3331 | { "rcrQ", { Ev, CL }, 0 }, | |
3332 | { "shlQ", { Ev, CL }, 0 }, | |
3333 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3334 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3335 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3336 | }, |
1ceb70f8 | 3337 | /* REG_F6 */ |
252b5132 | 3338 | { |
bf890a93 | 3339 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3340 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3341 | { "notA", { Ebh1 }, 0 }, |
3342 | { "negA", { Ebh1 }, 0 }, | |
3343 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3344 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3345 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3346 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3347 | }, |
1ceb70f8 | 3348 | /* REG_F7 */ |
252b5132 | 3349 | { |
bf890a93 | 3350 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3351 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3352 | { "notQ", { Evh1 }, 0 }, |
3353 | { "negQ", { Evh1 }, 0 }, | |
3354 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3355 | { "imulQ", { Ev }, 0 }, | |
3356 | { "divQ", { Ev }, 0 }, | |
3357 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3358 | }, |
1ceb70f8 | 3359 | /* REG_FE */ |
252b5132 | 3360 | { |
bf890a93 IT |
3361 | { "incA", { Ebh1 }, 0 }, |
3362 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3363 | }, |
1ceb70f8 | 3364 | /* REG_FF */ |
252b5132 | 3365 | { |
bf890a93 IT |
3366 | { "incQ", { Evh1 }, 0 }, |
3367 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3368 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3369 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3370 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3371 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3372 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3373 | { Bad_Opcode }, |
252b5132 | 3374 | }, |
1ceb70f8 | 3375 | /* REG_0F00 */ |
252b5132 | 3376 | { |
bf890a93 IT |
3377 | { "sldtD", { Sv }, 0 }, |
3378 | { "strD", { Sv }, 0 }, | |
3379 | { "lldt", { Ew }, 0 }, | |
3380 | { "ltr", { Ew }, 0 }, | |
3381 | { "verr", { Ew }, 0 }, | |
3382 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3383 | { Bad_Opcode }, |
3384 | { Bad_Opcode }, | |
252b5132 | 3385 | }, |
1ceb70f8 | 3386 | /* REG_0F01 */ |
252b5132 | 3387 | { |
1ceb70f8 L |
3388 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3389 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3390 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3391 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3392 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3393 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3394 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3395 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3396 | }, |
b5b1fc4f | 3397 | /* REG_0F0D */ |
252b5132 | 3398 | { |
bf890a93 IT |
3399 | { "prefetch", { Mb }, 0 }, |
3400 | { "prefetchw", { Mb }, 0 }, | |
3401 | { "prefetchwt1", { Mb }, 0 }, | |
3402 | { "prefetch", { Mb }, 0 }, | |
3403 | { "prefetch", { Mb }, 0 }, | |
3404 | { "prefetch", { Mb }, 0 }, | |
3405 | { "prefetch", { Mb }, 0 }, | |
3406 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3407 | }, |
1ceb70f8 | 3408 | /* REG_0F18 */ |
252b5132 | 3409 | { |
1ceb70f8 L |
3410 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3411 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3412 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3413 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3414 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3415 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3416 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3417 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3418 | }, |
c48935d7 IT |
3419 | /* REG_0F1C_MOD_0 */ |
3420 | { | |
3421 | { "cldemote", { Mb }, 0 }, | |
3422 | { "nopQ", { Ev }, 0 }, | |
3423 | { "nopQ", { Ev }, 0 }, | |
3424 | { "nopQ", { Ev }, 0 }, | |
3425 | { "nopQ", { Ev }, 0 }, | |
3426 | { "nopQ", { Ev }, 0 }, | |
3427 | { "nopQ", { Ev }, 0 }, | |
3428 | { "nopQ", { Ev }, 0 }, | |
3429 | }, | |
603555e5 L |
3430 | /* REG_0F1E_MOD_3 */ |
3431 | { | |
3432 | { "nopQ", { Ev }, 0 }, | |
3433 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3434 | { "nopQ", { Ev }, 0 }, | |
3435 | { "nopQ", { Ev }, 0 }, | |
3436 | { "nopQ", { Ev }, 0 }, | |
3437 | { "nopQ", { Ev }, 0 }, | |
3438 | { "nopQ", { Ev }, 0 }, | |
3439 | { RM_TABLE (RM_0F1E_MOD_3_REG_7) }, | |
3440 | }, | |
1ceb70f8 | 3441 | /* REG_0F71 */ |
a6bd098c | 3442 | { |
592d1631 L |
3443 | { Bad_Opcode }, |
3444 | { Bad_Opcode }, | |
1ceb70f8 | 3445 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3446 | { Bad_Opcode }, |
1ceb70f8 | 3447 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3448 | { Bad_Opcode }, |
1ceb70f8 | 3449 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3450 | }, |
1ceb70f8 | 3451 | /* REG_0F72 */ |
a6bd098c | 3452 | { |
592d1631 L |
3453 | { Bad_Opcode }, |
3454 | { Bad_Opcode }, | |
1ceb70f8 | 3455 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3456 | { Bad_Opcode }, |
1ceb70f8 | 3457 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3458 | { Bad_Opcode }, |
1ceb70f8 | 3459 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3460 | }, |
1ceb70f8 | 3461 | /* REG_0F73 */ |
252b5132 | 3462 | { |
592d1631 L |
3463 | { Bad_Opcode }, |
3464 | { Bad_Opcode }, | |
1ceb70f8 L |
3465 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3466 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3467 | { Bad_Opcode }, |
3468 | { Bad_Opcode }, | |
1ceb70f8 L |
3469 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3470 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3471 | }, |
1ceb70f8 | 3472 | /* REG_0FA6 */ |
252b5132 | 3473 | { |
bf890a93 IT |
3474 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3475 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3476 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3477 | }, |
1ceb70f8 | 3478 | /* REG_0FA7 */ |
4e7d34a6 | 3479 | { |
bf890a93 IT |
3480 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3481 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3482 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3483 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3484 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3485 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3486 | }, |
1ceb70f8 | 3487 | /* REG_0FAE */ |
4e7d34a6 | 3488 | { |
1ceb70f8 L |
3489 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3490 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3491 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3492 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3493 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3494 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3495 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3496 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3497 | }, |
1ceb70f8 | 3498 | /* REG_0FBA */ |
252b5132 | 3499 | { |
592d1631 L |
3500 | { Bad_Opcode }, |
3501 | { Bad_Opcode }, | |
3502 | { Bad_Opcode }, | |
3503 | { Bad_Opcode }, | |
bf890a93 IT |
3504 | { "btQ", { Ev, Ib }, 0 }, |
3505 | { "btsQ", { Evh1, Ib }, 0 }, | |
3506 | { "btrQ", { Evh1, Ib }, 0 }, | |
3507 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3508 | }, |
1ceb70f8 | 3509 | /* REG_0FC7 */ |
c608c12e | 3510 | { |
592d1631 | 3511 | { Bad_Opcode }, |
bf890a93 | 3512 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3513 | { Bad_Opcode }, |
963f3586 IT |
3514 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3515 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3516 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3517 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3518 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3519 | }, |
592a252b | 3520 | /* REG_VEX_0F71 */ |
c0f3af97 | 3521 | { |
592d1631 L |
3522 | { Bad_Opcode }, |
3523 | { Bad_Opcode }, | |
592a252b | 3524 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3525 | { Bad_Opcode }, |
592a252b | 3526 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3527 | { Bad_Opcode }, |
592a252b | 3528 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3529 | }, |
592a252b | 3530 | /* REG_VEX_0F72 */ |
c0f3af97 | 3531 | { |
592d1631 L |
3532 | { Bad_Opcode }, |
3533 | { Bad_Opcode }, | |
592a252b | 3534 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3535 | { Bad_Opcode }, |
592a252b | 3536 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3537 | { Bad_Opcode }, |
592a252b | 3538 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3539 | }, |
592a252b | 3540 | /* REG_VEX_0F73 */ |
c0f3af97 | 3541 | { |
592d1631 L |
3542 | { Bad_Opcode }, |
3543 | { Bad_Opcode }, | |
592a252b L |
3544 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3545 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3546 | { Bad_Opcode }, |
3547 | { Bad_Opcode }, | |
592a252b L |
3548 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3549 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3550 | }, |
592a252b | 3551 | /* REG_VEX_0FAE */ |
c0f3af97 | 3552 | { |
592d1631 L |
3553 | { Bad_Opcode }, |
3554 | { Bad_Opcode }, | |
592a252b L |
3555 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3556 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3557 | }, |
f12dc422 L |
3558 | /* REG_VEX_0F38F3 */ |
3559 | { | |
3560 | { Bad_Opcode }, | |
3561 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3562 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3563 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3564 | }, | |
f88c9eb0 SP |
3565 | /* REG_XOP_LWPCB */ |
3566 | { | |
bf890a93 IT |
3567 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3568 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3569 | }, |
3570 | /* REG_XOP_LWP */ | |
3571 | { | |
bf890a93 IT |
3572 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, |
3573 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Iq }, 0 }, | |
f88c9eb0 | 3574 | }, |
2a2a0f38 QN |
3575 | /* REG_XOP_TBM_01 */ |
3576 | { | |
3577 | { Bad_Opcode }, | |
bf890a93 IT |
3578 | { "blcfill", { { OP_LWP_E, 0 }, Ev }, 0 }, |
3579 | { "blsfill", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3580 | { "blcs", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3581 | { "tzmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3582 | { "blcic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3583 | { "blsic", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
3584 | { "t1mskc", { { OP_LWP_E, 0 }, Ev }, 0 }, | |
2a2a0f38 QN |
3585 | }, |
3586 | /* REG_XOP_TBM_02 */ | |
3587 | { | |
3588 | { Bad_Opcode }, | |
bf890a93 | 3589 | { "blcmsk", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 QN |
3590 | { Bad_Opcode }, |
3591 | { Bad_Opcode }, | |
3592 | { Bad_Opcode }, | |
3593 | { Bad_Opcode }, | |
bf890a93 | 3594 | { "blci", { { OP_LWP_E, 0 }, Ev }, 0 }, |
2a2a0f38 | 3595 | }, |
43234a1e L |
3596 | #define NEED_REG_TABLE |
3597 | #include "i386-dis-evex.h" | |
3598 | #undef NEED_REG_TABLE | |
4e7d34a6 L |
3599 | }; |
3600 | ||
1ceb70f8 L |
3601 | static const struct dis386 prefix_table[][4] = { |
3602 | /* PREFIX_90 */ | |
252b5132 | 3603 | { |
bf890a93 IT |
3604 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3605 | { "pause", { XX }, 0 }, | |
3606 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3607 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3608 | }, |
4e7d34a6 | 3609 | |
603555e5 L |
3610 | /* PREFIX_MOD_0_0F01_REG_5 */ |
3611 | { | |
3612 | { Bad_Opcode }, | |
3613 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3614 | }, | |
3615 | ||
2234eee6 | 3616 | /* PREFIX_MOD_3_0F01_REG_5_RM_0 */ |
603555e5 L |
3617 | { |
3618 | { Bad_Opcode }, | |
2234eee6 | 3619 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3620 | }, |
3621 | ||
3622 | /* PREFIX_MOD_3_0F01_REG_5_RM_2 */ | |
3623 | { | |
3624 | { Bad_Opcode }, | |
c2f76402 | 3625 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3626 | }, |
3627 | ||
3233d7d0 IT |
3628 | /* PREFIX_0F09 */ |
3629 | { | |
3630 | { "wbinvd", { XX }, 0 }, | |
3631 | { "wbnoinvd", { XX }, 0 }, | |
3632 | }, | |
3633 | ||
1ceb70f8 | 3634 | /* PREFIX_0F10 */ |
cc0ec051 | 3635 | { |
507bd325 L |
3636 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3637 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3638 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3639 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3640 | }, |
4e7d34a6 | 3641 | |
1ceb70f8 | 3642 | /* PREFIX_0F11 */ |
30d1c836 | 3643 | { |
507bd325 L |
3644 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3645 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3646 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3647 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3648 | }, |
252b5132 | 3649 | |
1ceb70f8 | 3650 | /* PREFIX_0F12 */ |
c608c12e | 3651 | { |
1ceb70f8 | 3652 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 L |
3653 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
3654 | { "movlpd", { XM, EXq }, PREFIX_OPCODE }, | |
3655 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3656 | }, |
4e7d34a6 | 3657 | |
1ceb70f8 | 3658 | /* PREFIX_0F16 */ |
c608c12e | 3659 | { |
1ceb70f8 | 3660 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 L |
3661 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
3662 | { "movhpd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3663 | }, |
4e7d34a6 | 3664 | |
7e8b059b L |
3665 | /* PREFIX_0F1A */ |
3666 | { | |
3667 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3668 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3669 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3670 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3671 | }, |
3672 | ||
3673 | /* PREFIX_0F1B */ | |
3674 | { | |
3675 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3676 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3677 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3678 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3679 | }, |
3680 | ||
c48935d7 IT |
3681 | /* PREFIX_0F1C */ |
3682 | { | |
3683 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3684 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3685 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3686 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3687 | }, | |
3688 | ||
603555e5 L |
3689 | /* PREFIX_0F1E */ |
3690 | { | |
3691 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3692 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3693 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3694 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3695 | }, | |
3696 | ||
1ceb70f8 | 3697 | /* PREFIX_0F2A */ |
c608c12e | 3698 | { |
507bd325 L |
3699 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
3700 | { "cvtsi2ss%LQ", { XM, Ev }, PREFIX_OPCODE }, | |
3701 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, | |
bf890a93 | 3702 | { "cvtsi2sd%LQ", { XM, Ev }, 0 }, |
c608c12e | 3703 | }, |
4e7d34a6 | 3704 | |
1ceb70f8 | 3705 | /* PREFIX_0F2B */ |
c608c12e | 3706 | { |
75c135a8 L |
3707 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3708 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3709 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3710 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3711 | }, |
4e7d34a6 | 3712 | |
1ceb70f8 | 3713 | /* PREFIX_0F2C */ |
c608c12e | 3714 | { |
507bd325 | 3715 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3716 | { "cvttss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3717 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3718 | { "cvttsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3719 | }, |
4e7d34a6 | 3720 | |
1ceb70f8 | 3721 | /* PREFIX_0F2D */ |
c608c12e | 3722 | { |
507bd325 | 3723 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
9646c87b | 3724 | { "cvtss2si", { Gv, EXd }, PREFIX_OPCODE }, |
507bd325 | 3725 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
9646c87b | 3726 | { "cvtsd2si", { Gv, EXq }, PREFIX_OPCODE }, |
c608c12e | 3727 | }, |
4e7d34a6 | 3728 | |
1ceb70f8 | 3729 | /* PREFIX_0F2E */ |
c608c12e | 3730 | { |
bf890a93 | 3731 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3732 | { Bad_Opcode }, |
bf890a93 | 3733 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3734 | }, |
4e7d34a6 | 3735 | |
1ceb70f8 | 3736 | /* PREFIX_0F2F */ |
c608c12e | 3737 | { |
bf890a93 | 3738 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3739 | { Bad_Opcode }, |
bf890a93 | 3740 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3741 | }, |
4e7d34a6 | 3742 | |
1ceb70f8 | 3743 | /* PREFIX_0F51 */ |
c608c12e | 3744 | { |
507bd325 L |
3745 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3746 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3747 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3748 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3749 | }, |
4e7d34a6 | 3750 | |
1ceb70f8 | 3751 | /* PREFIX_0F52 */ |
c608c12e | 3752 | { |
507bd325 L |
3753 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3754 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3755 | }, |
4e7d34a6 | 3756 | |
1ceb70f8 | 3757 | /* PREFIX_0F53 */ |
c608c12e | 3758 | { |
507bd325 L |
3759 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3760 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3761 | }, |
4e7d34a6 | 3762 | |
1ceb70f8 | 3763 | /* PREFIX_0F58 */ |
c608c12e | 3764 | { |
507bd325 L |
3765 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3766 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3767 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3768 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3769 | }, |
4e7d34a6 | 3770 | |
1ceb70f8 | 3771 | /* PREFIX_0F59 */ |
c608c12e | 3772 | { |
507bd325 L |
3773 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3774 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3775 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3776 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3777 | }, |
4e7d34a6 | 3778 | |
1ceb70f8 | 3779 | /* PREFIX_0F5A */ |
041bd2e0 | 3780 | { |
507bd325 L |
3781 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3782 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3783 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3784 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3785 | }, |
4e7d34a6 | 3786 | |
1ceb70f8 | 3787 | /* PREFIX_0F5B */ |
041bd2e0 | 3788 | { |
507bd325 L |
3789 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3790 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3791 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3792 | }, |
4e7d34a6 | 3793 | |
1ceb70f8 | 3794 | /* PREFIX_0F5C */ |
041bd2e0 | 3795 | { |
507bd325 L |
3796 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3797 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3798 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3799 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3800 | }, |
4e7d34a6 | 3801 | |
1ceb70f8 | 3802 | /* PREFIX_0F5D */ |
041bd2e0 | 3803 | { |
507bd325 L |
3804 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3805 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3806 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3807 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3808 | }, |
4e7d34a6 | 3809 | |
1ceb70f8 | 3810 | /* PREFIX_0F5E */ |
041bd2e0 | 3811 | { |
507bd325 L |
3812 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3813 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3814 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3815 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3816 | }, |
4e7d34a6 | 3817 | |
1ceb70f8 | 3818 | /* PREFIX_0F5F */ |
041bd2e0 | 3819 | { |
507bd325 L |
3820 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3821 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3822 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3823 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3824 | }, |
4e7d34a6 | 3825 | |
1ceb70f8 | 3826 | /* PREFIX_0F60 */ |
041bd2e0 | 3827 | { |
507bd325 | 3828 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3829 | { Bad_Opcode }, |
507bd325 | 3830 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3831 | }, |
4e7d34a6 | 3832 | |
1ceb70f8 | 3833 | /* PREFIX_0F61 */ |
041bd2e0 | 3834 | { |
507bd325 | 3835 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3836 | { Bad_Opcode }, |
507bd325 | 3837 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3838 | }, |
4e7d34a6 | 3839 | |
1ceb70f8 | 3840 | /* PREFIX_0F62 */ |
041bd2e0 | 3841 | { |
507bd325 | 3842 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3843 | { Bad_Opcode }, |
507bd325 | 3844 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3845 | }, |
4e7d34a6 | 3846 | |
1ceb70f8 | 3847 | /* PREFIX_0F6C */ |
041bd2e0 | 3848 | { |
592d1631 L |
3849 | { Bad_Opcode }, |
3850 | { Bad_Opcode }, | |
507bd325 | 3851 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3852 | }, |
4e7d34a6 | 3853 | |
1ceb70f8 | 3854 | /* PREFIX_0F6D */ |
0f17484f | 3855 | { |
592d1631 L |
3856 | { Bad_Opcode }, |
3857 | { Bad_Opcode }, | |
507bd325 | 3858 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3859 | }, |
4e7d34a6 | 3860 | |
1ceb70f8 | 3861 | /* PREFIX_0F6F */ |
ca164297 | 3862 | { |
507bd325 L |
3863 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3864 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3865 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3866 | }, |
4e7d34a6 | 3867 | |
1ceb70f8 | 3868 | /* PREFIX_0F70 */ |
4e7d34a6 | 3869 | { |
507bd325 L |
3870 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3871 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3872 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3873 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3874 | }, |
3875 | ||
92fddf8e L |
3876 | /* PREFIX_0F73_REG_3 */ |
3877 | { | |
592d1631 L |
3878 | { Bad_Opcode }, |
3879 | { Bad_Opcode }, | |
bf890a93 | 3880 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3881 | }, |
3882 | ||
3883 | /* PREFIX_0F73_REG_7 */ | |
3884 | { | |
592d1631 L |
3885 | { Bad_Opcode }, |
3886 | { Bad_Opcode }, | |
bf890a93 | 3887 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3888 | }, |
3889 | ||
1ceb70f8 | 3890 | /* PREFIX_0F78 */ |
4e7d34a6 | 3891 | { |
bf890a93 | 3892 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3893 | { Bad_Opcode }, |
bf890a93 IT |
3894 | {"extrq", { XS, Ib, Ib }, 0 }, |
3895 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3896 | }, |
3897 | ||
1ceb70f8 | 3898 | /* PREFIX_0F79 */ |
4e7d34a6 | 3899 | { |
bf890a93 | 3900 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3901 | { Bad_Opcode }, |
bf890a93 IT |
3902 | {"extrq", { XM, XS }, 0 }, |
3903 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3904 | }, |
3905 | ||
1ceb70f8 | 3906 | /* PREFIX_0F7C */ |
ca164297 | 3907 | { |
592d1631 L |
3908 | { Bad_Opcode }, |
3909 | { Bad_Opcode }, | |
507bd325 L |
3910 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3911 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3912 | }, |
4e7d34a6 | 3913 | |
1ceb70f8 | 3914 | /* PREFIX_0F7D */ |
ca164297 | 3915 | { |
592d1631 L |
3916 | { Bad_Opcode }, |
3917 | { Bad_Opcode }, | |
507bd325 L |
3918 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3919 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3920 | }, |
4e7d34a6 | 3921 | |
1ceb70f8 | 3922 | /* PREFIX_0F7E */ |
ca164297 | 3923 | { |
507bd325 L |
3924 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3925 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3926 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3927 | }, |
4e7d34a6 | 3928 | |
1ceb70f8 | 3929 | /* PREFIX_0F7F */ |
ca164297 | 3930 | { |
507bd325 L |
3931 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3932 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3933 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3934 | }, |
4e7d34a6 | 3935 | |
c7b8aa3a L |
3936 | /* PREFIX_0FAE_REG_0 */ |
3937 | { | |
3938 | { Bad_Opcode }, | |
bf890a93 | 3939 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3940 | }, |
3941 | ||
3942 | /* PREFIX_0FAE_REG_1 */ | |
3943 | { | |
3944 | { Bad_Opcode }, | |
bf890a93 | 3945 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3946 | }, |
3947 | ||
3948 | /* PREFIX_0FAE_REG_2 */ | |
3949 | { | |
3950 | { Bad_Opcode }, | |
bf890a93 | 3951 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3952 | }, |
3953 | ||
3954 | /* PREFIX_0FAE_REG_3 */ | |
3955 | { | |
3956 | { Bad_Opcode }, | |
bf890a93 | 3957 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3958 | }, |
3959 | ||
6b40c462 L |
3960 | /* PREFIX_MOD_0_0FAE_REG_4 */ |
3961 | { | |
3962 | { "xsave", { FXSAVE }, 0 }, | |
3963 | { "ptwrite%LQ", { Edq }, 0 }, | |
3964 | }, | |
3965 | ||
3966 | /* PREFIX_MOD_3_0FAE_REG_4 */ | |
3967 | { | |
3968 | { Bad_Opcode }, | |
3969 | { "ptwrite%LQ", { Edq }, 0 }, | |
3970 | }, | |
3971 | ||
603555e5 L |
3972 | /* PREFIX_MOD_0_0FAE_REG_5 */ |
3973 | { | |
3974 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3975 | }, |
3976 | ||
3977 | /* PREFIX_MOD_3_0FAE_REG_5 */ | |
3978 | { | |
3979 | { "lfence", { Skip_MODRM }, 0 }, | |
3980 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3981 | }, |
3982 | ||
de89d0a3 | 3983 | /* PREFIX_MOD_0_0FAE_REG_6 */ |
c5e7287a | 3984 | { |
603555e5 L |
3985 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3986 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3987 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3988 | }, |
3989 | ||
de89d0a3 IT |
3990 | /* PREFIX_MOD_1_0FAE_REG_6 */ |
3991 | { | |
3992 | { RM_TABLE (RM_0FAE_REG_6) }, | |
3993 | { "umonitor", { Eva }, PREFIX_OPCODE }, | |
ae1d3843 L |
3994 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3995 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3996 | }, |
3997 | ||
963f3586 IT |
3998 | /* PREFIX_0FAE_REG_7 */ |
3999 | { | |
bf890a93 | 4000 | { "clflush", { Mb }, 0 }, |
963f3586 | 4001 | { Bad_Opcode }, |
bf890a93 | 4002 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
4003 | }, |
4004 | ||
1ceb70f8 | 4005 | /* PREFIX_0FB8 */ |
ca164297 | 4006 | { |
592d1631 | 4007 | { Bad_Opcode }, |
bf890a93 | 4008 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 4009 | }, |
4e7d34a6 | 4010 | |
f12dc422 L |
4011 | /* PREFIX_0FBC */ |
4012 | { | |
bf890a93 IT |
4013 | { "bsfS", { Gv, Ev }, 0 }, |
4014 | { "tzcntS", { Gv, Ev }, 0 }, | |
4015 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
4016 | }, |
4017 | ||
1ceb70f8 | 4018 | /* PREFIX_0FBD */ |
050dfa73 | 4019 | { |
bf890a93 IT |
4020 | { "bsrS", { Gv, Ev }, 0 }, |
4021 | { "lzcntS", { Gv, Ev }, 0 }, | |
4022 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
4023 | }, |
4024 | ||
1ceb70f8 | 4025 | /* PREFIX_0FC2 */ |
050dfa73 | 4026 | { |
507bd325 L |
4027 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
4028 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
4029 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
4030 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 4031 | }, |
246c51aa | 4032 | |
a8484f96 | 4033 | /* PREFIX_MOD_0_0FC3 */ |
4ee52178 | 4034 | { |
a8484f96 | 4035 | { "movntiS", { Ev, Gv }, PREFIX_OPCODE }, |
4ee52178 L |
4036 | }, |
4037 | ||
f24bcbaa | 4038 | /* PREFIX_MOD_0_0FC7_REG_6 */ |
92fddf8e | 4039 | { |
bf890a93 IT |
4040 | { "vmptrld",{ Mq }, 0 }, |
4041 | { "vmxon", { Mq }, 0 }, | |
4042 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
4043 | }, |
4044 | ||
f24bcbaa L |
4045 | /* PREFIX_MOD_3_0FC7_REG_6 */ |
4046 | { | |
4047 | { "rdrand", { Ev }, 0 }, | |
4048 | { Bad_Opcode }, | |
4049 | { "rdrand", { Ev }, 0 } | |
4050 | }, | |
4051 | ||
4052 | /* PREFIX_MOD_3_0FC7_REG_7 */ | |
4053 | { | |
4054 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 4055 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
4056 | { "rdseed", { Ev }, 0 }, |
4057 | }, | |
4058 | ||
1ceb70f8 | 4059 | /* PREFIX_0FD0 */ |
050dfa73 | 4060 | { |
592d1631 L |
4061 | { Bad_Opcode }, |
4062 | { Bad_Opcode }, | |
bf890a93 IT |
4063 | { "addsubpd", { XM, EXx }, 0 }, |
4064 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 4065 | }, |
050dfa73 | 4066 | |
1ceb70f8 | 4067 | /* PREFIX_0FD6 */ |
050dfa73 | 4068 | { |
592d1631 | 4069 | { Bad_Opcode }, |
bf890a93 IT |
4070 | { "movq2dq",{ XM, MS }, 0 }, |
4071 | { "movq", { EXqS, XM }, 0 }, | |
4072 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
4073 | }, |
4074 | ||
1ceb70f8 | 4075 | /* PREFIX_0FE6 */ |
7918206c | 4076 | { |
592d1631 | 4077 | { Bad_Opcode }, |
507bd325 L |
4078 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
4079 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
4080 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 4081 | }, |
8b38ad71 | 4082 | |
1ceb70f8 | 4083 | /* PREFIX_0FE7 */ |
8b38ad71 | 4084 | { |
507bd325 | 4085 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 4086 | { Bad_Opcode }, |
75c135a8 | 4087 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
4088 | }, |
4089 | ||
1ceb70f8 | 4090 | /* PREFIX_0FF0 */ |
4e7d34a6 | 4091 | { |
592d1631 L |
4092 | { Bad_Opcode }, |
4093 | { Bad_Opcode }, | |
4094 | { Bad_Opcode }, | |
1ceb70f8 | 4095 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
4096 | }, |
4097 | ||
1ceb70f8 | 4098 | /* PREFIX_0FF7 */ |
4e7d34a6 | 4099 | { |
507bd325 | 4100 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 4101 | { Bad_Opcode }, |
507bd325 | 4102 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 4103 | }, |
42903f7f | 4104 | |
1ceb70f8 | 4105 | /* PREFIX_0F3810 */ |
42903f7f | 4106 | { |
592d1631 L |
4107 | { Bad_Opcode }, |
4108 | { Bad_Opcode }, | |
507bd325 | 4109 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4110 | }, |
4111 | ||
1ceb70f8 | 4112 | /* PREFIX_0F3814 */ |
42903f7f | 4113 | { |
592d1631 L |
4114 | { Bad_Opcode }, |
4115 | { Bad_Opcode }, | |
507bd325 | 4116 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4117 | }, |
4118 | ||
1ceb70f8 | 4119 | /* PREFIX_0F3815 */ |
42903f7f | 4120 | { |
592d1631 L |
4121 | { Bad_Opcode }, |
4122 | { Bad_Opcode }, | |
507bd325 | 4123 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4124 | }, |
4125 | ||
1ceb70f8 | 4126 | /* PREFIX_0F3817 */ |
42903f7f | 4127 | { |
592d1631 L |
4128 | { Bad_Opcode }, |
4129 | { Bad_Opcode }, | |
507bd325 | 4130 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4131 | }, |
4132 | ||
1ceb70f8 | 4133 | /* PREFIX_0F3820 */ |
42903f7f | 4134 | { |
592d1631 L |
4135 | { Bad_Opcode }, |
4136 | { Bad_Opcode }, | |
507bd325 | 4137 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4138 | }, |
4139 | ||
1ceb70f8 | 4140 | /* PREFIX_0F3821 */ |
42903f7f | 4141 | { |
592d1631 L |
4142 | { Bad_Opcode }, |
4143 | { Bad_Opcode }, | |
507bd325 | 4144 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4145 | }, |
4146 | ||
1ceb70f8 | 4147 | /* PREFIX_0F3822 */ |
42903f7f | 4148 | { |
592d1631 L |
4149 | { Bad_Opcode }, |
4150 | { Bad_Opcode }, | |
507bd325 | 4151 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4152 | }, |
4153 | ||
1ceb70f8 | 4154 | /* PREFIX_0F3823 */ |
42903f7f | 4155 | { |
592d1631 L |
4156 | { Bad_Opcode }, |
4157 | { Bad_Opcode }, | |
507bd325 | 4158 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4159 | }, |
4160 | ||
1ceb70f8 | 4161 | /* PREFIX_0F3824 */ |
42903f7f | 4162 | { |
592d1631 L |
4163 | { Bad_Opcode }, |
4164 | { Bad_Opcode }, | |
507bd325 | 4165 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4166 | }, |
4167 | ||
1ceb70f8 | 4168 | /* PREFIX_0F3825 */ |
42903f7f | 4169 | { |
592d1631 L |
4170 | { Bad_Opcode }, |
4171 | { Bad_Opcode }, | |
507bd325 | 4172 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4173 | }, |
4174 | ||
1ceb70f8 | 4175 | /* PREFIX_0F3828 */ |
42903f7f | 4176 | { |
592d1631 L |
4177 | { Bad_Opcode }, |
4178 | { Bad_Opcode }, | |
507bd325 | 4179 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4180 | }, |
4181 | ||
1ceb70f8 | 4182 | /* PREFIX_0F3829 */ |
42903f7f | 4183 | { |
592d1631 L |
4184 | { Bad_Opcode }, |
4185 | { Bad_Opcode }, | |
507bd325 | 4186 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4187 | }, |
4188 | ||
1ceb70f8 | 4189 | /* PREFIX_0F382A */ |
42903f7f | 4190 | { |
592d1631 L |
4191 | { Bad_Opcode }, |
4192 | { Bad_Opcode }, | |
75c135a8 | 4193 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4194 | }, |
4195 | ||
1ceb70f8 | 4196 | /* PREFIX_0F382B */ |
42903f7f | 4197 | { |
592d1631 L |
4198 | { Bad_Opcode }, |
4199 | { Bad_Opcode }, | |
507bd325 | 4200 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4201 | }, |
4202 | ||
1ceb70f8 | 4203 | /* PREFIX_0F3830 */ |
42903f7f | 4204 | { |
592d1631 L |
4205 | { Bad_Opcode }, |
4206 | { Bad_Opcode }, | |
507bd325 | 4207 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4208 | }, |
4209 | ||
1ceb70f8 | 4210 | /* PREFIX_0F3831 */ |
42903f7f | 4211 | { |
592d1631 L |
4212 | { Bad_Opcode }, |
4213 | { Bad_Opcode }, | |
507bd325 | 4214 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4215 | }, |
4216 | ||
1ceb70f8 | 4217 | /* PREFIX_0F3832 */ |
42903f7f | 4218 | { |
592d1631 L |
4219 | { Bad_Opcode }, |
4220 | { Bad_Opcode }, | |
507bd325 | 4221 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4222 | }, |
4223 | ||
1ceb70f8 | 4224 | /* PREFIX_0F3833 */ |
42903f7f | 4225 | { |
592d1631 L |
4226 | { Bad_Opcode }, |
4227 | { Bad_Opcode }, | |
507bd325 | 4228 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4229 | }, |
4230 | ||
1ceb70f8 | 4231 | /* PREFIX_0F3834 */ |
42903f7f | 4232 | { |
592d1631 L |
4233 | { Bad_Opcode }, |
4234 | { Bad_Opcode }, | |
507bd325 | 4235 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4236 | }, |
4237 | ||
1ceb70f8 | 4238 | /* PREFIX_0F3835 */ |
42903f7f | 4239 | { |
592d1631 L |
4240 | { Bad_Opcode }, |
4241 | { Bad_Opcode }, | |
507bd325 | 4242 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4243 | }, |
4244 | ||
1ceb70f8 | 4245 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4246 | { |
592d1631 L |
4247 | { Bad_Opcode }, |
4248 | { Bad_Opcode }, | |
507bd325 | 4249 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4250 | }, |
4251 | ||
1ceb70f8 | 4252 | /* PREFIX_0F3838 */ |
42903f7f | 4253 | { |
592d1631 L |
4254 | { Bad_Opcode }, |
4255 | { Bad_Opcode }, | |
507bd325 | 4256 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4257 | }, |
4258 | ||
1ceb70f8 | 4259 | /* PREFIX_0F3839 */ |
42903f7f | 4260 | { |
592d1631 L |
4261 | { Bad_Opcode }, |
4262 | { Bad_Opcode }, | |
507bd325 | 4263 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4264 | }, |
4265 | ||
1ceb70f8 | 4266 | /* PREFIX_0F383A */ |
42903f7f | 4267 | { |
592d1631 L |
4268 | { Bad_Opcode }, |
4269 | { Bad_Opcode }, | |
507bd325 | 4270 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4271 | }, |
4272 | ||
1ceb70f8 | 4273 | /* PREFIX_0F383B */ |
42903f7f | 4274 | { |
592d1631 L |
4275 | { Bad_Opcode }, |
4276 | { Bad_Opcode }, | |
507bd325 | 4277 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4278 | }, |
4279 | ||
1ceb70f8 | 4280 | /* PREFIX_0F383C */ |
42903f7f | 4281 | { |
592d1631 L |
4282 | { Bad_Opcode }, |
4283 | { Bad_Opcode }, | |
507bd325 | 4284 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4285 | }, |
4286 | ||
1ceb70f8 | 4287 | /* PREFIX_0F383D */ |
42903f7f | 4288 | { |
592d1631 L |
4289 | { Bad_Opcode }, |
4290 | { Bad_Opcode }, | |
507bd325 | 4291 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4292 | }, |
4293 | ||
1ceb70f8 | 4294 | /* PREFIX_0F383E */ |
42903f7f | 4295 | { |
592d1631 L |
4296 | { Bad_Opcode }, |
4297 | { Bad_Opcode }, | |
507bd325 | 4298 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4299 | }, |
4300 | ||
1ceb70f8 | 4301 | /* PREFIX_0F383F */ |
42903f7f | 4302 | { |
592d1631 L |
4303 | { Bad_Opcode }, |
4304 | { Bad_Opcode }, | |
507bd325 | 4305 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4306 | }, |
4307 | ||
1ceb70f8 | 4308 | /* PREFIX_0F3840 */ |
42903f7f | 4309 | { |
592d1631 L |
4310 | { Bad_Opcode }, |
4311 | { Bad_Opcode }, | |
507bd325 | 4312 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4313 | }, |
4314 | ||
1ceb70f8 | 4315 | /* PREFIX_0F3841 */ |
42903f7f | 4316 | { |
592d1631 L |
4317 | { Bad_Opcode }, |
4318 | { Bad_Opcode }, | |
507bd325 | 4319 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4320 | }, |
4321 | ||
f1f8f695 L |
4322 | /* PREFIX_0F3880 */ |
4323 | { | |
592d1631 L |
4324 | { Bad_Opcode }, |
4325 | { Bad_Opcode }, | |
507bd325 | 4326 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4327 | }, |
4328 | ||
4329 | /* PREFIX_0F3881 */ | |
4330 | { | |
592d1631 L |
4331 | { Bad_Opcode }, |
4332 | { Bad_Opcode }, | |
507bd325 | 4333 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4334 | }, |
4335 | ||
6c30d220 L |
4336 | /* PREFIX_0F3882 */ |
4337 | { | |
4338 | { Bad_Opcode }, | |
4339 | { Bad_Opcode }, | |
507bd325 | 4340 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4341 | }, |
4342 | ||
a0046408 L |
4343 | /* PREFIX_0F38C8 */ |
4344 | { | |
507bd325 | 4345 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4346 | }, |
4347 | ||
4348 | /* PREFIX_0F38C9 */ | |
4349 | { | |
507bd325 | 4350 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4351 | }, |
4352 | ||
4353 | /* PREFIX_0F38CA */ | |
4354 | { | |
507bd325 | 4355 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4356 | }, |
4357 | ||
4358 | /* PREFIX_0F38CB */ | |
4359 | { | |
507bd325 | 4360 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4361 | }, |
4362 | ||
4363 | /* PREFIX_0F38CC */ | |
4364 | { | |
507bd325 | 4365 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4366 | }, |
4367 | ||
4368 | /* PREFIX_0F38CD */ | |
4369 | { | |
507bd325 | 4370 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4371 | }, |
4372 | ||
48521003 IT |
4373 | /* PREFIX_0F38CF */ |
4374 | { | |
4375 | { Bad_Opcode }, | |
4376 | { Bad_Opcode }, | |
4377 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4378 | }, | |
4379 | ||
c0f3af97 L |
4380 | /* PREFIX_0F38DB */ |
4381 | { | |
592d1631 L |
4382 | { Bad_Opcode }, |
4383 | { Bad_Opcode }, | |
507bd325 | 4384 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4385 | }, |
4386 | ||
4387 | /* PREFIX_0F38DC */ | |
4388 | { | |
592d1631 L |
4389 | { Bad_Opcode }, |
4390 | { Bad_Opcode }, | |
507bd325 | 4391 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4392 | }, |
4393 | ||
4394 | /* PREFIX_0F38DD */ | |
4395 | { | |
592d1631 L |
4396 | { Bad_Opcode }, |
4397 | { Bad_Opcode }, | |
507bd325 | 4398 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4399 | }, |
4400 | ||
4401 | /* PREFIX_0F38DE */ | |
4402 | { | |
592d1631 L |
4403 | { Bad_Opcode }, |
4404 | { Bad_Opcode }, | |
507bd325 | 4405 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4406 | }, |
4407 | ||
4408 | /* PREFIX_0F38DF */ | |
4409 | { | |
592d1631 L |
4410 | { Bad_Opcode }, |
4411 | { Bad_Opcode }, | |
507bd325 | 4412 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4413 | }, |
4414 | ||
1ceb70f8 | 4415 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4416 | { |
507bd325 | 4417 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4418 | { Bad_Opcode }, |
507bd325 L |
4419 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4420 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4421 | }, |
4422 | ||
1ceb70f8 | 4423 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4424 | { |
507bd325 | 4425 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4426 | { Bad_Opcode }, |
507bd325 L |
4427 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4428 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4429 | }, |
4430 | ||
603555e5 | 4431 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4432 | { |
4433 | { Bad_Opcode }, | |
603555e5 L |
4434 | { Bad_Opcode }, |
4435 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4436 | }, | |
4437 | ||
4438 | /* PREFIX_0F38F6 */ | |
4439 | { | |
4440 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4441 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4442 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4443 | { Bad_Opcode }, |
4444 | }, | |
4445 | ||
c0a30a9f L |
4446 | /* PREFIX_0F38F8 */ |
4447 | { | |
4448 | { Bad_Opcode }, | |
5d79adc4 | 4449 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4450 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4451 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4452 | }, |
4453 | ||
4454 | /* PREFIX_0F38F9 */ | |
4455 | { | |
4456 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4457 | }, | |
4458 | ||
1ceb70f8 | 4459 | /* PREFIX_0F3A08 */ |
42903f7f | 4460 | { |
592d1631 L |
4461 | { Bad_Opcode }, |
4462 | { Bad_Opcode }, | |
507bd325 | 4463 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4464 | }, |
4465 | ||
1ceb70f8 | 4466 | /* PREFIX_0F3A09 */ |
42903f7f | 4467 | { |
592d1631 L |
4468 | { Bad_Opcode }, |
4469 | { Bad_Opcode }, | |
507bd325 | 4470 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4471 | }, |
4472 | ||
1ceb70f8 | 4473 | /* PREFIX_0F3A0A */ |
42903f7f | 4474 | { |
592d1631 L |
4475 | { Bad_Opcode }, |
4476 | { Bad_Opcode }, | |
507bd325 | 4477 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4478 | }, |
4479 | ||
1ceb70f8 | 4480 | /* PREFIX_0F3A0B */ |
42903f7f | 4481 | { |
592d1631 L |
4482 | { Bad_Opcode }, |
4483 | { Bad_Opcode }, | |
507bd325 | 4484 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4485 | }, |
4486 | ||
1ceb70f8 | 4487 | /* PREFIX_0F3A0C */ |
42903f7f | 4488 | { |
592d1631 L |
4489 | { Bad_Opcode }, |
4490 | { Bad_Opcode }, | |
507bd325 | 4491 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4492 | }, |
4493 | ||
1ceb70f8 | 4494 | /* PREFIX_0F3A0D */ |
42903f7f | 4495 | { |
592d1631 L |
4496 | { Bad_Opcode }, |
4497 | { Bad_Opcode }, | |
507bd325 | 4498 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4499 | }, |
4500 | ||
1ceb70f8 | 4501 | /* PREFIX_0F3A0E */ |
42903f7f | 4502 | { |
592d1631 L |
4503 | { Bad_Opcode }, |
4504 | { Bad_Opcode }, | |
507bd325 | 4505 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4506 | }, |
4507 | ||
1ceb70f8 | 4508 | /* PREFIX_0F3A14 */ |
42903f7f | 4509 | { |
592d1631 L |
4510 | { Bad_Opcode }, |
4511 | { Bad_Opcode }, | |
507bd325 | 4512 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4513 | }, |
4514 | ||
1ceb70f8 | 4515 | /* PREFIX_0F3A15 */ |
42903f7f | 4516 | { |
592d1631 L |
4517 | { Bad_Opcode }, |
4518 | { Bad_Opcode }, | |
507bd325 | 4519 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4520 | }, |
4521 | ||
1ceb70f8 | 4522 | /* PREFIX_0F3A16 */ |
42903f7f | 4523 | { |
592d1631 L |
4524 | { Bad_Opcode }, |
4525 | { Bad_Opcode }, | |
507bd325 | 4526 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4527 | }, |
4528 | ||
1ceb70f8 | 4529 | /* PREFIX_0F3A17 */ |
42903f7f | 4530 | { |
592d1631 L |
4531 | { Bad_Opcode }, |
4532 | { Bad_Opcode }, | |
507bd325 | 4533 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4534 | }, |
4535 | ||
1ceb70f8 | 4536 | /* PREFIX_0F3A20 */ |
42903f7f | 4537 | { |
592d1631 L |
4538 | { Bad_Opcode }, |
4539 | { Bad_Opcode }, | |
507bd325 | 4540 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4541 | }, |
4542 | ||
1ceb70f8 | 4543 | /* PREFIX_0F3A21 */ |
42903f7f | 4544 | { |
592d1631 L |
4545 | { Bad_Opcode }, |
4546 | { Bad_Opcode }, | |
507bd325 | 4547 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4548 | }, |
4549 | ||
1ceb70f8 | 4550 | /* PREFIX_0F3A22 */ |
42903f7f | 4551 | { |
592d1631 L |
4552 | { Bad_Opcode }, |
4553 | { Bad_Opcode }, | |
507bd325 | 4554 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4555 | }, |
4556 | ||
1ceb70f8 | 4557 | /* PREFIX_0F3A40 */ |
42903f7f | 4558 | { |
592d1631 L |
4559 | { Bad_Opcode }, |
4560 | { Bad_Opcode }, | |
507bd325 | 4561 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4562 | }, |
4563 | ||
1ceb70f8 | 4564 | /* PREFIX_0F3A41 */ |
42903f7f | 4565 | { |
592d1631 L |
4566 | { Bad_Opcode }, |
4567 | { Bad_Opcode }, | |
507bd325 | 4568 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4569 | }, |
4570 | ||
1ceb70f8 | 4571 | /* PREFIX_0F3A42 */ |
42903f7f | 4572 | { |
592d1631 L |
4573 | { Bad_Opcode }, |
4574 | { Bad_Opcode }, | |
507bd325 | 4575 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4576 | }, |
381d071f | 4577 | |
c0f3af97 L |
4578 | /* PREFIX_0F3A44 */ |
4579 | { | |
592d1631 L |
4580 | { Bad_Opcode }, |
4581 | { Bad_Opcode }, | |
507bd325 | 4582 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4583 | }, |
4584 | ||
1ceb70f8 | 4585 | /* PREFIX_0F3A60 */ |
381d071f | 4586 | { |
592d1631 L |
4587 | { Bad_Opcode }, |
4588 | { Bad_Opcode }, | |
15c7c1d8 | 4589 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4590 | }, |
4591 | ||
1ceb70f8 | 4592 | /* PREFIX_0F3A61 */ |
381d071f | 4593 | { |
592d1631 L |
4594 | { Bad_Opcode }, |
4595 | { Bad_Opcode }, | |
15c7c1d8 | 4596 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4597 | }, |
4598 | ||
1ceb70f8 | 4599 | /* PREFIX_0F3A62 */ |
381d071f | 4600 | { |
592d1631 L |
4601 | { Bad_Opcode }, |
4602 | { Bad_Opcode }, | |
507bd325 | 4603 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4604 | }, |
4605 | ||
1ceb70f8 | 4606 | /* PREFIX_0F3A63 */ |
381d071f | 4607 | { |
592d1631 L |
4608 | { Bad_Opcode }, |
4609 | { Bad_Opcode }, | |
507bd325 | 4610 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4611 | }, |
09a2c6cf | 4612 | |
a0046408 L |
4613 | /* PREFIX_0F3ACC */ |
4614 | { | |
507bd325 | 4615 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4616 | }, |
4617 | ||
48521003 IT |
4618 | /* PREFIX_0F3ACE */ |
4619 | { | |
4620 | { Bad_Opcode }, | |
4621 | { Bad_Opcode }, | |
4622 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4623 | }, | |
4624 | ||
4625 | /* PREFIX_0F3ACF */ | |
4626 | { | |
4627 | { Bad_Opcode }, | |
4628 | { Bad_Opcode }, | |
4629 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4630 | }, | |
4631 | ||
c0f3af97 | 4632 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4633 | { |
592d1631 L |
4634 | { Bad_Opcode }, |
4635 | { Bad_Opcode }, | |
507bd325 | 4636 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4637 | }, |
4638 | ||
592a252b | 4639 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4640 | { |
ec6f095a L |
4641 | { "vmovups", { XM, EXx }, 0 }, |
4642 | { "vmovss", { XMVexScalar, VexScalar, EXdScalar }, 0 }, | |
4643 | { "vmovupd", { XM, EXx }, 0 }, | |
4644 | { "vmovsd", { XMVexScalar, VexScalar, EXqScalar }, 0 }, | |
09a2c6cf L |
4645 | }, |
4646 | ||
592a252b | 4647 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4648 | { |
ec6f095a L |
4649 | { "vmovups", { EXxS, XM }, 0 }, |
4650 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4651 | { "vmovupd", { EXxS, XM }, 0 }, | |
4652 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4653 | }, |
4654 | ||
592a252b | 4655 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4656 | { |
592a252b | 4657 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4658 | { "vmovsldup", { XM, EXx }, 0 }, |
592a252b | 4659 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
ec6f095a | 4660 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4661 | }, |
4662 | ||
592a252b | 4663 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4664 | { |
592a252b | 4665 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4666 | { "vmovshdup", { XM, EXx }, 0 }, |
592a252b | 4667 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
5f754f58 | 4668 | }, |
7c52e0e8 | 4669 | |
592a252b | 4670 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4671 | { |
592d1631 | 4672 | { Bad_Opcode }, |
592a252b | 4673 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_1) }, |
592d1631 | 4674 | { Bad_Opcode }, |
592a252b | 4675 | { VEX_LEN_TABLE (VEX_LEN_0F2A_P_3) }, |
5f754f58 | 4676 | }, |
7c52e0e8 | 4677 | |
592a252b | 4678 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4679 | { |
592d1631 | 4680 | { Bad_Opcode }, |
592a252b | 4681 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_1) }, |
592d1631 | 4682 | { Bad_Opcode }, |
592a252b | 4683 | { VEX_LEN_TABLE (VEX_LEN_0F2C_P_3) }, |
5f754f58 | 4684 | }, |
7c52e0e8 | 4685 | |
592a252b | 4686 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4687 | { |
592d1631 | 4688 | { Bad_Opcode }, |
592a252b | 4689 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_1) }, |
592d1631 | 4690 | { Bad_Opcode }, |
592a252b | 4691 | { VEX_LEN_TABLE (VEX_LEN_0F2D_P_3) }, |
7c52e0e8 L |
4692 | }, |
4693 | ||
592a252b | 4694 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4695 | { |
ec6f095a | 4696 | { "vucomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4697 | { Bad_Opcode }, |
ec6f095a | 4698 | { "vucomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4699 | }, |
4700 | ||
592a252b | 4701 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4702 | { |
ec6f095a | 4703 | { "vcomiss", { XMScalar, EXdScalar }, 0 }, |
592d1631 | 4704 | { Bad_Opcode }, |
ec6f095a | 4705 | { "vcomisd", { XMScalar, EXqScalar }, 0 }, |
7c52e0e8 L |
4706 | }, |
4707 | ||
43234a1e L |
4708 | /* PREFIX_VEX_0F41 */ |
4709 | { | |
4710 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4711 | { Bad_Opcode }, |
4712 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4713 | }, |
4714 | ||
4715 | /* PREFIX_VEX_0F42 */ | |
4716 | { | |
4717 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4718 | { Bad_Opcode }, |
4719 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4720 | }, |
4721 | ||
4722 | /* PREFIX_VEX_0F44 */ | |
4723 | { | |
4724 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4725 | { Bad_Opcode }, |
4726 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4727 | }, |
4728 | ||
4729 | /* PREFIX_VEX_0F45 */ | |
4730 | { | |
4731 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4732 | { Bad_Opcode }, |
4733 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4734 | }, |
4735 | ||
4736 | /* PREFIX_VEX_0F46 */ | |
4737 | { | |
4738 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4739 | { Bad_Opcode }, |
4740 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4741 | }, |
4742 | ||
4743 | /* PREFIX_VEX_0F47 */ | |
4744 | { | |
4745 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4746 | { Bad_Opcode }, |
4747 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4748 | }, |
4749 | ||
1ba585e8 | 4750 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4751 | { |
1ba585e8 | 4752 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4753 | { Bad_Opcode }, |
1ba585e8 IT |
4754 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4755 | }, | |
4756 | ||
4757 | /* PREFIX_VEX_0F4B */ | |
4758 | { | |
4759 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4760 | { Bad_Opcode }, |
4761 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4762 | }, | |
4763 | ||
592a252b | 4764 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4765 | { |
ec6f095a L |
4766 | { "vsqrtps", { XM, EXx }, 0 }, |
4767 | { "vsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4768 | { "vsqrtpd", { XM, EXx }, 0 }, | |
4769 | { "vsqrtsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4770 | }, |
4771 | ||
592a252b | 4772 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4773 | { |
ec6f095a L |
4774 | { "vrsqrtps", { XM, EXx }, 0 }, |
4775 | { "vrsqrtss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4776 | }, |
4777 | ||
592a252b | 4778 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4779 | { |
ec6f095a L |
4780 | { "vrcpps", { XM, EXx }, 0 }, |
4781 | { "vrcpss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
7c52e0e8 L |
4782 | }, |
4783 | ||
592a252b | 4784 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4785 | { |
ec6f095a L |
4786 | { "vaddps", { XM, Vex, EXx }, 0 }, |
4787 | { "vaddss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4788 | { "vaddpd", { XM, Vex, EXx }, 0 }, | |
4789 | { "vaddsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4790 | }, |
4791 | ||
592a252b | 4792 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4793 | { |
ec6f095a L |
4794 | { "vmulps", { XM, Vex, EXx }, 0 }, |
4795 | { "vmulss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4796 | { "vmulpd", { XM, Vex, EXx }, 0 }, | |
4797 | { "vmulsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4798 | }, |
4799 | ||
592a252b | 4800 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4801 | { |
ec6f095a L |
4802 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
4803 | { "vcvtss2sd", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4804 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, | |
4805 | { "vcvtsd2ss", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4806 | }, |
4807 | ||
592a252b | 4808 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4809 | { |
ec6f095a L |
4810 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4811 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4812 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4813 | }, |
4814 | ||
592a252b | 4815 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4816 | { |
ec6f095a L |
4817 | { "vsubps", { XM, Vex, EXx }, 0 }, |
4818 | { "vsubss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4819 | { "vsubpd", { XM, Vex, EXx }, 0 }, | |
4820 | { "vsubsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4821 | }, |
4822 | ||
592a252b | 4823 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4824 | { |
ec6f095a L |
4825 | { "vminps", { XM, Vex, EXx }, 0 }, |
4826 | { "vminss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4827 | { "vminpd", { XM, Vex, EXx }, 0 }, | |
4828 | { "vminsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4829 | }, |
4830 | ||
592a252b | 4831 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4832 | { |
ec6f095a L |
4833 | { "vdivps", { XM, Vex, EXx }, 0 }, |
4834 | { "vdivss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4835 | { "vdivpd", { XM, Vex, EXx }, 0 }, | |
4836 | { "vdivsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4837 | }, |
4838 | ||
592a252b | 4839 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4840 | { |
ec6f095a L |
4841 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
4842 | { "vmaxss", { XMScalar, VexScalar, EXdScalar }, 0 }, | |
4843 | { "vmaxpd", { XM, Vex, EXx }, 0 }, | |
4844 | { "vmaxsd", { XMScalar, VexScalar, EXqScalar }, 0 }, | |
7c52e0e8 L |
4845 | }, |
4846 | ||
592a252b | 4847 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4848 | { |
592d1631 L |
4849 | { Bad_Opcode }, |
4850 | { Bad_Opcode }, | |
ec6f095a | 4851 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4852 | }, |
4853 | ||
592a252b | 4854 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4855 | { |
592d1631 L |
4856 | { Bad_Opcode }, |
4857 | { Bad_Opcode }, | |
ec6f095a | 4858 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4859 | }, |
4860 | ||
592a252b | 4861 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4862 | { |
592d1631 L |
4863 | { Bad_Opcode }, |
4864 | { Bad_Opcode }, | |
ec6f095a | 4865 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4866 | }, |
4867 | ||
592a252b | 4868 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4869 | { |
592d1631 L |
4870 | { Bad_Opcode }, |
4871 | { Bad_Opcode }, | |
ec6f095a | 4872 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4873 | }, |
4874 | ||
592a252b | 4875 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4876 | { |
592d1631 L |
4877 | { Bad_Opcode }, |
4878 | { Bad_Opcode }, | |
ec6f095a | 4879 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4880 | }, |
4881 | ||
592a252b | 4882 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4883 | { |
592d1631 L |
4884 | { Bad_Opcode }, |
4885 | { Bad_Opcode }, | |
ec6f095a | 4886 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4887 | }, |
4888 | ||
592a252b | 4889 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4890 | { |
592d1631 L |
4891 | { Bad_Opcode }, |
4892 | { Bad_Opcode }, | |
ec6f095a | 4893 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4894 | }, |
6439fc28 | 4895 | |
592a252b | 4896 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4897 | { |
592d1631 L |
4898 | { Bad_Opcode }, |
4899 | { Bad_Opcode }, | |
ec6f095a | 4900 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4901 | }, |
4902 | ||
592a252b | 4903 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4904 | { |
592d1631 L |
4905 | { Bad_Opcode }, |
4906 | { Bad_Opcode }, | |
ec6f095a | 4907 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4908 | }, |
4909 | ||
592a252b | 4910 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4911 | { |
592d1631 L |
4912 | { Bad_Opcode }, |
4913 | { Bad_Opcode }, | |
ec6f095a | 4914 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4915 | }, |
4916 | ||
592a252b | 4917 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4918 | { |
592d1631 L |
4919 | { Bad_Opcode }, |
4920 | { Bad_Opcode }, | |
ec6f095a | 4921 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4922 | }, |
4923 | ||
592a252b | 4924 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4925 | { |
592d1631 L |
4926 | { Bad_Opcode }, |
4927 | { Bad_Opcode }, | |
ec6f095a | 4928 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4929 | }, |
4930 | ||
592a252b | 4931 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4932 | { |
592d1631 L |
4933 | { Bad_Opcode }, |
4934 | { Bad_Opcode }, | |
ec6f095a | 4935 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4936 | }, |
4937 | ||
592a252b | 4938 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4939 | { |
592d1631 L |
4940 | { Bad_Opcode }, |
4941 | { Bad_Opcode }, | |
ec6f095a | 4942 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4943 | }, |
4944 | ||
592a252b | 4945 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4946 | { |
592d1631 L |
4947 | { Bad_Opcode }, |
4948 | { Bad_Opcode }, | |
592a252b | 4949 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4950 | }, |
4951 | ||
592a252b | 4952 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4953 | { |
592d1631 | 4954 | { Bad_Opcode }, |
ec6f095a L |
4955 | { "vmovdqu", { XM, EXx }, 0 }, |
4956 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4957 | }, |
4958 | ||
592a252b | 4959 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4960 | { |
592d1631 | 4961 | { Bad_Opcode }, |
ec6f095a L |
4962 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4963 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4964 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4965 | }, |
4966 | ||
592a252b | 4967 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4968 | { |
592d1631 L |
4969 | { Bad_Opcode }, |
4970 | { Bad_Opcode }, | |
ec6f095a | 4971 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4972 | }, |
4973 | ||
592a252b | 4974 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4975 | { |
592d1631 L |
4976 | { Bad_Opcode }, |
4977 | { Bad_Opcode }, | |
ec6f095a | 4978 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4979 | }, |
4980 | ||
592a252b | 4981 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4982 | { |
592d1631 L |
4983 | { Bad_Opcode }, |
4984 | { Bad_Opcode }, | |
ec6f095a | 4985 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4986 | }, |
4987 | ||
592a252b | 4988 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4989 | { |
592d1631 L |
4990 | { Bad_Opcode }, |
4991 | { Bad_Opcode }, | |
ec6f095a | 4992 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4993 | }, |
4994 | ||
592a252b | 4995 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4996 | { |
592d1631 L |
4997 | { Bad_Opcode }, |
4998 | { Bad_Opcode }, | |
ec6f095a | 4999 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5000 | }, |
5001 | ||
592a252b | 5002 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 5003 | { |
592d1631 L |
5004 | { Bad_Opcode }, |
5005 | { Bad_Opcode }, | |
ec6f095a | 5006 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5007 | }, |
5008 | ||
592a252b | 5009 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 5010 | { |
592d1631 L |
5011 | { Bad_Opcode }, |
5012 | { Bad_Opcode }, | |
ec6f095a | 5013 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5014 | }, |
5015 | ||
592a252b | 5016 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 5017 | { |
592d1631 L |
5018 | { Bad_Opcode }, |
5019 | { Bad_Opcode }, | |
ec6f095a | 5020 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5021 | }, |
5022 | ||
592a252b | 5023 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 5024 | { |
592d1631 L |
5025 | { Bad_Opcode }, |
5026 | { Bad_Opcode }, | |
ec6f095a | 5027 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5028 | }, |
5029 | ||
592a252b | 5030 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 5031 | { |
592d1631 L |
5032 | { Bad_Opcode }, |
5033 | { Bad_Opcode }, | |
ec6f095a | 5034 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
5035 | }, |
5036 | ||
592a252b | 5037 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 5038 | { |
592d1631 L |
5039 | { Bad_Opcode }, |
5040 | { Bad_Opcode }, | |
ec6f095a | 5041 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5042 | }, |
5043 | ||
592a252b | 5044 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 5045 | { |
592d1631 L |
5046 | { Bad_Opcode }, |
5047 | { Bad_Opcode }, | |
ec6f095a | 5048 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5049 | }, |
5050 | ||
592a252b | 5051 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 5052 | { |
592d1631 L |
5053 | { Bad_Opcode }, |
5054 | { Bad_Opcode }, | |
ec6f095a | 5055 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5056 | }, |
5057 | ||
592a252b | 5058 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 5059 | { |
ec6f095a | 5060 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 5064 | { |
592d1631 L |
5065 | { Bad_Opcode }, |
5066 | { Bad_Opcode }, | |
ec6f095a L |
5067 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
5068 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5069 | }, |
5070 | ||
592a252b | 5071 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 5072 | { |
592d1631 L |
5073 | { Bad_Opcode }, |
5074 | { Bad_Opcode }, | |
ec6f095a L |
5075 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
5076 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5077 | }, |
5078 | ||
592a252b | 5079 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 5080 | { |
592d1631 | 5081 | { Bad_Opcode }, |
592a252b L |
5082 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
5083 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
5084 | }, |
5085 | ||
592a252b | 5086 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 5087 | { |
592d1631 | 5088 | { Bad_Opcode }, |
ec6f095a L |
5089 | { "vmovdqu", { EXxS, XM }, 0 }, |
5090 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
5091 | }, |
5092 | ||
43234a1e L |
5093 | /* PREFIX_VEX_0F90 */ |
5094 | { | |
5095 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
5096 | { Bad_Opcode }, |
5097 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
5098 | }, |
5099 | ||
5100 | /* PREFIX_VEX_0F91 */ | |
5101 | { | |
5102 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
5103 | { Bad_Opcode }, |
5104 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
5105 | }, |
5106 | ||
5107 | /* PREFIX_VEX_0F92 */ | |
5108 | { | |
5109 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 5110 | { Bad_Opcode }, |
90a915bf | 5111 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 5112 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
5113 | }, |
5114 | ||
5115 | /* PREFIX_VEX_0F93 */ | |
5116 | { | |
5117 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5118 | { Bad_Opcode }, |
90a915bf | 5119 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5120 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5121 | }, |
5122 | ||
5123 | /* PREFIX_VEX_0F98 */ | |
5124 | { | |
5125 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5126 | { Bad_Opcode }, |
5127 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5128 | }, | |
5129 | ||
5130 | /* PREFIX_VEX_0F99 */ | |
5131 | { | |
5132 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5133 | { Bad_Opcode }, | |
5134 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5135 | }, |
5136 | ||
592a252b | 5137 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5138 | { |
ec6f095a L |
5139 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5140 | { "vcmpss", { XMScalar, VexScalar, EXdScalar, VCMP }, 0 }, | |
5141 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, | |
5142 | { "vcmpsd", { XMScalar, VexScalar, EXqScalar, VCMP }, 0 }, | |
c0f3af97 L |
5143 | }, |
5144 | ||
592a252b | 5145 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5146 | { |
592d1631 L |
5147 | { Bad_Opcode }, |
5148 | { Bad_Opcode }, | |
592a252b | 5149 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5150 | }, |
5151 | ||
592a252b | 5152 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5153 | { |
592d1631 L |
5154 | { Bad_Opcode }, |
5155 | { Bad_Opcode }, | |
592a252b | 5156 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5157 | }, |
5158 | ||
592a252b | 5159 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5160 | { |
592d1631 L |
5161 | { Bad_Opcode }, |
5162 | { Bad_Opcode }, | |
ec6f095a L |
5163 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5164 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5165 | }, |
5166 | ||
592a252b | 5167 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5168 | { |
592d1631 L |
5169 | { Bad_Opcode }, |
5170 | { Bad_Opcode }, | |
ec6f095a | 5171 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5172 | }, |
5173 | ||
592a252b | 5174 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5175 | { |
592d1631 L |
5176 | { Bad_Opcode }, |
5177 | { Bad_Opcode }, | |
ec6f095a | 5178 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5179 | }, |
5180 | ||
592a252b | 5181 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5182 | { |
592d1631 L |
5183 | { Bad_Opcode }, |
5184 | { Bad_Opcode }, | |
ec6f095a | 5185 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5186 | }, |
5187 | ||
592a252b | 5188 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5189 | { |
592d1631 L |
5190 | { Bad_Opcode }, |
5191 | { Bad_Opcode }, | |
ec6f095a | 5192 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5193 | }, |
5194 | ||
592a252b | 5195 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5196 | { |
592d1631 L |
5197 | { Bad_Opcode }, |
5198 | { Bad_Opcode }, | |
ec6f095a | 5199 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5200 | }, |
5201 | ||
592a252b | 5202 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5203 | { |
592d1631 L |
5204 | { Bad_Opcode }, |
5205 | { Bad_Opcode }, | |
592a252b | 5206 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5207 | }, |
5208 | ||
592a252b | 5209 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5210 | { |
592d1631 L |
5211 | { Bad_Opcode }, |
5212 | { Bad_Opcode }, | |
592a252b | 5213 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5214 | }, |
5215 | ||
592a252b | 5216 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5217 | { |
592d1631 L |
5218 | { Bad_Opcode }, |
5219 | { Bad_Opcode }, | |
ec6f095a | 5220 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5221 | }, |
5222 | ||
592a252b | 5223 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5224 | { |
592d1631 L |
5225 | { Bad_Opcode }, |
5226 | { Bad_Opcode }, | |
ec6f095a | 5227 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5228 | }, |
5229 | ||
592a252b | 5230 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5231 | { |
592d1631 L |
5232 | { Bad_Opcode }, |
5233 | { Bad_Opcode }, | |
ec6f095a | 5234 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5235 | }, |
5236 | ||
592a252b | 5237 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5238 | { |
592d1631 L |
5239 | { Bad_Opcode }, |
5240 | { Bad_Opcode }, | |
ec6f095a | 5241 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5242 | }, |
5243 | ||
592a252b | 5244 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5245 | { |
592d1631 L |
5246 | { Bad_Opcode }, |
5247 | { Bad_Opcode }, | |
ec6f095a | 5248 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5249 | }, |
5250 | ||
592a252b | 5251 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5252 | { |
592d1631 L |
5253 | { Bad_Opcode }, |
5254 | { Bad_Opcode }, | |
ec6f095a | 5255 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5256 | }, |
5257 | ||
592a252b | 5258 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5259 | { |
592d1631 L |
5260 | { Bad_Opcode }, |
5261 | { Bad_Opcode }, | |
ec6f095a | 5262 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5263 | }, |
5264 | ||
592a252b | 5265 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5266 | { |
592d1631 L |
5267 | { Bad_Opcode }, |
5268 | { Bad_Opcode }, | |
ec6f095a | 5269 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5270 | }, |
5271 | ||
592a252b | 5272 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5273 | { |
592d1631 L |
5274 | { Bad_Opcode }, |
5275 | { Bad_Opcode }, | |
ec6f095a | 5276 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5277 | }, |
5278 | ||
592a252b | 5279 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5280 | { |
592d1631 L |
5281 | { Bad_Opcode }, |
5282 | { Bad_Opcode }, | |
ec6f095a | 5283 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5284 | }, |
5285 | ||
592a252b | 5286 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5287 | { |
592d1631 L |
5288 | { Bad_Opcode }, |
5289 | { Bad_Opcode }, | |
ec6f095a | 5290 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5291 | }, |
5292 | ||
592a252b | 5293 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5294 | { |
592d1631 L |
5295 | { Bad_Opcode }, |
5296 | { Bad_Opcode }, | |
ec6f095a | 5297 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5298 | }, |
5299 | ||
592a252b | 5300 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5301 | { |
592d1631 L |
5302 | { Bad_Opcode }, |
5303 | { Bad_Opcode }, | |
ec6f095a | 5304 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5305 | }, |
5306 | ||
592a252b | 5307 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5308 | { |
592d1631 L |
5309 | { Bad_Opcode }, |
5310 | { Bad_Opcode }, | |
ec6f095a | 5311 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5312 | }, |
5313 | ||
592a252b | 5314 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5315 | { |
592d1631 | 5316 | { Bad_Opcode }, |
ec6f095a L |
5317 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5318 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5319 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5320 | }, |
5321 | ||
592a252b | 5322 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5323 | { |
592d1631 L |
5324 | { Bad_Opcode }, |
5325 | { Bad_Opcode }, | |
592a252b | 5326 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5327 | }, |
5328 | ||
592a252b | 5329 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5330 | { |
592d1631 L |
5331 | { Bad_Opcode }, |
5332 | { Bad_Opcode }, | |
ec6f095a | 5333 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5334 | }, |
5335 | ||
592a252b | 5336 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5337 | { |
592d1631 L |
5338 | { Bad_Opcode }, |
5339 | { Bad_Opcode }, | |
ec6f095a | 5340 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5341 | }, |
5342 | ||
592a252b | 5343 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5344 | { |
592d1631 L |
5345 | { Bad_Opcode }, |
5346 | { Bad_Opcode }, | |
ec6f095a | 5347 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5348 | }, |
5349 | ||
592a252b | 5350 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5351 | { |
592d1631 L |
5352 | { Bad_Opcode }, |
5353 | { Bad_Opcode }, | |
ec6f095a | 5354 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5355 | }, |
5356 | ||
592a252b | 5357 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5358 | { |
592d1631 L |
5359 | { Bad_Opcode }, |
5360 | { Bad_Opcode }, | |
ec6f095a | 5361 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5362 | }, |
5363 | ||
592a252b | 5364 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5365 | { |
592d1631 L |
5366 | { Bad_Opcode }, |
5367 | { Bad_Opcode }, | |
ec6f095a | 5368 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5369 | }, |
5370 | ||
592a252b | 5371 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5372 | { |
592d1631 L |
5373 | { Bad_Opcode }, |
5374 | { Bad_Opcode }, | |
ec6f095a | 5375 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5376 | }, |
5377 | ||
592a252b | 5378 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5379 | { |
592d1631 L |
5380 | { Bad_Opcode }, |
5381 | { Bad_Opcode }, | |
ec6f095a | 5382 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5383 | }, |
5384 | ||
592a252b | 5385 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5386 | { |
592d1631 L |
5387 | { Bad_Opcode }, |
5388 | { Bad_Opcode }, | |
5389 | { Bad_Opcode }, | |
592a252b | 5390 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5391 | }, |
5392 | ||
592a252b | 5393 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5394 | { |
592d1631 L |
5395 | { Bad_Opcode }, |
5396 | { Bad_Opcode }, | |
ec6f095a | 5397 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5398 | }, |
5399 | ||
592a252b | 5400 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5401 | { |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
ec6f095a | 5404 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5405 | }, |
5406 | ||
592a252b | 5407 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5408 | { |
592d1631 L |
5409 | { Bad_Opcode }, |
5410 | { Bad_Opcode }, | |
ec6f095a | 5411 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5412 | }, |
5413 | ||
592a252b | 5414 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5415 | { |
592d1631 L |
5416 | { Bad_Opcode }, |
5417 | { Bad_Opcode }, | |
ec6f095a | 5418 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5419 | }, |
5420 | ||
592a252b | 5421 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5422 | { |
592d1631 L |
5423 | { Bad_Opcode }, |
5424 | { Bad_Opcode }, | |
ec6f095a | 5425 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5426 | }, |
5427 | ||
592a252b | 5428 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5429 | { |
592d1631 L |
5430 | { Bad_Opcode }, |
5431 | { Bad_Opcode }, | |
ec6f095a | 5432 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5433 | }, |
5434 | ||
592a252b | 5435 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5436 | { |
592d1631 L |
5437 | { Bad_Opcode }, |
5438 | { Bad_Opcode }, | |
592a252b | 5439 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5440 | }, |
5441 | ||
592a252b | 5442 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5443 | { |
592d1631 L |
5444 | { Bad_Opcode }, |
5445 | { Bad_Opcode }, | |
ec6f095a | 5446 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5447 | }, |
5448 | ||
592a252b | 5449 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5450 | { |
592d1631 L |
5451 | { Bad_Opcode }, |
5452 | { Bad_Opcode }, | |
ec6f095a | 5453 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5454 | }, |
5455 | ||
592a252b | 5456 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5457 | { |
592d1631 L |
5458 | { Bad_Opcode }, |
5459 | { Bad_Opcode }, | |
ec6f095a | 5460 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5461 | }, |
5462 | ||
592a252b | 5463 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5464 | { |
592d1631 L |
5465 | { Bad_Opcode }, |
5466 | { Bad_Opcode }, | |
ec6f095a | 5467 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5468 | }, |
5469 | ||
592a252b | 5470 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5471 | { |
592d1631 L |
5472 | { Bad_Opcode }, |
5473 | { Bad_Opcode }, | |
ec6f095a | 5474 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5475 | }, |
5476 | ||
592a252b | 5477 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5478 | { |
592d1631 L |
5479 | { Bad_Opcode }, |
5480 | { Bad_Opcode }, | |
ec6f095a | 5481 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5482 | }, |
5483 | ||
592a252b | 5484 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5485 | { |
592d1631 L |
5486 | { Bad_Opcode }, |
5487 | { Bad_Opcode }, | |
ec6f095a | 5488 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5489 | }, |
5490 | ||
592a252b | 5491 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5492 | { |
592d1631 L |
5493 | { Bad_Opcode }, |
5494 | { Bad_Opcode }, | |
ec6f095a | 5495 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5496 | }, |
5497 | ||
592a252b | 5498 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5499 | { |
592d1631 L |
5500 | { Bad_Opcode }, |
5501 | { Bad_Opcode }, | |
ec6f095a | 5502 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5503 | }, |
5504 | ||
592a252b | 5505 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5506 | { |
592d1631 L |
5507 | { Bad_Opcode }, |
5508 | { Bad_Opcode }, | |
ec6f095a | 5509 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5510 | }, |
5511 | ||
592a252b | 5512 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5513 | { |
592d1631 L |
5514 | { Bad_Opcode }, |
5515 | { Bad_Opcode }, | |
ec6f095a | 5516 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5517 | }, |
5518 | ||
592a252b | 5519 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5520 | { |
592d1631 L |
5521 | { Bad_Opcode }, |
5522 | { Bad_Opcode }, | |
ec6f095a | 5523 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5524 | }, |
5525 | ||
592a252b | 5526 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5527 | { |
592d1631 L |
5528 | { Bad_Opcode }, |
5529 | { Bad_Opcode }, | |
ec6f095a | 5530 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5531 | }, |
5532 | ||
592a252b | 5533 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5534 | { |
592d1631 L |
5535 | { Bad_Opcode }, |
5536 | { Bad_Opcode }, | |
ec6f095a | 5537 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5538 | }, |
5539 | ||
592a252b | 5540 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5541 | { |
592d1631 L |
5542 | { Bad_Opcode }, |
5543 | { Bad_Opcode }, | |
ec6f095a | 5544 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5545 | }, |
5546 | ||
592a252b | 5547 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5548 | { |
592d1631 L |
5549 | { Bad_Opcode }, |
5550 | { Bad_Opcode }, | |
ec6f095a | 5551 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5552 | }, |
5553 | ||
592a252b | 5554 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5555 | { |
592d1631 L |
5556 | { Bad_Opcode }, |
5557 | { Bad_Opcode }, | |
ec6f095a | 5558 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5559 | }, |
5560 | ||
592a252b | 5561 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5562 | { |
592d1631 L |
5563 | { Bad_Opcode }, |
5564 | { Bad_Opcode }, | |
ec6f095a | 5565 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5566 | }, |
5567 | ||
592a252b | 5568 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5569 | { |
592d1631 L |
5570 | { Bad_Opcode }, |
5571 | { Bad_Opcode }, | |
ec6f095a | 5572 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5573 | }, |
5574 | ||
592a252b | 5575 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5576 | { |
592d1631 L |
5577 | { Bad_Opcode }, |
5578 | { Bad_Opcode }, | |
592a252b | 5579 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5580 | }, |
5581 | ||
592a252b | 5582 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5583 | { |
592d1631 L |
5584 | { Bad_Opcode }, |
5585 | { Bad_Opcode }, | |
592a252b | 5586 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5587 | }, |
5588 | ||
592a252b | 5589 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5590 | { |
592d1631 L |
5591 | { Bad_Opcode }, |
5592 | { Bad_Opcode }, | |
592a252b | 5593 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5594 | }, |
5595 | ||
592a252b | 5596 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5597 | { |
592d1631 L |
5598 | { Bad_Opcode }, |
5599 | { Bad_Opcode }, | |
592a252b | 5600 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5601 | }, |
5602 | ||
592a252b | 5603 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5604 | { |
5605 | { Bad_Opcode }, | |
5606 | { Bad_Opcode }, | |
bf890a93 | 5607 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, |
c7b8aa3a L |
5608 | }, |
5609 | ||
6c30d220 L |
5610 | /* PREFIX_VEX_0F3816 */ |
5611 | { | |
5612 | { Bad_Opcode }, | |
5613 | { Bad_Opcode }, | |
5614 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5615 | }, | |
5616 | ||
592a252b | 5617 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5618 | { |
592d1631 L |
5619 | { Bad_Opcode }, |
5620 | { Bad_Opcode }, | |
ec6f095a | 5621 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5622 | }, |
5623 | ||
592a252b | 5624 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5625 | { |
592d1631 L |
5626 | { Bad_Opcode }, |
5627 | { Bad_Opcode }, | |
6c30d220 | 5628 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5629 | }, |
5630 | ||
592a252b | 5631 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5632 | { |
592d1631 L |
5633 | { Bad_Opcode }, |
5634 | { Bad_Opcode }, | |
6c30d220 | 5635 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5636 | }, |
5637 | ||
592a252b | 5638 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5639 | { |
592d1631 L |
5640 | { Bad_Opcode }, |
5641 | { Bad_Opcode }, | |
592a252b | 5642 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5643 | }, |
5644 | ||
592a252b | 5645 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5646 | { |
592d1631 L |
5647 | { Bad_Opcode }, |
5648 | { Bad_Opcode }, | |
ec6f095a | 5649 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5650 | }, |
5651 | ||
592a252b | 5652 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5653 | { |
592d1631 L |
5654 | { Bad_Opcode }, |
5655 | { Bad_Opcode }, | |
ec6f095a | 5656 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5657 | }, |
5658 | ||
592a252b | 5659 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5660 | { |
592d1631 L |
5661 | { Bad_Opcode }, |
5662 | { Bad_Opcode }, | |
ec6f095a | 5663 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5664 | }, |
5665 | ||
592a252b | 5666 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5667 | { |
592d1631 L |
5668 | { Bad_Opcode }, |
5669 | { Bad_Opcode }, | |
ec6f095a | 5670 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5671 | }, |
5672 | ||
592a252b | 5673 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5674 | { |
592d1631 L |
5675 | { Bad_Opcode }, |
5676 | { Bad_Opcode }, | |
ec6f095a | 5677 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5678 | }, |
5679 | ||
592a252b | 5680 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5681 | { |
592d1631 L |
5682 | { Bad_Opcode }, |
5683 | { Bad_Opcode }, | |
ec6f095a | 5684 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5685 | }, |
5686 | ||
592a252b | 5687 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5688 | { |
592d1631 L |
5689 | { Bad_Opcode }, |
5690 | { Bad_Opcode }, | |
ec6f095a | 5691 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5692 | }, |
5693 | ||
592a252b | 5694 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5695 | { |
592d1631 L |
5696 | { Bad_Opcode }, |
5697 | { Bad_Opcode }, | |
ec6f095a | 5698 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5699 | }, |
5700 | ||
592a252b | 5701 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5702 | { |
592d1631 L |
5703 | { Bad_Opcode }, |
5704 | { Bad_Opcode }, | |
ec6f095a | 5705 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5706 | }, |
5707 | ||
592a252b | 5708 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5709 | { |
592d1631 L |
5710 | { Bad_Opcode }, |
5711 | { Bad_Opcode }, | |
ec6f095a | 5712 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5713 | }, |
5714 | ||
592a252b | 5715 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5716 | { |
592d1631 L |
5717 | { Bad_Opcode }, |
5718 | { Bad_Opcode }, | |
ec6f095a | 5719 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5720 | }, |
5721 | ||
592a252b | 5722 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5723 | { |
592d1631 L |
5724 | { Bad_Opcode }, |
5725 | { Bad_Opcode }, | |
592a252b | 5726 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5727 | }, |
5728 | ||
592a252b | 5729 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5730 | { |
592d1631 L |
5731 | { Bad_Opcode }, |
5732 | { Bad_Opcode }, | |
ec6f095a | 5733 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5734 | }, |
5735 | ||
592a252b | 5736 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5737 | { |
592d1631 L |
5738 | { Bad_Opcode }, |
5739 | { Bad_Opcode }, | |
592a252b | 5740 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5741 | }, |
5742 | ||
592a252b | 5743 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5744 | { |
592d1631 L |
5745 | { Bad_Opcode }, |
5746 | { Bad_Opcode }, | |
592a252b | 5747 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5748 | }, |
5749 | ||
592a252b | 5750 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5751 | { |
592d1631 L |
5752 | { Bad_Opcode }, |
5753 | { Bad_Opcode }, | |
592a252b | 5754 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5755 | }, |
5756 | ||
592a252b | 5757 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5758 | { |
592d1631 L |
5759 | { Bad_Opcode }, |
5760 | { Bad_Opcode }, | |
592a252b | 5761 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5762 | }, |
5763 | ||
592a252b | 5764 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5765 | { |
592d1631 L |
5766 | { Bad_Opcode }, |
5767 | { Bad_Opcode }, | |
ec6f095a | 5768 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5769 | }, |
5770 | ||
592a252b | 5771 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5772 | { |
592d1631 L |
5773 | { Bad_Opcode }, |
5774 | { Bad_Opcode }, | |
ec6f095a | 5775 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5776 | }, |
5777 | ||
592a252b | 5778 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5779 | { |
592d1631 L |
5780 | { Bad_Opcode }, |
5781 | { Bad_Opcode }, | |
ec6f095a | 5782 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5783 | }, |
5784 | ||
592a252b | 5785 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5786 | { |
592d1631 L |
5787 | { Bad_Opcode }, |
5788 | { Bad_Opcode }, | |
ec6f095a | 5789 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5790 | }, |
5791 | ||
592a252b | 5792 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5793 | { |
592d1631 L |
5794 | { Bad_Opcode }, |
5795 | { Bad_Opcode }, | |
ec6f095a | 5796 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5797 | }, |
5798 | ||
592a252b | 5799 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5800 | { |
592d1631 L |
5801 | { Bad_Opcode }, |
5802 | { Bad_Opcode }, | |
ec6f095a | 5803 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5804 | }, |
5805 | ||
5806 | /* PREFIX_VEX_0F3836 */ | |
5807 | { | |
5808 | { Bad_Opcode }, | |
5809 | { Bad_Opcode }, | |
5810 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5811 | }, |
5812 | ||
592a252b | 5813 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5814 | { |
592d1631 L |
5815 | { Bad_Opcode }, |
5816 | { Bad_Opcode }, | |
ec6f095a | 5817 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5818 | }, |
5819 | ||
592a252b | 5820 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5821 | { |
592d1631 L |
5822 | { Bad_Opcode }, |
5823 | { Bad_Opcode }, | |
ec6f095a | 5824 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5825 | }, |
5826 | ||
592a252b | 5827 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5828 | { |
592d1631 L |
5829 | { Bad_Opcode }, |
5830 | { Bad_Opcode }, | |
ec6f095a | 5831 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5832 | }, |
5833 | ||
592a252b | 5834 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5835 | { |
592d1631 L |
5836 | { Bad_Opcode }, |
5837 | { Bad_Opcode }, | |
ec6f095a | 5838 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5839 | }, |
5840 | ||
592a252b | 5841 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5842 | { |
592d1631 L |
5843 | { Bad_Opcode }, |
5844 | { Bad_Opcode }, | |
ec6f095a | 5845 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5846 | }, |
5847 | ||
592a252b | 5848 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5849 | { |
592d1631 L |
5850 | { Bad_Opcode }, |
5851 | { Bad_Opcode }, | |
ec6f095a | 5852 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5853 | }, |
5854 | ||
592a252b | 5855 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5856 | { |
592d1631 L |
5857 | { Bad_Opcode }, |
5858 | { Bad_Opcode }, | |
ec6f095a | 5859 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5860 | }, |
5861 | ||
592a252b | 5862 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5863 | { |
592d1631 L |
5864 | { Bad_Opcode }, |
5865 | { Bad_Opcode }, | |
ec6f095a | 5866 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5867 | }, |
5868 | ||
592a252b | 5869 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5870 | { |
592d1631 L |
5871 | { Bad_Opcode }, |
5872 | { Bad_Opcode }, | |
ec6f095a | 5873 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5874 | }, |
5875 | ||
592a252b | 5876 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5877 | { |
592d1631 L |
5878 | { Bad_Opcode }, |
5879 | { Bad_Opcode }, | |
ec6f095a | 5880 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5881 | }, |
5882 | ||
592a252b | 5883 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5884 | { |
592d1631 L |
5885 | { Bad_Opcode }, |
5886 | { Bad_Opcode }, | |
592a252b | 5887 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5888 | }, |
5889 | ||
6c30d220 L |
5890 | /* PREFIX_VEX_0F3845 */ |
5891 | { | |
5892 | { Bad_Opcode }, | |
5893 | { Bad_Opcode }, | |
bf890a93 | 5894 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5895 | }, |
5896 | ||
5897 | /* PREFIX_VEX_0F3846 */ | |
5898 | { | |
5899 | { Bad_Opcode }, | |
5900 | { Bad_Opcode }, | |
5901 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5902 | }, | |
5903 | ||
5904 | /* PREFIX_VEX_0F3847 */ | |
5905 | { | |
5906 | { Bad_Opcode }, | |
5907 | { Bad_Opcode }, | |
bf890a93 | 5908 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5909 | }, |
5910 | ||
5911 | /* PREFIX_VEX_0F3858 */ | |
5912 | { | |
5913 | { Bad_Opcode }, | |
5914 | { Bad_Opcode }, | |
5915 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5916 | }, | |
5917 | ||
5918 | /* PREFIX_VEX_0F3859 */ | |
5919 | { | |
5920 | { Bad_Opcode }, | |
5921 | { Bad_Opcode }, | |
5922 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5923 | }, | |
5924 | ||
5925 | /* PREFIX_VEX_0F385A */ | |
5926 | { | |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
5929 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5930 | }, | |
5931 | ||
5932 | /* PREFIX_VEX_0F3878 */ | |
5933 | { | |
5934 | { Bad_Opcode }, | |
5935 | { Bad_Opcode }, | |
5936 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5937 | }, | |
5938 | ||
5939 | /* PREFIX_VEX_0F3879 */ | |
5940 | { | |
5941 | { Bad_Opcode }, | |
5942 | { Bad_Opcode }, | |
5943 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5944 | }, | |
5945 | ||
5946 | /* PREFIX_VEX_0F388C */ | |
5947 | { | |
5948 | { Bad_Opcode }, | |
5949 | { Bad_Opcode }, | |
f7002f42 | 5950 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5951 | }, |
5952 | ||
5953 | /* PREFIX_VEX_0F388E */ | |
5954 | { | |
5955 | { Bad_Opcode }, | |
5956 | { Bad_Opcode }, | |
f7002f42 | 5957 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5958 | }, |
5959 | ||
5960 | /* PREFIX_VEX_0F3890 */ | |
5961 | { | |
5962 | { Bad_Opcode }, | |
5963 | { Bad_Opcode }, | |
bf890a93 | 5964 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5965 | }, |
5966 | ||
5967 | /* PREFIX_VEX_0F3891 */ | |
5968 | { | |
5969 | { Bad_Opcode }, | |
5970 | { Bad_Opcode }, | |
bf890a93 | 5971 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5972 | }, |
5973 | ||
5974 | /* PREFIX_VEX_0F3892 */ | |
5975 | { | |
5976 | { Bad_Opcode }, | |
5977 | { Bad_Opcode }, | |
bf890a93 | 5978 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5979 | }, |
5980 | ||
5981 | /* PREFIX_VEX_0F3893 */ | |
5982 | { | |
5983 | { Bad_Opcode }, | |
5984 | { Bad_Opcode }, | |
bf890a93 | 5985 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5986 | }, |
5987 | ||
592a252b | 5988 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5989 | { |
592d1631 L |
5990 | { Bad_Opcode }, |
5991 | { Bad_Opcode }, | |
bf890a93 | 5992 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5993 | }, |
5994 | ||
592a252b | 5995 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5996 | { |
592d1631 L |
5997 | { Bad_Opcode }, |
5998 | { Bad_Opcode }, | |
bf890a93 | 5999 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6000 | }, |
6001 | ||
592a252b | 6002 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 6003 | { |
592d1631 L |
6004 | { Bad_Opcode }, |
6005 | { Bad_Opcode }, | |
bf890a93 | 6006 | { "vfmadd132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6007 | }, |
6008 | ||
592a252b | 6009 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 6010 | { |
592d1631 L |
6011 | { Bad_Opcode }, |
6012 | { Bad_Opcode }, | |
bf890a93 | 6013 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
a5ff0eb2 L |
6014 | }, |
6015 | ||
592a252b | 6016 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 6017 | { |
592d1631 L |
6018 | { Bad_Opcode }, |
6019 | { Bad_Opcode }, | |
bf890a93 | 6020 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
6021 | }, |
6022 | ||
592a252b | 6023 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 6024 | { |
592d1631 L |
6025 | { Bad_Opcode }, |
6026 | { Bad_Opcode }, | |
bf890a93 | 6027 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6028 | }, |
6029 | ||
592a252b | 6030 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 6031 | { |
592d1631 L |
6032 | { Bad_Opcode }, |
6033 | { Bad_Opcode }, | |
bf890a93 | 6034 | { "vfnmadd132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6035 | }, |
6036 | ||
592a252b | 6037 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 6038 | { |
592d1631 L |
6039 | { Bad_Opcode }, |
6040 | { Bad_Opcode }, | |
bf890a93 | 6041 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6042 | }, |
6043 | ||
592a252b | 6044 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 6045 | { |
592d1631 L |
6046 | { Bad_Opcode }, |
6047 | { Bad_Opcode }, | |
bf890a93 | 6048 | { "vfnmsub132p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6049 | }, |
6050 | ||
592a252b | 6051 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 6052 | { |
592d1631 L |
6053 | { Bad_Opcode }, |
6054 | { Bad_Opcode }, | |
bf890a93 | 6055 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6056 | }, |
6057 | ||
592a252b | 6058 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 6059 | { |
592d1631 L |
6060 | { Bad_Opcode }, |
6061 | { Bad_Opcode }, | |
bf890a93 | 6062 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, 0 }, |
592d1631 | 6063 | { Bad_Opcode }, |
c0f3af97 L |
6064 | }, |
6065 | ||
592a252b | 6066 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 6067 | { |
592d1631 L |
6068 | { Bad_Opcode }, |
6069 | { Bad_Opcode }, | |
bf890a93 | 6070 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6071 | }, |
6072 | ||
592a252b | 6073 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 6074 | { |
592d1631 L |
6075 | { Bad_Opcode }, |
6076 | { Bad_Opcode }, | |
bf890a93 | 6077 | { "vfmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6078 | }, |
6079 | ||
592a252b | 6080 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 6081 | { |
592d1631 L |
6082 | { Bad_Opcode }, |
6083 | { Bad_Opcode }, | |
bf890a93 | 6084 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6085 | }, |
6086 | ||
592a252b | 6087 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 6088 | { |
592d1631 L |
6089 | { Bad_Opcode }, |
6090 | { Bad_Opcode }, | |
bf890a93 | 6091 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6092 | }, |
6093 | ||
592a252b | 6094 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 6095 | { |
592d1631 L |
6096 | { Bad_Opcode }, |
6097 | { Bad_Opcode }, | |
bf890a93 | 6098 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6099 | }, |
6100 | ||
592a252b | 6101 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 6102 | { |
592d1631 L |
6103 | { Bad_Opcode }, |
6104 | { Bad_Opcode }, | |
bf890a93 | 6105 | { "vfnmadd213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6106 | }, |
6107 | ||
592a252b | 6108 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 6109 | { |
592d1631 L |
6110 | { Bad_Opcode }, |
6111 | { Bad_Opcode }, | |
bf890a93 | 6112 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6113 | }, |
6114 | ||
592a252b | 6115 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 6116 | { |
592d1631 L |
6117 | { Bad_Opcode }, |
6118 | { Bad_Opcode }, | |
bf890a93 | 6119 | { "vfnmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6120 | }, |
6121 | ||
592a252b | 6122 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6123 | { |
592d1631 L |
6124 | { Bad_Opcode }, |
6125 | { Bad_Opcode }, | |
bf890a93 | 6126 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6127 | }, |
6128 | ||
592a252b | 6129 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6130 | { |
592d1631 L |
6131 | { Bad_Opcode }, |
6132 | { Bad_Opcode }, | |
bf890a93 | 6133 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6134 | }, |
6135 | ||
592a252b | 6136 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6137 | { |
592d1631 L |
6138 | { Bad_Opcode }, |
6139 | { Bad_Opcode }, | |
bf890a93 | 6140 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6141 | }, |
6142 | ||
592a252b | 6143 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6144 | { |
592d1631 L |
6145 | { Bad_Opcode }, |
6146 | { Bad_Opcode }, | |
bf890a93 | 6147 | { "vfmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6148 | }, |
6149 | ||
592a252b | 6150 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6151 | { |
592d1631 L |
6152 | { Bad_Opcode }, |
6153 | { Bad_Opcode }, | |
bf890a93 | 6154 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6155 | }, |
6156 | ||
592a252b | 6157 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6158 | { |
592d1631 L |
6159 | { Bad_Opcode }, |
6160 | { Bad_Opcode }, | |
bf890a93 | 6161 | { "vfmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6162 | }, |
6163 | ||
592a252b | 6164 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6165 | { |
592d1631 L |
6166 | { Bad_Opcode }, |
6167 | { Bad_Opcode }, | |
bf890a93 | 6168 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6169 | }, |
6170 | ||
592a252b | 6171 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6172 | { |
592d1631 L |
6173 | { Bad_Opcode }, |
6174 | { Bad_Opcode }, | |
bf890a93 | 6175 | { "vfnmadd231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6176 | }, |
6177 | ||
592a252b | 6178 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6179 | { |
592d1631 L |
6180 | { Bad_Opcode }, |
6181 | { Bad_Opcode }, | |
bf890a93 | 6182 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6183 | }, |
6184 | ||
592a252b | 6185 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6186 | { |
592d1631 L |
6187 | { Bad_Opcode }, |
6188 | { Bad_Opcode }, | |
bf890a93 | 6189 | { "vfnmsub231p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6190 | }, |
6191 | ||
592a252b | 6192 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6193 | { |
592d1631 L |
6194 | { Bad_Opcode }, |
6195 | { Bad_Opcode }, | |
bf890a93 | 6196 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
6197 | }, |
6198 | ||
48521003 IT |
6199 | /* PREFIX_VEX_0F38CF */ |
6200 | { | |
6201 | { Bad_Opcode }, | |
6202 | { Bad_Opcode }, | |
6203 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6204 | }, | |
6205 | ||
592a252b | 6206 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6207 | { |
592d1631 L |
6208 | { Bad_Opcode }, |
6209 | { Bad_Opcode }, | |
592a252b | 6210 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6211 | }, |
6212 | ||
592a252b | 6213 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6214 | { |
592d1631 L |
6215 | { Bad_Opcode }, |
6216 | { Bad_Opcode }, | |
8dcf1fad | 6217 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6218 | }, |
6219 | ||
592a252b | 6220 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6221 | { |
592d1631 L |
6222 | { Bad_Opcode }, |
6223 | { Bad_Opcode }, | |
8dcf1fad | 6224 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6225 | }, |
6226 | ||
592a252b | 6227 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6228 | { |
592d1631 L |
6229 | { Bad_Opcode }, |
6230 | { Bad_Opcode }, | |
8dcf1fad | 6231 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6232 | }, |
6233 | ||
592a252b | 6234 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6235 | { |
592d1631 L |
6236 | { Bad_Opcode }, |
6237 | { Bad_Opcode }, | |
8dcf1fad | 6238 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6239 | }, |
6240 | ||
f12dc422 L |
6241 | /* PREFIX_VEX_0F38F2 */ |
6242 | { | |
6243 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6244 | }, | |
6245 | ||
6246 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6247 | { | |
6248 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6249 | }, | |
6250 | ||
6251 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6252 | { | |
6253 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6254 | }, | |
6255 | ||
6256 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6257 | { | |
6258 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6259 | }, | |
6260 | ||
6c30d220 L |
6261 | /* PREFIX_VEX_0F38F5 */ |
6262 | { | |
6263 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6264 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6265 | { Bad_Opcode }, | |
6266 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6267 | }, | |
6268 | ||
6269 | /* PREFIX_VEX_0F38F6 */ | |
6270 | { | |
6271 | { Bad_Opcode }, | |
6272 | { Bad_Opcode }, | |
6273 | { Bad_Opcode }, | |
6274 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6275 | }, | |
6276 | ||
f12dc422 L |
6277 | /* PREFIX_VEX_0F38F7 */ |
6278 | { | |
6279 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6280 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6281 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6282 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6283 | }, | |
6284 | ||
6285 | /* PREFIX_VEX_0F3A00 */ | |
6286 | { | |
6287 | { Bad_Opcode }, | |
6288 | { Bad_Opcode }, | |
6289 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6290 | }, | |
6291 | ||
6292 | /* PREFIX_VEX_0F3A01 */ | |
6293 | { | |
6294 | { Bad_Opcode }, | |
6295 | { Bad_Opcode }, | |
6296 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6297 | }, | |
6298 | ||
6299 | /* PREFIX_VEX_0F3A02 */ | |
6300 | { | |
6301 | { Bad_Opcode }, | |
6302 | { Bad_Opcode }, | |
6303 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6304 | }, |
6305 | ||
592a252b | 6306 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6307 | { |
592d1631 L |
6308 | { Bad_Opcode }, |
6309 | { Bad_Opcode }, | |
592a252b | 6310 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6311 | }, |
6312 | ||
592a252b | 6313 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6314 | { |
592d1631 L |
6315 | { Bad_Opcode }, |
6316 | { Bad_Opcode }, | |
592a252b | 6317 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6318 | }, |
6319 | ||
592a252b | 6320 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6321 | { |
592d1631 L |
6322 | { Bad_Opcode }, |
6323 | { Bad_Opcode }, | |
592a252b | 6324 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6325 | }, |
6326 | ||
592a252b | 6327 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6328 | { |
592d1631 L |
6329 | { Bad_Opcode }, |
6330 | { Bad_Opcode }, | |
ec6f095a | 6331 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6332 | }, |
6333 | ||
592a252b | 6334 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6335 | { |
592d1631 L |
6336 | { Bad_Opcode }, |
6337 | { Bad_Opcode }, | |
ec6f095a | 6338 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6339 | }, |
6340 | ||
592a252b | 6341 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6342 | { |
592d1631 L |
6343 | { Bad_Opcode }, |
6344 | { Bad_Opcode }, | |
ec6f095a | 6345 | { "vroundss", { XMScalar, VexScalar, EXdScalar, Ib }, 0 }, |
0bfee649 L |
6346 | }, |
6347 | ||
592a252b | 6348 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6349 | { |
592d1631 L |
6350 | { Bad_Opcode }, |
6351 | { Bad_Opcode }, | |
ec6f095a | 6352 | { "vroundsd", { XMScalar, VexScalar, EXqScalar, Ib }, 0 }, |
0bfee649 L |
6353 | }, |
6354 | ||
592a252b | 6355 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6356 | { |
592d1631 L |
6357 | { Bad_Opcode }, |
6358 | { Bad_Opcode }, | |
ec6f095a | 6359 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6360 | }, |
6361 | ||
592a252b | 6362 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6363 | { |
592d1631 L |
6364 | { Bad_Opcode }, |
6365 | { Bad_Opcode }, | |
ec6f095a | 6366 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6367 | }, |
6368 | ||
592a252b | 6369 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6370 | { |
592d1631 L |
6371 | { Bad_Opcode }, |
6372 | { Bad_Opcode }, | |
ec6f095a | 6373 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6374 | }, |
6375 | ||
592a252b | 6376 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6377 | { |
592d1631 L |
6378 | { Bad_Opcode }, |
6379 | { Bad_Opcode }, | |
ec6f095a | 6380 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6381 | }, |
6382 | ||
592a252b | 6383 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6384 | { |
592d1631 L |
6385 | { Bad_Opcode }, |
6386 | { Bad_Opcode }, | |
592a252b | 6387 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6388 | }, |
6389 | ||
592a252b | 6390 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6391 | { |
592d1631 L |
6392 | { Bad_Opcode }, |
6393 | { Bad_Opcode }, | |
592a252b | 6394 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6395 | }, |
6396 | ||
592a252b | 6397 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6398 | { |
592d1631 L |
6399 | { Bad_Opcode }, |
6400 | { Bad_Opcode }, | |
592a252b | 6401 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6402 | }, |
6403 | ||
592a252b | 6404 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6405 | { |
592d1631 L |
6406 | { Bad_Opcode }, |
6407 | { Bad_Opcode }, | |
592a252b | 6408 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6409 | }, |
6410 | ||
592a252b | 6411 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6412 | { |
592d1631 L |
6413 | { Bad_Opcode }, |
6414 | { Bad_Opcode }, | |
592a252b | 6415 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6416 | }, |
6417 | ||
592a252b | 6418 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6419 | { |
592d1631 L |
6420 | { Bad_Opcode }, |
6421 | { Bad_Opcode }, | |
592a252b | 6422 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6423 | }, |
6424 | ||
592a252b | 6425 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6426 | { |
6427 | { Bad_Opcode }, | |
6428 | { Bad_Opcode }, | |
bf890a93 | 6429 | { "vcvtps2ph", { EXxmmq, XM, Ib }, 0 }, |
c7b8aa3a L |
6430 | }, |
6431 | ||
592a252b | 6432 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6433 | { |
592d1631 L |
6434 | { Bad_Opcode }, |
6435 | { Bad_Opcode }, | |
592a252b | 6436 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6437 | }, |
6438 | ||
592a252b | 6439 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6440 | { |
592d1631 L |
6441 | { Bad_Opcode }, |
6442 | { Bad_Opcode }, | |
592a252b | 6443 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6444 | }, |
6445 | ||
592a252b | 6446 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6447 | { |
592d1631 L |
6448 | { Bad_Opcode }, |
6449 | { Bad_Opcode }, | |
592a252b | 6450 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6451 | }, |
6452 | ||
43234a1e L |
6453 | /* PREFIX_VEX_0F3A30 */ |
6454 | { | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
6457 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6458 | }, | |
6459 | ||
1ba585e8 IT |
6460 | /* PREFIX_VEX_0F3A31 */ |
6461 | { | |
6462 | { Bad_Opcode }, | |
6463 | { Bad_Opcode }, | |
6464 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6465 | }, | |
6466 | ||
43234a1e L |
6467 | /* PREFIX_VEX_0F3A32 */ |
6468 | { | |
6469 | { Bad_Opcode }, | |
6470 | { Bad_Opcode }, | |
6471 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6472 | }, | |
6473 | ||
1ba585e8 IT |
6474 | /* PREFIX_VEX_0F3A33 */ |
6475 | { | |
6476 | { Bad_Opcode }, | |
6477 | { Bad_Opcode }, | |
6478 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6479 | }, | |
6480 | ||
6c30d220 L |
6481 | /* PREFIX_VEX_0F3A38 */ |
6482 | { | |
6483 | { Bad_Opcode }, | |
6484 | { Bad_Opcode }, | |
6485 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6486 | }, | |
6487 | ||
6488 | /* PREFIX_VEX_0F3A39 */ | |
6489 | { | |
6490 | { Bad_Opcode }, | |
6491 | { Bad_Opcode }, | |
6492 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6493 | }, | |
6494 | ||
592a252b | 6495 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6496 | { |
592d1631 L |
6497 | { Bad_Opcode }, |
6498 | { Bad_Opcode }, | |
ec6f095a | 6499 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6500 | }, |
6501 | ||
592a252b | 6502 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6503 | { |
592d1631 L |
6504 | { Bad_Opcode }, |
6505 | { Bad_Opcode }, | |
592a252b | 6506 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6507 | }, |
6508 | ||
592a252b | 6509 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6510 | { |
592d1631 L |
6511 | { Bad_Opcode }, |
6512 | { Bad_Opcode }, | |
ec6f095a | 6513 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6514 | }, |
6515 | ||
592a252b | 6516 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6517 | { |
592d1631 L |
6518 | { Bad_Opcode }, |
6519 | { Bad_Opcode }, | |
ff1982d5 | 6520 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6521 | }, |
6522 | ||
6c30d220 L |
6523 | /* PREFIX_VEX_0F3A46 */ |
6524 | { | |
6525 | { Bad_Opcode }, | |
6526 | { Bad_Opcode }, | |
6527 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6528 | }, | |
6529 | ||
592a252b | 6530 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6531 | { |
6532 | { Bad_Opcode }, | |
6533 | { Bad_Opcode }, | |
592a252b | 6534 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6535 | }, |
6536 | ||
592a252b | 6537 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6538 | { |
6539 | { Bad_Opcode }, | |
6540 | { Bad_Opcode }, | |
592a252b | 6541 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6542 | }, |
6543 | ||
592a252b | 6544 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6545 | { |
592d1631 L |
6546 | { Bad_Opcode }, |
6547 | { Bad_Opcode }, | |
592a252b | 6548 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6549 | }, |
6550 | ||
592a252b | 6551 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6552 | { |
592d1631 L |
6553 | { Bad_Opcode }, |
6554 | { Bad_Opcode }, | |
592a252b | 6555 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6556 | }, |
6557 | ||
592a252b | 6558 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6559 | { |
592d1631 L |
6560 | { Bad_Opcode }, |
6561 | { Bad_Opcode }, | |
6c30d220 | 6562 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6563 | }, |
6564 | ||
592a252b | 6565 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6566 | { |
592d1631 L |
6567 | { Bad_Opcode }, |
6568 | { Bad_Opcode }, | |
3a2430e0 | 6569 | { "vfmaddsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6570 | }, |
6571 | ||
592a252b | 6572 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6573 | { |
592d1631 L |
6574 | { Bad_Opcode }, |
6575 | { Bad_Opcode }, | |
3a2430e0 | 6576 | { "vfmaddsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6577 | }, |
6578 | ||
592a252b | 6579 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6580 | { |
592d1631 L |
6581 | { Bad_Opcode }, |
6582 | { Bad_Opcode }, | |
3a2430e0 | 6583 | { "vfmsubaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6584 | }, |
6585 | ||
592a252b | 6586 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6587 | { |
592d1631 L |
6588 | { Bad_Opcode }, |
6589 | { Bad_Opcode }, | |
3a2430e0 | 6590 | { "vfmsubaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6591 | }, |
6592 | ||
592a252b | 6593 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6594 | { |
592d1631 L |
6595 | { Bad_Opcode }, |
6596 | { Bad_Opcode }, | |
592a252b | 6597 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6598 | { Bad_Opcode }, |
c0f3af97 L |
6599 | }, |
6600 | ||
592a252b | 6601 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6602 | { |
592d1631 L |
6603 | { Bad_Opcode }, |
6604 | { Bad_Opcode }, | |
592a252b | 6605 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6606 | }, |
6607 | ||
592a252b | 6608 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6609 | { |
592d1631 L |
6610 | { Bad_Opcode }, |
6611 | { Bad_Opcode }, | |
592a252b | 6612 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6613 | }, |
6614 | ||
592a252b | 6615 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6616 | { |
592d1631 L |
6617 | { Bad_Opcode }, |
6618 | { Bad_Opcode }, | |
592a252b | 6619 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6620 | }, |
a5ff0eb2 | 6621 | |
592a252b | 6622 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6623 | { |
592d1631 L |
6624 | { Bad_Opcode }, |
6625 | { Bad_Opcode }, | |
3a2430e0 | 6626 | { "vfmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6627 | }, |
6628 | ||
592a252b | 6629 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6630 | { |
592d1631 L |
6631 | { Bad_Opcode }, |
6632 | { Bad_Opcode }, | |
3a2430e0 | 6633 | { "vfmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6634 | }, |
6635 | ||
592a252b | 6636 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6637 | { |
592d1631 L |
6638 | { Bad_Opcode }, |
6639 | { Bad_Opcode }, | |
592a252b | 6640 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6641 | }, |
6642 | ||
592a252b | 6643 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6644 | { |
592d1631 L |
6645 | { Bad_Opcode }, |
6646 | { Bad_Opcode }, | |
592a252b | 6647 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6648 | }, |
6649 | ||
592a252b | 6650 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6651 | { |
592d1631 L |
6652 | { Bad_Opcode }, |
6653 | { Bad_Opcode }, | |
3a2430e0 | 6654 | { "vfmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6655 | }, |
6656 | ||
592a252b | 6657 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6658 | { |
592d1631 L |
6659 | { Bad_Opcode }, |
6660 | { Bad_Opcode }, | |
3a2430e0 | 6661 | { "vfmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6662 | }, |
6663 | ||
592a252b | 6664 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6665 | { |
592d1631 L |
6666 | { Bad_Opcode }, |
6667 | { Bad_Opcode }, | |
592a252b | 6668 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6669 | }, |
6670 | ||
592a252b | 6671 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6672 | { |
592d1631 L |
6673 | { Bad_Opcode }, |
6674 | { Bad_Opcode }, | |
592a252b | 6675 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6676 | }, |
6677 | ||
592a252b | 6678 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6679 | { |
592d1631 L |
6680 | { Bad_Opcode }, |
6681 | { Bad_Opcode }, | |
3a2430e0 | 6682 | { "vfnmaddps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6683 | }, |
6684 | ||
592a252b | 6685 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6686 | { |
592d1631 L |
6687 | { Bad_Opcode }, |
6688 | { Bad_Opcode }, | |
3a2430e0 | 6689 | { "vfnmaddpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6690 | }, |
6691 | ||
592a252b | 6692 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6693 | { |
592d1631 L |
6694 | { Bad_Opcode }, |
6695 | { Bad_Opcode }, | |
592a252b | 6696 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6697 | }, |
6698 | ||
592a252b | 6699 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6700 | { |
592d1631 L |
6701 | { Bad_Opcode }, |
6702 | { Bad_Opcode }, | |
592a252b | 6703 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6704 | }, |
6705 | ||
592a252b | 6706 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6707 | { |
592d1631 L |
6708 | { Bad_Opcode }, |
6709 | { Bad_Opcode }, | |
3a2430e0 | 6710 | { "vfnmsubps", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 6711 | { Bad_Opcode }, |
922d8de8 DR |
6712 | }, |
6713 | ||
592a252b | 6714 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6715 | { |
592d1631 L |
6716 | { Bad_Opcode }, |
6717 | { Bad_Opcode }, | |
3a2430e0 | 6718 | { "vfnmsubpd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
922d8de8 DR |
6719 | }, |
6720 | ||
592a252b | 6721 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6722 | { |
592d1631 L |
6723 | { Bad_Opcode }, |
6724 | { Bad_Opcode }, | |
592a252b | 6725 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6726 | }, |
6727 | ||
592a252b | 6728 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6729 | { |
592d1631 L |
6730 | { Bad_Opcode }, |
6731 | { Bad_Opcode }, | |
592a252b | 6732 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6733 | }, |
6734 | ||
48521003 IT |
6735 | /* PREFIX_VEX_0F3ACE */ |
6736 | { | |
6737 | { Bad_Opcode }, | |
6738 | { Bad_Opcode }, | |
6739 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6740 | }, | |
6741 | ||
6742 | /* PREFIX_VEX_0F3ACF */ | |
6743 | { | |
6744 | { Bad_Opcode }, | |
6745 | { Bad_Opcode }, | |
6746 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6747 | }, | |
6748 | ||
592a252b | 6749 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6750 | { |
592d1631 L |
6751 | { Bad_Opcode }, |
6752 | { Bad_Opcode }, | |
592a252b | 6753 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6754 | }, |
6c30d220 L |
6755 | |
6756 | /* PREFIX_VEX_0F3AF0 */ | |
6757 | { | |
6758 | { Bad_Opcode }, | |
6759 | { Bad_Opcode }, | |
6760 | { Bad_Opcode }, | |
6761 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6762 | }, | |
43234a1e L |
6763 | |
6764 | #define NEED_PREFIX_TABLE | |
6765 | #include "i386-dis-evex.h" | |
6766 | #undef NEED_PREFIX_TABLE | |
c0f3af97 L |
6767 | }; |
6768 | ||
6769 | static const struct dis386 x86_64_table[][2] = { | |
6770 | /* X86_64_06 */ | |
6771 | { | |
bf890a93 | 6772 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6773 | }, |
6774 | ||
6775 | /* X86_64_07 */ | |
6776 | { | |
bf890a93 | 6777 | { "popP", { es }, 0 }, |
c0f3af97 L |
6778 | }, |
6779 | ||
6780 | /* X86_64_0D */ | |
6781 | { | |
bf890a93 | 6782 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6783 | }, |
6784 | ||
6785 | /* X86_64_16 */ | |
6786 | { | |
bf890a93 | 6787 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6788 | }, |
6789 | ||
6790 | /* X86_64_17 */ | |
6791 | { | |
bf890a93 | 6792 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6793 | }, |
6794 | ||
6795 | /* X86_64_1E */ | |
6796 | { | |
bf890a93 | 6797 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6798 | }, |
6799 | ||
6800 | /* X86_64_1F */ | |
6801 | { | |
bf890a93 | 6802 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6803 | }, |
6804 | ||
6805 | /* X86_64_27 */ | |
6806 | { | |
bf890a93 | 6807 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6808 | }, |
6809 | ||
6810 | /* X86_64_2F */ | |
6811 | { | |
bf890a93 | 6812 | { "das", { XX }, 0 }, |
c0f3af97 L |
6813 | }, |
6814 | ||
6815 | /* X86_64_37 */ | |
6816 | { | |
bf890a93 | 6817 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6818 | }, |
6819 | ||
6820 | /* X86_64_3F */ | |
6821 | { | |
bf890a93 | 6822 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6823 | }, |
6824 | ||
6825 | /* X86_64_60 */ | |
6826 | { | |
bf890a93 | 6827 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6828 | }, |
6829 | ||
6830 | /* X86_64_61 */ | |
6831 | { | |
bf890a93 | 6832 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6833 | }, |
6834 | ||
6835 | /* X86_64_62 */ | |
6836 | { | |
6837 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6838 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6839 | }, |
6840 | ||
6841 | /* X86_64_63 */ | |
6842 | { | |
bf890a93 IT |
6843 | { "arpl", { Ew, Gw }, 0 }, |
6844 | { "movs{lq|xd}", { Gv, Ed }, 0 }, | |
c0f3af97 L |
6845 | }, |
6846 | ||
6847 | /* X86_64_6D */ | |
6848 | { | |
bf890a93 IT |
6849 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6850 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6851 | }, |
6852 | ||
6853 | /* X86_64_6F */ | |
6854 | { | |
bf890a93 IT |
6855 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6856 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6857 | }, |
6858 | ||
d039fef3 | 6859 | /* X86_64_82 */ |
8b89fe14 | 6860 | { |
de194d85 | 6861 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6862 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6863 | }, |
6864 | ||
c0f3af97 L |
6865 | /* X86_64_9A */ |
6866 | { | |
bf890a93 | 6867 | { "Jcall{T|}", { Ap }, 0 }, |
c0f3af97 L |
6868 | }, |
6869 | ||
6870 | /* X86_64_C4 */ | |
6871 | { | |
6872 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6873 | { VEX_C4_TABLE (VEX_0F) }, | |
6874 | }, | |
6875 | ||
6876 | /* X86_64_C5 */ | |
6877 | { | |
6878 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6879 | { VEX_C5_TABLE (VEX_0F) }, | |
6880 | }, | |
6881 | ||
6882 | /* X86_64_CE */ | |
6883 | { | |
bf890a93 | 6884 | { "into", { XX }, 0 }, |
c0f3af97 L |
6885 | }, |
6886 | ||
6887 | /* X86_64_D4 */ | |
6888 | { | |
bf890a93 | 6889 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6890 | }, |
6891 | ||
6892 | /* X86_64_D5 */ | |
6893 | { | |
bf890a93 | 6894 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6895 | }, |
6896 | ||
a72d2af2 L |
6897 | /* X86_64_E8 */ |
6898 | { | |
6899 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6900 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6901 | }, |
6902 | ||
6903 | /* X86_64_E9 */ | |
6904 | { | |
6905 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6906 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6907 | }, |
6908 | ||
c0f3af97 L |
6909 | /* X86_64_EA */ |
6910 | { | |
bf890a93 | 6911 | { "Jjmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6912 | }, |
6913 | ||
6914 | /* X86_64_0F01_REG_0 */ | |
6915 | { | |
bf890a93 IT |
6916 | { "sgdt{Q|IQ}", { M }, 0 }, |
6917 | { "sgdt", { M }, 0 }, | |
c0f3af97 L |
6918 | }, |
6919 | ||
6920 | /* X86_64_0F01_REG_1 */ | |
6921 | { | |
bf890a93 IT |
6922 | { "sidt{Q|IQ}", { M }, 0 }, |
6923 | { "sidt", { M }, 0 }, | |
c0f3af97 L |
6924 | }, |
6925 | ||
6926 | /* X86_64_0F01_REG_2 */ | |
6927 | { | |
bf890a93 IT |
6928 | { "lgdt{Q|Q}", { M }, 0 }, |
6929 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6930 | }, |
6931 | ||
6932 | /* X86_64_0F01_REG_3 */ | |
6933 | { | |
bf890a93 IT |
6934 | { "lidt{Q|Q}", { M }, 0 }, |
6935 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6936 | }, |
6937 | }; | |
6938 | ||
6939 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6940 | |
6941 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6942 | { |
6943 | /* 00 */ | |
507bd325 L |
6944 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6945 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6946 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6947 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6948 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6949 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6950 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6951 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6952 | /* 08 */ |
507bd325 L |
6953 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6954 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6955 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6956 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6957 | { Bad_Opcode }, |
6958 | { Bad_Opcode }, | |
6959 | { Bad_Opcode }, | |
6960 | { Bad_Opcode }, | |
f88c9eb0 SP |
6961 | /* 10 */ |
6962 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6963 | { Bad_Opcode }, |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
f88c9eb0 SP |
6966 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6967 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6968 | { Bad_Opcode }, |
f88c9eb0 SP |
6969 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6970 | /* 18 */ | |
592d1631 L |
6971 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
507bd325 L |
6975 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6976 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6977 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6978 | { Bad_Opcode }, |
f88c9eb0 SP |
6979 | /* 20 */ |
6980 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6981 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6982 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6983 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6984 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6985 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6986 | { Bad_Opcode }, |
6987 | { Bad_Opcode }, | |
f88c9eb0 SP |
6988 | /* 28 */ |
6989 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6990 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6991 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6992 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6993 | { Bad_Opcode }, |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
f88c9eb0 SP |
6997 | /* 30 */ |
6998 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6999 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
7000 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
7001 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
7002 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
7003 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 7004 | { Bad_Opcode }, |
f88c9eb0 SP |
7005 | { PREFIX_TABLE (PREFIX_0F3837) }, |
7006 | /* 38 */ | |
7007 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
7008 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
7009 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
7010 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
7011 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
7012 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
7013 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
7014 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
7015 | /* 40 */ | |
7016 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
7017 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
7018 | { Bad_Opcode }, |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
f88c9eb0 | 7024 | /* 48 */ |
592d1631 L |
7025 | { Bad_Opcode }, |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
f88c9eb0 | 7033 | /* 50 */ |
592d1631 L |
7034 | { Bad_Opcode }, |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
f88c9eb0 | 7042 | /* 58 */ |
592d1631 L |
7043 | { Bad_Opcode }, |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
f88c9eb0 | 7051 | /* 60 */ |
592d1631 L |
7052 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
f88c9eb0 | 7060 | /* 68 */ |
592d1631 L |
7061 | { Bad_Opcode }, |
7062 | { Bad_Opcode }, | |
7063 | { Bad_Opcode }, | |
7064 | { Bad_Opcode }, | |
7065 | { Bad_Opcode }, | |
7066 | { Bad_Opcode }, | |
7067 | { Bad_Opcode }, | |
7068 | { Bad_Opcode }, | |
f88c9eb0 | 7069 | /* 70 */ |
592d1631 L |
7070 | { Bad_Opcode }, |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
f88c9eb0 | 7078 | /* 78 */ |
592d1631 L |
7079 | { Bad_Opcode }, |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
7082 | { Bad_Opcode }, | |
7083 | { Bad_Opcode }, | |
7084 | { Bad_Opcode }, | |
7085 | { Bad_Opcode }, | |
7086 | { Bad_Opcode }, | |
f88c9eb0 SP |
7087 | /* 80 */ |
7088 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
7089 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 7090 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
7091 | { Bad_Opcode }, |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
f88c9eb0 | 7096 | /* 88 */ |
592d1631 L |
7097 | { Bad_Opcode }, |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
f88c9eb0 | 7105 | /* 90 */ |
592d1631 L |
7106 | { Bad_Opcode }, |
7107 | { Bad_Opcode }, | |
7108 | { Bad_Opcode }, | |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
7111 | { Bad_Opcode }, | |
7112 | { Bad_Opcode }, | |
7113 | { Bad_Opcode }, | |
f88c9eb0 | 7114 | /* 98 */ |
592d1631 L |
7115 | { Bad_Opcode }, |
7116 | { Bad_Opcode }, | |
7117 | { Bad_Opcode }, | |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
f88c9eb0 | 7123 | /* a0 */ |
592d1631 L |
7124 | { Bad_Opcode }, |
7125 | { Bad_Opcode }, | |
7126 | { Bad_Opcode }, | |
7127 | { Bad_Opcode }, | |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
f88c9eb0 | 7132 | /* a8 */ |
592d1631 L |
7133 | { Bad_Opcode }, |
7134 | { Bad_Opcode }, | |
7135 | { Bad_Opcode }, | |
7136 | { Bad_Opcode }, | |
7137 | { Bad_Opcode }, | |
7138 | { Bad_Opcode }, | |
7139 | { Bad_Opcode }, | |
7140 | { Bad_Opcode }, | |
f88c9eb0 | 7141 | /* b0 */ |
592d1631 L |
7142 | { Bad_Opcode }, |
7143 | { Bad_Opcode }, | |
7144 | { Bad_Opcode }, | |
7145 | { Bad_Opcode }, | |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
7149 | { Bad_Opcode }, | |
f88c9eb0 | 7150 | /* b8 */ |
592d1631 L |
7151 | { Bad_Opcode }, |
7152 | { Bad_Opcode }, | |
7153 | { Bad_Opcode }, | |
7154 | { Bad_Opcode }, | |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
f88c9eb0 | 7159 | /* c0 */ |
592d1631 L |
7160 | { Bad_Opcode }, |
7161 | { Bad_Opcode }, | |
7162 | { Bad_Opcode }, | |
7163 | { Bad_Opcode }, | |
7164 | { Bad_Opcode }, | |
7165 | { Bad_Opcode }, | |
7166 | { Bad_Opcode }, | |
7167 | { Bad_Opcode }, | |
f88c9eb0 | 7168 | /* c8 */ |
a0046408 L |
7169 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7170 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7171 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7172 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7173 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7174 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7175 | { Bad_Opcode }, |
48521003 | 7176 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7177 | /* d0 */ |
592d1631 L |
7178 | { Bad_Opcode }, |
7179 | { Bad_Opcode }, | |
7180 | { Bad_Opcode }, | |
7181 | { Bad_Opcode }, | |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
f88c9eb0 | 7186 | /* d8 */ |
592d1631 L |
7187 | { Bad_Opcode }, |
7188 | { Bad_Opcode }, | |
7189 | { Bad_Opcode }, | |
f88c9eb0 SP |
7190 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7191 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7192 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7193 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7194 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7195 | /* e0 */ | |
592d1631 L |
7196 | { Bad_Opcode }, |
7197 | { Bad_Opcode }, | |
7198 | { Bad_Opcode }, | |
7199 | { Bad_Opcode }, | |
7200 | { Bad_Opcode }, | |
7201 | { Bad_Opcode }, | |
7202 | { Bad_Opcode }, | |
7203 | { Bad_Opcode }, | |
f88c9eb0 | 7204 | /* e8 */ |
592d1631 L |
7205 | { Bad_Opcode }, |
7206 | { Bad_Opcode }, | |
7207 | { Bad_Opcode }, | |
7208 | { Bad_Opcode }, | |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
f88c9eb0 SP |
7213 | /* f0 */ |
7214 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7215 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7216 | { Bad_Opcode }, |
7217 | { Bad_Opcode }, | |
7218 | { Bad_Opcode }, | |
603555e5 | 7219 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7220 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7221 | { Bad_Opcode }, |
f88c9eb0 | 7222 | /* f8 */ |
c0a30a9f L |
7223 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7224 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7225 | { Bad_Opcode }, |
7226 | { Bad_Opcode }, | |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
f88c9eb0 SP |
7231 | }, |
7232 | /* THREE_BYTE_0F3A */ | |
7233 | { | |
7234 | /* 00 */ | |
592d1631 L |
7235 | { Bad_Opcode }, |
7236 | { Bad_Opcode }, | |
7237 | { Bad_Opcode }, | |
7238 | { Bad_Opcode }, | |
7239 | { Bad_Opcode }, | |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
f88c9eb0 SP |
7243 | /* 08 */ |
7244 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7245 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7246 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7247 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7248 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7249 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7250 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7251 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7252 | /* 10 */ |
592d1631 L |
7253 | { Bad_Opcode }, |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
f88c9eb0 SP |
7257 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7258 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7259 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7260 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7261 | /* 18 */ | |
592d1631 L |
7262 | { Bad_Opcode }, |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
f88c9eb0 SP |
7270 | /* 20 */ |
7271 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7272 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7273 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7274 | { Bad_Opcode }, |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
f88c9eb0 | 7279 | /* 28 */ |
592d1631 L |
7280 | { Bad_Opcode }, |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
f88c9eb0 | 7288 | /* 30 */ |
592d1631 L |
7289 | { Bad_Opcode }, |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
f88c9eb0 | 7297 | /* 38 */ |
592d1631 L |
7298 | { Bad_Opcode }, |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
f88c9eb0 SP |
7306 | /* 40 */ |
7307 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7308 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7309 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7310 | { Bad_Opcode }, |
f88c9eb0 | 7311 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7312 | { Bad_Opcode }, |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
f88c9eb0 | 7315 | /* 48 */ |
592d1631 L |
7316 | { Bad_Opcode }, |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
f88c9eb0 | 7324 | /* 50 */ |
592d1631 L |
7325 | { Bad_Opcode }, |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
f88c9eb0 | 7333 | /* 58 */ |
592d1631 L |
7334 | { Bad_Opcode }, |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
f88c9eb0 SP |
7342 | /* 60 */ |
7343 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7344 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7345 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7346 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7347 | { Bad_Opcode }, |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
f88c9eb0 | 7351 | /* 68 */ |
592d1631 L |
7352 | { Bad_Opcode }, |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
7356 | { Bad_Opcode }, | |
7357 | { Bad_Opcode }, | |
7358 | { Bad_Opcode }, | |
7359 | { Bad_Opcode }, | |
f88c9eb0 | 7360 | /* 70 */ |
592d1631 L |
7361 | { Bad_Opcode }, |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
f88c9eb0 | 7369 | /* 78 */ |
592d1631 L |
7370 | { Bad_Opcode }, |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
7377 | { Bad_Opcode }, | |
f88c9eb0 | 7378 | /* 80 */ |
592d1631 L |
7379 | { Bad_Opcode }, |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
7384 | { Bad_Opcode }, | |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
f88c9eb0 | 7387 | /* 88 */ |
592d1631 L |
7388 | { Bad_Opcode }, |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
f88c9eb0 | 7396 | /* 90 */ |
592d1631 L |
7397 | { Bad_Opcode }, |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
f88c9eb0 | 7405 | /* 98 */ |
592d1631 L |
7406 | { Bad_Opcode }, |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
f88c9eb0 | 7414 | /* a0 */ |
592d1631 L |
7415 | { Bad_Opcode }, |
7416 | { Bad_Opcode }, | |
7417 | { Bad_Opcode }, | |
7418 | { Bad_Opcode }, | |
7419 | { Bad_Opcode }, | |
7420 | { Bad_Opcode }, | |
7421 | { Bad_Opcode }, | |
7422 | { Bad_Opcode }, | |
f88c9eb0 | 7423 | /* a8 */ |
592d1631 L |
7424 | { Bad_Opcode }, |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
7429 | { Bad_Opcode }, | |
7430 | { Bad_Opcode }, | |
7431 | { Bad_Opcode }, | |
f88c9eb0 | 7432 | /* b0 */ |
592d1631 L |
7433 | { Bad_Opcode }, |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
7438 | { Bad_Opcode }, | |
7439 | { Bad_Opcode }, | |
7440 | { Bad_Opcode }, | |
f88c9eb0 | 7441 | /* b8 */ |
592d1631 L |
7442 | { Bad_Opcode }, |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
7447 | { Bad_Opcode }, | |
7448 | { Bad_Opcode }, | |
7449 | { Bad_Opcode }, | |
f88c9eb0 | 7450 | /* c0 */ |
592d1631 L |
7451 | { Bad_Opcode }, |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
7456 | { Bad_Opcode }, | |
7457 | { Bad_Opcode }, | |
7458 | { Bad_Opcode }, | |
f88c9eb0 | 7459 | /* c8 */ |
592d1631 L |
7460 | { Bad_Opcode }, |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
a0046408 | 7464 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7465 | { Bad_Opcode }, |
48521003 IT |
7466 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7467 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7468 | /* d0 */ |
592d1631 L |
7469 | { Bad_Opcode }, |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
7474 | { Bad_Opcode }, | |
7475 | { Bad_Opcode }, | |
7476 | { Bad_Opcode }, | |
f88c9eb0 | 7477 | /* d8 */ |
592d1631 L |
7478 | { Bad_Opcode }, |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
7483 | { Bad_Opcode }, | |
7484 | { Bad_Opcode }, | |
f88c9eb0 SP |
7485 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7486 | /* e0 */ | |
592d1631 L |
7487 | { Bad_Opcode }, |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
592d1631 L |
7492 | { Bad_Opcode }, |
7493 | { Bad_Opcode }, | |
7494 | { Bad_Opcode }, | |
85f10a01 | 7495 | /* e8 */ |
592d1631 L |
7496 | { Bad_Opcode }, |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
7501 | { Bad_Opcode }, | |
7502 | { Bad_Opcode }, | |
7503 | { Bad_Opcode }, | |
85f10a01 | 7504 | /* f0 */ |
592d1631 L |
7505 | { Bad_Opcode }, |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
7510 | { Bad_Opcode }, | |
7511 | { Bad_Opcode }, | |
7512 | { Bad_Opcode }, | |
85f10a01 | 7513 | /* f8 */ |
592d1631 L |
7514 | { Bad_Opcode }, |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
7519 | { Bad_Opcode }, | |
7520 | { Bad_Opcode }, | |
7521 | { Bad_Opcode }, | |
85f10a01 | 7522 | }, |
f88c9eb0 SP |
7523 | }; |
7524 | ||
7525 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7526 | /* XOP_08 */ |
85f10a01 MM |
7527 | { |
7528 | /* 00 */ | |
592d1631 L |
7529 | { Bad_Opcode }, |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
85f10a01 | 7537 | /* 08 */ |
592d1631 L |
7538 | { Bad_Opcode }, |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
85f10a01 | 7546 | /* 10 */ |
3929df09 | 7547 | { Bad_Opcode }, |
592d1631 L |
7548 | { Bad_Opcode }, |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
85f10a01 | 7555 | /* 18 */ |
592d1631 L |
7556 | { Bad_Opcode }, |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
85f10a01 | 7564 | /* 20 */ |
592d1631 L |
7565 | { Bad_Opcode }, |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
7570 | { Bad_Opcode }, | |
7571 | { Bad_Opcode }, | |
7572 | { Bad_Opcode }, | |
85f10a01 | 7573 | /* 28 */ |
592d1631 L |
7574 | { Bad_Opcode }, |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
7580 | { Bad_Opcode }, | |
7581 | { Bad_Opcode }, | |
c0f3af97 | 7582 | /* 30 */ |
592d1631 L |
7583 | { Bad_Opcode }, |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
7588 | { Bad_Opcode }, | |
7589 | { Bad_Opcode }, | |
7590 | { Bad_Opcode }, | |
c0f3af97 | 7591 | /* 38 */ |
592d1631 L |
7592 | { Bad_Opcode }, |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
7598 | { Bad_Opcode }, | |
7599 | { Bad_Opcode }, | |
c0f3af97 | 7600 | /* 40 */ |
592d1631 L |
7601 | { Bad_Opcode }, |
7602 | { Bad_Opcode }, | |
7603 | { Bad_Opcode }, | |
7604 | { Bad_Opcode }, | |
7605 | { Bad_Opcode }, | |
7606 | { Bad_Opcode }, | |
7607 | { Bad_Opcode }, | |
7608 | { Bad_Opcode }, | |
85f10a01 | 7609 | /* 48 */ |
592d1631 L |
7610 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
c0f3af97 | 7618 | /* 50 */ |
592d1631 L |
7619 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
7625 | { Bad_Opcode }, | |
7626 | { Bad_Opcode }, | |
85f10a01 | 7627 | /* 58 */ |
592d1631 L |
7628 | { Bad_Opcode }, |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
c1e679ec | 7636 | /* 60 */ |
592d1631 L |
7637 | { Bad_Opcode }, |
7638 | { Bad_Opcode }, | |
7639 | { Bad_Opcode }, | |
7640 | { Bad_Opcode }, | |
7641 | { Bad_Opcode }, | |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
c0f3af97 | 7645 | /* 68 */ |
592d1631 L |
7646 | { Bad_Opcode }, |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
7650 | { Bad_Opcode }, | |
7651 | { Bad_Opcode }, | |
7652 | { Bad_Opcode }, | |
7653 | { Bad_Opcode }, | |
85f10a01 | 7654 | /* 70 */ |
592d1631 L |
7655 | { Bad_Opcode }, |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
85f10a01 | 7663 | /* 78 */ |
592d1631 L |
7664 | { Bad_Opcode }, |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
85f10a01 | 7672 | /* 80 */ |
592d1631 L |
7673 | { Bad_Opcode }, |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
3a2430e0 JB |
7678 | { "vpmacssww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7679 | { "vpmacsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7680 | { "vpmacssdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7681 | /* 88 */ |
592d1631 L |
7682 | { Bad_Opcode }, |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
7686 | { Bad_Opcode }, | |
7687 | { Bad_Opcode }, | |
3a2430e0 JB |
7688 | { "vpmacssdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7689 | { "vpmacssdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7690 | /* 90 */ |
592d1631 L |
7691 | { Bad_Opcode }, |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
3a2430e0 JB |
7696 | { "vpmacsww", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7697 | { "vpmacswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
7698 | { "vpmacsdql", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7699 | /* 98 */ |
592d1631 L |
7700 | { Bad_Opcode }, |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
3a2430e0 JB |
7706 | { "vpmacsdd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7707 | { "vpmacsdqh", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
5dd85c99 | 7708 | /* a0 */ |
592d1631 L |
7709 | { Bad_Opcode }, |
7710 | { Bad_Opcode }, | |
3a2430e0 JB |
7711 | { "vpcmov", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
7712 | { "vpperm", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, | |
592d1631 L |
7713 | { Bad_Opcode }, |
7714 | { Bad_Opcode }, | |
3a2430e0 | 7715 | { "vpmadcsswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7716 | { Bad_Opcode }, |
5dd85c99 | 7717 | /* a8 */ |
592d1631 L |
7718 | { Bad_Opcode }, |
7719 | { Bad_Opcode }, | |
7720 | { Bad_Opcode }, | |
7721 | { Bad_Opcode }, | |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
5dd85c99 | 7726 | /* b0 */ |
592d1631 L |
7727 | { Bad_Opcode }, |
7728 | { Bad_Opcode }, | |
7729 | { Bad_Opcode }, | |
7730 | { Bad_Opcode }, | |
7731 | { Bad_Opcode }, | |
7732 | { Bad_Opcode }, | |
3a2430e0 | 7733 | { "vpmadcswd", { XMVexW, Vex, EXVexW, EXVexW }, 0 }, |
592d1631 | 7734 | { Bad_Opcode }, |
5dd85c99 | 7735 | /* b8 */ |
592d1631 L |
7736 | { Bad_Opcode }, |
7737 | { Bad_Opcode }, | |
7738 | { Bad_Opcode }, | |
7739 | { Bad_Opcode }, | |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
5dd85c99 | 7744 | /* c0 */ |
bf890a93 IT |
7745 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7746 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7747 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7748 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7749 | { Bad_Opcode }, |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
5dd85c99 | 7753 | /* c8 */ |
592d1631 L |
7754 | { Bad_Opcode }, |
7755 | { Bad_Opcode }, | |
7756 | { Bad_Opcode }, | |
7757 | { Bad_Opcode }, | |
ff688e1f L |
7758 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7759 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7760 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7761 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7762 | /* d0 */ |
592d1631 L |
7763 | { Bad_Opcode }, |
7764 | { Bad_Opcode }, | |
7765 | { Bad_Opcode }, | |
7766 | { Bad_Opcode }, | |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
5dd85c99 | 7771 | /* d8 */ |
592d1631 L |
7772 | { Bad_Opcode }, |
7773 | { Bad_Opcode }, | |
7774 | { Bad_Opcode }, | |
7775 | { Bad_Opcode }, | |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
5dd85c99 | 7780 | /* e0 */ |
592d1631 L |
7781 | { Bad_Opcode }, |
7782 | { Bad_Opcode }, | |
7783 | { Bad_Opcode }, | |
7784 | { Bad_Opcode }, | |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
5dd85c99 | 7789 | /* e8 */ |
592d1631 L |
7790 | { Bad_Opcode }, |
7791 | { Bad_Opcode }, | |
7792 | { Bad_Opcode }, | |
7793 | { Bad_Opcode }, | |
ff688e1f L |
7794 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7795 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7796 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7797 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7798 | /* f0 */ |
592d1631 L |
7799 | { Bad_Opcode }, |
7800 | { Bad_Opcode }, | |
7801 | { Bad_Opcode }, | |
7802 | { Bad_Opcode }, | |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
5dd85c99 | 7807 | /* f8 */ |
592d1631 L |
7808 | { Bad_Opcode }, |
7809 | { Bad_Opcode }, | |
7810 | { Bad_Opcode }, | |
7811 | { Bad_Opcode }, | |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
5dd85c99 SP |
7816 | }, |
7817 | /* XOP_09 */ | |
7818 | { | |
7819 | /* 00 */ | |
592d1631 | 7820 | { Bad_Opcode }, |
2a2a0f38 QN |
7821 | { REG_TABLE (REG_XOP_TBM_01) }, |
7822 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7823 | { Bad_Opcode }, |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
5dd85c99 | 7828 | /* 08 */ |
592d1631 L |
7829 | { Bad_Opcode }, |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
5dd85c99 | 7837 | /* 10 */ |
592d1631 L |
7838 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, | |
5dd85c99 | 7840 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7841 | { Bad_Opcode }, |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
5dd85c99 | 7846 | /* 18 */ |
592d1631 L |
7847 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
5dd85c99 | 7855 | /* 20 */ |
592d1631 L |
7856 | { Bad_Opcode }, |
7857 | { Bad_Opcode }, | |
7858 | { Bad_Opcode }, | |
7859 | { Bad_Opcode }, | |
7860 | { Bad_Opcode }, | |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
5dd85c99 | 7864 | /* 28 */ |
592d1631 L |
7865 | { Bad_Opcode }, |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
5dd85c99 | 7873 | /* 30 */ |
592d1631 L |
7874 | { Bad_Opcode }, |
7875 | { Bad_Opcode }, | |
7876 | { Bad_Opcode }, | |
7877 | { Bad_Opcode }, | |
7878 | { Bad_Opcode }, | |
7879 | { Bad_Opcode }, | |
7880 | { Bad_Opcode }, | |
7881 | { Bad_Opcode }, | |
5dd85c99 | 7882 | /* 38 */ |
592d1631 L |
7883 | { Bad_Opcode }, |
7884 | { Bad_Opcode }, | |
7885 | { Bad_Opcode }, | |
7886 | { Bad_Opcode }, | |
7887 | { Bad_Opcode }, | |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
5dd85c99 | 7891 | /* 40 */ |
592d1631 L |
7892 | { Bad_Opcode }, |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
5dd85c99 | 7900 | /* 48 */ |
592d1631 L |
7901 | { Bad_Opcode }, |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
5dd85c99 | 7909 | /* 50 */ |
592d1631 L |
7910 | { Bad_Opcode }, |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
5dd85c99 | 7918 | /* 58 */ |
592d1631 L |
7919 | { Bad_Opcode }, |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
5dd85c99 | 7927 | /* 60 */ |
592d1631 L |
7928 | { Bad_Opcode }, |
7929 | { Bad_Opcode }, | |
7930 | { Bad_Opcode }, | |
7931 | { Bad_Opcode }, | |
7932 | { Bad_Opcode }, | |
7933 | { Bad_Opcode }, | |
7934 | { Bad_Opcode }, | |
7935 | { Bad_Opcode }, | |
5dd85c99 | 7936 | /* 68 */ |
592d1631 L |
7937 | { Bad_Opcode }, |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
7940 | { Bad_Opcode }, | |
7941 | { Bad_Opcode }, | |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
5dd85c99 | 7945 | /* 70 */ |
592d1631 L |
7946 | { Bad_Opcode }, |
7947 | { Bad_Opcode }, | |
7948 | { Bad_Opcode }, | |
7949 | { Bad_Opcode }, | |
7950 | { Bad_Opcode }, | |
7951 | { Bad_Opcode }, | |
7952 | { Bad_Opcode }, | |
7953 | { Bad_Opcode }, | |
5dd85c99 | 7954 | /* 78 */ |
592d1631 L |
7955 | { Bad_Opcode }, |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
7958 | { Bad_Opcode }, | |
7959 | { Bad_Opcode }, | |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
5dd85c99 | 7963 | /* 80 */ |
592a252b L |
7964 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_80) }, |
7965 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_81) }, | |
bf890a93 IT |
7966 | { "vfrczss", { XM, EXd }, 0 }, |
7967 | { "vfrczsd", { XM, EXq }, 0 }, | |
592d1631 L |
7968 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
5dd85c99 | 7972 | /* 88 */ |
592d1631 L |
7973 | { Bad_Opcode }, |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
5dd85c99 | 7981 | /* 90 */ |
bf890a93 IT |
7982 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7983 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7984 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7985 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7986 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7987 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7988 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7989 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7990 | /* 98 */ |
bf890a93 IT |
7991 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7992 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7993 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7994 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7995 | { Bad_Opcode }, |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
5dd85c99 | 7999 | /* a0 */ |
592d1631 L |
8000 | { Bad_Opcode }, |
8001 | { Bad_Opcode }, | |
8002 | { Bad_Opcode }, | |
8003 | { Bad_Opcode }, | |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
5dd85c99 | 8008 | /* a8 */ |
592d1631 L |
8009 | { Bad_Opcode }, |
8010 | { Bad_Opcode }, | |
8011 | { Bad_Opcode }, | |
8012 | { Bad_Opcode }, | |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
5dd85c99 | 8017 | /* b0 */ |
592d1631 L |
8018 | { Bad_Opcode }, |
8019 | { Bad_Opcode }, | |
8020 | { Bad_Opcode }, | |
8021 | { Bad_Opcode }, | |
8022 | { Bad_Opcode }, | |
8023 | { Bad_Opcode }, | |
8024 | { Bad_Opcode }, | |
8025 | { Bad_Opcode }, | |
5dd85c99 | 8026 | /* b8 */ |
592d1631 L |
8027 | { Bad_Opcode }, |
8028 | { Bad_Opcode }, | |
8029 | { Bad_Opcode }, | |
8030 | { Bad_Opcode }, | |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
5dd85c99 | 8035 | /* c0 */ |
592d1631 | 8036 | { Bad_Opcode }, |
bf890a93 IT |
8037 | { "vphaddbw", { XM, EXxmm }, 0 }, |
8038 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
8039 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8040 | { Bad_Opcode }, |
8041 | { Bad_Opcode }, | |
bf890a93 IT |
8042 | { "vphaddwd", { XM, EXxmm }, 0 }, |
8043 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8044 | /* c8 */ |
592d1631 L |
8045 | { Bad_Opcode }, |
8046 | { Bad_Opcode }, | |
8047 | { Bad_Opcode }, | |
bf890a93 | 8048 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
8049 | { Bad_Opcode }, |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
5dd85c99 | 8053 | /* d0 */ |
592d1631 | 8054 | { Bad_Opcode }, |
bf890a93 IT |
8055 | { "vphaddubw", { XM, EXxmm }, 0 }, |
8056 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
8057 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8058 | { Bad_Opcode }, |
8059 | { Bad_Opcode }, | |
bf890a93 IT |
8060 | { "vphadduwd", { XM, EXxmm }, 0 }, |
8061 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 8062 | /* d8 */ |
592d1631 L |
8063 | { Bad_Opcode }, |
8064 | { Bad_Opcode }, | |
8065 | { Bad_Opcode }, | |
bf890a93 | 8066 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
8067 | { Bad_Opcode }, |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
5dd85c99 | 8071 | /* e0 */ |
592d1631 | 8072 | { Bad_Opcode }, |
bf890a93 IT |
8073 | { "vphsubbw", { XM, EXxmm }, 0 }, |
8074 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
8075 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
8076 | { Bad_Opcode }, |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
4e7d34a6 | 8080 | /* e8 */ |
592d1631 L |
8081 | { Bad_Opcode }, |
8082 | { Bad_Opcode }, | |
8083 | { Bad_Opcode }, | |
8084 | { Bad_Opcode }, | |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
4e7d34a6 | 8089 | /* f0 */ |
592d1631 L |
8090 | { Bad_Opcode }, |
8091 | { Bad_Opcode }, | |
8092 | { Bad_Opcode }, | |
8093 | { Bad_Opcode }, | |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
4e7d34a6 | 8098 | /* f8 */ |
592d1631 L |
8099 | { Bad_Opcode }, |
8100 | { Bad_Opcode }, | |
8101 | { Bad_Opcode }, | |
8102 | { Bad_Opcode }, | |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
4e7d34a6 | 8107 | }, |
f88c9eb0 | 8108 | /* XOP_0A */ |
4e7d34a6 L |
8109 | { |
8110 | /* 00 */ | |
592d1631 L |
8111 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
4e7d34a6 | 8119 | /* 08 */ |
592d1631 L |
8120 | { Bad_Opcode }, |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
4e7d34a6 | 8128 | /* 10 */ |
bf890a93 | 8129 | { "bextr", { Gv, Ev, Iq }, 0 }, |
592d1631 | 8130 | { Bad_Opcode }, |
f88c9eb0 | 8131 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8132 | { Bad_Opcode }, |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
4e7d34a6 | 8137 | /* 18 */ |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
4e7d34a6 | 8146 | /* 20 */ |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
4e7d34a6 | 8155 | /* 28 */ |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
4e7d34a6 | 8164 | /* 30 */ |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
c0f3af97 | 8173 | /* 38 */ |
592d1631 L |
8174 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
c0f3af97 | 8182 | /* 40 */ |
592d1631 L |
8183 | { Bad_Opcode }, |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
c1e679ec | 8191 | /* 48 */ |
592d1631 L |
8192 | { Bad_Opcode }, |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
c1e679ec | 8200 | /* 50 */ |
592d1631 L |
8201 | { Bad_Opcode }, |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
4e7d34a6 | 8209 | /* 58 */ |
592d1631 L |
8210 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
4e7d34a6 | 8218 | /* 60 */ |
592d1631 L |
8219 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
4e7d34a6 | 8227 | /* 68 */ |
592d1631 L |
8228 | { Bad_Opcode }, |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
4e7d34a6 | 8236 | /* 70 */ |
592d1631 L |
8237 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
4e7d34a6 | 8245 | /* 78 */ |
592d1631 L |
8246 | { Bad_Opcode }, |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
4e7d34a6 | 8254 | /* 80 */ |
592d1631 L |
8255 | { Bad_Opcode }, |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
4e7d34a6 | 8263 | /* 88 */ |
592d1631 L |
8264 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
4e7d34a6 | 8272 | /* 90 */ |
592d1631 L |
8273 | { Bad_Opcode }, |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
4e7d34a6 | 8281 | /* 98 */ |
592d1631 L |
8282 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
4e7d34a6 | 8290 | /* a0 */ |
592d1631 L |
8291 | { Bad_Opcode }, |
8292 | { Bad_Opcode }, | |
8293 | { Bad_Opcode }, | |
8294 | { Bad_Opcode }, | |
8295 | { Bad_Opcode }, | |
8296 | { Bad_Opcode }, | |
8297 | { Bad_Opcode }, | |
8298 | { Bad_Opcode }, | |
4e7d34a6 | 8299 | /* a8 */ |
592d1631 L |
8300 | { Bad_Opcode }, |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
8305 | { Bad_Opcode }, | |
8306 | { Bad_Opcode }, | |
8307 | { Bad_Opcode }, | |
d5d7db8e | 8308 | /* b0 */ |
592d1631 L |
8309 | { Bad_Opcode }, |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
8314 | { Bad_Opcode }, | |
8315 | { Bad_Opcode }, | |
8316 | { Bad_Opcode }, | |
85f10a01 | 8317 | /* b8 */ |
592d1631 L |
8318 | { Bad_Opcode }, |
8319 | { Bad_Opcode }, | |
8320 | { Bad_Opcode }, | |
8321 | { Bad_Opcode }, | |
8322 | { Bad_Opcode }, | |
8323 | { Bad_Opcode }, | |
8324 | { Bad_Opcode }, | |
8325 | { Bad_Opcode }, | |
85f10a01 | 8326 | /* c0 */ |
592d1631 L |
8327 | { Bad_Opcode }, |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
8332 | { Bad_Opcode }, | |
8333 | { Bad_Opcode }, | |
8334 | { Bad_Opcode }, | |
85f10a01 | 8335 | /* c8 */ |
592d1631 L |
8336 | { Bad_Opcode }, |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
8341 | { Bad_Opcode }, | |
8342 | { Bad_Opcode }, | |
8343 | { Bad_Opcode }, | |
85f10a01 | 8344 | /* d0 */ |
592d1631 L |
8345 | { Bad_Opcode }, |
8346 | { Bad_Opcode }, | |
8347 | { Bad_Opcode }, | |
8348 | { Bad_Opcode }, | |
8349 | { Bad_Opcode }, | |
8350 | { Bad_Opcode }, | |
8351 | { Bad_Opcode }, | |
8352 | { Bad_Opcode }, | |
85f10a01 | 8353 | /* d8 */ |
592d1631 L |
8354 | { Bad_Opcode }, |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
8359 | { Bad_Opcode }, | |
8360 | { Bad_Opcode }, | |
8361 | { Bad_Opcode }, | |
85f10a01 | 8362 | /* e0 */ |
592d1631 L |
8363 | { Bad_Opcode }, |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
8368 | { Bad_Opcode }, | |
8369 | { Bad_Opcode }, | |
8370 | { Bad_Opcode }, | |
85f10a01 | 8371 | /* e8 */ |
592d1631 L |
8372 | { Bad_Opcode }, |
8373 | { Bad_Opcode }, | |
8374 | { Bad_Opcode }, | |
8375 | { Bad_Opcode }, | |
8376 | { Bad_Opcode }, | |
8377 | { Bad_Opcode }, | |
8378 | { Bad_Opcode }, | |
8379 | { Bad_Opcode }, | |
85f10a01 | 8380 | /* f0 */ |
592d1631 L |
8381 | { Bad_Opcode }, |
8382 | { Bad_Opcode }, | |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
8386 | { Bad_Opcode }, | |
8387 | { Bad_Opcode }, | |
8388 | { Bad_Opcode }, | |
85f10a01 | 8389 | /* f8 */ |
592d1631 L |
8390 | { Bad_Opcode }, |
8391 | { Bad_Opcode }, | |
8392 | { Bad_Opcode }, | |
8393 | { Bad_Opcode }, | |
8394 | { Bad_Opcode }, | |
8395 | { Bad_Opcode }, | |
8396 | { Bad_Opcode }, | |
8397 | { Bad_Opcode }, | |
85f10a01 | 8398 | }, |
c0f3af97 L |
8399 | }; |
8400 | ||
8401 | static const struct dis386 vex_table[][256] = { | |
8402 | /* VEX_0F */ | |
85f10a01 MM |
8403 | { |
8404 | /* 00 */ | |
592d1631 L |
8405 | { Bad_Opcode }, |
8406 | { Bad_Opcode }, | |
8407 | { Bad_Opcode }, | |
8408 | { Bad_Opcode }, | |
8409 | { Bad_Opcode }, | |
8410 | { Bad_Opcode }, | |
8411 | { Bad_Opcode }, | |
8412 | { Bad_Opcode }, | |
85f10a01 | 8413 | /* 08 */ |
592d1631 L |
8414 | { Bad_Opcode }, |
8415 | { Bad_Opcode }, | |
8416 | { Bad_Opcode }, | |
8417 | { Bad_Opcode }, | |
8418 | { Bad_Opcode }, | |
8419 | { Bad_Opcode }, | |
8420 | { Bad_Opcode }, | |
8421 | { Bad_Opcode }, | |
c0f3af97 | 8422 | /* 10 */ |
592a252b L |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8424 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8425 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8426 | { MOD_TABLE (MOD_VEX_0F13) }, | |
ec6f095a L |
8427 | { "vunpcklpX", { XM, Vex, EXx }, 0 }, |
8428 | { "vunpckhpX", { XM, Vex, EXx }, 0 }, | |
592a252b L |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8430 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8431 | /* 18 */ |
592d1631 L |
8432 | { Bad_Opcode }, |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
8436 | { Bad_Opcode }, | |
8437 | { Bad_Opcode }, | |
8438 | { Bad_Opcode }, | |
8439 | { Bad_Opcode }, | |
c0f3af97 | 8440 | /* 20 */ |
592d1631 L |
8441 | { Bad_Opcode }, |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
c0f3af97 | 8449 | /* 28 */ |
ec6f095a L |
8450 | { "vmovapX", { XM, EXx }, 0 }, |
8451 | { "vmovapX", { EXxS, XM }, 0 }, | |
592a252b L |
8452 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8453 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8454 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8455 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8456 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8457 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8458 | /* 30 */ |
592d1631 L |
8459 | { Bad_Opcode }, |
8460 | { Bad_Opcode }, | |
8461 | { Bad_Opcode }, | |
8462 | { Bad_Opcode }, | |
8463 | { Bad_Opcode }, | |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
4e7d34a6 | 8467 | /* 38 */ |
592d1631 L |
8468 | { Bad_Opcode }, |
8469 | { Bad_Opcode }, | |
8470 | { Bad_Opcode }, | |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
d5d7db8e | 8476 | /* 40 */ |
592d1631 | 8477 | { Bad_Opcode }, |
43234a1e L |
8478 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8479 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8480 | { Bad_Opcode }, |
43234a1e L |
8481 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8482 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8483 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8484 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8485 | /* 48 */ |
592d1631 L |
8486 | { Bad_Opcode }, |
8487 | { Bad_Opcode }, | |
1ba585e8 | 8488 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8489 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8490 | { Bad_Opcode }, |
8491 | { Bad_Opcode }, | |
8492 | { Bad_Opcode }, | |
8493 | { Bad_Opcode }, | |
d5d7db8e | 8494 | /* 50 */ |
592a252b L |
8495 | { MOD_TABLE (MOD_VEX_0F50) }, |
8496 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8497 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8498 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf890a93 IT |
8499 | { "vandpX", { XM, Vex, EXx }, 0 }, |
8500 | { "vandnpX", { XM, Vex, EXx }, 0 }, | |
8501 | { "vorpX", { XM, Vex, EXx }, 0 }, | |
8502 | { "vxorpX", { XM, Vex, EXx }, 0 }, | |
c0f3af97 | 8503 | /* 58 */ |
592a252b L |
8504 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8505 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8506 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8507 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8508 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8509 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8510 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8511 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8512 | /* 60 */ |
592a252b L |
8513 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8514 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8515 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8516 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8517 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8518 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8519 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8520 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8521 | /* 68 */ |
592a252b L |
8522 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8523 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8524 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8525 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8526 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8527 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8528 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8529 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8530 | /* 70 */ |
592a252b L |
8531 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8532 | { REG_TABLE (REG_VEX_0F71) }, | |
8533 | { REG_TABLE (REG_VEX_0F72) }, | |
8534 | { REG_TABLE (REG_VEX_0F73) }, | |
8535 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8536 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8537 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8538 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8539 | /* 78 */ |
592d1631 L |
8540 | { Bad_Opcode }, |
8541 | { Bad_Opcode }, | |
8542 | { Bad_Opcode }, | |
8543 | { Bad_Opcode }, | |
592a252b L |
8544 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8545 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8546 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8547 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8548 | /* 80 */ |
592d1631 L |
8549 | { Bad_Opcode }, |
8550 | { Bad_Opcode }, | |
8551 | { Bad_Opcode }, | |
8552 | { Bad_Opcode }, | |
8553 | { Bad_Opcode }, | |
8554 | { Bad_Opcode }, | |
8555 | { Bad_Opcode }, | |
8556 | { Bad_Opcode }, | |
c0f3af97 | 8557 | /* 88 */ |
592d1631 L |
8558 | { Bad_Opcode }, |
8559 | { Bad_Opcode }, | |
8560 | { Bad_Opcode }, | |
8561 | { Bad_Opcode }, | |
8562 | { Bad_Opcode }, | |
8563 | { Bad_Opcode }, | |
8564 | { Bad_Opcode }, | |
8565 | { Bad_Opcode }, | |
c0f3af97 | 8566 | /* 90 */ |
43234a1e L |
8567 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8568 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8571 | { Bad_Opcode }, |
8572 | { Bad_Opcode }, | |
8573 | { Bad_Opcode }, | |
8574 | { Bad_Opcode }, | |
c0f3af97 | 8575 | /* 98 */ |
43234a1e | 8576 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8577 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8578 | { Bad_Opcode }, |
8579 | { Bad_Opcode }, | |
8580 | { Bad_Opcode }, | |
8581 | { Bad_Opcode }, | |
8582 | { Bad_Opcode }, | |
8583 | { Bad_Opcode }, | |
c0f3af97 | 8584 | /* a0 */ |
592d1631 L |
8585 | { Bad_Opcode }, |
8586 | { Bad_Opcode }, | |
8587 | { Bad_Opcode }, | |
8588 | { Bad_Opcode }, | |
8589 | { Bad_Opcode }, | |
8590 | { Bad_Opcode }, | |
8591 | { Bad_Opcode }, | |
8592 | { Bad_Opcode }, | |
c0f3af97 | 8593 | /* a8 */ |
592d1631 L |
8594 | { Bad_Opcode }, |
8595 | { Bad_Opcode }, | |
8596 | { Bad_Opcode }, | |
8597 | { Bad_Opcode }, | |
8598 | { Bad_Opcode }, | |
8599 | { Bad_Opcode }, | |
592a252b | 8600 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8601 | { Bad_Opcode }, |
c0f3af97 | 8602 | /* b0 */ |
592d1631 L |
8603 | { Bad_Opcode }, |
8604 | { Bad_Opcode }, | |
8605 | { Bad_Opcode }, | |
8606 | { Bad_Opcode }, | |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
8609 | { Bad_Opcode }, | |
8610 | { Bad_Opcode }, | |
c0f3af97 | 8611 | /* b8 */ |
592d1631 L |
8612 | { Bad_Opcode }, |
8613 | { Bad_Opcode }, | |
8614 | { Bad_Opcode }, | |
8615 | { Bad_Opcode }, | |
8616 | { Bad_Opcode }, | |
8617 | { Bad_Opcode }, | |
8618 | { Bad_Opcode }, | |
8619 | { Bad_Opcode }, | |
c0f3af97 | 8620 | /* c0 */ |
592d1631 L |
8621 | { Bad_Opcode }, |
8622 | { Bad_Opcode }, | |
592a252b | 8623 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8624 | { Bad_Opcode }, |
592a252b L |
8625 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8626 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf890a93 | 8627 | { "vshufpX", { XM, Vex, EXx, Ib }, 0 }, |
592d1631 | 8628 | { Bad_Opcode }, |
c0f3af97 | 8629 | /* c8 */ |
592d1631 L |
8630 | { Bad_Opcode }, |
8631 | { Bad_Opcode }, | |
8632 | { Bad_Opcode }, | |
8633 | { Bad_Opcode }, | |
8634 | { Bad_Opcode }, | |
8635 | { Bad_Opcode }, | |
8636 | { Bad_Opcode }, | |
8637 | { Bad_Opcode }, | |
c0f3af97 | 8638 | /* d0 */ |
592a252b L |
8639 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8640 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8641 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8642 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8643 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8647 | /* d8 */ |
592a252b L |
8648 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8649 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8650 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8651 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8652 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8656 | /* e0 */ |
592a252b L |
8657 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8658 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8659 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8660 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8661 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8662 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8663 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8664 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8665 | /* e8 */ |
592a252b L |
8666 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8667 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8668 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8669 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8670 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8671 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8672 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8673 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8674 | /* f0 */ |
592a252b L |
8675 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8676 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8677 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8678 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8679 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8680 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8681 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8682 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8683 | /* f8 */ |
592a252b L |
8684 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8685 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8686 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8687 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8688 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8690 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8691 | { Bad_Opcode }, |
c0f3af97 L |
8692 | }, |
8693 | /* VEX_0F38 */ | |
8694 | { | |
8695 | /* 00 */ | |
592a252b L |
8696 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8697 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8698 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8699 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8700 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8701 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8702 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8703 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8704 | /* 08 */ |
592a252b L |
8705 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8706 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8707 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8708 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8709 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8710 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8711 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8712 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8713 | /* 10 */ |
592d1631 L |
8714 | { Bad_Opcode }, |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
592a252b | 8717 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8718 | { Bad_Opcode }, |
8719 | { Bad_Opcode }, | |
6c30d220 | 8720 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8721 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8722 | /* 18 */ |
592a252b L |
8723 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8724 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8725 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8726 | { Bad_Opcode }, |
592a252b L |
8727 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8728 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8729 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8730 | { Bad_Opcode }, |
c0f3af97 | 8731 | /* 20 */ |
592a252b L |
8732 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8733 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8734 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8735 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8736 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8737 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8738 | { Bad_Opcode }, |
8739 | { Bad_Opcode }, | |
c0f3af97 | 8740 | /* 28 */ |
592a252b L |
8741 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8742 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8743 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8744 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8745 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8746 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8747 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8748 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8749 | /* 30 */ |
592a252b L |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8751 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8754 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8755 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8756 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8757 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8758 | /* 38 */ |
592a252b L |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8767 | /* 40 */ |
592a252b L |
8768 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8769 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8770 | { Bad_Opcode }, |
8771 | { Bad_Opcode }, | |
8772 | { Bad_Opcode }, | |
6c30d220 L |
8773 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8776 | /* 48 */ |
592d1631 L |
8777 | { Bad_Opcode }, |
8778 | { Bad_Opcode }, | |
8779 | { Bad_Opcode }, | |
8780 | { Bad_Opcode }, | |
8781 | { Bad_Opcode }, | |
8782 | { Bad_Opcode }, | |
8783 | { Bad_Opcode }, | |
8784 | { Bad_Opcode }, | |
c0f3af97 | 8785 | /* 50 */ |
592d1631 L |
8786 | { Bad_Opcode }, |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
8789 | { Bad_Opcode }, | |
8790 | { Bad_Opcode }, | |
8791 | { Bad_Opcode }, | |
8792 | { Bad_Opcode }, | |
8793 | { Bad_Opcode }, | |
c0f3af97 | 8794 | /* 58 */ |
6c30d220 L |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8798 | { Bad_Opcode }, |
8799 | { Bad_Opcode }, | |
8800 | { Bad_Opcode }, | |
8801 | { Bad_Opcode }, | |
8802 | { Bad_Opcode }, | |
c0f3af97 | 8803 | /* 60 */ |
592d1631 L |
8804 | { Bad_Opcode }, |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
c0f3af97 | 8812 | /* 68 */ |
592d1631 L |
8813 | { Bad_Opcode }, |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
8820 | { Bad_Opcode }, | |
c0f3af97 | 8821 | /* 70 */ |
592d1631 L |
8822 | { Bad_Opcode }, |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
c0f3af97 | 8830 | /* 78 */ |
6c30d220 L |
8831 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8832 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8833 | { Bad_Opcode }, |
8834 | { Bad_Opcode }, | |
8835 | { Bad_Opcode }, | |
8836 | { Bad_Opcode }, | |
8837 | { Bad_Opcode }, | |
8838 | { Bad_Opcode }, | |
c0f3af97 | 8839 | /* 80 */ |
592d1631 L |
8840 | { Bad_Opcode }, |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
c0f3af97 | 8848 | /* 88 */ |
592d1631 L |
8849 | { Bad_Opcode }, |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
6c30d220 | 8853 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8854 | { Bad_Opcode }, |
6c30d220 | 8855 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8856 | { Bad_Opcode }, |
c0f3af97 | 8857 | /* 90 */ |
6c30d220 L |
8858 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8859 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8861 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8862 | { Bad_Opcode }, |
8863 | { Bad_Opcode }, | |
592a252b L |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8865 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8866 | /* 98 */ |
592a252b L |
8867 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8868 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8869 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8870 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8871 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8872 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8873 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8874 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8875 | /* a0 */ |
592d1631 L |
8876 | { Bad_Opcode }, |
8877 | { Bad_Opcode }, | |
8878 | { Bad_Opcode }, | |
8879 | { Bad_Opcode }, | |
8880 | { Bad_Opcode }, | |
8881 | { Bad_Opcode }, | |
592a252b L |
8882 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8883 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8884 | /* a8 */ |
592a252b L |
8885 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8886 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8887 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8893 | /* b0 */ |
592d1631 L |
8894 | { Bad_Opcode }, |
8895 | { Bad_Opcode }, | |
8896 | { Bad_Opcode }, | |
8897 | { Bad_Opcode }, | |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
592a252b L |
8900 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8902 | /* b8 */ |
592a252b L |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8905 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8908 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8909 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8910 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8911 | /* c0 */ |
592d1631 L |
8912 | { Bad_Opcode }, |
8913 | { Bad_Opcode }, | |
8914 | { Bad_Opcode }, | |
8915 | { Bad_Opcode }, | |
8916 | { Bad_Opcode }, | |
8917 | { Bad_Opcode }, | |
8918 | { Bad_Opcode }, | |
8919 | { Bad_Opcode }, | |
c0f3af97 | 8920 | /* c8 */ |
592d1631 L |
8921 | { Bad_Opcode }, |
8922 | { Bad_Opcode }, | |
8923 | { Bad_Opcode }, | |
8924 | { Bad_Opcode }, | |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
48521003 | 8928 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8929 | /* d0 */ |
592d1631 L |
8930 | { Bad_Opcode }, |
8931 | { Bad_Opcode }, | |
8932 | { Bad_Opcode }, | |
8933 | { Bad_Opcode }, | |
8934 | { Bad_Opcode }, | |
8935 | { Bad_Opcode }, | |
8936 | { Bad_Opcode }, | |
8937 | { Bad_Opcode }, | |
c0f3af97 | 8938 | /* d8 */ |
592d1631 L |
8939 | { Bad_Opcode }, |
8940 | { Bad_Opcode }, | |
8941 | { Bad_Opcode }, | |
592a252b L |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8944 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8945 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8946 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8947 | /* e0 */ |
592d1631 L |
8948 | { Bad_Opcode }, |
8949 | { Bad_Opcode }, | |
8950 | { Bad_Opcode }, | |
8951 | { Bad_Opcode }, | |
8952 | { Bad_Opcode }, | |
8953 | { Bad_Opcode }, | |
8954 | { Bad_Opcode }, | |
8955 | { Bad_Opcode }, | |
c0f3af97 | 8956 | /* e8 */ |
592d1631 L |
8957 | { Bad_Opcode }, |
8958 | { Bad_Opcode }, | |
8959 | { Bad_Opcode }, | |
8960 | { Bad_Opcode }, | |
8961 | { Bad_Opcode }, | |
8962 | { Bad_Opcode }, | |
8963 | { Bad_Opcode }, | |
8964 | { Bad_Opcode }, | |
c0f3af97 | 8965 | /* f0 */ |
592d1631 L |
8966 | { Bad_Opcode }, |
8967 | { Bad_Opcode }, | |
f12dc422 L |
8968 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8969 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8970 | { Bad_Opcode }, |
6c30d220 L |
8971 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8972 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8973 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8974 | /* f8 */ |
592d1631 L |
8975 | { Bad_Opcode }, |
8976 | { Bad_Opcode }, | |
8977 | { Bad_Opcode }, | |
8978 | { Bad_Opcode }, | |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
8982 | { Bad_Opcode }, | |
c0f3af97 L |
8983 | }, |
8984 | /* VEX_0F3A */ | |
8985 | { | |
8986 | /* 00 */ | |
6c30d220 L |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8990 | { Bad_Opcode }, |
592a252b L |
8991 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8992 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8993 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8994 | { Bad_Opcode }, |
c0f3af97 | 8995 | /* 08 */ |
592a252b L |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 9004 | /* 10 */ |
592d1631 L |
9005 | { Bad_Opcode }, |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
592a252b L |
9009 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
9010 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
9011 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
9012 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 9013 | /* 18 */ |
592a252b L |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
9016 | { Bad_Opcode }, |
9017 | { Bad_Opcode }, | |
9018 | { Bad_Opcode }, | |
592a252b | 9019 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
9020 | { Bad_Opcode }, |
9021 | { Bad_Opcode }, | |
c0f3af97 | 9022 | /* 20 */ |
592a252b L |
9023 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
9024 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
9025 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
9026 | { Bad_Opcode }, |
9027 | { Bad_Opcode }, | |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
c0f3af97 | 9031 | /* 28 */ |
592d1631 L |
9032 | { Bad_Opcode }, |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
c0f3af97 | 9040 | /* 30 */ |
43234a1e | 9041 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 9042 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 9043 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 9044 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
9045 | { Bad_Opcode }, |
9046 | { Bad_Opcode }, | |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
c0f3af97 | 9049 | /* 38 */ |
6c30d220 L |
9050 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
9051 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
9052 | { Bad_Opcode }, |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
c0f3af97 | 9058 | /* 40 */ |
592a252b L |
9059 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
9060 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
9061 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 9062 | { Bad_Opcode }, |
592a252b | 9063 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 9064 | { Bad_Opcode }, |
6c30d220 | 9065 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 9066 | { Bad_Opcode }, |
c0f3af97 | 9067 | /* 48 */ |
592a252b L |
9068 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
9069 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
9070 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
9071 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
9072 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
9073 | { Bad_Opcode }, |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
c0f3af97 | 9076 | /* 50 */ |
592d1631 L |
9077 | { Bad_Opcode }, |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
c0f3af97 | 9085 | /* 58 */ |
592d1631 L |
9086 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
592a252b L |
9090 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
9091 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
9092 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
9093 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 9094 | /* 60 */ |
592a252b L |
9095 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
9096 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
9097 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
9098 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
9099 | { Bad_Opcode }, |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
c0f3af97 | 9103 | /* 68 */ |
592a252b L |
9104 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
9105 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
9106 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
9107 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9108 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9109 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9110 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9111 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9112 | /* 70 */ |
592d1631 L |
9113 | { Bad_Opcode }, |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
c0f3af97 | 9121 | /* 78 */ |
592a252b L |
9122 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9123 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9124 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9125 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9126 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9127 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9128 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9129 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9130 | /* 80 */ |
592d1631 L |
9131 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
c0f3af97 | 9139 | /* 88 */ |
592d1631 L |
9140 | { Bad_Opcode }, |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
c0f3af97 | 9148 | /* 90 */ |
592d1631 L |
9149 | { Bad_Opcode }, |
9150 | { Bad_Opcode }, | |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
c0f3af97 | 9157 | /* 98 */ |
592d1631 L |
9158 | { Bad_Opcode }, |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
c0f3af97 | 9166 | /* a0 */ |
592d1631 L |
9167 | { Bad_Opcode }, |
9168 | { Bad_Opcode }, | |
9169 | { Bad_Opcode }, | |
9170 | { Bad_Opcode }, | |
9171 | { Bad_Opcode }, | |
9172 | { Bad_Opcode }, | |
9173 | { Bad_Opcode }, | |
9174 | { Bad_Opcode }, | |
c0f3af97 | 9175 | /* a8 */ |
592d1631 L |
9176 | { Bad_Opcode }, |
9177 | { Bad_Opcode }, | |
9178 | { Bad_Opcode }, | |
9179 | { Bad_Opcode }, | |
9180 | { Bad_Opcode }, | |
9181 | { Bad_Opcode }, | |
9182 | { Bad_Opcode }, | |
9183 | { Bad_Opcode }, | |
c0f3af97 | 9184 | /* b0 */ |
592d1631 L |
9185 | { Bad_Opcode }, |
9186 | { Bad_Opcode }, | |
9187 | { Bad_Opcode }, | |
9188 | { Bad_Opcode }, | |
9189 | { Bad_Opcode }, | |
9190 | { Bad_Opcode }, | |
9191 | { Bad_Opcode }, | |
9192 | { Bad_Opcode }, | |
c0f3af97 | 9193 | /* b8 */ |
592d1631 L |
9194 | { Bad_Opcode }, |
9195 | { Bad_Opcode }, | |
9196 | { Bad_Opcode }, | |
9197 | { Bad_Opcode }, | |
9198 | { Bad_Opcode }, | |
9199 | { Bad_Opcode }, | |
9200 | { Bad_Opcode }, | |
9201 | { Bad_Opcode }, | |
c0f3af97 | 9202 | /* c0 */ |
592d1631 L |
9203 | { Bad_Opcode }, |
9204 | { Bad_Opcode }, | |
9205 | { Bad_Opcode }, | |
9206 | { Bad_Opcode }, | |
9207 | { Bad_Opcode }, | |
9208 | { Bad_Opcode }, | |
9209 | { Bad_Opcode }, | |
9210 | { Bad_Opcode }, | |
c0f3af97 | 9211 | /* c8 */ |
592d1631 L |
9212 | { Bad_Opcode }, |
9213 | { Bad_Opcode }, | |
9214 | { Bad_Opcode }, | |
9215 | { Bad_Opcode }, | |
9216 | { Bad_Opcode }, | |
9217 | { Bad_Opcode }, | |
48521003 IT |
9218 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9219 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9220 | /* d0 */ |
592d1631 L |
9221 | { Bad_Opcode }, |
9222 | { Bad_Opcode }, | |
9223 | { Bad_Opcode }, | |
9224 | { Bad_Opcode }, | |
9225 | { Bad_Opcode }, | |
9226 | { Bad_Opcode }, | |
9227 | { Bad_Opcode }, | |
9228 | { Bad_Opcode }, | |
c0f3af97 | 9229 | /* d8 */ |
592d1631 L |
9230 | { Bad_Opcode }, |
9231 | { Bad_Opcode }, | |
9232 | { Bad_Opcode }, | |
9233 | { Bad_Opcode }, | |
9234 | { Bad_Opcode }, | |
9235 | { Bad_Opcode }, | |
9236 | { Bad_Opcode }, | |
592a252b | 9237 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9238 | /* e0 */ |
592d1631 L |
9239 | { Bad_Opcode }, |
9240 | { Bad_Opcode }, | |
9241 | { Bad_Opcode }, | |
9242 | { Bad_Opcode }, | |
9243 | { Bad_Opcode }, | |
9244 | { Bad_Opcode }, | |
9245 | { Bad_Opcode }, | |
9246 | { Bad_Opcode }, | |
c0f3af97 | 9247 | /* e8 */ |
592d1631 L |
9248 | { Bad_Opcode }, |
9249 | { Bad_Opcode }, | |
9250 | { Bad_Opcode }, | |
9251 | { Bad_Opcode }, | |
9252 | { Bad_Opcode }, | |
9253 | { Bad_Opcode }, | |
9254 | { Bad_Opcode }, | |
9255 | { Bad_Opcode }, | |
c0f3af97 | 9256 | /* f0 */ |
6c30d220 | 9257 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9258 | { Bad_Opcode }, |
9259 | { Bad_Opcode }, | |
9260 | { Bad_Opcode }, | |
9261 | { Bad_Opcode }, | |
9262 | { Bad_Opcode }, | |
9263 | { Bad_Opcode }, | |
9264 | { Bad_Opcode }, | |
c0f3af97 | 9265 | /* f8 */ |
592d1631 L |
9266 | { Bad_Opcode }, |
9267 | { Bad_Opcode }, | |
9268 | { Bad_Opcode }, | |
9269 | { Bad_Opcode }, | |
9270 | { Bad_Opcode }, | |
9271 | { Bad_Opcode }, | |
9272 | { Bad_Opcode }, | |
9273 | { Bad_Opcode }, | |
c0f3af97 L |
9274 | }, |
9275 | }; | |
9276 | ||
43234a1e L |
9277 | #define NEED_OPCODE_TABLE |
9278 | #include "i386-dis-evex.h" | |
9279 | #undef NEED_OPCODE_TABLE | |
c0f3af97 | 9280 | static const struct dis386 vex_len_table[][2] = { |
592a252b | 9281 | /* VEX_LEN_0F12_P_0_M_0 */ |
c0f3af97 | 9282 | { |
ec6f095a | 9283 | { "vmovlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9284 | }, |
9285 | ||
592a252b | 9286 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9287 | { |
ec6f095a | 9288 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9289 | }, |
9290 | ||
592a252b | 9291 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 9292 | { |
ec6f095a | 9293 | { "vmovlpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9294 | }, |
9295 | ||
592a252b | 9296 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9297 | { |
ec6f095a | 9298 | { "vmovlpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9299 | }, |
9300 | ||
592a252b | 9301 | /* VEX_LEN_0F16_P_0_M_0 */ |
c0f3af97 | 9302 | { |
ec6f095a | 9303 | { "vmovhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9304 | }, |
9305 | ||
592a252b | 9306 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9307 | { |
ec6f095a | 9308 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9309 | }, |
9310 | ||
592a252b | 9311 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 9312 | { |
ec6f095a | 9313 | { "vmovhpd", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9314 | }, |
9315 | ||
592a252b | 9316 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9317 | { |
ec6f095a | 9318 | { "vmovhpX", { EXq, XM }, 0 }, |
c0f3af97 L |
9319 | }, |
9320 | ||
592a252b | 9321 | /* VEX_LEN_0F2A_P_1 */ |
c0f3af97 | 9322 | { |
bf890a93 IT |
9323 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9324 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9325 | }, |
9326 | ||
592a252b | 9327 | /* VEX_LEN_0F2A_P_3 */ |
c0f3af97 | 9328 | { |
bf890a93 IT |
9329 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, |
9330 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Ev }, 0 }, | |
c0f3af97 L |
9331 | }, |
9332 | ||
592a252b | 9333 | /* VEX_LEN_0F2C_P_1 */ |
c0f3af97 | 9334 | { |
9646c87b JB |
9335 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, |
9336 | { "vcvttss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9337 | }, |
9338 | ||
592a252b | 9339 | /* VEX_LEN_0F2C_P_3 */ |
c0f3af97 | 9340 | { |
9646c87b JB |
9341 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, |
9342 | { "vcvttsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9343 | }, |
9344 | ||
592a252b | 9345 | /* VEX_LEN_0F2D_P_1 */ |
c0f3af97 | 9346 | { |
9646c87b JB |
9347 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, |
9348 | { "vcvtss2si", { Gv, EXdScalar }, 0 }, | |
c0f3af97 L |
9349 | }, |
9350 | ||
592a252b | 9351 | /* VEX_LEN_0F2D_P_3 */ |
c0f3af97 | 9352 | { |
9646c87b JB |
9353 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, |
9354 | { "vcvtsd2si", { Gv, EXqScalar }, 0 }, | |
c0f3af97 L |
9355 | }, |
9356 | ||
43234a1e L |
9357 | /* VEX_LEN_0F41_P_0 */ |
9358 | { | |
9359 | { Bad_Opcode }, | |
9360 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9361 | }, | |
1ba585e8 IT |
9362 | /* VEX_LEN_0F41_P_2 */ |
9363 | { | |
9364 | { Bad_Opcode }, | |
9365 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9366 | }, | |
43234a1e L |
9367 | /* VEX_LEN_0F42_P_0 */ |
9368 | { | |
9369 | { Bad_Opcode }, | |
9370 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9371 | }, | |
1ba585e8 IT |
9372 | /* VEX_LEN_0F42_P_2 */ |
9373 | { | |
9374 | { Bad_Opcode }, | |
9375 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9376 | }, | |
43234a1e L |
9377 | /* VEX_LEN_0F44_P_0 */ |
9378 | { | |
9379 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9380 | }, | |
1ba585e8 IT |
9381 | /* VEX_LEN_0F44_P_2 */ |
9382 | { | |
9383 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9384 | }, | |
43234a1e L |
9385 | /* VEX_LEN_0F45_P_0 */ |
9386 | { | |
9387 | { Bad_Opcode }, | |
9388 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9389 | }, | |
1ba585e8 IT |
9390 | /* VEX_LEN_0F45_P_2 */ |
9391 | { | |
9392 | { Bad_Opcode }, | |
9393 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9394 | }, | |
43234a1e L |
9395 | /* VEX_LEN_0F46_P_0 */ |
9396 | { | |
9397 | { Bad_Opcode }, | |
9398 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9399 | }, | |
1ba585e8 IT |
9400 | /* VEX_LEN_0F46_P_2 */ |
9401 | { | |
9402 | { Bad_Opcode }, | |
9403 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9404 | }, | |
43234a1e L |
9405 | /* VEX_LEN_0F47_P_0 */ |
9406 | { | |
9407 | { Bad_Opcode }, | |
9408 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9409 | }, | |
1ba585e8 IT |
9410 | /* VEX_LEN_0F47_P_2 */ |
9411 | { | |
9412 | { Bad_Opcode }, | |
9413 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9414 | }, | |
9415 | /* VEX_LEN_0F4A_P_0 */ | |
9416 | { | |
9417 | { Bad_Opcode }, | |
9418 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9419 | }, | |
9420 | /* VEX_LEN_0F4A_P_2 */ | |
9421 | { | |
9422 | { Bad_Opcode }, | |
9423 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9424 | }, | |
9425 | /* VEX_LEN_0F4B_P_0 */ | |
9426 | { | |
9427 | { Bad_Opcode }, | |
9428 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9429 | }, | |
43234a1e L |
9430 | /* VEX_LEN_0F4B_P_2 */ |
9431 | { | |
9432 | { Bad_Opcode }, | |
9433 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9434 | }, | |
9435 | ||
ec6f095a | 9436 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9437 | { |
ec6f095a | 9438 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9439 | }, |
9440 | ||
ec6f095a | 9441 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9442 | { |
ec6f095a L |
9443 | { "vzeroupper", { XX }, 0 }, |
9444 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9445 | }, |
9446 | ||
ec6f095a | 9447 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9448 | { |
ec6f095a | 9449 | { "vmovq", { XMScalar, EXqScalar }, 0 }, |
c0f3af97 L |
9450 | }, |
9451 | ||
ec6f095a | 9452 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9453 | { |
ec6f095a | 9454 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9455 | }, |
9456 | ||
ec6f095a | 9457 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9458 | { |
ec6f095a | 9459 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9460 | }, |
9461 | ||
ec6f095a | 9462 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9463 | { |
ec6f095a | 9464 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9465 | }, |
9466 | ||
ec6f095a | 9467 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9468 | { |
ec6f095a | 9469 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9470 | }, |
9471 | ||
ec6f095a | 9472 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9473 | { |
ec6f095a | 9474 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9475 | }, |
9476 | ||
ec6f095a | 9477 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9478 | { |
ec6f095a | 9479 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9480 | }, |
9481 | ||
ec6f095a | 9482 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9483 | { |
ec6f095a | 9484 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9485 | }, |
9486 | ||
ec6f095a | 9487 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9488 | { |
58a211d2 | 9489 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9490 | }, |
9491 | ||
ec6f095a | 9492 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9493 | { |
ec6f095a | 9494 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9495 | }, |
9496 | ||
ec6f095a | 9497 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9498 | { |
ec6f095a | 9499 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9500 | }, |
9501 | ||
ec6f095a | 9502 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9503 | { |
58a211d2 | 9504 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9505 | }, |
9506 | ||
ec6f095a | 9507 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9508 | { |
9509 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9510 | }, | |
9511 | ||
1ba585e8 IT |
9512 | /* VEX_LEN_0F98_P_2 */ |
9513 | { | |
9514 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9515 | }, | |
9516 | ||
9517 | /* VEX_LEN_0F99_P_0 */ | |
9518 | { | |
9519 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9520 | }, | |
9521 | ||
9522 | /* VEX_LEN_0F99_P_2 */ | |
9523 | { | |
9524 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9525 | }, | |
9526 | ||
6c30d220 | 9527 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9528 | { |
ec6f095a | 9529 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9530 | }, |
9531 | ||
6c30d220 | 9532 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9533 | { |
ec6f095a | 9534 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9535 | }, |
9536 | ||
6c30d220 | 9537 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9538 | { |
b50c9f31 | 9539 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9540 | }, |
9541 | ||
6c30d220 | 9542 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9543 | { |
b50c9f31 | 9544 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9545 | }, |
9546 | ||
6c30d220 | 9547 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9548 | { |
ec6f095a | 9549 | { "vmovq", { EXqScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9550 | }, |
9551 | ||
6c30d220 | 9552 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9553 | { |
ec6f095a | 9554 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9555 | }, |
9556 | ||
6c30d220 | 9557 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9558 | { |
6c30d220 L |
9559 | { Bad_Opcode }, |
9560 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9561 | }, |
9562 | ||
6c30d220 | 9563 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9564 | { |
6c30d220 L |
9565 | { Bad_Opcode }, |
9566 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9567 | }, |
9568 | ||
6c30d220 | 9569 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9570 | { |
6c30d220 L |
9571 | { Bad_Opcode }, |
9572 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9573 | }, |
9574 | ||
6c30d220 | 9575 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9576 | { |
6c30d220 L |
9577 | { Bad_Opcode }, |
9578 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9579 | }, |
9580 | ||
592a252b | 9581 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9582 | { |
ec6f095a | 9583 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9584 | }, |
9585 | ||
6c30d220 L |
9586 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9587 | { | |
9588 | { Bad_Opcode }, | |
9589 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9590 | }, | |
9591 | ||
592a252b | 9592 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9593 | { |
ec6f095a | 9594 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9595 | }, |
9596 | ||
f12dc422 L |
9597 | /* VEX_LEN_0F38F2_P_0 */ |
9598 | { | |
bf890a93 | 9599 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9600 | }, |
9601 | ||
9602 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9603 | { | |
bf890a93 | 9604 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9605 | }, |
9606 | ||
9607 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9608 | { | |
bf890a93 | 9609 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9610 | }, |
9611 | ||
9612 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9613 | { | |
bf890a93 | 9614 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9615 | }, |
9616 | ||
6c30d220 L |
9617 | /* VEX_LEN_0F38F5_P_0 */ |
9618 | { | |
bf890a93 | 9619 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9620 | }, |
9621 | ||
9622 | /* VEX_LEN_0F38F5_P_1 */ | |
9623 | { | |
bf890a93 | 9624 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9625 | }, |
9626 | ||
9627 | /* VEX_LEN_0F38F5_P_3 */ | |
9628 | { | |
bf890a93 | 9629 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9630 | }, |
9631 | ||
9632 | /* VEX_LEN_0F38F6_P_3 */ | |
9633 | { | |
bf890a93 | 9634 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9635 | }, |
9636 | ||
f12dc422 L |
9637 | /* VEX_LEN_0F38F7_P_0 */ |
9638 | { | |
bf890a93 | 9639 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9640 | }, |
9641 | ||
6c30d220 L |
9642 | /* VEX_LEN_0F38F7_P_1 */ |
9643 | { | |
bf890a93 | 9644 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9645 | }, |
9646 | ||
9647 | /* VEX_LEN_0F38F7_P_2 */ | |
9648 | { | |
bf890a93 | 9649 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9650 | }, |
9651 | ||
9652 | /* VEX_LEN_0F38F7_P_3 */ | |
9653 | { | |
bf890a93 | 9654 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9655 | }, |
9656 | ||
9657 | /* VEX_LEN_0F3A00_P_2 */ | |
9658 | { | |
9659 | { Bad_Opcode }, | |
9660 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9661 | }, | |
9662 | ||
9663 | /* VEX_LEN_0F3A01_P_2 */ | |
9664 | { | |
9665 | { Bad_Opcode }, | |
9666 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9667 | }, | |
9668 | ||
592a252b | 9669 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9670 | { |
592d1631 | 9671 | { Bad_Opcode }, |
592a252b | 9672 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9673 | }, |
9674 | ||
592a252b | 9675 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9676 | { |
b50c9f31 | 9677 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9678 | }, |
9679 | ||
592a252b | 9680 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9681 | { |
b50c9f31 | 9682 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9683 | }, |
9684 | ||
592a252b | 9685 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9686 | { |
bf890a93 | 9687 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9688 | }, |
9689 | ||
592a252b | 9690 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9691 | { |
bf890a93 | 9692 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9693 | }, |
9694 | ||
592a252b | 9695 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9696 | { |
592d1631 | 9697 | { Bad_Opcode }, |
592a252b | 9698 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9699 | }, |
9700 | ||
592a252b | 9701 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9702 | { |
592d1631 | 9703 | { Bad_Opcode }, |
592a252b | 9704 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9705 | }, |
9706 | ||
592a252b | 9707 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9708 | { |
b50c9f31 | 9709 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9710 | }, |
9711 | ||
592a252b | 9712 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9713 | { |
ec6f095a | 9714 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9715 | }, |
9716 | ||
592a252b | 9717 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9718 | { |
bf890a93 | 9719 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9720 | }, |
9721 | ||
43234a1e L |
9722 | /* VEX_LEN_0F3A30_P_2 */ |
9723 | { | |
9724 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9725 | }, | |
9726 | ||
1ba585e8 IT |
9727 | /* VEX_LEN_0F3A31_P_2 */ |
9728 | { | |
9729 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9730 | }, | |
9731 | ||
43234a1e L |
9732 | /* VEX_LEN_0F3A32_P_2 */ |
9733 | { | |
9734 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9735 | }, | |
9736 | ||
1ba585e8 IT |
9737 | /* VEX_LEN_0F3A33_P_2 */ |
9738 | { | |
9739 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9740 | }, | |
9741 | ||
6c30d220 | 9742 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9743 | { |
6c30d220 L |
9744 | { Bad_Opcode }, |
9745 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9746 | }, |
9747 | ||
6c30d220 | 9748 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9749 | { |
6c30d220 L |
9750 | { Bad_Opcode }, |
9751 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9752 | }, | |
9753 | ||
9754 | /* VEX_LEN_0F3A41_P_2 */ | |
9755 | { | |
ec6f095a | 9756 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9757 | }, |
9758 | ||
6c30d220 | 9759 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9760 | { |
6c30d220 L |
9761 | { Bad_Opcode }, |
9762 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9763 | }, |
9764 | ||
592a252b | 9765 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9766 | { |
15c7c1d8 | 9767 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9768 | }, |
9769 | ||
592a252b | 9770 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9771 | { |
15c7c1d8 | 9772 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9773 | }, |
9774 | ||
592a252b | 9775 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9776 | { |
ec6f095a | 9777 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9778 | }, |
9779 | ||
592a252b | 9780 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9781 | { |
ec6f095a | 9782 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9783 | }, |
9784 | ||
592a252b | 9785 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9786 | { |
3a2430e0 | 9787 | { "vfmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9788 | }, |
9789 | ||
592a252b | 9790 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9791 | { |
3a2430e0 | 9792 | { "vfmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9793 | }, |
9794 | ||
592a252b | 9795 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9796 | { |
3a2430e0 | 9797 | { "vfmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9798 | }, |
9799 | ||
592a252b | 9800 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9801 | { |
3a2430e0 | 9802 | { "vfmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9803 | }, |
9804 | ||
592a252b | 9805 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9806 | { |
3a2430e0 | 9807 | { "vfnmaddss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9808 | }, |
9809 | ||
592a252b | 9810 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9811 | { |
3a2430e0 | 9812 | { "vfnmaddsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9813 | }, |
9814 | ||
592a252b | 9815 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9816 | { |
3a2430e0 | 9817 | { "vfnmsubss", { XMVexW, Vex128, EXdVexW, EXdVexW }, 0 }, |
922d8de8 DR |
9818 | }, |
9819 | ||
592a252b | 9820 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9821 | { |
3a2430e0 | 9822 | { "vfnmsubsd", { XMVexW, Vex128, EXqVexW, EXqVexW }, 0 }, |
922d8de8 DR |
9823 | }, |
9824 | ||
592a252b | 9825 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9826 | { |
ec6f095a | 9827 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9828 | }, |
4c807e72 | 9829 | |
6c30d220 L |
9830 | /* VEX_LEN_0F3AF0_P_3 */ |
9831 | { | |
bf890a93 | 9832 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9833 | }, |
9834 | ||
ff688e1f L |
9835 | /* VEX_LEN_0FXOP_08_CC */ |
9836 | { | |
be92cb14 | 9837 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9838 | }, |
9839 | ||
9840 | /* VEX_LEN_0FXOP_08_CD */ | |
9841 | { | |
be92cb14 | 9842 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9843 | }, |
9844 | ||
9845 | /* VEX_LEN_0FXOP_08_CE */ | |
9846 | { | |
be92cb14 | 9847 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9848 | }, |
9849 | ||
9850 | /* VEX_LEN_0FXOP_08_CF */ | |
9851 | { | |
be92cb14 | 9852 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9853 | }, |
9854 | ||
9855 | /* VEX_LEN_0FXOP_08_EC */ | |
9856 | { | |
be92cb14 | 9857 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9858 | }, |
9859 | ||
9860 | /* VEX_LEN_0FXOP_08_ED */ | |
9861 | { | |
be92cb14 | 9862 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9863 | }, |
9864 | ||
9865 | /* VEX_LEN_0FXOP_08_EE */ | |
9866 | { | |
be92cb14 | 9867 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9868 | }, |
9869 | ||
9870 | /* VEX_LEN_0FXOP_08_EF */ | |
9871 | { | |
be92cb14 | 9872 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9873 | }, |
9874 | ||
592a252b | 9875 | /* VEX_LEN_0FXOP_09_80 */ |
5dd85c99 | 9876 | { |
bf890a93 IT |
9877 | { "vfrczps", { XM, EXxmm }, 0 }, |
9878 | { "vfrczps", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9879 | }, |
4c807e72 | 9880 | |
592a252b | 9881 | /* VEX_LEN_0FXOP_09_81 */ |
5dd85c99 | 9882 | { |
bf890a93 IT |
9883 | { "vfrczpd", { XM, EXxmm }, 0 }, |
9884 | { "vfrczpd", { XM, EXymmq }, 0 }, | |
5dd85c99 | 9885 | }, |
331d2d0d L |
9886 | }; |
9887 | ||
04e2a182 L |
9888 | static const struct dis386 evex_len_table[][3] = { |
9889 | #define NEED_EVEX_LEN_TABLE | |
9890 | #include "i386-dis-evex.h" | |
9891 | #undef NEED_EVEX_LEN_TABLE | |
9892 | }; | |
9893 | ||
9e30b8e0 | 9894 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9895 | { |
9896 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9897 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9898 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9899 | }, |
9900 | { | |
9901 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9902 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9903 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9904 | }, |
9905 | { | |
9906 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9907 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9908 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9909 | }, |
9910 | { | |
9911 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9912 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9913 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9914 | }, |
9915 | { | |
9916 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9917 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9918 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9919 | }, |
9920 | { | |
9921 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9922 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9923 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9924 | }, |
9925 | { | |
ec6f095a L |
9926 | /* VEX_W_0F45_P_0_LEN_1 */ |
9927 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9928 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9929 | }, |
9930 | { | |
ec6f095a L |
9931 | /* VEX_W_0F45_P_2_LEN_1 */ |
9932 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9933 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9934 | }, |
9935 | { | |
ec6f095a L |
9936 | /* VEX_W_0F46_P_0_LEN_1 */ |
9937 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9938 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9939 | }, |
9940 | { | |
ec6f095a L |
9941 | /* VEX_W_0F46_P_2_LEN_1 */ |
9942 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9943 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9944 | }, |
9945 | { | |
ec6f095a L |
9946 | /* VEX_W_0F47_P_0_LEN_1 */ |
9947 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9948 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9949 | }, |
9950 | { | |
ec6f095a L |
9951 | /* VEX_W_0F47_P_2_LEN_1 */ |
9952 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9953 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9954 | }, |
9955 | { | |
ec6f095a L |
9956 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9957 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9958 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9959 | }, |
9960 | { | |
ec6f095a L |
9961 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9962 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9963 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9964 | }, |
9965 | { | |
ec6f095a L |
9966 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9967 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9968 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9969 | }, |
9970 | { | |
ec6f095a L |
9971 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9972 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9973 | }, |
9974 | { | |
ec6f095a L |
9975 | /* VEX_W_0F90_P_0_LEN_0 */ |
9976 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9977 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9978 | }, |
9979 | { | |
ec6f095a L |
9980 | /* VEX_W_0F90_P_2_LEN_0 */ |
9981 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9982 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9983 | }, |
9984 | { | |
ec6f095a L |
9985 | /* VEX_W_0F91_P_0_LEN_0 */ |
9986 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9987 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9988 | }, |
9989 | { | |
ec6f095a L |
9990 | /* VEX_W_0F91_P_2_LEN_0 */ |
9991 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9992 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9993 | }, |
9994 | { | |
ec6f095a L |
9995 | /* VEX_W_0F92_P_0_LEN_0 */ |
9996 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9997 | }, |
9998 | { | |
ec6f095a L |
9999 | /* VEX_W_0F92_P_2_LEN_0 */ |
10000 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 10001 | }, |
9e30b8e0 | 10002 | { |
ec6f095a L |
10003 | /* VEX_W_0F93_P_0_LEN_0 */ |
10004 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
10005 | }, |
10006 | { | |
ec6f095a L |
10007 | /* VEX_W_0F93_P_2_LEN_0 */ |
10008 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 10009 | }, |
9e30b8e0 | 10010 | { |
ec6f095a L |
10011 | /* VEX_W_0F98_P_0_LEN_0 */ |
10012 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
10013 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
10014 | }, |
10015 | { | |
ec6f095a L |
10016 | /* VEX_W_0F98_P_2_LEN_0 */ |
10017 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
10018 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
10019 | }, |
10020 | { | |
ec6f095a L |
10021 | /* VEX_W_0F99_P_0_LEN_0 */ |
10022 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
10023 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
10024 | }, |
10025 | { | |
ec6f095a L |
10026 | /* VEX_W_0F99_P_2_LEN_0 */ |
10027 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
10028 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 10029 | }, |
9e30b8e0 | 10030 | { |
592a252b | 10031 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 10032 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10033 | }, |
10034 | { | |
592a252b | 10035 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 10036 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
10037 | }, |
10038 | { | |
592a252b | 10039 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 10040 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
10041 | }, |
10042 | { | |
592a252b | 10043 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 10044 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 10045 | }, |
6c30d220 L |
10046 | { |
10047 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 10048 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 10049 | }, |
bcf2684f | 10050 | { |
6c30d220 | 10051 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 10052 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 10053 | }, |
9e30b8e0 | 10054 | { |
6c30d220 | 10055 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 10056 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
10057 | }, |
10058 | { | |
592a252b | 10059 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 10060 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 10061 | }, |
53aa04a0 | 10062 | { |
592a252b | 10063 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 10064 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10065 | }, |
10066 | { | |
592a252b | 10067 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 10068 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
10069 | }, |
10070 | { | |
592a252b | 10071 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 10072 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
10073 | }, |
10074 | { | |
592a252b | 10075 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 10076 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 10077 | }, |
6c30d220 L |
10078 | { |
10079 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 10080 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 10081 | }, |
6c30d220 L |
10082 | { |
10083 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 10084 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
10085 | }, |
10086 | { | |
10087 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 10088 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
10089 | }, |
10090 | { | |
10091 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 10092 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
10093 | }, |
10094 | { | |
10095 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 10096 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
10097 | }, |
10098 | { | |
10099 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 10100 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
10101 | }, |
10102 | { | |
10103 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 10104 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 10105 | }, |
48521003 IT |
10106 | { |
10107 | /* VEX_W_0F38CF_P_2 */ | |
10108 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
10109 | }, | |
6c30d220 L |
10110 | { |
10111 | /* VEX_W_0F3A00_P_2 */ | |
10112 | { Bad_Opcode }, | |
bf890a93 | 10113 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10114 | }, |
10115 | { | |
10116 | /* VEX_W_0F3A01_P_2 */ | |
10117 | { Bad_Opcode }, | |
bf890a93 | 10118 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
10119 | }, |
10120 | { | |
10121 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 10122 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 10123 | }, |
9e30b8e0 | 10124 | { |
592a252b | 10125 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 10126 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10127 | }, |
10128 | { | |
592a252b | 10129 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 10130 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
10131 | }, |
10132 | { | |
592a252b | 10133 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 10134 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 10135 | }, |
9e30b8e0 | 10136 | { |
592a252b | 10137 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 10138 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
10139 | }, |
10140 | { | |
592a252b | 10141 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 10142 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 10143 | }, |
43234a1e | 10144 | { |
1ba585e8 | 10145 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
10146 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
10147 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
10148 | }, |
10149 | { | |
1ba585e8 | 10150 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
10151 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
10152 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10153 | }, |
10154 | { | |
10155 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10156 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10157 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10158 | }, |
1ba585e8 IT |
10159 | { |
10160 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10161 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10162 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10163 | }, |
6c30d220 L |
10164 | { |
10165 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10166 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10167 | }, |
10168 | { | |
10169 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10170 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10171 | }, |
6c30d220 L |
10172 | { |
10173 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10174 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10175 | }, |
a683cc34 | 10176 | { |
592a252b | 10177 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10178 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10179 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10180 | }, |
10181 | { | |
592a252b | 10182 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10183 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10184 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10185 | }, |
9e30b8e0 | 10186 | { |
592a252b | 10187 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10188 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10189 | }, |
10190 | { | |
592a252b | 10191 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10192 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10193 | }, |
10194 | { | |
592a252b | 10195 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10196 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10197 | }, |
48521003 IT |
10198 | { |
10199 | /* VEX_W_0F3ACE_P_2 */ | |
10200 | { Bad_Opcode }, | |
10201 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10202 | }, | |
10203 | { | |
10204 | /* VEX_W_0F3ACF_P_2 */ | |
10205 | { Bad_Opcode }, | |
10206 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10207 | }, | |
43234a1e L |
10208 | #define NEED_VEX_W_TABLE |
10209 | #include "i386-dis-evex.h" | |
10210 | #undef NEED_VEX_W_TABLE | |
9e30b8e0 L |
10211 | }; |
10212 | ||
10213 | static const struct dis386 mod_table[][2] = { | |
10214 | { | |
10215 | /* MOD_8D */ | |
bf890a93 | 10216 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10217 | }, |
42164a71 L |
10218 | { |
10219 | /* MOD_C6_REG_7 */ | |
10220 | { Bad_Opcode }, | |
10221 | { RM_TABLE (RM_C6_REG_7) }, | |
10222 | }, | |
10223 | { | |
10224 | /* MOD_C7_REG_7 */ | |
10225 | { Bad_Opcode }, | |
10226 | { RM_TABLE (RM_C7_REG_7) }, | |
10227 | }, | |
4a357820 MZ |
10228 | { |
10229 | /* MOD_FF_REG_3 */ | |
a72d2af2 | 10230 | { "Jcall^", { indirEp }, 0 }, |
4a357820 MZ |
10231 | }, |
10232 | { | |
10233 | /* MOD_FF_REG_5 */ | |
a72d2af2 | 10234 | { "Jjmp^", { indirEp }, 0 }, |
4a357820 | 10235 | }, |
9e30b8e0 L |
10236 | { |
10237 | /* MOD_0F01_REG_0 */ | |
10238 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10239 | { RM_TABLE (RM_0F01_REG_0) }, | |
10240 | }, | |
10241 | { | |
10242 | /* MOD_0F01_REG_1 */ | |
10243 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10244 | { RM_TABLE (RM_0F01_REG_1) }, | |
10245 | }, | |
10246 | { | |
10247 | /* MOD_0F01_REG_2 */ | |
10248 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10249 | { RM_TABLE (RM_0F01_REG_2) }, | |
10250 | }, | |
10251 | { | |
10252 | /* MOD_0F01_REG_3 */ | |
10253 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10254 | { RM_TABLE (RM_0F01_REG_3) }, | |
10255 | }, | |
8eab4136 L |
10256 | { |
10257 | /* MOD_0F01_REG_5 */ | |
603555e5 | 10258 | { PREFIX_TABLE (PREFIX_MOD_0_0F01_REG_5) }, |
8eab4136 L |
10259 | { RM_TABLE (RM_0F01_REG_5) }, |
10260 | }, | |
9e30b8e0 L |
10261 | { |
10262 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10263 | { "invlpg", { Mb }, 0 }, |
9e30b8e0 L |
10264 | { RM_TABLE (RM_0F01_REG_7) }, |
10265 | }, | |
10266 | { | |
10267 | /* MOD_0F12_PREFIX_0 */ | |
507bd325 L |
10268 | { "movlps", { XM, EXq }, PREFIX_OPCODE }, |
10269 | { "movhlps", { XM, EXq }, PREFIX_OPCODE }, | |
9e30b8e0 L |
10270 | }, |
10271 | { | |
10272 | /* MOD_0F13 */ | |
507bd325 | 10273 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10274 | }, |
10275 | { | |
10276 | /* MOD_0F16_PREFIX_0 */ | |
bf890a93 IT |
10277 | { "movhps", { XM, EXq }, 0 }, |
10278 | { "movlhps", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10279 | }, |
10280 | { | |
10281 | /* MOD_0F17 */ | |
507bd325 | 10282 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10283 | }, |
10284 | { | |
10285 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10286 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10287 | }, |
10288 | { | |
10289 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10290 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10291 | }, |
10292 | { | |
10293 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10294 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10295 | }, |
10296 | { | |
10297 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10298 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10299 | }, |
d7189fa5 RM |
10300 | { |
10301 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10302 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10303 | }, |
10304 | { | |
10305 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10306 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10307 | }, |
10308 | { | |
10309 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10310 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10311 | }, |
10312 | { | |
10313 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10314 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10315 | }, |
7e8b059b L |
10316 | { |
10317 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10318 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10319 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10320 | }, |
10321 | { | |
10322 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10323 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10324 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10325 | }, |
10326 | { | |
10327 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10328 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10329 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10330 | }, |
c48935d7 IT |
10331 | { |
10332 | /* MOD_0F1C_PREFIX_0 */ | |
10333 | { REG_TABLE (REG_0F1C_MOD_0) }, | |
10334 | { "nopQ", { Ev }, 0 }, | |
10335 | }, | |
603555e5 L |
10336 | { |
10337 | /* MOD_0F1E_PREFIX_1 */ | |
10338 | { "nopQ", { Ev }, 0 }, | |
10339 | { REG_TABLE (REG_0F1E_MOD_3) }, | |
10340 | }, | |
b844680a | 10341 | { |
92fddf8e | 10342 | /* MOD_0F24 */ |
7bb15c6f | 10343 | { Bad_Opcode }, |
bf890a93 | 10344 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10345 | }, |
10346 | { | |
92fddf8e | 10347 | /* MOD_0F26 */ |
592d1631 | 10348 | { Bad_Opcode }, |
bf890a93 | 10349 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10350 | }, |
75c135a8 L |
10351 | { |
10352 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10353 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10354 | }, |
10355 | { | |
10356 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10357 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10358 | }, |
10359 | { | |
10360 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10361 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10362 | }, |
10363 | { | |
10364 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10365 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10366 | }, |
10367 | { | |
10368 | /* MOD_0F51 */ | |
592d1631 | 10369 | { Bad_Opcode }, |
507bd325 | 10370 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10371 | }, |
b844680a | 10372 | { |
1ceb70f8 | 10373 | /* MOD_0F71_REG_2 */ |
592d1631 | 10374 | { Bad_Opcode }, |
bf890a93 | 10375 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10376 | }, |
10377 | { | |
1ceb70f8 | 10378 | /* MOD_0F71_REG_4 */ |
592d1631 | 10379 | { Bad_Opcode }, |
bf890a93 | 10380 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10381 | }, |
10382 | { | |
1ceb70f8 | 10383 | /* MOD_0F71_REG_6 */ |
592d1631 | 10384 | { Bad_Opcode }, |
bf890a93 | 10385 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10386 | }, |
10387 | { | |
1ceb70f8 | 10388 | /* MOD_0F72_REG_2 */ |
592d1631 | 10389 | { Bad_Opcode }, |
bf890a93 | 10390 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10391 | }, |
10392 | { | |
1ceb70f8 | 10393 | /* MOD_0F72_REG_4 */ |
592d1631 | 10394 | { Bad_Opcode }, |
bf890a93 | 10395 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10396 | }, |
10397 | { | |
1ceb70f8 | 10398 | /* MOD_0F72_REG_6 */ |
592d1631 | 10399 | { Bad_Opcode }, |
bf890a93 | 10400 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10401 | }, |
10402 | { | |
1ceb70f8 | 10403 | /* MOD_0F73_REG_2 */ |
592d1631 | 10404 | { Bad_Opcode }, |
bf890a93 | 10405 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10406 | }, |
10407 | { | |
1ceb70f8 | 10408 | /* MOD_0F73_REG_3 */ |
592d1631 | 10409 | { Bad_Opcode }, |
c0f3af97 L |
10410 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10411 | }, | |
10412 | { | |
10413 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10414 | { Bad_Opcode }, |
bf890a93 | 10415 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10416 | }, |
10417 | { | |
10418 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10419 | { Bad_Opcode }, |
c0f3af97 L |
10420 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10421 | }, | |
10422 | { | |
10423 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10424 | { "fxsave", { FXSAVE }, 0 }, |
c7b8aa3a | 10425 | { PREFIX_TABLE (PREFIX_0FAE_REG_0) }, |
c0f3af97 L |
10426 | }, |
10427 | { | |
10428 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10429 | { "fxrstor", { FXSAVE }, 0 }, |
c7b8aa3a | 10430 | { PREFIX_TABLE (PREFIX_0FAE_REG_1) }, |
c0f3af97 L |
10431 | }, |
10432 | { | |
10433 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10434 | { "ldmxcsr", { Md }, 0 }, |
c7b8aa3a | 10435 | { PREFIX_TABLE (PREFIX_0FAE_REG_2) }, |
c0f3af97 L |
10436 | }, |
10437 | { | |
10438 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10439 | { "stmxcsr", { Md }, 0 }, |
c7b8aa3a | 10440 | { PREFIX_TABLE (PREFIX_0FAE_REG_3) }, |
c0f3af97 L |
10441 | }, |
10442 | { | |
10443 | /* MOD_0FAE_REG_4 */ | |
6b40c462 L |
10444 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_4) }, |
10445 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_4) }, | |
c0f3af97 L |
10446 | }, |
10447 | { | |
10448 | /* MOD_0FAE_REG_5 */ | |
603555e5 | 10449 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_5) }, |
2234eee6 | 10450 | { PREFIX_TABLE (PREFIX_MOD_3_0FAE_REG_5) }, |
c0f3af97 L |
10451 | }, |
10452 | { | |
10453 | /* MOD_0FAE_REG_6 */ | |
de89d0a3 IT |
10454 | { PREFIX_TABLE (PREFIX_MOD_0_0FAE_REG_6) }, |
10455 | { PREFIX_TABLE (PREFIX_MOD_1_0FAE_REG_6) }, | |
c0f3af97 L |
10456 | }, |
10457 | { | |
10458 | /* MOD_0FAE_REG_7 */ | |
963f3586 | 10459 | { PREFIX_TABLE (PREFIX_0FAE_REG_7) }, |
c0f3af97 L |
10460 | { RM_TABLE (RM_0FAE_REG_7) }, |
10461 | }, | |
10462 | { | |
10463 | /* MOD_0FB2 */ | |
bf890a93 | 10464 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10465 | }, |
10466 | { | |
10467 | /* MOD_0FB4 */ | |
bf890a93 | 10468 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10469 | }, |
10470 | { | |
10471 | /* MOD_0FB5 */ | |
bf890a93 | 10472 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10473 | }, |
a8484f96 L |
10474 | { |
10475 | /* MOD_0FC3 */ | |
10476 | { PREFIX_TABLE (PREFIX_MOD_0_0FC3) }, | |
10477 | }, | |
963f3586 IT |
10478 | { |
10479 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10480 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10481 | }, |
10482 | { | |
10483 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10484 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10485 | }, |
10486 | { | |
10487 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10488 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10489 | }, |
c0f3af97 L |
10490 | { |
10491 | /* MOD_0FC7_REG_6 */ | |
f24bcbaa L |
10492 | { PREFIX_TABLE (PREFIX_MOD_0_0FC7_REG_6) }, |
10493 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_6) } | |
c0f3af97 L |
10494 | }, |
10495 | { | |
10496 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10497 | { "vmptrst", { Mq }, 0 }, |
f24bcbaa | 10498 | { PREFIX_TABLE (PREFIX_MOD_3_0FC7_REG_7) } |
c0f3af97 L |
10499 | }, |
10500 | { | |
10501 | /* MOD_0FD7 */ | |
592d1631 | 10502 | { Bad_Opcode }, |
bf890a93 | 10503 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10504 | }, |
10505 | { | |
10506 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10507 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10508 | }, |
10509 | { | |
10510 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10511 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10512 | }, |
10513 | { | |
10514 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10515 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10516 | }, |
603555e5 L |
10517 | { |
10518 | /* MOD_0F38F5_PREFIX_2 */ | |
10519 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10520 | }, | |
10521 | { | |
10522 | /* MOD_0F38F6_PREFIX_0 */ | |
10523 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10524 | }, | |
5d79adc4 L |
10525 | { |
10526 | /* MOD_0F38F8_PREFIX_1 */ | |
10527 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10528 | }, | |
c0a30a9f L |
10529 | { |
10530 | /* MOD_0F38F8_PREFIX_2 */ | |
10531 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10532 | }, | |
5d79adc4 L |
10533 | { |
10534 | /* MOD_0F38F8_PREFIX_3 */ | |
10535 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10536 | }, | |
c0a30a9f L |
10537 | { |
10538 | /* MOD_0F38F9_PREFIX_0 */ | |
10539 | { "movdiri", { Em, Gv }, PREFIX_OPCODE }, | |
10540 | }, | |
c0f3af97 L |
10541 | { |
10542 | /* MOD_62_32BIT */ | |
bf890a93 | 10543 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10544 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10545 | }, |
10546 | { | |
10547 | /* MOD_C4_32BIT */ | |
bf890a93 | 10548 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10549 | { VEX_C4_TABLE (VEX_0F) }, |
10550 | }, | |
10551 | { | |
10552 | /* MOD_C5_32BIT */ | |
bf890a93 | 10553 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10554 | { VEX_C5_TABLE (VEX_0F) }, |
10555 | }, | |
10556 | { | |
592a252b L |
10557 | /* MOD_VEX_0F12_PREFIX_0 */ |
10558 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10559 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 L |
10560 | }, |
10561 | { | |
592a252b L |
10562 | /* MOD_VEX_0F13 */ |
10563 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10564 | }, |
10565 | { | |
592a252b L |
10566 | /* MOD_VEX_0F16_PREFIX_0 */ |
10567 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10568 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 L |
10569 | }, |
10570 | { | |
592a252b L |
10571 | /* MOD_VEX_0F17 */ |
10572 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10573 | }, |
10574 | { | |
592a252b | 10575 | /* MOD_VEX_0F2B */ |
ec6f095a | 10576 | { "vmovntpX", { Mx, XM }, 0 }, |
c0f3af97 | 10577 | }, |
ab4e4ed5 AF |
10578 | { |
10579 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10580 | { Bad_Opcode }, | |
10581 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10582 | }, | |
10583 | { | |
10584 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10585 | { Bad_Opcode }, | |
10586 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10587 | }, | |
10588 | { | |
10589 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10590 | { Bad_Opcode }, | |
10591 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10592 | }, | |
10593 | { | |
10594 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10595 | { Bad_Opcode }, | |
10596 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10597 | }, | |
10598 | { | |
10599 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10600 | { Bad_Opcode }, | |
10601 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10602 | }, | |
10603 | { | |
10604 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10605 | { Bad_Opcode }, | |
10606 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10607 | }, | |
10608 | { | |
10609 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10610 | { Bad_Opcode }, | |
10611 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10612 | }, | |
10613 | { | |
10614 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10615 | { Bad_Opcode }, | |
10616 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10617 | }, | |
10618 | { | |
10619 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10620 | { Bad_Opcode }, | |
10621 | { "knotw", { MaskG, MaskR }, 0 }, | |
10622 | }, | |
10623 | { | |
10624 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10625 | { Bad_Opcode }, | |
10626 | { "knotq", { MaskG, MaskR }, 0 }, | |
10627 | }, | |
10628 | { | |
10629 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10630 | { Bad_Opcode }, | |
10631 | { "knotb", { MaskG, MaskR }, 0 }, | |
10632 | }, | |
10633 | { | |
10634 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10635 | { Bad_Opcode }, | |
10636 | { "knotd", { MaskG, MaskR }, 0 }, | |
10637 | }, | |
10638 | { | |
10639 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10640 | { Bad_Opcode }, | |
10641 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10642 | }, | |
10643 | { | |
10644 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10645 | { Bad_Opcode }, | |
10646 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10647 | }, | |
10648 | { | |
10649 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10650 | { Bad_Opcode }, | |
10651 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10652 | }, | |
10653 | { | |
10654 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10655 | { Bad_Opcode }, | |
10656 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10657 | }, | |
10658 | { | |
10659 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10660 | { Bad_Opcode }, | |
10661 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10662 | }, | |
10663 | { | |
10664 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10665 | { Bad_Opcode }, | |
10666 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10667 | }, | |
10668 | { | |
10669 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10670 | { Bad_Opcode }, | |
10671 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10672 | }, | |
10673 | { | |
10674 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10675 | { Bad_Opcode }, | |
10676 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10677 | }, | |
10678 | { | |
10679 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10680 | { Bad_Opcode }, | |
10681 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10682 | }, | |
10683 | { | |
10684 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10685 | { Bad_Opcode }, | |
10686 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10687 | }, | |
10688 | { | |
10689 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10690 | { Bad_Opcode }, | |
10691 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10692 | }, | |
10693 | { | |
10694 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10695 | { Bad_Opcode }, | |
10696 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10697 | }, | |
10698 | { | |
10699 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10700 | { Bad_Opcode }, | |
10701 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10702 | }, | |
10703 | { | |
10704 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10705 | { Bad_Opcode }, | |
10706 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10707 | }, | |
10708 | { | |
10709 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10710 | { Bad_Opcode }, | |
10711 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10712 | }, | |
10713 | { | |
10714 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10715 | { Bad_Opcode }, | |
10716 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10717 | }, | |
10718 | { | |
10719 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10720 | { Bad_Opcode }, | |
10721 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10722 | }, | |
10723 | { | |
10724 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10725 | { Bad_Opcode }, | |
10726 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10727 | }, | |
10728 | { | |
10729 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10730 | { Bad_Opcode }, | |
10731 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10732 | }, | |
c0f3af97 | 10733 | { |
592a252b | 10734 | /* MOD_VEX_0F50 */ |
592d1631 | 10735 | { Bad_Opcode }, |
ec6f095a | 10736 | { "vmovmskpX", { Gdq, XS }, 0 }, |
c0f3af97 L |
10737 | }, |
10738 | { | |
592a252b | 10739 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10740 | { Bad_Opcode }, |
592a252b | 10741 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10742 | }, |
10743 | { | |
592a252b | 10744 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10745 | { Bad_Opcode }, |
592a252b | 10746 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10747 | }, |
10748 | { | |
592a252b | 10749 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10750 | { Bad_Opcode }, |
592a252b | 10751 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10752 | }, |
10753 | { | |
592a252b | 10754 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10755 | { Bad_Opcode }, |
592a252b | 10756 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10757 | }, |
d8faab4e | 10758 | { |
592a252b | 10759 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10760 | { Bad_Opcode }, |
592a252b | 10761 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10762 | }, |
10763 | { | |
592a252b | 10764 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10765 | { Bad_Opcode }, |
592a252b | 10766 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10767 | }, |
876d4bfa | 10768 | { |
592a252b | 10769 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10770 | { Bad_Opcode }, |
592a252b | 10771 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10772 | }, |
10773 | { | |
592a252b | 10774 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10775 | { Bad_Opcode }, |
592a252b | 10776 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10777 | }, |
10778 | { | |
592a252b | 10779 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10780 | { Bad_Opcode }, |
592a252b | 10781 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10782 | }, |
10783 | { | |
592a252b | 10784 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10785 | { Bad_Opcode }, |
592a252b | 10786 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10787 | }, |
ab4e4ed5 AF |
10788 | { |
10789 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10790 | { "kmovw", { Ew, MaskG }, 0 }, | |
10791 | { Bad_Opcode }, | |
10792 | }, | |
10793 | { | |
10794 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10795 | { "kmovq", { Eq, MaskG }, 0 }, | |
10796 | { Bad_Opcode }, | |
10797 | }, | |
10798 | { | |
10799 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10800 | { "kmovb", { Eb, MaskG }, 0 }, | |
10801 | { Bad_Opcode }, | |
10802 | }, | |
10803 | { | |
10804 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10805 | { "kmovd", { Ed, MaskG }, 0 }, | |
10806 | { Bad_Opcode }, | |
10807 | }, | |
10808 | { | |
10809 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10810 | { Bad_Opcode }, | |
10811 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10812 | }, | |
10813 | { | |
10814 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10815 | { Bad_Opcode }, | |
10816 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10817 | }, | |
10818 | { | |
58a211d2 | 10819 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10820 | { Bad_Opcode }, |
58a211d2 | 10821 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10822 | }, |
10823 | { | |
10824 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10825 | { Bad_Opcode }, | |
10826 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10827 | }, | |
10828 | { | |
10829 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10830 | { Bad_Opcode }, | |
10831 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10832 | }, | |
10833 | { | |
58a211d2 | 10834 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10835 | { Bad_Opcode }, |
58a211d2 | 10836 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10837 | }, |
10838 | { | |
10839 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10840 | { Bad_Opcode }, | |
10841 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10842 | }, | |
10843 | { | |
10844 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10845 | { Bad_Opcode }, | |
10846 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10847 | }, | |
10848 | { | |
10849 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10850 | { Bad_Opcode }, | |
10851 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10852 | }, | |
10853 | { | |
10854 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10855 | { Bad_Opcode }, | |
10856 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10857 | }, | |
10858 | { | |
10859 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10860 | { Bad_Opcode }, | |
10861 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10862 | }, | |
10863 | { | |
10864 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10865 | { Bad_Opcode }, | |
10866 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10867 | }, | |
10868 | { | |
10869 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10870 | { Bad_Opcode }, | |
10871 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10872 | }, | |
10873 | { | |
10874 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10875 | { Bad_Opcode }, | |
10876 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10877 | }, | |
876d4bfa | 10878 | { |
592a252b L |
10879 | /* MOD_VEX_0FAE_REG_2 */ |
10880 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10881 | }, |
bbedc832 | 10882 | { |
592a252b L |
10883 | /* MOD_VEX_0FAE_REG_3 */ |
10884 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10885 | }, |
144c41d9 | 10886 | { |
592a252b | 10887 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10888 | { Bad_Opcode }, |
ec6f095a | 10889 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10890 | }, |
1afd85e3 | 10891 | { |
592a252b | 10892 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10893 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10894 | }, |
10895 | { | |
592a252b | 10896 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10897 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10898 | }, |
75c135a8 | 10899 | { |
592a252b L |
10900 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10901 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10902 | }, |
1afd85e3 | 10903 | { |
592a252b | 10904 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10905 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10906 | }, |
75c135a8 | 10907 | { |
592a252b L |
10908 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10909 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10910 | }, |
1afd85e3 | 10911 | { |
592a252b L |
10912 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10913 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10914 | }, |
10915 | { | |
592a252b L |
10916 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10917 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10918 | }, |
10919 | { | |
592a252b L |
10920 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10921 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10922 | }, |
6c30d220 L |
10923 | { |
10924 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10925 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10926 | }, | |
10927 | { | |
10928 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10929 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10930 | }, |
10931 | { | |
10932 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10933 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10934 | }, |
ab4e4ed5 AF |
10935 | { |
10936 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10937 | { Bad_Opcode }, | |
10938 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10939 | }, | |
10940 | { | |
10941 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10942 | { Bad_Opcode }, | |
10943 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10944 | }, | |
10945 | { | |
10946 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10947 | { Bad_Opcode }, | |
10948 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10949 | }, | |
10950 | { | |
10951 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10952 | { Bad_Opcode }, | |
10953 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10954 | }, | |
10955 | { | |
10956 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10957 | { Bad_Opcode }, | |
10958 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10959 | }, | |
10960 | { | |
10961 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10962 | { Bad_Opcode }, | |
10963 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10964 | }, | |
10965 | { | |
10966 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10967 | { Bad_Opcode }, | |
10968 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10969 | }, | |
10970 | { | |
10971 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10972 | { Bad_Opcode }, | |
10973 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10974 | }, | |
43234a1e L |
10975 | #define NEED_MOD_TABLE |
10976 | #include "i386-dis-evex.h" | |
10977 | #undef NEED_MOD_TABLE | |
b844680a L |
10978 | }; |
10979 | ||
1ceb70f8 | 10980 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10981 | { |
10982 | /* RM_C6_REG_7 */ | |
bf890a93 | 10983 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10984 | }, |
10985 | { | |
10986 | /* RM_C7_REG_7 */ | |
bf890a93 | 10987 | { "xbeginT", { Skip_MODRM, Jv }, 0 }, |
42164a71 | 10988 | }, |
b844680a | 10989 | { |
1ceb70f8 | 10990 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10991 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10992 | { "vmcall", { Skip_MODRM }, 0 }, |
10993 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10994 | { "vmresume", { Skip_MODRM }, 0 }, | |
10995 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10996 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10997 | }, |
10998 | { | |
1ceb70f8 | 10999 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
11000 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
11001 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
11002 | { "clac", { Skip_MODRM }, 0 }, | |
11003 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
11004 | { Bad_Opcode }, |
11005 | { Bad_Opcode }, | |
11006 | { Bad_Opcode }, | |
bf890a93 | 11007 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 11008 | }, |
475a2301 L |
11009 | { |
11010 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
11011 | { "xgetbv", { Skip_MODRM }, 0 }, |
11012 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
11013 | { Bad_Opcode }, |
11014 | { Bad_Opcode }, | |
bf890a93 IT |
11015 | { "vmfunc", { Skip_MODRM }, 0 }, |
11016 | { "xend", { Skip_MODRM }, 0 }, | |
11017 | { "xtest", { Skip_MODRM }, 0 }, | |
11018 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 11019 | }, |
b844680a | 11020 | { |
1ceb70f8 | 11021 | /* RM_0F01_REG_3 */ |
bf890a93 IT |
11022 | { "vmrun", { Skip_MODRM }, 0 }, |
11023 | { "vmmcall", { Skip_MODRM }, 0 }, | |
11024 | { "vmload", { Skip_MODRM }, 0 }, | |
11025 | { "vmsave", { Skip_MODRM }, 0 }, | |
11026 | { "stgi", { Skip_MODRM }, 0 }, | |
11027 | { "clgi", { Skip_MODRM }, 0 }, | |
11028 | { "skinit", { Skip_MODRM }, 0 }, | |
11029 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 11030 | }, |
8eab4136 L |
11031 | { |
11032 | /* RM_0F01_REG_5 */ | |
2234eee6 | 11033 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_0) }, |
8eab4136 | 11034 | { Bad_Opcode }, |
603555e5 | 11035 | { PREFIX_TABLE (PREFIX_MOD_3_0F01_REG_5_RM_2) }, |
8eab4136 L |
11036 | { Bad_Opcode }, |
11037 | { Bad_Opcode }, | |
11038 | { Bad_Opcode }, | |
11039 | { "rdpkru", { Skip_MODRM }, 0 }, | |
11040 | { "wrpkru", { Skip_MODRM }, 0 }, | |
11041 | }, | |
4e7d34a6 | 11042 | { |
1ceb70f8 | 11043 | /* RM_0F01_REG_7 */ |
bf890a93 IT |
11044 | { "swapgs", { Skip_MODRM }, 0 }, |
11045 | { "rdtscp", { Skip_MODRM }, 0 }, | |
9916071f AP |
11046 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, |
11047 | { "mwaitx", { { OP_Mwaitx, 0 } }, 0 }, | |
bf890a93 | 11048 | { "clzero", { Skip_MODRM }, 0 }, |
b844680a | 11049 | }, |
603555e5 L |
11050 | { |
11051 | /* RM_0F1E_MOD_3_REG_7 */ | |
11052 | { "nopQ", { Ev }, 0 }, | |
11053 | { "nopQ", { Ev }, 0 }, | |
11054 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
11055 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
11056 | { "nopQ", { Ev }, 0 }, | |
11057 | { "nopQ", { Ev }, 0 }, | |
11058 | { "nopQ", { Ev }, 0 }, | |
11059 | { "nopQ", { Ev }, 0 }, | |
11060 | }, | |
b844680a | 11061 | { |
1ceb70f8 | 11062 | /* RM_0FAE_REG_6 */ |
bf890a93 | 11063 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 11064 | }, |
bbedc832 | 11065 | { |
1ceb70f8 | 11066 | /* RM_0FAE_REG_7 */ |
b5cefcca L |
11067 | { "sfence", { Skip_MODRM }, 0 }, |
11068 | ||
144c41d9 | 11069 | }, |
b844680a L |
11070 | }; |
11071 | ||
c608c12e AM |
11072 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
11073 | ||
f16cd0d5 L |
11074 | /* We use the high bit to indicate different name for the same |
11075 | prefix. */ | |
f16cd0d5 | 11076 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
11077 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
11078 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 11079 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 11080 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 L |
11081 | |
11082 | static int | |
26ca5450 | 11083 | ckprefix (void) |
252b5132 | 11084 | { |
f16cd0d5 | 11085 | int newrex, i, length; |
52b15da3 | 11086 | rex = 0; |
c0f3af97 | 11087 | rex_ignored = 0; |
252b5132 | 11088 | prefixes = 0; |
7d421014 | 11089 | used_prefixes = 0; |
52b15da3 | 11090 | rex_used = 0; |
f16cd0d5 L |
11091 | last_lock_prefix = -1; |
11092 | last_repz_prefix = -1; | |
11093 | last_repnz_prefix = -1; | |
11094 | last_data_prefix = -1; | |
11095 | last_addr_prefix = -1; | |
11096 | last_rex_prefix = -1; | |
11097 | last_seg_prefix = -1; | |
d9949a36 | 11098 | fwait_prefix = -1; |
285ca992 | 11099 | active_seg_prefix = 0; |
f310f33d L |
11100 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
11101 | all_prefixes[i] = 0; | |
11102 | i = 0; | |
f16cd0d5 L |
11103 | length = 0; |
11104 | /* The maximum instruction length is 15bytes. */ | |
11105 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
11106 | { |
11107 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 11108 | newrex = 0; |
252b5132 RH |
11109 | switch (*codep) |
11110 | { | |
52b15da3 JH |
11111 | /* REX prefixes family. */ |
11112 | case 0x40: | |
11113 | case 0x41: | |
11114 | case 0x42: | |
11115 | case 0x43: | |
11116 | case 0x44: | |
11117 | case 0x45: | |
11118 | case 0x46: | |
11119 | case 0x47: | |
11120 | case 0x48: | |
11121 | case 0x49: | |
11122 | case 0x4a: | |
11123 | case 0x4b: | |
11124 | case 0x4c: | |
11125 | case 0x4d: | |
11126 | case 0x4e: | |
11127 | case 0x4f: | |
f16cd0d5 L |
11128 | if (address_mode == mode_64bit) |
11129 | newrex = *codep; | |
11130 | else | |
11131 | return 1; | |
11132 | last_rex_prefix = i; | |
52b15da3 | 11133 | break; |
252b5132 RH |
11134 | case 0xf3: |
11135 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11136 | last_repz_prefix = i; |
252b5132 RH |
11137 | break; |
11138 | case 0xf2: | |
11139 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11140 | last_repnz_prefix = i; |
252b5132 RH |
11141 | break; |
11142 | case 0xf0: | |
11143 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11144 | last_lock_prefix = i; |
252b5132 RH |
11145 | break; |
11146 | case 0x2e: | |
11147 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11148 | last_seg_prefix = i; |
285ca992 | 11149 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11150 | break; |
11151 | case 0x36: | |
11152 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11153 | last_seg_prefix = i; |
285ca992 | 11154 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11155 | break; |
11156 | case 0x3e: | |
11157 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11158 | last_seg_prefix = i; |
285ca992 | 11159 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11160 | break; |
11161 | case 0x26: | |
11162 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11163 | last_seg_prefix = i; |
285ca992 | 11164 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11165 | break; |
11166 | case 0x64: | |
11167 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11168 | last_seg_prefix = i; |
285ca992 | 11169 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11170 | break; |
11171 | case 0x65: | |
11172 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11173 | last_seg_prefix = i; |
285ca992 | 11174 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11175 | break; |
11176 | case 0x66: | |
11177 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11178 | last_data_prefix = i; |
252b5132 RH |
11179 | break; |
11180 | case 0x67: | |
11181 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11182 | last_addr_prefix = i; |
252b5132 | 11183 | break; |
5076851f | 11184 | case FWAIT_OPCODE: |
252b5132 RH |
11185 | /* fwait is really an instruction. If there are prefixes |
11186 | before the fwait, they belong to the fwait, *not* to the | |
11187 | following instruction. */ | |
d9949a36 | 11188 | fwait_prefix = i; |
3e7d61b2 | 11189 | if (prefixes || rex) |
252b5132 RH |
11190 | { |
11191 | prefixes |= PREFIX_FWAIT; | |
11192 | codep++; | |
6c067bbb RM |
11193 | /* This ensures that the previous REX prefixes are noticed |
11194 | as unused prefixes, as in the return case below. */ | |
11195 | rex_used = rex; | |
f16cd0d5 | 11196 | return 1; |
252b5132 RH |
11197 | } |
11198 | prefixes = PREFIX_FWAIT; | |
11199 | break; | |
11200 | default: | |
f16cd0d5 | 11201 | return 1; |
252b5132 | 11202 | } |
52b15da3 JH |
11203 | /* Rex is ignored when followed by another prefix. */ |
11204 | if (rex) | |
11205 | { | |
3e7d61b2 | 11206 | rex_used = rex; |
f16cd0d5 | 11207 | return 1; |
52b15da3 | 11208 | } |
f16cd0d5 | 11209 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11210 | all_prefixes[i++] = *codep; |
52b15da3 | 11211 | rex = newrex; |
252b5132 | 11212 | codep++; |
f16cd0d5 L |
11213 | length++; |
11214 | } | |
11215 | return 0; | |
11216 | } | |
11217 | ||
7d421014 ILT |
11218 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11219 | prefix byte. */ | |
11220 | ||
11221 | static const char * | |
26ca5450 | 11222 | prefix_name (int pref, int sizeflag) |
7d421014 | 11223 | { |
0003779b L |
11224 | static const char *rexes [16] = |
11225 | { | |
11226 | "rex", /* 0x40 */ | |
11227 | "rex.B", /* 0x41 */ | |
11228 | "rex.X", /* 0x42 */ | |
11229 | "rex.XB", /* 0x43 */ | |
11230 | "rex.R", /* 0x44 */ | |
11231 | "rex.RB", /* 0x45 */ | |
11232 | "rex.RX", /* 0x46 */ | |
11233 | "rex.RXB", /* 0x47 */ | |
11234 | "rex.W", /* 0x48 */ | |
11235 | "rex.WB", /* 0x49 */ | |
11236 | "rex.WX", /* 0x4a */ | |
11237 | "rex.WXB", /* 0x4b */ | |
11238 | "rex.WR", /* 0x4c */ | |
11239 | "rex.WRB", /* 0x4d */ | |
11240 | "rex.WRX", /* 0x4e */ | |
11241 | "rex.WRXB", /* 0x4f */ | |
11242 | }; | |
11243 | ||
7d421014 ILT |
11244 | switch (pref) |
11245 | { | |
52b15da3 JH |
11246 | /* REX prefixes family. */ |
11247 | case 0x40: | |
52b15da3 | 11248 | case 0x41: |
52b15da3 | 11249 | case 0x42: |
52b15da3 | 11250 | case 0x43: |
52b15da3 | 11251 | case 0x44: |
52b15da3 | 11252 | case 0x45: |
52b15da3 | 11253 | case 0x46: |
52b15da3 | 11254 | case 0x47: |
52b15da3 | 11255 | case 0x48: |
52b15da3 | 11256 | case 0x49: |
52b15da3 | 11257 | case 0x4a: |
52b15da3 | 11258 | case 0x4b: |
52b15da3 | 11259 | case 0x4c: |
52b15da3 | 11260 | case 0x4d: |
52b15da3 | 11261 | case 0x4e: |
52b15da3 | 11262 | case 0x4f: |
0003779b | 11263 | return rexes [pref - 0x40]; |
7d421014 ILT |
11264 | case 0xf3: |
11265 | return "repz"; | |
11266 | case 0xf2: | |
11267 | return "repnz"; | |
11268 | case 0xf0: | |
11269 | return "lock"; | |
11270 | case 0x2e: | |
11271 | return "cs"; | |
11272 | case 0x36: | |
11273 | return "ss"; | |
11274 | case 0x3e: | |
11275 | return "ds"; | |
11276 | case 0x26: | |
11277 | return "es"; | |
11278 | case 0x64: | |
11279 | return "fs"; | |
11280 | case 0x65: | |
11281 | return "gs"; | |
11282 | case 0x66: | |
11283 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11284 | case 0x67: | |
cb712a9e | 11285 | if (address_mode == mode_64bit) |
db6eb5be | 11286 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11287 | else |
2888cb7a | 11288 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11289 | case FWAIT_OPCODE: |
11290 | return "fwait"; | |
f16cd0d5 L |
11291 | case REP_PREFIX: |
11292 | return "rep"; | |
42164a71 L |
11293 | case XACQUIRE_PREFIX: |
11294 | return "xacquire"; | |
11295 | case XRELEASE_PREFIX: | |
11296 | return "xrelease"; | |
7e8b059b L |
11297 | case BND_PREFIX: |
11298 | return "bnd"; | |
04ef582a L |
11299 | case NOTRACK_PREFIX: |
11300 | return "notrack"; | |
7d421014 ILT |
11301 | default: |
11302 | return NULL; | |
11303 | } | |
11304 | } | |
11305 | ||
ce518a5f L |
11306 | static char op_out[MAX_OPERANDS][100]; |
11307 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11308 | static int two_source_ops; |
ce518a5f L |
11309 | static bfd_vma op_address[MAX_OPERANDS]; |
11310 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11311 | static bfd_vma start_pc; |
ce518a5f | 11312 | |
252b5132 RH |
11313 | /* |
11314 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11315 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11316 | * section of the "Virtual 8086 Mode" chapter.) | |
11317 | * 'pc' should be the address of this instruction, it will | |
11318 | * be used to print the target address if this is a relative jump or call | |
11319 | * The function returns the length of this instruction in bytes. | |
11320 | */ | |
11321 | ||
252b5132 | 11322 | static char intel_syntax; |
9d141669 | 11323 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11324 | static char open_char; |
11325 | static char close_char; | |
11326 | static char separator_char; | |
11327 | static char scale_char; | |
11328 | ||
5db04b09 L |
11329 | enum x86_64_isa |
11330 | { | |
11331 | amd64 = 0, | |
11332 | intel64 | |
11333 | }; | |
11334 | ||
11335 | static enum x86_64_isa isa64; | |
11336 | ||
e396998b AM |
11337 | /* Here for backwards compatibility. When gdb stops using |
11338 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11339 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11340 | int |
26ca5450 | 11341 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11342 | { |
11343 | intel_syntax = 0; | |
e396998b AM |
11344 | |
11345 | return print_insn (pc, info); | |
252b5132 RH |
11346 | } |
11347 | ||
11348 | int | |
26ca5450 | 11349 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11350 | { |
11351 | intel_syntax = 1; | |
e396998b AM |
11352 | |
11353 | return print_insn (pc, info); | |
252b5132 RH |
11354 | } |
11355 | ||
e396998b | 11356 | int |
26ca5450 | 11357 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11358 | { |
11359 | intel_syntax = -1; | |
11360 | ||
11361 | return print_insn (pc, info); | |
11362 | } | |
11363 | ||
f59a29b9 L |
11364 | void |
11365 | print_i386_disassembler_options (FILE *stream) | |
11366 | { | |
11367 | fprintf (stream, _("\n\ | |
11368 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11369 | with the -M switch (multiple options should be separated by commas):\n")); | |
11370 | ||
11371 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11372 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11373 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11374 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11375 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11376 | fprintf (stream, _(" att-mnemonic\n" |
11377 | " Display instruction in AT&T mnemonic\n")); | |
11378 | fprintf (stream, _(" intel-mnemonic\n" | |
11379 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11380 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11381 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11382 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11383 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11384 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11385 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11386 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11387 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11388 | } |
11389 | ||
592d1631 | 11390 | /* Bad opcode. */ |
bf890a93 | 11391 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11392 | |
b844680a L |
11393 | /* Get a pointer to struct dis386 with a valid name. */ |
11394 | ||
11395 | static const struct dis386 * | |
8bb15339 | 11396 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11397 | { |
91d6fa6a | 11398 | int vindex, vex_table_index; |
b844680a L |
11399 | |
11400 | if (dp->name != NULL) | |
11401 | return dp; | |
11402 | ||
11403 | switch (dp->op[0].bytemode) | |
11404 | { | |
1ceb70f8 L |
11405 | case USE_REG_TABLE: |
11406 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11407 | break; | |
11408 | ||
11409 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11410 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11411 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11412 | break; |
11413 | ||
11414 | case USE_RM_TABLE: | |
11415 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11416 | break; |
11417 | ||
4e7d34a6 | 11418 | case USE_PREFIX_TABLE: |
c0f3af97 | 11419 | if (need_vex) |
b844680a | 11420 | { |
c0f3af97 L |
11421 | /* The prefix in VEX is implicit. */ |
11422 | switch (vex.prefix) | |
11423 | { | |
11424 | case 0: | |
91d6fa6a | 11425 | vindex = 0; |
c0f3af97 L |
11426 | break; |
11427 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11428 | vindex = 1; |
c0f3af97 L |
11429 | break; |
11430 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11431 | vindex = 2; |
c0f3af97 L |
11432 | break; |
11433 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11434 | vindex = 3; |
c0f3af97 L |
11435 | break; |
11436 | default: | |
11437 | abort (); | |
11438 | break; | |
11439 | } | |
b844680a | 11440 | } |
7bb15c6f | 11441 | else |
b844680a | 11442 | { |
285ca992 L |
11443 | int last_prefix = -1; |
11444 | int prefix = 0; | |
91d6fa6a | 11445 | vindex = 0; |
285ca992 L |
11446 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11447 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11448 | last one wins. */ | |
11449 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11450 | { |
285ca992 | 11451 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11452 | { |
285ca992 L |
11453 | vindex = 1; |
11454 | prefix = PREFIX_REPZ; | |
11455 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11456 | } |
11457 | else | |
b844680a | 11458 | { |
285ca992 L |
11459 | vindex = 3; |
11460 | prefix = PREFIX_REPNZ; | |
11461 | last_prefix = last_repnz_prefix; | |
b844680a | 11462 | } |
285ca992 | 11463 | |
507bd325 L |
11464 | /* Check if prefix should be ignored. */ |
11465 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11466 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11467 | & prefix) != 0) | |
285ca992 L |
11468 | vindex = 0; |
11469 | } | |
11470 | ||
11471 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11472 | { | |
11473 | vindex = 2; | |
11474 | prefix = PREFIX_DATA; | |
11475 | last_prefix = last_data_prefix; | |
11476 | } | |
11477 | ||
11478 | if (vindex != 0) | |
11479 | { | |
11480 | used_prefixes |= prefix; | |
11481 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11482 | } |
11483 | } | |
91d6fa6a | 11484 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11485 | break; |
11486 | ||
4e7d34a6 | 11487 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11488 | vindex = address_mode == mode_64bit ? 1 : 0; |
11489 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11490 | break; |
11491 | ||
4e7d34a6 | 11492 | case USE_3BYTE_TABLE: |
8bb15339 | 11493 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11494 | vindex = *codep++; |
11495 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11496 | end_codep = codep; |
8bb15339 L |
11497 | modrm.mod = (*codep >> 6) & 3; |
11498 | modrm.reg = (*codep >> 3) & 7; | |
11499 | modrm.rm = *codep & 7; | |
11500 | break; | |
11501 | ||
c0f3af97 L |
11502 | case USE_VEX_LEN_TABLE: |
11503 | if (!need_vex) | |
11504 | abort (); | |
11505 | ||
11506 | switch (vex.length) | |
11507 | { | |
11508 | case 128: | |
91d6fa6a | 11509 | vindex = 0; |
c0f3af97 L |
11510 | break; |
11511 | case 256: | |
91d6fa6a | 11512 | vindex = 1; |
c0f3af97 L |
11513 | break; |
11514 | default: | |
11515 | abort (); | |
11516 | break; | |
11517 | } | |
11518 | ||
91d6fa6a | 11519 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11520 | break; |
11521 | ||
04e2a182 L |
11522 | case USE_EVEX_LEN_TABLE: |
11523 | if (!vex.evex) | |
11524 | abort (); | |
11525 | ||
11526 | switch (vex.length) | |
11527 | { | |
11528 | case 128: | |
11529 | vindex = 0; | |
11530 | break; | |
11531 | case 256: | |
11532 | vindex = 1; | |
11533 | break; | |
11534 | case 512: | |
11535 | vindex = 2; | |
11536 | break; | |
11537 | default: | |
11538 | abort (); | |
11539 | break; | |
11540 | } | |
11541 | ||
11542 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11543 | break; | |
11544 | ||
f88c9eb0 SP |
11545 | case USE_XOP_8F_TABLE: |
11546 | FETCH_DATA (info, codep + 3); | |
11547 | /* All bits in the REX prefix are ignored. */ | |
11548 | rex_ignored = rex; | |
11549 | rex = ~(*codep >> 5) & 0x7; | |
11550 | ||
11551 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11552 | switch ((*codep & 0x1f)) | |
11553 | { | |
11554 | default: | |
f07af43e L |
11555 | dp = &bad_opcode; |
11556 | return dp; | |
5dd85c99 SP |
11557 | case 0x8: |
11558 | vex_table_index = XOP_08; | |
11559 | break; | |
f88c9eb0 SP |
11560 | case 0x9: |
11561 | vex_table_index = XOP_09; | |
11562 | break; | |
11563 | case 0xa: | |
11564 | vex_table_index = XOP_0A; | |
11565 | break; | |
11566 | } | |
11567 | codep++; | |
11568 | vex.w = *codep & 0x80; | |
11569 | if (vex.w && address_mode == mode_64bit) | |
11570 | rex |= REX_W; | |
11571 | ||
11572 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11573 | if (address_mode != mode_64bit) |
f07af43e | 11574 | { |
abfcb414 AP |
11575 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11576 | rex &= ~REX_B; | |
f07af43e | 11577 | } |
f88c9eb0 SP |
11578 | |
11579 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11580 | switch ((*codep & 0x3)) | |
11581 | { | |
11582 | case 0: | |
f88c9eb0 SP |
11583 | break; |
11584 | case 1: | |
11585 | vex.prefix = DATA_PREFIX_OPCODE; | |
11586 | break; | |
11587 | case 2: | |
11588 | vex.prefix = REPE_PREFIX_OPCODE; | |
11589 | break; | |
11590 | case 3: | |
11591 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11592 | break; | |
11593 | } | |
11594 | need_vex = 1; | |
11595 | need_vex_reg = 1; | |
11596 | codep++; | |
91d6fa6a NC |
11597 | vindex = *codep++; |
11598 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11599 | |
285ca992 | 11600 | end_codep = codep; |
c48244a5 SP |
11601 | FETCH_DATA (info, codep + 1); |
11602 | modrm.mod = (*codep >> 6) & 3; | |
11603 | modrm.reg = (*codep >> 3) & 7; | |
11604 | modrm.rm = *codep & 7; | |
f88c9eb0 SP |
11605 | break; |
11606 | ||
c0f3af97 | 11607 | case USE_VEX_C4_TABLE: |
43234a1e | 11608 | /* VEX prefix. */ |
c0f3af97 L |
11609 | FETCH_DATA (info, codep + 3); |
11610 | /* All bits in the REX prefix are ignored. */ | |
11611 | rex_ignored = rex; | |
11612 | rex = ~(*codep >> 5) & 0x7; | |
11613 | switch ((*codep & 0x1f)) | |
11614 | { | |
11615 | default: | |
f07af43e L |
11616 | dp = &bad_opcode; |
11617 | return dp; | |
c0f3af97 | 11618 | case 0x1: |
f88c9eb0 | 11619 | vex_table_index = VEX_0F; |
c0f3af97 L |
11620 | break; |
11621 | case 0x2: | |
f88c9eb0 | 11622 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11623 | break; |
11624 | case 0x3: | |
f88c9eb0 | 11625 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11626 | break; |
11627 | } | |
11628 | codep++; | |
11629 | vex.w = *codep & 0x80; | |
9889cbb1 | 11630 | if (address_mode == mode_64bit) |
f07af43e | 11631 | { |
9889cbb1 L |
11632 | if (vex.w) |
11633 | rex |= REX_W; | |
9889cbb1 L |
11634 | } |
11635 | else | |
11636 | { | |
11637 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11638 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11639 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11640 | rex = 0; |
f07af43e | 11641 | } |
5f847646 | 11642 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11643 | vex.length = (*codep & 0x4) ? 256 : 128; |
11644 | switch ((*codep & 0x3)) | |
11645 | { | |
11646 | case 0: | |
c0f3af97 L |
11647 | break; |
11648 | case 1: | |
11649 | vex.prefix = DATA_PREFIX_OPCODE; | |
11650 | break; | |
11651 | case 2: | |
11652 | vex.prefix = REPE_PREFIX_OPCODE; | |
11653 | break; | |
11654 | case 3: | |
11655 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11656 | break; | |
11657 | } | |
11658 | need_vex = 1; | |
11659 | need_vex_reg = 1; | |
11660 | codep++; | |
91d6fa6a NC |
11661 | vindex = *codep++; |
11662 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11663 | end_codep = codep; |
53c4d625 JB |
11664 | /* There is no MODRM byte for VEX0F 77. */ |
11665 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11666 | { |
11667 | FETCH_DATA (info, codep + 1); | |
11668 | modrm.mod = (*codep >> 6) & 3; | |
11669 | modrm.reg = (*codep >> 3) & 7; | |
11670 | modrm.rm = *codep & 7; | |
11671 | } | |
11672 | break; | |
11673 | ||
11674 | case USE_VEX_C5_TABLE: | |
43234a1e | 11675 | /* VEX prefix. */ |
c0f3af97 L |
11676 | FETCH_DATA (info, codep + 2); |
11677 | /* All bits in the REX prefix are ignored. */ | |
11678 | rex_ignored = rex; | |
11679 | rex = (*codep & 0x80) ? 0 : REX_R; | |
11680 | ||
9889cbb1 L |
11681 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11682 | VEX.vvvv is 1. */ | |
c0f3af97 | 11683 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11684 | vex.length = (*codep & 0x4) ? 256 : 128; |
11685 | switch ((*codep & 0x3)) | |
11686 | { | |
11687 | case 0: | |
c0f3af97 L |
11688 | break; |
11689 | case 1: | |
11690 | vex.prefix = DATA_PREFIX_OPCODE; | |
11691 | break; | |
11692 | case 2: | |
11693 | vex.prefix = REPE_PREFIX_OPCODE; | |
11694 | break; | |
11695 | case 3: | |
11696 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11697 | break; | |
11698 | } | |
11699 | need_vex = 1; | |
11700 | need_vex_reg = 1; | |
11701 | codep++; | |
91d6fa6a NC |
11702 | vindex = *codep++; |
11703 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11704 | end_codep = codep; |
53c4d625 JB |
11705 | /* There is no MODRM byte for VEX 77. */ |
11706 | if (vindex != 0x77) | |
c0f3af97 L |
11707 | { |
11708 | FETCH_DATA (info, codep + 1); | |
11709 | modrm.mod = (*codep >> 6) & 3; | |
11710 | modrm.reg = (*codep >> 3) & 7; | |
11711 | modrm.rm = *codep & 7; | |
11712 | } | |
11713 | break; | |
11714 | ||
9e30b8e0 L |
11715 | case USE_VEX_W_TABLE: |
11716 | if (!need_vex) | |
11717 | abort (); | |
11718 | ||
11719 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11720 | break; | |
11721 | ||
43234a1e L |
11722 | case USE_EVEX_TABLE: |
11723 | two_source_ops = 0; | |
11724 | /* EVEX prefix. */ | |
11725 | vex.evex = 1; | |
11726 | FETCH_DATA (info, codep + 4); | |
11727 | /* All bits in the REX prefix are ignored. */ | |
11728 | rex_ignored = rex; | |
11729 | /* The first byte after 0x62. */ | |
11730 | rex = ~(*codep >> 5) & 0x7; | |
11731 | vex.r = *codep & 0x10; | |
11732 | switch ((*codep & 0xf)) | |
11733 | { | |
11734 | default: | |
11735 | return &bad_opcode; | |
11736 | case 0x1: | |
11737 | vex_table_index = EVEX_0F; | |
11738 | break; | |
11739 | case 0x2: | |
11740 | vex_table_index = EVEX_0F38; | |
11741 | break; | |
11742 | case 0x3: | |
11743 | vex_table_index = EVEX_0F3A; | |
11744 | break; | |
11745 | } | |
11746 | ||
11747 | /* The second byte after 0x62. */ | |
11748 | codep++; | |
11749 | vex.w = *codep & 0x80; | |
11750 | if (vex.w && address_mode == mode_64bit) | |
11751 | rex |= REX_W; | |
11752 | ||
11753 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11754 | |
11755 | /* The U bit. */ | |
11756 | if (!(*codep & 0x4)) | |
11757 | return &bad_opcode; | |
11758 | ||
11759 | switch ((*codep & 0x3)) | |
11760 | { | |
11761 | case 0: | |
43234a1e L |
11762 | break; |
11763 | case 1: | |
11764 | vex.prefix = DATA_PREFIX_OPCODE; | |
11765 | break; | |
11766 | case 2: | |
11767 | vex.prefix = REPE_PREFIX_OPCODE; | |
11768 | break; | |
11769 | case 3: | |
11770 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11771 | break; | |
11772 | } | |
11773 | ||
11774 | /* The third byte after 0x62. */ | |
11775 | codep++; | |
11776 | ||
11777 | /* Remember the static rounding bits. */ | |
11778 | vex.ll = (*codep >> 5) & 3; | |
11779 | vex.b = (*codep & 0x10) != 0; | |
11780 | ||
11781 | vex.v = *codep & 0x8; | |
11782 | vex.mask_register_specifier = *codep & 0x7; | |
11783 | vex.zeroing = *codep & 0x80; | |
11784 | ||
5f847646 JB |
11785 | if (address_mode != mode_64bit) |
11786 | { | |
11787 | /* In 16/32-bit mode silently ignore following bits. */ | |
11788 | rex &= ~REX_B; | |
11789 | vex.r = 1; | |
11790 | vex.v = 1; | |
11791 | } | |
11792 | ||
43234a1e L |
11793 | need_vex = 1; |
11794 | need_vex_reg = 1; | |
11795 | codep++; | |
11796 | vindex = *codep++; | |
11797 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11798 | end_codep = codep; |
43234a1e L |
11799 | FETCH_DATA (info, codep + 1); |
11800 | modrm.mod = (*codep >> 6) & 3; | |
11801 | modrm.reg = (*codep >> 3) & 7; | |
11802 | modrm.rm = *codep & 7; | |
11803 | ||
11804 | /* Set vector length. */ | |
11805 | if (modrm.mod == 3 && vex.b) | |
11806 | vex.length = 512; | |
11807 | else | |
11808 | { | |
11809 | switch (vex.ll) | |
11810 | { | |
11811 | case 0x0: | |
11812 | vex.length = 128; | |
11813 | break; | |
11814 | case 0x1: | |
11815 | vex.length = 256; | |
11816 | break; | |
11817 | case 0x2: | |
11818 | vex.length = 512; | |
11819 | break; | |
11820 | default: | |
11821 | return &bad_opcode; | |
11822 | } | |
11823 | } | |
11824 | break; | |
11825 | ||
592d1631 L |
11826 | case 0: |
11827 | dp = &bad_opcode; | |
11828 | break; | |
11829 | ||
b844680a | 11830 | default: |
d34b5006 | 11831 | abort (); |
b844680a L |
11832 | } |
11833 | ||
11834 | if (dp->name != NULL) | |
11835 | return dp; | |
11836 | else | |
8bb15339 | 11837 | return get_valid_dis386 (dp, info); |
b844680a L |
11838 | } |
11839 | ||
dfc8cf43 | 11840 | static void |
55cf16e1 | 11841 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11842 | { |
11843 | /* If modrm.mod == 3, operand must be register. */ | |
11844 | if (need_modrm | |
55cf16e1 | 11845 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11846 | && modrm.mod != 3 |
11847 | && modrm.rm == 4) | |
11848 | { | |
11849 | FETCH_DATA (info, codep + 2); | |
11850 | sib.index = (codep [1] >> 3) & 7; | |
11851 | sib.scale = (codep [1] >> 6) & 3; | |
11852 | sib.base = codep [1] & 7; | |
11853 | } | |
11854 | } | |
11855 | ||
e396998b | 11856 | static int |
26ca5450 | 11857 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11858 | { |
2da11e11 | 11859 | const struct dis386 *dp; |
252b5132 | 11860 | int i; |
ce518a5f | 11861 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11862 | int needcomma; |
df18fdba | 11863 | int sizeflag, orig_sizeflag; |
e396998b | 11864 | const char *p; |
252b5132 | 11865 | struct dis_private priv; |
f16cd0d5 | 11866 | int prefix_length; |
252b5132 | 11867 | |
d7921315 L |
11868 | priv.orig_sizeflag = AFLAG | DFLAG; |
11869 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11870 | address_mode = mode_32bit; |
2da11e11 | 11871 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11872 | { |
11873 | address_mode = mode_16bit; | |
11874 | priv.orig_sizeflag = 0; | |
11875 | } | |
2da11e11 | 11876 | else |
d7921315 L |
11877 | address_mode = mode_64bit; |
11878 | ||
11879 | if (intel_syntax == (char) -1) | |
11880 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11881 | |
11882 | for (p = info->disassembler_options; p != NULL; ) | |
11883 | { | |
5db04b09 L |
11884 | if (CONST_STRNEQ (p, "amd64")) |
11885 | isa64 = amd64; | |
11886 | else if (CONST_STRNEQ (p, "intel64")) | |
11887 | isa64 = intel64; | |
11888 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11889 | { |
cb712a9e | 11890 | address_mode = mode_64bit; |
e396998b AM |
11891 | priv.orig_sizeflag = AFLAG | DFLAG; |
11892 | } | |
0112cd26 | 11893 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11894 | { |
cb712a9e | 11895 | address_mode = mode_32bit; |
e396998b AM |
11896 | priv.orig_sizeflag = AFLAG | DFLAG; |
11897 | } | |
0112cd26 | 11898 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11899 | { |
cb712a9e | 11900 | address_mode = mode_16bit; |
e396998b AM |
11901 | priv.orig_sizeflag = 0; |
11902 | } | |
0112cd26 | 11903 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11904 | { |
11905 | intel_syntax = 1; | |
9d141669 L |
11906 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11907 | intel_mnemonic = 1; | |
e396998b | 11908 | } |
0112cd26 | 11909 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11910 | { |
11911 | intel_syntax = 0; | |
9d141669 L |
11912 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11913 | intel_mnemonic = 0; | |
e396998b | 11914 | } |
0112cd26 | 11915 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11916 | { |
f59a29b9 L |
11917 | if (address_mode == mode_64bit) |
11918 | { | |
11919 | if (p[4] == '3' && p[5] == '2') | |
11920 | priv.orig_sizeflag &= ~AFLAG; | |
11921 | else if (p[4] == '6' && p[5] == '4') | |
11922 | priv.orig_sizeflag |= AFLAG; | |
11923 | } | |
11924 | else | |
11925 | { | |
11926 | if (p[4] == '1' && p[5] == '6') | |
11927 | priv.orig_sizeflag &= ~AFLAG; | |
11928 | else if (p[4] == '3' && p[5] == '2') | |
11929 | priv.orig_sizeflag |= AFLAG; | |
11930 | } | |
e396998b | 11931 | } |
0112cd26 | 11932 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11933 | { |
11934 | if (p[4] == '1' && p[5] == '6') | |
11935 | priv.orig_sizeflag &= ~DFLAG; | |
11936 | else if (p[4] == '3' && p[5] == '2') | |
11937 | priv.orig_sizeflag |= DFLAG; | |
11938 | } | |
0112cd26 | 11939 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11940 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11941 | ||
11942 | p = strchr (p, ','); | |
11943 | if (p != NULL) | |
11944 | p++; | |
11945 | } | |
11946 | ||
c0f92bf9 L |
11947 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11948 | { | |
11949 | (*info->fprintf_func) (info->stream, | |
11950 | _("64-bit address is disabled")); | |
11951 | return -1; | |
11952 | } | |
11953 | ||
e396998b AM |
11954 | if (intel_syntax) |
11955 | { | |
11956 | names64 = intel_names64; | |
11957 | names32 = intel_names32; | |
11958 | names16 = intel_names16; | |
11959 | names8 = intel_names8; | |
11960 | names8rex = intel_names8rex; | |
11961 | names_seg = intel_names_seg; | |
b9733481 | 11962 | names_mm = intel_names_mm; |
7e8b059b | 11963 | names_bnd = intel_names_bnd; |
b9733481 L |
11964 | names_xmm = intel_names_xmm; |
11965 | names_ymm = intel_names_ymm; | |
43234a1e | 11966 | names_zmm = intel_names_zmm; |
db51cc60 L |
11967 | index64 = intel_index64; |
11968 | index32 = intel_index32; | |
43234a1e | 11969 | names_mask = intel_names_mask; |
e396998b AM |
11970 | index16 = intel_index16; |
11971 | open_char = '['; | |
11972 | close_char = ']'; | |
11973 | separator_char = '+'; | |
11974 | scale_char = '*'; | |
11975 | } | |
11976 | else | |
11977 | { | |
11978 | names64 = att_names64; | |
11979 | names32 = att_names32; | |
11980 | names16 = att_names16; | |
11981 | names8 = att_names8; | |
11982 | names8rex = att_names8rex; | |
11983 | names_seg = att_names_seg; | |
b9733481 | 11984 | names_mm = att_names_mm; |
7e8b059b | 11985 | names_bnd = att_names_bnd; |
b9733481 L |
11986 | names_xmm = att_names_xmm; |
11987 | names_ymm = att_names_ymm; | |
43234a1e | 11988 | names_zmm = att_names_zmm; |
db51cc60 L |
11989 | index64 = att_index64; |
11990 | index32 = att_index32; | |
43234a1e | 11991 | names_mask = att_names_mask; |
e396998b AM |
11992 | index16 = att_index16; |
11993 | open_char = '('; | |
11994 | close_char = ')'; | |
11995 | separator_char = ','; | |
11996 | scale_char = ','; | |
11997 | } | |
2da11e11 | 11998 | |
4fe53c98 | 11999 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
12000 | puts most long word instructions on a single line. Use 8 bytes |
12001 | for Intel L1OM. */ | |
d7921315 | 12002 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
12003 | info->bytes_per_line = 8; |
12004 | else | |
12005 | info->bytes_per_line = 7; | |
252b5132 | 12006 | |
26ca5450 | 12007 | info->private_data = &priv; |
252b5132 RH |
12008 | priv.max_fetched = priv.the_buffer; |
12009 | priv.insn_start = pc; | |
252b5132 RH |
12010 | |
12011 | obuf[0] = 0; | |
ce518a5f L |
12012 | for (i = 0; i < MAX_OPERANDS; ++i) |
12013 | { | |
12014 | op_out[i][0] = 0; | |
12015 | op_index[i] = -1; | |
12016 | } | |
252b5132 RH |
12017 | |
12018 | the_info = info; | |
12019 | start_pc = pc; | |
e396998b AM |
12020 | start_codep = priv.the_buffer; |
12021 | codep = priv.the_buffer; | |
252b5132 | 12022 | |
8df14d78 | 12023 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 12024 | { |
7d421014 ILT |
12025 | const char *name; |
12026 | ||
5076851f | 12027 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
12028 | means we have an incomplete instruction of some sort. Just |
12029 | print the first byte as a prefix or a .byte pseudo-op. */ | |
12030 | if (codep > priv.the_buffer) | |
5076851f | 12031 | { |
e396998b | 12032 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
12033 | if (name != NULL) |
12034 | (*info->fprintf_func) (info->stream, "%s", name); | |
12035 | else | |
5076851f | 12036 | { |
7d421014 ILT |
12037 | /* Just print the first byte as a .byte instruction. */ |
12038 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 12039 | (unsigned int) priv.the_buffer[0]); |
5076851f | 12040 | } |
5076851f | 12041 | |
7d421014 | 12042 | return 1; |
5076851f ILT |
12043 | } |
12044 | ||
12045 | return -1; | |
12046 | } | |
12047 | ||
52b15da3 | 12048 | obufp = obuf; |
f16cd0d5 L |
12049 | sizeflag = priv.orig_sizeflag; |
12050 | ||
12051 | if (!ckprefix () || rex_used) | |
12052 | { | |
12053 | /* Too many prefixes or unused REX prefixes. */ | |
12054 | for (i = 0; | |
f6dd4781 | 12055 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 12056 | i++) |
de882298 | 12057 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 12058 | i == 0 ? "" : " ", |
f16cd0d5 | 12059 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 12060 | return i; |
f16cd0d5 | 12061 | } |
252b5132 RH |
12062 | |
12063 | insn_codep = codep; | |
12064 | ||
12065 | FETCH_DATA (info, codep + 1); | |
12066 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
12067 | ||
3e7d61b2 | 12068 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 12069 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 12070 | { |
86a80a50 | 12071 | /* Handle prefixes before fwait. */ |
d9949a36 | 12072 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
12073 | i++) |
12074 | (*info->fprintf_func) (info->stream, "%s ", | |
12075 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 12076 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 12077 | return i + 1; |
252b5132 RH |
12078 | } |
12079 | ||
252b5132 RH |
12080 | if (*codep == 0x0f) |
12081 | { | |
eec0f4ca | 12082 | unsigned char threebyte; |
5f40e14d JS |
12083 | |
12084 | codep++; | |
12085 | FETCH_DATA (info, codep + 1); | |
12086 | threebyte = *codep; | |
eec0f4ca | 12087 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 12088 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 12089 | codep++; |
252b5132 RH |
12090 | } |
12091 | else | |
12092 | { | |
6439fc28 | 12093 | dp = &dis386[*codep]; |
252b5132 | 12094 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 12095 | codep++; |
252b5132 | 12096 | } |
246c51aa | 12097 | |
df18fdba L |
12098 | /* Save sizeflag for printing the extra prefixes later before updating |
12099 | it for mnemonic and operand processing. The prefix names depend | |
12100 | only on the address mode. */ | |
12101 | orig_sizeflag = sizeflag; | |
c608c12e | 12102 | if (prefixes & PREFIX_ADDR) |
df18fdba | 12103 | sizeflag ^= AFLAG; |
b844680a | 12104 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 12105 | sizeflag ^= DFLAG; |
3ffd33cf | 12106 | |
285ca992 | 12107 | end_codep = codep; |
8bb15339 | 12108 | if (need_modrm) |
252b5132 RH |
12109 | { |
12110 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
12111 | modrm.mod = (*codep >> 6) & 3; |
12112 | modrm.reg = (*codep >> 3) & 7; | |
12113 | modrm.rm = *codep & 7; | |
252b5132 RH |
12114 | } |
12115 | ||
42d5f9c6 MS |
12116 | need_vex = 0; |
12117 | need_vex_reg = 0; | |
12118 | vex_w_done = 0; | |
caf0678c | 12119 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 12120 | |
ce518a5f | 12121 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 12122 | { |
55cf16e1 | 12123 | get_sib (info, sizeflag); |
252b5132 RH |
12124 | dofloat (sizeflag); |
12125 | } | |
12126 | else | |
12127 | { | |
8bb15339 | 12128 | dp = get_valid_dis386 (dp, info); |
b844680a | 12129 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12130 | { |
55cf16e1 | 12131 | get_sib (info, sizeflag); |
ce518a5f L |
12132 | for (i = 0; i < MAX_OPERANDS; ++i) |
12133 | { | |
246c51aa | 12134 | obufp = op_out[i]; |
ce518a5f L |
12135 | op_ad = MAX_OPERANDS - 1 - i; |
12136 | if (dp->op[i].rtn) | |
12137 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12138 | /* For EVEX instruction after the last operand masking |
12139 | should be printed. */ | |
12140 | if (i == 0 && vex.evex) | |
12141 | { | |
12142 | /* Don't print {%k0}. */ | |
12143 | if (vex.mask_register_specifier) | |
12144 | { | |
12145 | oappend ("{"); | |
12146 | oappend (names_mask[vex.mask_register_specifier]); | |
12147 | oappend ("}"); | |
12148 | } | |
12149 | if (vex.zeroing) | |
12150 | oappend ("{z}"); | |
12151 | } | |
ce518a5f | 12152 | } |
6439fc28 | 12153 | } |
252b5132 RH |
12154 | } |
12155 | ||
d869730d | 12156 | /* Check if the REX prefix is used. */ |
e2e6193d | 12157 | if (rex_ignored == 0 && (rex ^ rex_used) == 0 && last_rex_prefix >= 0) |
f16cd0d5 L |
12158 | all_prefixes[last_rex_prefix] = 0; |
12159 | ||
5e6718e4 | 12160 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12161 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12162 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12163 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12164 | all_prefixes[last_seg_prefix] = 0; |
12165 | ||
5e6718e4 | 12166 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12167 | if ((prefixes & PREFIX_ADDR) != 0 |
12168 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12169 | all_prefixes[last_addr_prefix] = 0; | |
12170 | ||
df18fdba L |
12171 | /* Check if the DATA prefix is used. */ |
12172 | if ((prefixes & PREFIX_DATA) != 0 | |
12173 | && (used_prefixes & PREFIX_DATA) != 0) | |
12174 | all_prefixes[last_data_prefix] = 0; | |
f16cd0d5 | 12175 | |
df18fdba | 12176 | /* Print the extra prefixes. */ |
f16cd0d5 | 12177 | prefix_length = 0; |
f310f33d | 12178 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12179 | if (all_prefixes[i]) |
12180 | { | |
12181 | const char *name; | |
df18fdba | 12182 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12183 | if (name == NULL) |
12184 | abort (); | |
12185 | prefix_length += strlen (name) + 1; | |
12186 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12187 | } | |
b844680a | 12188 | |
285ca992 L |
12189 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12190 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12191 | used by putop and MMX/SSE operand and may be overriden by the | |
12192 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12193 | separately. */ | |
3888916d | 12194 | if (dp->prefix_requirement == PREFIX_OPCODE |
285ca992 L |
12195 | && dp != &bad_opcode |
12196 | && (((prefixes | |
12197 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0 | |
12198 | && (used_prefixes | |
12199 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
12200 | || ((((prefixes | |
12201 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12202 | == PREFIX_DATA) | |
12203 | && (used_prefixes & PREFIX_DATA) == 0)))) | |
12204 | { | |
12205 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12206 | return end_codep - priv.the_buffer; | |
12207 | } | |
12208 | ||
f16cd0d5 L |
12209 | /* Check maximum code length. */ |
12210 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12211 | { | |
12212 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12213 | return MAX_CODE_LENGTH; | |
12214 | } | |
b844680a | 12215 | |
ea397f5b | 12216 | obufp = mnemonicendp; |
f16cd0d5 | 12217 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12218 | oappend (" "); |
12219 | oappend (" "); | |
12220 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12221 | ||
12222 | /* The enter and bound instructions are printed with operands in the same | |
12223 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12224 | if (intel_syntax || two_source_ops) |
252b5132 | 12225 | { |
185b1163 L |
12226 | bfd_vma riprel; |
12227 | ||
ce518a5f | 12228 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12229 | op_txt[i] = op_out[i]; |
246c51aa | 12230 | |
3a8547d2 JB |
12231 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12232 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12233 | { | |
12234 | op_txt[2] = op_out[3]; | |
12235 | op_txt[3] = op_out[2]; | |
12236 | } | |
12237 | ||
ce518a5f L |
12238 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12239 | { | |
6c067bbb RM |
12240 | op_ad = op_index[i]; |
12241 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12242 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12243 | riprel = op_riprel[i]; |
12244 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12245 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12246 | } |
252b5132 RH |
12247 | } |
12248 | else | |
12249 | { | |
ce518a5f | 12250 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12251 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12252 | } |
12253 | ||
ce518a5f L |
12254 | needcomma = 0; |
12255 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12256 | if (*op_txt[i]) | |
12257 | { | |
12258 | if (needcomma) | |
12259 | (*info->fprintf_func) (info->stream, ","); | |
12260 | if (op_index[i] != -1 && !op_riprel[i]) | |
12261 | (*info->print_address_func) ((bfd_vma) op_address[op_index[i]], info); | |
12262 | else | |
12263 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12264 | needcomma = 1; | |
12265 | } | |
050dfa73 | 12266 | |
ce518a5f | 12267 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12268 | if (op_index[i] != -1 && op_riprel[i]) |
12269 | { | |
12270 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12271 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12272 | + op_address[op_index[i]]), info); |
185b1163 | 12273 | break; |
52b15da3 | 12274 | } |
e396998b | 12275 | return codep - priv.the_buffer; |
252b5132 RH |
12276 | } |
12277 | ||
6439fc28 | 12278 | static const char *float_mem[] = { |
252b5132 | 12279 | /* d8 */ |
7c52e0e8 L |
12280 | "fadd{s|}", |
12281 | "fmul{s|}", | |
12282 | "fcom{s|}", | |
12283 | "fcomp{s|}", | |
12284 | "fsub{s|}", | |
12285 | "fsubr{s|}", | |
12286 | "fdiv{s|}", | |
12287 | "fdivr{s|}", | |
db6eb5be | 12288 | /* d9 */ |
7c52e0e8 | 12289 | "fld{s|}", |
252b5132 | 12290 | "(bad)", |
7c52e0e8 L |
12291 | "fst{s|}", |
12292 | "fstp{s|}", | |
9306ca4a | 12293 | "fldenvIC", |
252b5132 | 12294 | "fldcw", |
9306ca4a | 12295 | "fNstenvIC", |
252b5132 RH |
12296 | "fNstcw", |
12297 | /* da */ | |
7c52e0e8 L |
12298 | "fiadd{l|}", |
12299 | "fimul{l|}", | |
12300 | "ficom{l|}", | |
12301 | "ficomp{l|}", | |
12302 | "fisub{l|}", | |
12303 | "fisubr{l|}", | |
12304 | "fidiv{l|}", | |
12305 | "fidivr{l|}", | |
252b5132 | 12306 | /* db */ |
7c52e0e8 L |
12307 | "fild{l|}", |
12308 | "fisttp{l|}", | |
12309 | "fist{l|}", | |
12310 | "fistp{l|}", | |
252b5132 | 12311 | "(bad)", |
6439fc28 | 12312 | "fld{t||t|}", |
252b5132 | 12313 | "(bad)", |
6439fc28 | 12314 | "fstp{t||t|}", |
252b5132 | 12315 | /* dc */ |
7c52e0e8 L |
12316 | "fadd{l|}", |
12317 | "fmul{l|}", | |
12318 | "fcom{l|}", | |
12319 | "fcomp{l|}", | |
12320 | "fsub{l|}", | |
12321 | "fsubr{l|}", | |
12322 | "fdiv{l|}", | |
12323 | "fdivr{l|}", | |
252b5132 | 12324 | /* dd */ |
7c52e0e8 L |
12325 | "fld{l|}", |
12326 | "fisttp{ll|}", | |
12327 | "fst{l||}", | |
12328 | "fstp{l|}", | |
9306ca4a | 12329 | "frstorIC", |
252b5132 | 12330 | "(bad)", |
9306ca4a | 12331 | "fNsaveIC", |
252b5132 RH |
12332 | "fNstsw", |
12333 | /* de */ | |
ac465521 JB |
12334 | "fiadd{s|}", |
12335 | "fimul{s|}", | |
12336 | "ficom{s|}", | |
12337 | "ficomp{s|}", | |
12338 | "fisub{s|}", | |
12339 | "fisubr{s|}", | |
12340 | "fidiv{s|}", | |
12341 | "fidivr{s|}", | |
252b5132 | 12342 | /* df */ |
ac465521 JB |
12343 | "fild{s|}", |
12344 | "fisttp{s|}", | |
12345 | "fist{s|}", | |
12346 | "fistp{s|}", | |
252b5132 | 12347 | "fbld", |
7c52e0e8 | 12348 | "fild{ll|}", |
252b5132 | 12349 | "fbstp", |
7c52e0e8 | 12350 | "fistp{ll|}", |
1d9f512f AM |
12351 | }; |
12352 | ||
12353 | static const unsigned char float_mem_mode[] = { | |
12354 | /* d8 */ | |
12355 | d_mode, | |
12356 | d_mode, | |
12357 | d_mode, | |
12358 | d_mode, | |
12359 | d_mode, | |
12360 | d_mode, | |
12361 | d_mode, | |
12362 | d_mode, | |
12363 | /* d9 */ | |
12364 | d_mode, | |
12365 | 0, | |
12366 | d_mode, | |
12367 | d_mode, | |
12368 | 0, | |
12369 | w_mode, | |
12370 | 0, | |
12371 | w_mode, | |
12372 | /* da */ | |
12373 | d_mode, | |
12374 | d_mode, | |
12375 | d_mode, | |
12376 | d_mode, | |
12377 | d_mode, | |
12378 | d_mode, | |
12379 | d_mode, | |
12380 | d_mode, | |
12381 | /* db */ | |
12382 | d_mode, | |
12383 | d_mode, | |
12384 | d_mode, | |
12385 | d_mode, | |
12386 | 0, | |
9306ca4a | 12387 | t_mode, |
1d9f512f | 12388 | 0, |
9306ca4a | 12389 | t_mode, |
1d9f512f AM |
12390 | /* dc */ |
12391 | q_mode, | |
12392 | q_mode, | |
12393 | q_mode, | |
12394 | q_mode, | |
12395 | q_mode, | |
12396 | q_mode, | |
12397 | q_mode, | |
12398 | q_mode, | |
12399 | /* dd */ | |
12400 | q_mode, | |
12401 | q_mode, | |
12402 | q_mode, | |
12403 | q_mode, | |
12404 | 0, | |
12405 | 0, | |
12406 | 0, | |
12407 | w_mode, | |
12408 | /* de */ | |
12409 | w_mode, | |
12410 | w_mode, | |
12411 | w_mode, | |
12412 | w_mode, | |
12413 | w_mode, | |
12414 | w_mode, | |
12415 | w_mode, | |
12416 | w_mode, | |
12417 | /* df */ | |
12418 | w_mode, | |
12419 | w_mode, | |
12420 | w_mode, | |
12421 | w_mode, | |
9306ca4a | 12422 | t_mode, |
1d9f512f | 12423 | q_mode, |
9306ca4a | 12424 | t_mode, |
1d9f512f | 12425 | q_mode |
252b5132 RH |
12426 | }; |
12427 | ||
ce518a5f L |
12428 | #define ST { OP_ST, 0 } |
12429 | #define STi { OP_STi, 0 } | |
252b5132 | 12430 | |
48c97fa1 L |
12431 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12432 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12433 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12434 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12435 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12436 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12437 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12438 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12439 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12440 | |
2da11e11 | 12441 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12442 | /* d8 */ |
12443 | { | |
bf890a93 IT |
12444 | { "fadd", { ST, STi }, 0 }, |
12445 | { "fmul", { ST, STi }, 0 }, | |
12446 | { "fcom", { STi }, 0 }, | |
12447 | { "fcomp", { STi }, 0 }, | |
12448 | { "fsub", { ST, STi }, 0 }, | |
12449 | { "fsubr", { ST, STi }, 0 }, | |
12450 | { "fdiv", { ST, STi }, 0 }, | |
12451 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12452 | }, |
12453 | /* d9 */ | |
12454 | { | |
bf890a93 IT |
12455 | { "fld", { STi }, 0 }, |
12456 | { "fxch", { STi }, 0 }, | |
252b5132 | 12457 | { FGRPd9_2 }, |
592d1631 | 12458 | { Bad_Opcode }, |
252b5132 RH |
12459 | { FGRPd9_4 }, |
12460 | { FGRPd9_5 }, | |
12461 | { FGRPd9_6 }, | |
12462 | { FGRPd9_7 }, | |
12463 | }, | |
12464 | /* da */ | |
12465 | { | |
bf890a93 IT |
12466 | { "fcmovb", { ST, STi }, 0 }, |
12467 | { "fcmove", { ST, STi }, 0 }, | |
12468 | { "fcmovbe",{ ST, STi }, 0 }, | |
12469 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12470 | { Bad_Opcode }, |
252b5132 | 12471 | { FGRPda_5 }, |
592d1631 L |
12472 | { Bad_Opcode }, |
12473 | { Bad_Opcode }, | |
252b5132 RH |
12474 | }, |
12475 | /* db */ | |
12476 | { | |
bf890a93 IT |
12477 | { "fcmovnb",{ ST, STi }, 0 }, |
12478 | { "fcmovne",{ ST, STi }, 0 }, | |
12479 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12480 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12481 | { FGRPdb_4 }, |
bf890a93 IT |
12482 | { "fucomi", { ST, STi }, 0 }, |
12483 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12484 | { Bad_Opcode }, |
252b5132 RH |
12485 | }, |
12486 | /* dc */ | |
12487 | { | |
bf890a93 IT |
12488 | { "fadd", { STi, ST }, 0 }, |
12489 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12490 | { Bad_Opcode }, |
12491 | { Bad_Opcode }, | |
d53e6b98 JB |
12492 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12493 | { "fsub{M|}", { STi, ST }, 0 }, | |
12494 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12495 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12496 | }, |
12497 | /* dd */ | |
12498 | { | |
bf890a93 | 12499 | { "ffree", { STi }, 0 }, |
592d1631 | 12500 | { Bad_Opcode }, |
bf890a93 IT |
12501 | { "fst", { STi }, 0 }, |
12502 | { "fstp", { STi }, 0 }, | |
12503 | { "fucom", { STi }, 0 }, | |
12504 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12505 | { Bad_Opcode }, |
12506 | { Bad_Opcode }, | |
252b5132 RH |
12507 | }, |
12508 | /* de */ | |
12509 | { | |
bf890a93 IT |
12510 | { "faddp", { STi, ST }, 0 }, |
12511 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12512 | { Bad_Opcode }, |
252b5132 | 12513 | { FGRPde_3 }, |
d53e6b98 JB |
12514 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12515 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12516 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12517 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12518 | }, |
12519 | /* df */ | |
12520 | { | |
bf890a93 | 12521 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12522 | { Bad_Opcode }, |
12523 | { Bad_Opcode }, | |
12524 | { Bad_Opcode }, | |
252b5132 | 12525 | { FGRPdf_4 }, |
bf890a93 IT |
12526 | { "fucomip", { ST, STi }, 0 }, |
12527 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12528 | { Bad_Opcode }, |
252b5132 RH |
12529 | }, |
12530 | }; | |
12531 | ||
252b5132 | 12532 | static char *fgrps[][8] = { |
48c97fa1 L |
12533 | /* Bad opcode 0 */ |
12534 | { | |
12535 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12536 | }, | |
12537 | ||
12538 | /* d9_2 1 */ | |
252b5132 RH |
12539 | { |
12540 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12541 | }, | |
12542 | ||
48c97fa1 | 12543 | /* d9_4 2 */ |
252b5132 RH |
12544 | { |
12545 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12546 | }, | |
12547 | ||
48c97fa1 | 12548 | /* d9_5 3 */ |
252b5132 RH |
12549 | { |
12550 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12551 | }, | |
12552 | ||
48c97fa1 | 12553 | /* d9_6 4 */ |
252b5132 RH |
12554 | { |
12555 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12556 | }, | |
12557 | ||
48c97fa1 | 12558 | /* d9_7 5 */ |
252b5132 RH |
12559 | { |
12560 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12561 | }, | |
12562 | ||
48c97fa1 | 12563 | /* da_5 6 */ |
252b5132 RH |
12564 | { |
12565 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12566 | }, | |
12567 | ||
48c97fa1 | 12568 | /* db_4 7 */ |
252b5132 | 12569 | { |
309d3373 JB |
12570 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12571 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12572 | }, |
12573 | ||
48c97fa1 | 12574 | /* de_3 8 */ |
252b5132 RH |
12575 | { |
12576 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12577 | }, | |
12578 | ||
48c97fa1 | 12579 | /* df_4 9 */ |
252b5132 RH |
12580 | { |
12581 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12582 | }, | |
12583 | }; | |
12584 | ||
b6169b20 L |
12585 | static void |
12586 | swap_operand (void) | |
12587 | { | |
12588 | mnemonicendp[0] = '.'; | |
12589 | mnemonicendp[1] = 's'; | |
12590 | mnemonicendp += 2; | |
12591 | } | |
12592 | ||
b844680a L |
12593 | static void |
12594 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12595 | int sizeflag ATTRIBUTE_UNUSED) | |
12596 | { | |
12597 | /* Skip mod/rm byte. */ | |
12598 | MODRM_CHECK; | |
12599 | codep++; | |
12600 | } | |
12601 | ||
252b5132 | 12602 | static void |
26ca5450 | 12603 | dofloat (int sizeflag) |
252b5132 | 12604 | { |
2da11e11 | 12605 | const struct dis386 *dp; |
252b5132 RH |
12606 | unsigned char floatop; |
12607 | ||
12608 | floatop = codep[-1]; | |
12609 | ||
7967e09e | 12610 | if (modrm.mod != 3) |
252b5132 | 12611 | { |
7967e09e | 12612 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12613 | |
12614 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12615 | obufp = op_out[0]; |
6e50d963 | 12616 | op_ad = 2; |
1d9f512f | 12617 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12618 | return; |
12619 | } | |
6608db57 | 12620 | /* Skip mod/rm byte. */ |
4bba6815 | 12621 | MODRM_CHECK; |
252b5132 RH |
12622 | codep++; |
12623 | ||
7967e09e | 12624 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12625 | if (dp->name == NULL) |
12626 | { | |
7967e09e | 12627 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12628 | |
6608db57 | 12629 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12630 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12631 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12632 | } |
12633 | else | |
12634 | { | |
12635 | putop (dp->name, sizeflag); | |
12636 | ||
ce518a5f | 12637 | obufp = op_out[0]; |
6e50d963 | 12638 | op_ad = 2; |
ce518a5f L |
12639 | if (dp->op[0].rtn) |
12640 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12641 | |
ce518a5f | 12642 | obufp = op_out[1]; |
6e50d963 | 12643 | op_ad = 1; |
ce518a5f L |
12644 | if (dp->op[1].rtn) |
12645 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12646 | } |
12647 | } | |
12648 | ||
9ce09ba2 RM |
12649 | /* Like oappend (below), but S is a string starting with '%'. |
12650 | In Intel syntax, the '%' is elided. */ | |
12651 | static void | |
12652 | oappend_maybe_intel (const char *s) | |
12653 | { | |
12654 | oappend (s + intel_syntax); | |
12655 | } | |
12656 | ||
252b5132 | 12657 | static void |
26ca5450 | 12658 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12659 | { |
9ce09ba2 | 12660 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12661 | } |
12662 | ||
252b5132 | 12663 | static void |
26ca5450 | 12664 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12665 | { |
7967e09e | 12666 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12667 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12668 | } |
12669 | ||
6608db57 | 12670 | /* Capital letters in template are macros. */ |
6439fc28 | 12671 | static int |
d3ce72d0 | 12672 | putop (const char *in_template, int sizeflag) |
252b5132 | 12673 | { |
2da11e11 | 12674 | const char *p; |
9306ca4a | 12675 | int alt = 0; |
9d141669 | 12676 | int cond = 1; |
98b528ac L |
12677 | unsigned int l = 0, len = 1; |
12678 | char last[4]; | |
12679 | ||
12680 | #define SAVE_LAST(c) \ | |
12681 | if (l < len && l < sizeof (last)) \ | |
12682 | last[l++] = c; \ | |
12683 | else \ | |
12684 | abort (); | |
252b5132 | 12685 | |
d3ce72d0 | 12686 | for (p = in_template; *p; p++) |
252b5132 RH |
12687 | { |
12688 | switch (*p) | |
12689 | { | |
12690 | default: | |
12691 | *obufp++ = *p; | |
12692 | break; | |
98b528ac L |
12693 | case '%': |
12694 | len++; | |
12695 | break; | |
9d141669 L |
12696 | case '!': |
12697 | cond = 0; | |
12698 | break; | |
6439fc28 | 12699 | case '{': |
6439fc28 | 12700 | if (intel_syntax) |
6439fc28 AM |
12701 | { |
12702 | while (*++p != '|') | |
7c52e0e8 L |
12703 | if (*p == '}' || *p == '\0') |
12704 | abort (); | |
6439fc28 | 12705 | } |
9306ca4a JB |
12706 | /* Fall through. */ |
12707 | case 'I': | |
12708 | alt = 1; | |
12709 | continue; | |
6439fc28 AM |
12710 | case '|': |
12711 | while (*++p != '}') | |
12712 | { | |
12713 | if (*p == '\0') | |
12714 | abort (); | |
12715 | } | |
12716 | break; | |
12717 | case '}': | |
12718 | break; | |
252b5132 | 12719 | case 'A': |
db6eb5be AM |
12720 | if (intel_syntax) |
12721 | break; | |
7967e09e | 12722 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12723 | *obufp++ = 'b'; |
12724 | break; | |
12725 | case 'B': | |
4b06377f L |
12726 | if (l == 0 && len == 1) |
12727 | { | |
12728 | case_B: | |
12729 | if (intel_syntax) | |
12730 | break; | |
12731 | if (sizeflag & SUFFIX_ALWAYS) | |
12732 | *obufp++ = 'b'; | |
12733 | } | |
12734 | else | |
12735 | { | |
12736 | if (l != 1 | |
12737 | || len != 2 | |
12738 | || last[0] != 'L') | |
12739 | { | |
12740 | SAVE_LAST (*p); | |
12741 | break; | |
12742 | } | |
12743 | ||
12744 | if (address_mode == mode_64bit | |
12745 | && !(prefixes & PREFIX_ADDR)) | |
12746 | { | |
12747 | *obufp++ = 'a'; | |
12748 | *obufp++ = 'b'; | |
12749 | *obufp++ = 's'; | |
12750 | } | |
12751 | ||
12752 | goto case_B; | |
12753 | } | |
252b5132 | 12754 | break; |
9306ca4a JB |
12755 | case 'C': |
12756 | if (intel_syntax && !alt) | |
12757 | break; | |
12758 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12759 | { | |
12760 | if (sizeflag & DFLAG) | |
12761 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12762 | else | |
12763 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12764 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12765 | } | |
12766 | break; | |
ed7841b3 JB |
12767 | case 'D': |
12768 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12769 | break; | |
161a04f6 | 12770 | USED_REX (REX_W); |
7967e09e | 12771 | if (modrm.mod == 3) |
ed7841b3 | 12772 | { |
161a04f6 | 12773 | if (rex & REX_W) |
ed7841b3 | 12774 | *obufp++ = 'q'; |
ed7841b3 | 12775 | else |
f16cd0d5 L |
12776 | { |
12777 | if (sizeflag & DFLAG) | |
12778 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12779 | else | |
12780 | *obufp++ = 'w'; | |
12781 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12782 | } | |
ed7841b3 JB |
12783 | } |
12784 | else | |
12785 | *obufp++ = 'w'; | |
12786 | break; | |
252b5132 | 12787 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12788 | if (address_mode == mode_64bit) |
c1a64871 JH |
12789 | { |
12790 | if (sizeflag & AFLAG) | |
12791 | *obufp++ = 'r'; | |
12792 | else | |
12793 | *obufp++ = 'e'; | |
12794 | } | |
12795 | else | |
12796 | if (sizeflag & AFLAG) | |
12797 | *obufp++ = 'e'; | |
3ffd33cf AM |
12798 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12799 | break; | |
12800 | case 'F': | |
db6eb5be AM |
12801 | if (intel_syntax) |
12802 | break; | |
e396998b | 12803 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12804 | { |
12805 | if (sizeflag & AFLAG) | |
cb712a9e | 12806 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12807 | else |
cb712a9e | 12808 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12809 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12810 | } | |
252b5132 | 12811 | break; |
52fd6d94 JB |
12812 | case 'G': |
12813 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12814 | break; | |
161a04f6 | 12815 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12816 | *obufp++ = 'l'; |
12817 | else | |
12818 | *obufp++ = 'w'; | |
161a04f6 | 12819 | if (!(rex & REX_W)) |
52fd6d94 JB |
12820 | used_prefixes |= (prefixes & PREFIX_DATA); |
12821 | break; | |
5dd0794d | 12822 | case 'H': |
db6eb5be AM |
12823 | if (intel_syntax) |
12824 | break; | |
5dd0794d AM |
12825 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12826 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12827 | { | |
12828 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12829 | *obufp++ = ','; | |
12830 | *obufp++ = 'p'; | |
12831 | if (prefixes & PREFIX_DS) | |
12832 | *obufp++ = 't'; | |
12833 | else | |
12834 | *obufp++ = 'n'; | |
12835 | } | |
12836 | break; | |
9306ca4a JB |
12837 | case 'J': |
12838 | if (intel_syntax) | |
12839 | break; | |
12840 | *obufp++ = 'l'; | |
12841 | break; | |
42903f7f L |
12842 | case 'K': |
12843 | USED_REX (REX_W); | |
12844 | if (rex & REX_W) | |
12845 | *obufp++ = 'q'; | |
12846 | else | |
12847 | *obufp++ = 'd'; | |
12848 | break; | |
6dd5059a | 12849 | case 'Z': |
04d824a4 JB |
12850 | if (l != 0 || len != 1) |
12851 | { | |
12852 | if (l != 1 || len != 2 || last[0] != 'X') | |
12853 | { | |
12854 | SAVE_LAST (*p); | |
12855 | break; | |
12856 | } | |
12857 | if (!need_vex || !vex.evex) | |
12858 | abort (); | |
12859 | if (intel_syntax | |
12860 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12861 | break; | |
12862 | switch (vex.length) | |
12863 | { | |
12864 | case 128: | |
12865 | *obufp++ = 'x'; | |
12866 | break; | |
12867 | case 256: | |
12868 | *obufp++ = 'y'; | |
12869 | break; | |
12870 | case 512: | |
12871 | *obufp++ = 'z'; | |
12872 | break; | |
12873 | default: | |
12874 | abort (); | |
12875 | } | |
12876 | break; | |
12877 | } | |
6dd5059a L |
12878 | if (intel_syntax) |
12879 | break; | |
12880 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12881 | { | |
12882 | *obufp++ = 'q'; | |
12883 | break; | |
12884 | } | |
12885 | /* Fall through. */ | |
98b528ac | 12886 | goto case_L; |
252b5132 | 12887 | case 'L': |
98b528ac L |
12888 | if (l != 0 || len != 1) |
12889 | { | |
12890 | SAVE_LAST (*p); | |
12891 | break; | |
12892 | } | |
12893 | case_L: | |
db6eb5be AM |
12894 | if (intel_syntax) |
12895 | break; | |
252b5132 RH |
12896 | if (sizeflag & SUFFIX_ALWAYS) |
12897 | *obufp++ = 'l'; | |
252b5132 | 12898 | break; |
9d141669 L |
12899 | case 'M': |
12900 | if (intel_mnemonic != cond) | |
12901 | *obufp++ = 'r'; | |
12902 | break; | |
252b5132 RH |
12903 | case 'N': |
12904 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12905 | *obufp++ = 'n'; | |
7d421014 ILT |
12906 | else |
12907 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12908 | break; |
52b15da3 | 12909 | case 'O': |
161a04f6 L |
12910 | USED_REX (REX_W); |
12911 | if (rex & REX_W) | |
6439fc28 | 12912 | *obufp++ = 'o'; |
a35ca55a JB |
12913 | else if (intel_syntax && (sizeflag & DFLAG)) |
12914 | *obufp++ = 'q'; | |
52b15da3 JH |
12915 | else |
12916 | *obufp++ = 'd'; | |
161a04f6 | 12917 | if (!(rex & REX_W)) |
a35ca55a | 12918 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12919 | break; |
07f5af7d L |
12920 | case '&': |
12921 | if (!intel_syntax | |
12922 | && address_mode == mode_64bit | |
12923 | && isa64 == intel64) | |
12924 | { | |
12925 | *obufp++ = 'q'; | |
12926 | break; | |
12927 | } | |
12928 | /* Fall through. */ | |
6439fc28 | 12929 | case 'T': |
d9e3625e L |
12930 | if (!intel_syntax |
12931 | && address_mode == mode_64bit | |
7bb15c6f | 12932 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12933 | { |
12934 | *obufp++ = 'q'; | |
12935 | break; | |
12936 | } | |
6608db57 | 12937 | /* Fall through. */ |
4b4c407a | 12938 | goto case_P; |
252b5132 | 12939 | case 'P': |
4b4c407a | 12940 | if (l == 0 && len == 1) |
d9e3625e | 12941 | { |
4b4c407a L |
12942 | case_P: |
12943 | if (intel_syntax) | |
d9e3625e | 12944 | { |
4b4c407a L |
12945 | if ((rex & REX_W) == 0 |
12946 | && (prefixes & PREFIX_DATA)) | |
12947 | { | |
12948 | if ((sizeflag & DFLAG) == 0) | |
12949 | *obufp++ = 'w'; | |
12950 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12951 | } | |
12952 | break; | |
12953 | } | |
12954 | if ((prefixes & PREFIX_DATA) | |
12955 | || (rex & REX_W) | |
12956 | || (sizeflag & SUFFIX_ALWAYS)) | |
12957 | { | |
12958 | USED_REX (REX_W); | |
12959 | if (rex & REX_W) | |
12960 | *obufp++ = 'q'; | |
12961 | else | |
12962 | { | |
12963 | if (sizeflag & DFLAG) | |
12964 | *obufp++ = 'l'; | |
12965 | else | |
12966 | *obufp++ = 'w'; | |
12967 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12968 | } | |
d9e3625e | 12969 | } |
d9e3625e | 12970 | } |
4b4c407a | 12971 | else |
252b5132 | 12972 | { |
4b4c407a L |
12973 | if (l != 1 || len != 2 || last[0] != 'L') |
12974 | { | |
12975 | SAVE_LAST (*p); | |
12976 | break; | |
12977 | } | |
12978 | ||
12979 | if ((prefixes & PREFIX_DATA) | |
12980 | || (rex & REX_W) | |
12981 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12982 | { |
4b4c407a L |
12983 | USED_REX (REX_W); |
12984 | if (rex & REX_W) | |
12985 | *obufp++ = 'q'; | |
12986 | else | |
12987 | { | |
12988 | if (sizeflag & DFLAG) | |
12989 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12990 | else | |
12991 | *obufp++ = 'w'; | |
12992 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12993 | } | |
52b15da3 | 12994 | } |
252b5132 RH |
12995 | } |
12996 | break; | |
6439fc28 | 12997 | case 'U': |
db6eb5be AM |
12998 | if (intel_syntax) |
12999 | break; | |
7bb15c6f | 13000 | if (address_mode == mode_64bit |
6c067bbb | 13001 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 13002 | { |
7967e09e | 13003 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 13004 | *obufp++ = 'q'; |
6439fc28 AM |
13005 | break; |
13006 | } | |
6608db57 | 13007 | /* Fall through. */ |
98b528ac | 13008 | goto case_Q; |
252b5132 | 13009 | case 'Q': |
98b528ac | 13010 | if (l == 0 && len == 1) |
252b5132 | 13011 | { |
98b528ac L |
13012 | case_Q: |
13013 | if (intel_syntax && !alt) | |
13014 | break; | |
13015 | USED_REX (REX_W); | |
13016 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 13017 | { |
98b528ac L |
13018 | if (rex & REX_W) |
13019 | *obufp++ = 'q'; | |
52b15da3 | 13020 | else |
98b528ac L |
13021 | { |
13022 | if (sizeflag & DFLAG) | |
13023 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
13024 | else | |
13025 | *obufp++ = 'w'; | |
f16cd0d5 | 13026 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 13027 | } |
52b15da3 | 13028 | } |
98b528ac L |
13029 | } |
13030 | else | |
13031 | { | |
13032 | if (l != 1 || len != 2 || last[0] != 'L') | |
13033 | { | |
13034 | SAVE_LAST (*p); | |
13035 | break; | |
13036 | } | |
13037 | if (intel_syntax | |
13038 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) | |
13039 | break; | |
13040 | if ((rex & REX_W)) | |
13041 | { | |
13042 | USED_REX (REX_W); | |
13043 | *obufp++ = 'q'; | |
13044 | } | |
13045 | else | |
13046 | *obufp++ = 'l'; | |
252b5132 RH |
13047 | } |
13048 | break; | |
13049 | case 'R': | |
161a04f6 L |
13050 | USED_REX (REX_W); |
13051 | if (rex & REX_W) | |
a35ca55a JB |
13052 | *obufp++ = 'q'; |
13053 | else if (sizeflag & DFLAG) | |
c608c12e | 13054 | { |
a35ca55a | 13055 | if (intel_syntax) |
c608c12e | 13056 | *obufp++ = 'd'; |
c608c12e | 13057 | else |
a35ca55a | 13058 | *obufp++ = 'l'; |
c608c12e | 13059 | } |
252b5132 | 13060 | else |
a35ca55a JB |
13061 | *obufp++ = 'w'; |
13062 | if (intel_syntax && !p[1] | |
161a04f6 | 13063 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 13064 | *obufp++ = 'e'; |
161a04f6 | 13065 | if (!(rex & REX_W)) |
52b15da3 | 13066 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 13067 | break; |
1a114b12 | 13068 | case 'V': |
4b06377f | 13069 | if (l == 0 && len == 1) |
1a114b12 | 13070 | { |
4b06377f L |
13071 | if (intel_syntax) |
13072 | break; | |
7bb15c6f | 13073 | if (address_mode == mode_64bit |
6c067bbb | 13074 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
13075 | { |
13076 | if (sizeflag & SUFFIX_ALWAYS) | |
13077 | *obufp++ = 'q'; | |
13078 | break; | |
13079 | } | |
13080 | } | |
13081 | else | |
13082 | { | |
13083 | if (l != 1 | |
13084 | || len != 2 | |
13085 | || last[0] != 'L') | |
13086 | { | |
13087 | SAVE_LAST (*p); | |
13088 | break; | |
13089 | } | |
13090 | ||
13091 | if (rex & REX_W) | |
13092 | { | |
13093 | *obufp++ = 'a'; | |
13094 | *obufp++ = 'b'; | |
13095 | *obufp++ = 's'; | |
13096 | } | |
1a114b12 JB |
13097 | } |
13098 | /* Fall through. */ | |
4b06377f | 13099 | goto case_S; |
252b5132 | 13100 | case 'S': |
4b06377f | 13101 | if (l == 0 && len == 1) |
252b5132 | 13102 | { |
4b06377f L |
13103 | case_S: |
13104 | if (intel_syntax) | |
13105 | break; | |
13106 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13107 | { |
4b06377f L |
13108 | if (rex & REX_W) |
13109 | *obufp++ = 'q'; | |
52b15da3 | 13110 | else |
4b06377f L |
13111 | { |
13112 | if (sizeflag & DFLAG) | |
13113 | *obufp++ = 'l'; | |
13114 | else | |
13115 | *obufp++ = 'w'; | |
13116 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13117 | } | |
13118 | } | |
13119 | } | |
13120 | else | |
13121 | { | |
13122 | if (l != 1 | |
13123 | || len != 2 | |
13124 | || last[0] != 'L') | |
13125 | { | |
13126 | SAVE_LAST (*p); | |
13127 | break; | |
52b15da3 | 13128 | } |
4b06377f L |
13129 | |
13130 | if (address_mode == mode_64bit | |
13131 | && !(prefixes & PREFIX_ADDR)) | |
13132 | { | |
13133 | *obufp++ = 'a'; | |
13134 | *obufp++ = 'b'; | |
13135 | *obufp++ = 's'; | |
13136 | } | |
13137 | ||
13138 | goto case_S; | |
252b5132 | 13139 | } |
252b5132 | 13140 | break; |
041bd2e0 | 13141 | case 'X': |
c0f3af97 L |
13142 | if (l != 0 || len != 1) |
13143 | { | |
13144 | SAVE_LAST (*p); | |
13145 | break; | |
13146 | } | |
13147 | if (need_vex && vex.prefix) | |
13148 | { | |
13149 | if (vex.prefix == DATA_PREFIX_OPCODE) | |
13150 | *obufp++ = 'd'; | |
13151 | else | |
13152 | *obufp++ = 's'; | |
13153 | } | |
041bd2e0 | 13154 | else |
f16cd0d5 L |
13155 | { |
13156 | if (prefixes & PREFIX_DATA) | |
13157 | *obufp++ = 'd'; | |
13158 | else | |
13159 | *obufp++ = 's'; | |
13160 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13161 | } | |
041bd2e0 | 13162 | break; |
76f227a5 | 13163 | case 'Y': |
c0f3af97 | 13164 | if (l == 0 && len == 1) |
9646c87b | 13165 | abort (); |
c0f3af97 L |
13166 | else |
13167 | { | |
13168 | if (l != 1 || len != 2 || last[0] != 'X') | |
13169 | { | |
13170 | SAVE_LAST (*p); | |
13171 | break; | |
13172 | } | |
13173 | if (!need_vex) | |
13174 | abort (); | |
13175 | if (intel_syntax | |
04d824a4 | 13176 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13177 | break; |
13178 | switch (vex.length) | |
13179 | { | |
13180 | case 128: | |
13181 | *obufp++ = 'x'; | |
13182 | break; | |
13183 | case 256: | |
13184 | *obufp++ = 'y'; | |
13185 | break; | |
04d824a4 JB |
13186 | case 512: |
13187 | if (!vex.evex) | |
c0f3af97 | 13188 | default: |
04d824a4 | 13189 | abort (); |
c0f3af97 | 13190 | } |
76f227a5 JH |
13191 | } |
13192 | break; | |
252b5132 | 13193 | case 'W': |
0bfee649 | 13194 | if (l == 0 && len == 1) |
a35ca55a | 13195 | { |
0bfee649 L |
13196 | /* operand size flag for cwtl, cbtw */ |
13197 | USED_REX (REX_W); | |
13198 | if (rex & REX_W) | |
13199 | { | |
13200 | if (intel_syntax) | |
13201 | *obufp++ = 'd'; | |
13202 | else | |
13203 | *obufp++ = 'l'; | |
13204 | } | |
13205 | else if (sizeflag & DFLAG) | |
13206 | *obufp++ = 'w'; | |
a35ca55a | 13207 | else |
0bfee649 L |
13208 | *obufp++ = 'b'; |
13209 | if (!(rex & REX_W)) | |
13210 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13211 | } |
252b5132 | 13212 | else |
0bfee649 | 13213 | { |
6c30d220 L |
13214 | if (l != 1 |
13215 | || len != 2 | |
13216 | || (last[0] != 'X' | |
13217 | && last[0] != 'L')) | |
0bfee649 L |
13218 | { |
13219 | SAVE_LAST (*p); | |
13220 | break; | |
13221 | } | |
13222 | if (!need_vex) | |
13223 | abort (); | |
6c30d220 L |
13224 | if (last[0] == 'X') |
13225 | *obufp++ = vex.w ? 'd': 's'; | |
13226 | else | |
13227 | *obufp++ = vex.w ? 'q': 'd'; | |
0bfee649 | 13228 | } |
252b5132 | 13229 | break; |
a72d2af2 L |
13230 | case '^': |
13231 | if (intel_syntax) | |
13232 | break; | |
13233 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
13234 | { | |
13235 | if (sizeflag & DFLAG) | |
13236 | *obufp++ = 'l'; | |
13237 | else | |
13238 | *obufp++ = 'w'; | |
13239 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13240 | } | |
13241 | break; | |
5db04b09 L |
13242 | case '@': |
13243 | if (intel_syntax) | |
13244 | break; | |
13245 | if (address_mode == mode_64bit | |
13246 | && (isa64 == intel64 | |
13247 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13248 | *obufp++ = 'q'; | |
13249 | else if ((prefixes & PREFIX_DATA)) | |
13250 | { | |
13251 | if (!(sizeflag & DFLAG)) | |
13252 | *obufp++ = 'w'; | |
13253 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13254 | } | |
13255 | break; | |
252b5132 | 13256 | } |
9306ca4a | 13257 | alt = 0; |
252b5132 RH |
13258 | } |
13259 | *obufp = 0; | |
ea397f5b | 13260 | mnemonicendp = obufp; |
6439fc28 | 13261 | return 0; |
252b5132 RH |
13262 | } |
13263 | ||
13264 | static void | |
26ca5450 | 13265 | oappend (const char *s) |
252b5132 | 13266 | { |
ea397f5b | 13267 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13268 | } |
13269 | ||
13270 | static void | |
26ca5450 | 13271 | append_seg (void) |
252b5132 | 13272 | { |
285ca992 L |
13273 | /* Only print the active segment register. */ |
13274 | if (!active_seg_prefix) | |
13275 | return; | |
13276 | ||
13277 | used_prefixes |= active_seg_prefix; | |
13278 | switch (active_seg_prefix) | |
7d421014 | 13279 | { |
285ca992 | 13280 | case PREFIX_CS: |
9ce09ba2 | 13281 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13282 | break; |
13283 | case PREFIX_DS: | |
9ce09ba2 | 13284 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13285 | break; |
13286 | case PREFIX_SS: | |
9ce09ba2 | 13287 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13288 | break; |
13289 | case PREFIX_ES: | |
9ce09ba2 | 13290 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13291 | break; |
13292 | case PREFIX_FS: | |
9ce09ba2 | 13293 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13294 | break; |
13295 | case PREFIX_GS: | |
9ce09ba2 | 13296 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13297 | break; |
13298 | default: | |
13299 | break; | |
7d421014 | 13300 | } |
252b5132 RH |
13301 | } |
13302 | ||
13303 | static void | |
26ca5450 | 13304 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13305 | { |
13306 | if (!intel_syntax) | |
13307 | oappend ("*"); | |
13308 | OP_E (bytemode, sizeflag); | |
13309 | } | |
13310 | ||
52b15da3 | 13311 | static void |
26ca5450 | 13312 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13313 | { |
cb712a9e | 13314 | if (address_mode == mode_64bit) |
52b15da3 JH |
13315 | { |
13316 | if (hex) | |
13317 | { | |
13318 | char tmp[30]; | |
13319 | int i; | |
13320 | buf[0] = '0'; | |
13321 | buf[1] = 'x'; | |
13322 | sprintf_vma (tmp, disp); | |
6608db57 | 13323 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13324 | strcpy (buf + 2, tmp + i); |
13325 | } | |
13326 | else | |
13327 | { | |
13328 | bfd_signed_vma v = disp; | |
13329 | char tmp[30]; | |
13330 | int i; | |
13331 | if (v < 0) | |
13332 | { | |
13333 | *(buf++) = '-'; | |
13334 | v = -disp; | |
6608db57 | 13335 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13336 | if (v < 0) |
13337 | { | |
13338 | strcpy (buf, "9223372036854775808"); | |
13339 | return; | |
13340 | } | |
13341 | } | |
13342 | if (!v) | |
13343 | { | |
13344 | strcpy (buf, "0"); | |
13345 | return; | |
13346 | } | |
13347 | ||
13348 | i = 0; | |
13349 | tmp[29] = 0; | |
13350 | while (v) | |
13351 | { | |
6608db57 | 13352 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13353 | v /= 10; |
13354 | i++; | |
13355 | } | |
13356 | strcpy (buf, tmp + 29 - i); | |
13357 | } | |
13358 | } | |
13359 | else | |
13360 | { | |
13361 | if (hex) | |
13362 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13363 | else | |
13364 | sprintf (buf, "%d", (int) disp); | |
13365 | } | |
13366 | } | |
13367 | ||
5d669648 L |
13368 | /* Put DISP in BUF as signed hex number. */ |
13369 | ||
13370 | static void | |
13371 | print_displacement (char *buf, bfd_vma disp) | |
13372 | { | |
13373 | bfd_signed_vma val = disp; | |
13374 | char tmp[30]; | |
13375 | int i, j = 0; | |
13376 | ||
13377 | if (val < 0) | |
13378 | { | |
13379 | buf[j++] = '-'; | |
13380 | val = -disp; | |
13381 | ||
13382 | /* Check for possible overflow. */ | |
13383 | if (val < 0) | |
13384 | { | |
13385 | switch (address_mode) | |
13386 | { | |
13387 | case mode_64bit: | |
13388 | strcpy (buf + j, "0x8000000000000000"); | |
13389 | break; | |
13390 | case mode_32bit: | |
13391 | strcpy (buf + j, "0x80000000"); | |
13392 | break; | |
13393 | case mode_16bit: | |
13394 | strcpy (buf + j, "0x8000"); | |
13395 | break; | |
13396 | } | |
13397 | return; | |
13398 | } | |
13399 | } | |
13400 | ||
13401 | buf[j++] = '0'; | |
13402 | buf[j++] = 'x'; | |
13403 | ||
0af1713e | 13404 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13405 | for (i = 0; tmp[i] == '0'; i++) |
13406 | continue; | |
13407 | if (tmp[i] == '\0') | |
13408 | i--; | |
13409 | strcpy (buf + j, tmp + i); | |
13410 | } | |
13411 | ||
3f31e633 JB |
13412 | static void |
13413 | intel_operand_size (int bytemode, int sizeflag) | |
13414 | { | |
43234a1e L |
13415 | if (vex.evex |
13416 | && vex.b | |
13417 | && (bytemode == x_mode | |
13418 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13419 | { | |
13420 | if (vex.w) | |
13421 | oappend ("QWORD PTR "); | |
13422 | else | |
13423 | oappend ("DWORD PTR "); | |
13424 | return; | |
13425 | } | |
3f31e633 JB |
13426 | switch (bytemode) |
13427 | { | |
13428 | case b_mode: | |
b6169b20 | 13429 | case b_swap_mode: |
42903f7f | 13430 | case dqb_mode: |
1ba585e8 | 13431 | case db_mode: |
3f31e633 JB |
13432 | oappend ("BYTE PTR "); |
13433 | break; | |
13434 | case w_mode: | |
1ba585e8 | 13435 | case dw_mode: |
3f31e633 JB |
13436 | case dqw_mode: |
13437 | oappend ("WORD PTR "); | |
13438 | break; | |
07f5af7d L |
13439 | case indir_v_mode: |
13440 | if (address_mode == mode_64bit && isa64 == intel64) | |
13441 | { | |
13442 | oappend ("QWORD PTR "); | |
13443 | break; | |
13444 | } | |
1a0670f3 | 13445 | /* Fall through. */ |
1a114b12 | 13446 | case stack_v_mode: |
7bb15c6f | 13447 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13448 | { |
13449 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13450 | break; |
13451 | } | |
1a0670f3 | 13452 | /* Fall through. */ |
3f31e633 | 13453 | case v_mode: |
b6169b20 | 13454 | case v_swap_mode: |
3f31e633 | 13455 | case dq_mode: |
161a04f6 L |
13456 | USED_REX (REX_W); |
13457 | if (rex & REX_W) | |
3f31e633 | 13458 | oappend ("QWORD PTR "); |
3f31e633 | 13459 | else |
f16cd0d5 L |
13460 | { |
13461 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13462 | oappend ("DWORD PTR "); | |
13463 | else | |
13464 | oappend ("WORD PTR "); | |
13465 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13466 | } | |
3f31e633 | 13467 | break; |
52fd6d94 | 13468 | case z_mode: |
161a04f6 | 13469 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13470 | *obufp++ = 'D'; |
13471 | oappend ("WORD PTR "); | |
161a04f6 | 13472 | if (!(rex & REX_W)) |
52fd6d94 JB |
13473 | used_prefixes |= (prefixes & PREFIX_DATA); |
13474 | break; | |
34b772a6 JB |
13475 | case a_mode: |
13476 | if (sizeflag & DFLAG) | |
13477 | oappend ("QWORD PTR "); | |
13478 | else | |
13479 | oappend ("DWORD PTR "); | |
13480 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13481 | break; | |
3f31e633 | 13482 | case d_mode: |
539f890d L |
13483 | case d_scalar_mode: |
13484 | case d_scalar_swap_mode: | |
fa99fab2 | 13485 | case d_swap_mode: |
42903f7f | 13486 | case dqd_mode: |
3f31e633 JB |
13487 | oappend ("DWORD PTR "); |
13488 | break; | |
13489 | case q_mode: | |
539f890d L |
13490 | case q_scalar_mode: |
13491 | case q_scalar_swap_mode: | |
b6169b20 | 13492 | case q_swap_mode: |
3f31e633 JB |
13493 | oappend ("QWORD PTR "); |
13494 | break; | |
d20dee9e | 13495 | case dqa_mode: |
3f31e633 | 13496 | case m_mode: |
cb712a9e | 13497 | if (address_mode == mode_64bit) |
3f31e633 JB |
13498 | oappend ("QWORD PTR "); |
13499 | else | |
13500 | oappend ("DWORD PTR "); | |
13501 | break; | |
13502 | case f_mode: | |
13503 | if (sizeflag & DFLAG) | |
13504 | oappend ("FWORD PTR "); | |
13505 | else | |
13506 | oappend ("DWORD PTR "); | |
13507 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13508 | break; | |
13509 | case t_mode: | |
13510 | oappend ("TBYTE PTR "); | |
13511 | break; | |
13512 | case x_mode: | |
b6169b20 | 13513 | case x_swap_mode: |
43234a1e L |
13514 | case evex_x_gscat_mode: |
13515 | case evex_x_nobcst_mode: | |
53467f57 IT |
13516 | case b_scalar_mode: |
13517 | case w_scalar_mode: | |
c0f3af97 L |
13518 | if (need_vex) |
13519 | { | |
13520 | switch (vex.length) | |
13521 | { | |
13522 | case 128: | |
13523 | oappend ("XMMWORD PTR "); | |
13524 | break; | |
13525 | case 256: | |
13526 | oappend ("YMMWORD PTR "); | |
13527 | break; | |
43234a1e L |
13528 | case 512: |
13529 | oappend ("ZMMWORD PTR "); | |
13530 | break; | |
c0f3af97 L |
13531 | default: |
13532 | abort (); | |
13533 | } | |
13534 | } | |
13535 | else | |
13536 | oappend ("XMMWORD PTR "); | |
13537 | break; | |
13538 | case xmm_mode: | |
3f31e633 JB |
13539 | oappend ("XMMWORD PTR "); |
13540 | break; | |
43234a1e L |
13541 | case ymm_mode: |
13542 | oappend ("YMMWORD PTR "); | |
13543 | break; | |
c0f3af97 | 13544 | case xmmq_mode: |
43234a1e | 13545 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13546 | if (!need_vex) |
13547 | abort (); | |
13548 | ||
13549 | switch (vex.length) | |
13550 | { | |
13551 | case 128: | |
13552 | oappend ("QWORD PTR "); | |
13553 | break; | |
13554 | case 256: | |
13555 | oappend ("XMMWORD PTR "); | |
13556 | break; | |
43234a1e L |
13557 | case 512: |
13558 | oappend ("YMMWORD PTR "); | |
13559 | break; | |
c0f3af97 L |
13560 | default: |
13561 | abort (); | |
13562 | } | |
13563 | break; | |
6c30d220 L |
13564 | case xmm_mb_mode: |
13565 | if (!need_vex) | |
13566 | abort (); | |
13567 | ||
13568 | switch (vex.length) | |
13569 | { | |
13570 | case 128: | |
13571 | case 256: | |
43234a1e | 13572 | case 512: |
6c30d220 L |
13573 | oappend ("BYTE PTR "); |
13574 | break; | |
13575 | default: | |
13576 | abort (); | |
13577 | } | |
13578 | break; | |
13579 | case xmm_mw_mode: | |
13580 | if (!need_vex) | |
13581 | abort (); | |
13582 | ||
13583 | switch (vex.length) | |
13584 | { | |
13585 | case 128: | |
13586 | case 256: | |
43234a1e | 13587 | case 512: |
6c30d220 L |
13588 | oappend ("WORD PTR "); |
13589 | break; | |
13590 | default: | |
13591 | abort (); | |
13592 | } | |
13593 | break; | |
13594 | case xmm_md_mode: | |
13595 | if (!need_vex) | |
13596 | abort (); | |
13597 | ||
13598 | switch (vex.length) | |
13599 | { | |
13600 | case 128: | |
13601 | case 256: | |
43234a1e | 13602 | case 512: |
6c30d220 L |
13603 | oappend ("DWORD PTR "); |
13604 | break; | |
13605 | default: | |
13606 | abort (); | |
13607 | } | |
13608 | break; | |
13609 | case xmm_mq_mode: | |
13610 | if (!need_vex) | |
13611 | abort (); | |
13612 | ||
13613 | switch (vex.length) | |
13614 | { | |
13615 | case 128: | |
13616 | case 256: | |
43234a1e | 13617 | case 512: |
6c30d220 L |
13618 | oappend ("QWORD PTR "); |
13619 | break; | |
13620 | default: | |
13621 | abort (); | |
13622 | } | |
13623 | break; | |
13624 | case xmmdw_mode: | |
13625 | if (!need_vex) | |
13626 | abort (); | |
13627 | ||
13628 | switch (vex.length) | |
13629 | { | |
13630 | case 128: | |
13631 | oappend ("WORD PTR "); | |
13632 | break; | |
13633 | case 256: | |
13634 | oappend ("DWORD PTR "); | |
13635 | break; | |
43234a1e L |
13636 | case 512: |
13637 | oappend ("QWORD PTR "); | |
13638 | break; | |
6c30d220 L |
13639 | default: |
13640 | abort (); | |
13641 | } | |
13642 | break; | |
13643 | case xmmqd_mode: | |
13644 | if (!need_vex) | |
13645 | abort (); | |
13646 | ||
13647 | switch (vex.length) | |
13648 | { | |
13649 | case 128: | |
13650 | oappend ("DWORD PTR "); | |
13651 | break; | |
13652 | case 256: | |
13653 | oappend ("QWORD PTR "); | |
13654 | break; | |
43234a1e L |
13655 | case 512: |
13656 | oappend ("XMMWORD PTR "); | |
13657 | break; | |
6c30d220 L |
13658 | default: |
13659 | abort (); | |
13660 | } | |
13661 | break; | |
c0f3af97 L |
13662 | case ymmq_mode: |
13663 | if (!need_vex) | |
13664 | abort (); | |
13665 | ||
13666 | switch (vex.length) | |
13667 | { | |
13668 | case 128: | |
13669 | oappend ("QWORD PTR "); | |
13670 | break; | |
13671 | case 256: | |
13672 | oappend ("YMMWORD PTR "); | |
13673 | break; | |
43234a1e L |
13674 | case 512: |
13675 | oappend ("ZMMWORD PTR "); | |
13676 | break; | |
c0f3af97 L |
13677 | default: |
13678 | abort (); | |
13679 | } | |
13680 | break; | |
6c30d220 L |
13681 | case ymmxmm_mode: |
13682 | if (!need_vex) | |
13683 | abort (); | |
13684 | ||
13685 | switch (vex.length) | |
13686 | { | |
13687 | case 128: | |
13688 | case 256: | |
13689 | oappend ("XMMWORD PTR "); | |
13690 | break; | |
13691 | default: | |
13692 | abort (); | |
13693 | } | |
13694 | break; | |
fb9c77c7 L |
13695 | case o_mode: |
13696 | oappend ("OWORD PTR "); | |
13697 | break; | |
43234a1e | 13698 | case xmm_mdq_mode: |
0bfee649 | 13699 | case vex_w_dq_mode: |
1c480963 | 13700 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13701 | if (!need_vex) |
13702 | abort (); | |
13703 | ||
13704 | if (vex.w) | |
13705 | oappend ("QWORD PTR "); | |
13706 | else | |
13707 | oappend ("DWORD PTR "); | |
13708 | break; | |
43234a1e L |
13709 | case vex_vsib_d_w_dq_mode: |
13710 | case vex_vsib_q_w_dq_mode: | |
13711 | if (!need_vex) | |
13712 | abort (); | |
13713 | ||
13714 | if (!vex.evex) | |
13715 | { | |
13716 | if (vex.w) | |
13717 | oappend ("QWORD PTR "); | |
13718 | else | |
13719 | oappend ("DWORD PTR "); | |
13720 | } | |
13721 | else | |
13722 | { | |
b28d1bda IT |
13723 | switch (vex.length) |
13724 | { | |
13725 | case 128: | |
13726 | oappend ("XMMWORD PTR "); | |
13727 | break; | |
13728 | case 256: | |
13729 | oappend ("YMMWORD PTR "); | |
13730 | break; | |
13731 | case 512: | |
13732 | oappend ("ZMMWORD PTR "); | |
13733 | break; | |
13734 | default: | |
13735 | abort (); | |
13736 | } | |
43234a1e L |
13737 | } |
13738 | break; | |
5fc35d96 IT |
13739 | case vex_vsib_q_w_d_mode: |
13740 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13741 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13742 | abort (); |
13743 | ||
b28d1bda IT |
13744 | switch (vex.length) |
13745 | { | |
13746 | case 128: | |
13747 | oappend ("QWORD PTR "); | |
13748 | break; | |
13749 | case 256: | |
13750 | oappend ("XMMWORD PTR "); | |
13751 | break; | |
13752 | case 512: | |
13753 | oappend ("YMMWORD PTR "); | |
13754 | break; | |
13755 | default: | |
13756 | abort (); | |
13757 | } | |
5fc35d96 IT |
13758 | |
13759 | break; | |
1ba585e8 IT |
13760 | case mask_bd_mode: |
13761 | if (!need_vex || vex.length != 128) | |
13762 | abort (); | |
13763 | if (vex.w) | |
13764 | oappend ("DWORD PTR "); | |
13765 | else | |
13766 | oappend ("BYTE PTR "); | |
13767 | break; | |
43234a1e L |
13768 | case mask_mode: |
13769 | if (!need_vex) | |
13770 | abort (); | |
1ba585e8 IT |
13771 | if (vex.w) |
13772 | oappend ("QWORD PTR "); | |
13773 | else | |
13774 | oappend ("WORD PTR "); | |
43234a1e | 13775 | break; |
6c75cc62 | 13776 | case v_bnd_mode: |
d276ec69 | 13777 | case v_bndmk_mode: |
3f31e633 JB |
13778 | default: |
13779 | break; | |
13780 | } | |
13781 | } | |
13782 | ||
252b5132 | 13783 | static void |
c0f3af97 | 13784 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13785 | { |
c0f3af97 L |
13786 | int reg = modrm.rm; |
13787 | const char **names; | |
252b5132 | 13788 | |
c0f3af97 L |
13789 | USED_REX (REX_B); |
13790 | if ((rex & REX_B)) | |
13791 | reg += 8; | |
252b5132 | 13792 | |
b6169b20 | 13793 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13794 | && (bytemode == b_swap_mode |
9f79e886 | 13795 | || bytemode == bnd_swap_mode |
60227d64 | 13796 | || bytemode == v_swap_mode)) |
b6169b20 L |
13797 | swap_operand (); |
13798 | ||
c0f3af97 | 13799 | switch (bytemode) |
252b5132 | 13800 | { |
c0f3af97 | 13801 | case b_mode: |
b6169b20 | 13802 | case b_swap_mode: |
c0f3af97 L |
13803 | USED_REX (0); |
13804 | if (rex) | |
13805 | names = names8rex; | |
13806 | else | |
13807 | names = names8; | |
13808 | break; | |
13809 | case w_mode: | |
13810 | names = names16; | |
13811 | break; | |
13812 | case d_mode: | |
1ba585e8 IT |
13813 | case dw_mode: |
13814 | case db_mode: | |
c0f3af97 L |
13815 | names = names32; |
13816 | break; | |
13817 | case q_mode: | |
13818 | names = names64; | |
13819 | break; | |
13820 | case m_mode: | |
6c75cc62 | 13821 | case v_bnd_mode: |
c0f3af97 L |
13822 | names = address_mode == mode_64bit ? names64 : names32; |
13823 | break; | |
7e8b059b | 13824 | case bnd_mode: |
9f79e886 | 13825 | case bnd_swap_mode: |
0d96e4df L |
13826 | if (reg > 0x3) |
13827 | { | |
13828 | oappend ("(bad)"); | |
13829 | return; | |
13830 | } | |
7e8b059b L |
13831 | names = names_bnd; |
13832 | break; | |
07f5af7d L |
13833 | case indir_v_mode: |
13834 | if (address_mode == mode_64bit && isa64 == intel64) | |
13835 | { | |
13836 | names = names64; | |
13837 | break; | |
13838 | } | |
1a0670f3 | 13839 | /* Fall through. */ |
c0f3af97 | 13840 | case stack_v_mode: |
7bb15c6f | 13841 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13842 | { |
c0f3af97 | 13843 | names = names64; |
252b5132 | 13844 | break; |
252b5132 | 13845 | } |
c0f3af97 | 13846 | bytemode = v_mode; |
1a0670f3 | 13847 | /* Fall through. */ |
c0f3af97 | 13848 | case v_mode: |
b6169b20 | 13849 | case v_swap_mode: |
c0f3af97 L |
13850 | case dq_mode: |
13851 | case dqb_mode: | |
13852 | case dqd_mode: | |
13853 | case dqw_mode: | |
d20dee9e | 13854 | case dqa_mode: |
c0f3af97 L |
13855 | USED_REX (REX_W); |
13856 | if (rex & REX_W) | |
13857 | names = names64; | |
c0f3af97 | 13858 | else |
f16cd0d5 | 13859 | { |
7bb15c6f | 13860 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13861 | || (bytemode != v_mode |
13862 | && bytemode != v_swap_mode)) | |
13863 | names = names32; | |
13864 | else | |
13865 | names = names16; | |
13866 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13867 | } | |
c0f3af97 | 13868 | break; |
de89d0a3 IT |
13869 | case va_mode: |
13870 | names = (address_mode == mode_64bit | |
13871 | ? names64 : names32); | |
13872 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13873 | names = (address_mode == mode_16bit |
13874 | ? names16 : names); | |
de89d0a3 IT |
13875 | else |
13876 | { | |
13877 | /* Remove "addr16/addr32". */ | |
13878 | all_prefixes[last_addr_prefix] = 0; | |
13879 | names = (address_mode != mode_32bit | |
13880 | ? names32 : names16); | |
13881 | used_prefixes |= PREFIX_ADDR; | |
13882 | } | |
13883 | break; | |
1ba585e8 | 13884 | case mask_bd_mode: |
43234a1e | 13885 | case mask_mode: |
9889cbb1 L |
13886 | if (reg > 0x7) |
13887 | { | |
13888 | oappend ("(bad)"); | |
13889 | return; | |
13890 | } | |
43234a1e L |
13891 | names = names_mask; |
13892 | break; | |
c0f3af97 L |
13893 | case 0: |
13894 | return; | |
13895 | default: | |
13896 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13897 | return; |
13898 | } | |
c0f3af97 L |
13899 | oappend (names[reg]); |
13900 | } | |
13901 | ||
13902 | static void | |
c1e679ec | 13903 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13904 | { |
13905 | bfd_vma disp = 0; | |
13906 | int add = (rex & REX_B) ? 8 : 0; | |
13907 | int riprel = 0; | |
43234a1e L |
13908 | int shift; |
13909 | ||
13910 | if (vex.evex) | |
13911 | { | |
13912 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13913 | if (vex.b | |
13914 | && bytemode != x_mode | |
90a915bf | 13915 | && bytemode != xmmq_mode |
43234a1e L |
13916 | && bytemode != evex_half_bcst_xmmq_mode) |
13917 | { | |
13918 | BadOp (); | |
13919 | return; | |
13920 | } | |
13921 | switch (bytemode) | |
13922 | { | |
1ba585e8 IT |
13923 | case dqw_mode: |
13924 | case dw_mode: | |
1ba585e8 IT |
13925 | shift = 1; |
13926 | break; | |
13927 | case dqb_mode: | |
13928 | case db_mode: | |
13929 | shift = 0; | |
13930 | break; | |
b50c9f31 JB |
13931 | case dq_mode: |
13932 | if (address_mode != mode_64bit) | |
13933 | { | |
13934 | shift = 2; | |
13935 | break; | |
13936 | } | |
13937 | /* fall through */ | |
43234a1e | 13938 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13939 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13940 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13941 | case vex_vsib_q_w_d_mode: |
43234a1e L |
13942 | case evex_x_gscat_mode: |
13943 | case xmm_mdq_mode: | |
13944 | shift = vex.w ? 3 : 2; | |
13945 | break; | |
43234a1e L |
13946 | case x_mode: |
13947 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13948 | case xmmq_mode: |
43234a1e L |
13949 | if (vex.b) |
13950 | { | |
13951 | shift = vex.w ? 3 : 2; | |
13952 | break; | |
13953 | } | |
1a0670f3 | 13954 | /* Fall through. */ |
43234a1e L |
13955 | case xmmqd_mode: |
13956 | case xmmdw_mode: | |
43234a1e L |
13957 | case ymmq_mode: |
13958 | case evex_x_nobcst_mode: | |
13959 | case x_swap_mode: | |
13960 | switch (vex.length) | |
13961 | { | |
13962 | case 128: | |
13963 | shift = 4; | |
13964 | break; | |
13965 | case 256: | |
13966 | shift = 5; | |
13967 | break; | |
13968 | case 512: | |
13969 | shift = 6; | |
13970 | break; | |
13971 | default: | |
13972 | abort (); | |
13973 | } | |
13974 | break; | |
13975 | case ymm_mode: | |
13976 | shift = 5; | |
13977 | break; | |
13978 | case xmm_mode: | |
13979 | shift = 4; | |
13980 | break; | |
13981 | case xmm_mq_mode: | |
13982 | case q_mode: | |
13983 | case q_scalar_mode: | |
13984 | case q_swap_mode: | |
13985 | case q_scalar_swap_mode: | |
13986 | shift = 3; | |
13987 | break; | |
13988 | case dqd_mode: | |
13989 | case xmm_md_mode: | |
13990 | case d_mode: | |
13991 | case d_scalar_mode: | |
13992 | case d_swap_mode: | |
13993 | case d_scalar_swap_mode: | |
13994 | shift = 2; | |
13995 | break; | |
5074ad8a | 13996 | case w_scalar_mode: |
43234a1e L |
13997 | case xmm_mw_mode: |
13998 | shift = 1; | |
13999 | break; | |
5074ad8a | 14000 | case b_scalar_mode: |
43234a1e L |
14001 | case xmm_mb_mode: |
14002 | shift = 0; | |
14003 | break; | |
d20dee9e L |
14004 | case dqa_mode: |
14005 | shift = address_mode == mode_64bit ? 3 : 2; | |
14006 | break; | |
43234a1e L |
14007 | default: |
14008 | abort (); | |
14009 | } | |
14010 | /* Make necessary corrections to shift for modes that need it. | |
14011 | For these modes we currently have shift 4, 5 or 6 depending on | |
14012 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
14013 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
14014 | xmmq_mode). In case of broadcast enabled the corrections | |
14015 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
14016 | if (!vex.b |
14017 | && (bytemode == xmmq_mode | |
14018 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
14019 | shift -= 1; |
14020 | else if (bytemode == xmmqd_mode) | |
14021 | shift -= 2; | |
14022 | else if (bytemode == xmmdw_mode) | |
14023 | shift -= 3; | |
b28d1bda IT |
14024 | else if (bytemode == ymmq_mode && vex.length == 128) |
14025 | shift -= 1; | |
43234a1e L |
14026 | } |
14027 | else | |
14028 | shift = 0; | |
252b5132 | 14029 | |
c0f3af97 | 14030 | USED_REX (REX_B); |
3f31e633 JB |
14031 | if (intel_syntax) |
14032 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14033 | append_seg (); |
14034 | ||
5d669648 | 14035 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 14036 | { |
5d669648 L |
14037 | /* 32/64 bit address mode */ |
14038 | int havedisp; | |
252b5132 RH |
14039 | int havesib; |
14040 | int havebase; | |
0f7da397 | 14041 | int haveindex; |
20afcfb7 | 14042 | int needindex; |
1bc60e56 | 14043 | int needaddr32; |
82c18208 | 14044 | int base, rbase; |
91d6fa6a | 14045 | int vindex = 0; |
252b5132 | 14046 | int scale = 0; |
7e8b059b L |
14047 | int addr32flag = !((sizeflag & AFLAG) |
14048 | || bytemode == v_bnd_mode | |
d276ec69 | 14049 | || bytemode == v_bndmk_mode |
9f79e886 JB |
14050 | || bytemode == bnd_mode |
14051 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
14052 | const char **indexes64 = names64; |
14053 | const char **indexes32 = names32; | |
252b5132 RH |
14054 | |
14055 | havesib = 0; | |
14056 | havebase = 1; | |
0f7da397 | 14057 | haveindex = 0; |
7967e09e | 14058 | base = modrm.rm; |
252b5132 RH |
14059 | |
14060 | if (base == 4) | |
14061 | { | |
14062 | havesib = 1; | |
dfc8cf43 | 14063 | vindex = sib.index; |
161a04f6 L |
14064 | USED_REX (REX_X); |
14065 | if (rex & REX_X) | |
91d6fa6a | 14066 | vindex += 8; |
6c30d220 L |
14067 | switch (bytemode) |
14068 | { | |
14069 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 14070 | case vex_vsib_d_w_d_mode: |
6c30d220 | 14071 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 14072 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
14073 | if (!need_vex) |
14074 | abort (); | |
43234a1e L |
14075 | if (vex.evex) |
14076 | { | |
14077 | if (!vex.v) | |
14078 | vindex += 16; | |
14079 | } | |
6c30d220 L |
14080 | |
14081 | haveindex = 1; | |
14082 | switch (vex.length) | |
14083 | { | |
14084 | case 128: | |
7bb15c6f | 14085 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
14086 | break; |
14087 | case 256: | |
5fc35d96 IT |
14088 | if (!vex.w |
14089 | || bytemode == vex_vsib_q_w_dq_mode | |
14090 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 14091 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 14092 | else |
7bb15c6f | 14093 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14094 | break; |
43234a1e | 14095 | case 512: |
5fc35d96 IT |
14096 | if (!vex.w |
14097 | || bytemode == vex_vsib_q_w_dq_mode | |
14098 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14099 | indexes64 = indexes32 = names_zmm; |
14100 | else | |
14101 | indexes64 = indexes32 = names_ymm; | |
14102 | break; | |
6c30d220 L |
14103 | default: |
14104 | abort (); | |
14105 | } | |
14106 | break; | |
14107 | default: | |
14108 | haveindex = vindex != 4; | |
14109 | break; | |
14110 | } | |
14111 | scale = sib.scale; | |
14112 | base = sib.base; | |
252b5132 RH |
14113 | codep++; |
14114 | } | |
82c18208 | 14115 | rbase = base + add; |
252b5132 | 14116 | |
7967e09e | 14117 | switch (modrm.mod) |
252b5132 RH |
14118 | { |
14119 | case 0: | |
82c18208 | 14120 | if (base == 5) |
252b5132 RH |
14121 | { |
14122 | havebase = 0; | |
cb712a9e | 14123 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14124 | riprel = 1; |
14125 | disp = get32s (); | |
d276ec69 JB |
14126 | if (riprel && bytemode == v_bndmk_mode) |
14127 | { | |
14128 | oappend ("(bad)"); | |
14129 | return; | |
14130 | } | |
252b5132 RH |
14131 | } |
14132 | break; | |
14133 | case 1: | |
14134 | FETCH_DATA (the_info, codep + 1); | |
14135 | disp = *codep++; | |
14136 | if ((disp & 0x80) != 0) | |
14137 | disp -= 0x100; | |
43234a1e L |
14138 | if (vex.evex && shift > 0) |
14139 | disp <<= shift; | |
252b5132 RH |
14140 | break; |
14141 | case 2: | |
52b15da3 | 14142 | disp = get32s (); |
252b5132 RH |
14143 | break; |
14144 | } | |
14145 | ||
1bc60e56 L |
14146 | needindex = 0; |
14147 | needaddr32 = 0; | |
14148 | if (havesib | |
14149 | && !havebase | |
14150 | && !haveindex | |
14151 | && address_mode != mode_16bit) | |
14152 | { | |
14153 | if (address_mode == mode_64bit) | |
14154 | { | |
14155 | /* Display eiz instead of addr32. */ | |
14156 | needindex = addr32flag; | |
14157 | needaddr32 = 1; | |
14158 | } | |
14159 | else | |
14160 | { | |
14161 | /* In 32-bit mode, we need index register to tell [offset] | |
14162 | from [eiz*1 + offset]. */ | |
14163 | needindex = 1; | |
14164 | } | |
14165 | } | |
14166 | ||
20afcfb7 L |
14167 | havedisp = (havebase |
14168 | || needindex | |
14169 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14170 | |
252b5132 | 14171 | if (!intel_syntax) |
82c18208 | 14172 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14173 | { |
5d669648 L |
14174 | if (havedisp || riprel) |
14175 | print_displacement (scratchbuf, disp); | |
14176 | else | |
14177 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14178 | oappend (scratchbuf); |
52b15da3 JH |
14179 | if (riprel) |
14180 | { | |
14181 | set_op (disp, 1); | |
28596323 | 14182 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14183 | } |
db6eb5be | 14184 | } |
2da11e11 | 14185 | |
1bc60e56 | 14186 | if ((havebase || haveindex || needaddr32 || riprel) |
7e8b059b | 14187 | && (bytemode != v_bnd_mode) |
d276ec69 | 14188 | && (bytemode != v_bndmk_mode) |
9f79e886 JB |
14189 | && (bytemode != bnd_mode) |
14190 | && (bytemode != bnd_swap_mode)) | |
87767711 JB |
14191 | used_prefixes |= PREFIX_ADDR; |
14192 | ||
5d669648 | 14193 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14194 | { |
252b5132 | 14195 | *obufp++ = open_char; |
52b15da3 | 14196 | if (intel_syntax && riprel) |
185b1163 L |
14197 | { |
14198 | set_op (disp, 1); | |
28596323 | 14199 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14200 | } |
db6eb5be | 14201 | *obufp = '\0'; |
252b5132 | 14202 | if (havebase) |
7e8b059b | 14203 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14204 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14205 | if (havesib) |
14206 | { | |
db51cc60 L |
14207 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14208 | print index to tell base + index from base. */ | |
14209 | if (scale != 0 | |
20afcfb7 | 14210 | || needindex |
db51cc60 L |
14211 | || haveindex |
14212 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14213 | { |
9306ca4a | 14214 | if (!intel_syntax || havebase) |
db6eb5be | 14215 | { |
9306ca4a JB |
14216 | *obufp++ = separator_char; |
14217 | *obufp = '\0'; | |
db6eb5be | 14218 | } |
db51cc60 | 14219 | if (haveindex) |
7e8b059b | 14220 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14221 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14222 | else |
7e8b059b | 14223 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14224 | ? index64 : index32); |
14225 | ||
db6eb5be AM |
14226 | *obufp++ = scale_char; |
14227 | *obufp = '\0'; | |
14228 | sprintf (scratchbuf, "%d", 1 << scale); | |
14229 | oappend (scratchbuf); | |
14230 | } | |
252b5132 | 14231 | } |
185b1163 | 14232 | if (intel_syntax |
82c18208 | 14233 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14234 | { |
db51cc60 | 14235 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14236 | { |
14237 | *obufp++ = '+'; | |
14238 | *obufp = '\0'; | |
14239 | } | |
05203043 | 14240 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14241 | { |
14242 | *obufp++ = '-'; | |
14243 | *obufp = '\0'; | |
14244 | disp = - (bfd_signed_vma) disp; | |
14245 | } | |
14246 | ||
db51cc60 L |
14247 | if (havedisp) |
14248 | print_displacement (scratchbuf, disp); | |
14249 | else | |
14250 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14251 | oappend (scratchbuf); |
14252 | } | |
252b5132 RH |
14253 | |
14254 | *obufp++ = close_char; | |
db6eb5be | 14255 | *obufp = '\0'; |
252b5132 RH |
14256 | } |
14257 | else if (intel_syntax) | |
db6eb5be | 14258 | { |
82c18208 | 14259 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14260 | { |
285ca992 | 14261 | if (!active_seg_prefix) |
252b5132 | 14262 | { |
d708bcba | 14263 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14264 | oappend (":"); |
14265 | } | |
52b15da3 | 14266 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14267 | oappend (scratchbuf); |
14268 | } | |
14269 | } | |
252b5132 RH |
14270 | } |
14271 | else | |
f16cd0d5 L |
14272 | { |
14273 | /* 16 bit address mode */ | |
14274 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14275 | switch (modrm.mod) |
252b5132 RH |
14276 | { |
14277 | case 0: | |
7967e09e | 14278 | if (modrm.rm == 6) |
252b5132 RH |
14279 | { |
14280 | disp = get16 (); | |
14281 | if ((disp & 0x8000) != 0) | |
14282 | disp -= 0x10000; | |
14283 | } | |
14284 | break; | |
14285 | case 1: | |
14286 | FETCH_DATA (the_info, codep + 1); | |
14287 | disp = *codep++; | |
14288 | if ((disp & 0x80) != 0) | |
14289 | disp -= 0x100; | |
65f3ed04 JB |
14290 | if (vex.evex && shift > 0) |
14291 | disp <<= shift; | |
252b5132 RH |
14292 | break; |
14293 | case 2: | |
14294 | disp = get16 (); | |
14295 | if ((disp & 0x8000) != 0) | |
14296 | disp -= 0x10000; | |
14297 | break; | |
14298 | } | |
14299 | ||
14300 | if (!intel_syntax) | |
7967e09e | 14301 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14302 | { |
5d669648 | 14303 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14304 | oappend (scratchbuf); |
14305 | } | |
252b5132 | 14306 | |
7967e09e | 14307 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14308 | { |
14309 | *obufp++ = open_char; | |
db6eb5be | 14310 | *obufp = '\0'; |
7967e09e | 14311 | oappend (index16[modrm.rm]); |
5d669648 L |
14312 | if (intel_syntax |
14313 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14314 | { |
5d669648 | 14315 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14316 | { |
14317 | *obufp++ = '+'; | |
14318 | *obufp = '\0'; | |
14319 | } | |
7967e09e | 14320 | else if (modrm.mod != 1) |
3d456fa1 JB |
14321 | { |
14322 | *obufp++ = '-'; | |
14323 | *obufp = '\0'; | |
14324 | disp = - (bfd_signed_vma) disp; | |
14325 | } | |
14326 | ||
5d669648 | 14327 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14328 | oappend (scratchbuf); |
14329 | } | |
14330 | ||
db6eb5be AM |
14331 | *obufp++ = close_char; |
14332 | *obufp = '\0'; | |
252b5132 | 14333 | } |
3d456fa1 JB |
14334 | else if (intel_syntax) |
14335 | { | |
285ca992 | 14336 | if (!active_seg_prefix) |
3d456fa1 JB |
14337 | { |
14338 | oappend (names_seg[ds_reg - es_reg]); | |
14339 | oappend (":"); | |
14340 | } | |
14341 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14342 | oappend (scratchbuf); | |
14343 | } | |
252b5132 | 14344 | } |
43234a1e L |
14345 | if (vex.evex && vex.b |
14346 | && (bytemode == x_mode | |
90a915bf | 14347 | || bytemode == xmmq_mode |
43234a1e L |
14348 | || bytemode == evex_half_bcst_xmmq_mode)) |
14349 | { | |
90a915bf IT |
14350 | if (vex.w |
14351 | || bytemode == xmmq_mode | |
14352 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14353 | { |
14354 | switch (vex.length) | |
14355 | { | |
14356 | case 128: | |
14357 | oappend ("{1to2}"); | |
14358 | break; | |
14359 | case 256: | |
14360 | oappend ("{1to4}"); | |
14361 | break; | |
14362 | case 512: | |
14363 | oappend ("{1to8}"); | |
14364 | break; | |
14365 | default: | |
14366 | abort (); | |
14367 | } | |
14368 | } | |
43234a1e | 14369 | else |
b28d1bda IT |
14370 | { |
14371 | switch (vex.length) | |
14372 | { | |
14373 | case 128: | |
14374 | oappend ("{1to4}"); | |
14375 | break; | |
14376 | case 256: | |
14377 | oappend ("{1to8}"); | |
14378 | break; | |
14379 | case 512: | |
14380 | oappend ("{1to16}"); | |
14381 | break; | |
14382 | default: | |
14383 | abort (); | |
14384 | } | |
14385 | } | |
43234a1e | 14386 | } |
252b5132 RH |
14387 | } |
14388 | ||
c0f3af97 | 14389 | static void |
8b3f93e7 | 14390 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14391 | { |
14392 | /* Skip mod/rm byte. */ | |
14393 | MODRM_CHECK; | |
14394 | codep++; | |
14395 | ||
14396 | if (modrm.mod == 3) | |
14397 | OP_E_register (bytemode, sizeflag); | |
14398 | else | |
c1e679ec | 14399 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14400 | } |
14401 | ||
252b5132 | 14402 | static void |
26ca5450 | 14403 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14404 | { |
52b15da3 | 14405 | int add = 0; |
c0a30a9f | 14406 | const char **names; |
161a04f6 L |
14407 | USED_REX (REX_R); |
14408 | if (rex & REX_R) | |
52b15da3 | 14409 | add += 8; |
252b5132 RH |
14410 | switch (bytemode) |
14411 | { | |
14412 | case b_mode: | |
52b15da3 JH |
14413 | USED_REX (0); |
14414 | if (rex) | |
7967e09e | 14415 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14416 | else |
7967e09e | 14417 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14418 | break; |
14419 | case w_mode: | |
7967e09e | 14420 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14421 | break; |
14422 | case d_mode: | |
1ba585e8 IT |
14423 | case db_mode: |
14424 | case dw_mode: | |
7967e09e | 14425 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14426 | break; |
14427 | case q_mode: | |
7967e09e | 14428 | oappend (names64[modrm.reg + add]); |
252b5132 | 14429 | break; |
7e8b059b | 14430 | case bnd_mode: |
0d96e4df L |
14431 | if (modrm.reg > 0x3) |
14432 | { | |
14433 | oappend ("(bad)"); | |
14434 | return; | |
14435 | } | |
7e8b059b L |
14436 | oappend (names_bnd[modrm.reg]); |
14437 | break; | |
252b5132 | 14438 | case v_mode: |
9306ca4a | 14439 | case dq_mode: |
42903f7f L |
14440 | case dqb_mode: |
14441 | case dqd_mode: | |
9306ca4a | 14442 | case dqw_mode: |
161a04f6 L |
14443 | USED_REX (REX_W); |
14444 | if (rex & REX_W) | |
7967e09e | 14445 | oappend (names64[modrm.reg + add]); |
252b5132 | 14446 | else |
f16cd0d5 L |
14447 | { |
14448 | if ((sizeflag & DFLAG) || bytemode != v_mode) | |
14449 | oappend (names32[modrm.reg + add]); | |
14450 | else | |
14451 | oappend (names16[modrm.reg + add]); | |
14452 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14453 | } | |
252b5132 | 14454 | break; |
c0a30a9f L |
14455 | case va_mode: |
14456 | names = (address_mode == mode_64bit | |
14457 | ? names64 : names32); | |
14458 | if (!(prefixes & PREFIX_ADDR)) | |
14459 | { | |
14460 | if (address_mode == mode_16bit) | |
14461 | names = names16; | |
14462 | } | |
14463 | else | |
14464 | { | |
14465 | /* Remove "addr16/addr32". */ | |
14466 | all_prefixes[last_addr_prefix] = 0; | |
14467 | names = (address_mode != mode_32bit | |
14468 | ? names32 : names16); | |
14469 | used_prefixes |= PREFIX_ADDR; | |
14470 | } | |
14471 | oappend (names[modrm.reg + add]); | |
14472 | break; | |
90700ea2 | 14473 | case m_mode: |
cb712a9e | 14474 | if (address_mode == mode_64bit) |
7967e09e | 14475 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14476 | else |
7967e09e | 14477 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14478 | break; |
1ba585e8 | 14479 | case mask_bd_mode: |
43234a1e | 14480 | case mask_mode: |
9889cbb1 L |
14481 | if ((modrm.reg + add) > 0x7) |
14482 | { | |
14483 | oappend ("(bad)"); | |
14484 | return; | |
14485 | } | |
43234a1e L |
14486 | oappend (names_mask[modrm.reg + add]); |
14487 | break; | |
252b5132 RH |
14488 | default: |
14489 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14490 | break; | |
14491 | } | |
14492 | } | |
14493 | ||
52b15da3 | 14494 | static bfd_vma |
26ca5450 | 14495 | get64 (void) |
52b15da3 | 14496 | { |
5dd0794d | 14497 | bfd_vma x; |
52b15da3 | 14498 | #ifdef BFD64 |
5dd0794d AM |
14499 | unsigned int a; |
14500 | unsigned int b; | |
14501 | ||
52b15da3 JH |
14502 | FETCH_DATA (the_info, codep + 8); |
14503 | a = *codep++ & 0xff; | |
14504 | a |= (*codep++ & 0xff) << 8; | |
14505 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14506 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14507 | b = *codep++ & 0xff; |
52b15da3 JH |
14508 | b |= (*codep++ & 0xff) << 8; |
14509 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14510 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14511 | x = a + ((bfd_vma) b << 32); |
14512 | #else | |
6608db57 | 14513 | abort (); |
5dd0794d | 14514 | x = 0; |
52b15da3 JH |
14515 | #endif |
14516 | return x; | |
14517 | } | |
14518 | ||
14519 | static bfd_signed_vma | |
26ca5450 | 14520 | get32 (void) |
252b5132 | 14521 | { |
52b15da3 | 14522 | bfd_signed_vma x = 0; |
252b5132 RH |
14523 | |
14524 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14525 | x = *codep++ & (bfd_signed_vma) 0xff; |
14526 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14527 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14528 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14529 | return x; | |
14530 | } | |
14531 | ||
14532 | static bfd_signed_vma | |
26ca5450 | 14533 | get32s (void) |
52b15da3 JH |
14534 | { |
14535 | bfd_signed_vma x = 0; | |
14536 | ||
14537 | FETCH_DATA (the_info, codep + 4); | |
14538 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14539 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14540 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14541 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14542 | ||
14543 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14544 | ||
252b5132 RH |
14545 | return x; |
14546 | } | |
14547 | ||
14548 | static int | |
26ca5450 | 14549 | get16 (void) |
252b5132 RH |
14550 | { |
14551 | int x = 0; | |
14552 | ||
14553 | FETCH_DATA (the_info, codep + 2); | |
14554 | x = *codep++ & 0xff; | |
14555 | x |= (*codep++ & 0xff) << 8; | |
14556 | return x; | |
14557 | } | |
14558 | ||
14559 | static void | |
26ca5450 | 14560 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14561 | { |
14562 | op_index[op_ad] = op_ad; | |
cb712a9e | 14563 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14564 | { |
14565 | op_address[op_ad] = op; | |
14566 | op_riprel[op_ad] = riprel; | |
14567 | } | |
14568 | else | |
14569 | { | |
14570 | /* Mask to get a 32-bit address. */ | |
14571 | op_address[op_ad] = op & 0xffffffff; | |
14572 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14573 | } | |
252b5132 RH |
14574 | } |
14575 | ||
14576 | static void | |
26ca5450 | 14577 | OP_REG (int code, int sizeflag) |
252b5132 | 14578 | { |
2da11e11 | 14579 | const char *s; |
9b60702d | 14580 | int add; |
de882298 RM |
14581 | |
14582 | switch (code) | |
14583 | { | |
14584 | case es_reg: case ss_reg: case cs_reg: | |
14585 | case ds_reg: case fs_reg: case gs_reg: | |
14586 | oappend (names_seg[code - es_reg]); | |
14587 | return; | |
14588 | } | |
14589 | ||
161a04f6 L |
14590 | USED_REX (REX_B); |
14591 | if (rex & REX_B) | |
52b15da3 | 14592 | add = 8; |
9b60702d L |
14593 | else |
14594 | add = 0; | |
52b15da3 JH |
14595 | |
14596 | switch (code) | |
14597 | { | |
52b15da3 JH |
14598 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14599 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14600 | s = names16[code - ax_reg + add]; | |
14601 | break; | |
52b15da3 JH |
14602 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14603 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14604 | USED_REX (0); | |
14605 | if (rex) | |
14606 | s = names8rex[code - al_reg + add]; | |
14607 | else | |
14608 | s = names8[code - al_reg]; | |
14609 | break; | |
6439fc28 AM |
14610 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14611 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14612 | if (address_mode == mode_64bit |
6c067bbb | 14613 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14614 | { |
14615 | s = names64[code - rAX_reg + add]; | |
14616 | break; | |
14617 | } | |
14618 | code += eAX_reg - rAX_reg; | |
6608db57 | 14619 | /* Fall through. */ |
52b15da3 JH |
14620 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14621 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14622 | USED_REX (REX_W); |
14623 | if (rex & REX_W) | |
52b15da3 | 14624 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14625 | else |
f16cd0d5 L |
14626 | { |
14627 | if (sizeflag & DFLAG) | |
14628 | s = names32[code - eAX_reg + add]; | |
14629 | else | |
14630 | s = names16[code - eAX_reg + add]; | |
14631 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14632 | } | |
52b15da3 | 14633 | break; |
52b15da3 JH |
14634 | default: |
14635 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14636 | break; | |
14637 | } | |
14638 | oappend (s); | |
14639 | } | |
14640 | ||
14641 | static void | |
26ca5450 | 14642 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14643 | { |
14644 | const char *s; | |
252b5132 RH |
14645 | |
14646 | switch (code) | |
14647 | { | |
14648 | case indir_dx_reg: | |
d708bcba | 14649 | if (intel_syntax) |
52fd6d94 | 14650 | s = "dx"; |
d708bcba | 14651 | else |
db6eb5be | 14652 | s = "(%dx)"; |
252b5132 RH |
14653 | break; |
14654 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14655 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14656 | s = names16[code - ax_reg]; | |
14657 | break; | |
14658 | case es_reg: case ss_reg: case cs_reg: | |
14659 | case ds_reg: case fs_reg: case gs_reg: | |
14660 | s = names_seg[code - es_reg]; | |
14661 | break; | |
14662 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14663 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14664 | USED_REX (0); |
14665 | if (rex) | |
14666 | s = names8rex[code - al_reg]; | |
14667 | else | |
14668 | s = names8[code - al_reg]; | |
252b5132 RH |
14669 | break; |
14670 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14671 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14672 | USED_REX (REX_W); |
14673 | if (rex & REX_W) | |
52b15da3 | 14674 | s = names64[code - eAX_reg]; |
252b5132 | 14675 | else |
f16cd0d5 L |
14676 | { |
14677 | if (sizeflag & DFLAG) | |
14678 | s = names32[code - eAX_reg]; | |
14679 | else | |
14680 | s = names16[code - eAX_reg]; | |
14681 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14682 | } | |
252b5132 | 14683 | break; |
52fd6d94 | 14684 | case z_mode_ax_reg: |
161a04f6 | 14685 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14686 | s = *names32; |
14687 | else | |
14688 | s = *names16; | |
161a04f6 | 14689 | if (!(rex & REX_W)) |
52fd6d94 JB |
14690 | used_prefixes |= (prefixes & PREFIX_DATA); |
14691 | break; | |
252b5132 RH |
14692 | default: |
14693 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14694 | break; | |
14695 | } | |
14696 | oappend (s); | |
14697 | } | |
14698 | ||
14699 | static void | |
26ca5450 | 14700 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14701 | { |
52b15da3 JH |
14702 | bfd_signed_vma op; |
14703 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14704 | |
14705 | switch (bytemode) | |
14706 | { | |
14707 | case b_mode: | |
14708 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14709 | op = *codep++; |
14710 | mask = 0xff; | |
14711 | break; | |
14712 | case q_mode: | |
cb712a9e | 14713 | if (address_mode == mode_64bit) |
6439fc28 AM |
14714 | { |
14715 | op = get32s (); | |
14716 | break; | |
14717 | } | |
6608db57 | 14718 | /* Fall through. */ |
252b5132 | 14719 | case v_mode: |
161a04f6 L |
14720 | USED_REX (REX_W); |
14721 | if (rex & REX_W) | |
52b15da3 | 14722 | op = get32s (); |
252b5132 | 14723 | else |
52b15da3 | 14724 | { |
f16cd0d5 L |
14725 | if (sizeflag & DFLAG) |
14726 | { | |
14727 | op = get32 (); | |
14728 | mask = 0xffffffff; | |
14729 | } | |
14730 | else | |
14731 | { | |
14732 | op = get16 (); | |
14733 | mask = 0xfffff; | |
14734 | } | |
14735 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14736 | } |
252b5132 RH |
14737 | break; |
14738 | case w_mode: | |
52b15da3 | 14739 | mask = 0xfffff; |
252b5132 RH |
14740 | op = get16 (); |
14741 | break; | |
9306ca4a JB |
14742 | case const_1_mode: |
14743 | if (intel_syntax) | |
6c067bbb | 14744 | oappend ("1"); |
9306ca4a | 14745 | return; |
252b5132 RH |
14746 | default: |
14747 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14748 | return; | |
14749 | } | |
14750 | ||
52b15da3 JH |
14751 | op &= mask; |
14752 | scratchbuf[0] = '$'; | |
d708bcba | 14753 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14754 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14755 | scratchbuf[0] = '\0'; |
14756 | } | |
14757 | ||
14758 | static void | |
26ca5450 | 14759 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 JH |
14760 | { |
14761 | bfd_signed_vma op; | |
14762 | bfd_signed_vma mask = -1; | |
14763 | ||
cb712a9e | 14764 | if (address_mode != mode_64bit) |
6439fc28 AM |
14765 | { |
14766 | OP_I (bytemode, sizeflag); | |
14767 | return; | |
14768 | } | |
14769 | ||
52b15da3 JH |
14770 | switch (bytemode) |
14771 | { | |
14772 | case b_mode: | |
14773 | FETCH_DATA (the_info, codep + 1); | |
14774 | op = *codep++; | |
14775 | mask = 0xff; | |
14776 | break; | |
14777 | case v_mode: | |
161a04f6 L |
14778 | USED_REX (REX_W); |
14779 | if (rex & REX_W) | |
52b15da3 | 14780 | op = get64 (); |
52b15da3 JH |
14781 | else |
14782 | { | |
f16cd0d5 L |
14783 | if (sizeflag & DFLAG) |
14784 | { | |
14785 | op = get32 (); | |
14786 | mask = 0xffffffff; | |
14787 | } | |
14788 | else | |
14789 | { | |
14790 | op = get16 (); | |
14791 | mask = 0xfffff; | |
14792 | } | |
14793 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14794 | } |
52b15da3 JH |
14795 | break; |
14796 | case w_mode: | |
14797 | mask = 0xfffff; | |
14798 | op = get16 (); | |
14799 | break; | |
14800 | default: | |
14801 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14802 | return; | |
14803 | } | |
14804 | ||
14805 | op &= mask; | |
14806 | scratchbuf[0] = '$'; | |
d708bcba | 14807 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14808 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14809 | scratchbuf[0] = '\0'; |
14810 | } | |
14811 | ||
14812 | static void | |
26ca5450 | 14813 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14814 | { |
52b15da3 | 14815 | bfd_signed_vma op; |
252b5132 RH |
14816 | |
14817 | switch (bytemode) | |
14818 | { | |
14819 | case b_mode: | |
e3949f17 | 14820 | case b_T_mode: |
252b5132 RH |
14821 | FETCH_DATA (the_info, codep + 1); |
14822 | op = *codep++; | |
14823 | if ((op & 0x80) != 0) | |
14824 | op -= 0x100; | |
e3949f17 L |
14825 | if (bytemode == b_T_mode) |
14826 | { | |
14827 | if (address_mode != mode_64bit | |
7bb15c6f | 14828 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14829 | { |
6c067bbb RM |
14830 | /* The operand-size prefix is overridden by a REX prefix. */ |
14831 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14832 | op &= 0xffffffff; |
14833 | else | |
14834 | op &= 0xffff; | |
14835 | } | |
14836 | } | |
14837 | else | |
14838 | { | |
14839 | if (!(rex & REX_W)) | |
14840 | { | |
14841 | if (sizeflag & DFLAG) | |
14842 | op &= 0xffffffff; | |
14843 | else | |
14844 | op &= 0xffff; | |
14845 | } | |
14846 | } | |
252b5132 RH |
14847 | break; |
14848 | case v_mode: | |
7bb15c6f RM |
14849 | /* The operand-size prefix is overridden by a REX prefix. */ |
14850 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14851 | op = get32s (); |
252b5132 | 14852 | else |
d9e3625e | 14853 | op = get16 (); |
252b5132 RH |
14854 | break; |
14855 | default: | |
14856 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14857 | return; | |
14858 | } | |
52b15da3 JH |
14859 | |
14860 | scratchbuf[0] = '$'; | |
14861 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14862 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14863 | } |
14864 | ||
14865 | static void | |
26ca5450 | 14866 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14867 | { |
52b15da3 | 14868 | bfd_vma disp; |
7081ff04 | 14869 | bfd_vma mask = -1; |
65ca155d | 14870 | bfd_vma segment = 0; |
252b5132 RH |
14871 | |
14872 | switch (bytemode) | |
14873 | { | |
14874 | case b_mode: | |
14875 | FETCH_DATA (the_info, codep + 1); | |
14876 | disp = *codep++; | |
14877 | if ((disp & 0x80) != 0) | |
14878 | disp -= 0x100; | |
14879 | break; | |
14880 | case v_mode: | |
5db04b09 L |
14881 | if (isa64 == amd64) |
14882 | USED_REX (REX_W); | |
14883 | if ((sizeflag & DFLAG) | |
14884 | || (address_mode == mode_64bit | |
14885 | && (isa64 != amd64 || (rex & REX_W)))) | |
52b15da3 | 14886 | disp = get32s (); |
252b5132 RH |
14887 | else |
14888 | { | |
14889 | disp = get16 (); | |
206717e8 L |
14890 | if ((disp & 0x8000) != 0) |
14891 | disp -= 0x10000; | |
65ca155d L |
14892 | /* In 16bit mode, address is wrapped around at 64k within |
14893 | the same segment. Otherwise, a data16 prefix on a jump | |
14894 | instruction means that the pc is masked to 16 bits after | |
14895 | the displacement is added! */ | |
14896 | mask = 0xffff; | |
14897 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14898 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14899 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14900 | } |
5db04b09 L |
14901 | if (address_mode != mode_64bit |
14902 | || (isa64 == amd64 && !(rex & REX_W))) | |
f16cd0d5 | 14903 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14904 | break; |
14905 | default: | |
14906 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14907 | return; | |
14908 | } | |
42d5f9c6 | 14909 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14910 | set_op (disp, 0); |
14911 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14912 | oappend (scratchbuf); |
14913 | } | |
14914 | ||
252b5132 | 14915 | static void |
ed7841b3 | 14916 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14917 | { |
ed7841b3 | 14918 | if (bytemode == w_mode) |
7967e09e | 14919 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14920 | else |
7967e09e | 14921 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14922 | } |
14923 | ||
14924 | static void | |
26ca5450 | 14925 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14926 | { |
14927 | int seg, offset; | |
14928 | ||
c608c12e | 14929 | if (sizeflag & DFLAG) |
252b5132 | 14930 | { |
c608c12e AM |
14931 | offset = get32 (); |
14932 | seg = get16 (); | |
252b5132 | 14933 | } |
c608c12e AM |
14934 | else |
14935 | { | |
14936 | offset = get16 (); | |
14937 | seg = get16 (); | |
14938 | } | |
7d421014 | 14939 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14940 | if (intel_syntax) |
3f31e633 | 14941 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14942 | else |
14943 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14944 | oappend (scratchbuf); |
252b5132 RH |
14945 | } |
14946 | ||
252b5132 | 14947 | static void |
3f31e633 | 14948 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14949 | { |
52b15da3 | 14950 | bfd_vma off; |
252b5132 | 14951 | |
3f31e633 JB |
14952 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14953 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14954 | append_seg (); |
14955 | ||
cb712a9e | 14956 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14957 | off = get32 (); |
14958 | else | |
14959 | off = get16 (); | |
14960 | ||
14961 | if (intel_syntax) | |
14962 | { | |
285ca992 | 14963 | if (!active_seg_prefix) |
252b5132 | 14964 | { |
d708bcba | 14965 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14966 | oappend (":"); |
14967 | } | |
14968 | } | |
52b15da3 JH |
14969 | print_operand_value (scratchbuf, 1, off); |
14970 | oappend (scratchbuf); | |
14971 | } | |
6439fc28 | 14972 | |
52b15da3 | 14973 | static void |
3f31e633 | 14974 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14975 | { |
14976 | bfd_vma off; | |
14977 | ||
539e75ad L |
14978 | if (address_mode != mode_64bit |
14979 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14980 | { |
14981 | OP_OFF (bytemode, sizeflag); | |
14982 | return; | |
14983 | } | |
14984 | ||
3f31e633 JB |
14985 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14986 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14987 | append_seg (); |
14988 | ||
6608db57 | 14989 | off = get64 (); |
52b15da3 JH |
14990 | |
14991 | if (intel_syntax) | |
14992 | { | |
285ca992 | 14993 | if (!active_seg_prefix) |
52b15da3 | 14994 | { |
d708bcba | 14995 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
14996 | oappend (":"); |
14997 | } | |
14998 | } | |
14999 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
15000 | oappend (scratchbuf); |
15001 | } | |
15002 | ||
15003 | static void | |
26ca5450 | 15004 | ptr_reg (int code, int sizeflag) |
252b5132 | 15005 | { |
2da11e11 | 15006 | const char *s; |
d708bcba | 15007 | |
1d9f512f | 15008 | *obufp++ = open_char; |
20f0a1fc | 15009 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 15010 | if (address_mode == mode_64bit) |
c1a64871 JH |
15011 | { |
15012 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 15013 | s = names32[code - eAX_reg]; |
c1a64871 | 15014 | else |
db6eb5be | 15015 | s = names64[code - eAX_reg]; |
c1a64871 | 15016 | } |
52b15da3 | 15017 | else if (sizeflag & AFLAG) |
252b5132 RH |
15018 | s = names32[code - eAX_reg]; |
15019 | else | |
15020 | s = names16[code - eAX_reg]; | |
15021 | oappend (s); | |
1d9f512f AM |
15022 | *obufp++ = close_char; |
15023 | *obufp = 0; | |
252b5132 RH |
15024 | } |
15025 | ||
15026 | static void | |
26ca5450 | 15027 | OP_ESreg (int code, int sizeflag) |
252b5132 | 15028 | { |
9306ca4a | 15029 | if (intel_syntax) |
52fd6d94 JB |
15030 | { |
15031 | switch (codep[-1]) | |
15032 | { | |
15033 | case 0x6d: /* insw/insl */ | |
15034 | intel_operand_size (z_mode, sizeflag); | |
15035 | break; | |
15036 | case 0xa5: /* movsw/movsl/movsq */ | |
15037 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15038 | case 0xab: /* stosw/stosl */ | |
15039 | case 0xaf: /* scasw/scasl */ | |
15040 | intel_operand_size (v_mode, sizeflag); | |
15041 | break; | |
15042 | default: | |
15043 | intel_operand_size (b_mode, sizeflag); | |
15044 | } | |
15045 | } | |
9ce09ba2 | 15046 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
15047 | ptr_reg (code, sizeflag); |
15048 | } | |
15049 | ||
15050 | static void | |
26ca5450 | 15051 | OP_DSreg (int code, int sizeflag) |
252b5132 | 15052 | { |
9306ca4a | 15053 | if (intel_syntax) |
52fd6d94 JB |
15054 | { |
15055 | switch (codep[-1]) | |
15056 | { | |
15057 | case 0x6f: /* outsw/outsl */ | |
15058 | intel_operand_size (z_mode, sizeflag); | |
15059 | break; | |
15060 | case 0xa5: /* movsw/movsl/movsq */ | |
15061 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
15062 | case 0xad: /* lodsw/lodsl/lodsq */ | |
15063 | intel_operand_size (v_mode, sizeflag); | |
15064 | break; | |
15065 | default: | |
15066 | intel_operand_size (b_mode, sizeflag); | |
15067 | } | |
15068 | } | |
285ca992 L |
15069 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
15070 | default segment register DS is printed. */ | |
15071 | if (!active_seg_prefix) | |
15072 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 15073 | append_seg (); |
252b5132 RH |
15074 | ptr_reg (code, sizeflag); |
15075 | } | |
15076 | ||
252b5132 | 15077 | static void |
26ca5450 | 15078 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15079 | { |
9b60702d | 15080 | int add; |
161a04f6 | 15081 | if (rex & REX_R) |
c4a530c5 | 15082 | { |
161a04f6 | 15083 | USED_REX (REX_R); |
c4a530c5 JB |
15084 | add = 8; |
15085 | } | |
cb712a9e | 15086 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 15087 | { |
f16cd0d5 | 15088 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
15089 | used_prefixes |= PREFIX_LOCK; |
15090 | add = 8; | |
15091 | } | |
9b60702d L |
15092 | else |
15093 | add = 0; | |
7967e09e | 15094 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 15095 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15096 | } |
15097 | ||
252b5132 | 15098 | static void |
26ca5450 | 15099 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15100 | { |
9b60702d | 15101 | int add; |
161a04f6 L |
15102 | USED_REX (REX_R); |
15103 | if (rex & REX_R) | |
52b15da3 | 15104 | add = 8; |
9b60702d L |
15105 | else |
15106 | add = 0; | |
d708bcba | 15107 | if (intel_syntax) |
7967e09e | 15108 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 15109 | else |
7967e09e | 15110 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
15111 | oappend (scratchbuf); |
15112 | } | |
15113 | ||
252b5132 | 15114 | static void |
26ca5450 | 15115 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15116 | { |
7967e09e | 15117 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 15118 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
15119 | } |
15120 | ||
15121 | static void | |
6f74c397 | 15122 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15123 | { |
68f34464 L |
15124 | /* Skip mod/rm byte. */ |
15125 | MODRM_CHECK; | |
15126 | codep++; | |
15127 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15128 | } |
15129 | ||
15130 | static void | |
26ca5450 | 15131 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15132 | { |
b9733481 L |
15133 | int reg = modrm.reg; |
15134 | const char **names; | |
15135 | ||
041bd2e0 JH |
15136 | used_prefixes |= (prefixes & PREFIX_DATA); |
15137 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15138 | { |
b9733481 | 15139 | names = names_xmm; |
161a04f6 L |
15140 | USED_REX (REX_R); |
15141 | if (rex & REX_R) | |
b9733481 | 15142 | reg += 8; |
20f0a1fc | 15143 | } |
041bd2e0 | 15144 | else |
b9733481 L |
15145 | names = names_mm; |
15146 | oappend (names[reg]); | |
252b5132 RH |
15147 | } |
15148 | ||
c608c12e | 15149 | static void |
c0f3af97 | 15150 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15151 | { |
b9733481 L |
15152 | int reg = modrm.reg; |
15153 | const char **names; | |
15154 | ||
161a04f6 L |
15155 | USED_REX (REX_R); |
15156 | if (rex & REX_R) | |
b9733481 | 15157 | reg += 8; |
43234a1e L |
15158 | if (vex.evex) |
15159 | { | |
15160 | if (!vex.r) | |
15161 | reg += 16; | |
15162 | } | |
15163 | ||
539f890d L |
15164 | if (need_vex |
15165 | && bytemode != xmm_mode | |
43234a1e L |
15166 | && bytemode != xmmq_mode |
15167 | && bytemode != evex_half_bcst_xmmq_mode | |
15168 | && bytemode != ymm_mode | |
539f890d | 15169 | && bytemode != scalar_mode) |
c0f3af97 L |
15170 | { |
15171 | switch (vex.length) | |
15172 | { | |
15173 | case 128: | |
b9733481 | 15174 | names = names_xmm; |
c0f3af97 L |
15175 | break; |
15176 | case 256: | |
5fc35d96 IT |
15177 | if (vex.w |
15178 | || (bytemode != vex_vsib_q_w_dq_mode | |
15179 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15180 | names = names_ymm; |
15181 | else | |
15182 | names = names_xmm; | |
c0f3af97 | 15183 | break; |
43234a1e L |
15184 | case 512: |
15185 | names = names_zmm; | |
15186 | break; | |
c0f3af97 L |
15187 | default: |
15188 | abort (); | |
15189 | } | |
15190 | } | |
43234a1e L |
15191 | else if (bytemode == xmmq_mode |
15192 | || bytemode == evex_half_bcst_xmmq_mode) | |
15193 | { | |
15194 | switch (vex.length) | |
15195 | { | |
15196 | case 128: | |
15197 | case 256: | |
15198 | names = names_xmm; | |
15199 | break; | |
15200 | case 512: | |
15201 | names = names_ymm; | |
15202 | break; | |
15203 | default: | |
15204 | abort (); | |
15205 | } | |
15206 | } | |
15207 | else if (bytemode == ymm_mode) | |
15208 | names = names_ymm; | |
c0f3af97 | 15209 | else |
b9733481 L |
15210 | names = names_xmm; |
15211 | oappend (names[reg]); | |
c608c12e AM |
15212 | } |
15213 | ||
252b5132 | 15214 | static void |
26ca5450 | 15215 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15216 | { |
b9733481 L |
15217 | int reg; |
15218 | const char **names; | |
15219 | ||
7967e09e | 15220 | if (modrm.mod != 3) |
252b5132 | 15221 | { |
b6169b20 L |
15222 | if (intel_syntax |
15223 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15224 | { |
15225 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15226 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15227 | } |
252b5132 RH |
15228 | OP_E (bytemode, sizeflag); |
15229 | return; | |
15230 | } | |
15231 | ||
b6169b20 L |
15232 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15233 | swap_operand (); | |
15234 | ||
6608db57 | 15235 | /* Skip mod/rm byte. */ |
4bba6815 | 15236 | MODRM_CHECK; |
252b5132 | 15237 | codep++; |
041bd2e0 | 15238 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15239 | reg = modrm.rm; |
041bd2e0 | 15240 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15241 | { |
b9733481 | 15242 | names = names_xmm; |
161a04f6 L |
15243 | USED_REX (REX_B); |
15244 | if (rex & REX_B) | |
b9733481 | 15245 | reg += 8; |
20f0a1fc | 15246 | } |
041bd2e0 | 15247 | else |
b9733481 L |
15248 | names = names_mm; |
15249 | oappend (names[reg]); | |
252b5132 RH |
15250 | } |
15251 | ||
246c51aa L |
15252 | /* cvt* are the only instructions in sse2 which have |
15253 | both SSE and MMX operands and also have 0x66 prefix | |
15254 | in their opcode. 0x66 was originally used to differentiate | |
15255 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15256 | cvt* separately using OP_EMC and OP_MXC */ |
15257 | static void | |
15258 | OP_EMC (int bytemode, int sizeflag) | |
15259 | { | |
7967e09e | 15260 | if (modrm.mod != 3) |
4d9567e0 MM |
15261 | { |
15262 | if (intel_syntax && bytemode == v_mode) | |
15263 | { | |
15264 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15265 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15266 | } |
4d9567e0 MM |
15267 | OP_E (bytemode, sizeflag); |
15268 | return; | |
15269 | } | |
246c51aa | 15270 | |
4d9567e0 MM |
15271 | /* Skip mod/rm byte. */ |
15272 | MODRM_CHECK; | |
15273 | codep++; | |
15274 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15275 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15276 | } |
15277 | ||
15278 | static void | |
15279 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15280 | { | |
15281 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15282 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15283 | } |
15284 | ||
c608c12e | 15285 | static void |
26ca5450 | 15286 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15287 | { |
b9733481 L |
15288 | int reg; |
15289 | const char **names; | |
d6f574e0 L |
15290 | |
15291 | /* Skip mod/rm byte. */ | |
15292 | MODRM_CHECK; | |
15293 | codep++; | |
15294 | ||
7967e09e | 15295 | if (modrm.mod != 3) |
c608c12e | 15296 | { |
c1e679ec | 15297 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15298 | return; |
15299 | } | |
d6f574e0 | 15300 | |
b9733481 | 15301 | reg = modrm.rm; |
161a04f6 L |
15302 | USED_REX (REX_B); |
15303 | if (rex & REX_B) | |
b9733481 | 15304 | reg += 8; |
43234a1e L |
15305 | if (vex.evex) |
15306 | { | |
15307 | USED_REX (REX_X); | |
15308 | if ((rex & REX_X)) | |
15309 | reg += 16; | |
15310 | } | |
c608c12e | 15311 | |
b6169b20 | 15312 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15313 | && (bytemode == x_swap_mode |
15314 | || bytemode == d_swap_mode | |
7bb15c6f | 15315 | || bytemode == d_scalar_swap_mode |
539f890d L |
15316 | || bytemode == q_swap_mode |
15317 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15318 | swap_operand (); |
15319 | ||
c0f3af97 L |
15320 | if (need_vex |
15321 | && bytemode != xmm_mode | |
6c30d220 L |
15322 | && bytemode != xmmdw_mode |
15323 | && bytemode != xmmqd_mode | |
15324 | && bytemode != xmm_mb_mode | |
15325 | && bytemode != xmm_mw_mode | |
15326 | && bytemode != xmm_md_mode | |
15327 | && bytemode != xmm_mq_mode | |
43234a1e | 15328 | && bytemode != xmm_mdq_mode |
539f890d | 15329 | && bytemode != xmmq_mode |
43234a1e L |
15330 | && bytemode != evex_half_bcst_xmmq_mode |
15331 | && bytemode != ymm_mode | |
539f890d | 15332 | && bytemode != d_scalar_mode |
7bb15c6f | 15333 | && bytemode != d_scalar_swap_mode |
539f890d | 15334 | && bytemode != q_scalar_mode |
1c480963 L |
15335 | && bytemode != q_scalar_swap_mode |
15336 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15337 | { |
15338 | switch (vex.length) | |
15339 | { | |
15340 | case 128: | |
b9733481 | 15341 | names = names_xmm; |
c0f3af97 L |
15342 | break; |
15343 | case 256: | |
b9733481 | 15344 | names = names_ymm; |
c0f3af97 | 15345 | break; |
43234a1e L |
15346 | case 512: |
15347 | names = names_zmm; | |
15348 | break; | |
c0f3af97 L |
15349 | default: |
15350 | abort (); | |
15351 | } | |
15352 | } | |
43234a1e L |
15353 | else if (bytemode == xmmq_mode |
15354 | || bytemode == evex_half_bcst_xmmq_mode) | |
15355 | { | |
15356 | switch (vex.length) | |
15357 | { | |
15358 | case 128: | |
15359 | case 256: | |
15360 | names = names_xmm; | |
15361 | break; | |
15362 | case 512: | |
15363 | names = names_ymm; | |
15364 | break; | |
15365 | default: | |
15366 | abort (); | |
15367 | } | |
15368 | } | |
15369 | else if (bytemode == ymm_mode) | |
15370 | names = names_ymm; | |
c0f3af97 | 15371 | else |
b9733481 L |
15372 | names = names_xmm; |
15373 | oappend (names[reg]); | |
c608c12e AM |
15374 | } |
15375 | ||
252b5132 | 15376 | static void |
26ca5450 | 15377 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15378 | { |
7967e09e | 15379 | if (modrm.mod == 3) |
2da11e11 AM |
15380 | OP_EM (bytemode, sizeflag); |
15381 | else | |
6608db57 | 15382 | BadOp (); |
252b5132 RH |
15383 | } |
15384 | ||
992aaec9 | 15385 | static void |
26ca5450 | 15386 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15387 | { |
7967e09e | 15388 | if (modrm.mod == 3) |
992aaec9 AM |
15389 | OP_EX (bytemode, sizeflag); |
15390 | else | |
6608db57 | 15391 | BadOp (); |
992aaec9 AM |
15392 | } |
15393 | ||
cc0ec051 AM |
15394 | static void |
15395 | OP_M (int bytemode, int sizeflag) | |
15396 | { | |
7967e09e | 15397 | if (modrm.mod == 3) |
75413a22 L |
15398 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15399 | BadOp (); | |
cc0ec051 AM |
15400 | else |
15401 | OP_E (bytemode, sizeflag); | |
15402 | } | |
15403 | ||
15404 | static void | |
15405 | OP_0f07 (int bytemode, int sizeflag) | |
15406 | { | |
7967e09e | 15407 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15408 | BadOp (); |
15409 | else | |
15410 | OP_E (bytemode, sizeflag); | |
15411 | } | |
15412 | ||
46e883c5 | 15413 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15414 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15415 | |
cc0ec051 | 15416 | static void |
46e883c5 | 15417 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15418 | { |
8b38ad71 L |
15419 | if ((prefixes & PREFIX_DATA) != 0 |
15420 | || (rex != 0 | |
15421 | && rex != 0x48 | |
15422 | && address_mode == mode_64bit)) | |
46e883c5 L |
15423 | OP_REG (bytemode, sizeflag); |
15424 | else | |
15425 | strcpy (obuf, "nop"); | |
15426 | } | |
15427 | ||
15428 | static void | |
15429 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15430 | { | |
8b38ad71 L |
15431 | if ((prefixes & PREFIX_DATA) != 0 |
15432 | || (rex != 0 | |
15433 | && rex != 0x48 | |
15434 | && address_mode == mode_64bit)) | |
46e883c5 | 15435 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15436 | } |
15437 | ||
84037f8c | 15438 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15439 | /* 00 */ NULL, NULL, NULL, NULL, |
15440 | /* 04 */ NULL, NULL, NULL, NULL, | |
15441 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15442 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15443 | /* 10 */ NULL, NULL, NULL, NULL, |
15444 | /* 14 */ NULL, NULL, NULL, NULL, | |
15445 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15446 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15447 | /* 20 */ NULL, NULL, NULL, NULL, |
15448 | /* 24 */ NULL, NULL, NULL, NULL, | |
15449 | /* 28 */ NULL, NULL, NULL, NULL, | |
15450 | /* 2C */ NULL, NULL, NULL, NULL, | |
15451 | /* 30 */ NULL, NULL, NULL, NULL, | |
15452 | /* 34 */ NULL, NULL, NULL, NULL, | |
15453 | /* 38 */ NULL, NULL, NULL, NULL, | |
15454 | /* 3C */ NULL, NULL, NULL, NULL, | |
15455 | /* 40 */ NULL, NULL, NULL, NULL, | |
15456 | /* 44 */ NULL, NULL, NULL, NULL, | |
15457 | /* 48 */ NULL, NULL, NULL, NULL, | |
15458 | /* 4C */ NULL, NULL, NULL, NULL, | |
15459 | /* 50 */ NULL, NULL, NULL, NULL, | |
15460 | /* 54 */ NULL, NULL, NULL, NULL, | |
15461 | /* 58 */ NULL, NULL, NULL, NULL, | |
15462 | /* 5C */ NULL, NULL, NULL, NULL, | |
15463 | /* 60 */ NULL, NULL, NULL, NULL, | |
15464 | /* 64 */ NULL, NULL, NULL, NULL, | |
15465 | /* 68 */ NULL, NULL, NULL, NULL, | |
15466 | /* 6C */ NULL, NULL, NULL, NULL, | |
15467 | /* 70 */ NULL, NULL, NULL, NULL, | |
15468 | /* 74 */ NULL, NULL, NULL, NULL, | |
15469 | /* 78 */ NULL, NULL, NULL, NULL, | |
15470 | /* 7C */ NULL, NULL, NULL, NULL, | |
15471 | /* 80 */ NULL, NULL, NULL, NULL, | |
15472 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15473 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15474 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15475 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15476 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15477 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15478 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15479 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15480 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15481 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15482 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15483 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15484 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15485 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15486 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15487 | /* C0 */ NULL, NULL, NULL, NULL, | |
15488 | /* C4 */ NULL, NULL, NULL, NULL, | |
15489 | /* C8 */ NULL, NULL, NULL, NULL, | |
15490 | /* CC */ NULL, NULL, NULL, NULL, | |
15491 | /* D0 */ NULL, NULL, NULL, NULL, | |
15492 | /* D4 */ NULL, NULL, NULL, NULL, | |
15493 | /* D8 */ NULL, NULL, NULL, NULL, | |
15494 | /* DC */ NULL, NULL, NULL, NULL, | |
15495 | /* E0 */ NULL, NULL, NULL, NULL, | |
15496 | /* E4 */ NULL, NULL, NULL, NULL, | |
15497 | /* E8 */ NULL, NULL, NULL, NULL, | |
15498 | /* EC */ NULL, NULL, NULL, NULL, | |
15499 | /* F0 */ NULL, NULL, NULL, NULL, | |
15500 | /* F4 */ NULL, NULL, NULL, NULL, | |
15501 | /* F8 */ NULL, NULL, NULL, NULL, | |
15502 | /* FC */ NULL, NULL, NULL, NULL, | |
15503 | }; | |
15504 | ||
15505 | static void | |
26ca5450 | 15506 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15507 | { |
15508 | const char *mnemonic; | |
15509 | ||
15510 | FETCH_DATA (the_info, codep + 1); | |
15511 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15512 | place where an 8-bit immediate would normally go. ie. the last | |
15513 | byte of the instruction. */ | |
ea397f5b | 15514 | obufp = mnemonicendp; |
c608c12e | 15515 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15516 | if (mnemonic) |
2da11e11 | 15517 | oappend (mnemonic); |
252b5132 RH |
15518 | else |
15519 | { | |
15520 | /* Since a variable sized modrm/sib chunk is between the start | |
15521 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15522 | all the modrm processing first, and don't know until now that | |
15523 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15524 | op_out[0][0] = '\0'; |
15525 | op_out[1][0] = '\0'; | |
6608db57 | 15526 | BadOp (); |
252b5132 | 15527 | } |
ea397f5b | 15528 | mnemonicendp = obufp; |
252b5132 | 15529 | } |
c608c12e | 15530 | |
ea397f5b L |
15531 | static struct op simd_cmp_op[] = |
15532 | { | |
15533 | { STRING_COMMA_LEN ("eq") }, | |
15534 | { STRING_COMMA_LEN ("lt") }, | |
15535 | { STRING_COMMA_LEN ("le") }, | |
15536 | { STRING_COMMA_LEN ("unord") }, | |
15537 | { STRING_COMMA_LEN ("neq") }, | |
15538 | { STRING_COMMA_LEN ("nlt") }, | |
15539 | { STRING_COMMA_LEN ("nle") }, | |
15540 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15541 | }; |
15542 | ||
15543 | static void | |
ad19981d | 15544 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15545 | { |
15546 | unsigned int cmp_type; | |
15547 | ||
15548 | FETCH_DATA (the_info, codep + 1); | |
15549 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15550 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15551 | { |
ad19981d | 15552 | char suffix [3]; |
ea397f5b | 15553 | char *p = mnemonicendp - 2; |
ad19981d L |
15554 | suffix[0] = p[0]; |
15555 | suffix[1] = p[1]; | |
15556 | suffix[2] = '\0'; | |
ea397f5b L |
15557 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15558 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15559 | } |
15560 | else | |
15561 | { | |
ad19981d L |
15562 | /* We have a reserved extension byte. Output it directly. */ |
15563 | scratchbuf[0] = '$'; | |
15564 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15565 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15566 | scratchbuf[0] = '\0'; |
c608c12e AM |
15567 | } |
15568 | } | |
15569 | ||
9916071f AP |
15570 | static void |
15571 | OP_Mwaitx (int bytemode ATTRIBUTE_UNUSED, | |
15572 | int sizeflag ATTRIBUTE_UNUSED) | |
15573 | { | |
15574 | /* mwaitx %eax,%ecx,%ebx */ | |
15575 | if (!intel_syntax) | |
15576 | { | |
15577 | const char **names = (address_mode == mode_64bit | |
15578 | ? names64 : names32); | |
15579 | strcpy (op_out[0], names[0]); | |
15580 | strcpy (op_out[1], names[1]); | |
15581 | strcpy (op_out[2], names[3]); | |
15582 | two_source_ops = 1; | |
15583 | } | |
15584 | /* Skip mod/rm byte. */ | |
15585 | MODRM_CHECK; | |
15586 | codep++; | |
15587 | } | |
15588 | ||
ca164297 | 15589 | static void |
b844680a L |
15590 | OP_Mwait (int bytemode ATTRIBUTE_UNUSED, |
15591 | int sizeflag ATTRIBUTE_UNUSED) | |
15592 | { | |
15593 | /* mwait %eax,%ecx */ | |
15594 | if (!intel_syntax) | |
15595 | { | |
15596 | const char **names = (address_mode == mode_64bit | |
15597 | ? names64 : names32); | |
15598 | strcpy (op_out[0], names[0]); | |
15599 | strcpy (op_out[1], names[1]); | |
15600 | two_source_ops = 1; | |
15601 | } | |
15602 | /* Skip mod/rm byte. */ | |
15603 | MODRM_CHECK; | |
15604 | codep++; | |
15605 | } | |
15606 | ||
15607 | static void | |
15608 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15609 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15610 | { |
b844680a L |
15611 | /* monitor %eax,%ecx,%edx" */ |
15612 | if (!intel_syntax) | |
ca164297 | 15613 | { |
b844680a | 15614 | const char **op1_names; |
cb712a9e L |
15615 | const char **names = (address_mode == mode_64bit |
15616 | ? names64 : names32); | |
1d9f512f | 15617 | |
b844680a L |
15618 | if (!(prefixes & PREFIX_ADDR)) |
15619 | op1_names = (address_mode == mode_16bit | |
15620 | ? names16 : names); | |
ca164297 L |
15621 | else |
15622 | { | |
b844680a | 15623 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15624 | all_prefixes[last_addr_prefix] = 0; |
b844680a L |
15625 | op1_names = (address_mode != mode_32bit |
15626 | ? names32 : names16); | |
15627 | used_prefixes |= PREFIX_ADDR; | |
ca164297 | 15628 | } |
b844680a L |
15629 | strcpy (op_out[0], op1_names[0]); |
15630 | strcpy (op_out[1], names[1]); | |
15631 | strcpy (op_out[2], names[2]); | |
15632 | two_source_ops = 1; | |
ca164297 | 15633 | } |
b844680a L |
15634 | /* Skip mod/rm byte. */ |
15635 | MODRM_CHECK; | |
15636 | codep++; | |
30123838 JB |
15637 | } |
15638 | ||
6608db57 KH |
15639 | static void |
15640 | BadOp (void) | |
2da11e11 | 15641 | { |
6608db57 KH |
15642 | /* Throw away prefixes and 1st. opcode byte. */ |
15643 | codep = insn_codep + 1; | |
2da11e11 AM |
15644 | oappend ("(bad)"); |
15645 | } | |
4cc91dba | 15646 | |
35c52694 L |
15647 | static void |
15648 | REP_Fixup (int bytemode, int sizeflag) | |
15649 | { | |
15650 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15651 | lods and stos. */ | |
35c52694 | 15652 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15653 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15654 | |
15655 | switch (bytemode) | |
15656 | { | |
15657 | case al_reg: | |
15658 | case eAX_reg: | |
15659 | case indir_dx_reg: | |
15660 | OP_IMREG (bytemode, sizeflag); | |
15661 | break; | |
15662 | case eDI_reg: | |
15663 | OP_ESreg (bytemode, sizeflag); | |
15664 | break; | |
15665 | case eSI_reg: | |
15666 | OP_DSreg (bytemode, sizeflag); | |
15667 | break; | |
15668 | default: | |
15669 | abort (); | |
15670 | break; | |
15671 | } | |
15672 | } | |
f5804c90 | 15673 | |
7e8b059b L |
15674 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15675 | "bnd". */ | |
15676 | ||
15677 | static void | |
15678 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15679 | { | |
15680 | if (prefixes & PREFIX_REPNZ) | |
15681 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15682 | } | |
15683 | ||
04ef582a L |
15684 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15685 | "notrack". */ | |
15686 | ||
15687 | static void | |
15688 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15689 | int sizeflag ATTRIBUTE_UNUSED) | |
15690 | { | |
9fef80d6 | 15691 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15692 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15693 | { | |
4e9ac44a | 15694 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15695 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15696 | active_seg_prefix = 0; |
15697 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15698 | } | |
15699 | } | |
15700 | ||
42164a71 L |
15701 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15702 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15703 | */ | |
15704 | ||
15705 | static void | |
15706 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15707 | { | |
15708 | if (modrm.mod != 3 | |
15709 | && (prefixes & PREFIX_LOCK) != 0) | |
15710 | { | |
15711 | if (prefixes & PREFIX_REPZ) | |
15712 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15713 | if (prefixes & PREFIX_REPNZ) | |
15714 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15715 | } | |
15716 | ||
15717 | OP_E (bytemode, sizeflag); | |
15718 | } | |
15719 | ||
15720 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15721 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15722 | */ | |
15723 | ||
15724 | static void | |
15725 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15726 | { | |
15727 | if (modrm.mod != 3) | |
15728 | { | |
15729 | if (prefixes & PREFIX_REPZ) | |
15730 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15731 | if (prefixes & PREFIX_REPNZ) | |
15732 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15733 | } | |
15734 | ||
15735 | OP_E (bytemode, sizeflag); | |
15736 | } | |
15737 | ||
15738 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15739 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15740 | ||
15741 | static void | |
15742 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15743 | { | |
15744 | if (modrm.mod != 3 | |
15745 | && last_repz_prefix > last_repnz_prefix | |
15746 | && (prefixes & PREFIX_REPZ) != 0) | |
15747 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15748 | ||
15749 | OP_E (bytemode, sizeflag); | |
15750 | } | |
15751 | ||
f5804c90 L |
15752 | static void |
15753 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15754 | { | |
161a04f6 L |
15755 | USED_REX (REX_W); |
15756 | if (rex & REX_W) | |
f5804c90 L |
15757 | { |
15758 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15759 | char *p = mnemonicendp - 2; |
15760 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15761 | bytemode = o_mode; |
f5804c90 | 15762 | } |
42164a71 L |
15763 | else if ((prefixes & PREFIX_LOCK) != 0) |
15764 | { | |
15765 | if (prefixes & PREFIX_REPZ) | |
15766 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15767 | if (prefixes & PREFIX_REPNZ) | |
15768 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15769 | } | |
15770 | ||
f5804c90 L |
15771 | OP_M (bytemode, sizeflag); |
15772 | } | |
42903f7f L |
15773 | |
15774 | static void | |
15775 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15776 | { | |
b9733481 L |
15777 | const char **names; |
15778 | ||
c0f3af97 L |
15779 | if (need_vex) |
15780 | { | |
15781 | switch (vex.length) | |
15782 | { | |
15783 | case 128: | |
b9733481 | 15784 | names = names_xmm; |
c0f3af97 L |
15785 | break; |
15786 | case 256: | |
b9733481 | 15787 | names = names_ymm; |
c0f3af97 L |
15788 | break; |
15789 | default: | |
15790 | abort (); | |
15791 | } | |
15792 | } | |
15793 | else | |
b9733481 L |
15794 | names = names_xmm; |
15795 | oappend (names[reg]); | |
42903f7f | 15796 | } |
381d071f L |
15797 | |
15798 | static void | |
15799 | CRC32_Fixup (int bytemode, int sizeflag) | |
15800 | { | |
15801 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15802 | char *p = mnemonicendp; |
381d071f L |
15803 | |
15804 | switch (bytemode) | |
15805 | { | |
15806 | case b_mode: | |
20592a94 | 15807 | if (intel_syntax) |
ea397f5b | 15808 | goto skip; |
20592a94 | 15809 | |
381d071f L |
15810 | *p++ = 'b'; |
15811 | break; | |
15812 | case v_mode: | |
20592a94 | 15813 | if (intel_syntax) |
ea397f5b | 15814 | goto skip; |
20592a94 | 15815 | |
381d071f L |
15816 | USED_REX (REX_W); |
15817 | if (rex & REX_W) | |
15818 | *p++ = 'q'; | |
7bb15c6f | 15819 | else |
f16cd0d5 L |
15820 | { |
15821 | if (sizeflag & DFLAG) | |
15822 | *p++ = 'l'; | |
15823 | else | |
15824 | *p++ = 'w'; | |
15825 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15826 | } | |
381d071f L |
15827 | break; |
15828 | default: | |
15829 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15830 | break; | |
15831 | } | |
ea397f5b | 15832 | mnemonicendp = p; |
381d071f L |
15833 | *p = '\0'; |
15834 | ||
ea397f5b | 15835 | skip: |
381d071f L |
15836 | if (modrm.mod == 3) |
15837 | { | |
15838 | int add; | |
15839 | ||
15840 | /* Skip mod/rm byte. */ | |
15841 | MODRM_CHECK; | |
15842 | codep++; | |
15843 | ||
15844 | USED_REX (REX_B); | |
15845 | add = (rex & REX_B) ? 8 : 0; | |
15846 | if (bytemode == b_mode) | |
15847 | { | |
15848 | USED_REX (0); | |
15849 | if (rex) | |
15850 | oappend (names8rex[modrm.rm + add]); | |
15851 | else | |
15852 | oappend (names8[modrm.rm + add]); | |
15853 | } | |
15854 | else | |
15855 | { | |
15856 | USED_REX (REX_W); | |
15857 | if (rex & REX_W) | |
15858 | oappend (names64[modrm.rm + add]); | |
15859 | else if ((prefixes & PREFIX_DATA)) | |
15860 | oappend (names16[modrm.rm + add]); | |
15861 | else | |
15862 | oappend (names32[modrm.rm + add]); | |
15863 | } | |
15864 | } | |
15865 | else | |
9344ff29 | 15866 | OP_E (bytemode, sizeflag); |
381d071f | 15867 | } |
85f10a01 | 15868 | |
eacc9c89 L |
15869 | static void |
15870 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15871 | { | |
15872 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15873 | USED_REX (REX_W); | |
15874 | if (rex & REX_W) | |
15875 | { | |
15876 | char *p = mnemonicendp; | |
15877 | *p++ = '6'; | |
15878 | *p++ = '4'; | |
15879 | *p = '\0'; | |
15880 | mnemonicendp = p; | |
15881 | } | |
15882 | OP_M (bytemode, sizeflag); | |
15883 | } | |
15884 | ||
15c7c1d8 JB |
15885 | static void |
15886 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15887 | { | |
15888 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15889 | if (!intel_syntax) | |
15890 | { | |
15891 | char *p = mnemonicendp; | |
15892 | ||
15893 | USED_REX (REX_W); | |
15894 | if (rex & REX_W) | |
15895 | *p++ = 'q'; | |
15896 | else if (sizeflag & SUFFIX_ALWAYS) | |
15897 | *p++ = 'l'; | |
15898 | ||
15899 | *p = '\0'; | |
15900 | mnemonicendp = p; | |
15901 | } | |
15902 | ||
15903 | OP_EX (bytemode, sizeflag); | |
15904 | } | |
15905 | ||
c0f3af97 L |
15906 | /* Display the destination register operand for instructions with |
15907 | VEX. */ | |
15908 | ||
15909 | static void | |
15910 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15911 | { | |
539f890d | 15912 | int reg; |
b9733481 L |
15913 | const char **names; |
15914 | ||
c0f3af97 L |
15915 | if (!need_vex) |
15916 | abort (); | |
15917 | ||
15918 | if (!need_vex_reg) | |
15919 | return; | |
15920 | ||
539f890d | 15921 | reg = vex.register_specifier; |
5f847646 JB |
15922 | if (address_mode != mode_64bit) |
15923 | reg &= 7; | |
15924 | else if (vex.evex && !vex.v) | |
15925 | reg += 16; | |
43234a1e | 15926 | |
539f890d L |
15927 | if (bytemode == vex_scalar_mode) |
15928 | { | |
15929 | oappend (names_xmm[reg]); | |
15930 | return; | |
15931 | } | |
15932 | ||
c0f3af97 L |
15933 | switch (vex.length) |
15934 | { | |
15935 | case 128: | |
15936 | switch (bytemode) | |
15937 | { | |
15938 | case vex_mode: | |
15939 | case vex128_mode: | |
6c30d220 | 15940 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15941 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15942 | names = names_xmm; |
15943 | break; | |
15944 | case dq_mode: | |
390a6789 | 15945 | if (rex & REX_W) |
cb21baef L |
15946 | names = names64; |
15947 | else | |
15948 | names = names32; | |
c0f3af97 | 15949 | break; |
1ba585e8 | 15950 | case mask_bd_mode: |
43234a1e | 15951 | case mask_mode: |
9889cbb1 L |
15952 | if (reg > 0x7) |
15953 | { | |
15954 | oappend ("(bad)"); | |
15955 | return; | |
15956 | } | |
43234a1e L |
15957 | names = names_mask; |
15958 | break; | |
c0f3af97 L |
15959 | default: |
15960 | abort (); | |
15961 | return; | |
15962 | } | |
c0f3af97 L |
15963 | break; |
15964 | case 256: | |
15965 | switch (bytemode) | |
15966 | { | |
15967 | case vex_mode: | |
15968 | case vex256_mode: | |
6c30d220 L |
15969 | names = names_ymm; |
15970 | break; | |
15971 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15972 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15973 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15974 | break; |
1ba585e8 | 15975 | case mask_bd_mode: |
43234a1e | 15976 | case mask_mode: |
9889cbb1 L |
15977 | if (reg > 0x7) |
15978 | { | |
15979 | oappend ("(bad)"); | |
15980 | return; | |
15981 | } | |
43234a1e L |
15982 | names = names_mask; |
15983 | break; | |
c0f3af97 | 15984 | default: |
a37a2806 NC |
15985 | /* See PR binutils/20893 for a reproducer. */ |
15986 | oappend ("(bad)"); | |
c0f3af97 L |
15987 | return; |
15988 | } | |
c0f3af97 | 15989 | break; |
43234a1e L |
15990 | case 512: |
15991 | names = names_zmm; | |
15992 | break; | |
c0f3af97 L |
15993 | default: |
15994 | abort (); | |
15995 | break; | |
15996 | } | |
539f890d | 15997 | oappend (names[reg]); |
c0f3af97 L |
15998 | } |
15999 | ||
922d8de8 DR |
16000 | /* Get the VEX immediate byte without moving codep. */ |
16001 | ||
16002 | static unsigned char | |
ccc5981b | 16003 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
16004 | { |
16005 | int bytes_before_imm = 0; | |
16006 | ||
922d8de8 DR |
16007 | if (modrm.mod != 3) |
16008 | { | |
16009 | /* There are SIB/displacement bytes. */ | |
16010 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 16011 | { |
922d8de8 | 16012 | /* 32/64 bit address mode */ |
6c067bbb | 16013 | int base = modrm.rm; |
922d8de8 DR |
16014 | |
16015 | /* Check SIB byte. */ | |
6c067bbb RM |
16016 | if (base == 4) |
16017 | { | |
16018 | FETCH_DATA (the_info, codep + 1); | |
16019 | base = *codep & 7; | |
16020 | /* When decoding the third source, don't increase | |
16021 | bytes_before_imm as this has already been incremented | |
16022 | by one in OP_E_memory while decoding the second | |
16023 | source operand. */ | |
16024 | if (opnum == 0) | |
16025 | bytes_before_imm++; | |
16026 | } | |
16027 | ||
16028 | /* Don't increase bytes_before_imm when decoding the third source, | |
16029 | it has already been incremented by OP_E_memory while decoding | |
16030 | the second source operand. */ | |
16031 | if (opnum == 0) | |
16032 | { | |
16033 | switch (modrm.mod) | |
16034 | { | |
16035 | case 0: | |
16036 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
16037 | SIB == 5, there is a 4 byte displacement. */ | |
16038 | if (base != 5) | |
16039 | /* No displacement. */ | |
16040 | break; | |
1a0670f3 | 16041 | /* Fall through. */ |
6c067bbb RM |
16042 | case 2: |
16043 | /* 4 byte displacement. */ | |
16044 | bytes_before_imm += 4; | |
16045 | break; | |
16046 | case 1: | |
16047 | /* 1 byte displacement. */ | |
16048 | bytes_before_imm++; | |
16049 | break; | |
16050 | } | |
16051 | } | |
16052 | } | |
922d8de8 | 16053 | else |
02e647f9 SP |
16054 | { |
16055 | /* 16 bit address mode */ | |
6c067bbb RM |
16056 | /* Don't increase bytes_before_imm when decoding the third source, |
16057 | it has already been incremented by OP_E_memory while decoding | |
16058 | the second source operand. */ | |
16059 | if (opnum == 0) | |
16060 | { | |
02e647f9 SP |
16061 | switch (modrm.mod) |
16062 | { | |
16063 | case 0: | |
16064 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
16065 | if (modrm.rm != 6) | |
16066 | /* No displacement. */ | |
16067 | break; | |
1a0670f3 | 16068 | /* Fall through. */ |
02e647f9 SP |
16069 | case 2: |
16070 | /* 2 byte displacement. */ | |
16071 | bytes_before_imm += 2; | |
16072 | break; | |
16073 | case 1: | |
16074 | /* 1 byte displacement: when decoding the third source, | |
16075 | don't increase bytes_before_imm as this has already | |
16076 | been incremented by one in OP_E_memory while decoding | |
16077 | the second source operand. */ | |
16078 | if (opnum == 0) | |
16079 | bytes_before_imm++; | |
ccc5981b | 16080 | |
02e647f9 SP |
16081 | break; |
16082 | } | |
922d8de8 DR |
16083 | } |
16084 | } | |
16085 | } | |
16086 | ||
16087 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
16088 | return codep [bytes_before_imm]; | |
16089 | } | |
16090 | ||
16091 | static void | |
16092 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
16093 | { | |
b9733481 L |
16094 | const char **names; |
16095 | ||
922d8de8 DR |
16096 | if (reg == -1 && modrm.mod != 3) |
16097 | { | |
16098 | OP_E_memory (bytemode, sizeflag); | |
16099 | return; | |
16100 | } | |
16101 | else | |
16102 | { | |
16103 | if (reg == -1) | |
16104 | { | |
16105 | reg = modrm.rm; | |
16106 | USED_REX (REX_B); | |
16107 | if (rex & REX_B) | |
16108 | reg += 8; | |
16109 | } | |
5f847646 JB |
16110 | if (address_mode != mode_64bit) |
16111 | reg &= 7; | |
922d8de8 DR |
16112 | } |
16113 | ||
16114 | switch (vex.length) | |
16115 | { | |
16116 | case 128: | |
b9733481 | 16117 | names = names_xmm; |
922d8de8 DR |
16118 | break; |
16119 | case 256: | |
b9733481 | 16120 | names = names_ymm; |
922d8de8 DR |
16121 | break; |
16122 | default: | |
16123 | abort (); | |
16124 | } | |
b9733481 | 16125 | oappend (names[reg]); |
922d8de8 DR |
16126 | } |
16127 | ||
a683cc34 SP |
16128 | static void |
16129 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
16130 | { | |
16131 | int reg = -1; | |
16132 | static unsigned char vex_imm8; | |
16133 | ||
16134 | if (vex_w_done == 0) | |
16135 | { | |
16136 | vex_w_done = 1; | |
16137 | ||
16138 | /* Skip mod/rm byte. */ | |
16139 | MODRM_CHECK; | |
16140 | codep++; | |
16141 | ||
16142 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16143 | ||
16144 | if (vex.w) | |
16145 | reg = vex_imm8 >> 4; | |
16146 | ||
16147 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16148 | } | |
16149 | else if (vex_w_done == 1) | |
16150 | { | |
16151 | vex_w_done = 2; | |
16152 | ||
16153 | if (!vex.w) | |
16154 | reg = vex_imm8 >> 4; | |
16155 | ||
16156 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16157 | } | |
16158 | else | |
16159 | { | |
16160 | /* Output the imm8 directly. */ | |
16161 | scratchbuf[0] = '$'; | |
16162 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16163 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16164 | scratchbuf[0] = '\0'; |
16165 | codep++; | |
16166 | } | |
16167 | } | |
16168 | ||
5dd85c99 SP |
16169 | static void |
16170 | OP_Vex_2src (int bytemode, int sizeflag) | |
16171 | { | |
16172 | if (modrm.mod == 3) | |
16173 | { | |
b9733481 | 16174 | int reg = modrm.rm; |
5dd85c99 | 16175 | USED_REX (REX_B); |
b9733481 L |
16176 | if (rex & REX_B) |
16177 | reg += 8; | |
16178 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16179 | } |
16180 | else | |
16181 | { | |
16182 | if (intel_syntax | |
16183 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16184 | { | |
16185 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16186 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16187 | } | |
16188 | OP_E (bytemode, sizeflag); | |
16189 | } | |
16190 | } | |
16191 | ||
16192 | static void | |
16193 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16194 | { | |
16195 | if (modrm.mod == 3) | |
16196 | { | |
16197 | /* Skip mod/rm byte. */ | |
16198 | MODRM_CHECK; | |
16199 | codep++; | |
16200 | } | |
16201 | ||
16202 | if (vex.w) | |
5f847646 JB |
16203 | { |
16204 | unsigned int reg = vex.register_specifier; | |
16205 | ||
16206 | if (address_mode != mode_64bit) | |
16207 | reg &= 7; | |
16208 | oappend (names_xmm[reg]); | |
16209 | } | |
5dd85c99 SP |
16210 | else |
16211 | OP_Vex_2src (bytemode, sizeflag); | |
16212 | } | |
16213 | ||
16214 | static void | |
16215 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16216 | { | |
16217 | if (vex.w) | |
16218 | OP_Vex_2src (bytemode, sizeflag); | |
16219 | else | |
5f847646 JB |
16220 | { |
16221 | unsigned int reg = vex.register_specifier; | |
16222 | ||
16223 | if (address_mode != mode_64bit) | |
16224 | reg &= 7; | |
16225 | oappend (names_xmm[reg]); | |
16226 | } | |
5dd85c99 SP |
16227 | } |
16228 | ||
922d8de8 DR |
16229 | static void |
16230 | OP_EX_VexW (int bytemode, int sizeflag) | |
16231 | { | |
16232 | int reg = -1; | |
16233 | ||
16234 | if (!vex_w_done) | |
16235 | { | |
41effecb SP |
16236 | /* Skip mod/rm byte. */ |
16237 | MODRM_CHECK; | |
16238 | codep++; | |
16239 | ||
922d8de8 | 16240 | if (vex.w) |
ccc5981b | 16241 | reg = get_vex_imm8 (sizeflag, 0) >> 4; |
922d8de8 DR |
16242 | } |
16243 | else | |
16244 | { | |
16245 | if (!vex.w) | |
ccc5981b | 16246 | reg = get_vex_imm8 (sizeflag, 1) >> 4; |
922d8de8 DR |
16247 | } |
16248 | ||
16249 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
922d8de8 | 16250 | |
3a2430e0 JB |
16251 | if (vex_w_done) |
16252 | codep++; | |
16253 | vex_w_done = 1; | |
922d8de8 DR |
16254 | } |
16255 | ||
c0f3af97 L |
16256 | static void |
16257 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16258 | { | |
16259 | int reg; | |
b9733481 L |
16260 | const char **names; |
16261 | ||
c0f3af97 L |
16262 | FETCH_DATA (the_info, codep + 1); |
16263 | reg = *codep++; | |
16264 | ||
16265 | if (bytemode != x_mode) | |
16266 | abort (); | |
16267 | ||
c0f3af97 | 16268 | reg >>= 4; |
5f847646 JB |
16269 | if (address_mode != mode_64bit) |
16270 | reg &= 7; | |
dae39acc | 16271 | |
c0f3af97 L |
16272 | switch (vex.length) |
16273 | { | |
16274 | case 128: | |
b9733481 | 16275 | names = names_xmm; |
c0f3af97 L |
16276 | break; |
16277 | case 256: | |
b9733481 | 16278 | names = names_ymm; |
c0f3af97 L |
16279 | break; |
16280 | default: | |
16281 | abort (); | |
16282 | } | |
b9733481 | 16283 | oappend (names[reg]); |
c0f3af97 L |
16284 | } |
16285 | ||
922d8de8 DR |
16286 | static void |
16287 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16288 | { | |
16289 | /* Turn off the REX.W bit since it is used for swapping operands | |
16290 | now. */ | |
16291 | rex &= ~REX_W; | |
16292 | OP_XMM (bytemode, sizeflag); | |
16293 | } | |
16294 | ||
c0f3af97 L |
16295 | static void |
16296 | OP_EX_Vex (int bytemode, int sizeflag) | |
16297 | { | |
16298 | if (modrm.mod != 3) | |
16299 | { | |
16300 | if (vex.register_specifier != 0) | |
16301 | BadOp (); | |
16302 | need_vex_reg = 0; | |
16303 | } | |
16304 | OP_EX (bytemode, sizeflag); | |
16305 | } | |
16306 | ||
16307 | static void | |
16308 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16309 | { | |
16310 | if (modrm.mod != 3) | |
16311 | { | |
16312 | if (vex.register_specifier != 0) | |
16313 | BadOp (); | |
16314 | need_vex_reg = 0; | |
16315 | } | |
16316 | OP_XMM (bytemode, sizeflag); | |
16317 | } | |
16318 | ||
ea397f5b L |
16319 | static struct op vex_cmp_op[] = |
16320 | { | |
16321 | { STRING_COMMA_LEN ("eq") }, | |
16322 | { STRING_COMMA_LEN ("lt") }, | |
16323 | { STRING_COMMA_LEN ("le") }, | |
16324 | { STRING_COMMA_LEN ("unord") }, | |
16325 | { STRING_COMMA_LEN ("neq") }, | |
16326 | { STRING_COMMA_LEN ("nlt") }, | |
16327 | { STRING_COMMA_LEN ("nle") }, | |
16328 | { STRING_COMMA_LEN ("ord") }, | |
16329 | { STRING_COMMA_LEN ("eq_uq") }, | |
16330 | { STRING_COMMA_LEN ("nge") }, | |
16331 | { STRING_COMMA_LEN ("ngt") }, | |
16332 | { STRING_COMMA_LEN ("false") }, | |
16333 | { STRING_COMMA_LEN ("neq_oq") }, | |
16334 | { STRING_COMMA_LEN ("ge") }, | |
16335 | { STRING_COMMA_LEN ("gt") }, | |
16336 | { STRING_COMMA_LEN ("true") }, | |
16337 | { STRING_COMMA_LEN ("eq_os") }, | |
16338 | { STRING_COMMA_LEN ("lt_oq") }, | |
16339 | { STRING_COMMA_LEN ("le_oq") }, | |
16340 | { STRING_COMMA_LEN ("unord_s") }, | |
16341 | { STRING_COMMA_LEN ("neq_us") }, | |
16342 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16343 | { STRING_COMMA_LEN ("nle_uq") }, | |
16344 | { STRING_COMMA_LEN ("ord_s") }, | |
16345 | { STRING_COMMA_LEN ("eq_us") }, | |
16346 | { STRING_COMMA_LEN ("nge_uq") }, | |
16347 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16348 | { STRING_COMMA_LEN ("false_os") }, | |
16349 | { STRING_COMMA_LEN ("neq_os") }, | |
16350 | { STRING_COMMA_LEN ("ge_oq") }, | |
16351 | { STRING_COMMA_LEN ("gt_oq") }, | |
16352 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16353 | }; |
16354 | ||
16355 | static void | |
16356 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16357 | { | |
16358 | unsigned int cmp_type; | |
16359 | ||
16360 | FETCH_DATA (the_info, codep + 1); | |
16361 | cmp_type = *codep++ & 0xff; | |
16362 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16363 | { | |
16364 | char suffix [3]; | |
ea397f5b | 16365 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16366 | suffix[0] = p[0]; |
16367 | suffix[1] = p[1]; | |
16368 | suffix[2] = '\0'; | |
ea397f5b L |
16369 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16370 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16371 | } |
16372 | else | |
16373 | { | |
16374 | /* We have a reserved extension byte. Output it directly. */ | |
16375 | scratchbuf[0] = '$'; | |
16376 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16377 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16378 | scratchbuf[0] = '\0'; |
16379 | } | |
16380 | } | |
16381 | ||
43234a1e L |
16382 | static void |
16383 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16384 | int sizeflag ATTRIBUTE_UNUSED) | |
16385 | { | |
16386 | unsigned int cmp_type; | |
16387 | ||
16388 | if (!vex.evex) | |
16389 | abort (); | |
16390 | ||
16391 | FETCH_DATA (the_info, codep + 1); | |
16392 | cmp_type = *codep++ & 0xff; | |
16393 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16394 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16395 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16396 | && cmp_type != 3 | |
16397 | && cmp_type != 7) | |
16398 | { | |
16399 | char suffix [3]; | |
16400 | char *p = mnemonicendp - 2; | |
16401 | ||
16402 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16403 | if (p[0] == 'p') | |
16404 | { | |
16405 | p++; | |
16406 | suffix[0] = p[0]; | |
16407 | suffix[1] = '\0'; | |
16408 | } | |
16409 | else | |
16410 | { | |
16411 | suffix[0] = p[0]; | |
16412 | suffix[1] = p[1]; | |
16413 | suffix[2] = '\0'; | |
16414 | } | |
16415 | ||
16416 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16417 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16418 | } | |
be92cb14 JB |
16419 | else |
16420 | { | |
16421 | /* We have a reserved extension byte. Output it directly. */ | |
16422 | scratchbuf[0] = '$'; | |
16423 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16424 | oappend_maybe_intel (scratchbuf); | |
16425 | scratchbuf[0] = '\0'; | |
16426 | } | |
16427 | } | |
16428 | ||
16429 | static const struct op xop_cmp_op[] = | |
16430 | { | |
16431 | { STRING_COMMA_LEN ("lt") }, | |
16432 | { STRING_COMMA_LEN ("le") }, | |
16433 | { STRING_COMMA_LEN ("gt") }, | |
16434 | { STRING_COMMA_LEN ("ge") }, | |
16435 | { STRING_COMMA_LEN ("eq") }, | |
16436 | { STRING_COMMA_LEN ("neq") }, | |
16437 | { STRING_COMMA_LEN ("false") }, | |
16438 | { STRING_COMMA_LEN ("true") } | |
16439 | }; | |
16440 | ||
16441 | static void | |
16442 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16443 | int sizeflag ATTRIBUTE_UNUSED) | |
16444 | { | |
16445 | unsigned int cmp_type; | |
16446 | ||
16447 | FETCH_DATA (the_info, codep + 1); | |
16448 | cmp_type = *codep++ & 0xff; | |
16449 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16450 | { | |
16451 | char suffix[3]; | |
16452 | char *p = mnemonicendp - 2; | |
16453 | ||
16454 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16455 | if (p[0] == 'm') | |
16456 | { | |
16457 | p++; | |
16458 | suffix[0] = p[0]; | |
16459 | suffix[1] = '\0'; | |
16460 | } | |
16461 | else | |
16462 | { | |
16463 | suffix[0] = p[0]; | |
16464 | suffix[1] = p[1]; | |
16465 | suffix[2] = '\0'; | |
16466 | } | |
16467 | ||
16468 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16469 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16470 | } | |
43234a1e L |
16471 | else |
16472 | { | |
16473 | /* We have a reserved extension byte. Output it directly. */ | |
16474 | scratchbuf[0] = '$'; | |
16475 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16476 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16477 | scratchbuf[0] = '\0'; |
16478 | } | |
16479 | } | |
16480 | ||
ea397f5b L |
16481 | static const struct op pclmul_op[] = |
16482 | { | |
16483 | { STRING_COMMA_LEN ("lql") }, | |
16484 | { STRING_COMMA_LEN ("hql") }, | |
16485 | { STRING_COMMA_LEN ("lqh") }, | |
16486 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16487 | }; |
16488 | ||
16489 | static void | |
16490 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16491 | int sizeflag ATTRIBUTE_UNUSED) | |
16492 | { | |
16493 | unsigned int pclmul_type; | |
16494 | ||
16495 | FETCH_DATA (the_info, codep + 1); | |
16496 | pclmul_type = *codep++ & 0xff; | |
16497 | switch (pclmul_type) | |
16498 | { | |
16499 | case 0x10: | |
16500 | pclmul_type = 2; | |
16501 | break; | |
16502 | case 0x11: | |
16503 | pclmul_type = 3; | |
16504 | break; | |
16505 | default: | |
16506 | break; | |
7bb15c6f | 16507 | } |
c0f3af97 L |
16508 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16509 | { | |
16510 | char suffix [4]; | |
ea397f5b | 16511 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16512 | suffix[0] = p[0]; |
16513 | suffix[1] = p[1]; | |
16514 | suffix[2] = p[2]; | |
16515 | suffix[3] = '\0'; | |
ea397f5b L |
16516 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16517 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16518 | } |
16519 | else | |
16520 | { | |
16521 | /* We have a reserved extension byte. Output it directly. */ | |
16522 | scratchbuf[0] = '$'; | |
16523 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16524 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16525 | scratchbuf[0] = '\0'; |
16526 | } | |
16527 | } | |
16528 | ||
f1f8f695 L |
16529 | static void |
16530 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16531 | { | |
16532 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16533 | char *p = mnemonicendp; |
f1f8f695 L |
16534 | |
16535 | switch (bytemode) | |
16536 | { | |
16537 | case v_mode: | |
16538 | if (intel_syntax) | |
ea397f5b | 16539 | goto skip; |
f1f8f695 L |
16540 | |
16541 | USED_REX (REX_W); | |
16542 | if (sizeflag & SUFFIX_ALWAYS) | |
16543 | { | |
16544 | if (rex & REX_W) | |
16545 | *p++ = 'q'; | |
f1f8f695 | 16546 | else |
f16cd0d5 L |
16547 | { |
16548 | if (sizeflag & DFLAG) | |
16549 | *p++ = 'l'; | |
16550 | else | |
16551 | *p++ = 'w'; | |
16552 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16553 | } | |
f1f8f695 | 16554 | } |
f1f8f695 L |
16555 | break; |
16556 | default: | |
16557 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16558 | break; | |
16559 | } | |
ea397f5b | 16560 | mnemonicendp = p; |
f1f8f695 L |
16561 | *p = '\0'; |
16562 | ||
ea397f5b | 16563 | skip: |
f1f8f695 L |
16564 | OP_M (bytemode, sizeflag); |
16565 | } | |
f88c9eb0 SP |
16566 | |
16567 | static void | |
16568 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16569 | { | |
16570 | int reg; | |
16571 | const char **names; | |
16572 | ||
16573 | /* Skip mod/rm byte. */ | |
16574 | MODRM_CHECK; | |
16575 | codep++; | |
16576 | ||
390a6789 | 16577 | if (rex & REX_W) |
f88c9eb0 | 16578 | names = names64; |
f88c9eb0 | 16579 | else |
ce7d077e | 16580 | names = names32; |
f88c9eb0 SP |
16581 | |
16582 | reg = modrm.rm; | |
16583 | USED_REX (REX_B); | |
16584 | if (rex & REX_B) | |
16585 | reg += 8; | |
16586 | ||
16587 | oappend (names[reg]); | |
16588 | } | |
16589 | ||
16590 | static void | |
16591 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16592 | { | |
16593 | const char **names; | |
5f847646 | 16594 | unsigned int reg = vex.register_specifier; |
f88c9eb0 | 16595 | |
390a6789 | 16596 | if (rex & REX_W) |
f88c9eb0 | 16597 | names = names64; |
f88c9eb0 | 16598 | else |
ce7d077e | 16599 | names = names32; |
f88c9eb0 | 16600 | |
5f847646 JB |
16601 | if (address_mode != mode_64bit) |
16602 | reg &= 7; | |
16603 | oappend (names[reg]); | |
f88c9eb0 | 16604 | } |
43234a1e L |
16605 | |
16606 | static void | |
16607 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16608 | { | |
16609 | if (!vex.evex | |
1ba585e8 | 16610 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16611 | abort (); |
16612 | ||
16613 | USED_REX (REX_R); | |
16614 | if ((rex & REX_R) != 0 || !vex.r) | |
16615 | { | |
16616 | BadOp (); | |
16617 | return; | |
16618 | } | |
16619 | ||
16620 | oappend (names_mask [modrm.reg]); | |
16621 | } | |
16622 | ||
16623 | static void | |
16624 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16625 | { | |
16626 | if (!vex.evex | |
16627 | || (bytemode != evex_rounding_mode | |
70df6fc9 | 16628 | && bytemode != evex_rounding_64_mode |
43234a1e L |
16629 | && bytemode != evex_sae_mode)) |
16630 | abort (); | |
16631 | if (modrm.mod == 3 && vex.b) | |
16632 | switch (bytemode) | |
16633 | { | |
70df6fc9 L |
16634 | case evex_rounding_64_mode: |
16635 | if (address_mode != mode_64bit) | |
16636 | { | |
16637 | oappend ("(bad)"); | |
16638 | break; | |
16639 | } | |
16640 | /* Fall through. */ | |
43234a1e L |
16641 | case evex_rounding_mode: |
16642 | oappend (names_rounding[vex.ll]); | |
16643 | break; | |
16644 | case evex_sae_mode: | |
16645 | oappend ("{sae}"); | |
16646 | break; | |
16647 | default: | |
16648 | break; | |
16649 | } | |
16650 | } |