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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
b3adc24a | 2 | Copyright (C) 1988-2020 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 RH |
41 | |
42 | #include <setjmp.h> | |
43 | ||
26ca5450 AJ |
44 | static int print_insn (bfd_vma, disassemble_info *); |
45 | static void dofloat (int); | |
46 | static void OP_ST (int, int); | |
47 | static void OP_STi (int, int); | |
48 | static int putop (const char *, int); | |
49 | static void oappend (const char *); | |
50 | static void append_seg (void); | |
51 | static void OP_indirE (int, int); | |
52 | static void print_operand_value (char *, int, bfd_vma); | |
c0f3af97 | 53 | static void OP_E_register (int, int); |
c1e679ec | 54 | static void OP_E_memory (int, int); |
5d669648 | 55 | static void print_displacement (char *, bfd_vma); |
26ca5450 AJ |
56 | static void OP_E (int, int); |
57 | static void OP_G (int, int); | |
58 | static bfd_vma get64 (void); | |
59 | static bfd_signed_vma get32 (void); | |
60 | static bfd_signed_vma get32s (void); | |
61 | static int get16 (void); | |
62 | static void set_op (bfd_vma, int); | |
b844680a | 63 | static void OP_Skip_MODRM (int, int); |
26ca5450 AJ |
64 | static void OP_REG (int, int); |
65 | static void OP_IMREG (int, int); | |
66 | static void OP_I (int, int); | |
67 | static void OP_I64 (int, int); | |
68 | static void OP_sI (int, int); | |
69 | static void OP_J (int, int); | |
70 | static void OP_SEG (int, int); | |
71 | static void OP_DIR (int, int); | |
72 | static void OP_OFF (int, int); | |
73 | static void OP_OFF64 (int, int); | |
74 | static void ptr_reg (int, int); | |
75 | static void OP_ESreg (int, int); | |
76 | static void OP_DSreg (int, int); | |
77 | static void OP_C (int, int); | |
78 | static void OP_D (int, int); | |
79 | static void OP_T (int, int); | |
6f74c397 | 80 | static void OP_R (int, int); |
26ca5450 AJ |
81 | static void OP_MMX (int, int); |
82 | static void OP_XMM (int, int); | |
83 | static void OP_EM (int, int); | |
84 | static void OP_EX (int, int); | |
4d9567e0 MM |
85 | static void OP_EMC (int,int); |
86 | static void OP_MXC (int,int); | |
26ca5450 AJ |
87 | static void OP_MS (int, int); |
88 | static void OP_XS (int, int); | |
cc0ec051 | 89 | static void OP_M (int, int); |
c0f3af97 L |
90 | static void OP_VEX (int, int); |
91 | static void OP_EX_Vex (int, int); | |
a683cc34 | 92 | static void OP_EX_VexImmW (int, int); |
c0f3af97 | 93 | static void OP_XMM_Vex (int, int); |
922d8de8 | 94 | static void OP_XMM_VexW (int, int); |
43234a1e | 95 | static void OP_Rounding (int, int); |
c0f3af97 L |
96 | static void OP_REG_VexI4 (int, int); |
97 | static void PCLMUL_Fixup (int, int); | |
c0f3af97 | 98 | static void VCMP_Fixup (int, int); |
43234a1e | 99 | static void VPCMP_Fixup (int, int); |
be92cb14 | 100 | static void VPCOM_Fixup (int, int); |
cc0ec051 | 101 | static void OP_0f07 (int, int); |
b844680a L |
102 | static void OP_Monitor (int, int); |
103 | static void OP_Mwait (int, int); | |
46e883c5 L |
104 | static void NOP_Fixup1 (int, int); |
105 | static void NOP_Fixup2 (int, int); | |
26ca5450 | 106 | static void OP_3DNowSuffix (int, int); |
ad19981d | 107 | static void CMP_Fixup (int, int); |
26ca5450 | 108 | static void BadOp (void); |
35c52694 | 109 | static void REP_Fixup (int, int); |
d835a58b | 110 | static void SEP_Fixup (int, int); |
7e8b059b | 111 | static void BND_Fixup (int, int); |
04ef582a | 112 | static void NOTRACK_Fixup (int, int); |
42164a71 L |
113 | static void HLE_Fixup1 (int, int); |
114 | static void HLE_Fixup2 (int, int); | |
115 | static void HLE_Fixup3 (int, int); | |
f5804c90 | 116 | static void CMPXCHG8B_Fixup (int, int); |
42903f7f | 117 | static void XMM_Fixup (int, int); |
381d071f | 118 | static void CRC32_Fixup (int, int); |
eacc9c89 | 119 | static void FXSAVE_Fixup (int, int); |
15c7c1d8 | 120 | static void PCMPESTR_Fixup (int, int); |
f88c9eb0 SP |
121 | static void OP_LWPCB_E (int, int); |
122 | static void OP_LWP_E (int, int); | |
5dd85c99 SP |
123 | static void OP_Vex_2src_1 (int, int); |
124 | static void OP_Vex_2src_2 (int, int); | |
c1e679ec | 125 | |
f1f8f695 | 126 | static void MOVBE_Fixup (int, int); |
bc31405e | 127 | static void MOVSXD_Fixup (int, int); |
252b5132 | 128 | |
43234a1e L |
129 | static void OP_Mask (int, int); |
130 | ||
6608db57 | 131 | struct dis_private { |
252b5132 RH |
132 | /* Points to first byte not fetched. */ |
133 | bfd_byte *max_fetched; | |
0b1cf022 | 134 | bfd_byte the_buffer[MAX_MNEM_SIZE]; |
252b5132 | 135 | bfd_vma insn_start; |
e396998b | 136 | int orig_sizeflag; |
8df14d78 | 137 | OPCODES_SIGJMP_BUF bailout; |
252b5132 RH |
138 | }; |
139 | ||
cb712a9e L |
140 | enum address_mode |
141 | { | |
142 | mode_16bit, | |
143 | mode_32bit, | |
144 | mode_64bit | |
145 | }; | |
146 | ||
147 | enum address_mode address_mode; | |
52b15da3 | 148 | |
5076851f ILT |
149 | /* Flags for the prefixes for the current instruction. See below. */ |
150 | static int prefixes; | |
151 | ||
52b15da3 JH |
152 | /* REX prefix the current instruction. See below. */ |
153 | static int rex; | |
154 | /* Bits of REX we've already used. */ | |
155 | static int rex_used; | |
52b15da3 JH |
156 | /* Mark parts used in the REX prefix. When we are testing for |
157 | empty prefix (for 8bit register REX extension), just mask it | |
158 | out. Otherwise test for REX bit is excuse for existence of REX | |
159 | only in case value is nonzero. */ | |
160 | #define USED_REX(value) \ | |
161 | { \ | |
162 | if (value) \ | |
161a04f6 L |
163 | { \ |
164 | if ((rex & value)) \ | |
165 | rex_used |= (value) | REX_OPCODE; \ | |
166 | } \ | |
52b15da3 | 167 | else \ |
161a04f6 | 168 | rex_used |= REX_OPCODE; \ |
52b15da3 JH |
169 | } |
170 | ||
7d421014 ILT |
171 | /* Flags for prefixes which we somehow handled when printing the |
172 | current instruction. */ | |
173 | static int used_prefixes; | |
174 | ||
5076851f ILT |
175 | /* Flags stored in PREFIXES. */ |
176 | #define PREFIX_REPZ 1 | |
177 | #define PREFIX_REPNZ 2 | |
178 | #define PREFIX_LOCK 4 | |
179 | #define PREFIX_CS 8 | |
180 | #define PREFIX_SS 0x10 | |
181 | #define PREFIX_DS 0x20 | |
182 | #define PREFIX_ES 0x40 | |
183 | #define PREFIX_FS 0x80 | |
184 | #define PREFIX_GS 0x100 | |
185 | #define PREFIX_DATA 0x200 | |
186 | #define PREFIX_ADDR 0x400 | |
187 | #define PREFIX_FWAIT 0x800 | |
188 | ||
252b5132 RH |
189 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
190 | to ADDR (exclusive) are valid. Returns 1 for success, longjmps | |
191 | on error. */ | |
192 | #define FETCH_DATA(info, addr) \ | |
6608db57 | 193 | ((addr) <= ((struct dis_private *) (info->private_data))->max_fetched \ |
252b5132 RH |
194 | ? 1 : fetch_data ((info), (addr))) |
195 | ||
196 | static int | |
26ca5450 | 197 | fetch_data (struct disassemble_info *info, bfd_byte *addr) |
252b5132 RH |
198 | { |
199 | int status; | |
6608db57 | 200 | struct dis_private *priv = (struct dis_private *) info->private_data; |
252b5132 RH |
201 | bfd_vma start = priv->insn_start + (priv->max_fetched - priv->the_buffer); |
202 | ||
0b1cf022 | 203 | if (addr <= priv->the_buffer + MAX_MNEM_SIZE) |
272c9217 JB |
204 | status = (*info->read_memory_func) (start, |
205 | priv->max_fetched, | |
206 | addr - priv->max_fetched, | |
207 | info); | |
208 | else | |
209 | status = -1; | |
252b5132 RH |
210 | if (status != 0) |
211 | { | |
7d421014 | 212 | /* If we did manage to read at least one byte, then |
db6eb5be AM |
213 | print_insn_i386 will do something sensible. Otherwise, print |
214 | an error. We do that here because this is where we know | |
215 | STATUS. */ | |
7d421014 | 216 | if (priv->max_fetched == priv->the_buffer) |
5076851f | 217 | (*info->memory_error_func) (status, start, info); |
8df14d78 | 218 | OPCODES_SIGLONGJMP (priv->bailout, 1); |
252b5132 RH |
219 | } |
220 | else | |
221 | priv->max_fetched = addr; | |
222 | return 1; | |
223 | } | |
224 | ||
bf890a93 | 225 | /* Possible values for prefix requirement. */ |
507bd325 L |
226 | #define PREFIX_IGNORED_SHIFT 16 |
227 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
228 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
229 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
230 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
231 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
232 | ||
233 | /* Opcode prefixes. */ | |
234 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
235 | | PREFIX_REPNZ \ | |
236 | | PREFIX_DATA) | |
237 | ||
238 | /* Prefixes ignored. */ | |
239 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
240 | | PREFIX_IGNORED_REPNZ \ | |
241 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 242 | |
ce518a5f | 243 | #define XX { NULL, 0 } |
507bd325 | 244 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
245 | |
246 | #define Eb { OP_E, b_mode } | |
7e8b059b | 247 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 248 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 249 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 250 | #define Ev { OP_E, v_mode } |
de89d0a3 | 251 | #define Eva { OP_E, va_mode } |
7e8b059b | 252 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 253 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
254 | #define Ed { OP_E, d_mode } |
255 | #define Edq { OP_E, dq_mode } | |
256 | #define Edqw { OP_E, dqw_mode } | |
42903f7f | 257 | #define Edqb { OP_E, dqb_mode } |
1ba585e8 IT |
258 | #define Edb { OP_E, db_mode } |
259 | #define Edw { OP_E, dw_mode } | |
42903f7f | 260 | #define Edqd { OP_E, dqd_mode } |
09335d05 | 261 | #define Eq { OP_E, q_mode } |
07f5af7d | 262 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
263 | #define indirEp { OP_indirE, f_mode } |
264 | #define stackEv { OP_E, stack_v_mode } | |
265 | #define Em { OP_E, m_mode } | |
266 | #define Ew { OP_E, w_mode } | |
267 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 268 | #define Ma { OP_M, a_mode } |
b844680a | 269 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 270 | #define Md { OP_M, d_mode } |
f1f8f695 | 271 | #define Mo { OP_M, o_mode } |
ce518a5f L |
272 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
273 | #define Mq { OP_M, q_mode } | |
d276ec69 | 274 | #define Mv_bnd { OP_M, v_bndmk_mode } |
4ee52178 | 275 | #define Mx { OP_M, x_mode } |
c0f3af97 | 276 | #define Mxmm { OP_M, xmm_mode } |
ce518a5f | 277 | #define Gb { OP_G, b_mode } |
7e8b059b | 278 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
279 | #define Gv { OP_G, v_mode } |
280 | #define Gd { OP_G, d_mode } | |
281 | #define Gdq { OP_G, dq_mode } | |
282 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 283 | #define Gva { OP_G, va_mode } |
ce518a5f | 284 | #define Gw { OP_G, w_mode } |
6f74c397 | 285 | #define Rd { OP_R, d_mode } |
43234a1e | 286 | #define Rdq { OP_R, dq_mode } |
6f74c397 | 287 | #define Rm { OP_R, m_mode } |
ce518a5f L |
288 | #define Ib { OP_I, b_mode } |
289 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 290 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 291 | #define Iv { OP_I, v_mode } |
7bb15c6f | 292 | #define sIv { OP_sI, v_mode } |
ce518a5f | 293 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 294 | #define Id { OP_I, d_mode } |
ce518a5f L |
295 | #define Iw { OP_I, w_mode } |
296 | #define I1 { OP_I, const_1_mode } | |
297 | #define Jb { OP_J, b_mode } | |
298 | #define Jv { OP_J, v_mode } | |
376cd056 | 299 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
300 | #define Cm { OP_C, m_mode } |
301 | #define Dm { OP_D, m_mode } | |
302 | #define Td { OP_T, d_mode } | |
b844680a | 303 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
304 | |
305 | #define RMeAX { OP_REG, eAX_reg } | |
306 | #define RMeBX { OP_REG, eBX_reg } | |
307 | #define RMeCX { OP_REG, eCX_reg } | |
308 | #define RMeDX { OP_REG, eDX_reg } | |
309 | #define RMeSP { OP_REG, eSP_reg } | |
310 | #define RMeBP { OP_REG, eBP_reg } | |
311 | #define RMeSI { OP_REG, eSI_reg } | |
312 | #define RMeDI { OP_REG, eDI_reg } | |
313 | #define RMrAX { OP_REG, rAX_reg } | |
314 | #define RMrBX { OP_REG, rBX_reg } | |
315 | #define RMrCX { OP_REG, rCX_reg } | |
316 | #define RMrDX { OP_REG, rDX_reg } | |
317 | #define RMrSP { OP_REG, rSP_reg } | |
318 | #define RMrBP { OP_REG, rBP_reg } | |
319 | #define RMrSI { OP_REG, rSI_reg } | |
320 | #define RMrDI { OP_REG, rDI_reg } | |
321 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
322 | #define RMCL { OP_REG, cl_reg } |
323 | #define RMDL { OP_REG, dl_reg } | |
324 | #define RMBL { OP_REG, bl_reg } | |
325 | #define RMAH { OP_REG, ah_reg } | |
326 | #define RMCH { OP_REG, ch_reg } | |
327 | #define RMDH { OP_REG, dh_reg } | |
328 | #define RMBH { OP_REG, bh_reg } | |
329 | #define RMAX { OP_REG, ax_reg } | |
330 | #define RMDX { OP_REG, dx_reg } | |
331 | ||
332 | #define eAX { OP_IMREG, eAX_reg } | |
333 | #define eBX { OP_IMREG, eBX_reg } | |
334 | #define eCX { OP_IMREG, eCX_reg } | |
335 | #define eDX { OP_IMREG, eDX_reg } | |
336 | #define eSP { OP_IMREG, eSP_reg } | |
337 | #define eBP { OP_IMREG, eBP_reg } | |
338 | #define eSI { OP_IMREG, eSI_reg } | |
339 | #define eDI { OP_IMREG, eDI_reg } | |
340 | #define AL { OP_IMREG, al_reg } | |
341 | #define CL { OP_IMREG, cl_reg } | |
342 | #define DL { OP_IMREG, dl_reg } | |
343 | #define BL { OP_IMREG, bl_reg } | |
344 | #define AH { OP_IMREG, ah_reg } | |
345 | #define CH { OP_IMREG, ch_reg } | |
346 | #define DH { OP_IMREG, dh_reg } | |
347 | #define BH { OP_IMREG, bh_reg } | |
348 | #define AX { OP_IMREG, ax_reg } | |
349 | #define DX { OP_IMREG, dx_reg } | |
350 | #define zAX { OP_IMREG, z_mode_ax_reg } | |
351 | #define indirDX { OP_IMREG, indir_dx_reg } | |
352 | ||
353 | #define Sw { OP_SEG, w_mode } | |
354 | #define Sv { OP_SEG, v_mode } | |
355 | #define Ap { OP_DIR, 0 } | |
356 | #define Ob { OP_OFF64, b_mode } | |
357 | #define Ov { OP_OFF64, v_mode } | |
358 | #define Xb { OP_DSreg, eSI_reg } | |
359 | #define Xv { OP_DSreg, eSI_reg } | |
360 | #define Xz { OP_DSreg, eSI_reg } | |
361 | #define Yb { OP_ESreg, eDI_reg } | |
362 | #define Yv { OP_ESreg, eDI_reg } | |
363 | #define DSBX { OP_DSreg, eBX_reg } | |
364 | ||
365 | #define es { OP_REG, es_reg } | |
366 | #define ss { OP_REG, ss_reg } | |
367 | #define cs { OP_REG, cs_reg } | |
368 | #define ds { OP_REG, ds_reg } | |
369 | #define fs { OP_REG, fs_reg } | |
370 | #define gs { OP_REG, gs_reg } | |
371 | ||
372 | #define MX { OP_MMX, 0 } | |
373 | #define XM { OP_XMM, 0 } | |
539f890d | 374 | #define XMScalar { OP_XMM, scalar_mode } |
6c30d220 | 375 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 376 | #define XMM { OP_XMM, xmm_mode } |
43234a1e | 377 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 378 | #define EM { OP_EM, v_mode } |
b6169b20 | 379 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 380 | #define EMd { OP_EM, d_mode } |
14051056 | 381 | #define EMx { OP_EM, x_mode } |
53467f57 | 382 | #define EXbScalar { OP_EX, b_scalar_mode } |
8976381e | 383 | #define EXw { OP_EX, w_mode } |
53467f57 | 384 | #define EXwScalar { OP_EX, w_scalar_mode } |
09a2c6cf | 385 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 386 | #define EXdS { OP_EX, d_swap_mode } |
09a2c6cf | 387 | #define EXq { OP_EX, q_mode } |
b6169b20 | 388 | #define EXqS { OP_EX, q_swap_mode } |
09a2c6cf | 389 | #define EXx { OP_EX, x_mode } |
b6169b20 | 390 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 391 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 392 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 393 | #define EXxmmq { OP_EX, xmmq_mode } |
43234a1e | 394 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
395 | #define EXxmm_mb { OP_EX, xmm_mb_mode } |
396 | #define EXxmm_mw { OP_EX, xmm_mw_mode } | |
397 | #define EXxmm_md { OP_EX, xmm_md_mode } | |
398 | #define EXxmm_mq { OP_EX, xmm_mq_mode } | |
399 | #define EXxmmdw { OP_EX, xmmdw_mode } | |
400 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
c0f3af97 | 401 | #define EXymmq { OP_EX, ymmq_mode } |
1c480963 | 402 | #define EXVexWdqScalar { OP_EX, vex_scalar_w_dq_mode } |
43234a1e L |
403 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
404 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
ce518a5f L |
405 | #define MS { OP_MS, v_mode } |
406 | #define XS { OP_XS, v_mode } | |
09335d05 | 407 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 408 | #define MXC { OP_MXC, 0 } |
ce518a5f | 409 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 410 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 411 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 412 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 413 | #define FXSAVE { FXSAVE_Fixup, 0 } |
5dd85c99 SP |
414 | #define Vex_2src_1 { OP_Vex_2src_1, 0 } |
415 | #define Vex_2src_2 { OP_Vex_2src_2, 0 } | |
252b5132 | 416 | |
c0f3af97 | 417 | #define Vex { OP_VEX, vex_mode } |
539f890d | 418 | #define VexScalar { OP_VEX, vex_scalar_mode } |
6c30d220 | 419 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
c0f3af97 L |
420 | #define Vex128 { OP_VEX, vex128_mode } |
421 | #define Vex256 { OP_VEX, vex256_mode } | |
cb21baef | 422 | #define VexGdq { OP_VEX, dq_mode } |
539f890d | 423 | #define EXdVexScalarS { OP_EX_Vex, d_scalar_swap_mode } |
539f890d | 424 | #define EXqVexScalarS { OP_EX_Vex, q_scalar_swap_mode } |
a683cc34 | 425 | #define EXVexImmW { OP_EX_VexImmW, x_mode } |
539f890d | 426 | #define XMVexScalar { OP_XMM_Vex, scalar_mode } |
922d8de8 | 427 | #define XMVexW { OP_XMM_VexW, 0 } |
c0f3af97 L |
428 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
429 | #define PCLMUL { PCLMUL_Fixup, 0 } | |
c0f3af97 | 430 | #define VCMP { VCMP_Fixup, 0 } |
43234a1e | 431 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 432 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
433 | |
434 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 435 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
436 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
437 | ||
438 | #define XMask { OP_Mask, mask_mode } | |
439 | #define MaskG { OP_G, mask_mode } | |
440 | #define MaskE { OP_E, mask_mode } | |
1ba585e8 | 441 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e L |
442 | #define MaskR { OP_R, mask_mode } |
443 | #define MaskVex { OP_VEX, mask_mode } | |
c0f3af97 | 444 | |
6c30d220 | 445 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
5fc35d96 | 446 | #define MVexVSIBDQWpX { OP_M, vex_vsib_d_w_d_mode } |
6c30d220 | 447 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } |
5fc35d96 | 448 | #define MVexVSIBQDWpX { OP_M, vex_vsib_q_w_d_mode } |
6c30d220 | 449 | |
35c52694 | 450 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
451 | #define Xbr { REP_Fixup, eSI_reg } |
452 | #define Xvr { REP_Fixup, eSI_reg } | |
453 | #define Ybr { REP_Fixup, eDI_reg } | |
454 | #define Yvr { REP_Fixup, eDI_reg } | |
455 | #define Yzr { REP_Fixup, eDI_reg } | |
456 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
457 | #define ALr { REP_Fixup, al_reg } | |
458 | #define eAXr { REP_Fixup, eAX_reg } | |
459 | ||
42164a71 L |
460 | /* Used handle HLE prefix for lockable instructions. */ |
461 | #define Ebh1 { HLE_Fixup1, b_mode } | |
462 | #define Evh1 { HLE_Fixup1, v_mode } | |
463 | #define Ebh2 { HLE_Fixup2, b_mode } | |
464 | #define Evh2 { HLE_Fixup2, v_mode } | |
465 | #define Ebh3 { HLE_Fixup3, b_mode } | |
466 | #define Evh3 { HLE_Fixup3, v_mode } | |
467 | ||
7e8b059b | 468 | #define BND { BND_Fixup, 0 } |
04ef582a | 469 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 470 | |
ce518a5f L |
471 | #define cond_jump_flag { NULL, cond_jump_mode } |
472 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 473 | |
252b5132 | 474 | /* bits in sizeflag */ |
252b5132 | 475 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
476 | #define AFLAG 2 |
477 | #define DFLAG 1 | |
478 | ||
51e7da1b L |
479 | enum |
480 | { | |
481 | /* byte operand */ | |
482 | b_mode = 1, | |
483 | /* byte operand with operand swapped */ | |
3873ba12 | 484 | b_swap_mode, |
e3949f17 L |
485 | /* byte operand, sign extend like 'T' suffix */ |
486 | b_T_mode, | |
51e7da1b | 487 | /* operand size depends on prefixes */ |
3873ba12 | 488 | v_mode, |
51e7da1b | 489 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 490 | v_swap_mode, |
de89d0a3 IT |
491 | /* operand size depends on address prefix */ |
492 | va_mode, | |
51e7da1b | 493 | /* word operand */ |
3873ba12 | 494 | w_mode, |
51e7da1b | 495 | /* double word operand */ |
3873ba12 | 496 | d_mode, |
51e7da1b | 497 | /* double word operand with operand swapped */ |
3873ba12 | 498 | d_swap_mode, |
51e7da1b | 499 | /* quad word operand */ |
3873ba12 | 500 | q_mode, |
51e7da1b | 501 | /* quad word operand with operand swapped */ |
3873ba12 | 502 | q_swap_mode, |
51e7da1b | 503 | /* ten-byte operand */ |
3873ba12 | 504 | t_mode, |
43234a1e L |
505 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
506 | broadcast enabled. */ | |
3873ba12 | 507 | x_mode, |
43234a1e L |
508 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
509 | evex_x_gscat_mode, | |
510 | /* Similar to x_mode, but with disabled broadcast. */ | |
511 | evex_x_nobcst_mode, | |
512 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
513 | in EVEX. */ | |
3873ba12 | 514 | x_swap_mode, |
51e7da1b | 515 | /* 16-byte XMM operand */ |
3873ba12 | 516 | xmm_mode, |
43234a1e L |
517 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
518 | memory operand (depending on vector length). Broadcast isn't | |
519 | allowed. */ | |
3873ba12 | 520 | xmmq_mode, |
43234a1e L |
521 | /* Same as xmmq_mode, but broadcast is allowed. */ |
522 | evex_half_bcst_xmmq_mode, | |
6c30d220 L |
523 | /* XMM register or byte memory operand */ |
524 | xmm_mb_mode, | |
525 | /* XMM register or word memory operand */ | |
526 | xmm_mw_mode, | |
527 | /* XMM register or double word memory operand */ | |
528 | xmm_md_mode, | |
529 | /* XMM register or quad word memory operand */ | |
530 | xmm_mq_mode, | |
43234a1e | 531 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 532 | xmmdw_mode, |
43234a1e | 533 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 534 | xmmqd_mode, |
43234a1e L |
535 | /* 32-byte YMM operand */ |
536 | ymm_mode, | |
537 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 538 | ymmq_mode, |
6c30d220 L |
539 | /* 32-byte YMM or 16-byte word operand */ |
540 | ymmxmm_mode, | |
51e7da1b | 541 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 542 | m_mode, |
51e7da1b | 543 | /* pair of v_mode operands */ |
3873ba12 L |
544 | a_mode, |
545 | cond_jump_mode, | |
546 | loop_jcxz_mode, | |
bc31405e | 547 | movsxd_mode, |
7e8b059b | 548 | v_bnd_mode, |
d276ec69 JB |
549 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
550 | v_bndmk_mode, | |
51e7da1b | 551 | /* operand size depends on REX prefixes. */ |
3873ba12 | 552 | dq_mode, |
376cd056 JB |
553 | /* registers like dq_mode, memory like w_mode, displacements like |
554 | v_mode without considering Intel64 ISA. */ | |
3873ba12 | 555 | dqw_mode, |
9f79e886 | 556 | /* bounds operand */ |
7e8b059b | 557 | bnd_mode, |
9f79e886 JB |
558 | /* bounds operand with operand swapped */ |
559 | bnd_swap_mode, | |
51e7da1b | 560 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
561 | f_mode, |
562 | const_1_mode, | |
07f5af7d L |
563 | /* v_mode for indirect branch opcodes. */ |
564 | indir_v_mode, | |
51e7da1b | 565 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 566 | stack_v_mode, |
51e7da1b | 567 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 568 | z_mode, |
51e7da1b | 569 | /* 16-byte operand */ |
3873ba12 | 570 | o_mode, |
51e7da1b | 571 | /* registers like dq_mode, memory like b_mode. */ |
3873ba12 | 572 | dqb_mode, |
1ba585e8 IT |
573 | /* registers like d_mode, memory like b_mode. */ |
574 | db_mode, | |
575 | /* registers like d_mode, memory like w_mode. */ | |
576 | dw_mode, | |
51e7da1b | 577 | /* registers like dq_mode, memory like d_mode. */ |
3873ba12 | 578 | dqd_mode, |
51e7da1b | 579 | /* normal vex mode */ |
3873ba12 | 580 | vex_mode, |
51e7da1b | 581 | /* 128bit vex mode */ |
3873ba12 | 582 | vex128_mode, |
51e7da1b | 583 | /* 256bit vex mode */ |
3873ba12 | 584 | vex256_mode, |
d55ee72f | 585 | |
825bd36c | 586 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 587 | vex_vsib_d_w_dq_mode, |
5fc35d96 IT |
588 | /* Similar to vex_vsib_d_w_dq_mode, with smaller memory. */ |
589 | vex_vsib_d_w_d_mode, | |
825bd36c | 590 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 591 | vex_vsib_q_w_dq_mode, |
5fc35d96 IT |
592 | /* Similar to vex_vsib_q_w_dq_mode, with smaller memory. */ |
593 | vex_vsib_q_w_d_mode, | |
6c30d220 | 594 | |
539f890d L |
595 | /* scalar, ignore vector length. */ |
596 | scalar_mode, | |
53467f57 IT |
597 | /* like b_mode, ignore vector length. */ |
598 | b_scalar_mode, | |
599 | /* like w_mode, ignore vector length. */ | |
600 | w_scalar_mode, | |
539f890d L |
601 | /* like d_swap_mode, ignore vector length. */ |
602 | d_scalar_swap_mode, | |
539f890d L |
603 | /* like q_swap_mode, ignore vector length. */ |
604 | q_scalar_swap_mode, | |
605 | /* like vex_mode, ignore vector length. */ | |
606 | vex_scalar_mode, | |
825bd36c | 607 | /* Operand size depends on the VEX.W bit, ignore vector length. */ |
1c480963 | 608 | vex_scalar_w_dq_mode, |
539f890d | 609 | |
43234a1e L |
610 | /* Static rounding. */ |
611 | evex_rounding_mode, | |
70df6fc9 L |
612 | /* Static rounding, 64-bit mode only. */ |
613 | evex_rounding_64_mode, | |
43234a1e L |
614 | /* Supress all exceptions. */ |
615 | evex_sae_mode, | |
616 | ||
617 | /* Mask register operand. */ | |
618 | mask_mode, | |
1ba585e8 IT |
619 | /* Mask register operand. */ |
620 | mask_bd_mode, | |
43234a1e | 621 | |
3873ba12 L |
622 | es_reg, |
623 | cs_reg, | |
624 | ss_reg, | |
625 | ds_reg, | |
626 | fs_reg, | |
627 | gs_reg, | |
d55ee72f | 628 | |
3873ba12 L |
629 | eAX_reg, |
630 | eCX_reg, | |
631 | eDX_reg, | |
632 | eBX_reg, | |
633 | eSP_reg, | |
634 | eBP_reg, | |
635 | eSI_reg, | |
636 | eDI_reg, | |
d55ee72f | 637 | |
3873ba12 L |
638 | al_reg, |
639 | cl_reg, | |
640 | dl_reg, | |
641 | bl_reg, | |
642 | ah_reg, | |
643 | ch_reg, | |
644 | dh_reg, | |
645 | bh_reg, | |
d55ee72f | 646 | |
3873ba12 L |
647 | ax_reg, |
648 | cx_reg, | |
649 | dx_reg, | |
650 | bx_reg, | |
651 | sp_reg, | |
652 | bp_reg, | |
653 | si_reg, | |
654 | di_reg, | |
d55ee72f | 655 | |
3873ba12 L |
656 | rAX_reg, |
657 | rCX_reg, | |
658 | rDX_reg, | |
659 | rBX_reg, | |
660 | rSP_reg, | |
661 | rBP_reg, | |
662 | rSI_reg, | |
663 | rDI_reg, | |
d55ee72f | 664 | |
3873ba12 L |
665 | z_mode_ax_reg, |
666 | indir_dx_reg | |
51e7da1b | 667 | }; |
252b5132 | 668 | |
51e7da1b L |
669 | enum |
670 | { | |
671 | FLOATCODE = 1, | |
3873ba12 L |
672 | USE_REG_TABLE, |
673 | USE_MOD_TABLE, | |
674 | USE_RM_TABLE, | |
675 | USE_PREFIX_TABLE, | |
676 | USE_X86_64_TABLE, | |
677 | USE_3BYTE_TABLE, | |
f88c9eb0 | 678 | USE_XOP_8F_TABLE, |
3873ba12 L |
679 | USE_VEX_C4_TABLE, |
680 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 681 | USE_VEX_LEN_TABLE, |
43234a1e | 682 | USE_VEX_W_TABLE, |
04e2a182 L |
683 | USE_EVEX_TABLE, |
684 | USE_EVEX_LEN_TABLE | |
51e7da1b | 685 | }; |
6439fc28 | 686 | |
bf890a93 | 687 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 688 | |
bf890a93 IT |
689 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
690 | #define DIS386_PREFIX(T, I, P) NULL, { { NULL, (T)}, { NULL, (I) } }, P | |
1ceb70f8 L |
691 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
692 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
693 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
694 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
695 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
696 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
bf890a93 | 697 | #define THREE_BYTE_TABLE_PREFIX(I, P) DIS386_PREFIX (USE_3BYTE_TABLE, (I), P) |
f88c9eb0 | 698 | #define XOP_8F_TABLE(I) DIS386 (USE_XOP_8F_TABLE, (I)) |
c0f3af97 L |
699 | #define VEX_C4_TABLE(I) DIS386 (USE_VEX_C4_TABLE, (I)) |
700 | #define VEX_C5_TABLE(I) DIS386 (USE_VEX_C5_TABLE, (I)) | |
701 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) | |
9e30b8e0 | 702 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
43234a1e | 703 | #define EVEX_TABLE(I) DIS386 (USE_EVEX_TABLE, (I)) |
04e2a182 | 704 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 705 | |
51e7da1b L |
706 | enum |
707 | { | |
708 | REG_80 = 0, | |
3873ba12 | 709 | REG_81, |
7148c369 | 710 | REG_83, |
3873ba12 L |
711 | REG_8F, |
712 | REG_C0, | |
713 | REG_C1, | |
714 | REG_C6, | |
715 | REG_C7, | |
716 | REG_D0, | |
717 | REG_D1, | |
718 | REG_D2, | |
719 | REG_D3, | |
720 | REG_F6, | |
721 | REG_F7, | |
722 | REG_FE, | |
723 | REG_FF, | |
724 | REG_0F00, | |
725 | REG_0F01, | |
726 | REG_0F0D, | |
727 | REG_0F18, | |
f8687e93 JB |
728 | REG_0F1C_P_0_MOD_0, |
729 | REG_0F1E_P_1_MOD_3, | |
3873ba12 L |
730 | REG_0F71, |
731 | REG_0F72, | |
732 | REG_0F73, | |
733 | REG_0FA6, | |
734 | REG_0FA7, | |
735 | REG_0FAE, | |
736 | REG_0FBA, | |
737 | REG_0FC7, | |
592a252b L |
738 | REG_VEX_0F71, |
739 | REG_VEX_0F72, | |
740 | REG_VEX_0F73, | |
741 | REG_VEX_0FAE, | |
f12dc422 | 742 | REG_VEX_0F38F3, |
f88c9eb0 | 743 | REG_XOP_LWPCB, |
2a2a0f38 QN |
744 | REG_XOP_LWP, |
745 | REG_XOP_TBM_01, | |
43234a1e L |
746 | REG_XOP_TBM_02, |
747 | ||
1ba585e8 | 748 | REG_EVEX_0F71, |
43234a1e L |
749 | REG_EVEX_0F72, |
750 | REG_EVEX_0F73, | |
751 | REG_EVEX_0F38C6, | |
752 | REG_EVEX_0F38C7 | |
51e7da1b | 753 | }; |
1ceb70f8 | 754 | |
51e7da1b L |
755 | enum |
756 | { | |
757 | MOD_8D = 0, | |
42164a71 L |
758 | MOD_C6_REG_7, |
759 | MOD_C7_REG_7, | |
4a357820 MZ |
760 | MOD_FF_REG_3, |
761 | MOD_FF_REG_5, | |
3873ba12 L |
762 | MOD_0F01_REG_0, |
763 | MOD_0F01_REG_1, | |
764 | MOD_0F01_REG_2, | |
765 | MOD_0F01_REG_3, | |
8eab4136 | 766 | MOD_0F01_REG_5, |
3873ba12 L |
767 | MOD_0F01_REG_7, |
768 | MOD_0F12_PREFIX_0, | |
18897deb | 769 | MOD_0F12_PREFIX_2, |
3873ba12 L |
770 | MOD_0F13, |
771 | MOD_0F16_PREFIX_0, | |
18897deb | 772 | MOD_0F16_PREFIX_2, |
3873ba12 L |
773 | MOD_0F17, |
774 | MOD_0F18_REG_0, | |
775 | MOD_0F18_REG_1, | |
776 | MOD_0F18_REG_2, | |
777 | MOD_0F18_REG_3, | |
d7189fa5 RM |
778 | MOD_0F18_REG_4, |
779 | MOD_0F18_REG_5, | |
780 | MOD_0F18_REG_6, | |
781 | MOD_0F18_REG_7, | |
7e8b059b L |
782 | MOD_0F1A_PREFIX_0, |
783 | MOD_0F1B_PREFIX_0, | |
784 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 785 | MOD_0F1C_PREFIX_0, |
603555e5 | 786 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
787 | MOD_0F24, |
788 | MOD_0F26, | |
789 | MOD_0F2B_PREFIX_0, | |
790 | MOD_0F2B_PREFIX_1, | |
791 | MOD_0F2B_PREFIX_2, | |
792 | MOD_0F2B_PREFIX_3, | |
a5aaedb9 | 793 | MOD_0F50, |
3873ba12 L |
794 | MOD_0F71_REG_2, |
795 | MOD_0F71_REG_4, | |
796 | MOD_0F71_REG_6, | |
797 | MOD_0F72_REG_2, | |
798 | MOD_0F72_REG_4, | |
799 | MOD_0F72_REG_6, | |
800 | MOD_0F73_REG_2, | |
801 | MOD_0F73_REG_3, | |
802 | MOD_0F73_REG_6, | |
803 | MOD_0F73_REG_7, | |
804 | MOD_0FAE_REG_0, | |
805 | MOD_0FAE_REG_1, | |
806 | MOD_0FAE_REG_2, | |
807 | MOD_0FAE_REG_3, | |
808 | MOD_0FAE_REG_4, | |
809 | MOD_0FAE_REG_5, | |
810 | MOD_0FAE_REG_6, | |
811 | MOD_0FAE_REG_7, | |
812 | MOD_0FB2, | |
813 | MOD_0FB4, | |
814 | MOD_0FB5, | |
a8484f96 | 815 | MOD_0FC3, |
963f3586 IT |
816 | MOD_0FC7_REG_3, |
817 | MOD_0FC7_REG_4, | |
818 | MOD_0FC7_REG_5, | |
3873ba12 L |
819 | MOD_0FC7_REG_6, |
820 | MOD_0FC7_REG_7, | |
821 | MOD_0FD7, | |
822 | MOD_0FE7_PREFIX_2, | |
823 | MOD_0FF0_PREFIX_3, | |
824 | MOD_0F382A_PREFIX_2, | |
603555e5 L |
825 | MOD_0F38F5_PREFIX_2, |
826 | MOD_0F38F6_PREFIX_0, | |
5d79adc4 | 827 | MOD_0F38F8_PREFIX_1, |
c0a30a9f | 828 | MOD_0F38F8_PREFIX_2, |
5d79adc4 | 829 | MOD_0F38F8_PREFIX_3, |
c0a30a9f | 830 | MOD_0F38F9_PREFIX_0, |
3873ba12 L |
831 | MOD_62_32BIT, |
832 | MOD_C4_32BIT, | |
833 | MOD_C5_32BIT, | |
592a252b | 834 | MOD_VEX_0F12_PREFIX_0, |
18897deb | 835 | MOD_VEX_0F12_PREFIX_2, |
592a252b L |
836 | MOD_VEX_0F13, |
837 | MOD_VEX_0F16_PREFIX_0, | |
18897deb | 838 | MOD_VEX_0F16_PREFIX_2, |
592a252b L |
839 | MOD_VEX_0F17, |
840 | MOD_VEX_0F2B, | |
ab4e4ed5 AF |
841 | MOD_VEX_W_0_0F41_P_0_LEN_1, |
842 | MOD_VEX_W_1_0F41_P_0_LEN_1, | |
843 | MOD_VEX_W_0_0F41_P_2_LEN_1, | |
844 | MOD_VEX_W_1_0F41_P_2_LEN_1, | |
845 | MOD_VEX_W_0_0F42_P_0_LEN_1, | |
846 | MOD_VEX_W_1_0F42_P_0_LEN_1, | |
847 | MOD_VEX_W_0_0F42_P_2_LEN_1, | |
848 | MOD_VEX_W_1_0F42_P_2_LEN_1, | |
849 | MOD_VEX_W_0_0F44_P_0_LEN_1, | |
850 | MOD_VEX_W_1_0F44_P_0_LEN_1, | |
851 | MOD_VEX_W_0_0F44_P_2_LEN_1, | |
852 | MOD_VEX_W_1_0F44_P_2_LEN_1, | |
853 | MOD_VEX_W_0_0F45_P_0_LEN_1, | |
854 | MOD_VEX_W_1_0F45_P_0_LEN_1, | |
855 | MOD_VEX_W_0_0F45_P_2_LEN_1, | |
856 | MOD_VEX_W_1_0F45_P_2_LEN_1, | |
857 | MOD_VEX_W_0_0F46_P_0_LEN_1, | |
858 | MOD_VEX_W_1_0F46_P_0_LEN_1, | |
859 | MOD_VEX_W_0_0F46_P_2_LEN_1, | |
860 | MOD_VEX_W_1_0F46_P_2_LEN_1, | |
861 | MOD_VEX_W_0_0F47_P_0_LEN_1, | |
862 | MOD_VEX_W_1_0F47_P_0_LEN_1, | |
863 | MOD_VEX_W_0_0F47_P_2_LEN_1, | |
864 | MOD_VEX_W_1_0F47_P_2_LEN_1, | |
865 | MOD_VEX_W_0_0F4A_P_0_LEN_1, | |
866 | MOD_VEX_W_1_0F4A_P_0_LEN_1, | |
867 | MOD_VEX_W_0_0F4A_P_2_LEN_1, | |
868 | MOD_VEX_W_1_0F4A_P_2_LEN_1, | |
869 | MOD_VEX_W_0_0F4B_P_0_LEN_1, | |
870 | MOD_VEX_W_1_0F4B_P_0_LEN_1, | |
871 | MOD_VEX_W_0_0F4B_P_2_LEN_1, | |
592a252b L |
872 | MOD_VEX_0F50, |
873 | MOD_VEX_0F71_REG_2, | |
874 | MOD_VEX_0F71_REG_4, | |
875 | MOD_VEX_0F71_REG_6, | |
876 | MOD_VEX_0F72_REG_2, | |
877 | MOD_VEX_0F72_REG_4, | |
878 | MOD_VEX_0F72_REG_6, | |
879 | MOD_VEX_0F73_REG_2, | |
880 | MOD_VEX_0F73_REG_3, | |
881 | MOD_VEX_0F73_REG_6, | |
882 | MOD_VEX_0F73_REG_7, | |
ab4e4ed5 AF |
883 | MOD_VEX_W_0_0F91_P_0_LEN_0, |
884 | MOD_VEX_W_1_0F91_P_0_LEN_0, | |
885 | MOD_VEX_W_0_0F91_P_2_LEN_0, | |
886 | MOD_VEX_W_1_0F91_P_2_LEN_0, | |
887 | MOD_VEX_W_0_0F92_P_0_LEN_0, | |
888 | MOD_VEX_W_0_0F92_P_2_LEN_0, | |
58a211d2 | 889 | MOD_VEX_0F92_P_3_LEN_0, |
ab4e4ed5 AF |
890 | MOD_VEX_W_0_0F93_P_0_LEN_0, |
891 | MOD_VEX_W_0_0F93_P_2_LEN_0, | |
58a211d2 | 892 | MOD_VEX_0F93_P_3_LEN_0, |
ab4e4ed5 AF |
893 | MOD_VEX_W_0_0F98_P_0_LEN_0, |
894 | MOD_VEX_W_1_0F98_P_0_LEN_0, | |
895 | MOD_VEX_W_0_0F98_P_2_LEN_0, | |
896 | MOD_VEX_W_1_0F98_P_2_LEN_0, | |
897 | MOD_VEX_W_0_0F99_P_0_LEN_0, | |
898 | MOD_VEX_W_1_0F99_P_0_LEN_0, | |
899 | MOD_VEX_W_0_0F99_P_2_LEN_0, | |
900 | MOD_VEX_W_1_0F99_P_2_LEN_0, | |
592a252b L |
901 | MOD_VEX_0FAE_REG_2, |
902 | MOD_VEX_0FAE_REG_3, | |
903 | MOD_VEX_0FD7_PREFIX_2, | |
904 | MOD_VEX_0FE7_PREFIX_2, | |
905 | MOD_VEX_0FF0_PREFIX_3, | |
592a252b L |
906 | MOD_VEX_0F381A_PREFIX_2, |
907 | MOD_VEX_0F382A_PREFIX_2, | |
908 | MOD_VEX_0F382C_PREFIX_2, | |
909 | MOD_VEX_0F382D_PREFIX_2, | |
910 | MOD_VEX_0F382E_PREFIX_2, | |
6c30d220 L |
911 | MOD_VEX_0F382F_PREFIX_2, |
912 | MOD_VEX_0F385A_PREFIX_2, | |
913 | MOD_VEX_0F388C_PREFIX_2, | |
914 | MOD_VEX_0F388E_PREFIX_2, | |
ab4e4ed5 AF |
915 | MOD_VEX_W_0_0F3A30_P_2_LEN_0, |
916 | MOD_VEX_W_1_0F3A30_P_2_LEN_0, | |
917 | MOD_VEX_W_0_0F3A31_P_2_LEN_0, | |
918 | MOD_VEX_W_1_0F3A31_P_2_LEN_0, | |
919 | MOD_VEX_W_0_0F3A32_P_2_LEN_0, | |
920 | MOD_VEX_W_1_0F3A32_P_2_LEN_0, | |
921 | MOD_VEX_W_0_0F3A33_P_2_LEN_0, | |
922 | MOD_VEX_W_1_0F3A33_P_2_LEN_0, | |
43234a1e | 923 | |
43234a1e | 924 | MOD_EVEX_0F12_PREFIX_0, |
97e6786a JB |
925 | MOD_EVEX_0F12_PREFIX_2, |
926 | MOD_EVEX_0F13, | |
43234a1e | 927 | MOD_EVEX_0F16_PREFIX_0, |
97e6786a JB |
928 | MOD_EVEX_0F16_PREFIX_2, |
929 | MOD_EVEX_0F17, | |
930 | MOD_EVEX_0F2B, | |
bc152a17 JB |
931 | MOD_EVEX_0F381A_P_2_W_0, |
932 | MOD_EVEX_0F381A_P_2_W_1, | |
933 | MOD_EVEX_0F381B_P_2_W_0, | |
934 | MOD_EVEX_0F381B_P_2_W_1, | |
935 | MOD_EVEX_0F385A_P_2_W_0, | |
936 | MOD_EVEX_0F385A_P_2_W_1, | |
937 | MOD_EVEX_0F385B_P_2_W_0, | |
938 | MOD_EVEX_0F385B_P_2_W_1, | |
43234a1e L |
939 | MOD_EVEX_0F38C6_REG_1, |
940 | MOD_EVEX_0F38C6_REG_2, | |
941 | MOD_EVEX_0F38C6_REG_5, | |
942 | MOD_EVEX_0F38C6_REG_6, | |
943 | MOD_EVEX_0F38C7_REG_1, | |
944 | MOD_EVEX_0F38C7_REG_2, | |
945 | MOD_EVEX_0F38C7_REG_5, | |
946 | MOD_EVEX_0F38C7_REG_6 | |
51e7da1b | 947 | }; |
1ceb70f8 | 948 | |
51e7da1b L |
949 | enum |
950 | { | |
42164a71 L |
951 | RM_C6_REG_7 = 0, |
952 | RM_C7_REG_7, | |
953 | RM_0F01_REG_0, | |
3873ba12 L |
954 | RM_0F01_REG_1, |
955 | RM_0F01_REG_2, | |
956 | RM_0F01_REG_3, | |
f8687e93 JB |
957 | RM_0F01_REG_5_MOD_3, |
958 | RM_0F01_REG_7_MOD_3, | |
959 | RM_0F1E_P_1_MOD_3_REG_7, | |
960 | RM_0FAE_REG_6_MOD_3_P_0, | |
961 | RM_0FAE_REG_7_MOD_3, | |
51e7da1b | 962 | }; |
1ceb70f8 | 963 | |
51e7da1b L |
964 | enum |
965 | { | |
966 | PREFIX_90 = 0, | |
a847e322 | 967 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
968 | PREFIX_0F01_REG_5_MOD_0, |
969 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 970 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 971 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
267b8516 JB |
972 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
973 | PREFIX_0F01_REG_7_MOD_3_RM_3, | |
3233d7d0 | 974 | PREFIX_0F09, |
3873ba12 L |
975 | PREFIX_0F10, |
976 | PREFIX_0F11, | |
977 | PREFIX_0F12, | |
978 | PREFIX_0F16, | |
7e8b059b L |
979 | PREFIX_0F1A, |
980 | PREFIX_0F1B, | |
c48935d7 | 981 | PREFIX_0F1C, |
603555e5 | 982 | PREFIX_0F1E, |
3873ba12 L |
983 | PREFIX_0F2A, |
984 | PREFIX_0F2B, | |
985 | PREFIX_0F2C, | |
986 | PREFIX_0F2D, | |
987 | PREFIX_0F2E, | |
988 | PREFIX_0F2F, | |
989 | PREFIX_0F51, | |
990 | PREFIX_0F52, | |
991 | PREFIX_0F53, | |
992 | PREFIX_0F58, | |
993 | PREFIX_0F59, | |
994 | PREFIX_0F5A, | |
995 | PREFIX_0F5B, | |
996 | PREFIX_0F5C, | |
997 | PREFIX_0F5D, | |
998 | PREFIX_0F5E, | |
999 | PREFIX_0F5F, | |
1000 | PREFIX_0F60, | |
1001 | PREFIX_0F61, | |
1002 | PREFIX_0F62, | |
1003 | PREFIX_0F6C, | |
1004 | PREFIX_0F6D, | |
1005 | PREFIX_0F6F, | |
1006 | PREFIX_0F70, | |
1007 | PREFIX_0F73_REG_3, | |
1008 | PREFIX_0F73_REG_7, | |
1009 | PREFIX_0F78, | |
1010 | PREFIX_0F79, | |
1011 | PREFIX_0F7C, | |
1012 | PREFIX_0F7D, | |
1013 | PREFIX_0F7E, | |
1014 | PREFIX_0F7F, | |
f8687e93 JB |
1015 | PREFIX_0FAE_REG_0_MOD_3, |
1016 | PREFIX_0FAE_REG_1_MOD_3, | |
1017 | PREFIX_0FAE_REG_2_MOD_3, | |
1018 | PREFIX_0FAE_REG_3_MOD_3, | |
1019 | PREFIX_0FAE_REG_4_MOD_0, | |
1020 | PREFIX_0FAE_REG_4_MOD_3, | |
1021 | PREFIX_0FAE_REG_5_MOD_0, | |
1022 | PREFIX_0FAE_REG_5_MOD_3, | |
1023 | PREFIX_0FAE_REG_6_MOD_0, | |
1024 | PREFIX_0FAE_REG_6_MOD_3, | |
1025 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 1026 | PREFIX_0FB8, |
f12dc422 | 1027 | PREFIX_0FBC, |
3873ba12 L |
1028 | PREFIX_0FBD, |
1029 | PREFIX_0FC2, | |
f8687e93 JB |
1030 | PREFIX_0FC3_MOD_0, |
1031 | PREFIX_0FC7_REG_6_MOD_0, | |
1032 | PREFIX_0FC7_REG_6_MOD_3, | |
1033 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
1034 | PREFIX_0FD0, |
1035 | PREFIX_0FD6, | |
1036 | PREFIX_0FE6, | |
1037 | PREFIX_0FE7, | |
1038 | PREFIX_0FF0, | |
1039 | PREFIX_0FF7, | |
1040 | PREFIX_0F3810, | |
1041 | PREFIX_0F3814, | |
1042 | PREFIX_0F3815, | |
1043 | PREFIX_0F3817, | |
1044 | PREFIX_0F3820, | |
1045 | PREFIX_0F3821, | |
1046 | PREFIX_0F3822, | |
1047 | PREFIX_0F3823, | |
1048 | PREFIX_0F3824, | |
1049 | PREFIX_0F3825, | |
1050 | PREFIX_0F3828, | |
1051 | PREFIX_0F3829, | |
1052 | PREFIX_0F382A, | |
1053 | PREFIX_0F382B, | |
1054 | PREFIX_0F3830, | |
1055 | PREFIX_0F3831, | |
1056 | PREFIX_0F3832, | |
1057 | PREFIX_0F3833, | |
1058 | PREFIX_0F3834, | |
1059 | PREFIX_0F3835, | |
1060 | PREFIX_0F3837, | |
1061 | PREFIX_0F3838, | |
1062 | PREFIX_0F3839, | |
1063 | PREFIX_0F383A, | |
1064 | PREFIX_0F383B, | |
1065 | PREFIX_0F383C, | |
1066 | PREFIX_0F383D, | |
1067 | PREFIX_0F383E, | |
1068 | PREFIX_0F383F, | |
1069 | PREFIX_0F3840, | |
1070 | PREFIX_0F3841, | |
1071 | PREFIX_0F3880, | |
1072 | PREFIX_0F3881, | |
6c30d220 | 1073 | PREFIX_0F3882, |
a0046408 L |
1074 | PREFIX_0F38C8, |
1075 | PREFIX_0F38C9, | |
1076 | PREFIX_0F38CA, | |
1077 | PREFIX_0F38CB, | |
1078 | PREFIX_0F38CC, | |
1079 | PREFIX_0F38CD, | |
48521003 | 1080 | PREFIX_0F38CF, |
3873ba12 L |
1081 | PREFIX_0F38DB, |
1082 | PREFIX_0F38DC, | |
1083 | PREFIX_0F38DD, | |
1084 | PREFIX_0F38DE, | |
1085 | PREFIX_0F38DF, | |
1086 | PREFIX_0F38F0, | |
1087 | PREFIX_0F38F1, | |
603555e5 | 1088 | PREFIX_0F38F5, |
e2e1fcde | 1089 | PREFIX_0F38F6, |
c0a30a9f L |
1090 | PREFIX_0F38F8, |
1091 | PREFIX_0F38F9, | |
3873ba12 L |
1092 | PREFIX_0F3A08, |
1093 | PREFIX_0F3A09, | |
1094 | PREFIX_0F3A0A, | |
1095 | PREFIX_0F3A0B, | |
1096 | PREFIX_0F3A0C, | |
1097 | PREFIX_0F3A0D, | |
1098 | PREFIX_0F3A0E, | |
1099 | PREFIX_0F3A14, | |
1100 | PREFIX_0F3A15, | |
1101 | PREFIX_0F3A16, | |
1102 | PREFIX_0F3A17, | |
1103 | PREFIX_0F3A20, | |
1104 | PREFIX_0F3A21, | |
1105 | PREFIX_0F3A22, | |
1106 | PREFIX_0F3A40, | |
1107 | PREFIX_0F3A41, | |
1108 | PREFIX_0F3A42, | |
1109 | PREFIX_0F3A44, | |
1110 | PREFIX_0F3A60, | |
1111 | PREFIX_0F3A61, | |
1112 | PREFIX_0F3A62, | |
1113 | PREFIX_0F3A63, | |
a0046408 | 1114 | PREFIX_0F3ACC, |
48521003 IT |
1115 | PREFIX_0F3ACE, |
1116 | PREFIX_0F3ACF, | |
3873ba12 | 1117 | PREFIX_0F3ADF, |
592a252b L |
1118 | PREFIX_VEX_0F10, |
1119 | PREFIX_VEX_0F11, | |
1120 | PREFIX_VEX_0F12, | |
1121 | PREFIX_VEX_0F16, | |
1122 | PREFIX_VEX_0F2A, | |
1123 | PREFIX_VEX_0F2C, | |
1124 | PREFIX_VEX_0F2D, | |
1125 | PREFIX_VEX_0F2E, | |
1126 | PREFIX_VEX_0F2F, | |
43234a1e L |
1127 | PREFIX_VEX_0F41, |
1128 | PREFIX_VEX_0F42, | |
1129 | PREFIX_VEX_0F44, | |
1130 | PREFIX_VEX_0F45, | |
1131 | PREFIX_VEX_0F46, | |
1132 | PREFIX_VEX_0F47, | |
1ba585e8 | 1133 | PREFIX_VEX_0F4A, |
43234a1e | 1134 | PREFIX_VEX_0F4B, |
592a252b L |
1135 | PREFIX_VEX_0F51, |
1136 | PREFIX_VEX_0F52, | |
1137 | PREFIX_VEX_0F53, | |
1138 | PREFIX_VEX_0F58, | |
1139 | PREFIX_VEX_0F59, | |
1140 | PREFIX_VEX_0F5A, | |
1141 | PREFIX_VEX_0F5B, | |
1142 | PREFIX_VEX_0F5C, | |
1143 | PREFIX_VEX_0F5D, | |
1144 | PREFIX_VEX_0F5E, | |
1145 | PREFIX_VEX_0F5F, | |
1146 | PREFIX_VEX_0F60, | |
1147 | PREFIX_VEX_0F61, | |
1148 | PREFIX_VEX_0F62, | |
1149 | PREFIX_VEX_0F63, | |
1150 | PREFIX_VEX_0F64, | |
1151 | PREFIX_VEX_0F65, | |
1152 | PREFIX_VEX_0F66, | |
1153 | PREFIX_VEX_0F67, | |
1154 | PREFIX_VEX_0F68, | |
1155 | PREFIX_VEX_0F69, | |
1156 | PREFIX_VEX_0F6A, | |
1157 | PREFIX_VEX_0F6B, | |
1158 | PREFIX_VEX_0F6C, | |
1159 | PREFIX_VEX_0F6D, | |
1160 | PREFIX_VEX_0F6E, | |
1161 | PREFIX_VEX_0F6F, | |
1162 | PREFIX_VEX_0F70, | |
1163 | PREFIX_VEX_0F71_REG_2, | |
1164 | PREFIX_VEX_0F71_REG_4, | |
1165 | PREFIX_VEX_0F71_REG_6, | |
1166 | PREFIX_VEX_0F72_REG_2, | |
1167 | PREFIX_VEX_0F72_REG_4, | |
1168 | PREFIX_VEX_0F72_REG_6, | |
1169 | PREFIX_VEX_0F73_REG_2, | |
1170 | PREFIX_VEX_0F73_REG_3, | |
1171 | PREFIX_VEX_0F73_REG_6, | |
1172 | PREFIX_VEX_0F73_REG_7, | |
1173 | PREFIX_VEX_0F74, | |
1174 | PREFIX_VEX_0F75, | |
1175 | PREFIX_VEX_0F76, | |
1176 | PREFIX_VEX_0F77, | |
1177 | PREFIX_VEX_0F7C, | |
1178 | PREFIX_VEX_0F7D, | |
1179 | PREFIX_VEX_0F7E, | |
1180 | PREFIX_VEX_0F7F, | |
43234a1e L |
1181 | PREFIX_VEX_0F90, |
1182 | PREFIX_VEX_0F91, | |
1183 | PREFIX_VEX_0F92, | |
1184 | PREFIX_VEX_0F93, | |
1185 | PREFIX_VEX_0F98, | |
1ba585e8 | 1186 | PREFIX_VEX_0F99, |
592a252b L |
1187 | PREFIX_VEX_0FC2, |
1188 | PREFIX_VEX_0FC4, | |
1189 | PREFIX_VEX_0FC5, | |
1190 | PREFIX_VEX_0FD0, | |
1191 | PREFIX_VEX_0FD1, | |
1192 | PREFIX_VEX_0FD2, | |
1193 | PREFIX_VEX_0FD3, | |
1194 | PREFIX_VEX_0FD4, | |
1195 | PREFIX_VEX_0FD5, | |
1196 | PREFIX_VEX_0FD6, | |
1197 | PREFIX_VEX_0FD7, | |
1198 | PREFIX_VEX_0FD8, | |
1199 | PREFIX_VEX_0FD9, | |
1200 | PREFIX_VEX_0FDA, | |
1201 | PREFIX_VEX_0FDB, | |
1202 | PREFIX_VEX_0FDC, | |
1203 | PREFIX_VEX_0FDD, | |
1204 | PREFIX_VEX_0FDE, | |
1205 | PREFIX_VEX_0FDF, | |
1206 | PREFIX_VEX_0FE0, | |
1207 | PREFIX_VEX_0FE1, | |
1208 | PREFIX_VEX_0FE2, | |
1209 | PREFIX_VEX_0FE3, | |
1210 | PREFIX_VEX_0FE4, | |
1211 | PREFIX_VEX_0FE5, | |
1212 | PREFIX_VEX_0FE6, | |
1213 | PREFIX_VEX_0FE7, | |
1214 | PREFIX_VEX_0FE8, | |
1215 | PREFIX_VEX_0FE9, | |
1216 | PREFIX_VEX_0FEA, | |
1217 | PREFIX_VEX_0FEB, | |
1218 | PREFIX_VEX_0FEC, | |
1219 | PREFIX_VEX_0FED, | |
1220 | PREFIX_VEX_0FEE, | |
1221 | PREFIX_VEX_0FEF, | |
1222 | PREFIX_VEX_0FF0, | |
1223 | PREFIX_VEX_0FF1, | |
1224 | PREFIX_VEX_0FF2, | |
1225 | PREFIX_VEX_0FF3, | |
1226 | PREFIX_VEX_0FF4, | |
1227 | PREFIX_VEX_0FF5, | |
1228 | PREFIX_VEX_0FF6, | |
1229 | PREFIX_VEX_0FF7, | |
1230 | PREFIX_VEX_0FF8, | |
1231 | PREFIX_VEX_0FF9, | |
1232 | PREFIX_VEX_0FFA, | |
1233 | PREFIX_VEX_0FFB, | |
1234 | PREFIX_VEX_0FFC, | |
1235 | PREFIX_VEX_0FFD, | |
1236 | PREFIX_VEX_0FFE, | |
1237 | PREFIX_VEX_0F3800, | |
1238 | PREFIX_VEX_0F3801, | |
1239 | PREFIX_VEX_0F3802, | |
1240 | PREFIX_VEX_0F3803, | |
1241 | PREFIX_VEX_0F3804, | |
1242 | PREFIX_VEX_0F3805, | |
1243 | PREFIX_VEX_0F3806, | |
1244 | PREFIX_VEX_0F3807, | |
1245 | PREFIX_VEX_0F3808, | |
1246 | PREFIX_VEX_0F3809, | |
1247 | PREFIX_VEX_0F380A, | |
1248 | PREFIX_VEX_0F380B, | |
1249 | PREFIX_VEX_0F380C, | |
1250 | PREFIX_VEX_0F380D, | |
1251 | PREFIX_VEX_0F380E, | |
1252 | PREFIX_VEX_0F380F, | |
1253 | PREFIX_VEX_0F3813, | |
6c30d220 | 1254 | PREFIX_VEX_0F3816, |
592a252b L |
1255 | PREFIX_VEX_0F3817, |
1256 | PREFIX_VEX_0F3818, | |
1257 | PREFIX_VEX_0F3819, | |
1258 | PREFIX_VEX_0F381A, | |
1259 | PREFIX_VEX_0F381C, | |
1260 | PREFIX_VEX_0F381D, | |
1261 | PREFIX_VEX_0F381E, | |
1262 | PREFIX_VEX_0F3820, | |
1263 | PREFIX_VEX_0F3821, | |
1264 | PREFIX_VEX_0F3822, | |
1265 | PREFIX_VEX_0F3823, | |
1266 | PREFIX_VEX_0F3824, | |
1267 | PREFIX_VEX_0F3825, | |
1268 | PREFIX_VEX_0F3828, | |
1269 | PREFIX_VEX_0F3829, | |
1270 | PREFIX_VEX_0F382A, | |
1271 | PREFIX_VEX_0F382B, | |
1272 | PREFIX_VEX_0F382C, | |
1273 | PREFIX_VEX_0F382D, | |
1274 | PREFIX_VEX_0F382E, | |
1275 | PREFIX_VEX_0F382F, | |
1276 | PREFIX_VEX_0F3830, | |
1277 | PREFIX_VEX_0F3831, | |
1278 | PREFIX_VEX_0F3832, | |
1279 | PREFIX_VEX_0F3833, | |
1280 | PREFIX_VEX_0F3834, | |
1281 | PREFIX_VEX_0F3835, | |
6c30d220 | 1282 | PREFIX_VEX_0F3836, |
592a252b L |
1283 | PREFIX_VEX_0F3837, |
1284 | PREFIX_VEX_0F3838, | |
1285 | PREFIX_VEX_0F3839, | |
1286 | PREFIX_VEX_0F383A, | |
1287 | PREFIX_VEX_0F383B, | |
1288 | PREFIX_VEX_0F383C, | |
1289 | PREFIX_VEX_0F383D, | |
1290 | PREFIX_VEX_0F383E, | |
1291 | PREFIX_VEX_0F383F, | |
1292 | PREFIX_VEX_0F3840, | |
1293 | PREFIX_VEX_0F3841, | |
6c30d220 L |
1294 | PREFIX_VEX_0F3845, |
1295 | PREFIX_VEX_0F3846, | |
1296 | PREFIX_VEX_0F3847, | |
1297 | PREFIX_VEX_0F3858, | |
1298 | PREFIX_VEX_0F3859, | |
1299 | PREFIX_VEX_0F385A, | |
1300 | PREFIX_VEX_0F3878, | |
1301 | PREFIX_VEX_0F3879, | |
1302 | PREFIX_VEX_0F388C, | |
1303 | PREFIX_VEX_0F388E, | |
1304 | PREFIX_VEX_0F3890, | |
1305 | PREFIX_VEX_0F3891, | |
1306 | PREFIX_VEX_0F3892, | |
1307 | PREFIX_VEX_0F3893, | |
592a252b L |
1308 | PREFIX_VEX_0F3896, |
1309 | PREFIX_VEX_0F3897, | |
1310 | PREFIX_VEX_0F3898, | |
1311 | PREFIX_VEX_0F3899, | |
1312 | PREFIX_VEX_0F389A, | |
1313 | PREFIX_VEX_0F389B, | |
1314 | PREFIX_VEX_0F389C, | |
1315 | PREFIX_VEX_0F389D, | |
1316 | PREFIX_VEX_0F389E, | |
1317 | PREFIX_VEX_0F389F, | |
1318 | PREFIX_VEX_0F38A6, | |
1319 | PREFIX_VEX_0F38A7, | |
1320 | PREFIX_VEX_0F38A8, | |
1321 | PREFIX_VEX_0F38A9, | |
1322 | PREFIX_VEX_0F38AA, | |
1323 | PREFIX_VEX_0F38AB, | |
1324 | PREFIX_VEX_0F38AC, | |
1325 | PREFIX_VEX_0F38AD, | |
1326 | PREFIX_VEX_0F38AE, | |
1327 | PREFIX_VEX_0F38AF, | |
1328 | PREFIX_VEX_0F38B6, | |
1329 | PREFIX_VEX_0F38B7, | |
1330 | PREFIX_VEX_0F38B8, | |
1331 | PREFIX_VEX_0F38B9, | |
1332 | PREFIX_VEX_0F38BA, | |
1333 | PREFIX_VEX_0F38BB, | |
1334 | PREFIX_VEX_0F38BC, | |
1335 | PREFIX_VEX_0F38BD, | |
1336 | PREFIX_VEX_0F38BE, | |
1337 | PREFIX_VEX_0F38BF, | |
48521003 | 1338 | PREFIX_VEX_0F38CF, |
592a252b L |
1339 | PREFIX_VEX_0F38DB, |
1340 | PREFIX_VEX_0F38DC, | |
1341 | PREFIX_VEX_0F38DD, | |
1342 | PREFIX_VEX_0F38DE, | |
1343 | PREFIX_VEX_0F38DF, | |
f12dc422 L |
1344 | PREFIX_VEX_0F38F2, |
1345 | PREFIX_VEX_0F38F3_REG_1, | |
1346 | PREFIX_VEX_0F38F3_REG_2, | |
1347 | PREFIX_VEX_0F38F3_REG_3, | |
6c30d220 L |
1348 | PREFIX_VEX_0F38F5, |
1349 | PREFIX_VEX_0F38F6, | |
f12dc422 | 1350 | PREFIX_VEX_0F38F7, |
6c30d220 L |
1351 | PREFIX_VEX_0F3A00, |
1352 | PREFIX_VEX_0F3A01, | |
1353 | PREFIX_VEX_0F3A02, | |
592a252b L |
1354 | PREFIX_VEX_0F3A04, |
1355 | PREFIX_VEX_0F3A05, | |
1356 | PREFIX_VEX_0F3A06, | |
1357 | PREFIX_VEX_0F3A08, | |
1358 | PREFIX_VEX_0F3A09, | |
1359 | PREFIX_VEX_0F3A0A, | |
1360 | PREFIX_VEX_0F3A0B, | |
1361 | PREFIX_VEX_0F3A0C, | |
1362 | PREFIX_VEX_0F3A0D, | |
1363 | PREFIX_VEX_0F3A0E, | |
1364 | PREFIX_VEX_0F3A0F, | |
1365 | PREFIX_VEX_0F3A14, | |
1366 | PREFIX_VEX_0F3A15, | |
1367 | PREFIX_VEX_0F3A16, | |
1368 | PREFIX_VEX_0F3A17, | |
1369 | PREFIX_VEX_0F3A18, | |
1370 | PREFIX_VEX_0F3A19, | |
1371 | PREFIX_VEX_0F3A1D, | |
1372 | PREFIX_VEX_0F3A20, | |
1373 | PREFIX_VEX_0F3A21, | |
1374 | PREFIX_VEX_0F3A22, | |
43234a1e | 1375 | PREFIX_VEX_0F3A30, |
1ba585e8 | 1376 | PREFIX_VEX_0F3A31, |
43234a1e | 1377 | PREFIX_VEX_0F3A32, |
1ba585e8 | 1378 | PREFIX_VEX_0F3A33, |
6c30d220 L |
1379 | PREFIX_VEX_0F3A38, |
1380 | PREFIX_VEX_0F3A39, | |
592a252b L |
1381 | PREFIX_VEX_0F3A40, |
1382 | PREFIX_VEX_0F3A41, | |
1383 | PREFIX_VEX_0F3A42, | |
1384 | PREFIX_VEX_0F3A44, | |
6c30d220 | 1385 | PREFIX_VEX_0F3A46, |
592a252b L |
1386 | PREFIX_VEX_0F3A48, |
1387 | PREFIX_VEX_0F3A49, | |
1388 | PREFIX_VEX_0F3A4A, | |
1389 | PREFIX_VEX_0F3A4B, | |
1390 | PREFIX_VEX_0F3A4C, | |
1391 | PREFIX_VEX_0F3A5C, | |
1392 | PREFIX_VEX_0F3A5D, | |
1393 | PREFIX_VEX_0F3A5E, | |
1394 | PREFIX_VEX_0F3A5F, | |
1395 | PREFIX_VEX_0F3A60, | |
1396 | PREFIX_VEX_0F3A61, | |
1397 | PREFIX_VEX_0F3A62, | |
1398 | PREFIX_VEX_0F3A63, | |
1399 | PREFIX_VEX_0F3A68, | |
1400 | PREFIX_VEX_0F3A69, | |
1401 | PREFIX_VEX_0F3A6A, | |
1402 | PREFIX_VEX_0F3A6B, | |
1403 | PREFIX_VEX_0F3A6C, | |
1404 | PREFIX_VEX_0F3A6D, | |
1405 | PREFIX_VEX_0F3A6E, | |
1406 | PREFIX_VEX_0F3A6F, | |
1407 | PREFIX_VEX_0F3A78, | |
1408 | PREFIX_VEX_0F3A79, | |
1409 | PREFIX_VEX_0F3A7A, | |
1410 | PREFIX_VEX_0F3A7B, | |
1411 | PREFIX_VEX_0F3A7C, | |
1412 | PREFIX_VEX_0F3A7D, | |
1413 | PREFIX_VEX_0F3A7E, | |
1414 | PREFIX_VEX_0F3A7F, | |
48521003 IT |
1415 | PREFIX_VEX_0F3ACE, |
1416 | PREFIX_VEX_0F3ACF, | |
6c30d220 | 1417 | PREFIX_VEX_0F3ADF, |
43234a1e L |
1418 | PREFIX_VEX_0F3AF0, |
1419 | ||
1420 | PREFIX_EVEX_0F10, | |
1421 | PREFIX_EVEX_0F11, | |
1422 | PREFIX_EVEX_0F12, | |
43234a1e | 1423 | PREFIX_EVEX_0F16, |
43234a1e | 1424 | PREFIX_EVEX_0F2A, |
43234a1e L |
1425 | PREFIX_EVEX_0F2C, |
1426 | PREFIX_EVEX_0F2D, | |
1427 | PREFIX_EVEX_0F2E, | |
1428 | PREFIX_EVEX_0F2F, | |
1429 | PREFIX_EVEX_0F51, | |
1430 | PREFIX_EVEX_0F58, | |
1431 | PREFIX_EVEX_0F59, | |
1432 | PREFIX_EVEX_0F5A, | |
1433 | PREFIX_EVEX_0F5B, | |
1434 | PREFIX_EVEX_0F5C, | |
1435 | PREFIX_EVEX_0F5D, | |
1436 | PREFIX_EVEX_0F5E, | |
1437 | PREFIX_EVEX_0F5F, | |
1ba585e8 IT |
1438 | PREFIX_EVEX_0F64, |
1439 | PREFIX_EVEX_0F65, | |
43234a1e | 1440 | PREFIX_EVEX_0F66, |
43234a1e L |
1441 | PREFIX_EVEX_0F6E, |
1442 | PREFIX_EVEX_0F6F, | |
1443 | PREFIX_EVEX_0F70, | |
1ba585e8 IT |
1444 | PREFIX_EVEX_0F71_REG_2, |
1445 | PREFIX_EVEX_0F71_REG_4, | |
1446 | PREFIX_EVEX_0F71_REG_6, | |
43234a1e L |
1447 | PREFIX_EVEX_0F72_REG_0, |
1448 | PREFIX_EVEX_0F72_REG_1, | |
1449 | PREFIX_EVEX_0F72_REG_2, | |
1450 | PREFIX_EVEX_0F72_REG_4, | |
1451 | PREFIX_EVEX_0F72_REG_6, | |
1452 | PREFIX_EVEX_0F73_REG_2, | |
1ba585e8 | 1453 | PREFIX_EVEX_0F73_REG_3, |
43234a1e | 1454 | PREFIX_EVEX_0F73_REG_6, |
1ba585e8 IT |
1455 | PREFIX_EVEX_0F73_REG_7, |
1456 | PREFIX_EVEX_0F74, | |
1457 | PREFIX_EVEX_0F75, | |
43234a1e L |
1458 | PREFIX_EVEX_0F76, |
1459 | PREFIX_EVEX_0F78, | |
1460 | PREFIX_EVEX_0F79, | |
1461 | PREFIX_EVEX_0F7A, | |
1462 | PREFIX_EVEX_0F7B, | |
1463 | PREFIX_EVEX_0F7E, | |
1464 | PREFIX_EVEX_0F7F, | |
1465 | PREFIX_EVEX_0FC2, | |
1ba585e8 IT |
1466 | PREFIX_EVEX_0FC4, |
1467 | PREFIX_EVEX_0FC5, | |
43234a1e L |
1468 | PREFIX_EVEX_0FD6, |
1469 | PREFIX_EVEX_0FDB, | |
1470 | PREFIX_EVEX_0FDF, | |
1471 | PREFIX_EVEX_0FE2, | |
1472 | PREFIX_EVEX_0FE6, | |
1473 | PREFIX_EVEX_0FE7, | |
1474 | PREFIX_EVEX_0FEB, | |
1475 | PREFIX_EVEX_0FEF, | |
43234a1e | 1476 | PREFIX_EVEX_0F380D, |
1ba585e8 | 1477 | PREFIX_EVEX_0F3810, |
43234a1e L |
1478 | PREFIX_EVEX_0F3811, |
1479 | PREFIX_EVEX_0F3812, | |
1480 | PREFIX_EVEX_0F3813, | |
1481 | PREFIX_EVEX_0F3814, | |
1482 | PREFIX_EVEX_0F3815, | |
1483 | PREFIX_EVEX_0F3816, | |
43234a1e L |
1484 | PREFIX_EVEX_0F3819, |
1485 | PREFIX_EVEX_0F381A, | |
1486 | PREFIX_EVEX_0F381B, | |
1487 | PREFIX_EVEX_0F381E, | |
1488 | PREFIX_EVEX_0F381F, | |
1ba585e8 | 1489 | PREFIX_EVEX_0F3820, |
43234a1e L |
1490 | PREFIX_EVEX_0F3821, |
1491 | PREFIX_EVEX_0F3822, | |
1492 | PREFIX_EVEX_0F3823, | |
1493 | PREFIX_EVEX_0F3824, | |
1494 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1495 | PREFIX_EVEX_0F3826, |
43234a1e L |
1496 | PREFIX_EVEX_0F3827, |
1497 | PREFIX_EVEX_0F3828, | |
1498 | PREFIX_EVEX_0F3829, | |
1499 | PREFIX_EVEX_0F382A, | |
1500 | PREFIX_EVEX_0F382C, | |
1501 | PREFIX_EVEX_0F382D, | |
1ba585e8 | 1502 | PREFIX_EVEX_0F3830, |
43234a1e L |
1503 | PREFIX_EVEX_0F3831, |
1504 | PREFIX_EVEX_0F3832, | |
1505 | PREFIX_EVEX_0F3833, | |
1506 | PREFIX_EVEX_0F3834, | |
1507 | PREFIX_EVEX_0F3835, | |
1508 | PREFIX_EVEX_0F3836, | |
1509 | PREFIX_EVEX_0F3837, | |
1ba585e8 | 1510 | PREFIX_EVEX_0F3838, |
43234a1e L |
1511 | PREFIX_EVEX_0F3839, |
1512 | PREFIX_EVEX_0F383A, | |
1513 | PREFIX_EVEX_0F383B, | |
1514 | PREFIX_EVEX_0F383D, | |
1515 | PREFIX_EVEX_0F383F, | |
1516 | PREFIX_EVEX_0F3840, | |
1517 | PREFIX_EVEX_0F3842, | |
1518 | PREFIX_EVEX_0F3843, | |
1519 | PREFIX_EVEX_0F3844, | |
1520 | PREFIX_EVEX_0F3845, | |
1521 | PREFIX_EVEX_0F3846, | |
1522 | PREFIX_EVEX_0F3847, | |
1523 | PREFIX_EVEX_0F384C, | |
1524 | PREFIX_EVEX_0F384D, | |
1525 | PREFIX_EVEX_0F384E, | |
1526 | PREFIX_EVEX_0F384F, | |
8cfcb765 IT |
1527 | PREFIX_EVEX_0F3850, |
1528 | PREFIX_EVEX_0F3851, | |
47acf0bd IT |
1529 | PREFIX_EVEX_0F3852, |
1530 | PREFIX_EVEX_0F3853, | |
ee6872be | 1531 | PREFIX_EVEX_0F3854, |
620214f7 | 1532 | PREFIX_EVEX_0F3855, |
43234a1e L |
1533 | PREFIX_EVEX_0F3859, |
1534 | PREFIX_EVEX_0F385A, | |
1535 | PREFIX_EVEX_0F385B, | |
53467f57 IT |
1536 | PREFIX_EVEX_0F3862, |
1537 | PREFIX_EVEX_0F3863, | |
43234a1e L |
1538 | PREFIX_EVEX_0F3864, |
1539 | PREFIX_EVEX_0F3865, | |
1ba585e8 | 1540 | PREFIX_EVEX_0F3866, |
9186c494 | 1541 | PREFIX_EVEX_0F3868, |
53467f57 IT |
1542 | PREFIX_EVEX_0F3870, |
1543 | PREFIX_EVEX_0F3871, | |
1544 | PREFIX_EVEX_0F3872, | |
1545 | PREFIX_EVEX_0F3873, | |
1ba585e8 | 1546 | PREFIX_EVEX_0F3875, |
43234a1e L |
1547 | PREFIX_EVEX_0F3876, |
1548 | PREFIX_EVEX_0F3877, | |
1ba585e8 IT |
1549 | PREFIX_EVEX_0F387A, |
1550 | PREFIX_EVEX_0F387B, | |
43234a1e | 1551 | PREFIX_EVEX_0F387C, |
1ba585e8 | 1552 | PREFIX_EVEX_0F387D, |
43234a1e L |
1553 | PREFIX_EVEX_0F387E, |
1554 | PREFIX_EVEX_0F387F, | |
14f195c9 | 1555 | PREFIX_EVEX_0F3883, |
43234a1e L |
1556 | PREFIX_EVEX_0F3888, |
1557 | PREFIX_EVEX_0F3889, | |
1558 | PREFIX_EVEX_0F388A, | |
1559 | PREFIX_EVEX_0F388B, | |
1ba585e8 | 1560 | PREFIX_EVEX_0F388D, |
ee6872be | 1561 | PREFIX_EVEX_0F388F, |
43234a1e L |
1562 | PREFIX_EVEX_0F3890, |
1563 | PREFIX_EVEX_0F3891, | |
1564 | PREFIX_EVEX_0F3892, | |
1565 | PREFIX_EVEX_0F3893, | |
43234a1e L |
1566 | PREFIX_EVEX_0F389A, |
1567 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1568 | PREFIX_EVEX_0F38A0, |
1569 | PREFIX_EVEX_0F38A1, | |
1570 | PREFIX_EVEX_0F38A2, | |
1571 | PREFIX_EVEX_0F38A3, | |
43234a1e L |
1572 | PREFIX_EVEX_0F38AA, |
1573 | PREFIX_EVEX_0F38AB, | |
2cc1b5aa IT |
1574 | PREFIX_EVEX_0F38B4, |
1575 | PREFIX_EVEX_0F38B5, | |
43234a1e L |
1576 | PREFIX_EVEX_0F38C4, |
1577 | PREFIX_EVEX_0F38C6_REG_1, | |
1578 | PREFIX_EVEX_0F38C6_REG_2, | |
1579 | PREFIX_EVEX_0F38C6_REG_5, | |
1580 | PREFIX_EVEX_0F38C6_REG_6, | |
1581 | PREFIX_EVEX_0F38C7_REG_1, | |
1582 | PREFIX_EVEX_0F38C7_REG_2, | |
1583 | PREFIX_EVEX_0F38C7_REG_5, | |
1584 | PREFIX_EVEX_0F38C7_REG_6, | |
1585 | PREFIX_EVEX_0F38C8, | |
1586 | PREFIX_EVEX_0F38CA, | |
1587 | PREFIX_EVEX_0F38CB, | |
1588 | PREFIX_EVEX_0F38CC, | |
1589 | PREFIX_EVEX_0F38CD, | |
1590 | ||
1591 | PREFIX_EVEX_0F3A00, | |
1592 | PREFIX_EVEX_0F3A01, | |
1593 | PREFIX_EVEX_0F3A03, | |
43234a1e L |
1594 | PREFIX_EVEX_0F3A05, |
1595 | PREFIX_EVEX_0F3A08, | |
1596 | PREFIX_EVEX_0F3A09, | |
1597 | PREFIX_EVEX_0F3A0A, | |
1598 | PREFIX_EVEX_0F3A0B, | |
1ba585e8 IT |
1599 | PREFIX_EVEX_0F3A14, |
1600 | PREFIX_EVEX_0F3A15, | |
90a915bf | 1601 | PREFIX_EVEX_0F3A16, |
43234a1e L |
1602 | PREFIX_EVEX_0F3A17, |
1603 | PREFIX_EVEX_0F3A18, | |
1604 | PREFIX_EVEX_0F3A19, | |
1605 | PREFIX_EVEX_0F3A1A, | |
1606 | PREFIX_EVEX_0F3A1B, | |
43234a1e L |
1607 | PREFIX_EVEX_0F3A1E, |
1608 | PREFIX_EVEX_0F3A1F, | |
1ba585e8 | 1609 | PREFIX_EVEX_0F3A20, |
43234a1e | 1610 | PREFIX_EVEX_0F3A21, |
90a915bf | 1611 | PREFIX_EVEX_0F3A22, |
43234a1e L |
1612 | PREFIX_EVEX_0F3A23, |
1613 | PREFIX_EVEX_0F3A25, | |
1614 | PREFIX_EVEX_0F3A26, | |
1615 | PREFIX_EVEX_0F3A27, | |
1616 | PREFIX_EVEX_0F3A38, | |
1617 | PREFIX_EVEX_0F3A39, | |
1618 | PREFIX_EVEX_0F3A3A, | |
1619 | PREFIX_EVEX_0F3A3B, | |
1ba585e8 IT |
1620 | PREFIX_EVEX_0F3A3E, |
1621 | PREFIX_EVEX_0F3A3F, | |
1622 | PREFIX_EVEX_0F3A42, | |
43234a1e | 1623 | PREFIX_EVEX_0F3A43, |
90a915bf IT |
1624 | PREFIX_EVEX_0F3A50, |
1625 | PREFIX_EVEX_0F3A51, | |
43234a1e | 1626 | PREFIX_EVEX_0F3A54, |
90a915bf IT |
1627 | PREFIX_EVEX_0F3A55, |
1628 | PREFIX_EVEX_0F3A56, | |
1629 | PREFIX_EVEX_0F3A57, | |
1630 | PREFIX_EVEX_0F3A66, | |
53467f57 IT |
1631 | PREFIX_EVEX_0F3A67, |
1632 | PREFIX_EVEX_0F3A70, | |
1633 | PREFIX_EVEX_0F3A71, | |
1634 | PREFIX_EVEX_0F3A72, | |
48521003 | 1635 | PREFIX_EVEX_0F3A73, |
51e7da1b | 1636 | }; |
4e7d34a6 | 1637 | |
51e7da1b L |
1638 | enum |
1639 | { | |
1640 | X86_64_06 = 0, | |
3873ba12 | 1641 | X86_64_07, |
1673df32 | 1642 | X86_64_0E, |
3873ba12 L |
1643 | X86_64_16, |
1644 | X86_64_17, | |
1645 | X86_64_1E, | |
1646 | X86_64_1F, | |
1647 | X86_64_27, | |
1648 | X86_64_2F, | |
1649 | X86_64_37, | |
1650 | X86_64_3F, | |
1651 | X86_64_60, | |
1652 | X86_64_61, | |
1653 | X86_64_62, | |
1654 | X86_64_63, | |
1655 | X86_64_6D, | |
1656 | X86_64_6F, | |
d039fef3 | 1657 | X86_64_82, |
3873ba12 | 1658 | X86_64_9A, |
aeab2b26 JB |
1659 | X86_64_C2, |
1660 | X86_64_C3, | |
3873ba12 L |
1661 | X86_64_C4, |
1662 | X86_64_C5, | |
1663 | X86_64_CE, | |
1664 | X86_64_D4, | |
1665 | X86_64_D5, | |
a72d2af2 L |
1666 | X86_64_E8, |
1667 | X86_64_E9, | |
3873ba12 L |
1668 | X86_64_EA, |
1669 | X86_64_0F01_REG_0, | |
1670 | X86_64_0F01_REG_1, | |
1671 | X86_64_0F01_REG_2, | |
1672 | X86_64_0F01_REG_3 | |
51e7da1b | 1673 | }; |
4e7d34a6 | 1674 | |
51e7da1b L |
1675 | enum |
1676 | { | |
1677 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1678 | THREE_BYTE_0F3A |
51e7da1b | 1679 | }; |
4e7d34a6 | 1680 | |
f88c9eb0 SP |
1681 | enum |
1682 | { | |
5dd85c99 SP |
1683 | XOP_08 = 0, |
1684 | XOP_09, | |
f88c9eb0 SP |
1685 | XOP_0A |
1686 | }; | |
1687 | ||
51e7da1b L |
1688 | enum |
1689 | { | |
1690 | VEX_0F = 0, | |
3873ba12 L |
1691 | VEX_0F38, |
1692 | VEX_0F3A | |
51e7da1b | 1693 | }; |
c0f3af97 | 1694 | |
43234a1e L |
1695 | enum |
1696 | { | |
1697 | EVEX_0F = 0, | |
1698 | EVEX_0F38, | |
1699 | EVEX_0F3A | |
1700 | }; | |
1701 | ||
51e7da1b L |
1702 | enum |
1703 | { | |
ec6f095a | 1704 | VEX_LEN_0F12_P_0_M_0 = 0, |
592a252b | 1705 | VEX_LEN_0F12_P_0_M_1, |
18897deb | 1706 | #define VEX_LEN_0F12_P_2_M_0 VEX_LEN_0F12_P_0_M_0 |
592a252b L |
1707 | VEX_LEN_0F13_M_0, |
1708 | VEX_LEN_0F16_P_0_M_0, | |
1709 | VEX_LEN_0F16_P_0_M_1, | |
18897deb | 1710 | #define VEX_LEN_0F16_P_2_M_0 VEX_LEN_0F16_P_0_M_0 |
592a252b | 1711 | VEX_LEN_0F17_M_0, |
43234a1e | 1712 | VEX_LEN_0F41_P_0, |
1ba585e8 | 1713 | VEX_LEN_0F41_P_2, |
43234a1e | 1714 | VEX_LEN_0F42_P_0, |
1ba585e8 | 1715 | VEX_LEN_0F42_P_2, |
43234a1e | 1716 | VEX_LEN_0F44_P_0, |
1ba585e8 | 1717 | VEX_LEN_0F44_P_2, |
43234a1e | 1718 | VEX_LEN_0F45_P_0, |
1ba585e8 | 1719 | VEX_LEN_0F45_P_2, |
43234a1e | 1720 | VEX_LEN_0F46_P_0, |
1ba585e8 | 1721 | VEX_LEN_0F46_P_2, |
43234a1e | 1722 | VEX_LEN_0F47_P_0, |
1ba585e8 IT |
1723 | VEX_LEN_0F47_P_2, |
1724 | VEX_LEN_0F4A_P_0, | |
1725 | VEX_LEN_0F4A_P_2, | |
1726 | VEX_LEN_0F4B_P_0, | |
43234a1e | 1727 | VEX_LEN_0F4B_P_2, |
592a252b | 1728 | VEX_LEN_0F6E_P_2, |
ec6f095a | 1729 | VEX_LEN_0F77_P_0, |
592a252b L |
1730 | VEX_LEN_0F7E_P_1, |
1731 | VEX_LEN_0F7E_P_2, | |
43234a1e | 1732 | VEX_LEN_0F90_P_0, |
1ba585e8 | 1733 | VEX_LEN_0F90_P_2, |
43234a1e | 1734 | VEX_LEN_0F91_P_0, |
1ba585e8 | 1735 | VEX_LEN_0F91_P_2, |
43234a1e | 1736 | VEX_LEN_0F92_P_0, |
90a915bf | 1737 | VEX_LEN_0F92_P_2, |
1ba585e8 | 1738 | VEX_LEN_0F92_P_3, |
43234a1e | 1739 | VEX_LEN_0F93_P_0, |
90a915bf | 1740 | VEX_LEN_0F93_P_2, |
1ba585e8 | 1741 | VEX_LEN_0F93_P_3, |
43234a1e | 1742 | VEX_LEN_0F98_P_0, |
1ba585e8 IT |
1743 | VEX_LEN_0F98_P_2, |
1744 | VEX_LEN_0F99_P_0, | |
1745 | VEX_LEN_0F99_P_2, | |
592a252b L |
1746 | VEX_LEN_0FAE_R_2_M_0, |
1747 | VEX_LEN_0FAE_R_3_M_0, | |
592a252b L |
1748 | VEX_LEN_0FC4_P_2, |
1749 | VEX_LEN_0FC5_P_2, | |
592a252b | 1750 | VEX_LEN_0FD6_P_2, |
592a252b | 1751 | VEX_LEN_0FF7_P_2, |
6c30d220 L |
1752 | VEX_LEN_0F3816_P_2, |
1753 | VEX_LEN_0F3819_P_2, | |
592a252b | 1754 | VEX_LEN_0F381A_P_2_M_0, |
6c30d220 | 1755 | VEX_LEN_0F3836_P_2, |
592a252b | 1756 | VEX_LEN_0F3841_P_2, |
6c30d220 | 1757 | VEX_LEN_0F385A_P_2_M_0, |
592a252b | 1758 | VEX_LEN_0F38DB_P_2, |
f12dc422 L |
1759 | VEX_LEN_0F38F2_P_0, |
1760 | VEX_LEN_0F38F3_R_1_P_0, | |
1761 | VEX_LEN_0F38F3_R_2_P_0, | |
1762 | VEX_LEN_0F38F3_R_3_P_0, | |
6c30d220 L |
1763 | VEX_LEN_0F38F5_P_0, |
1764 | VEX_LEN_0F38F5_P_1, | |
1765 | VEX_LEN_0F38F5_P_3, | |
1766 | VEX_LEN_0F38F6_P_3, | |
f12dc422 | 1767 | VEX_LEN_0F38F7_P_0, |
6c30d220 L |
1768 | VEX_LEN_0F38F7_P_1, |
1769 | VEX_LEN_0F38F7_P_2, | |
1770 | VEX_LEN_0F38F7_P_3, | |
1771 | VEX_LEN_0F3A00_P_2, | |
1772 | VEX_LEN_0F3A01_P_2, | |
592a252b | 1773 | VEX_LEN_0F3A06_P_2, |
592a252b L |
1774 | VEX_LEN_0F3A14_P_2, |
1775 | VEX_LEN_0F3A15_P_2, | |
1776 | VEX_LEN_0F3A16_P_2, | |
1777 | VEX_LEN_0F3A17_P_2, | |
1778 | VEX_LEN_0F3A18_P_2, | |
1779 | VEX_LEN_0F3A19_P_2, | |
1780 | VEX_LEN_0F3A20_P_2, | |
1781 | VEX_LEN_0F3A21_P_2, | |
1782 | VEX_LEN_0F3A22_P_2, | |
43234a1e | 1783 | VEX_LEN_0F3A30_P_2, |
1ba585e8 | 1784 | VEX_LEN_0F3A31_P_2, |
43234a1e | 1785 | VEX_LEN_0F3A32_P_2, |
1ba585e8 | 1786 | VEX_LEN_0F3A33_P_2, |
6c30d220 L |
1787 | VEX_LEN_0F3A38_P_2, |
1788 | VEX_LEN_0F3A39_P_2, | |
592a252b | 1789 | VEX_LEN_0F3A41_P_2, |
6c30d220 | 1790 | VEX_LEN_0F3A46_P_2, |
592a252b L |
1791 | VEX_LEN_0F3A60_P_2, |
1792 | VEX_LEN_0F3A61_P_2, | |
1793 | VEX_LEN_0F3A62_P_2, | |
1794 | VEX_LEN_0F3A63_P_2, | |
1795 | VEX_LEN_0F3A6A_P_2, | |
1796 | VEX_LEN_0F3A6B_P_2, | |
1797 | VEX_LEN_0F3A6E_P_2, | |
1798 | VEX_LEN_0F3A6F_P_2, | |
1799 | VEX_LEN_0F3A7A_P_2, | |
1800 | VEX_LEN_0F3A7B_P_2, | |
1801 | VEX_LEN_0F3A7E_P_2, | |
1802 | VEX_LEN_0F3A7F_P_2, | |
1803 | VEX_LEN_0F3ADF_P_2, | |
6c30d220 | 1804 | VEX_LEN_0F3AF0_P_3, |
ff688e1f L |
1805 | VEX_LEN_0FXOP_08_CC, |
1806 | VEX_LEN_0FXOP_08_CD, | |
1807 | VEX_LEN_0FXOP_08_CE, | |
1808 | VEX_LEN_0FXOP_08_CF, | |
1809 | VEX_LEN_0FXOP_08_EC, | |
1810 | VEX_LEN_0FXOP_08_ED, | |
1811 | VEX_LEN_0FXOP_08_EE, | |
1812 | VEX_LEN_0FXOP_08_EF, | |
b5b098c2 JB |
1813 | VEX_LEN_0FXOP_09_82_W_0, |
1814 | VEX_LEN_0FXOP_09_83_W_0, | |
51e7da1b | 1815 | }; |
c0f3af97 | 1816 | |
04e2a182 L |
1817 | enum |
1818 | { | |
1819 | EVEX_LEN_0F6E_P_2 = 0, | |
1820 | EVEX_LEN_0F7E_P_1, | |
1821 | EVEX_LEN_0F7E_P_2, | |
e74d9fa9 JB |
1822 | EVEX_LEN_0FC4_P_2, |
1823 | EVEX_LEN_0FC5_P_2, | |
12efd68d | 1824 | EVEX_LEN_0FD6_P_2, |
3a57774c | 1825 | EVEX_LEN_0F3816_P_2, |
f0a6222e L |
1826 | EVEX_LEN_0F3819_P_2_W_0, |
1827 | EVEX_LEN_0F3819_P_2_W_1, | |
bc152a17 JB |
1828 | EVEX_LEN_0F381A_P_2_W_0_M_0, |
1829 | EVEX_LEN_0F381A_P_2_W_1_M_0, | |
1830 | EVEX_LEN_0F381B_P_2_W_0_M_0, | |
1831 | EVEX_LEN_0F381B_P_2_W_1_M_0, | |
3a57774c | 1832 | EVEX_LEN_0F3836_P_2, |
bc152a17 JB |
1833 | EVEX_LEN_0F385A_P_2_W_0_M_0, |
1834 | EVEX_LEN_0F385A_P_2_W_1_M_0, | |
1835 | EVEX_LEN_0F385B_P_2_W_0_M_0, | |
1836 | EVEX_LEN_0F385B_P_2_W_1_M_0, | |
e395f487 L |
1837 | EVEX_LEN_0F38C6_REG_1_PREFIX_2, |
1838 | EVEX_LEN_0F38C6_REG_2_PREFIX_2, | |
1839 | EVEX_LEN_0F38C6_REG_5_PREFIX_2, | |
1840 | EVEX_LEN_0F38C6_REG_6_PREFIX_2, | |
1841 | EVEX_LEN_0F38C7_R_1_P_2_W_0, | |
1842 | EVEX_LEN_0F38C7_R_1_P_2_W_1, | |
1843 | EVEX_LEN_0F38C7_R_2_P_2_W_0, | |
1844 | EVEX_LEN_0F38C7_R_2_P_2_W_1, | |
1845 | EVEX_LEN_0F38C7_R_5_P_2_W_0, | |
1846 | EVEX_LEN_0F38C7_R_5_P_2_W_1, | |
1847 | EVEX_LEN_0F38C7_R_6_P_2_W_0, | |
1848 | EVEX_LEN_0F38C7_R_6_P_2_W_1, | |
3a57774c JB |
1849 | EVEX_LEN_0F3A00_P_2_W_1, |
1850 | EVEX_LEN_0F3A01_P_2_W_1, | |
e74d9fa9 JB |
1851 | EVEX_LEN_0F3A14_P_2, |
1852 | EVEX_LEN_0F3A15_P_2, | |
1853 | EVEX_LEN_0F3A16_P_2, | |
1854 | EVEX_LEN_0F3A17_P_2, | |
12efd68d L |
1855 | EVEX_LEN_0F3A18_P_2_W_0, |
1856 | EVEX_LEN_0F3A18_P_2_W_1, | |
1857 | EVEX_LEN_0F3A19_P_2_W_0, | |
1858 | EVEX_LEN_0F3A19_P_2_W_1, | |
1859 | EVEX_LEN_0F3A1A_P_2_W_0, | |
1860 | EVEX_LEN_0F3A1A_P_2_W_1, | |
1861 | EVEX_LEN_0F3A1B_P_2_W_0, | |
6e1c90b7 | 1862 | EVEX_LEN_0F3A1B_P_2_W_1, |
e74d9fa9 JB |
1863 | EVEX_LEN_0F3A20_P_2, |
1864 | EVEX_LEN_0F3A21_P_2_W_0, | |
1865 | EVEX_LEN_0F3A22_P_2, | |
6e1c90b7 L |
1866 | EVEX_LEN_0F3A23_P_2_W_0, |
1867 | EVEX_LEN_0F3A23_P_2_W_1, | |
1868 | EVEX_LEN_0F3A38_P_2_W_0, | |
1869 | EVEX_LEN_0F3A38_P_2_W_1, | |
1870 | EVEX_LEN_0F3A39_P_2_W_0, | |
1871 | EVEX_LEN_0F3A39_P_2_W_1, | |
1872 | EVEX_LEN_0F3A3A_P_2_W_0, | |
1873 | EVEX_LEN_0F3A3A_P_2_W_1, | |
1874 | EVEX_LEN_0F3A3B_P_2_W_0, | |
1875 | EVEX_LEN_0F3A3B_P_2_W_1, | |
1876 | EVEX_LEN_0F3A43_P_2_W_0, | |
1877 | EVEX_LEN_0F3A43_P_2_W_1 | |
04e2a182 L |
1878 | }; |
1879 | ||
9e30b8e0 L |
1880 | enum |
1881 | { | |
ec6f095a | 1882 | VEX_W_0F41_P_0_LEN_1 = 0, |
1ba585e8 | 1883 | VEX_W_0F41_P_2_LEN_1, |
43234a1e | 1884 | VEX_W_0F42_P_0_LEN_1, |
1ba585e8 | 1885 | VEX_W_0F42_P_2_LEN_1, |
43234a1e | 1886 | VEX_W_0F44_P_0_LEN_0, |
1ba585e8 | 1887 | VEX_W_0F44_P_2_LEN_0, |
43234a1e | 1888 | VEX_W_0F45_P_0_LEN_1, |
1ba585e8 | 1889 | VEX_W_0F45_P_2_LEN_1, |
43234a1e | 1890 | VEX_W_0F46_P_0_LEN_1, |
1ba585e8 | 1891 | VEX_W_0F46_P_2_LEN_1, |
43234a1e | 1892 | VEX_W_0F47_P_0_LEN_1, |
1ba585e8 IT |
1893 | VEX_W_0F47_P_2_LEN_1, |
1894 | VEX_W_0F4A_P_0_LEN_1, | |
1895 | VEX_W_0F4A_P_2_LEN_1, | |
1896 | VEX_W_0F4B_P_0_LEN_1, | |
43234a1e | 1897 | VEX_W_0F4B_P_2_LEN_1, |
43234a1e | 1898 | VEX_W_0F90_P_0_LEN_0, |
1ba585e8 | 1899 | VEX_W_0F90_P_2_LEN_0, |
43234a1e | 1900 | VEX_W_0F91_P_0_LEN_0, |
1ba585e8 | 1901 | VEX_W_0F91_P_2_LEN_0, |
43234a1e | 1902 | VEX_W_0F92_P_0_LEN_0, |
90a915bf | 1903 | VEX_W_0F92_P_2_LEN_0, |
43234a1e | 1904 | VEX_W_0F93_P_0_LEN_0, |
90a915bf | 1905 | VEX_W_0F93_P_2_LEN_0, |
43234a1e | 1906 | VEX_W_0F98_P_0_LEN_0, |
1ba585e8 IT |
1907 | VEX_W_0F98_P_2_LEN_0, |
1908 | VEX_W_0F99_P_0_LEN_0, | |
1909 | VEX_W_0F99_P_2_LEN_0, | |
592a252b L |
1910 | VEX_W_0F380C_P_2, |
1911 | VEX_W_0F380D_P_2, | |
1912 | VEX_W_0F380E_P_2, | |
1913 | VEX_W_0F380F_P_2, | |
6431c801 | 1914 | VEX_W_0F3813_P_2, |
6c30d220 | 1915 | VEX_W_0F3816_P_2, |
6c30d220 L |
1916 | VEX_W_0F3818_P_2, |
1917 | VEX_W_0F3819_P_2, | |
592a252b | 1918 | VEX_W_0F381A_P_2_M_0, |
592a252b L |
1919 | VEX_W_0F382C_P_2_M_0, |
1920 | VEX_W_0F382D_P_2_M_0, | |
1921 | VEX_W_0F382E_P_2_M_0, | |
1922 | VEX_W_0F382F_P_2_M_0, | |
6c30d220 | 1923 | VEX_W_0F3836_P_2, |
6c30d220 L |
1924 | VEX_W_0F3846_P_2, |
1925 | VEX_W_0F3858_P_2, | |
1926 | VEX_W_0F3859_P_2, | |
1927 | VEX_W_0F385A_P_2_M_0, | |
1928 | VEX_W_0F3878_P_2, | |
1929 | VEX_W_0F3879_P_2, | |
48521003 | 1930 | VEX_W_0F38CF_P_2, |
6c30d220 L |
1931 | VEX_W_0F3A00_P_2, |
1932 | VEX_W_0F3A01_P_2, | |
1933 | VEX_W_0F3A02_P_2, | |
592a252b L |
1934 | VEX_W_0F3A04_P_2, |
1935 | VEX_W_0F3A05_P_2, | |
1936 | VEX_W_0F3A06_P_2, | |
592a252b L |
1937 | VEX_W_0F3A18_P_2, |
1938 | VEX_W_0F3A19_P_2, | |
6431c801 | 1939 | VEX_W_0F3A1D_P_2, |
43234a1e | 1940 | VEX_W_0F3A30_P_2_LEN_0, |
1ba585e8 | 1941 | VEX_W_0F3A31_P_2_LEN_0, |
43234a1e | 1942 | VEX_W_0F3A32_P_2_LEN_0, |
1ba585e8 | 1943 | VEX_W_0F3A33_P_2_LEN_0, |
6c30d220 L |
1944 | VEX_W_0F3A38_P_2, |
1945 | VEX_W_0F3A39_P_2, | |
6c30d220 | 1946 | VEX_W_0F3A46_P_2, |
592a252b L |
1947 | VEX_W_0F3A48_P_2, |
1948 | VEX_W_0F3A49_P_2, | |
1949 | VEX_W_0F3A4A_P_2, | |
1950 | VEX_W_0F3A4B_P_2, | |
1951 | VEX_W_0F3A4C_P_2, | |
48521003 IT |
1952 | VEX_W_0F3ACE_P_2, |
1953 | VEX_W_0F3ACF_P_2, | |
43234a1e | 1954 | |
b5b098c2 JB |
1955 | VEX_W_0FXOP_09_80, |
1956 | VEX_W_0FXOP_09_81, | |
1957 | VEX_W_0FXOP_09_82, | |
1958 | VEX_W_0FXOP_09_83, | |
1959 | ||
36cc073e | 1960 | EVEX_W_0F10_P_1, |
36cc073e | 1961 | EVEX_W_0F10_P_3, |
36cc073e | 1962 | EVEX_W_0F11_P_1, |
36cc073e | 1963 | EVEX_W_0F11_P_3, |
43234a1e L |
1964 | EVEX_W_0F12_P_0_M_1, |
1965 | EVEX_W_0F12_P_1, | |
43234a1e | 1966 | EVEX_W_0F12_P_3, |
43234a1e L |
1967 | EVEX_W_0F16_P_0_M_1, |
1968 | EVEX_W_0F16_P_1, | |
43234a1e | 1969 | EVEX_W_0F2A_P_3, |
43234a1e | 1970 | EVEX_W_0F51_P_1, |
43234a1e | 1971 | EVEX_W_0F51_P_3, |
43234a1e | 1972 | EVEX_W_0F58_P_1, |
43234a1e | 1973 | EVEX_W_0F58_P_3, |
43234a1e | 1974 | EVEX_W_0F59_P_1, |
43234a1e L |
1975 | EVEX_W_0F59_P_3, |
1976 | EVEX_W_0F5A_P_0, | |
1977 | EVEX_W_0F5A_P_1, | |
1978 | EVEX_W_0F5A_P_2, | |
1979 | EVEX_W_0F5A_P_3, | |
1980 | EVEX_W_0F5B_P_0, | |
1981 | EVEX_W_0F5B_P_1, | |
1982 | EVEX_W_0F5B_P_2, | |
43234a1e | 1983 | EVEX_W_0F5C_P_1, |
43234a1e | 1984 | EVEX_W_0F5C_P_3, |
43234a1e | 1985 | EVEX_W_0F5D_P_1, |
43234a1e | 1986 | EVEX_W_0F5D_P_3, |
43234a1e | 1987 | EVEX_W_0F5E_P_1, |
43234a1e | 1988 | EVEX_W_0F5E_P_3, |
43234a1e | 1989 | EVEX_W_0F5F_P_1, |
43234a1e | 1990 | EVEX_W_0F5F_P_3, |
fedfb81e | 1991 | EVEX_W_0F62, |
43234a1e | 1992 | EVEX_W_0F66_P_2, |
fedfb81e JB |
1993 | EVEX_W_0F6A, |
1994 | EVEX_W_0F6B, | |
1995 | EVEX_W_0F6C, | |
1996 | EVEX_W_0F6D, | |
43234a1e L |
1997 | EVEX_W_0F6F_P_1, |
1998 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1999 | EVEX_W_0F6F_P_3, |
43234a1e L |
2000 | EVEX_W_0F70_P_2, |
2001 | EVEX_W_0F72_R_2_P_2, | |
2002 | EVEX_W_0F72_R_6_P_2, | |
2003 | EVEX_W_0F73_R_2_P_2, | |
2004 | EVEX_W_0F73_R_6_P_2, | |
2005 | EVEX_W_0F76_P_2, | |
2006 | EVEX_W_0F78_P_0, | |
90a915bf | 2007 | EVEX_W_0F78_P_2, |
43234a1e | 2008 | EVEX_W_0F79_P_0, |
90a915bf | 2009 | EVEX_W_0F79_P_2, |
43234a1e | 2010 | EVEX_W_0F7A_P_1, |
90a915bf | 2011 | EVEX_W_0F7A_P_2, |
43234a1e | 2012 | EVEX_W_0F7A_P_3, |
90a915bf | 2013 | EVEX_W_0F7B_P_2, |
43234a1e L |
2014 | EVEX_W_0F7B_P_3, |
2015 | EVEX_W_0F7E_P_1, | |
43234a1e L |
2016 | EVEX_W_0F7F_P_1, |
2017 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 2018 | EVEX_W_0F7F_P_3, |
43234a1e | 2019 | EVEX_W_0FC2_P_1, |
43234a1e | 2020 | EVEX_W_0FC2_P_3, |
fedfb81e JB |
2021 | EVEX_W_0FD2, |
2022 | EVEX_W_0FD3, | |
2023 | EVEX_W_0FD4, | |
43234a1e L |
2024 | EVEX_W_0FD6_P_2, |
2025 | EVEX_W_0FE6_P_1, | |
2026 | EVEX_W_0FE6_P_2, | |
2027 | EVEX_W_0FE6_P_3, | |
2028 | EVEX_W_0FE7_P_2, | |
fedfb81e JB |
2029 | EVEX_W_0FF2, |
2030 | EVEX_W_0FF3, | |
2031 | EVEX_W_0FF4, | |
2032 | EVEX_W_0FFA, | |
2033 | EVEX_W_0FFB, | |
2034 | EVEX_W_0FFE, | |
43234a1e | 2035 | EVEX_W_0F380D_P_2, |
1ba585e8 IT |
2036 | EVEX_W_0F3810_P_1, |
2037 | EVEX_W_0F3810_P_2, | |
43234a1e | 2038 | EVEX_W_0F3811_P_1, |
1ba585e8 | 2039 | EVEX_W_0F3811_P_2, |
43234a1e | 2040 | EVEX_W_0F3812_P_1, |
1ba585e8 | 2041 | EVEX_W_0F3812_P_2, |
43234a1e L |
2042 | EVEX_W_0F3813_P_1, |
2043 | EVEX_W_0F3813_P_2, | |
2044 | EVEX_W_0F3814_P_1, | |
2045 | EVEX_W_0F3815_P_1, | |
43234a1e L |
2046 | EVEX_W_0F3819_P_2, |
2047 | EVEX_W_0F381A_P_2, | |
2048 | EVEX_W_0F381B_P_2, | |
2049 | EVEX_W_0F381E_P_2, | |
2050 | EVEX_W_0F381F_P_2, | |
1ba585e8 | 2051 | EVEX_W_0F3820_P_1, |
43234a1e L |
2052 | EVEX_W_0F3821_P_1, |
2053 | EVEX_W_0F3822_P_1, | |
2054 | EVEX_W_0F3823_P_1, | |
2055 | EVEX_W_0F3824_P_1, | |
2056 | EVEX_W_0F3825_P_1, | |
2057 | EVEX_W_0F3825_P_2, | |
2058 | EVEX_W_0F3828_P_2, | |
2059 | EVEX_W_0F3829_P_2, | |
2060 | EVEX_W_0F382A_P_1, | |
2061 | EVEX_W_0F382A_P_2, | |
fedfb81e | 2062 | EVEX_W_0F382B, |
1ba585e8 | 2063 | EVEX_W_0F3830_P_1, |
43234a1e L |
2064 | EVEX_W_0F3831_P_1, |
2065 | EVEX_W_0F3832_P_1, | |
2066 | EVEX_W_0F3833_P_1, | |
2067 | EVEX_W_0F3834_P_1, | |
2068 | EVEX_W_0F3835_P_1, | |
2069 | EVEX_W_0F3835_P_2, | |
2070 | EVEX_W_0F3837_P_2, | |
2071 | EVEX_W_0F383A_P_1, | |
d6aab7a1 | 2072 | EVEX_W_0F3852_P_1, |
43234a1e L |
2073 | EVEX_W_0F3859_P_2, |
2074 | EVEX_W_0F385A_P_2, | |
2075 | EVEX_W_0F385B_P_2, | |
53467f57 IT |
2076 | EVEX_W_0F3862_P_2, |
2077 | EVEX_W_0F3863_P_2, | |
53467f57 | 2078 | EVEX_W_0F3870_P_2, |
d6aab7a1 | 2079 | EVEX_W_0F3872_P_1, |
53467f57 | 2080 | EVEX_W_0F3872_P_2, |
d6aab7a1 | 2081 | EVEX_W_0F3872_P_3, |
1ba585e8 IT |
2082 | EVEX_W_0F387A_P_2, |
2083 | EVEX_W_0F387B_P_2, | |
14f195c9 | 2084 | EVEX_W_0F3883_P_2, |
43234a1e L |
2085 | EVEX_W_0F3891_P_2, |
2086 | EVEX_W_0F3893_P_2, | |
2087 | EVEX_W_0F38A1_P_2, | |
2088 | EVEX_W_0F38A3_P_2, | |
2089 | EVEX_W_0F38C7_R_1_P_2, | |
2090 | EVEX_W_0F38C7_R_2_P_2, | |
2091 | EVEX_W_0F38C7_R_5_P_2, | |
2092 | EVEX_W_0F38C7_R_6_P_2, | |
2093 | ||
2094 | EVEX_W_0F3A00_P_2, | |
2095 | EVEX_W_0F3A01_P_2, | |
43234a1e L |
2096 | EVEX_W_0F3A05_P_2, |
2097 | EVEX_W_0F3A08_P_2, | |
2098 | EVEX_W_0F3A09_P_2, | |
2099 | EVEX_W_0F3A0A_P_2, | |
2100 | EVEX_W_0F3A0B_P_2, | |
2101 | EVEX_W_0F3A18_P_2, | |
2102 | EVEX_W_0F3A19_P_2, | |
2103 | EVEX_W_0F3A1A_P_2, | |
2104 | EVEX_W_0F3A1B_P_2, | |
43234a1e L |
2105 | EVEX_W_0F3A21_P_2, |
2106 | EVEX_W_0F3A23_P_2, | |
2107 | EVEX_W_0F3A38_P_2, | |
2108 | EVEX_W_0F3A39_P_2, | |
2109 | EVEX_W_0F3A3A_P_2, | |
2110 | EVEX_W_0F3A3B_P_2, | |
1ba585e8 | 2111 | EVEX_W_0F3A42_P_2, |
90a915bf | 2112 | EVEX_W_0F3A43_P_2, |
53467f57 | 2113 | EVEX_W_0F3A70_P_2, |
53467f57 | 2114 | EVEX_W_0F3A72_P_2, |
9e30b8e0 L |
2115 | }; |
2116 | ||
26ca5450 | 2117 | typedef void (*op_rtn) (int bytemode, int sizeflag); |
252b5132 RH |
2118 | |
2119 | struct dis386 { | |
2da11e11 | 2120 | const char *name; |
ce518a5f L |
2121 | struct |
2122 | { | |
2123 | op_rtn rtn; | |
2124 | int bytemode; | |
2125 | } op[MAX_OPERANDS]; | |
bf890a93 | 2126 | unsigned int prefix_requirement; |
252b5132 RH |
2127 | }; |
2128 | ||
2129 | /* Upper case letters in the instruction names here are macros. | |
2130 | 'A' => print 'b' if no register operands or suffix_always is true | |
2131 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 2132 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 2133 | size prefix |
ed7841b3 | 2134 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 2135 | suffix_always is true |
252b5132 | 2136 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 2137 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 2138 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 2139 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 2140 | 'I' unused. |
8f570d62 | 2141 | 'J' unused. |
42903f7f | 2142 | 'K' => print 'd' or 'q' if rex prefix is present. |
252b5132 | 2143 | 'L' => print 'l' if suffix_always is true |
9d141669 | 2144 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 2145 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 2146 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
52b15da3 | 2147 | 'P' => print 'w', 'l' or 'q' if instruction has an operand size prefix, |
98b528ac L |
2148 | or suffix_always is true. print 'q' if rex prefix is present. |
2149 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always | |
2150 | is true | |
a35ca55a | 2151 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 2152 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
a72d2af2 L |
2153 | 'T' => print 'q' in 64bit mode if instruction has no operand size |
2154 | prefix and behave as 'P' otherwise | |
2155 | 'U' => print 'q' in 64bit mode if instruction has no operand size | |
2156 | prefix and behave as 'Q' otherwise | |
2157 | 'V' => print 'q' in 64bit mode if instruction has no operand size | |
2158 | prefix and behave as 'S' otherwise | |
a35ca55a | 2159 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 2160 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
9646c87b | 2161 | 'Y' unused. |
6dd5059a | 2162 | 'Z' => print 'q' in 64bit mode and behave as 'L' otherwise |
9d141669 | 2163 | '!' => change condition from true to false or from false to true. |
98b528ac | 2164 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
2165 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
2166 | prefix or suffix_always is true (lcall/ljmp). | |
5db04b09 L |
2167 | '@' => print 'q' for Intel64 ISA, 'w' or 'q' for AMD64 ISA depending |
2168 | on operand size prefix. | |
07f5af7d L |
2169 | '&' => print 'q' in 64bit mode for Intel64 ISA or if instruction |
2170 | has no operand size prefix for AMD64 ISA, behave as 'P' | |
2171 | otherwise | |
98b528ac L |
2172 | |
2173 | 2 upper case letter macros: | |
04d824a4 JB |
2174 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
2175 | operands and no broadcast. | |
2176 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
2177 | register operands and no broadcast. | |
4b06377f | 2178 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
589958d6 JB |
2179 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory |
2180 | operand or no operand at all in 64bit mode, or if suffix_always | |
2181 | is true. | |
4b06377f L |
2182 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
2183 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
2184 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
6c30d220 | 2185 | "LW" => print 'd', 'q' depending on the VEX.W bit |
931452b6 | 2186 | "BW" => print 'b' or 'w' depending on the EVEX.W bit |
4b4c407a L |
2187 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
2188 | an operand size prefix, or suffix_always is true. print | |
2189 | 'q' if rex prefix is present. | |
52b15da3 | 2190 | |
6439fc28 AM |
2191 | Many of the above letters print nothing in Intel mode. See "putop" |
2192 | for the details. | |
52b15da3 | 2193 | |
6439fc28 | 2194 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 2195 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 2196 | |
6439fc28 | 2197 | static const struct dis386 dis386[] = { |
252b5132 | 2198 | /* 00 */ |
bf890a93 IT |
2199 | { "addB", { Ebh1, Gb }, 0 }, |
2200 | { "addS", { Evh1, Gv }, 0 }, | |
2201 | { "addB", { Gb, EbS }, 0 }, | |
2202 | { "addS", { Gv, EvS }, 0 }, | |
2203 | { "addB", { AL, Ib }, 0 }, | |
2204 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2205 | { X86_64_TABLE (X86_64_06) }, |
2206 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 2207 | /* 08 */ |
bf890a93 IT |
2208 | { "orB", { Ebh1, Gb }, 0 }, |
2209 | { "orS", { Evh1, Gv }, 0 }, | |
2210 | { "orB", { Gb, EbS }, 0 }, | |
2211 | { "orS", { Gv, EvS }, 0 }, | |
2212 | { "orB", { AL, Ib }, 0 }, | |
2213 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 2214 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 2215 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 2216 | /* 10 */ |
bf890a93 IT |
2217 | { "adcB", { Ebh1, Gb }, 0 }, |
2218 | { "adcS", { Evh1, Gv }, 0 }, | |
2219 | { "adcB", { Gb, EbS }, 0 }, | |
2220 | { "adcS", { Gv, EvS }, 0 }, | |
2221 | { "adcB", { AL, Ib }, 0 }, | |
2222 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2223 | { X86_64_TABLE (X86_64_16) }, |
2224 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 2225 | /* 18 */ |
bf890a93 IT |
2226 | { "sbbB", { Ebh1, Gb }, 0 }, |
2227 | { "sbbS", { Evh1, Gv }, 0 }, | |
2228 | { "sbbB", { Gb, EbS }, 0 }, | |
2229 | { "sbbS", { Gv, EvS }, 0 }, | |
2230 | { "sbbB", { AL, Ib }, 0 }, | |
2231 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
2232 | { X86_64_TABLE (X86_64_1E) }, |
2233 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 2234 | /* 20 */ |
bf890a93 IT |
2235 | { "andB", { Ebh1, Gb }, 0 }, |
2236 | { "andS", { Evh1, Gv }, 0 }, | |
2237 | { "andB", { Gb, EbS }, 0 }, | |
2238 | { "andS", { Gv, EvS }, 0 }, | |
2239 | { "andB", { AL, Ib }, 0 }, | |
2240 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 2241 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 2242 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 2243 | /* 28 */ |
bf890a93 IT |
2244 | { "subB", { Ebh1, Gb }, 0 }, |
2245 | { "subS", { Evh1, Gv }, 0 }, | |
2246 | { "subB", { Gb, EbS }, 0 }, | |
2247 | { "subS", { Gv, EvS }, 0 }, | |
2248 | { "subB", { AL, Ib }, 0 }, | |
2249 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 2250 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 2251 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 2252 | /* 30 */ |
bf890a93 IT |
2253 | { "xorB", { Ebh1, Gb }, 0 }, |
2254 | { "xorS", { Evh1, Gv }, 0 }, | |
2255 | { "xorB", { Gb, EbS }, 0 }, | |
2256 | { "xorS", { Gv, EvS }, 0 }, | |
2257 | { "xorB", { AL, Ib }, 0 }, | |
2258 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 2259 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 2260 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 2261 | /* 38 */ |
bf890a93 IT |
2262 | { "cmpB", { Eb, Gb }, 0 }, |
2263 | { "cmpS", { Ev, Gv }, 0 }, | |
2264 | { "cmpB", { Gb, EbS }, 0 }, | |
2265 | { "cmpS", { Gv, EvS }, 0 }, | |
2266 | { "cmpB", { AL, Ib }, 0 }, | |
2267 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 2268 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 2269 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 2270 | /* 40 */ |
bf890a93 IT |
2271 | { "inc{S|}", { RMeAX }, 0 }, |
2272 | { "inc{S|}", { RMeCX }, 0 }, | |
2273 | { "inc{S|}", { RMeDX }, 0 }, | |
2274 | { "inc{S|}", { RMeBX }, 0 }, | |
2275 | { "inc{S|}", { RMeSP }, 0 }, | |
2276 | { "inc{S|}", { RMeBP }, 0 }, | |
2277 | { "inc{S|}", { RMeSI }, 0 }, | |
2278 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 2279 | /* 48 */ |
bf890a93 IT |
2280 | { "dec{S|}", { RMeAX }, 0 }, |
2281 | { "dec{S|}", { RMeCX }, 0 }, | |
2282 | { "dec{S|}", { RMeDX }, 0 }, | |
2283 | { "dec{S|}", { RMeBX }, 0 }, | |
2284 | { "dec{S|}", { RMeSP }, 0 }, | |
2285 | { "dec{S|}", { RMeBP }, 0 }, | |
2286 | { "dec{S|}", { RMeSI }, 0 }, | |
2287 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 2288 | /* 50 */ |
bf890a93 IT |
2289 | { "pushV", { RMrAX }, 0 }, |
2290 | { "pushV", { RMrCX }, 0 }, | |
2291 | { "pushV", { RMrDX }, 0 }, | |
2292 | { "pushV", { RMrBX }, 0 }, | |
2293 | { "pushV", { RMrSP }, 0 }, | |
2294 | { "pushV", { RMrBP }, 0 }, | |
2295 | { "pushV", { RMrSI }, 0 }, | |
2296 | { "pushV", { RMrDI }, 0 }, | |
252b5132 | 2297 | /* 58 */ |
bf890a93 IT |
2298 | { "popV", { RMrAX }, 0 }, |
2299 | { "popV", { RMrCX }, 0 }, | |
2300 | { "popV", { RMrDX }, 0 }, | |
2301 | { "popV", { RMrBX }, 0 }, | |
2302 | { "popV", { RMrSP }, 0 }, | |
2303 | { "popV", { RMrBP }, 0 }, | |
2304 | { "popV", { RMrSI }, 0 }, | |
2305 | { "popV", { RMrDI }, 0 }, | |
252b5132 | 2306 | /* 60 */ |
4e7d34a6 L |
2307 | { X86_64_TABLE (X86_64_60) }, |
2308 | { X86_64_TABLE (X86_64_61) }, | |
2309 | { X86_64_TABLE (X86_64_62) }, | |
2310 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
2311 | { Bad_Opcode }, /* seg fs */ |
2312 | { Bad_Opcode }, /* seg gs */ | |
2313 | { Bad_Opcode }, /* op size prefix */ | |
2314 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 2315 | /* 68 */ |
bf890a93 IT |
2316 | { "pushT", { sIv }, 0 }, |
2317 | { "imulS", { Gv, Ev, Iv }, 0 }, | |
2318 | { "pushT", { sIbT }, 0 }, | |
2319 | { "imulS", { Gv, Ev, sIb }, 0 }, | |
2320 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 2321 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 2322 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 2323 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 2324 | /* 70 */ |
bf890a93 IT |
2325 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
2326 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
2327 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
2328 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2329 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2330 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
2331 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2332 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2333 | /* 78 */ |
bf890a93 IT |
2334 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
2335 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
2336 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2337 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
2338 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
2339 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
2340 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
2341 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2342 | /* 80 */ |
1ceb70f8 L |
2343 | { REG_TABLE (REG_80) }, |
2344 | { REG_TABLE (REG_81) }, | |
d039fef3 | 2345 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 2346 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
2347 | { "testB", { Eb, Gb }, 0 }, |
2348 | { "testS", { Ev, Gv }, 0 }, | |
2349 | { "xchgB", { Ebh2, Gb }, 0 }, | |
2350 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 2351 | /* 88 */ |
bf890a93 IT |
2352 | { "movB", { Ebh3, Gb }, 0 }, |
2353 | { "movS", { Evh3, Gv }, 0 }, | |
2354 | { "movB", { Gb, EbS }, 0 }, | |
2355 | { "movS", { Gv, EvS }, 0 }, | |
2356 | { "movD", { Sv, Sw }, 0 }, | |
1ceb70f8 | 2357 | { MOD_TABLE (MOD_8D) }, |
bf890a93 | 2358 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 2359 | { REG_TABLE (REG_8F) }, |
252b5132 | 2360 | /* 90 */ |
1ceb70f8 | 2361 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
2362 | { "xchgS", { RMeCX, eAX }, 0 }, |
2363 | { "xchgS", { RMeDX, eAX }, 0 }, | |
2364 | { "xchgS", { RMeBX, eAX }, 0 }, | |
2365 | { "xchgS", { RMeSP, eAX }, 0 }, | |
2366 | { "xchgS", { RMeBP, eAX }, 0 }, | |
2367 | { "xchgS", { RMeSI, eAX }, 0 }, | |
2368 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 2369 | /* 98 */ |
bf890a93 IT |
2370 | { "cW{t|}R", { XX }, 0 }, |
2371 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 2372 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 2373 | { Bad_Opcode }, /* fwait */ |
bf890a93 IT |
2374 | { "pushfT", { XX }, 0 }, |
2375 | { "popfT", { XX }, 0 }, | |
2376 | { "sahf", { XX }, 0 }, | |
2377 | { "lahf", { XX }, 0 }, | |
252b5132 | 2378 | /* a0 */ |
bf890a93 IT |
2379 | { "mov%LB", { AL, Ob }, 0 }, |
2380 | { "mov%LS", { eAX, Ov }, 0 }, | |
2381 | { "mov%LB", { Ob, AL }, 0 }, | |
2382 | { "mov%LS", { Ov, eAX }, 0 }, | |
2383 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
2384 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
2385 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
2386 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 2387 | /* a8 */ |
bf890a93 IT |
2388 | { "testB", { AL, Ib }, 0 }, |
2389 | { "testS", { eAX, Iv }, 0 }, | |
2390 | { "stosB", { Ybr, AL }, 0 }, | |
2391 | { "stosS", { Yvr, eAX }, 0 }, | |
2392 | { "lodsB", { ALr, Xb }, 0 }, | |
2393 | { "lodsS", { eAXr, Xv }, 0 }, | |
2394 | { "scasB", { AL, Yb }, 0 }, | |
2395 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 2396 | /* b0 */ |
bf890a93 IT |
2397 | { "movB", { RMAL, Ib }, 0 }, |
2398 | { "movB", { RMCL, Ib }, 0 }, | |
2399 | { "movB", { RMDL, Ib }, 0 }, | |
2400 | { "movB", { RMBL, Ib }, 0 }, | |
2401 | { "movB", { RMAH, Ib }, 0 }, | |
2402 | { "movB", { RMCH, Ib }, 0 }, | |
2403 | { "movB", { RMDH, Ib }, 0 }, | |
2404 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 2405 | /* b8 */ |
bf890a93 IT |
2406 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
2407 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
2408 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
2409 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
2410 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
2411 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
2412 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
2413 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 2414 | /* c0 */ |
1ceb70f8 L |
2415 | { REG_TABLE (REG_C0) }, |
2416 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
2417 | { X86_64_TABLE (X86_64_C2) }, |
2418 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
2419 | { X86_64_TABLE (X86_64_C4) }, |
2420 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
2421 | { REG_TABLE (REG_C6) }, |
2422 | { REG_TABLE (REG_C7) }, | |
252b5132 | 2423 | /* c8 */ |
bf890a93 IT |
2424 | { "enterT", { Iw, Ib }, 0 }, |
2425 | { "leaveT", { XX }, 0 }, | |
8f570d62 JB |
2426 | { "{l|}ret{|f}P", { Iw }, 0 }, |
2427 | { "{l|}ret{|f}P", { XX }, 0 }, | |
bf890a93 IT |
2428 | { "int3", { XX }, 0 }, |
2429 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 2430 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 2431 | { "iret%LP", { XX }, 0 }, |
252b5132 | 2432 | /* d0 */ |
1ceb70f8 L |
2433 | { REG_TABLE (REG_D0) }, |
2434 | { REG_TABLE (REG_D1) }, | |
2435 | { REG_TABLE (REG_D2) }, | |
2436 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
2437 | { X86_64_TABLE (X86_64_D4) }, |
2438 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 2439 | { Bad_Opcode }, |
bf890a93 | 2440 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
2441 | /* d8 */ |
2442 | { FLOAT }, | |
2443 | { FLOAT }, | |
2444 | { FLOAT }, | |
2445 | { FLOAT }, | |
2446 | { FLOAT }, | |
2447 | { FLOAT }, | |
2448 | { FLOAT }, | |
2449 | { FLOAT }, | |
2450 | /* e0 */ | |
bf890a93 IT |
2451 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2452 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2453 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2454 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2455 | { "inB", { AL, Ib }, 0 }, | |
2456 | { "inG", { zAX, Ib }, 0 }, | |
2457 | { "outB", { Ib, AL }, 0 }, | |
2458 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2459 | /* e8 */ |
a72d2af2 L |
2460 | { X86_64_TABLE (X86_64_E8) }, |
2461 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2462 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2463 | { "jmp", { Jb, BND }, 0 }, |
2464 | { "inB", { AL, indirDX }, 0 }, | |
2465 | { "inG", { zAX, indirDX }, 0 }, | |
2466 | { "outB", { indirDX, AL }, 0 }, | |
2467 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2468 | /* f0 */ |
592d1631 | 2469 | { Bad_Opcode }, /* lock prefix */ |
bf890a93 | 2470 | { "icebp", { XX }, 0 }, |
592d1631 L |
2471 | { Bad_Opcode }, /* repne */ |
2472 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2473 | { "hlt", { XX }, 0 }, |
2474 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2475 | { REG_TABLE (REG_F6) }, |
2476 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2477 | /* f8 */ |
bf890a93 IT |
2478 | { "clc", { XX }, 0 }, |
2479 | { "stc", { XX }, 0 }, | |
2480 | { "cli", { XX }, 0 }, | |
2481 | { "sti", { XX }, 0 }, | |
2482 | { "cld", { XX }, 0 }, | |
2483 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2484 | { REG_TABLE (REG_FE) }, |
2485 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2486 | }; |
2487 | ||
6439fc28 | 2488 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2489 | /* 00 */ |
1ceb70f8 L |
2490 | { REG_TABLE (REG_0F00 ) }, |
2491 | { REG_TABLE (REG_0F01 ) }, | |
bf890a93 IT |
2492 | { "larS", { Gv, Ew }, 0 }, |
2493 | { "lslS", { Gv, Ew }, 0 }, | |
592d1631 | 2494 | { Bad_Opcode }, |
bf890a93 IT |
2495 | { "syscall", { XX }, 0 }, |
2496 | { "clts", { XX }, 0 }, | |
589958d6 | 2497 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2498 | /* 08 */ |
bf890a93 | 2499 | { "invd", { XX }, 0 }, |
3233d7d0 | 2500 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2501 | { Bad_Opcode }, |
bf890a93 | 2502 | { "ud2", { XX }, 0 }, |
592d1631 | 2503 | { Bad_Opcode }, |
b5b1fc4f | 2504 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2505 | { "femms", { XX }, 0 }, |
2506 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2507 | /* 10 */ |
1ceb70f8 L |
2508 | { PREFIX_TABLE (PREFIX_0F10) }, |
2509 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2510 | { PREFIX_TABLE (PREFIX_0F12) }, | |
2511 | { MOD_TABLE (MOD_0F13) }, | |
507bd325 L |
2512 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2513 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2514 | { PREFIX_TABLE (PREFIX_0F16) }, |
2515 | { MOD_TABLE (MOD_0F17) }, | |
252b5132 | 2516 | /* 18 */ |
1ceb70f8 | 2517 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2518 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2519 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2520 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2521 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2522 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2523 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2524 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2525 | /* 20 */ |
bf890a93 IT |
2526 | { "movZ", { Rm, Cm }, 0 }, |
2527 | { "movZ", { Rm, Dm }, 0 }, | |
2528 | { "movZ", { Cm, Rm }, 0 }, | |
2529 | { "movZ", { Dm, Rm }, 0 }, | |
1ceb70f8 | 2530 | { MOD_TABLE (MOD_0F24) }, |
592d1631 | 2531 | { Bad_Opcode }, |
1ceb70f8 | 2532 | { MOD_TABLE (MOD_0F26) }, |
592d1631 | 2533 | { Bad_Opcode }, |
252b5132 | 2534 | /* 28 */ |
507bd325 L |
2535 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2536 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2537 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2538 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2539 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2540 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2541 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2542 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2543 | /* 30 */ |
bf890a93 IT |
2544 | { "wrmsr", { XX }, 0 }, |
2545 | { "rdtsc", { XX }, 0 }, | |
2546 | { "rdmsr", { XX }, 0 }, | |
2547 | { "rdpmc", { XX }, 0 }, | |
d835a58b JB |
2548 | { "sysenter", { SEP }, 0 }, |
2549 | { "sysexit", { SEP }, 0 }, | |
592d1631 | 2550 | { Bad_Opcode }, |
bf890a93 | 2551 | { "getsec", { XX }, 0 }, |
252b5132 | 2552 | /* 38 */ |
507bd325 | 2553 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F38, PREFIX_OPCODE) }, |
592d1631 | 2554 | { Bad_Opcode }, |
507bd325 | 2555 | { THREE_BYTE_TABLE_PREFIX (THREE_BYTE_0F3A, PREFIX_OPCODE) }, |
592d1631 L |
2556 | { Bad_Opcode }, |
2557 | { Bad_Opcode }, | |
2558 | { Bad_Opcode }, | |
2559 | { Bad_Opcode }, | |
2560 | { Bad_Opcode }, | |
252b5132 | 2561 | /* 40 */ |
bf890a93 IT |
2562 | { "cmovoS", { Gv, Ev }, 0 }, |
2563 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2564 | { "cmovbS", { Gv, Ev }, 0 }, | |
2565 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2566 | { "cmoveS", { Gv, Ev }, 0 }, | |
2567 | { "cmovneS", { Gv, Ev }, 0 }, | |
2568 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2569 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2570 | /* 48 */ |
bf890a93 IT |
2571 | { "cmovsS", { Gv, Ev }, 0 }, |
2572 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2573 | { "cmovpS", { Gv, Ev }, 0 }, | |
2574 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2575 | { "cmovlS", { Gv, Ev }, 0 }, | |
2576 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2577 | { "cmovleS", { Gv, Ev }, 0 }, | |
2578 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2579 | /* 50 */ |
a5aaedb9 | 2580 | { MOD_TABLE (MOD_0F50) }, |
1ceb70f8 L |
2581 | { PREFIX_TABLE (PREFIX_0F51) }, |
2582 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2583 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2584 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2585 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2586 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2587 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2588 | /* 58 */ |
1ceb70f8 L |
2589 | { PREFIX_TABLE (PREFIX_0F58) }, |
2590 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2591 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2592 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2593 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2594 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2595 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2596 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2597 | /* 60 */ |
1ceb70f8 L |
2598 | { PREFIX_TABLE (PREFIX_0F60) }, |
2599 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2600 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2601 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2602 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2603 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2604 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2605 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2606 | /* 68 */ |
507bd325 L |
2607 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2608 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2609 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2610 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2611 | { PREFIX_TABLE (PREFIX_0F6C) }, |
2612 | { PREFIX_TABLE (PREFIX_0F6D) }, | |
507bd325 | 2613 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2614 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2615 | /* 70 */ |
1ceb70f8 L |
2616 | { PREFIX_TABLE (PREFIX_0F70) }, |
2617 | { REG_TABLE (REG_0F71) }, | |
2618 | { REG_TABLE (REG_0F72) }, | |
2619 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2620 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2621 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2622 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2623 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2624 | /* 78 */ |
1ceb70f8 L |
2625 | { PREFIX_TABLE (PREFIX_0F78) }, |
2626 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2627 | { Bad_Opcode }, |
592d1631 | 2628 | { Bad_Opcode }, |
1ceb70f8 L |
2629 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2630 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2631 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2632 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2633 | /* 80 */ |
bf890a93 IT |
2634 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2635 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2636 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2637 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2638 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2639 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2640 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2641 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2642 | /* 88 */ |
bf890a93 IT |
2643 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2644 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2645 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2646 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2647 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2648 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2649 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2650 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2651 | /* 90 */ |
bf890a93 IT |
2652 | { "seto", { Eb }, 0 }, |
2653 | { "setno", { Eb }, 0 }, | |
2654 | { "setb", { Eb }, 0 }, | |
2655 | { "setae", { Eb }, 0 }, | |
2656 | { "sete", { Eb }, 0 }, | |
2657 | { "setne", { Eb }, 0 }, | |
2658 | { "setbe", { Eb }, 0 }, | |
2659 | { "seta", { Eb }, 0 }, | |
252b5132 | 2660 | /* 98 */ |
bf890a93 IT |
2661 | { "sets", { Eb }, 0 }, |
2662 | { "setns", { Eb }, 0 }, | |
2663 | { "setp", { Eb }, 0 }, | |
2664 | { "setnp", { Eb }, 0 }, | |
2665 | { "setl", { Eb }, 0 }, | |
2666 | { "setge", { Eb }, 0 }, | |
2667 | { "setle", { Eb }, 0 }, | |
2668 | { "setg", { Eb }, 0 }, | |
252b5132 | 2669 | /* a0 */ |
bf890a93 IT |
2670 | { "pushT", { fs }, 0 }, |
2671 | { "popT", { fs }, 0 }, | |
2672 | { "cpuid", { XX }, 0 }, | |
2673 | { "btS", { Ev, Gv }, 0 }, | |
2674 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2675 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2676 | { REG_TABLE (REG_0FA6) }, |
2677 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2678 | /* a8 */ |
bf890a93 IT |
2679 | { "pushT", { gs }, 0 }, |
2680 | { "popT", { gs }, 0 }, | |
2681 | { "rsm", { XX }, 0 }, | |
2682 | { "btsS", { Evh1, Gv }, 0 }, | |
2683 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2684 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2685 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2686 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2687 | /* b0 */ |
bf890a93 IT |
2688 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2689 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2690 | { MOD_TABLE (MOD_0FB2) }, |
bf890a93 | 2691 | { "btrS", { Evh1, Gv }, 0 }, |
1ceb70f8 L |
2692 | { MOD_TABLE (MOD_0FB4) }, |
2693 | { MOD_TABLE (MOD_0FB5) }, | |
bf890a93 IT |
2694 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2695 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2696 | /* b8 */ |
1ceb70f8 | 2697 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2698 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2699 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2700 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2701 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2702 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2703 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2704 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2705 | /* c0 */ |
bf890a93 IT |
2706 | { "xaddB", { Ebh1, Gb }, 0 }, |
2707 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2708 | { PREFIX_TABLE (PREFIX_0FC2) }, |
a8484f96 | 2709 | { MOD_TABLE (MOD_0FC3) }, |
507bd325 L |
2710 | { "pinsrw", { MX, Edqw, Ib }, PREFIX_OPCODE }, |
2711 | { "pextrw", { Gdq, MS, Ib }, PREFIX_OPCODE }, | |
2712 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
1ceb70f8 | 2713 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2714 | /* c8 */ |
bf890a93 IT |
2715 | { "bswap", { RMeAX }, 0 }, |
2716 | { "bswap", { RMeCX }, 0 }, | |
2717 | { "bswap", { RMeDX }, 0 }, | |
2718 | { "bswap", { RMeBX }, 0 }, | |
2719 | { "bswap", { RMeSP }, 0 }, | |
2720 | { "bswap", { RMeBP }, 0 }, | |
2721 | { "bswap", { RMeSI }, 0 }, | |
2722 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2723 | /* d0 */ |
1ceb70f8 | 2724 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2725 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2726 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2727 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2728 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2729 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2730 | { PREFIX_TABLE (PREFIX_0FD6) }, |
75c135a8 | 2731 | { MOD_TABLE (MOD_0FD7) }, |
252b5132 | 2732 | /* d8 */ |
507bd325 L |
2733 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2734 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2735 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2736 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2737 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2738 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2739 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2740 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2741 | /* e0 */ |
507bd325 L |
2742 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2743 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2744 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2745 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2746 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2747 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2748 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2749 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2750 | /* e8 */ |
507bd325 L |
2751 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2752 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2753 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2754 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2755 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2756 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2757 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2758 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2759 | /* f0 */ |
1ceb70f8 | 2760 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2761 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2762 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2763 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2764 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2765 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2766 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2767 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2768 | /* f8 */ |
507bd325 L |
2769 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2770 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2771 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2772 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2773 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2774 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2775 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2776 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2777 | }; |
2778 | ||
2779 | static const unsigned char onebyte_has_modrm[256] = { | |
c608c12e AM |
2780 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2781 | /* ------------------------------- */ | |
2782 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2783 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2784 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2785 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2786 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2787 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2788 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2789 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2790 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2791 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2792 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2793 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2794 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2795 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2796 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2797 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2798 | /* ------------------------------- */ | |
2799 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2800 | }; |
2801 | ||
2802 | static const unsigned char twobyte_has_modrm[256] = { | |
c608c12e AM |
2803 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2804 | /* ------------------------------- */ | |
252b5132 | 2805 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2806 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2807 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2808 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2809 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2810 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2811 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2812 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2813 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2814 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2815 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2816 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2817 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2818 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2819 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2820 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2821 | /* ------------------------------- */ |
2822 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2823 | }; | |
2824 | ||
252b5132 RH |
2825 | static char obuf[100]; |
2826 | static char *obufp; | |
ea397f5b | 2827 | static char *mnemonicendp; |
252b5132 RH |
2828 | static char scratchbuf[100]; |
2829 | static unsigned char *start_codep; | |
2830 | static unsigned char *insn_codep; | |
2831 | static unsigned char *codep; | |
285ca992 | 2832 | static unsigned char *end_codep; |
f16cd0d5 L |
2833 | static int last_lock_prefix; |
2834 | static int last_repz_prefix; | |
2835 | static int last_repnz_prefix; | |
2836 | static int last_data_prefix; | |
2837 | static int last_addr_prefix; | |
2838 | static int last_rex_prefix; | |
2839 | static int last_seg_prefix; | |
d9949a36 | 2840 | static int fwait_prefix; |
285ca992 L |
2841 | /* The active segment register prefix. */ |
2842 | static int active_seg_prefix; | |
f16cd0d5 L |
2843 | #define MAX_CODE_LENGTH 15 |
2844 | /* We can up to 14 prefixes since the maximum instruction length is | |
2845 | 15bytes. */ | |
2846 | static int all_prefixes[MAX_CODE_LENGTH - 1]; | |
252b5132 | 2847 | static disassemble_info *the_info; |
7967e09e L |
2848 | static struct |
2849 | { | |
2850 | int mod; | |
7967e09e | 2851 | int reg; |
484c222e | 2852 | int rm; |
7967e09e L |
2853 | } |
2854 | modrm; | |
4bba6815 | 2855 | static unsigned char need_modrm; |
dfc8cf43 L |
2856 | static struct |
2857 | { | |
2858 | int scale; | |
2859 | int index; | |
2860 | int base; | |
2861 | } | |
2862 | sib; | |
c0f3af97 L |
2863 | static struct |
2864 | { | |
2865 | int register_specifier; | |
2866 | int length; | |
2867 | int prefix; | |
2868 | int w; | |
43234a1e L |
2869 | int evex; |
2870 | int r; | |
2871 | int v; | |
2872 | int mask_register_specifier; | |
2873 | int zeroing; | |
2874 | int ll; | |
2875 | int b; | |
c0f3af97 L |
2876 | } |
2877 | vex; | |
2878 | static unsigned char need_vex; | |
2879 | static unsigned char need_vex_reg; | |
dae39acc | 2880 | static unsigned char vex_w_done; |
252b5132 | 2881 | |
ea397f5b L |
2882 | struct op |
2883 | { | |
2884 | const char *name; | |
2885 | unsigned int len; | |
2886 | }; | |
2887 | ||
4bba6815 AM |
2888 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2889 | values are stale. Hitting this abort likely indicates that you | |
2890 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
2891 | #define MODRM_CHECK if (!need_modrm) abort () | |
2892 | ||
d708bcba AM |
2893 | static const char **names64; |
2894 | static const char **names32; | |
2895 | static const char **names16; | |
2896 | static const char **names8; | |
2897 | static const char **names8rex; | |
2898 | static const char **names_seg; | |
db51cc60 L |
2899 | static const char *index64; |
2900 | static const char *index32; | |
d708bcba | 2901 | static const char **index16; |
7e8b059b | 2902 | static const char **names_bnd; |
d708bcba AM |
2903 | |
2904 | static const char *intel_names64[] = { | |
2905 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", | |
2906 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" | |
2907 | }; | |
2908 | static const char *intel_names32[] = { | |
2909 | "eax", "ecx", "edx", "ebx", "esp", "ebp", "esi", "edi", | |
2910 | "r8d", "r9d", "r10d", "r11d", "r12d", "r13d", "r14d", "r15d" | |
2911 | }; | |
2912 | static const char *intel_names16[] = { | |
2913 | "ax", "cx", "dx", "bx", "sp", "bp", "si", "di", | |
2914 | "r8w", "r9w", "r10w", "r11w", "r12w", "r13w", "r14w", "r15w" | |
2915 | }; | |
2916 | static const char *intel_names8[] = { | |
2917 | "al", "cl", "dl", "bl", "ah", "ch", "dh", "bh", | |
2918 | }; | |
2919 | static const char *intel_names8rex[] = { | |
2920 | "al", "cl", "dl", "bl", "spl", "bpl", "sil", "dil", | |
2921 | "r8b", "r9b", "r10b", "r11b", "r12b", "r13b", "r14b", "r15b" | |
2922 | }; | |
2923 | static const char *intel_names_seg[] = { | |
2924 | "es", "cs", "ss", "ds", "fs", "gs", "?", "?", | |
2925 | }; | |
db51cc60 L |
2926 | static const char *intel_index64 = "riz"; |
2927 | static const char *intel_index32 = "eiz"; | |
d708bcba AM |
2928 | static const char *intel_index16[] = { |
2929 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" | |
2930 | }; | |
2931 | ||
2932 | static const char *att_names64[] = { | |
2933 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", | |
52b15da3 JH |
2934 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2935 | }; | |
d708bcba AM |
2936 | static const char *att_names32[] = { |
2937 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", | |
52b15da3 | 2938 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2939 | }; |
d708bcba AM |
2940 | static const char *att_names16[] = { |
2941 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", | |
52b15da3 | 2942 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2943 | }; |
d708bcba AM |
2944 | static const char *att_names8[] = { |
2945 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", | |
252b5132 | 2946 | }; |
d708bcba AM |
2947 | static const char *att_names8rex[] = { |
2948 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", | |
52b15da3 JH |
2949 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2950 | }; | |
d708bcba AM |
2951 | static const char *att_names_seg[] = { |
2952 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", | |
252b5132 | 2953 | }; |
db51cc60 L |
2954 | static const char *att_index64 = "%riz"; |
2955 | static const char *att_index32 = "%eiz"; | |
d708bcba AM |
2956 | static const char *att_index16[] = { |
2957 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" | |
252b5132 RH |
2958 | }; |
2959 | ||
b9733481 L |
2960 | static const char **names_mm; |
2961 | static const char *intel_names_mm[] = { | |
2962 | "mm0", "mm1", "mm2", "mm3", | |
2963 | "mm4", "mm5", "mm6", "mm7" | |
2964 | }; | |
2965 | static const char *att_names_mm[] = { | |
2966 | "%mm0", "%mm1", "%mm2", "%mm3", | |
2967 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2968 | }; | |
2969 | ||
7e8b059b L |
2970 | static const char *intel_names_bnd[] = { |
2971 | "bnd0", "bnd1", "bnd2", "bnd3" | |
2972 | }; | |
2973 | ||
2974 | static const char *att_names_bnd[] = { | |
2975 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" | |
2976 | }; | |
2977 | ||
b9733481 L |
2978 | static const char **names_xmm; |
2979 | static const char *intel_names_xmm[] = { | |
2980 | "xmm0", "xmm1", "xmm2", "xmm3", | |
2981 | "xmm4", "xmm5", "xmm6", "xmm7", | |
2982 | "xmm8", "xmm9", "xmm10", "xmm11", | |
43234a1e L |
2983 | "xmm12", "xmm13", "xmm14", "xmm15", |
2984 | "xmm16", "xmm17", "xmm18", "xmm19", | |
2985 | "xmm20", "xmm21", "xmm22", "xmm23", | |
2986 | "xmm24", "xmm25", "xmm26", "xmm27", | |
2987 | "xmm28", "xmm29", "xmm30", "xmm31" | |
b9733481 L |
2988 | }; |
2989 | static const char *att_names_xmm[] = { | |
2990 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", | |
2991 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2992 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
2993 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
2994 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
2995 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
2996 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
2997 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
2998 | }; |
2999 | ||
3000 | static const char **names_ymm; | |
3001 | static const char *intel_names_ymm[] = { | |
3002 | "ymm0", "ymm1", "ymm2", "ymm3", | |
3003 | "ymm4", "ymm5", "ymm6", "ymm7", | |
3004 | "ymm8", "ymm9", "ymm10", "ymm11", | |
43234a1e L |
3005 | "ymm12", "ymm13", "ymm14", "ymm15", |
3006 | "ymm16", "ymm17", "ymm18", "ymm19", | |
3007 | "ymm20", "ymm21", "ymm22", "ymm23", | |
3008 | "ymm24", "ymm25", "ymm26", "ymm27", | |
3009 | "ymm28", "ymm29", "ymm30", "ymm31" | |
b9733481 L |
3010 | }; |
3011 | static const char *att_names_ymm[] = { | |
3012 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", | |
3013 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
3014 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
3015 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
3016 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
3017 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
3018 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
3019 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
3020 | }; | |
3021 | ||
3022 | static const char **names_zmm; | |
3023 | static const char *intel_names_zmm[] = { | |
3024 | "zmm0", "zmm1", "zmm2", "zmm3", | |
3025 | "zmm4", "zmm5", "zmm6", "zmm7", | |
3026 | "zmm8", "zmm9", "zmm10", "zmm11", | |
3027 | "zmm12", "zmm13", "zmm14", "zmm15", | |
3028 | "zmm16", "zmm17", "zmm18", "zmm19", | |
3029 | "zmm20", "zmm21", "zmm22", "zmm23", | |
3030 | "zmm24", "zmm25", "zmm26", "zmm27", | |
3031 | "zmm28", "zmm29", "zmm30", "zmm31" | |
3032 | }; | |
3033 | static const char *att_names_zmm[] = { | |
3034 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", | |
3035 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
3036 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
3037 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
3038 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
3039 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
3040 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
3041 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
3042 | }; | |
3043 | ||
3044 | static const char **names_mask; | |
3045 | static const char *intel_names_mask[] = { | |
3046 | "k0", "k1", "k2", "k3", "k4", "k5", "k6", "k7" | |
3047 | }; | |
3048 | static const char *att_names_mask[] = { | |
3049 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" | |
3050 | }; | |
3051 | ||
3052 | static const char *names_rounding[] = | |
3053 | { | |
3054 | "{rn-sae}", | |
3055 | "{rd-sae}", | |
3056 | "{ru-sae}", | |
3057 | "{rz-sae}" | |
b9733481 L |
3058 | }; |
3059 | ||
1ceb70f8 L |
3060 | static const struct dis386 reg_table[][8] = { |
3061 | /* REG_80 */ | |
252b5132 | 3062 | { |
bf890a93 IT |
3063 | { "addA", { Ebh1, Ib }, 0 }, |
3064 | { "orA", { Ebh1, Ib }, 0 }, | |
3065 | { "adcA", { Ebh1, Ib }, 0 }, | |
3066 | { "sbbA", { Ebh1, Ib }, 0 }, | |
3067 | { "andA", { Ebh1, Ib }, 0 }, | |
3068 | { "subA", { Ebh1, Ib }, 0 }, | |
3069 | { "xorA", { Ebh1, Ib }, 0 }, | |
3070 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 3071 | }, |
1ceb70f8 | 3072 | /* REG_81 */ |
252b5132 | 3073 | { |
bf890a93 IT |
3074 | { "addQ", { Evh1, Iv }, 0 }, |
3075 | { "orQ", { Evh1, Iv }, 0 }, | |
3076 | { "adcQ", { Evh1, Iv }, 0 }, | |
3077 | { "sbbQ", { Evh1, Iv }, 0 }, | |
3078 | { "andQ", { Evh1, Iv }, 0 }, | |
3079 | { "subQ", { Evh1, Iv }, 0 }, | |
3080 | { "xorQ", { Evh1, Iv }, 0 }, | |
3081 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 3082 | }, |
7148c369 | 3083 | /* REG_83 */ |
252b5132 | 3084 | { |
bf890a93 IT |
3085 | { "addQ", { Evh1, sIb }, 0 }, |
3086 | { "orQ", { Evh1, sIb }, 0 }, | |
3087 | { "adcQ", { Evh1, sIb }, 0 }, | |
3088 | { "sbbQ", { Evh1, sIb }, 0 }, | |
3089 | { "andQ", { Evh1, sIb }, 0 }, | |
3090 | { "subQ", { Evh1, sIb }, 0 }, | |
3091 | { "xorQ", { Evh1, sIb }, 0 }, | |
3092 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 3093 | }, |
1ceb70f8 | 3094 | /* REG_8F */ |
4e7d34a6 | 3095 | { |
bf890a93 | 3096 | { "popU", { stackEv }, 0 }, |
c48244a5 | 3097 | { XOP_8F_TABLE (XOP_09) }, |
592d1631 L |
3098 | { Bad_Opcode }, |
3099 | { Bad_Opcode }, | |
3100 | { Bad_Opcode }, | |
f88c9eb0 | 3101 | { XOP_8F_TABLE (XOP_09) }, |
4e7d34a6 | 3102 | }, |
1ceb70f8 | 3103 | /* REG_C0 */ |
252b5132 | 3104 | { |
bf890a93 IT |
3105 | { "rolA", { Eb, Ib }, 0 }, |
3106 | { "rorA", { Eb, Ib }, 0 }, | |
3107 | { "rclA", { Eb, Ib }, 0 }, | |
3108 | { "rcrA", { Eb, Ib }, 0 }, | |
3109 | { "shlA", { Eb, Ib }, 0 }, | |
3110 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 3111 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 3112 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 3113 | }, |
1ceb70f8 | 3114 | /* REG_C1 */ |
252b5132 | 3115 | { |
bf890a93 IT |
3116 | { "rolQ", { Ev, Ib }, 0 }, |
3117 | { "rorQ", { Ev, Ib }, 0 }, | |
3118 | { "rclQ", { Ev, Ib }, 0 }, | |
3119 | { "rcrQ", { Ev, Ib }, 0 }, | |
3120 | { "shlQ", { Ev, Ib }, 0 }, | |
3121 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 3122 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 3123 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 3124 | }, |
1ceb70f8 | 3125 | /* REG_C6 */ |
4e7d34a6 | 3126 | { |
bf890a93 | 3127 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
3128 | { Bad_Opcode }, |
3129 | { Bad_Opcode }, | |
3130 | { Bad_Opcode }, | |
3131 | { Bad_Opcode }, | |
3132 | { Bad_Opcode }, | |
3133 | { Bad_Opcode }, | |
3134 | { MOD_TABLE (MOD_C6_REG_7) }, | |
4e7d34a6 | 3135 | }, |
1ceb70f8 | 3136 | /* REG_C7 */ |
4e7d34a6 | 3137 | { |
bf890a93 | 3138 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
3139 | { Bad_Opcode }, |
3140 | { Bad_Opcode }, | |
3141 | { Bad_Opcode }, | |
3142 | { Bad_Opcode }, | |
3143 | { Bad_Opcode }, | |
3144 | { Bad_Opcode }, | |
3145 | { MOD_TABLE (MOD_C7_REG_7) }, | |
4e7d34a6 | 3146 | }, |
1ceb70f8 | 3147 | /* REG_D0 */ |
252b5132 | 3148 | { |
bf890a93 IT |
3149 | { "rolA", { Eb, I1 }, 0 }, |
3150 | { "rorA", { Eb, I1 }, 0 }, | |
3151 | { "rclA", { Eb, I1 }, 0 }, | |
3152 | { "rcrA", { Eb, I1 }, 0 }, | |
3153 | { "shlA", { Eb, I1 }, 0 }, | |
3154 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 3155 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 3156 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 3157 | }, |
1ceb70f8 | 3158 | /* REG_D1 */ |
252b5132 | 3159 | { |
bf890a93 IT |
3160 | { "rolQ", { Ev, I1 }, 0 }, |
3161 | { "rorQ", { Ev, I1 }, 0 }, | |
3162 | { "rclQ", { Ev, I1 }, 0 }, | |
3163 | { "rcrQ", { Ev, I1 }, 0 }, | |
3164 | { "shlQ", { Ev, I1 }, 0 }, | |
3165 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 3166 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 3167 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 3168 | }, |
1ceb70f8 | 3169 | /* REG_D2 */ |
252b5132 | 3170 | { |
bf890a93 IT |
3171 | { "rolA", { Eb, CL }, 0 }, |
3172 | { "rorA", { Eb, CL }, 0 }, | |
3173 | { "rclA", { Eb, CL }, 0 }, | |
3174 | { "rcrA", { Eb, CL }, 0 }, | |
3175 | { "shlA", { Eb, CL }, 0 }, | |
3176 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 3177 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 3178 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 3179 | }, |
1ceb70f8 | 3180 | /* REG_D3 */ |
252b5132 | 3181 | { |
bf890a93 IT |
3182 | { "rolQ", { Ev, CL }, 0 }, |
3183 | { "rorQ", { Ev, CL }, 0 }, | |
3184 | { "rclQ", { Ev, CL }, 0 }, | |
3185 | { "rcrQ", { Ev, CL }, 0 }, | |
3186 | { "shlQ", { Ev, CL }, 0 }, | |
3187 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 3188 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 3189 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 3190 | }, |
1ceb70f8 | 3191 | /* REG_F6 */ |
252b5132 | 3192 | { |
bf890a93 | 3193 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 3194 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
3195 | { "notA", { Ebh1 }, 0 }, |
3196 | { "negA", { Ebh1 }, 0 }, | |
3197 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
3198 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
3199 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
3200 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 3201 | }, |
1ceb70f8 | 3202 | /* REG_F7 */ |
252b5132 | 3203 | { |
bf890a93 | 3204 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 3205 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
3206 | { "notQ", { Evh1 }, 0 }, |
3207 | { "negQ", { Evh1 }, 0 }, | |
3208 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
3209 | { "imulQ", { Ev }, 0 }, | |
3210 | { "divQ", { Ev }, 0 }, | |
3211 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 3212 | }, |
1ceb70f8 | 3213 | /* REG_FE */ |
252b5132 | 3214 | { |
bf890a93 IT |
3215 | { "incA", { Ebh1 }, 0 }, |
3216 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 3217 | }, |
1ceb70f8 | 3218 | /* REG_FF */ |
252b5132 | 3219 | { |
bf890a93 IT |
3220 | { "incQ", { Evh1 }, 0 }, |
3221 | { "decQ", { Evh1 }, 0 }, | |
9fef80d6 | 3222 | { "call{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3223 | { MOD_TABLE (MOD_FF_REG_3) }, |
9fef80d6 | 3224 | { "jmp{&|}", { NOTRACK, indirEv, BND }, 0 }, |
4a357820 | 3225 | { MOD_TABLE (MOD_FF_REG_5) }, |
bf890a93 | 3226 | { "pushU", { stackEv }, 0 }, |
592d1631 | 3227 | { Bad_Opcode }, |
252b5132 | 3228 | }, |
1ceb70f8 | 3229 | /* REG_0F00 */ |
252b5132 | 3230 | { |
bf890a93 IT |
3231 | { "sldtD", { Sv }, 0 }, |
3232 | { "strD", { Sv }, 0 }, | |
3233 | { "lldt", { Ew }, 0 }, | |
3234 | { "ltr", { Ew }, 0 }, | |
3235 | { "verr", { Ew }, 0 }, | |
3236 | { "verw", { Ew }, 0 }, | |
592d1631 L |
3237 | { Bad_Opcode }, |
3238 | { Bad_Opcode }, | |
252b5132 | 3239 | }, |
1ceb70f8 | 3240 | /* REG_0F01 */ |
252b5132 | 3241 | { |
1ceb70f8 L |
3242 | { MOD_TABLE (MOD_0F01_REG_0) }, |
3243 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
3244 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
3245 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 3246 | { "smswD", { Sv }, 0 }, |
8eab4136 | 3247 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 3248 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 3249 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 3250 | }, |
b5b1fc4f | 3251 | /* REG_0F0D */ |
252b5132 | 3252 | { |
bf890a93 IT |
3253 | { "prefetch", { Mb }, 0 }, |
3254 | { "prefetchw", { Mb }, 0 }, | |
3255 | { "prefetchwt1", { Mb }, 0 }, | |
3256 | { "prefetch", { Mb }, 0 }, | |
3257 | { "prefetch", { Mb }, 0 }, | |
3258 | { "prefetch", { Mb }, 0 }, | |
3259 | { "prefetch", { Mb }, 0 }, | |
3260 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 3261 | }, |
1ceb70f8 | 3262 | /* REG_0F18 */ |
252b5132 | 3263 | { |
1ceb70f8 L |
3264 | { MOD_TABLE (MOD_0F18_REG_0) }, |
3265 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
3266 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
3267 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
d7189fa5 RM |
3268 | { MOD_TABLE (MOD_0F18_REG_4) }, |
3269 | { MOD_TABLE (MOD_0F18_REG_5) }, | |
3270 | { MOD_TABLE (MOD_0F18_REG_6) }, | |
3271 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 3272 | }, |
f8687e93 | 3273 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
3274 | { |
3275 | { "cldemote", { Mb }, 0 }, | |
3276 | { "nopQ", { Ev }, 0 }, | |
3277 | { "nopQ", { Ev }, 0 }, | |
3278 | { "nopQ", { Ev }, 0 }, | |
3279 | { "nopQ", { Ev }, 0 }, | |
3280 | { "nopQ", { Ev }, 0 }, | |
3281 | { "nopQ", { Ev }, 0 }, | |
3282 | { "nopQ", { Ev }, 0 }, | |
3283 | }, | |
f8687e93 | 3284 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 L |
3285 | { |
3286 | { "nopQ", { Ev }, 0 }, | |
3287 | { "rdsspK", { Rdq }, PREFIX_OPCODE }, | |
3288 | { "nopQ", { Ev }, 0 }, | |
3289 | { "nopQ", { Ev }, 0 }, | |
3290 | { "nopQ", { Ev }, 0 }, | |
3291 | { "nopQ", { Ev }, 0 }, | |
3292 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 3293 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 3294 | }, |
1ceb70f8 | 3295 | /* REG_0F71 */ |
a6bd098c | 3296 | { |
592d1631 L |
3297 | { Bad_Opcode }, |
3298 | { Bad_Opcode }, | |
1ceb70f8 | 3299 | { MOD_TABLE (MOD_0F71_REG_2) }, |
592d1631 | 3300 | { Bad_Opcode }, |
1ceb70f8 | 3301 | { MOD_TABLE (MOD_0F71_REG_4) }, |
592d1631 | 3302 | { Bad_Opcode }, |
1ceb70f8 | 3303 | { MOD_TABLE (MOD_0F71_REG_6) }, |
a6bd098c | 3304 | }, |
1ceb70f8 | 3305 | /* REG_0F72 */ |
a6bd098c | 3306 | { |
592d1631 L |
3307 | { Bad_Opcode }, |
3308 | { Bad_Opcode }, | |
1ceb70f8 | 3309 | { MOD_TABLE (MOD_0F72_REG_2) }, |
592d1631 | 3310 | { Bad_Opcode }, |
1ceb70f8 | 3311 | { MOD_TABLE (MOD_0F72_REG_4) }, |
592d1631 | 3312 | { Bad_Opcode }, |
1ceb70f8 | 3313 | { MOD_TABLE (MOD_0F72_REG_6) }, |
a6bd098c | 3314 | }, |
1ceb70f8 | 3315 | /* REG_0F73 */ |
252b5132 | 3316 | { |
592d1631 L |
3317 | { Bad_Opcode }, |
3318 | { Bad_Opcode }, | |
1ceb70f8 L |
3319 | { MOD_TABLE (MOD_0F73_REG_2) }, |
3320 | { MOD_TABLE (MOD_0F73_REG_3) }, | |
592d1631 L |
3321 | { Bad_Opcode }, |
3322 | { Bad_Opcode }, | |
1ceb70f8 L |
3323 | { MOD_TABLE (MOD_0F73_REG_6) }, |
3324 | { MOD_TABLE (MOD_0F73_REG_7) }, | |
252b5132 | 3325 | }, |
1ceb70f8 | 3326 | /* REG_0FA6 */ |
252b5132 | 3327 | { |
bf890a93 IT |
3328 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
3329 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
3330 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3331 | }, |
1ceb70f8 | 3332 | /* REG_0FA7 */ |
4e7d34a6 | 3333 | { |
bf890a93 IT |
3334 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
3335 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
3336 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
3337 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
3338 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
3339 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 3340 | }, |
1ceb70f8 | 3341 | /* REG_0FAE */ |
4e7d34a6 | 3342 | { |
1ceb70f8 L |
3343 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
3344 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
3345 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
3346 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 3347 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
3348 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
3349 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
3350 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 3351 | }, |
1ceb70f8 | 3352 | /* REG_0FBA */ |
252b5132 | 3353 | { |
592d1631 L |
3354 | { Bad_Opcode }, |
3355 | { Bad_Opcode }, | |
3356 | { Bad_Opcode }, | |
3357 | { Bad_Opcode }, | |
bf890a93 IT |
3358 | { "btQ", { Ev, Ib }, 0 }, |
3359 | { "btsQ", { Evh1, Ib }, 0 }, | |
3360 | { "btrQ", { Evh1, Ib }, 0 }, | |
3361 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 3362 | }, |
1ceb70f8 | 3363 | /* REG_0FC7 */ |
c608c12e | 3364 | { |
592d1631 | 3365 | { Bad_Opcode }, |
bf890a93 | 3366 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 3367 | { Bad_Opcode }, |
963f3586 IT |
3368 | { MOD_TABLE (MOD_0FC7_REG_3) }, |
3369 | { MOD_TABLE (MOD_0FC7_REG_4) }, | |
3370 | { MOD_TABLE (MOD_0FC7_REG_5) }, | |
1ceb70f8 L |
3371 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
3372 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 3373 | }, |
592a252b | 3374 | /* REG_VEX_0F71 */ |
c0f3af97 | 3375 | { |
592d1631 L |
3376 | { Bad_Opcode }, |
3377 | { Bad_Opcode }, | |
592a252b | 3378 | { MOD_TABLE (MOD_VEX_0F71_REG_2) }, |
592d1631 | 3379 | { Bad_Opcode }, |
592a252b | 3380 | { MOD_TABLE (MOD_VEX_0F71_REG_4) }, |
592d1631 | 3381 | { Bad_Opcode }, |
592a252b | 3382 | { MOD_TABLE (MOD_VEX_0F71_REG_6) }, |
c0f3af97 | 3383 | }, |
592a252b | 3384 | /* REG_VEX_0F72 */ |
c0f3af97 | 3385 | { |
592d1631 L |
3386 | { Bad_Opcode }, |
3387 | { Bad_Opcode }, | |
592a252b | 3388 | { MOD_TABLE (MOD_VEX_0F72_REG_2) }, |
592d1631 | 3389 | { Bad_Opcode }, |
592a252b | 3390 | { MOD_TABLE (MOD_VEX_0F72_REG_4) }, |
592d1631 | 3391 | { Bad_Opcode }, |
592a252b | 3392 | { MOD_TABLE (MOD_VEX_0F72_REG_6) }, |
c0f3af97 | 3393 | }, |
592a252b | 3394 | /* REG_VEX_0F73 */ |
c0f3af97 | 3395 | { |
592d1631 L |
3396 | { Bad_Opcode }, |
3397 | { Bad_Opcode }, | |
592a252b L |
3398 | { MOD_TABLE (MOD_VEX_0F73_REG_2) }, |
3399 | { MOD_TABLE (MOD_VEX_0F73_REG_3) }, | |
592d1631 L |
3400 | { Bad_Opcode }, |
3401 | { Bad_Opcode }, | |
592a252b L |
3402 | { MOD_TABLE (MOD_VEX_0F73_REG_6) }, |
3403 | { MOD_TABLE (MOD_VEX_0F73_REG_7) }, | |
c0f3af97 | 3404 | }, |
592a252b | 3405 | /* REG_VEX_0FAE */ |
c0f3af97 | 3406 | { |
592d1631 L |
3407 | { Bad_Opcode }, |
3408 | { Bad_Opcode }, | |
592a252b L |
3409 | { MOD_TABLE (MOD_VEX_0FAE_REG_2) }, |
3410 | { MOD_TABLE (MOD_VEX_0FAE_REG_3) }, | |
c0f3af97 | 3411 | }, |
f12dc422 L |
3412 | /* REG_VEX_0F38F3 */ |
3413 | { | |
3414 | { Bad_Opcode }, | |
3415 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_1) }, | |
3416 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_2) }, | |
3417 | { PREFIX_TABLE (PREFIX_VEX_0F38F3_REG_3) }, | |
3418 | }, | |
f88c9eb0 SP |
3419 | /* REG_XOP_LWPCB */ |
3420 | { | |
bf890a93 IT |
3421 | { "llwpcb", { { OP_LWPCB_E, 0 } }, 0 }, |
3422 | { "slwpcb", { { OP_LWPCB_E, 0 } }, 0 }, | |
f88c9eb0 SP |
3423 | }, |
3424 | /* REG_XOP_LWP */ | |
3425 | { | |
c1dc7af5 JB |
3426 | { "lwpins", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, |
3427 | { "lwpval", { { OP_LWP_E, 0 }, Ed, Id }, 0 }, | |
f88c9eb0 | 3428 | }, |
2a2a0f38 QN |
3429 | /* REG_XOP_TBM_01 */ |
3430 | { | |
3431 | { Bad_Opcode }, | |
c1dc7af5 JB |
3432 | { "blcfill", { { OP_LWP_E, 0 }, Edq }, 0 }, |
3433 | { "blsfill", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3434 | { "blcs", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3435 | { "tzmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3436 | { "blcic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3437 | { "blsic", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
3438 | { "t1mskc", { { OP_LWP_E, 0 }, Edq }, 0 }, | |
2a2a0f38 QN |
3439 | }, |
3440 | /* REG_XOP_TBM_02 */ | |
3441 | { | |
3442 | { Bad_Opcode }, | |
c1dc7af5 | 3443 | { "blcmsk", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 QN |
3444 | { Bad_Opcode }, |
3445 | { Bad_Opcode }, | |
3446 | { Bad_Opcode }, | |
3447 | { Bad_Opcode }, | |
c1dc7af5 | 3448 | { "blci", { { OP_LWP_E, 0 }, Edq }, 0 }, |
2a2a0f38 | 3449 | }, |
ad692897 L |
3450 | |
3451 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
3452 | }; |
3453 | ||
1ceb70f8 L |
3454 | static const struct dis386 prefix_table[][4] = { |
3455 | /* PREFIX_90 */ | |
252b5132 | 3456 | { |
bf890a93 IT |
3457 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, |
3458 | { "pause", { XX }, 0 }, | |
3459 | { "xchgS", { { NOP_Fixup1, eAX_reg }, { NOP_Fixup2, eAX_reg } }, 0 }, | |
507bd325 | 3460 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 3461 | }, |
4e7d34a6 | 3462 | |
f9630fa6 | 3463 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
3464 | { |
3465 | { "vmmcall", { Skip_MODRM }, 0 }, | |
3466 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
3467 | { Bad_Opcode }, |
3468 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
3469 | }, |
3470 | ||
f8687e93 | 3471 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
3472 | { |
3473 | { Bad_Opcode }, | |
3474 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
3475 | }, | |
3476 | ||
f8687e93 | 3477 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 3478 | { |
4b27d27c | 3479 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 3480 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 3481 | { Bad_Opcode }, |
efe30057 | 3482 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
3483 | }, |
3484 | ||
3485 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
3486 | { | |
3487 | { Bad_Opcode }, | |
3488 | { Bad_Opcode }, | |
3489 | { Bad_Opcode }, | |
3490 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
3491 | }, |
3492 | ||
f8687e93 | 3493 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
3494 | { |
3495 | { Bad_Opcode }, | |
c2f76402 | 3496 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
3497 | }, |
3498 | ||
267b8516 JB |
3499 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3500 | { | |
3501 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3502 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3503 | }, |
3504 | ||
3505 | /* PREFIX_0F01_REG_7_MOD_3_RM_3 */ | |
3506 | { | |
7abb8d81 | 3507 | { "mwaitx", { { OP_Mwait, eBX_reg } }, 0 }, |
267b8516 JB |
3508 | }, |
3509 | ||
3233d7d0 IT |
3510 | /* PREFIX_0F09 */ |
3511 | { | |
3512 | { "wbinvd", { XX }, 0 }, | |
3513 | { "wbnoinvd", { XX }, 0 }, | |
3514 | }, | |
3515 | ||
1ceb70f8 | 3516 | /* PREFIX_0F10 */ |
cc0ec051 | 3517 | { |
507bd325 L |
3518 | { "movups", { XM, EXx }, PREFIX_OPCODE }, |
3519 | { "movss", { XM, EXd }, PREFIX_OPCODE }, | |
3520 | { "movupd", { XM, EXx }, PREFIX_OPCODE }, | |
3521 | { "movsd", { XM, EXq }, PREFIX_OPCODE }, | |
30d1c836 | 3522 | }, |
4e7d34a6 | 3523 | |
1ceb70f8 | 3524 | /* PREFIX_0F11 */ |
30d1c836 | 3525 | { |
507bd325 L |
3526 | { "movups", { EXxS, XM }, PREFIX_OPCODE }, |
3527 | { "movss", { EXdS, XM }, PREFIX_OPCODE }, | |
3528 | { "movupd", { EXxS, XM }, PREFIX_OPCODE }, | |
3529 | { "movsd", { EXqS, XM }, PREFIX_OPCODE }, | |
4e7d34a6 | 3530 | }, |
252b5132 | 3531 | |
1ceb70f8 | 3532 | /* PREFIX_0F12 */ |
c608c12e | 3533 | { |
1ceb70f8 | 3534 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
507bd325 | 3535 | { "movsldup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3536 | { MOD_TABLE (MOD_0F12_PREFIX_2) }, |
507bd325 | 3537 | { "movddup", { XM, EXq }, PREFIX_OPCODE }, |
c608c12e | 3538 | }, |
4e7d34a6 | 3539 | |
1ceb70f8 | 3540 | /* PREFIX_0F16 */ |
c608c12e | 3541 | { |
1ceb70f8 | 3542 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
507bd325 | 3543 | { "movshdup", { XM, EXx }, PREFIX_OPCODE }, |
18897deb | 3544 | { MOD_TABLE (MOD_0F16_PREFIX_2) }, |
c608c12e | 3545 | }, |
4e7d34a6 | 3546 | |
7e8b059b L |
3547 | /* PREFIX_0F1A */ |
3548 | { | |
3549 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3550 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3551 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3552 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3553 | }, |
3554 | ||
3555 | /* PREFIX_0F1B */ | |
3556 | { | |
3557 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3558 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3559 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3560 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3561 | }, |
3562 | ||
c48935d7 IT |
3563 | /* PREFIX_0F1C */ |
3564 | { | |
3565 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
3566 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3567 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3568 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3569 | }, | |
3570 | ||
603555e5 L |
3571 | /* PREFIX_0F1E */ |
3572 | { | |
3573 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3574 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, | |
3575 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3576 | { "nopQ", { Ev }, PREFIX_OPCODE }, | |
3577 | }, | |
3578 | ||
1ceb70f8 | 3579 | /* PREFIX_0F2A */ |
c608c12e | 3580 | { |
507bd325 | 3581 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3582 | { "cvtsi2ss%LQ", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3583 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
e1a1babd | 3584 | { "cvtsi2sd%LQ", { XM, Edq }, 0 }, |
c608c12e | 3585 | }, |
4e7d34a6 | 3586 | |
1ceb70f8 | 3587 | /* PREFIX_0F2B */ |
c608c12e | 3588 | { |
75c135a8 L |
3589 | { MOD_TABLE (MOD_0F2B_PREFIX_0) }, |
3590 | { MOD_TABLE (MOD_0F2B_PREFIX_1) }, | |
3591 | { MOD_TABLE (MOD_0F2B_PREFIX_2) }, | |
3592 | { MOD_TABLE (MOD_0F2B_PREFIX_3) }, | |
c608c12e | 3593 | }, |
4e7d34a6 | 3594 | |
1ceb70f8 | 3595 | /* PREFIX_0F2C */ |
c608c12e | 3596 | { |
507bd325 | 3597 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3598 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3599 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3600 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3601 | }, |
4e7d34a6 | 3602 | |
1ceb70f8 | 3603 | /* PREFIX_0F2D */ |
c608c12e | 3604 | { |
507bd325 | 3605 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3606 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3607 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3608 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3609 | }, |
4e7d34a6 | 3610 | |
1ceb70f8 | 3611 | /* PREFIX_0F2E */ |
c608c12e | 3612 | { |
bf890a93 | 3613 | { "ucomiss",{ XM, EXd }, 0 }, |
592d1631 | 3614 | { Bad_Opcode }, |
bf890a93 | 3615 | { "ucomisd",{ XM, EXq }, 0 }, |
c608c12e | 3616 | }, |
4e7d34a6 | 3617 | |
1ceb70f8 | 3618 | /* PREFIX_0F2F */ |
c608c12e | 3619 | { |
bf890a93 | 3620 | { "comiss", { XM, EXd }, 0 }, |
592d1631 | 3621 | { Bad_Opcode }, |
bf890a93 | 3622 | { "comisd", { XM, EXq }, 0 }, |
c608c12e | 3623 | }, |
4e7d34a6 | 3624 | |
1ceb70f8 | 3625 | /* PREFIX_0F51 */ |
c608c12e | 3626 | { |
507bd325 L |
3627 | { "sqrtps", { XM, EXx }, PREFIX_OPCODE }, |
3628 | { "sqrtss", { XM, EXd }, PREFIX_OPCODE }, | |
3629 | { "sqrtpd", { XM, EXx }, PREFIX_OPCODE }, | |
3630 | { "sqrtsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3631 | }, |
4e7d34a6 | 3632 | |
1ceb70f8 | 3633 | /* PREFIX_0F52 */ |
c608c12e | 3634 | { |
507bd325 L |
3635 | { "rsqrtps",{ XM, EXx }, PREFIX_OPCODE }, |
3636 | { "rsqrtss",{ XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3637 | }, |
4e7d34a6 | 3638 | |
1ceb70f8 | 3639 | /* PREFIX_0F53 */ |
c608c12e | 3640 | { |
507bd325 L |
3641 | { "rcpps", { XM, EXx }, PREFIX_OPCODE }, |
3642 | { "rcpss", { XM, EXd }, PREFIX_OPCODE }, | |
c608c12e | 3643 | }, |
4e7d34a6 | 3644 | |
1ceb70f8 | 3645 | /* PREFIX_0F58 */ |
c608c12e | 3646 | { |
507bd325 L |
3647 | { "addps", { XM, EXx }, PREFIX_OPCODE }, |
3648 | { "addss", { XM, EXd }, PREFIX_OPCODE }, | |
3649 | { "addpd", { XM, EXx }, PREFIX_OPCODE }, | |
3650 | { "addsd", { XM, EXq }, PREFIX_OPCODE }, | |
c608c12e | 3651 | }, |
4e7d34a6 | 3652 | |
1ceb70f8 | 3653 | /* PREFIX_0F59 */ |
c608c12e | 3654 | { |
507bd325 L |
3655 | { "mulps", { XM, EXx }, PREFIX_OPCODE }, |
3656 | { "mulss", { XM, EXd }, PREFIX_OPCODE }, | |
3657 | { "mulpd", { XM, EXx }, PREFIX_OPCODE }, | |
3658 | { "mulsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3659 | }, |
4e7d34a6 | 3660 | |
1ceb70f8 | 3661 | /* PREFIX_0F5A */ |
041bd2e0 | 3662 | { |
507bd325 L |
3663 | { "cvtps2pd", { XM, EXq }, PREFIX_OPCODE }, |
3664 | { "cvtss2sd", { XM, EXd }, PREFIX_OPCODE }, | |
3665 | { "cvtpd2ps", { XM, EXx }, PREFIX_OPCODE }, | |
3666 | { "cvtsd2ss", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3667 | }, |
4e7d34a6 | 3668 | |
1ceb70f8 | 3669 | /* PREFIX_0F5B */ |
041bd2e0 | 3670 | { |
507bd325 L |
3671 | { "cvtdq2ps", { XM, EXx }, PREFIX_OPCODE }, |
3672 | { "cvttps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3673 | { "cvtps2dq", { XM, EXx }, PREFIX_OPCODE }, | |
041bd2e0 | 3674 | }, |
4e7d34a6 | 3675 | |
1ceb70f8 | 3676 | /* PREFIX_0F5C */ |
041bd2e0 | 3677 | { |
507bd325 L |
3678 | { "subps", { XM, EXx }, PREFIX_OPCODE }, |
3679 | { "subss", { XM, EXd }, PREFIX_OPCODE }, | |
3680 | { "subpd", { XM, EXx }, PREFIX_OPCODE }, | |
3681 | { "subsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3682 | }, |
4e7d34a6 | 3683 | |
1ceb70f8 | 3684 | /* PREFIX_0F5D */ |
041bd2e0 | 3685 | { |
507bd325 L |
3686 | { "minps", { XM, EXx }, PREFIX_OPCODE }, |
3687 | { "minss", { XM, EXd }, PREFIX_OPCODE }, | |
3688 | { "minpd", { XM, EXx }, PREFIX_OPCODE }, | |
3689 | { "minsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3690 | }, |
4e7d34a6 | 3691 | |
1ceb70f8 | 3692 | /* PREFIX_0F5E */ |
041bd2e0 | 3693 | { |
507bd325 L |
3694 | { "divps", { XM, EXx }, PREFIX_OPCODE }, |
3695 | { "divss", { XM, EXd }, PREFIX_OPCODE }, | |
3696 | { "divpd", { XM, EXx }, PREFIX_OPCODE }, | |
3697 | { "divsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3698 | }, |
4e7d34a6 | 3699 | |
1ceb70f8 | 3700 | /* PREFIX_0F5F */ |
041bd2e0 | 3701 | { |
507bd325 L |
3702 | { "maxps", { XM, EXx }, PREFIX_OPCODE }, |
3703 | { "maxss", { XM, EXd }, PREFIX_OPCODE }, | |
3704 | { "maxpd", { XM, EXx }, PREFIX_OPCODE }, | |
3705 | { "maxsd", { XM, EXq }, PREFIX_OPCODE }, | |
041bd2e0 | 3706 | }, |
4e7d34a6 | 3707 | |
1ceb70f8 | 3708 | /* PREFIX_0F60 */ |
041bd2e0 | 3709 | { |
507bd325 | 3710 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3711 | { Bad_Opcode }, |
507bd325 | 3712 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3713 | }, |
4e7d34a6 | 3714 | |
1ceb70f8 | 3715 | /* PREFIX_0F61 */ |
041bd2e0 | 3716 | { |
507bd325 | 3717 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3718 | { Bad_Opcode }, |
507bd325 | 3719 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3720 | }, |
4e7d34a6 | 3721 | |
1ceb70f8 | 3722 | /* PREFIX_0F62 */ |
041bd2e0 | 3723 | { |
507bd325 | 3724 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3725 | { Bad_Opcode }, |
507bd325 | 3726 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3727 | }, |
4e7d34a6 | 3728 | |
1ceb70f8 | 3729 | /* PREFIX_0F6C */ |
041bd2e0 | 3730 | { |
592d1631 L |
3731 | { Bad_Opcode }, |
3732 | { Bad_Opcode }, | |
507bd325 | 3733 | { "punpcklqdq", { XM, EXx }, PREFIX_OPCODE }, |
0f17484f | 3734 | }, |
4e7d34a6 | 3735 | |
1ceb70f8 | 3736 | /* PREFIX_0F6D */ |
0f17484f | 3737 | { |
592d1631 L |
3738 | { Bad_Opcode }, |
3739 | { Bad_Opcode }, | |
507bd325 | 3740 | { "punpckhqdq", { XM, EXx }, PREFIX_OPCODE }, |
041bd2e0 | 3741 | }, |
4e7d34a6 | 3742 | |
1ceb70f8 | 3743 | /* PREFIX_0F6F */ |
ca164297 | 3744 | { |
507bd325 L |
3745 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3746 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3747 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3748 | }, |
4e7d34a6 | 3749 | |
1ceb70f8 | 3750 | /* PREFIX_0F70 */ |
4e7d34a6 | 3751 | { |
507bd325 L |
3752 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3753 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3754 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3755 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3756 | }, |
3757 | ||
92fddf8e L |
3758 | /* PREFIX_0F73_REG_3 */ |
3759 | { | |
592d1631 L |
3760 | { Bad_Opcode }, |
3761 | { Bad_Opcode }, | |
bf890a93 | 3762 | { "psrldq", { XS, Ib }, 0 }, |
92fddf8e L |
3763 | }, |
3764 | ||
3765 | /* PREFIX_0F73_REG_7 */ | |
3766 | { | |
592d1631 L |
3767 | { Bad_Opcode }, |
3768 | { Bad_Opcode }, | |
bf890a93 | 3769 | { "pslldq", { XS, Ib }, 0 }, |
92fddf8e L |
3770 | }, |
3771 | ||
1ceb70f8 | 3772 | /* PREFIX_0F78 */ |
4e7d34a6 | 3773 | { |
bf890a93 | 3774 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3775 | { Bad_Opcode }, |
bf890a93 IT |
3776 | {"extrq", { XS, Ib, Ib }, 0 }, |
3777 | {"insertq", { XM, XS, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3778 | }, |
3779 | ||
1ceb70f8 | 3780 | /* PREFIX_0F79 */ |
4e7d34a6 | 3781 | { |
bf890a93 | 3782 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3783 | { Bad_Opcode }, |
bf890a93 IT |
3784 | {"extrq", { XM, XS }, 0 }, |
3785 | {"insertq", { XM, XS }, 0 }, | |
4e7d34a6 L |
3786 | }, |
3787 | ||
1ceb70f8 | 3788 | /* PREFIX_0F7C */ |
ca164297 | 3789 | { |
592d1631 L |
3790 | { Bad_Opcode }, |
3791 | { Bad_Opcode }, | |
507bd325 L |
3792 | { "haddpd", { XM, EXx }, PREFIX_OPCODE }, |
3793 | { "haddps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3794 | }, |
4e7d34a6 | 3795 | |
1ceb70f8 | 3796 | /* PREFIX_0F7D */ |
ca164297 | 3797 | { |
592d1631 L |
3798 | { Bad_Opcode }, |
3799 | { Bad_Opcode }, | |
507bd325 L |
3800 | { "hsubpd", { XM, EXx }, PREFIX_OPCODE }, |
3801 | { "hsubps", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3802 | }, |
4e7d34a6 | 3803 | |
1ceb70f8 | 3804 | /* PREFIX_0F7E */ |
ca164297 | 3805 | { |
507bd325 L |
3806 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3807 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3808 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3809 | }, |
4e7d34a6 | 3810 | |
1ceb70f8 | 3811 | /* PREFIX_0F7F */ |
ca164297 | 3812 | { |
507bd325 L |
3813 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3814 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3815 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3816 | }, |
4e7d34a6 | 3817 | |
f8687e93 | 3818 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3819 | { |
3820 | { Bad_Opcode }, | |
bf890a93 | 3821 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3822 | }, |
3823 | ||
f8687e93 | 3824 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3825 | { |
3826 | { Bad_Opcode }, | |
bf890a93 | 3827 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3828 | }, |
3829 | ||
f8687e93 | 3830 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3831 | { |
3832 | { Bad_Opcode }, | |
bf890a93 | 3833 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3834 | }, |
3835 | ||
f8687e93 | 3836 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3837 | { |
3838 | { Bad_Opcode }, | |
bf890a93 | 3839 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3840 | }, |
3841 | ||
f8687e93 | 3842 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3843 | { |
3844 | { "xsave", { FXSAVE }, 0 }, | |
3845 | { "ptwrite%LQ", { Edq }, 0 }, | |
3846 | }, | |
3847 | ||
f8687e93 | 3848 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3849 | { |
3850 | { Bad_Opcode }, | |
3851 | { "ptwrite%LQ", { Edq }, 0 }, | |
3852 | }, | |
3853 | ||
f8687e93 | 3854 | /* PREFIX_0FAE_REG_5_MOD_0 */ |
603555e5 L |
3855 | { |
3856 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, | |
2234eee6 L |
3857 | }, |
3858 | ||
f8687e93 | 3859 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3860 | { |
3861 | { "lfence", { Skip_MODRM }, 0 }, | |
3862 | { "incsspK", { Rdq }, PREFIX_OPCODE }, | |
603555e5 L |
3863 | }, |
3864 | ||
f8687e93 | 3865 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3866 | { |
603555e5 L |
3867 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3868 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3869 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3870 | }, |
3871 | ||
f8687e93 | 3872 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3873 | { |
f8687e93 | 3874 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3875 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3876 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3877 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3878 | }, |
3879 | ||
f8687e93 | 3880 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3881 | { |
bf890a93 | 3882 | { "clflush", { Mb }, 0 }, |
963f3586 | 3883 | { Bad_Opcode }, |
bf890a93 | 3884 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3885 | }, |
3886 | ||
1ceb70f8 | 3887 | /* PREFIX_0FB8 */ |
ca164297 | 3888 | { |
592d1631 | 3889 | { Bad_Opcode }, |
bf890a93 | 3890 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3891 | }, |
4e7d34a6 | 3892 | |
f12dc422 L |
3893 | /* PREFIX_0FBC */ |
3894 | { | |
bf890a93 IT |
3895 | { "bsfS", { Gv, Ev }, 0 }, |
3896 | { "tzcntS", { Gv, Ev }, 0 }, | |
3897 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3898 | }, |
3899 | ||
1ceb70f8 | 3900 | /* PREFIX_0FBD */ |
050dfa73 | 3901 | { |
bf890a93 IT |
3902 | { "bsrS", { Gv, Ev }, 0 }, |
3903 | { "lzcntS", { Gv, Ev }, 0 }, | |
3904 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3905 | }, |
3906 | ||
1ceb70f8 | 3907 | /* PREFIX_0FC2 */ |
050dfa73 | 3908 | { |
507bd325 L |
3909 | { "cmpps", { XM, EXx, CMP }, PREFIX_OPCODE }, |
3910 | { "cmpss", { XM, EXd, CMP }, PREFIX_OPCODE }, | |
3911 | { "cmppd", { XM, EXx, CMP }, PREFIX_OPCODE }, | |
3912 | { "cmpsd", { XM, EXq, CMP }, PREFIX_OPCODE }, | |
050dfa73 | 3913 | }, |
246c51aa | 3914 | |
f8687e93 | 3915 | /* PREFIX_0FC3_MOD_0 */ |
4ee52178 | 3916 | { |
e1a1babd | 3917 | { "movntiS", { Edq, Gdq }, PREFIX_OPCODE }, |
4ee52178 L |
3918 | }, |
3919 | ||
f8687e93 | 3920 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3921 | { |
bf890a93 IT |
3922 | { "vmptrld",{ Mq }, 0 }, |
3923 | { "vmxon", { Mq }, 0 }, | |
3924 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3925 | }, |
3926 | ||
f8687e93 | 3927 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3928 | { |
3929 | { "rdrand", { Ev }, 0 }, | |
3930 | { Bad_Opcode }, | |
3931 | { "rdrand", { Ev }, 0 } | |
3932 | }, | |
3933 | ||
f8687e93 | 3934 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3935 | { |
3936 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3937 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3938 | { "rdseed", { Ev }, 0 }, |
3939 | }, | |
3940 | ||
1ceb70f8 | 3941 | /* PREFIX_0FD0 */ |
050dfa73 | 3942 | { |
592d1631 L |
3943 | { Bad_Opcode }, |
3944 | { Bad_Opcode }, | |
bf890a93 IT |
3945 | { "addsubpd", { XM, EXx }, 0 }, |
3946 | { "addsubps", { XM, EXx }, 0 }, | |
246c51aa | 3947 | }, |
050dfa73 | 3948 | |
1ceb70f8 | 3949 | /* PREFIX_0FD6 */ |
050dfa73 | 3950 | { |
592d1631 | 3951 | { Bad_Opcode }, |
bf890a93 IT |
3952 | { "movq2dq",{ XM, MS }, 0 }, |
3953 | { "movq", { EXqS, XM }, 0 }, | |
3954 | { "movdq2q",{ MX, XS }, 0 }, | |
050dfa73 MM |
3955 | }, |
3956 | ||
1ceb70f8 | 3957 | /* PREFIX_0FE6 */ |
7918206c | 3958 | { |
592d1631 | 3959 | { Bad_Opcode }, |
507bd325 L |
3960 | { "cvtdq2pd", { XM, EXq }, PREFIX_OPCODE }, |
3961 | { "cvttpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
3962 | { "cvtpd2dq", { XM, EXx }, PREFIX_OPCODE }, | |
7918206c | 3963 | }, |
8b38ad71 | 3964 | |
1ceb70f8 | 3965 | /* PREFIX_0FE7 */ |
8b38ad71 | 3966 | { |
507bd325 | 3967 | { "movntq", { Mq, MX }, PREFIX_OPCODE }, |
592d1631 | 3968 | { Bad_Opcode }, |
75c135a8 | 3969 | { MOD_TABLE (MOD_0FE7_PREFIX_2) }, |
4e7d34a6 L |
3970 | }, |
3971 | ||
1ceb70f8 | 3972 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3973 | { |
592d1631 L |
3974 | { Bad_Opcode }, |
3975 | { Bad_Opcode }, | |
3976 | { Bad_Opcode }, | |
1ceb70f8 | 3977 | { MOD_TABLE (MOD_0FF0_PREFIX_3) }, |
4e7d34a6 L |
3978 | }, |
3979 | ||
1ceb70f8 | 3980 | /* PREFIX_0FF7 */ |
4e7d34a6 | 3981 | { |
507bd325 | 3982 | { "maskmovq", { MX, MS }, PREFIX_OPCODE }, |
592d1631 | 3983 | { Bad_Opcode }, |
507bd325 | 3984 | { "maskmovdqu", { XM, XS }, PREFIX_OPCODE }, |
8b38ad71 | 3985 | }, |
42903f7f | 3986 | |
1ceb70f8 | 3987 | /* PREFIX_0F3810 */ |
42903f7f | 3988 | { |
592d1631 L |
3989 | { Bad_Opcode }, |
3990 | { Bad_Opcode }, | |
507bd325 | 3991 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
3992 | }, |
3993 | ||
1ceb70f8 | 3994 | /* PREFIX_0F3814 */ |
42903f7f | 3995 | { |
592d1631 L |
3996 | { Bad_Opcode }, |
3997 | { Bad_Opcode }, | |
507bd325 | 3998 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
3999 | }, |
4000 | ||
1ceb70f8 | 4001 | /* PREFIX_0F3815 */ |
42903f7f | 4002 | { |
592d1631 L |
4003 | { Bad_Opcode }, |
4004 | { Bad_Opcode }, | |
507bd325 | 4005 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_OPCODE }, |
42903f7f L |
4006 | }, |
4007 | ||
1ceb70f8 | 4008 | /* PREFIX_0F3817 */ |
42903f7f | 4009 | { |
592d1631 L |
4010 | { Bad_Opcode }, |
4011 | { Bad_Opcode }, | |
507bd325 | 4012 | { "ptest", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4013 | }, |
4014 | ||
1ceb70f8 | 4015 | /* PREFIX_0F3820 */ |
42903f7f | 4016 | { |
592d1631 L |
4017 | { Bad_Opcode }, |
4018 | { Bad_Opcode }, | |
507bd325 | 4019 | { "pmovsxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4020 | }, |
4021 | ||
1ceb70f8 | 4022 | /* PREFIX_0F3821 */ |
42903f7f | 4023 | { |
592d1631 L |
4024 | { Bad_Opcode }, |
4025 | { Bad_Opcode }, | |
507bd325 | 4026 | { "pmovsxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4027 | }, |
4028 | ||
1ceb70f8 | 4029 | /* PREFIX_0F3822 */ |
42903f7f | 4030 | { |
592d1631 L |
4031 | { Bad_Opcode }, |
4032 | { Bad_Opcode }, | |
507bd325 | 4033 | { "pmovsxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4034 | }, |
4035 | ||
1ceb70f8 | 4036 | /* PREFIX_0F3823 */ |
42903f7f | 4037 | { |
592d1631 L |
4038 | { Bad_Opcode }, |
4039 | { Bad_Opcode }, | |
507bd325 | 4040 | { "pmovsxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4041 | }, |
4042 | ||
1ceb70f8 | 4043 | /* PREFIX_0F3824 */ |
42903f7f | 4044 | { |
592d1631 L |
4045 | { Bad_Opcode }, |
4046 | { Bad_Opcode }, | |
507bd325 | 4047 | { "pmovsxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4048 | }, |
4049 | ||
1ceb70f8 | 4050 | /* PREFIX_0F3825 */ |
42903f7f | 4051 | { |
592d1631 L |
4052 | { Bad_Opcode }, |
4053 | { Bad_Opcode }, | |
507bd325 | 4054 | { "pmovsxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4055 | }, |
4056 | ||
1ceb70f8 | 4057 | /* PREFIX_0F3828 */ |
42903f7f | 4058 | { |
592d1631 L |
4059 | { Bad_Opcode }, |
4060 | { Bad_Opcode }, | |
507bd325 | 4061 | { "pmuldq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4062 | }, |
4063 | ||
1ceb70f8 | 4064 | /* PREFIX_0F3829 */ |
42903f7f | 4065 | { |
592d1631 L |
4066 | { Bad_Opcode }, |
4067 | { Bad_Opcode }, | |
507bd325 | 4068 | { "pcmpeqq", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4069 | }, |
4070 | ||
1ceb70f8 | 4071 | /* PREFIX_0F382A */ |
42903f7f | 4072 | { |
592d1631 L |
4073 | { Bad_Opcode }, |
4074 | { Bad_Opcode }, | |
75c135a8 | 4075 | { MOD_TABLE (MOD_0F382A_PREFIX_2) }, |
42903f7f L |
4076 | }, |
4077 | ||
1ceb70f8 | 4078 | /* PREFIX_0F382B */ |
42903f7f | 4079 | { |
592d1631 L |
4080 | { Bad_Opcode }, |
4081 | { Bad_Opcode }, | |
507bd325 | 4082 | { "packusdw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4083 | }, |
4084 | ||
1ceb70f8 | 4085 | /* PREFIX_0F3830 */ |
42903f7f | 4086 | { |
592d1631 L |
4087 | { Bad_Opcode }, |
4088 | { Bad_Opcode }, | |
507bd325 | 4089 | { "pmovzxbw", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4090 | }, |
4091 | ||
1ceb70f8 | 4092 | /* PREFIX_0F3831 */ |
42903f7f | 4093 | { |
592d1631 L |
4094 | { Bad_Opcode }, |
4095 | { Bad_Opcode }, | |
507bd325 | 4096 | { "pmovzxbd", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4097 | }, |
4098 | ||
1ceb70f8 | 4099 | /* PREFIX_0F3832 */ |
42903f7f | 4100 | { |
592d1631 L |
4101 | { Bad_Opcode }, |
4102 | { Bad_Opcode }, | |
507bd325 | 4103 | { "pmovzxbq", { XM, EXw }, PREFIX_OPCODE }, |
42903f7f L |
4104 | }, |
4105 | ||
1ceb70f8 | 4106 | /* PREFIX_0F3833 */ |
42903f7f | 4107 | { |
592d1631 L |
4108 | { Bad_Opcode }, |
4109 | { Bad_Opcode }, | |
507bd325 | 4110 | { "pmovzxwd", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4111 | }, |
4112 | ||
1ceb70f8 | 4113 | /* PREFIX_0F3834 */ |
42903f7f | 4114 | { |
592d1631 L |
4115 | { Bad_Opcode }, |
4116 | { Bad_Opcode }, | |
507bd325 | 4117 | { "pmovzxwq", { XM, EXd }, PREFIX_OPCODE }, |
42903f7f L |
4118 | }, |
4119 | ||
1ceb70f8 | 4120 | /* PREFIX_0F3835 */ |
42903f7f | 4121 | { |
592d1631 L |
4122 | { Bad_Opcode }, |
4123 | { Bad_Opcode }, | |
507bd325 | 4124 | { "pmovzxdq", { XM, EXq }, PREFIX_OPCODE }, |
42903f7f L |
4125 | }, |
4126 | ||
1ceb70f8 | 4127 | /* PREFIX_0F3837 */ |
4e7d34a6 | 4128 | { |
592d1631 L |
4129 | { Bad_Opcode }, |
4130 | { Bad_Opcode }, | |
507bd325 | 4131 | { "pcmpgtq", { XM, EXx }, PREFIX_OPCODE }, |
4e7d34a6 L |
4132 | }, |
4133 | ||
1ceb70f8 | 4134 | /* PREFIX_0F3838 */ |
42903f7f | 4135 | { |
592d1631 L |
4136 | { Bad_Opcode }, |
4137 | { Bad_Opcode }, | |
507bd325 | 4138 | { "pminsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4139 | }, |
4140 | ||
1ceb70f8 | 4141 | /* PREFIX_0F3839 */ |
42903f7f | 4142 | { |
592d1631 L |
4143 | { Bad_Opcode }, |
4144 | { Bad_Opcode }, | |
507bd325 | 4145 | { "pminsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4146 | }, |
4147 | ||
1ceb70f8 | 4148 | /* PREFIX_0F383A */ |
42903f7f | 4149 | { |
592d1631 L |
4150 | { Bad_Opcode }, |
4151 | { Bad_Opcode }, | |
507bd325 | 4152 | { "pminuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4153 | }, |
4154 | ||
1ceb70f8 | 4155 | /* PREFIX_0F383B */ |
42903f7f | 4156 | { |
592d1631 L |
4157 | { Bad_Opcode }, |
4158 | { Bad_Opcode }, | |
507bd325 | 4159 | { "pminud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4160 | }, |
4161 | ||
1ceb70f8 | 4162 | /* PREFIX_0F383C */ |
42903f7f | 4163 | { |
592d1631 L |
4164 | { Bad_Opcode }, |
4165 | { Bad_Opcode }, | |
507bd325 | 4166 | { "pmaxsb", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4167 | }, |
4168 | ||
1ceb70f8 | 4169 | /* PREFIX_0F383D */ |
42903f7f | 4170 | { |
592d1631 L |
4171 | { Bad_Opcode }, |
4172 | { Bad_Opcode }, | |
507bd325 | 4173 | { "pmaxsd", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4174 | }, |
4175 | ||
1ceb70f8 | 4176 | /* PREFIX_0F383E */ |
42903f7f | 4177 | { |
592d1631 L |
4178 | { Bad_Opcode }, |
4179 | { Bad_Opcode }, | |
507bd325 | 4180 | { "pmaxuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4181 | }, |
4182 | ||
1ceb70f8 | 4183 | /* PREFIX_0F383F */ |
42903f7f | 4184 | { |
592d1631 L |
4185 | { Bad_Opcode }, |
4186 | { Bad_Opcode }, | |
507bd325 | 4187 | { "pmaxud", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4188 | }, |
4189 | ||
1ceb70f8 | 4190 | /* PREFIX_0F3840 */ |
42903f7f | 4191 | { |
592d1631 L |
4192 | { Bad_Opcode }, |
4193 | { Bad_Opcode }, | |
507bd325 | 4194 | { "pmulld", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4195 | }, |
4196 | ||
1ceb70f8 | 4197 | /* PREFIX_0F3841 */ |
42903f7f | 4198 | { |
592d1631 L |
4199 | { Bad_Opcode }, |
4200 | { Bad_Opcode }, | |
507bd325 | 4201 | { "phminposuw", { XM, EXx }, PREFIX_OPCODE }, |
42903f7f L |
4202 | }, |
4203 | ||
f1f8f695 L |
4204 | /* PREFIX_0F3880 */ |
4205 | { | |
592d1631 L |
4206 | { Bad_Opcode }, |
4207 | { Bad_Opcode }, | |
507bd325 | 4208 | { "invept", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4209 | }, |
4210 | ||
4211 | /* PREFIX_0F3881 */ | |
4212 | { | |
592d1631 L |
4213 | { Bad_Opcode }, |
4214 | { Bad_Opcode }, | |
507bd325 | 4215 | { "invvpid", { Gm, Mo }, PREFIX_OPCODE }, |
f1f8f695 L |
4216 | }, |
4217 | ||
6c30d220 L |
4218 | /* PREFIX_0F3882 */ |
4219 | { | |
4220 | { Bad_Opcode }, | |
4221 | { Bad_Opcode }, | |
507bd325 | 4222 | { "invpcid", { Gm, M }, PREFIX_OPCODE }, |
6c30d220 L |
4223 | }, |
4224 | ||
a0046408 L |
4225 | /* PREFIX_0F38C8 */ |
4226 | { | |
507bd325 | 4227 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4228 | }, |
4229 | ||
4230 | /* PREFIX_0F38C9 */ | |
4231 | { | |
507bd325 | 4232 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4233 | }, |
4234 | ||
4235 | /* PREFIX_0F38CA */ | |
4236 | { | |
507bd325 | 4237 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4238 | }, |
4239 | ||
4240 | /* PREFIX_0F38CB */ | |
4241 | { | |
507bd325 | 4242 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, |
a0046408 L |
4243 | }, |
4244 | ||
4245 | /* PREFIX_0F38CC */ | |
4246 | { | |
507bd325 | 4247 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4248 | }, |
4249 | ||
4250 | /* PREFIX_0F38CD */ | |
4251 | { | |
507bd325 | 4252 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, |
a0046408 L |
4253 | }, |
4254 | ||
48521003 IT |
4255 | /* PREFIX_0F38CF */ |
4256 | { | |
4257 | { Bad_Opcode }, | |
4258 | { Bad_Opcode }, | |
4259 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_OPCODE }, | |
4260 | }, | |
4261 | ||
c0f3af97 L |
4262 | /* PREFIX_0F38DB */ |
4263 | { | |
592d1631 L |
4264 | { Bad_Opcode }, |
4265 | { Bad_Opcode }, | |
507bd325 | 4266 | { "aesimc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4267 | }, |
4268 | ||
4269 | /* PREFIX_0F38DC */ | |
4270 | { | |
592d1631 L |
4271 | { Bad_Opcode }, |
4272 | { Bad_Opcode }, | |
507bd325 | 4273 | { "aesenc", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4274 | }, |
4275 | ||
4276 | /* PREFIX_0F38DD */ | |
4277 | { | |
592d1631 L |
4278 | { Bad_Opcode }, |
4279 | { Bad_Opcode }, | |
507bd325 | 4280 | { "aesenclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4281 | }, |
4282 | ||
4283 | /* PREFIX_0F38DE */ | |
4284 | { | |
592d1631 L |
4285 | { Bad_Opcode }, |
4286 | { Bad_Opcode }, | |
507bd325 | 4287 | { "aesdec", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4288 | }, |
4289 | ||
4290 | /* PREFIX_0F38DF */ | |
4291 | { | |
592d1631 L |
4292 | { Bad_Opcode }, |
4293 | { Bad_Opcode }, | |
507bd325 | 4294 | { "aesdeclast", { XM, EXx }, PREFIX_OPCODE }, |
c0f3af97 L |
4295 | }, |
4296 | ||
1ceb70f8 | 4297 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 4298 | { |
507bd325 | 4299 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
592d1631 | 4300 | { Bad_Opcode }, |
507bd325 L |
4301 | { "movbeS", { Gv, { MOVBE_Fixup, v_mode } }, PREFIX_OPCODE }, |
4302 | { "crc32", { Gdq, { CRC32_Fixup, b_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4303 | }, |
4304 | ||
1ceb70f8 | 4305 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 4306 | { |
507bd325 | 4307 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
592d1631 | 4308 | { Bad_Opcode }, |
507bd325 L |
4309 | { "movbeS", { { MOVBE_Fixup, v_mode }, Gv }, PREFIX_OPCODE }, |
4310 | { "crc32", { Gdq, { CRC32_Fixup, v_mode } }, PREFIX_OPCODE }, | |
4e7d34a6 L |
4311 | }, |
4312 | ||
603555e5 | 4313 | /* PREFIX_0F38F5 */ |
e2e1fcde L |
4314 | { |
4315 | { Bad_Opcode }, | |
603555e5 L |
4316 | { Bad_Opcode }, |
4317 | { MOD_TABLE (MOD_0F38F5_PREFIX_2) }, | |
4318 | }, | |
4319 | ||
4320 | /* PREFIX_0F38F6 */ | |
4321 | { | |
4322 | { MOD_TABLE (MOD_0F38F6_PREFIX_0) }, | |
507bd325 L |
4323 | { "adoxS", { Gdq, Edq}, PREFIX_OPCODE }, |
4324 | { "adcxS", { Gdq, Edq}, PREFIX_OPCODE }, | |
e2e1fcde L |
4325 | { Bad_Opcode }, |
4326 | }, | |
4327 | ||
c0a30a9f L |
4328 | /* PREFIX_0F38F8 */ |
4329 | { | |
4330 | { Bad_Opcode }, | |
5d79adc4 | 4331 | { MOD_TABLE (MOD_0F38F8_PREFIX_1) }, |
c0a30a9f | 4332 | { MOD_TABLE (MOD_0F38F8_PREFIX_2) }, |
5d79adc4 | 4333 | { MOD_TABLE (MOD_0F38F8_PREFIX_3) }, |
c0a30a9f L |
4334 | }, |
4335 | ||
4336 | /* PREFIX_0F38F9 */ | |
4337 | { | |
4338 | { MOD_TABLE (MOD_0F38F9_PREFIX_0) }, | |
4339 | }, | |
4340 | ||
1ceb70f8 | 4341 | /* PREFIX_0F3A08 */ |
42903f7f | 4342 | { |
592d1631 L |
4343 | { Bad_Opcode }, |
4344 | { Bad_Opcode }, | |
507bd325 | 4345 | { "roundps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4346 | }, |
4347 | ||
1ceb70f8 | 4348 | /* PREFIX_0F3A09 */ |
42903f7f | 4349 | { |
592d1631 L |
4350 | { Bad_Opcode }, |
4351 | { Bad_Opcode }, | |
507bd325 | 4352 | { "roundpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4353 | }, |
4354 | ||
1ceb70f8 | 4355 | /* PREFIX_0F3A0A */ |
42903f7f | 4356 | { |
592d1631 L |
4357 | { Bad_Opcode }, |
4358 | { Bad_Opcode }, | |
507bd325 | 4359 | { "roundss", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4360 | }, |
4361 | ||
1ceb70f8 | 4362 | /* PREFIX_0F3A0B */ |
42903f7f | 4363 | { |
592d1631 L |
4364 | { Bad_Opcode }, |
4365 | { Bad_Opcode }, | |
507bd325 | 4366 | { "roundsd", { XM, EXq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4367 | }, |
4368 | ||
1ceb70f8 | 4369 | /* PREFIX_0F3A0C */ |
42903f7f | 4370 | { |
592d1631 L |
4371 | { Bad_Opcode }, |
4372 | { Bad_Opcode }, | |
507bd325 | 4373 | { "blendps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4374 | }, |
4375 | ||
1ceb70f8 | 4376 | /* PREFIX_0F3A0D */ |
42903f7f | 4377 | { |
592d1631 L |
4378 | { Bad_Opcode }, |
4379 | { Bad_Opcode }, | |
507bd325 | 4380 | { "blendpd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4381 | }, |
4382 | ||
1ceb70f8 | 4383 | /* PREFIX_0F3A0E */ |
42903f7f | 4384 | { |
592d1631 L |
4385 | { Bad_Opcode }, |
4386 | { Bad_Opcode }, | |
507bd325 | 4387 | { "pblendw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4388 | }, |
4389 | ||
1ceb70f8 | 4390 | /* PREFIX_0F3A14 */ |
42903f7f | 4391 | { |
592d1631 L |
4392 | { Bad_Opcode }, |
4393 | { Bad_Opcode }, | |
507bd325 | 4394 | { "pextrb", { Edqb, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4395 | }, |
4396 | ||
1ceb70f8 | 4397 | /* PREFIX_0F3A15 */ |
42903f7f | 4398 | { |
592d1631 L |
4399 | { Bad_Opcode }, |
4400 | { Bad_Opcode }, | |
507bd325 | 4401 | { "pextrw", { Edqw, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4402 | }, |
4403 | ||
1ceb70f8 | 4404 | /* PREFIX_0F3A16 */ |
42903f7f | 4405 | { |
592d1631 L |
4406 | { Bad_Opcode }, |
4407 | { Bad_Opcode }, | |
507bd325 | 4408 | { "pextrK", { Edq, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4409 | }, |
4410 | ||
1ceb70f8 | 4411 | /* PREFIX_0F3A17 */ |
42903f7f | 4412 | { |
592d1631 L |
4413 | { Bad_Opcode }, |
4414 | { Bad_Opcode }, | |
507bd325 | 4415 | { "extractps", { Edqd, XM, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4416 | }, |
4417 | ||
1ceb70f8 | 4418 | /* PREFIX_0F3A20 */ |
42903f7f | 4419 | { |
592d1631 L |
4420 | { Bad_Opcode }, |
4421 | { Bad_Opcode }, | |
507bd325 | 4422 | { "pinsrb", { XM, Edqb, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4423 | }, |
4424 | ||
1ceb70f8 | 4425 | /* PREFIX_0F3A21 */ |
42903f7f | 4426 | { |
592d1631 L |
4427 | { Bad_Opcode }, |
4428 | { Bad_Opcode }, | |
507bd325 | 4429 | { "insertps", { XM, EXd, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4430 | }, |
4431 | ||
1ceb70f8 | 4432 | /* PREFIX_0F3A22 */ |
42903f7f | 4433 | { |
592d1631 L |
4434 | { Bad_Opcode }, |
4435 | { Bad_Opcode }, | |
507bd325 | 4436 | { "pinsrK", { XM, Edq, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4437 | }, |
4438 | ||
1ceb70f8 | 4439 | /* PREFIX_0F3A40 */ |
42903f7f | 4440 | { |
592d1631 L |
4441 | { Bad_Opcode }, |
4442 | { Bad_Opcode }, | |
507bd325 | 4443 | { "dpps", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4444 | }, |
4445 | ||
1ceb70f8 | 4446 | /* PREFIX_0F3A41 */ |
42903f7f | 4447 | { |
592d1631 L |
4448 | { Bad_Opcode }, |
4449 | { Bad_Opcode }, | |
507bd325 | 4450 | { "dppd", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f L |
4451 | }, |
4452 | ||
1ceb70f8 | 4453 | /* PREFIX_0F3A42 */ |
42903f7f | 4454 | { |
592d1631 L |
4455 | { Bad_Opcode }, |
4456 | { Bad_Opcode }, | |
507bd325 | 4457 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_OPCODE }, |
42903f7f | 4458 | }, |
381d071f | 4459 | |
c0f3af97 L |
4460 | /* PREFIX_0F3A44 */ |
4461 | { | |
592d1631 L |
4462 | { Bad_Opcode }, |
4463 | { Bad_Opcode }, | |
507bd325 | 4464 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_OPCODE }, |
c0f3af97 L |
4465 | }, |
4466 | ||
1ceb70f8 | 4467 | /* PREFIX_0F3A60 */ |
381d071f | 4468 | { |
592d1631 L |
4469 | { Bad_Opcode }, |
4470 | { Bad_Opcode }, | |
15c7c1d8 | 4471 | { "pcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4472 | }, |
4473 | ||
1ceb70f8 | 4474 | /* PREFIX_0F3A61 */ |
381d071f | 4475 | { |
592d1631 L |
4476 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, | |
15c7c1d8 | 4478 | { "pcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, PREFIX_OPCODE }, |
381d071f L |
4479 | }, |
4480 | ||
1ceb70f8 | 4481 | /* PREFIX_0F3A62 */ |
381d071f | 4482 | { |
592d1631 L |
4483 | { Bad_Opcode }, |
4484 | { Bad_Opcode }, | |
507bd325 | 4485 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f L |
4486 | }, |
4487 | ||
1ceb70f8 | 4488 | /* PREFIX_0F3A63 */ |
381d071f | 4489 | { |
592d1631 L |
4490 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, | |
507bd325 | 4492 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_OPCODE }, |
381d071f | 4493 | }, |
09a2c6cf | 4494 | |
a0046408 L |
4495 | /* PREFIX_0F3ACC */ |
4496 | { | |
507bd325 | 4497 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
a0046408 L |
4498 | }, |
4499 | ||
48521003 IT |
4500 | /* PREFIX_0F3ACE */ |
4501 | { | |
4502 | { Bad_Opcode }, | |
4503 | { Bad_Opcode }, | |
4504 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4505 | }, | |
4506 | ||
4507 | /* PREFIX_0F3ACF */ | |
4508 | { | |
4509 | { Bad_Opcode }, | |
4510 | { Bad_Opcode }, | |
4511 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_OPCODE }, | |
4512 | }, | |
4513 | ||
c0f3af97 | 4514 | /* PREFIX_0F3ADF */ |
09a2c6cf | 4515 | { |
592d1631 L |
4516 | { Bad_Opcode }, |
4517 | { Bad_Opcode }, | |
507bd325 | 4518 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_OPCODE }, |
09a2c6cf L |
4519 | }, |
4520 | ||
592a252b | 4521 | /* PREFIX_VEX_0F10 */ |
09a2c6cf | 4522 | { |
ec6f095a | 4523 | { "vmovups", { XM, EXx }, 0 }, |
5b872f7d | 4524 | { "vmovss", { XMVexScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4525 | { "vmovupd", { XM, EXx }, 0 }, |
5b872f7d | 4526 | { "vmovsd", { XMVexScalar, VexScalar, EXxmm_mq }, 0 }, |
09a2c6cf L |
4527 | }, |
4528 | ||
592a252b | 4529 | /* PREFIX_VEX_0F11 */ |
09a2c6cf | 4530 | { |
ec6f095a L |
4531 | { "vmovups", { EXxS, XM }, 0 }, |
4532 | { "vmovss", { EXdVexScalarS, VexScalar, XMScalar }, 0 }, | |
4533 | { "vmovupd", { EXxS, XM }, 0 }, | |
4534 | { "vmovsd", { EXqVexScalarS, VexScalar, XMScalar }, 0 }, | |
09a2c6cf L |
4535 | }, |
4536 | ||
592a252b | 4537 | /* PREFIX_VEX_0F12 */ |
09a2c6cf | 4538 | { |
592a252b | 4539 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_0) }, |
ec6f095a | 4540 | { "vmovsldup", { XM, EXx }, 0 }, |
18897deb | 4541 | { MOD_TABLE (MOD_VEX_0F12_PREFIX_2) }, |
ec6f095a | 4542 | { "vmovddup", { XM, EXymmq }, 0 }, |
09a2c6cf L |
4543 | }, |
4544 | ||
592a252b | 4545 | /* PREFIX_VEX_0F16 */ |
09a2c6cf | 4546 | { |
592a252b | 4547 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_0) }, |
ec6f095a | 4548 | { "vmovshdup", { XM, EXx }, 0 }, |
18897deb | 4549 | { MOD_TABLE (MOD_VEX_0F16_PREFIX_2) }, |
5f754f58 | 4550 | }, |
7c52e0e8 | 4551 | |
592a252b | 4552 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 4553 | { |
592d1631 | 4554 | { Bad_Opcode }, |
2b7bcc87 | 4555 | { "vcvtsi2ss%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
592d1631 | 4556 | { Bad_Opcode }, |
2b7bcc87 | 4557 | { "vcvtsi2sd%LQ", { XMScalar, VexScalar, Edq }, 0 }, |
5f754f58 | 4558 | }, |
7c52e0e8 | 4559 | |
592a252b | 4560 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 4561 | { |
592d1631 | 4562 | { Bad_Opcode }, |
5b872f7d | 4563 | { "vcvttss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4564 | { Bad_Opcode }, |
5b872f7d | 4565 | { "vcvttsd2si", { Gdq, EXxmm_mq }, 0 }, |
5f754f58 | 4566 | }, |
7c52e0e8 | 4567 | |
592a252b | 4568 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 4569 | { |
592d1631 | 4570 | { Bad_Opcode }, |
5b872f7d | 4571 | { "vcvtss2si", { Gdq, EXxmm_md }, 0 }, |
592d1631 | 4572 | { Bad_Opcode }, |
5b872f7d | 4573 | { "vcvtsd2si", { Gdq, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4574 | }, |
4575 | ||
592a252b | 4576 | /* PREFIX_VEX_0F2E */ |
7c52e0e8 | 4577 | { |
5b872f7d | 4578 | { "vucomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4579 | { Bad_Opcode }, |
5b872f7d | 4580 | { "vucomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4581 | }, |
4582 | ||
592a252b | 4583 | /* PREFIX_VEX_0F2F */ |
7c52e0e8 | 4584 | { |
5b872f7d | 4585 | { "vcomiss", { XMScalar, EXxmm_md }, 0 }, |
592d1631 | 4586 | { Bad_Opcode }, |
5b872f7d | 4587 | { "vcomisd", { XMScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4588 | }, |
4589 | ||
43234a1e L |
4590 | /* PREFIX_VEX_0F41 */ |
4591 | { | |
4592 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_0) }, | |
1ba585e8 IT |
4593 | { Bad_Opcode }, |
4594 | { VEX_LEN_TABLE (VEX_LEN_0F41_P_2) }, | |
43234a1e L |
4595 | }, |
4596 | ||
4597 | /* PREFIX_VEX_0F42 */ | |
4598 | { | |
4599 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_0) }, | |
1ba585e8 IT |
4600 | { Bad_Opcode }, |
4601 | { VEX_LEN_TABLE (VEX_LEN_0F42_P_2) }, | |
43234a1e L |
4602 | }, |
4603 | ||
4604 | /* PREFIX_VEX_0F44 */ | |
4605 | { | |
4606 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_0) }, | |
1ba585e8 IT |
4607 | { Bad_Opcode }, |
4608 | { VEX_LEN_TABLE (VEX_LEN_0F44_P_2) }, | |
43234a1e L |
4609 | }, |
4610 | ||
4611 | /* PREFIX_VEX_0F45 */ | |
4612 | { | |
4613 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_0) }, | |
1ba585e8 IT |
4614 | { Bad_Opcode }, |
4615 | { VEX_LEN_TABLE (VEX_LEN_0F45_P_2) }, | |
43234a1e L |
4616 | }, |
4617 | ||
4618 | /* PREFIX_VEX_0F46 */ | |
4619 | { | |
4620 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_0) }, | |
1ba585e8 IT |
4621 | { Bad_Opcode }, |
4622 | { VEX_LEN_TABLE (VEX_LEN_0F46_P_2) }, | |
43234a1e L |
4623 | }, |
4624 | ||
4625 | /* PREFIX_VEX_0F47 */ | |
4626 | { | |
4627 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_0) }, | |
1ba585e8 IT |
4628 | { Bad_Opcode }, |
4629 | { VEX_LEN_TABLE (VEX_LEN_0F47_P_2) }, | |
43234a1e L |
4630 | }, |
4631 | ||
1ba585e8 | 4632 | /* PREFIX_VEX_0F4A */ |
43234a1e | 4633 | { |
1ba585e8 | 4634 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_0) }, |
43234a1e | 4635 | { Bad_Opcode }, |
1ba585e8 IT |
4636 | { VEX_LEN_TABLE (VEX_LEN_0F4A_P_2) }, |
4637 | }, | |
4638 | ||
4639 | /* PREFIX_VEX_0F4B */ | |
4640 | { | |
4641 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_0) }, | |
43234a1e L |
4642 | { Bad_Opcode }, |
4643 | { VEX_LEN_TABLE (VEX_LEN_0F4B_P_2) }, | |
4644 | }, | |
4645 | ||
592a252b | 4646 | /* PREFIX_VEX_0F51 */ |
7c52e0e8 | 4647 | { |
ec6f095a | 4648 | { "vsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4649 | { "vsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4650 | { "vsqrtpd", { XM, EXx }, 0 }, |
5b872f7d | 4651 | { "vsqrtsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4652 | }, |
4653 | ||
592a252b | 4654 | /* PREFIX_VEX_0F52 */ |
7c52e0e8 | 4655 | { |
ec6f095a | 4656 | { "vrsqrtps", { XM, EXx }, 0 }, |
5b872f7d | 4657 | { "vrsqrtss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4658 | }, |
4659 | ||
592a252b | 4660 | /* PREFIX_VEX_0F53 */ |
7c52e0e8 | 4661 | { |
ec6f095a | 4662 | { "vrcpps", { XM, EXx }, 0 }, |
5b872f7d | 4663 | { "vrcpss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
7c52e0e8 L |
4664 | }, |
4665 | ||
592a252b | 4666 | /* PREFIX_VEX_0F58 */ |
7c52e0e8 | 4667 | { |
ec6f095a | 4668 | { "vaddps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4669 | { "vaddss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4670 | { "vaddpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4671 | { "vaddsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4672 | }, |
4673 | ||
592a252b | 4674 | /* PREFIX_VEX_0F59 */ |
7c52e0e8 | 4675 | { |
ec6f095a | 4676 | { "vmulps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4677 | { "vmulss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4678 | { "vmulpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4679 | { "vmulsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4680 | }, |
4681 | ||
592a252b | 4682 | /* PREFIX_VEX_0F5A */ |
7c52e0e8 | 4683 | { |
ec6f095a | 4684 | { "vcvtps2pd", { XM, EXxmmq }, 0 }, |
5b872f7d | 4685 | { "vcvtss2sd", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4686 | { "vcvtpd2ps%XY",{ XMM, EXx }, 0 }, |
5b872f7d | 4687 | { "vcvtsd2ss", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4688 | }, |
4689 | ||
592a252b | 4690 | /* PREFIX_VEX_0F5B */ |
7c52e0e8 | 4691 | { |
ec6f095a L |
4692 | { "vcvtdq2ps", { XM, EXx }, 0 }, |
4693 | { "vcvttps2dq", { XM, EXx }, 0 }, | |
4694 | { "vcvtps2dq", { XM, EXx }, 0 }, | |
7c52e0e8 L |
4695 | }, |
4696 | ||
592a252b | 4697 | /* PREFIX_VEX_0F5C */ |
7c52e0e8 | 4698 | { |
ec6f095a | 4699 | { "vsubps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4700 | { "vsubss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4701 | { "vsubpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4702 | { "vsubsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4703 | }, |
4704 | ||
592a252b | 4705 | /* PREFIX_VEX_0F5D */ |
7c52e0e8 | 4706 | { |
ec6f095a | 4707 | { "vminps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4708 | { "vminss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4709 | { "vminpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4710 | { "vminsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4711 | }, |
4712 | ||
592a252b | 4713 | /* PREFIX_VEX_0F5E */ |
7c52e0e8 | 4714 | { |
ec6f095a | 4715 | { "vdivps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4716 | { "vdivss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4717 | { "vdivpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4718 | { "vdivsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4719 | }, |
4720 | ||
592a252b | 4721 | /* PREFIX_VEX_0F5F */ |
7c52e0e8 | 4722 | { |
ec6f095a | 4723 | { "vmaxps", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4724 | { "vmaxss", { XMScalar, VexScalar, EXxmm_md }, 0 }, |
ec6f095a | 4725 | { "vmaxpd", { XM, Vex, EXx }, 0 }, |
5b872f7d | 4726 | { "vmaxsd", { XMScalar, VexScalar, EXxmm_mq }, 0 }, |
7c52e0e8 L |
4727 | }, |
4728 | ||
592a252b | 4729 | /* PREFIX_VEX_0F60 */ |
7c52e0e8 | 4730 | { |
592d1631 L |
4731 | { Bad_Opcode }, |
4732 | { Bad_Opcode }, | |
ec6f095a | 4733 | { "vpunpcklbw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4734 | }, |
4735 | ||
592a252b | 4736 | /* PREFIX_VEX_0F61 */ |
7c52e0e8 | 4737 | { |
592d1631 L |
4738 | { Bad_Opcode }, |
4739 | { Bad_Opcode }, | |
ec6f095a | 4740 | { "vpunpcklwd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4741 | }, |
4742 | ||
592a252b | 4743 | /* PREFIX_VEX_0F62 */ |
7c52e0e8 | 4744 | { |
592d1631 L |
4745 | { Bad_Opcode }, |
4746 | { Bad_Opcode }, | |
ec6f095a | 4747 | { "vpunpckldq", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4748 | }, |
4749 | ||
592a252b | 4750 | /* PREFIX_VEX_0F63 */ |
7c52e0e8 | 4751 | { |
592d1631 L |
4752 | { Bad_Opcode }, |
4753 | { Bad_Opcode }, | |
ec6f095a | 4754 | { "vpacksswb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4755 | }, |
4756 | ||
592a252b | 4757 | /* PREFIX_VEX_0F64 */ |
7c52e0e8 | 4758 | { |
592d1631 L |
4759 | { Bad_Opcode }, |
4760 | { Bad_Opcode }, | |
ec6f095a | 4761 | { "vpcmpgtb", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4762 | }, |
4763 | ||
592a252b | 4764 | /* PREFIX_VEX_0F65 */ |
7c52e0e8 | 4765 | { |
592d1631 L |
4766 | { Bad_Opcode }, |
4767 | { Bad_Opcode }, | |
ec6f095a | 4768 | { "vpcmpgtw", { XM, Vex, EXx }, 0 }, |
7c52e0e8 L |
4769 | }, |
4770 | ||
592a252b | 4771 | /* PREFIX_VEX_0F66 */ |
7c52e0e8 | 4772 | { |
592d1631 L |
4773 | { Bad_Opcode }, |
4774 | { Bad_Opcode }, | |
ec6f095a | 4775 | { "vpcmpgtd", { XM, Vex, EXx }, 0 }, |
7c52e0e8 | 4776 | }, |
6439fc28 | 4777 | |
592a252b | 4778 | /* PREFIX_VEX_0F67 */ |
331d2d0d | 4779 | { |
592d1631 L |
4780 | { Bad_Opcode }, |
4781 | { Bad_Opcode }, | |
ec6f095a | 4782 | { "vpackuswb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4783 | }, |
4784 | ||
592a252b | 4785 | /* PREFIX_VEX_0F68 */ |
c0f3af97 | 4786 | { |
592d1631 L |
4787 | { Bad_Opcode }, |
4788 | { Bad_Opcode }, | |
ec6f095a | 4789 | { "vpunpckhbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4790 | }, |
4791 | ||
592a252b | 4792 | /* PREFIX_VEX_0F69 */ |
c0f3af97 | 4793 | { |
592d1631 L |
4794 | { Bad_Opcode }, |
4795 | { Bad_Opcode }, | |
ec6f095a | 4796 | { "vpunpckhwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4797 | }, |
4798 | ||
592a252b | 4799 | /* PREFIX_VEX_0F6A */ |
c0f3af97 | 4800 | { |
592d1631 L |
4801 | { Bad_Opcode }, |
4802 | { Bad_Opcode }, | |
ec6f095a | 4803 | { "vpunpckhdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4804 | }, |
4805 | ||
592a252b | 4806 | /* PREFIX_VEX_0F6B */ |
c0f3af97 | 4807 | { |
592d1631 L |
4808 | { Bad_Opcode }, |
4809 | { Bad_Opcode }, | |
ec6f095a | 4810 | { "vpackssdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4811 | }, |
4812 | ||
592a252b | 4813 | /* PREFIX_VEX_0F6C */ |
c0f3af97 | 4814 | { |
592d1631 L |
4815 | { Bad_Opcode }, |
4816 | { Bad_Opcode }, | |
ec6f095a | 4817 | { "vpunpcklqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4818 | }, |
4819 | ||
592a252b | 4820 | /* PREFIX_VEX_0F6D */ |
c0f3af97 | 4821 | { |
592d1631 L |
4822 | { Bad_Opcode }, |
4823 | { Bad_Opcode }, | |
ec6f095a | 4824 | { "vpunpckhqdq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4825 | }, |
4826 | ||
592a252b | 4827 | /* PREFIX_VEX_0F6E */ |
c0f3af97 | 4828 | { |
592d1631 L |
4829 | { Bad_Opcode }, |
4830 | { Bad_Opcode }, | |
592a252b | 4831 | { VEX_LEN_TABLE (VEX_LEN_0F6E_P_2) }, |
c0f3af97 L |
4832 | }, |
4833 | ||
592a252b | 4834 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 4835 | { |
592d1631 | 4836 | { Bad_Opcode }, |
ec6f095a L |
4837 | { "vmovdqu", { XM, EXx }, 0 }, |
4838 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
4839 | }, |
4840 | ||
592a252b | 4841 | /* PREFIX_VEX_0F70 */ |
c0f3af97 | 4842 | { |
592d1631 | 4843 | { Bad_Opcode }, |
ec6f095a L |
4844 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
4845 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
4846 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
c0f3af97 L |
4847 | }, |
4848 | ||
592a252b | 4849 | /* PREFIX_VEX_0F71_REG_2 */ |
c0f3af97 | 4850 | { |
592d1631 L |
4851 | { Bad_Opcode }, |
4852 | { Bad_Opcode }, | |
ec6f095a | 4853 | { "vpsrlw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4854 | }, |
4855 | ||
592a252b | 4856 | /* PREFIX_VEX_0F71_REG_4 */ |
c0f3af97 | 4857 | { |
592d1631 L |
4858 | { Bad_Opcode }, |
4859 | { Bad_Opcode }, | |
ec6f095a | 4860 | { "vpsraw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4861 | }, |
4862 | ||
592a252b | 4863 | /* PREFIX_VEX_0F71_REG_6 */ |
c0f3af97 | 4864 | { |
592d1631 L |
4865 | { Bad_Opcode }, |
4866 | { Bad_Opcode }, | |
ec6f095a | 4867 | { "vpsllw", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4868 | }, |
4869 | ||
592a252b | 4870 | /* PREFIX_VEX_0F72_REG_2 */ |
c0f3af97 | 4871 | { |
592d1631 L |
4872 | { Bad_Opcode }, |
4873 | { Bad_Opcode }, | |
ec6f095a | 4874 | { "vpsrld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4875 | }, |
4876 | ||
592a252b | 4877 | /* PREFIX_VEX_0F72_REG_4 */ |
c0f3af97 | 4878 | { |
592d1631 L |
4879 | { Bad_Opcode }, |
4880 | { Bad_Opcode }, | |
ec6f095a | 4881 | { "vpsrad", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4882 | }, |
4883 | ||
592a252b | 4884 | /* PREFIX_VEX_0F72_REG_6 */ |
c0f3af97 | 4885 | { |
592d1631 L |
4886 | { Bad_Opcode }, |
4887 | { Bad_Opcode }, | |
ec6f095a | 4888 | { "vpslld", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4889 | }, |
4890 | ||
592a252b | 4891 | /* PREFIX_VEX_0F73_REG_2 */ |
c0f3af97 | 4892 | { |
592d1631 L |
4893 | { Bad_Opcode }, |
4894 | { Bad_Opcode }, | |
ec6f095a | 4895 | { "vpsrlq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4896 | }, |
4897 | ||
592a252b | 4898 | /* PREFIX_VEX_0F73_REG_3 */ |
c0f3af97 | 4899 | { |
592d1631 L |
4900 | { Bad_Opcode }, |
4901 | { Bad_Opcode }, | |
ec6f095a | 4902 | { "vpsrldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4903 | }, |
4904 | ||
592a252b | 4905 | /* PREFIX_VEX_0F73_REG_6 */ |
c0f3af97 | 4906 | { |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
ec6f095a | 4909 | { "vpsllq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4910 | }, |
4911 | ||
592a252b | 4912 | /* PREFIX_VEX_0F73_REG_7 */ |
c0f3af97 | 4913 | { |
592d1631 L |
4914 | { Bad_Opcode }, |
4915 | { Bad_Opcode }, | |
ec6f095a | 4916 | { "vpslldq", { Vex, XS, Ib }, 0 }, |
c0f3af97 L |
4917 | }, |
4918 | ||
592a252b | 4919 | /* PREFIX_VEX_0F74 */ |
c0f3af97 | 4920 | { |
592d1631 L |
4921 | { Bad_Opcode }, |
4922 | { Bad_Opcode }, | |
ec6f095a | 4923 | { "vpcmpeqb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4924 | }, |
4925 | ||
592a252b | 4926 | /* PREFIX_VEX_0F75 */ |
c0f3af97 | 4927 | { |
592d1631 L |
4928 | { Bad_Opcode }, |
4929 | { Bad_Opcode }, | |
ec6f095a | 4930 | { "vpcmpeqw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4931 | }, |
4932 | ||
592a252b | 4933 | /* PREFIX_VEX_0F76 */ |
c0f3af97 | 4934 | { |
592d1631 L |
4935 | { Bad_Opcode }, |
4936 | { Bad_Opcode }, | |
ec6f095a | 4937 | { "vpcmpeqd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
4938 | }, |
4939 | ||
592a252b | 4940 | /* PREFIX_VEX_0F77 */ |
c0f3af97 | 4941 | { |
ec6f095a | 4942 | { VEX_LEN_TABLE (VEX_LEN_0F77_P_0) }, |
c0f3af97 L |
4943 | }, |
4944 | ||
592a252b | 4945 | /* PREFIX_VEX_0F7C */ |
c0f3af97 | 4946 | { |
592d1631 L |
4947 | { Bad_Opcode }, |
4948 | { Bad_Opcode }, | |
ec6f095a L |
4949 | { "vhaddpd", { XM, Vex, EXx }, 0 }, |
4950 | { "vhaddps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4951 | }, |
4952 | ||
592a252b | 4953 | /* PREFIX_VEX_0F7D */ |
c0f3af97 | 4954 | { |
592d1631 L |
4955 | { Bad_Opcode }, |
4956 | { Bad_Opcode }, | |
ec6f095a L |
4957 | { "vhsubpd", { XM, Vex, EXx }, 0 }, |
4958 | { "vhsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
4959 | }, |
4960 | ||
592a252b | 4961 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 4962 | { |
592d1631 | 4963 | { Bad_Opcode }, |
592a252b L |
4964 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
4965 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
4966 | }, |
4967 | ||
592a252b | 4968 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 4969 | { |
592d1631 | 4970 | { Bad_Opcode }, |
ec6f095a L |
4971 | { "vmovdqu", { EXxS, XM }, 0 }, |
4972 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
4973 | }, |
4974 | ||
43234a1e L |
4975 | /* PREFIX_VEX_0F90 */ |
4976 | { | |
4977 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_0) }, | |
1ba585e8 IT |
4978 | { Bad_Opcode }, |
4979 | { VEX_LEN_TABLE (VEX_LEN_0F90_P_2) }, | |
43234a1e L |
4980 | }, |
4981 | ||
4982 | /* PREFIX_VEX_0F91 */ | |
4983 | { | |
4984 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_0) }, | |
1ba585e8 IT |
4985 | { Bad_Opcode }, |
4986 | { VEX_LEN_TABLE (VEX_LEN_0F91_P_2) }, | |
43234a1e L |
4987 | }, |
4988 | ||
4989 | /* PREFIX_VEX_0F92 */ | |
4990 | { | |
4991 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_0) }, | |
1ba585e8 | 4992 | { Bad_Opcode }, |
90a915bf | 4993 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_2) }, |
1ba585e8 | 4994 | { VEX_LEN_TABLE (VEX_LEN_0F92_P_3) }, |
43234a1e L |
4995 | }, |
4996 | ||
4997 | /* PREFIX_VEX_0F93 */ | |
4998 | { | |
4999 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_0) }, | |
1ba585e8 | 5000 | { Bad_Opcode }, |
90a915bf | 5001 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_2) }, |
1ba585e8 | 5002 | { VEX_LEN_TABLE (VEX_LEN_0F93_P_3) }, |
43234a1e L |
5003 | }, |
5004 | ||
5005 | /* PREFIX_VEX_0F98 */ | |
5006 | { | |
5007 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_0) }, | |
1ba585e8 IT |
5008 | { Bad_Opcode }, |
5009 | { VEX_LEN_TABLE (VEX_LEN_0F98_P_2) }, | |
5010 | }, | |
5011 | ||
5012 | /* PREFIX_VEX_0F99 */ | |
5013 | { | |
5014 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_0) }, | |
5015 | { Bad_Opcode }, | |
5016 | { VEX_LEN_TABLE (VEX_LEN_0F99_P_2) }, | |
43234a1e L |
5017 | }, |
5018 | ||
592a252b | 5019 | /* PREFIX_VEX_0FC2 */ |
c0f3af97 | 5020 | { |
ec6f095a | 5021 | { "vcmpps", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5022 | { "vcmpss", { XMScalar, VexScalar, EXxmm_md, VCMP }, 0 }, |
ec6f095a | 5023 | { "vcmppd", { XM, Vex, EXx, VCMP }, 0 }, |
5b872f7d | 5024 | { "vcmpsd", { XMScalar, VexScalar, EXxmm_mq, VCMP }, 0 }, |
c0f3af97 L |
5025 | }, |
5026 | ||
592a252b | 5027 | /* PREFIX_VEX_0FC4 */ |
c0f3af97 | 5028 | { |
592d1631 L |
5029 | { Bad_Opcode }, |
5030 | { Bad_Opcode }, | |
592a252b | 5031 | { VEX_LEN_TABLE (VEX_LEN_0FC4_P_2) }, |
c0f3af97 L |
5032 | }, |
5033 | ||
592a252b | 5034 | /* PREFIX_VEX_0FC5 */ |
c0f3af97 | 5035 | { |
592d1631 L |
5036 | { Bad_Opcode }, |
5037 | { Bad_Opcode }, | |
592a252b | 5038 | { VEX_LEN_TABLE (VEX_LEN_0FC5_P_2) }, |
c0f3af97 L |
5039 | }, |
5040 | ||
592a252b | 5041 | /* PREFIX_VEX_0FD0 */ |
c0f3af97 | 5042 | { |
592d1631 L |
5043 | { Bad_Opcode }, |
5044 | { Bad_Opcode }, | |
ec6f095a L |
5045 | { "vaddsubpd", { XM, Vex, EXx }, 0 }, |
5046 | { "vaddsubps", { XM, Vex, EXx }, 0 }, | |
c0f3af97 L |
5047 | }, |
5048 | ||
592a252b | 5049 | /* PREFIX_VEX_0FD1 */ |
c0f3af97 | 5050 | { |
592d1631 L |
5051 | { Bad_Opcode }, |
5052 | { Bad_Opcode }, | |
ec6f095a | 5053 | { "vpsrlw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5054 | }, |
5055 | ||
592a252b | 5056 | /* PREFIX_VEX_0FD2 */ |
c0f3af97 | 5057 | { |
592d1631 L |
5058 | { Bad_Opcode }, |
5059 | { Bad_Opcode }, | |
ec6f095a | 5060 | { "vpsrld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5061 | }, |
5062 | ||
592a252b | 5063 | /* PREFIX_VEX_0FD3 */ |
c0f3af97 | 5064 | { |
592d1631 L |
5065 | { Bad_Opcode }, |
5066 | { Bad_Opcode }, | |
ec6f095a | 5067 | { "vpsrlq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5068 | }, |
5069 | ||
592a252b | 5070 | /* PREFIX_VEX_0FD4 */ |
c0f3af97 | 5071 | { |
592d1631 L |
5072 | { Bad_Opcode }, |
5073 | { Bad_Opcode }, | |
ec6f095a | 5074 | { "vpaddq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5075 | }, |
5076 | ||
592a252b | 5077 | /* PREFIX_VEX_0FD5 */ |
c0f3af97 | 5078 | { |
592d1631 L |
5079 | { Bad_Opcode }, |
5080 | { Bad_Opcode }, | |
ec6f095a | 5081 | { "vpmullw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5082 | }, |
5083 | ||
592a252b | 5084 | /* PREFIX_VEX_0FD6 */ |
c0f3af97 | 5085 | { |
592d1631 L |
5086 | { Bad_Opcode }, |
5087 | { Bad_Opcode }, | |
592a252b | 5088 | { VEX_LEN_TABLE (VEX_LEN_0FD6_P_2) }, |
c0f3af97 L |
5089 | }, |
5090 | ||
592a252b | 5091 | /* PREFIX_VEX_0FD7 */ |
c0f3af97 | 5092 | { |
592d1631 L |
5093 | { Bad_Opcode }, |
5094 | { Bad_Opcode }, | |
592a252b | 5095 | { MOD_TABLE (MOD_VEX_0FD7_PREFIX_2) }, |
c0f3af97 L |
5096 | }, |
5097 | ||
592a252b | 5098 | /* PREFIX_VEX_0FD8 */ |
c0f3af97 | 5099 | { |
592d1631 L |
5100 | { Bad_Opcode }, |
5101 | { Bad_Opcode }, | |
ec6f095a | 5102 | { "vpsubusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5103 | }, |
5104 | ||
592a252b | 5105 | /* PREFIX_VEX_0FD9 */ |
c0f3af97 | 5106 | { |
592d1631 L |
5107 | { Bad_Opcode }, |
5108 | { Bad_Opcode }, | |
ec6f095a | 5109 | { "vpsubusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5110 | }, |
5111 | ||
592a252b | 5112 | /* PREFIX_VEX_0FDA */ |
c0f3af97 | 5113 | { |
592d1631 L |
5114 | { Bad_Opcode }, |
5115 | { Bad_Opcode }, | |
ec6f095a | 5116 | { "vpminub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5117 | }, |
5118 | ||
592a252b | 5119 | /* PREFIX_VEX_0FDB */ |
c0f3af97 | 5120 | { |
592d1631 L |
5121 | { Bad_Opcode }, |
5122 | { Bad_Opcode }, | |
ec6f095a | 5123 | { "vpand", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5124 | }, |
5125 | ||
592a252b | 5126 | /* PREFIX_VEX_0FDC */ |
c0f3af97 | 5127 | { |
592d1631 L |
5128 | { Bad_Opcode }, |
5129 | { Bad_Opcode }, | |
ec6f095a | 5130 | { "vpaddusb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5131 | }, |
5132 | ||
592a252b | 5133 | /* PREFIX_VEX_0FDD */ |
c0f3af97 | 5134 | { |
592d1631 L |
5135 | { Bad_Opcode }, |
5136 | { Bad_Opcode }, | |
ec6f095a | 5137 | { "vpaddusw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5138 | }, |
5139 | ||
592a252b | 5140 | /* PREFIX_VEX_0FDE */ |
c0f3af97 | 5141 | { |
592d1631 L |
5142 | { Bad_Opcode }, |
5143 | { Bad_Opcode }, | |
ec6f095a | 5144 | { "vpmaxub", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5145 | }, |
5146 | ||
592a252b | 5147 | /* PREFIX_VEX_0FDF */ |
c0f3af97 | 5148 | { |
592d1631 L |
5149 | { Bad_Opcode }, |
5150 | { Bad_Opcode }, | |
ec6f095a | 5151 | { "vpandn", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5152 | }, |
5153 | ||
592a252b | 5154 | /* PREFIX_VEX_0FE0 */ |
c0f3af97 | 5155 | { |
592d1631 L |
5156 | { Bad_Opcode }, |
5157 | { Bad_Opcode }, | |
ec6f095a | 5158 | { "vpavgb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5159 | }, |
5160 | ||
592a252b | 5161 | /* PREFIX_VEX_0FE1 */ |
c0f3af97 | 5162 | { |
592d1631 L |
5163 | { Bad_Opcode }, |
5164 | { Bad_Opcode }, | |
ec6f095a | 5165 | { "vpsraw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5166 | }, |
5167 | ||
592a252b | 5168 | /* PREFIX_VEX_0FE2 */ |
c0f3af97 | 5169 | { |
592d1631 L |
5170 | { Bad_Opcode }, |
5171 | { Bad_Opcode }, | |
ec6f095a | 5172 | { "vpsrad", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5173 | }, |
5174 | ||
592a252b | 5175 | /* PREFIX_VEX_0FE3 */ |
c0f3af97 | 5176 | { |
592d1631 L |
5177 | { Bad_Opcode }, |
5178 | { Bad_Opcode }, | |
ec6f095a | 5179 | { "vpavgw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5180 | }, |
5181 | ||
592a252b | 5182 | /* PREFIX_VEX_0FE4 */ |
c0f3af97 | 5183 | { |
592d1631 L |
5184 | { Bad_Opcode }, |
5185 | { Bad_Opcode }, | |
ec6f095a | 5186 | { "vpmulhuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5187 | }, |
5188 | ||
592a252b | 5189 | /* PREFIX_VEX_0FE5 */ |
c0f3af97 | 5190 | { |
592d1631 L |
5191 | { Bad_Opcode }, |
5192 | { Bad_Opcode }, | |
ec6f095a | 5193 | { "vpmulhw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5194 | }, |
5195 | ||
592a252b | 5196 | /* PREFIX_VEX_0FE6 */ |
c0f3af97 | 5197 | { |
592d1631 | 5198 | { Bad_Opcode }, |
ec6f095a L |
5199 | { "vcvtdq2pd", { XM, EXxmmq }, 0 }, |
5200 | { "vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
5201 | { "vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
c0f3af97 L |
5202 | }, |
5203 | ||
592a252b | 5204 | /* PREFIX_VEX_0FE7 */ |
c0f3af97 | 5205 | { |
592d1631 L |
5206 | { Bad_Opcode }, |
5207 | { Bad_Opcode }, | |
592a252b | 5208 | { MOD_TABLE (MOD_VEX_0FE7_PREFIX_2) }, |
c0f3af97 L |
5209 | }, |
5210 | ||
592a252b | 5211 | /* PREFIX_VEX_0FE8 */ |
c0f3af97 | 5212 | { |
592d1631 L |
5213 | { Bad_Opcode }, |
5214 | { Bad_Opcode }, | |
ec6f095a | 5215 | { "vpsubsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5216 | }, |
5217 | ||
592a252b | 5218 | /* PREFIX_VEX_0FE9 */ |
c0f3af97 | 5219 | { |
592d1631 L |
5220 | { Bad_Opcode }, |
5221 | { Bad_Opcode }, | |
ec6f095a | 5222 | { "vpsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5223 | }, |
5224 | ||
592a252b | 5225 | /* PREFIX_VEX_0FEA */ |
c0f3af97 | 5226 | { |
592d1631 L |
5227 | { Bad_Opcode }, |
5228 | { Bad_Opcode }, | |
ec6f095a | 5229 | { "vpminsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5230 | }, |
5231 | ||
592a252b | 5232 | /* PREFIX_VEX_0FEB */ |
c0f3af97 | 5233 | { |
592d1631 L |
5234 | { Bad_Opcode }, |
5235 | { Bad_Opcode }, | |
ec6f095a | 5236 | { "vpor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5237 | }, |
5238 | ||
592a252b | 5239 | /* PREFIX_VEX_0FEC */ |
c0f3af97 | 5240 | { |
592d1631 L |
5241 | { Bad_Opcode }, |
5242 | { Bad_Opcode }, | |
ec6f095a | 5243 | { "vpaddsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5244 | }, |
5245 | ||
592a252b | 5246 | /* PREFIX_VEX_0FED */ |
c0f3af97 | 5247 | { |
592d1631 L |
5248 | { Bad_Opcode }, |
5249 | { Bad_Opcode }, | |
ec6f095a | 5250 | { "vpaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5251 | }, |
5252 | ||
592a252b | 5253 | /* PREFIX_VEX_0FEE */ |
c0f3af97 | 5254 | { |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
ec6f095a | 5257 | { "vpmaxsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5258 | }, |
5259 | ||
592a252b | 5260 | /* PREFIX_VEX_0FEF */ |
c0f3af97 | 5261 | { |
592d1631 L |
5262 | { Bad_Opcode }, |
5263 | { Bad_Opcode }, | |
ec6f095a | 5264 | { "vpxor", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5265 | }, |
5266 | ||
592a252b | 5267 | /* PREFIX_VEX_0FF0 */ |
c0f3af97 | 5268 | { |
592d1631 L |
5269 | { Bad_Opcode }, |
5270 | { Bad_Opcode }, | |
5271 | { Bad_Opcode }, | |
592a252b | 5272 | { MOD_TABLE (MOD_VEX_0FF0_PREFIX_3) }, |
c0f3af97 L |
5273 | }, |
5274 | ||
592a252b | 5275 | /* PREFIX_VEX_0FF1 */ |
c0f3af97 | 5276 | { |
592d1631 L |
5277 | { Bad_Opcode }, |
5278 | { Bad_Opcode }, | |
ec6f095a | 5279 | { "vpsllw", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5280 | }, |
5281 | ||
592a252b | 5282 | /* PREFIX_VEX_0FF2 */ |
c0f3af97 | 5283 | { |
592d1631 L |
5284 | { Bad_Opcode }, |
5285 | { Bad_Opcode }, | |
ec6f095a | 5286 | { "vpslld", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5287 | }, |
5288 | ||
592a252b | 5289 | /* PREFIX_VEX_0FF3 */ |
c0f3af97 | 5290 | { |
592d1631 L |
5291 | { Bad_Opcode }, |
5292 | { Bad_Opcode }, | |
ec6f095a | 5293 | { "vpsllq", { XM, Vex, EXxmm }, 0 }, |
c0f3af97 L |
5294 | }, |
5295 | ||
592a252b | 5296 | /* PREFIX_VEX_0FF4 */ |
c0f3af97 | 5297 | { |
592d1631 L |
5298 | { Bad_Opcode }, |
5299 | { Bad_Opcode }, | |
ec6f095a | 5300 | { "vpmuludq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5301 | }, |
5302 | ||
592a252b | 5303 | /* PREFIX_VEX_0FF5 */ |
c0f3af97 | 5304 | { |
592d1631 L |
5305 | { Bad_Opcode }, |
5306 | { Bad_Opcode }, | |
ec6f095a | 5307 | { "vpmaddwd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5308 | }, |
5309 | ||
592a252b | 5310 | /* PREFIX_VEX_0FF6 */ |
c0f3af97 | 5311 | { |
592d1631 L |
5312 | { Bad_Opcode }, |
5313 | { Bad_Opcode }, | |
ec6f095a | 5314 | { "vpsadbw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5315 | }, |
5316 | ||
592a252b | 5317 | /* PREFIX_VEX_0FF7 */ |
c0f3af97 | 5318 | { |
592d1631 L |
5319 | { Bad_Opcode }, |
5320 | { Bad_Opcode }, | |
592a252b | 5321 | { VEX_LEN_TABLE (VEX_LEN_0FF7_P_2) }, |
c0f3af97 L |
5322 | }, |
5323 | ||
592a252b | 5324 | /* PREFIX_VEX_0FF8 */ |
c0f3af97 | 5325 | { |
592d1631 L |
5326 | { Bad_Opcode }, |
5327 | { Bad_Opcode }, | |
ec6f095a | 5328 | { "vpsubb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5329 | }, |
5330 | ||
592a252b | 5331 | /* PREFIX_VEX_0FF9 */ |
c0f3af97 | 5332 | { |
592d1631 L |
5333 | { Bad_Opcode }, |
5334 | { Bad_Opcode }, | |
ec6f095a | 5335 | { "vpsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5336 | }, |
5337 | ||
592a252b | 5338 | /* PREFIX_VEX_0FFA */ |
c0f3af97 | 5339 | { |
592d1631 L |
5340 | { Bad_Opcode }, |
5341 | { Bad_Opcode }, | |
ec6f095a | 5342 | { "vpsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5343 | }, |
5344 | ||
592a252b | 5345 | /* PREFIX_VEX_0FFB */ |
c0f3af97 | 5346 | { |
592d1631 L |
5347 | { Bad_Opcode }, |
5348 | { Bad_Opcode }, | |
ec6f095a | 5349 | { "vpsubq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5350 | }, |
5351 | ||
592a252b | 5352 | /* PREFIX_VEX_0FFC */ |
c0f3af97 | 5353 | { |
592d1631 L |
5354 | { Bad_Opcode }, |
5355 | { Bad_Opcode }, | |
ec6f095a | 5356 | { "vpaddb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5357 | }, |
5358 | ||
592a252b | 5359 | /* PREFIX_VEX_0FFD */ |
c0f3af97 | 5360 | { |
592d1631 L |
5361 | { Bad_Opcode }, |
5362 | { Bad_Opcode }, | |
ec6f095a | 5363 | { "vpaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5364 | }, |
5365 | ||
592a252b | 5366 | /* PREFIX_VEX_0FFE */ |
c0f3af97 | 5367 | { |
592d1631 L |
5368 | { Bad_Opcode }, |
5369 | { Bad_Opcode }, | |
ec6f095a | 5370 | { "vpaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5371 | }, |
5372 | ||
592a252b | 5373 | /* PREFIX_VEX_0F3800 */ |
c0f3af97 | 5374 | { |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
ec6f095a | 5377 | { "vpshufb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5378 | }, |
5379 | ||
592a252b | 5380 | /* PREFIX_VEX_0F3801 */ |
c0f3af97 | 5381 | { |
592d1631 L |
5382 | { Bad_Opcode }, |
5383 | { Bad_Opcode }, | |
ec6f095a | 5384 | { "vphaddw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5385 | }, |
5386 | ||
592a252b | 5387 | /* PREFIX_VEX_0F3802 */ |
c0f3af97 | 5388 | { |
592d1631 L |
5389 | { Bad_Opcode }, |
5390 | { Bad_Opcode }, | |
ec6f095a | 5391 | { "vphaddd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5392 | }, |
5393 | ||
592a252b | 5394 | /* PREFIX_VEX_0F3803 */ |
c0f3af97 | 5395 | { |
592d1631 L |
5396 | { Bad_Opcode }, |
5397 | { Bad_Opcode }, | |
ec6f095a | 5398 | { "vphaddsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5399 | }, |
5400 | ||
592a252b | 5401 | /* PREFIX_VEX_0F3804 */ |
c0f3af97 | 5402 | { |
592d1631 L |
5403 | { Bad_Opcode }, |
5404 | { Bad_Opcode }, | |
ec6f095a | 5405 | { "vpmaddubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5406 | }, |
5407 | ||
592a252b | 5408 | /* PREFIX_VEX_0F3805 */ |
c0f3af97 | 5409 | { |
592d1631 L |
5410 | { Bad_Opcode }, |
5411 | { Bad_Opcode }, | |
ec6f095a | 5412 | { "vphsubw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5413 | }, |
5414 | ||
592a252b | 5415 | /* PREFIX_VEX_0F3806 */ |
c0f3af97 | 5416 | { |
592d1631 L |
5417 | { Bad_Opcode }, |
5418 | { Bad_Opcode }, | |
ec6f095a | 5419 | { "vphsubd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5420 | }, |
5421 | ||
592a252b | 5422 | /* PREFIX_VEX_0F3807 */ |
c0f3af97 | 5423 | { |
592d1631 L |
5424 | { Bad_Opcode }, |
5425 | { Bad_Opcode }, | |
ec6f095a | 5426 | { "vphsubsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5427 | }, |
5428 | ||
592a252b | 5429 | /* PREFIX_VEX_0F3808 */ |
c0f3af97 | 5430 | { |
592d1631 L |
5431 | { Bad_Opcode }, |
5432 | { Bad_Opcode }, | |
ec6f095a | 5433 | { "vpsignb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5434 | }, |
5435 | ||
592a252b | 5436 | /* PREFIX_VEX_0F3809 */ |
c0f3af97 | 5437 | { |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
ec6f095a | 5440 | { "vpsignw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5441 | }, |
5442 | ||
592a252b | 5443 | /* PREFIX_VEX_0F380A */ |
c0f3af97 | 5444 | { |
592d1631 L |
5445 | { Bad_Opcode }, |
5446 | { Bad_Opcode }, | |
ec6f095a | 5447 | { "vpsignd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5448 | }, |
5449 | ||
592a252b | 5450 | /* PREFIX_VEX_0F380B */ |
c0f3af97 | 5451 | { |
592d1631 L |
5452 | { Bad_Opcode }, |
5453 | { Bad_Opcode }, | |
ec6f095a | 5454 | { "vpmulhrsw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5455 | }, |
5456 | ||
592a252b | 5457 | /* PREFIX_VEX_0F380C */ |
c0f3af97 | 5458 | { |
592d1631 L |
5459 | { Bad_Opcode }, |
5460 | { Bad_Opcode }, | |
592a252b | 5461 | { VEX_W_TABLE (VEX_W_0F380C_P_2) }, |
c0f3af97 L |
5462 | }, |
5463 | ||
592a252b | 5464 | /* PREFIX_VEX_0F380D */ |
c0f3af97 | 5465 | { |
592d1631 L |
5466 | { Bad_Opcode }, |
5467 | { Bad_Opcode }, | |
592a252b | 5468 | { VEX_W_TABLE (VEX_W_0F380D_P_2) }, |
c0f3af97 L |
5469 | }, |
5470 | ||
592a252b | 5471 | /* PREFIX_VEX_0F380E */ |
c0f3af97 | 5472 | { |
592d1631 L |
5473 | { Bad_Opcode }, |
5474 | { Bad_Opcode }, | |
592a252b | 5475 | { VEX_W_TABLE (VEX_W_0F380E_P_2) }, |
c0f3af97 L |
5476 | }, |
5477 | ||
592a252b | 5478 | /* PREFIX_VEX_0F380F */ |
c0f3af97 | 5479 | { |
592d1631 L |
5480 | { Bad_Opcode }, |
5481 | { Bad_Opcode }, | |
592a252b | 5482 | { VEX_W_TABLE (VEX_W_0F380F_P_2) }, |
c0f3af97 L |
5483 | }, |
5484 | ||
592a252b | 5485 | /* PREFIX_VEX_0F3813 */ |
c7b8aa3a L |
5486 | { |
5487 | { Bad_Opcode }, | |
5488 | { Bad_Opcode }, | |
6431c801 | 5489 | { VEX_W_TABLE (VEX_W_0F3813_P_2) }, |
c7b8aa3a L |
5490 | }, |
5491 | ||
6c30d220 L |
5492 | /* PREFIX_VEX_0F3816 */ |
5493 | { | |
5494 | { Bad_Opcode }, | |
5495 | { Bad_Opcode }, | |
5496 | { VEX_LEN_TABLE (VEX_LEN_0F3816_P_2) }, | |
5497 | }, | |
5498 | ||
592a252b | 5499 | /* PREFIX_VEX_0F3817 */ |
c0f3af97 | 5500 | { |
592d1631 L |
5501 | { Bad_Opcode }, |
5502 | { Bad_Opcode }, | |
ec6f095a | 5503 | { "vptest", { XM, EXx }, 0 }, |
c0f3af97 L |
5504 | }, |
5505 | ||
592a252b | 5506 | /* PREFIX_VEX_0F3818 */ |
c0f3af97 | 5507 | { |
592d1631 L |
5508 | { Bad_Opcode }, |
5509 | { Bad_Opcode }, | |
6c30d220 | 5510 | { VEX_W_TABLE (VEX_W_0F3818_P_2) }, |
c0f3af97 L |
5511 | }, |
5512 | ||
592a252b | 5513 | /* PREFIX_VEX_0F3819 */ |
c0f3af97 | 5514 | { |
592d1631 L |
5515 | { Bad_Opcode }, |
5516 | { Bad_Opcode }, | |
6c30d220 | 5517 | { VEX_LEN_TABLE (VEX_LEN_0F3819_P_2) }, |
c0f3af97 L |
5518 | }, |
5519 | ||
592a252b | 5520 | /* PREFIX_VEX_0F381A */ |
c0f3af97 | 5521 | { |
592d1631 L |
5522 | { Bad_Opcode }, |
5523 | { Bad_Opcode }, | |
592a252b | 5524 | { MOD_TABLE (MOD_VEX_0F381A_PREFIX_2) }, |
c0f3af97 L |
5525 | }, |
5526 | ||
592a252b | 5527 | /* PREFIX_VEX_0F381C */ |
c0f3af97 | 5528 | { |
592d1631 L |
5529 | { Bad_Opcode }, |
5530 | { Bad_Opcode }, | |
ec6f095a | 5531 | { "vpabsb", { XM, EXx }, 0 }, |
c0f3af97 L |
5532 | }, |
5533 | ||
592a252b | 5534 | /* PREFIX_VEX_0F381D */ |
c0f3af97 | 5535 | { |
592d1631 L |
5536 | { Bad_Opcode }, |
5537 | { Bad_Opcode }, | |
ec6f095a | 5538 | { "vpabsw", { XM, EXx }, 0 }, |
c0f3af97 L |
5539 | }, |
5540 | ||
592a252b | 5541 | /* PREFIX_VEX_0F381E */ |
c0f3af97 | 5542 | { |
592d1631 L |
5543 | { Bad_Opcode }, |
5544 | { Bad_Opcode }, | |
ec6f095a | 5545 | { "vpabsd", { XM, EXx }, 0 }, |
c0f3af97 L |
5546 | }, |
5547 | ||
592a252b | 5548 | /* PREFIX_VEX_0F3820 */ |
c0f3af97 | 5549 | { |
592d1631 L |
5550 | { Bad_Opcode }, |
5551 | { Bad_Opcode }, | |
ec6f095a | 5552 | { "vpmovsxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5553 | }, |
5554 | ||
592a252b | 5555 | /* PREFIX_VEX_0F3821 */ |
c0f3af97 | 5556 | { |
592d1631 L |
5557 | { Bad_Opcode }, |
5558 | { Bad_Opcode }, | |
ec6f095a | 5559 | { "vpmovsxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5560 | }, |
5561 | ||
592a252b | 5562 | /* PREFIX_VEX_0F3822 */ |
c0f3af97 | 5563 | { |
592d1631 L |
5564 | { Bad_Opcode }, |
5565 | { Bad_Opcode }, | |
ec6f095a | 5566 | { "vpmovsxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5567 | }, |
5568 | ||
592a252b | 5569 | /* PREFIX_VEX_0F3823 */ |
c0f3af97 | 5570 | { |
592d1631 L |
5571 | { Bad_Opcode }, |
5572 | { Bad_Opcode }, | |
ec6f095a | 5573 | { "vpmovsxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5574 | }, |
5575 | ||
592a252b | 5576 | /* PREFIX_VEX_0F3824 */ |
c0f3af97 | 5577 | { |
592d1631 L |
5578 | { Bad_Opcode }, |
5579 | { Bad_Opcode }, | |
ec6f095a | 5580 | { "vpmovsxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5581 | }, |
5582 | ||
592a252b | 5583 | /* PREFIX_VEX_0F3825 */ |
c0f3af97 | 5584 | { |
592d1631 L |
5585 | { Bad_Opcode }, |
5586 | { Bad_Opcode }, | |
ec6f095a | 5587 | { "vpmovsxdq", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5588 | }, |
5589 | ||
592a252b | 5590 | /* PREFIX_VEX_0F3828 */ |
c0f3af97 | 5591 | { |
592d1631 L |
5592 | { Bad_Opcode }, |
5593 | { Bad_Opcode }, | |
ec6f095a | 5594 | { "vpmuldq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5595 | }, |
5596 | ||
592a252b | 5597 | /* PREFIX_VEX_0F3829 */ |
c0f3af97 | 5598 | { |
592d1631 L |
5599 | { Bad_Opcode }, |
5600 | { Bad_Opcode }, | |
ec6f095a | 5601 | { "vpcmpeqq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5602 | }, |
5603 | ||
592a252b | 5604 | /* PREFIX_VEX_0F382A */ |
c0f3af97 | 5605 | { |
592d1631 L |
5606 | { Bad_Opcode }, |
5607 | { Bad_Opcode }, | |
592a252b | 5608 | { MOD_TABLE (MOD_VEX_0F382A_PREFIX_2) }, |
c0f3af97 L |
5609 | }, |
5610 | ||
592a252b | 5611 | /* PREFIX_VEX_0F382B */ |
c0f3af97 | 5612 | { |
592d1631 L |
5613 | { Bad_Opcode }, |
5614 | { Bad_Opcode }, | |
ec6f095a | 5615 | { "vpackusdw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5616 | }, |
5617 | ||
592a252b | 5618 | /* PREFIX_VEX_0F382C */ |
c0f3af97 | 5619 | { |
592d1631 L |
5620 | { Bad_Opcode }, |
5621 | { Bad_Opcode }, | |
592a252b | 5622 | { MOD_TABLE (MOD_VEX_0F382C_PREFIX_2) }, |
c0f3af97 L |
5623 | }, |
5624 | ||
592a252b | 5625 | /* PREFIX_VEX_0F382D */ |
c0f3af97 | 5626 | { |
592d1631 L |
5627 | { Bad_Opcode }, |
5628 | { Bad_Opcode }, | |
592a252b | 5629 | { MOD_TABLE (MOD_VEX_0F382D_PREFIX_2) }, |
c0f3af97 L |
5630 | }, |
5631 | ||
592a252b | 5632 | /* PREFIX_VEX_0F382E */ |
c0f3af97 | 5633 | { |
592d1631 L |
5634 | { Bad_Opcode }, |
5635 | { Bad_Opcode }, | |
592a252b | 5636 | { MOD_TABLE (MOD_VEX_0F382E_PREFIX_2) }, |
c0f3af97 L |
5637 | }, |
5638 | ||
592a252b | 5639 | /* PREFIX_VEX_0F382F */ |
c0f3af97 | 5640 | { |
592d1631 L |
5641 | { Bad_Opcode }, |
5642 | { Bad_Opcode }, | |
592a252b | 5643 | { MOD_TABLE (MOD_VEX_0F382F_PREFIX_2) }, |
c0f3af97 L |
5644 | }, |
5645 | ||
592a252b | 5646 | /* PREFIX_VEX_0F3830 */ |
c0f3af97 | 5647 | { |
592d1631 L |
5648 | { Bad_Opcode }, |
5649 | { Bad_Opcode }, | |
ec6f095a | 5650 | { "vpmovzxbw", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5651 | }, |
5652 | ||
592a252b | 5653 | /* PREFIX_VEX_0F3831 */ |
c0f3af97 | 5654 | { |
592d1631 L |
5655 | { Bad_Opcode }, |
5656 | { Bad_Opcode }, | |
ec6f095a | 5657 | { "vpmovzxbd", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5658 | }, |
5659 | ||
592a252b | 5660 | /* PREFIX_VEX_0F3832 */ |
c0f3af97 | 5661 | { |
592d1631 L |
5662 | { Bad_Opcode }, |
5663 | { Bad_Opcode }, | |
ec6f095a | 5664 | { "vpmovzxbq", { XM, EXxmmdw }, 0 }, |
c0f3af97 L |
5665 | }, |
5666 | ||
592a252b | 5667 | /* PREFIX_VEX_0F3833 */ |
c0f3af97 | 5668 | { |
592d1631 L |
5669 | { Bad_Opcode }, |
5670 | { Bad_Opcode }, | |
ec6f095a | 5671 | { "vpmovzxwd", { XM, EXxmmq }, 0 }, |
c0f3af97 L |
5672 | }, |
5673 | ||
592a252b | 5674 | /* PREFIX_VEX_0F3834 */ |
c0f3af97 | 5675 | { |
592d1631 L |
5676 | { Bad_Opcode }, |
5677 | { Bad_Opcode }, | |
ec6f095a | 5678 | { "vpmovzxwq", { XM, EXxmmqd }, 0 }, |
c0f3af97 L |
5679 | }, |
5680 | ||
592a252b | 5681 | /* PREFIX_VEX_0F3835 */ |
c0f3af97 | 5682 | { |
592d1631 L |
5683 | { Bad_Opcode }, |
5684 | { Bad_Opcode }, | |
ec6f095a | 5685 | { "vpmovzxdq", { XM, EXxmmq }, 0 }, |
6c30d220 L |
5686 | }, |
5687 | ||
5688 | /* PREFIX_VEX_0F3836 */ | |
5689 | { | |
5690 | { Bad_Opcode }, | |
5691 | { Bad_Opcode }, | |
5692 | { VEX_LEN_TABLE (VEX_LEN_0F3836_P_2) }, | |
c0f3af97 L |
5693 | }, |
5694 | ||
592a252b | 5695 | /* PREFIX_VEX_0F3837 */ |
c0f3af97 | 5696 | { |
592d1631 L |
5697 | { Bad_Opcode }, |
5698 | { Bad_Opcode }, | |
ec6f095a | 5699 | { "vpcmpgtq", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5700 | }, |
5701 | ||
592a252b | 5702 | /* PREFIX_VEX_0F3838 */ |
c0f3af97 | 5703 | { |
592d1631 L |
5704 | { Bad_Opcode }, |
5705 | { Bad_Opcode }, | |
ec6f095a | 5706 | { "vpminsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5707 | }, |
5708 | ||
592a252b | 5709 | /* PREFIX_VEX_0F3839 */ |
c0f3af97 | 5710 | { |
592d1631 L |
5711 | { Bad_Opcode }, |
5712 | { Bad_Opcode }, | |
ec6f095a | 5713 | { "vpminsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5714 | }, |
5715 | ||
592a252b | 5716 | /* PREFIX_VEX_0F383A */ |
c0f3af97 | 5717 | { |
592d1631 L |
5718 | { Bad_Opcode }, |
5719 | { Bad_Opcode }, | |
ec6f095a | 5720 | { "vpminuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5721 | }, |
5722 | ||
592a252b | 5723 | /* PREFIX_VEX_0F383B */ |
c0f3af97 | 5724 | { |
592d1631 L |
5725 | { Bad_Opcode }, |
5726 | { Bad_Opcode }, | |
ec6f095a | 5727 | { "vpminud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5728 | }, |
5729 | ||
592a252b | 5730 | /* PREFIX_VEX_0F383C */ |
c0f3af97 | 5731 | { |
592d1631 L |
5732 | { Bad_Opcode }, |
5733 | { Bad_Opcode }, | |
ec6f095a | 5734 | { "vpmaxsb", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5735 | }, |
5736 | ||
592a252b | 5737 | /* PREFIX_VEX_0F383D */ |
c0f3af97 | 5738 | { |
592d1631 L |
5739 | { Bad_Opcode }, |
5740 | { Bad_Opcode }, | |
ec6f095a | 5741 | { "vpmaxsd", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5742 | }, |
5743 | ||
592a252b | 5744 | /* PREFIX_VEX_0F383E */ |
c0f3af97 | 5745 | { |
592d1631 L |
5746 | { Bad_Opcode }, |
5747 | { Bad_Opcode }, | |
ec6f095a | 5748 | { "vpmaxuw", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5749 | }, |
5750 | ||
592a252b | 5751 | /* PREFIX_VEX_0F383F */ |
c0f3af97 | 5752 | { |
592d1631 L |
5753 | { Bad_Opcode }, |
5754 | { Bad_Opcode }, | |
ec6f095a | 5755 | { "vpmaxud", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5756 | }, |
5757 | ||
592a252b | 5758 | /* PREFIX_VEX_0F3840 */ |
c0f3af97 | 5759 | { |
592d1631 L |
5760 | { Bad_Opcode }, |
5761 | { Bad_Opcode }, | |
ec6f095a | 5762 | { "vpmulld", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5763 | }, |
5764 | ||
592a252b | 5765 | /* PREFIX_VEX_0F3841 */ |
c0f3af97 | 5766 | { |
592d1631 L |
5767 | { Bad_Opcode }, |
5768 | { Bad_Opcode }, | |
592a252b | 5769 | { VEX_LEN_TABLE (VEX_LEN_0F3841_P_2) }, |
c0f3af97 L |
5770 | }, |
5771 | ||
6c30d220 L |
5772 | /* PREFIX_VEX_0F3845 */ |
5773 | { | |
5774 | { Bad_Opcode }, | |
5775 | { Bad_Opcode }, | |
bf890a93 | 5776 | { "vpsrlv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5777 | }, |
5778 | ||
5779 | /* PREFIX_VEX_0F3846 */ | |
5780 | { | |
5781 | { Bad_Opcode }, | |
5782 | { Bad_Opcode }, | |
5783 | { VEX_W_TABLE (VEX_W_0F3846_P_2) }, | |
5784 | }, | |
5785 | ||
5786 | /* PREFIX_VEX_0F3847 */ | |
5787 | { | |
5788 | { Bad_Opcode }, | |
5789 | { Bad_Opcode }, | |
bf890a93 | 5790 | { "vpsllv%LW", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
5791 | }, |
5792 | ||
5793 | /* PREFIX_VEX_0F3858 */ | |
5794 | { | |
5795 | { Bad_Opcode }, | |
5796 | { Bad_Opcode }, | |
5797 | { VEX_W_TABLE (VEX_W_0F3858_P_2) }, | |
5798 | }, | |
5799 | ||
5800 | /* PREFIX_VEX_0F3859 */ | |
5801 | { | |
5802 | { Bad_Opcode }, | |
5803 | { Bad_Opcode }, | |
5804 | { VEX_W_TABLE (VEX_W_0F3859_P_2) }, | |
5805 | }, | |
5806 | ||
5807 | /* PREFIX_VEX_0F385A */ | |
5808 | { | |
5809 | { Bad_Opcode }, | |
5810 | { Bad_Opcode }, | |
5811 | { MOD_TABLE (MOD_VEX_0F385A_PREFIX_2) }, | |
5812 | }, | |
5813 | ||
5814 | /* PREFIX_VEX_0F3878 */ | |
5815 | { | |
5816 | { Bad_Opcode }, | |
5817 | { Bad_Opcode }, | |
5818 | { VEX_W_TABLE (VEX_W_0F3878_P_2) }, | |
5819 | }, | |
5820 | ||
5821 | /* PREFIX_VEX_0F3879 */ | |
5822 | { | |
5823 | { Bad_Opcode }, | |
5824 | { Bad_Opcode }, | |
5825 | { VEX_W_TABLE (VEX_W_0F3879_P_2) }, | |
5826 | }, | |
5827 | ||
5828 | /* PREFIX_VEX_0F388C */ | |
5829 | { | |
5830 | { Bad_Opcode }, | |
5831 | { Bad_Opcode }, | |
f7002f42 | 5832 | { MOD_TABLE (MOD_VEX_0F388C_PREFIX_2) }, |
6c30d220 L |
5833 | }, |
5834 | ||
5835 | /* PREFIX_VEX_0F388E */ | |
5836 | { | |
5837 | { Bad_Opcode }, | |
5838 | { Bad_Opcode }, | |
f7002f42 | 5839 | { MOD_TABLE (MOD_VEX_0F388E_PREFIX_2) }, |
6c30d220 L |
5840 | }, |
5841 | ||
5842 | /* PREFIX_VEX_0F3890 */ | |
5843 | { | |
5844 | { Bad_Opcode }, | |
5845 | { Bad_Opcode }, | |
bf890a93 | 5846 | { "vpgatherd%LW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5847 | }, |
5848 | ||
5849 | /* PREFIX_VEX_0F3891 */ | |
5850 | { | |
5851 | { Bad_Opcode }, | |
5852 | { Bad_Opcode }, | |
bf890a93 | 5853 | { "vpgatherq%LW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5854 | }, |
5855 | ||
5856 | /* PREFIX_VEX_0F3892 */ | |
5857 | { | |
5858 | { Bad_Opcode }, | |
5859 | { Bad_Opcode }, | |
bf890a93 | 5860 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, Vex }, 0 }, |
6c30d220 L |
5861 | }, |
5862 | ||
5863 | /* PREFIX_VEX_0F3893 */ | |
5864 | { | |
5865 | { Bad_Opcode }, | |
5866 | { Bad_Opcode }, | |
bf890a93 | 5867 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, 0 }, |
6c30d220 L |
5868 | }, |
5869 | ||
592a252b | 5870 | /* PREFIX_VEX_0F3896 */ |
a5ff0eb2 | 5871 | { |
592d1631 L |
5872 | { Bad_Opcode }, |
5873 | { Bad_Opcode }, | |
6df22cf6 | 5874 | { "vfmaddsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5875 | }, |
5876 | ||
592a252b | 5877 | /* PREFIX_VEX_0F3897 */ |
a5ff0eb2 | 5878 | { |
592d1631 L |
5879 | { Bad_Opcode }, |
5880 | { Bad_Opcode }, | |
6df22cf6 | 5881 | { "vfmsubadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5882 | }, |
5883 | ||
592a252b | 5884 | /* PREFIX_VEX_0F3898 */ |
a5ff0eb2 | 5885 | { |
592d1631 L |
5886 | { Bad_Opcode }, |
5887 | { Bad_Opcode }, | |
6df22cf6 | 5888 | { "vfmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5889 | }, |
5890 | ||
592a252b | 5891 | /* PREFIX_VEX_0F3899 */ |
a5ff0eb2 | 5892 | { |
592d1631 L |
5893 | { Bad_Opcode }, |
5894 | { Bad_Opcode }, | |
6df22cf6 | 5895 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
a5ff0eb2 L |
5896 | }, |
5897 | ||
592a252b | 5898 | /* PREFIX_VEX_0F389A */ |
a5ff0eb2 | 5899 | { |
592d1631 L |
5900 | { Bad_Opcode }, |
5901 | { Bad_Opcode }, | |
bf890a93 | 5902 | { "vfmsub132p%XW", { XM, Vex, EXx }, 0 }, |
a5ff0eb2 L |
5903 | }, |
5904 | ||
592a252b | 5905 | /* PREFIX_VEX_0F389B */ |
c0f3af97 | 5906 | { |
592d1631 L |
5907 | { Bad_Opcode }, |
5908 | { Bad_Opcode }, | |
bf890a93 | 5909 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
5910 | }, |
5911 | ||
592a252b | 5912 | /* PREFIX_VEX_0F389C */ |
c0f3af97 | 5913 | { |
592d1631 L |
5914 | { Bad_Opcode }, |
5915 | { Bad_Opcode }, | |
6df22cf6 | 5916 | { "vfnmadd132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5917 | }, |
5918 | ||
592a252b | 5919 | /* PREFIX_VEX_0F389D */ |
c0f3af97 | 5920 | { |
592d1631 L |
5921 | { Bad_Opcode }, |
5922 | { Bad_Opcode }, | |
6df22cf6 | 5923 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5924 | }, |
5925 | ||
592a252b | 5926 | /* PREFIX_VEX_0F389E */ |
c0f3af97 | 5927 | { |
592d1631 L |
5928 | { Bad_Opcode }, |
5929 | { Bad_Opcode }, | |
6df22cf6 | 5930 | { "vfnmsub132p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5931 | }, |
5932 | ||
592a252b | 5933 | /* PREFIX_VEX_0F389F */ |
c0f3af97 | 5934 | { |
592d1631 L |
5935 | { Bad_Opcode }, |
5936 | { Bad_Opcode }, | |
6df22cf6 | 5937 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5938 | }, |
5939 | ||
592a252b | 5940 | /* PREFIX_VEX_0F38A6 */ |
c0f3af97 | 5941 | { |
592d1631 L |
5942 | { Bad_Opcode }, |
5943 | { Bad_Opcode }, | |
6df22cf6 | 5944 | { "vfmaddsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
592d1631 | 5945 | { Bad_Opcode }, |
c0f3af97 L |
5946 | }, |
5947 | ||
592a252b | 5948 | /* PREFIX_VEX_0F38A7 */ |
c0f3af97 | 5949 | { |
592d1631 L |
5950 | { Bad_Opcode }, |
5951 | { Bad_Opcode }, | |
6df22cf6 | 5952 | { "vfmsubadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5953 | }, |
5954 | ||
592a252b | 5955 | /* PREFIX_VEX_0F38A8 */ |
c0f3af97 | 5956 | { |
592d1631 L |
5957 | { Bad_Opcode }, |
5958 | { Bad_Opcode }, | |
6df22cf6 | 5959 | { "vfmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5960 | }, |
5961 | ||
592a252b | 5962 | /* PREFIX_VEX_0F38A9 */ |
c0f3af97 | 5963 | { |
592d1631 L |
5964 | { Bad_Opcode }, |
5965 | { Bad_Opcode }, | |
6df22cf6 | 5966 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5967 | }, |
5968 | ||
592a252b | 5969 | /* PREFIX_VEX_0F38AA */ |
c0f3af97 | 5970 | { |
592d1631 L |
5971 | { Bad_Opcode }, |
5972 | { Bad_Opcode }, | |
bf890a93 | 5973 | { "vfmsub213p%XW", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
5974 | }, |
5975 | ||
592a252b | 5976 | /* PREFIX_VEX_0F38AB */ |
c0f3af97 | 5977 | { |
592d1631 L |
5978 | { Bad_Opcode }, |
5979 | { Bad_Opcode }, | |
bf890a93 | 5980 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar }, 0 }, |
c0f3af97 L |
5981 | }, |
5982 | ||
592a252b | 5983 | /* PREFIX_VEX_0F38AC */ |
c0f3af97 | 5984 | { |
592d1631 L |
5985 | { Bad_Opcode }, |
5986 | { Bad_Opcode }, | |
6df22cf6 | 5987 | { "vfnmadd213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
5988 | }, |
5989 | ||
592a252b | 5990 | /* PREFIX_VEX_0F38AD */ |
c0f3af97 | 5991 | { |
592d1631 L |
5992 | { Bad_Opcode }, |
5993 | { Bad_Opcode }, | |
6df22cf6 | 5994 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
5995 | }, |
5996 | ||
592a252b | 5997 | /* PREFIX_VEX_0F38AE */ |
c0f3af97 | 5998 | { |
592d1631 L |
5999 | { Bad_Opcode }, |
6000 | { Bad_Opcode }, | |
6df22cf6 | 6001 | { "vfnmsub213p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6002 | }, |
6003 | ||
592a252b | 6004 | /* PREFIX_VEX_0F38AF */ |
c0f3af97 | 6005 | { |
592d1631 L |
6006 | { Bad_Opcode }, |
6007 | { Bad_Opcode }, | |
6df22cf6 | 6008 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6009 | }, |
6010 | ||
592a252b | 6011 | /* PREFIX_VEX_0F38B6 */ |
c0f3af97 | 6012 | { |
592d1631 L |
6013 | { Bad_Opcode }, |
6014 | { Bad_Opcode }, | |
6df22cf6 | 6015 | { "vfmaddsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6016 | }, |
6017 | ||
592a252b | 6018 | /* PREFIX_VEX_0F38B7 */ |
c0f3af97 | 6019 | { |
592d1631 L |
6020 | { Bad_Opcode }, |
6021 | { Bad_Opcode }, | |
6df22cf6 | 6022 | { "vfmsubadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6023 | }, |
6024 | ||
592a252b | 6025 | /* PREFIX_VEX_0F38B8 */ |
c0f3af97 | 6026 | { |
592d1631 L |
6027 | { Bad_Opcode }, |
6028 | { Bad_Opcode }, | |
6df22cf6 | 6029 | { "vfmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6030 | }, |
6031 | ||
592a252b | 6032 | /* PREFIX_VEX_0F38B9 */ |
c0f3af97 | 6033 | { |
592d1631 L |
6034 | { Bad_Opcode }, |
6035 | { Bad_Opcode }, | |
6df22cf6 | 6036 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6037 | }, |
6038 | ||
592a252b | 6039 | /* PREFIX_VEX_0F38BA */ |
c0f3af97 | 6040 | { |
592d1631 L |
6041 | { Bad_Opcode }, |
6042 | { Bad_Opcode }, | |
6df22cf6 | 6043 | { "vfmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6044 | }, |
6045 | ||
592a252b | 6046 | /* PREFIX_VEX_0F38BB */ |
c0f3af97 | 6047 | { |
592d1631 L |
6048 | { Bad_Opcode }, |
6049 | { Bad_Opcode }, | |
6df22cf6 | 6050 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6051 | }, |
6052 | ||
592a252b | 6053 | /* PREFIX_VEX_0F38BC */ |
c0f3af97 | 6054 | { |
592d1631 L |
6055 | { Bad_Opcode }, |
6056 | { Bad_Opcode }, | |
6df22cf6 | 6057 | { "vfnmadd231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6058 | }, |
6059 | ||
592a252b | 6060 | /* PREFIX_VEX_0F38BD */ |
c0f3af97 | 6061 | { |
592d1631 L |
6062 | { Bad_Opcode }, |
6063 | { Bad_Opcode }, | |
6df22cf6 | 6064 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6065 | }, |
6066 | ||
592a252b | 6067 | /* PREFIX_VEX_0F38BE */ |
c0f3af97 | 6068 | { |
592d1631 L |
6069 | { Bad_Opcode }, |
6070 | { Bad_Opcode }, | |
6df22cf6 | 6071 | { "vfnmsub231p%XW", { XM, Vex, EXx, EXxEVexR }, 0 }, |
c0f3af97 L |
6072 | }, |
6073 | ||
592a252b | 6074 | /* PREFIX_VEX_0F38BF */ |
c0f3af97 | 6075 | { |
592d1631 L |
6076 | { Bad_Opcode }, |
6077 | { Bad_Opcode }, | |
6df22cf6 | 6078 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXVexWdqScalar, EXxEVexR }, 0 }, |
c0f3af97 L |
6079 | }, |
6080 | ||
48521003 IT |
6081 | /* PREFIX_VEX_0F38CF */ |
6082 | { | |
6083 | { Bad_Opcode }, | |
6084 | { Bad_Opcode }, | |
6085 | { VEX_W_TABLE (VEX_W_0F38CF_P_2) }, | |
6086 | }, | |
6087 | ||
592a252b | 6088 | /* PREFIX_VEX_0F38DB */ |
c0f3af97 | 6089 | { |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
592a252b | 6092 | { VEX_LEN_TABLE (VEX_LEN_0F38DB_P_2) }, |
c0f3af97 L |
6093 | }, |
6094 | ||
592a252b | 6095 | /* PREFIX_VEX_0F38DC */ |
c0f3af97 | 6096 | { |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
8dcf1fad | 6099 | { "vaesenc", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6100 | }, |
6101 | ||
592a252b | 6102 | /* PREFIX_VEX_0F38DD */ |
c0f3af97 | 6103 | { |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
8dcf1fad | 6106 | { "vaesenclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6107 | }, |
6108 | ||
592a252b | 6109 | /* PREFIX_VEX_0F38DE */ |
c0f3af97 | 6110 | { |
592d1631 L |
6111 | { Bad_Opcode }, |
6112 | { Bad_Opcode }, | |
8dcf1fad | 6113 | { "vaesdec", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6114 | }, |
6115 | ||
592a252b | 6116 | /* PREFIX_VEX_0F38DF */ |
c0f3af97 | 6117 | { |
592d1631 L |
6118 | { Bad_Opcode }, |
6119 | { Bad_Opcode }, | |
8dcf1fad | 6120 | { "vaesdeclast", { XM, Vex, EXx }, 0 }, |
c0f3af97 L |
6121 | }, |
6122 | ||
f12dc422 L |
6123 | /* PREFIX_VEX_0F38F2 */ |
6124 | { | |
6125 | { VEX_LEN_TABLE (VEX_LEN_0F38F2_P_0) }, | |
6126 | }, | |
6127 | ||
6128 | /* PREFIX_VEX_0F38F3_REG_1 */ | |
6129 | { | |
6130 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_1_P_0) }, | |
6131 | }, | |
6132 | ||
6133 | /* PREFIX_VEX_0F38F3_REG_2 */ | |
6134 | { | |
6135 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_2_P_0) }, | |
6136 | }, | |
6137 | ||
6138 | /* PREFIX_VEX_0F38F3_REG_3 */ | |
6139 | { | |
6140 | { VEX_LEN_TABLE (VEX_LEN_0F38F3_R_3_P_0) }, | |
6141 | }, | |
6142 | ||
6c30d220 L |
6143 | /* PREFIX_VEX_0F38F5 */ |
6144 | { | |
6145 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_0) }, | |
6146 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_1) }, | |
6147 | { Bad_Opcode }, | |
6148 | { VEX_LEN_TABLE (VEX_LEN_0F38F5_P_3) }, | |
6149 | }, | |
6150 | ||
6151 | /* PREFIX_VEX_0F38F6 */ | |
6152 | { | |
6153 | { Bad_Opcode }, | |
6154 | { Bad_Opcode }, | |
6155 | { Bad_Opcode }, | |
6156 | { VEX_LEN_TABLE (VEX_LEN_0F38F6_P_3) }, | |
6157 | }, | |
6158 | ||
f12dc422 L |
6159 | /* PREFIX_VEX_0F38F7 */ |
6160 | { | |
6161 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_0) }, | |
6c30d220 L |
6162 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_1) }, |
6163 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_2) }, | |
6164 | { VEX_LEN_TABLE (VEX_LEN_0F38F7_P_3) }, | |
6165 | }, | |
6166 | ||
6167 | /* PREFIX_VEX_0F3A00 */ | |
6168 | { | |
6169 | { Bad_Opcode }, | |
6170 | { Bad_Opcode }, | |
6171 | { VEX_LEN_TABLE (VEX_LEN_0F3A00_P_2) }, | |
6172 | }, | |
6173 | ||
6174 | /* PREFIX_VEX_0F3A01 */ | |
6175 | { | |
6176 | { Bad_Opcode }, | |
6177 | { Bad_Opcode }, | |
6178 | { VEX_LEN_TABLE (VEX_LEN_0F3A01_P_2) }, | |
6179 | }, | |
6180 | ||
6181 | /* PREFIX_VEX_0F3A02 */ | |
6182 | { | |
6183 | { Bad_Opcode }, | |
6184 | { Bad_Opcode }, | |
6185 | { VEX_W_TABLE (VEX_W_0F3A02_P_2) }, | |
f12dc422 L |
6186 | }, |
6187 | ||
592a252b | 6188 | /* PREFIX_VEX_0F3A04 */ |
c0f3af97 | 6189 | { |
592d1631 L |
6190 | { Bad_Opcode }, |
6191 | { Bad_Opcode }, | |
592a252b | 6192 | { VEX_W_TABLE (VEX_W_0F3A04_P_2) }, |
c0f3af97 L |
6193 | }, |
6194 | ||
592a252b | 6195 | /* PREFIX_VEX_0F3A05 */ |
c0f3af97 | 6196 | { |
592d1631 L |
6197 | { Bad_Opcode }, |
6198 | { Bad_Opcode }, | |
592a252b | 6199 | { VEX_W_TABLE (VEX_W_0F3A05_P_2) }, |
c0f3af97 L |
6200 | }, |
6201 | ||
592a252b | 6202 | /* PREFIX_VEX_0F3A06 */ |
c0f3af97 | 6203 | { |
592d1631 L |
6204 | { Bad_Opcode }, |
6205 | { Bad_Opcode }, | |
592a252b | 6206 | { VEX_LEN_TABLE (VEX_LEN_0F3A06_P_2) }, |
c0f3af97 L |
6207 | }, |
6208 | ||
592a252b | 6209 | /* PREFIX_VEX_0F3A08 */ |
c0f3af97 | 6210 | { |
592d1631 L |
6211 | { Bad_Opcode }, |
6212 | { Bad_Opcode }, | |
ec6f095a | 6213 | { "vroundps", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6214 | }, |
6215 | ||
592a252b | 6216 | /* PREFIX_VEX_0F3A09 */ |
c0f3af97 | 6217 | { |
592d1631 L |
6218 | { Bad_Opcode }, |
6219 | { Bad_Opcode }, | |
ec6f095a | 6220 | { "vroundpd", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
6221 | }, |
6222 | ||
592a252b | 6223 | /* PREFIX_VEX_0F3A0A */ |
c0f3af97 | 6224 | { |
592d1631 L |
6225 | { Bad_Opcode }, |
6226 | { Bad_Opcode }, | |
5b872f7d | 6227 | { "vroundss", { XMScalar, VexScalar, EXxmm_md, Ib }, 0 }, |
0bfee649 L |
6228 | }, |
6229 | ||
592a252b | 6230 | /* PREFIX_VEX_0F3A0B */ |
0bfee649 | 6231 | { |
592d1631 L |
6232 | { Bad_Opcode }, |
6233 | { Bad_Opcode }, | |
5b872f7d | 6234 | { "vroundsd", { XMScalar, VexScalar, EXxmm_mq, Ib }, 0 }, |
0bfee649 L |
6235 | }, |
6236 | ||
592a252b | 6237 | /* PREFIX_VEX_0F3A0C */ |
0bfee649 | 6238 | { |
592d1631 L |
6239 | { Bad_Opcode }, |
6240 | { Bad_Opcode }, | |
ec6f095a | 6241 | { "vblendps", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6242 | }, |
6243 | ||
592a252b | 6244 | /* PREFIX_VEX_0F3A0D */ |
0bfee649 | 6245 | { |
592d1631 L |
6246 | { Bad_Opcode }, |
6247 | { Bad_Opcode }, | |
ec6f095a | 6248 | { "vblendpd", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6249 | }, |
6250 | ||
592a252b | 6251 | /* PREFIX_VEX_0F3A0E */ |
0bfee649 | 6252 | { |
592d1631 L |
6253 | { Bad_Opcode }, |
6254 | { Bad_Opcode }, | |
ec6f095a | 6255 | { "vpblendw", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6256 | }, |
6257 | ||
592a252b | 6258 | /* PREFIX_VEX_0F3A0F */ |
0bfee649 | 6259 | { |
592d1631 L |
6260 | { Bad_Opcode }, |
6261 | { Bad_Opcode }, | |
ec6f095a | 6262 | { "vpalignr", { XM, Vex, EXx, Ib }, 0 }, |
0bfee649 L |
6263 | }, |
6264 | ||
592a252b | 6265 | /* PREFIX_VEX_0F3A14 */ |
0bfee649 | 6266 | { |
592d1631 L |
6267 | { Bad_Opcode }, |
6268 | { Bad_Opcode }, | |
592a252b | 6269 | { VEX_LEN_TABLE (VEX_LEN_0F3A14_P_2) }, |
0bfee649 L |
6270 | }, |
6271 | ||
592a252b | 6272 | /* PREFIX_VEX_0F3A15 */ |
0bfee649 | 6273 | { |
592d1631 L |
6274 | { Bad_Opcode }, |
6275 | { Bad_Opcode }, | |
592a252b | 6276 | { VEX_LEN_TABLE (VEX_LEN_0F3A15_P_2) }, |
0bfee649 L |
6277 | }, |
6278 | ||
592a252b | 6279 | /* PREFIX_VEX_0F3A16 */ |
c0f3af97 | 6280 | { |
592d1631 L |
6281 | { Bad_Opcode }, |
6282 | { Bad_Opcode }, | |
592a252b | 6283 | { VEX_LEN_TABLE (VEX_LEN_0F3A16_P_2) }, |
c0f3af97 L |
6284 | }, |
6285 | ||
592a252b | 6286 | /* PREFIX_VEX_0F3A17 */ |
c0f3af97 | 6287 | { |
592d1631 L |
6288 | { Bad_Opcode }, |
6289 | { Bad_Opcode }, | |
592a252b | 6290 | { VEX_LEN_TABLE (VEX_LEN_0F3A17_P_2) }, |
c0f3af97 L |
6291 | }, |
6292 | ||
592a252b | 6293 | /* PREFIX_VEX_0F3A18 */ |
c0f3af97 | 6294 | { |
592d1631 L |
6295 | { Bad_Opcode }, |
6296 | { Bad_Opcode }, | |
592a252b | 6297 | { VEX_LEN_TABLE (VEX_LEN_0F3A18_P_2) }, |
c0f3af97 L |
6298 | }, |
6299 | ||
592a252b | 6300 | /* PREFIX_VEX_0F3A19 */ |
c0f3af97 | 6301 | { |
592d1631 L |
6302 | { Bad_Opcode }, |
6303 | { Bad_Opcode }, | |
592a252b | 6304 | { VEX_LEN_TABLE (VEX_LEN_0F3A19_P_2) }, |
c0f3af97 L |
6305 | }, |
6306 | ||
592a252b | 6307 | /* PREFIX_VEX_0F3A1D */ |
c7b8aa3a L |
6308 | { |
6309 | { Bad_Opcode }, | |
6310 | { Bad_Opcode }, | |
6431c801 | 6311 | { VEX_W_TABLE (VEX_W_0F3A1D_P_2) }, |
c7b8aa3a L |
6312 | }, |
6313 | ||
592a252b | 6314 | /* PREFIX_VEX_0F3A20 */ |
c0f3af97 | 6315 | { |
592d1631 L |
6316 | { Bad_Opcode }, |
6317 | { Bad_Opcode }, | |
592a252b | 6318 | { VEX_LEN_TABLE (VEX_LEN_0F3A20_P_2) }, |
c0f3af97 L |
6319 | }, |
6320 | ||
592a252b | 6321 | /* PREFIX_VEX_0F3A21 */ |
c0f3af97 | 6322 | { |
592d1631 L |
6323 | { Bad_Opcode }, |
6324 | { Bad_Opcode }, | |
592a252b | 6325 | { VEX_LEN_TABLE (VEX_LEN_0F3A21_P_2) }, |
c0f3af97 L |
6326 | }, |
6327 | ||
592a252b | 6328 | /* PREFIX_VEX_0F3A22 */ |
0bfee649 | 6329 | { |
592d1631 L |
6330 | { Bad_Opcode }, |
6331 | { Bad_Opcode }, | |
592a252b | 6332 | { VEX_LEN_TABLE (VEX_LEN_0F3A22_P_2) }, |
0bfee649 L |
6333 | }, |
6334 | ||
43234a1e L |
6335 | /* PREFIX_VEX_0F3A30 */ |
6336 | { | |
6337 | { Bad_Opcode }, | |
6338 | { Bad_Opcode }, | |
6339 | { VEX_LEN_TABLE (VEX_LEN_0F3A30_P_2) }, | |
6340 | }, | |
6341 | ||
1ba585e8 IT |
6342 | /* PREFIX_VEX_0F3A31 */ |
6343 | { | |
6344 | { Bad_Opcode }, | |
6345 | { Bad_Opcode }, | |
6346 | { VEX_LEN_TABLE (VEX_LEN_0F3A31_P_2) }, | |
6347 | }, | |
6348 | ||
43234a1e L |
6349 | /* PREFIX_VEX_0F3A32 */ |
6350 | { | |
6351 | { Bad_Opcode }, | |
6352 | { Bad_Opcode }, | |
6353 | { VEX_LEN_TABLE (VEX_LEN_0F3A32_P_2) }, | |
6354 | }, | |
6355 | ||
1ba585e8 IT |
6356 | /* PREFIX_VEX_0F3A33 */ |
6357 | { | |
6358 | { Bad_Opcode }, | |
6359 | { Bad_Opcode }, | |
6360 | { VEX_LEN_TABLE (VEX_LEN_0F3A33_P_2) }, | |
6361 | }, | |
6362 | ||
6c30d220 L |
6363 | /* PREFIX_VEX_0F3A38 */ |
6364 | { | |
6365 | { Bad_Opcode }, | |
6366 | { Bad_Opcode }, | |
6367 | { VEX_LEN_TABLE (VEX_LEN_0F3A38_P_2) }, | |
6368 | }, | |
6369 | ||
6370 | /* PREFIX_VEX_0F3A39 */ | |
6371 | { | |
6372 | { Bad_Opcode }, | |
6373 | { Bad_Opcode }, | |
6374 | { VEX_LEN_TABLE (VEX_LEN_0F3A39_P_2) }, | |
6375 | }, | |
6376 | ||
592a252b | 6377 | /* PREFIX_VEX_0F3A40 */ |
c0f3af97 | 6378 | { |
592d1631 L |
6379 | { Bad_Opcode }, |
6380 | { Bad_Opcode }, | |
ec6f095a | 6381 | { "vdpps", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6382 | }, |
6383 | ||
592a252b | 6384 | /* PREFIX_VEX_0F3A41 */ |
c0f3af97 | 6385 | { |
592d1631 L |
6386 | { Bad_Opcode }, |
6387 | { Bad_Opcode }, | |
592a252b | 6388 | { VEX_LEN_TABLE (VEX_LEN_0F3A41_P_2) }, |
c0f3af97 L |
6389 | }, |
6390 | ||
592a252b | 6391 | /* PREFIX_VEX_0F3A42 */ |
c0f3af97 | 6392 | { |
592d1631 L |
6393 | { Bad_Opcode }, |
6394 | { Bad_Opcode }, | |
ec6f095a | 6395 | { "vmpsadbw", { XM, Vex, EXx, Ib }, 0 }, |
c0f3af97 L |
6396 | }, |
6397 | ||
592a252b | 6398 | /* PREFIX_VEX_0F3A44 */ |
ce2f5b3c | 6399 | { |
592d1631 L |
6400 | { Bad_Opcode }, |
6401 | { Bad_Opcode }, | |
ff1982d5 | 6402 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, 0 }, |
ce2f5b3c L |
6403 | }, |
6404 | ||
6c30d220 L |
6405 | /* PREFIX_VEX_0F3A46 */ |
6406 | { | |
6407 | { Bad_Opcode }, | |
6408 | { Bad_Opcode }, | |
6409 | { VEX_LEN_TABLE (VEX_LEN_0F3A46_P_2) }, | |
6410 | }, | |
6411 | ||
592a252b | 6412 | /* PREFIX_VEX_0F3A48 */ |
a683cc34 SP |
6413 | { |
6414 | { Bad_Opcode }, | |
6415 | { Bad_Opcode }, | |
592a252b | 6416 | { VEX_W_TABLE (VEX_W_0F3A48_P_2) }, |
a683cc34 SP |
6417 | }, |
6418 | ||
592a252b | 6419 | /* PREFIX_VEX_0F3A49 */ |
a683cc34 SP |
6420 | { |
6421 | { Bad_Opcode }, | |
6422 | { Bad_Opcode }, | |
592a252b | 6423 | { VEX_W_TABLE (VEX_W_0F3A49_P_2) }, |
a683cc34 SP |
6424 | }, |
6425 | ||
592a252b | 6426 | /* PREFIX_VEX_0F3A4A */ |
c0f3af97 | 6427 | { |
592d1631 L |
6428 | { Bad_Opcode }, |
6429 | { Bad_Opcode }, | |
592a252b | 6430 | { VEX_W_TABLE (VEX_W_0F3A4A_P_2) }, |
c0f3af97 L |
6431 | }, |
6432 | ||
592a252b | 6433 | /* PREFIX_VEX_0F3A4B */ |
c0f3af97 | 6434 | { |
592d1631 L |
6435 | { Bad_Opcode }, |
6436 | { Bad_Opcode }, | |
592a252b | 6437 | { VEX_W_TABLE (VEX_W_0F3A4B_P_2) }, |
c0f3af97 L |
6438 | }, |
6439 | ||
592a252b | 6440 | /* PREFIX_VEX_0F3A4C */ |
c0f3af97 | 6441 | { |
592d1631 L |
6442 | { Bad_Opcode }, |
6443 | { Bad_Opcode }, | |
6c30d220 | 6444 | { VEX_W_TABLE (VEX_W_0F3A4C_P_2) }, |
c0f3af97 L |
6445 | }, |
6446 | ||
592a252b | 6447 | /* PREFIX_VEX_0F3A5C */ |
922d8de8 | 6448 | { |
592d1631 L |
6449 | { Bad_Opcode }, |
6450 | { Bad_Opcode }, | |
b13b1bc0 | 6451 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6452 | }, |
6453 | ||
592a252b | 6454 | /* PREFIX_VEX_0F3A5D */ |
922d8de8 | 6455 | { |
592d1631 L |
6456 | { Bad_Opcode }, |
6457 | { Bad_Opcode }, | |
b13b1bc0 | 6458 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6459 | }, |
6460 | ||
592a252b | 6461 | /* PREFIX_VEX_0F3A5E */ |
922d8de8 | 6462 | { |
592d1631 L |
6463 | { Bad_Opcode }, |
6464 | { Bad_Opcode }, | |
b13b1bc0 | 6465 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6466 | }, |
6467 | ||
592a252b | 6468 | /* PREFIX_VEX_0F3A5F */ |
922d8de8 | 6469 | { |
592d1631 L |
6470 | { Bad_Opcode }, |
6471 | { Bad_Opcode }, | |
b13b1bc0 | 6472 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6473 | }, |
6474 | ||
592a252b | 6475 | /* PREFIX_VEX_0F3A60 */ |
c0f3af97 | 6476 | { |
592d1631 L |
6477 | { Bad_Opcode }, |
6478 | { Bad_Opcode }, | |
592a252b | 6479 | { VEX_LEN_TABLE (VEX_LEN_0F3A60_P_2) }, |
592d1631 | 6480 | { Bad_Opcode }, |
c0f3af97 L |
6481 | }, |
6482 | ||
592a252b | 6483 | /* PREFIX_VEX_0F3A61 */ |
c0f3af97 | 6484 | { |
592d1631 L |
6485 | { Bad_Opcode }, |
6486 | { Bad_Opcode }, | |
592a252b | 6487 | { VEX_LEN_TABLE (VEX_LEN_0F3A61_P_2) }, |
c0f3af97 L |
6488 | }, |
6489 | ||
592a252b | 6490 | /* PREFIX_VEX_0F3A62 */ |
c0f3af97 | 6491 | { |
592d1631 L |
6492 | { Bad_Opcode }, |
6493 | { Bad_Opcode }, | |
592a252b | 6494 | { VEX_LEN_TABLE (VEX_LEN_0F3A62_P_2) }, |
c0f3af97 L |
6495 | }, |
6496 | ||
592a252b | 6497 | /* PREFIX_VEX_0F3A63 */ |
c0f3af97 | 6498 | { |
592d1631 L |
6499 | { Bad_Opcode }, |
6500 | { Bad_Opcode }, | |
592a252b | 6501 | { VEX_LEN_TABLE (VEX_LEN_0F3A63_P_2) }, |
c0f3af97 | 6502 | }, |
a5ff0eb2 | 6503 | |
592a252b | 6504 | /* PREFIX_VEX_0F3A68 */ |
922d8de8 | 6505 | { |
592d1631 L |
6506 | { Bad_Opcode }, |
6507 | { Bad_Opcode }, | |
b13b1bc0 | 6508 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6509 | }, |
6510 | ||
592a252b | 6511 | /* PREFIX_VEX_0F3A69 */ |
922d8de8 | 6512 | { |
592d1631 L |
6513 | { Bad_Opcode }, |
6514 | { Bad_Opcode }, | |
b13b1bc0 | 6515 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6516 | }, |
6517 | ||
592a252b | 6518 | /* PREFIX_VEX_0F3A6A */ |
922d8de8 | 6519 | { |
592d1631 L |
6520 | { Bad_Opcode }, |
6521 | { Bad_Opcode }, | |
592a252b | 6522 | { VEX_LEN_TABLE (VEX_LEN_0F3A6A_P_2) }, |
922d8de8 DR |
6523 | }, |
6524 | ||
592a252b | 6525 | /* PREFIX_VEX_0F3A6B */ |
922d8de8 | 6526 | { |
592d1631 L |
6527 | { Bad_Opcode }, |
6528 | { Bad_Opcode }, | |
592a252b | 6529 | { VEX_LEN_TABLE (VEX_LEN_0F3A6B_P_2) }, |
922d8de8 DR |
6530 | }, |
6531 | ||
592a252b | 6532 | /* PREFIX_VEX_0F3A6C */ |
922d8de8 | 6533 | { |
592d1631 L |
6534 | { Bad_Opcode }, |
6535 | { Bad_Opcode }, | |
b13b1bc0 | 6536 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6537 | }, |
6538 | ||
592a252b | 6539 | /* PREFIX_VEX_0F3A6D */ |
922d8de8 | 6540 | { |
592d1631 L |
6541 | { Bad_Opcode }, |
6542 | { Bad_Opcode }, | |
b13b1bc0 | 6543 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6544 | }, |
6545 | ||
592a252b | 6546 | /* PREFIX_VEX_0F3A6E */ |
922d8de8 | 6547 | { |
592d1631 L |
6548 | { Bad_Opcode }, |
6549 | { Bad_Opcode }, | |
592a252b | 6550 | { VEX_LEN_TABLE (VEX_LEN_0F3A6E_P_2) }, |
922d8de8 DR |
6551 | }, |
6552 | ||
592a252b | 6553 | /* PREFIX_VEX_0F3A6F */ |
922d8de8 | 6554 | { |
592d1631 L |
6555 | { Bad_Opcode }, |
6556 | { Bad_Opcode }, | |
592a252b | 6557 | { VEX_LEN_TABLE (VEX_LEN_0F3A6F_P_2) }, |
922d8de8 DR |
6558 | }, |
6559 | ||
592a252b | 6560 | /* PREFIX_VEX_0F3A78 */ |
922d8de8 | 6561 | { |
592d1631 L |
6562 | { Bad_Opcode }, |
6563 | { Bad_Opcode }, | |
b13b1bc0 | 6564 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6565 | }, |
6566 | ||
592a252b | 6567 | /* PREFIX_VEX_0F3A79 */ |
922d8de8 | 6568 | { |
592d1631 L |
6569 | { Bad_Opcode }, |
6570 | { Bad_Opcode }, | |
b13b1bc0 | 6571 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6572 | }, |
6573 | ||
592a252b | 6574 | /* PREFIX_VEX_0F3A7A */ |
922d8de8 | 6575 | { |
592d1631 L |
6576 | { Bad_Opcode }, |
6577 | { Bad_Opcode }, | |
592a252b | 6578 | { VEX_LEN_TABLE (VEX_LEN_0F3A7A_P_2) }, |
922d8de8 DR |
6579 | }, |
6580 | ||
592a252b | 6581 | /* PREFIX_VEX_0F3A7B */ |
922d8de8 | 6582 | { |
592d1631 L |
6583 | { Bad_Opcode }, |
6584 | { Bad_Opcode }, | |
592a252b | 6585 | { VEX_LEN_TABLE (VEX_LEN_0F3A7B_P_2) }, |
922d8de8 DR |
6586 | }, |
6587 | ||
592a252b | 6588 | /* PREFIX_VEX_0F3A7C */ |
922d8de8 | 6589 | { |
592d1631 L |
6590 | { Bad_Opcode }, |
6591 | { Bad_Opcode }, | |
b13b1bc0 | 6592 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
592d1631 | 6593 | { Bad_Opcode }, |
922d8de8 DR |
6594 | }, |
6595 | ||
592a252b | 6596 | /* PREFIX_VEX_0F3A7D */ |
922d8de8 | 6597 | { |
592d1631 L |
6598 | { Bad_Opcode }, |
6599 | { Bad_Opcode }, | |
b13b1bc0 | 6600 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
922d8de8 DR |
6601 | }, |
6602 | ||
592a252b | 6603 | /* PREFIX_VEX_0F3A7E */ |
922d8de8 | 6604 | { |
592d1631 L |
6605 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, | |
592a252b | 6607 | { VEX_LEN_TABLE (VEX_LEN_0F3A7E_P_2) }, |
922d8de8 DR |
6608 | }, |
6609 | ||
592a252b | 6610 | /* PREFIX_VEX_0F3A7F */ |
922d8de8 | 6611 | { |
592d1631 L |
6612 | { Bad_Opcode }, |
6613 | { Bad_Opcode }, | |
592a252b | 6614 | { VEX_LEN_TABLE (VEX_LEN_0F3A7F_P_2) }, |
922d8de8 DR |
6615 | }, |
6616 | ||
48521003 IT |
6617 | /* PREFIX_VEX_0F3ACE */ |
6618 | { | |
6619 | { Bad_Opcode }, | |
6620 | { Bad_Opcode }, | |
6621 | { VEX_W_TABLE (VEX_W_0F3ACE_P_2) }, | |
6622 | }, | |
6623 | ||
6624 | /* PREFIX_VEX_0F3ACF */ | |
6625 | { | |
6626 | { Bad_Opcode }, | |
6627 | { Bad_Opcode }, | |
6628 | { VEX_W_TABLE (VEX_W_0F3ACF_P_2) }, | |
6629 | }, | |
6630 | ||
592a252b | 6631 | /* PREFIX_VEX_0F3ADF */ |
a5ff0eb2 | 6632 | { |
592d1631 L |
6633 | { Bad_Opcode }, |
6634 | { Bad_Opcode }, | |
592a252b | 6635 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF_P_2) }, |
a5ff0eb2 | 6636 | }, |
6c30d220 L |
6637 | |
6638 | /* PREFIX_VEX_0F3AF0 */ | |
6639 | { | |
6640 | { Bad_Opcode }, | |
6641 | { Bad_Opcode }, | |
6642 | { Bad_Opcode }, | |
6643 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0_P_3) }, | |
6644 | }, | |
43234a1e | 6645 | |
ad692897 | 6646 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
6647 | }; |
6648 | ||
6649 | static const struct dis386 x86_64_table[][2] = { | |
6650 | /* X86_64_06 */ | |
6651 | { | |
bf890a93 | 6652 | { "pushP", { es }, 0 }, |
c0f3af97 L |
6653 | }, |
6654 | ||
6655 | /* X86_64_07 */ | |
6656 | { | |
bf890a93 | 6657 | { "popP", { es }, 0 }, |
c0f3af97 L |
6658 | }, |
6659 | ||
1673df32 | 6660 | /* X86_64_0E */ |
c0f3af97 | 6661 | { |
bf890a93 | 6662 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
6663 | }, |
6664 | ||
6665 | /* X86_64_16 */ | |
6666 | { | |
bf890a93 | 6667 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
6668 | }, |
6669 | ||
6670 | /* X86_64_17 */ | |
6671 | { | |
bf890a93 | 6672 | { "popP", { ss }, 0 }, |
c0f3af97 L |
6673 | }, |
6674 | ||
6675 | /* X86_64_1E */ | |
6676 | { | |
bf890a93 | 6677 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
6678 | }, |
6679 | ||
6680 | /* X86_64_1F */ | |
6681 | { | |
bf890a93 | 6682 | { "popP", { ds }, 0 }, |
c0f3af97 L |
6683 | }, |
6684 | ||
6685 | /* X86_64_27 */ | |
6686 | { | |
bf890a93 | 6687 | { "daa", { XX }, 0 }, |
c0f3af97 L |
6688 | }, |
6689 | ||
6690 | /* X86_64_2F */ | |
6691 | { | |
bf890a93 | 6692 | { "das", { XX }, 0 }, |
c0f3af97 L |
6693 | }, |
6694 | ||
6695 | /* X86_64_37 */ | |
6696 | { | |
bf890a93 | 6697 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
6698 | }, |
6699 | ||
6700 | /* X86_64_3F */ | |
6701 | { | |
bf890a93 | 6702 | { "aas", { XX }, 0 }, |
c0f3af97 L |
6703 | }, |
6704 | ||
6705 | /* X86_64_60 */ | |
6706 | { | |
bf890a93 | 6707 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
6708 | }, |
6709 | ||
6710 | /* X86_64_61 */ | |
6711 | { | |
bf890a93 | 6712 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
6713 | }, |
6714 | ||
6715 | /* X86_64_62 */ | |
6716 | { | |
6717 | { MOD_TABLE (MOD_62_32BIT) }, | |
43234a1e | 6718 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
6719 | }, |
6720 | ||
6721 | /* X86_64_63 */ | |
6722 | { | |
bf890a93 | 6723 | { "arpl", { Ew, Gw }, 0 }, |
bc31405e | 6724 | { "movs", { { OP_G, movsxd_mode }, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
6725 | }, |
6726 | ||
6727 | /* X86_64_6D */ | |
6728 | { | |
bf890a93 IT |
6729 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
6730 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
6731 | }, |
6732 | ||
6733 | /* X86_64_6F */ | |
6734 | { | |
bf890a93 IT |
6735 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
6736 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
6737 | }, |
6738 | ||
d039fef3 | 6739 | /* X86_64_82 */ |
8b89fe14 | 6740 | { |
de194d85 | 6741 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 6742 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
6743 | }, |
6744 | ||
c0f3af97 L |
6745 | /* X86_64_9A */ |
6746 | { | |
8f570d62 | 6747 | { "{l|}call{T|}", { Ap }, 0 }, |
c0f3af97 L |
6748 | }, |
6749 | ||
aeab2b26 JB |
6750 | /* X86_64_C2 */ |
6751 | { | |
6752 | { "retP", { Iw, BND }, 0 }, | |
6753 | { "ret@", { Iw, BND }, 0 }, | |
6754 | }, | |
6755 | ||
6756 | /* X86_64_C3 */ | |
6757 | { | |
6758 | { "retP", { BND }, 0 }, | |
6759 | { "ret@", { BND }, 0 }, | |
6760 | }, | |
6761 | ||
c0f3af97 L |
6762 | /* X86_64_C4 */ |
6763 | { | |
6764 | { MOD_TABLE (MOD_C4_32BIT) }, | |
6765 | { VEX_C4_TABLE (VEX_0F) }, | |
6766 | }, | |
6767 | ||
6768 | /* X86_64_C5 */ | |
6769 | { | |
6770 | { MOD_TABLE (MOD_C5_32BIT) }, | |
6771 | { VEX_C5_TABLE (VEX_0F) }, | |
6772 | }, | |
6773 | ||
6774 | /* X86_64_CE */ | |
6775 | { | |
bf890a93 | 6776 | { "into", { XX }, 0 }, |
c0f3af97 L |
6777 | }, |
6778 | ||
6779 | /* X86_64_D4 */ | |
6780 | { | |
bf890a93 | 6781 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
6782 | }, |
6783 | ||
6784 | /* X86_64_D5 */ | |
6785 | { | |
bf890a93 | 6786 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
6787 | }, |
6788 | ||
a72d2af2 L |
6789 | /* X86_64_E8 */ |
6790 | { | |
6791 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 6792 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
6793 | }, |
6794 | ||
6795 | /* X86_64_E9 */ | |
6796 | { | |
6797 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 6798 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
6799 | }, |
6800 | ||
c0f3af97 L |
6801 | /* X86_64_EA */ |
6802 | { | |
8f570d62 | 6803 | { "{l|}jmp{T|}", { Ap }, 0 }, |
c0f3af97 L |
6804 | }, |
6805 | ||
6806 | /* X86_64_0F01_REG_0 */ | |
6807 | { | |
d1c36125 | 6808 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 6809 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
6810 | }, |
6811 | ||
6812 | /* X86_64_0F01_REG_1 */ | |
6813 | { | |
d1c36125 | 6814 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 6815 | { "sidt", { M }, 0 }, |
c0f3af97 L |
6816 | }, |
6817 | ||
6818 | /* X86_64_0F01_REG_2 */ | |
6819 | { | |
bf890a93 IT |
6820 | { "lgdt{Q|Q}", { M }, 0 }, |
6821 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
6822 | }, |
6823 | ||
6824 | /* X86_64_0F01_REG_3 */ | |
6825 | { | |
bf890a93 IT |
6826 | { "lidt{Q|Q}", { M }, 0 }, |
6827 | { "lidt", { M }, 0 }, | |
c0f3af97 L |
6828 | }, |
6829 | }; | |
6830 | ||
6831 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
6832 | |
6833 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
6834 | { |
6835 | /* 00 */ | |
507bd325 L |
6836 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
6837 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
6838 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
6839 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
6840 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
6841 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
6842 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
6843 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 6844 | /* 08 */ |
507bd325 L |
6845 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
6846 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
6847 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
6848 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
6849 | { Bad_Opcode }, |
6850 | { Bad_Opcode }, | |
6851 | { Bad_Opcode }, | |
6852 | { Bad_Opcode }, | |
f88c9eb0 SP |
6853 | /* 10 */ |
6854 | { PREFIX_TABLE (PREFIX_0F3810) }, | |
592d1631 L |
6855 | { Bad_Opcode }, |
6856 | { Bad_Opcode }, | |
6857 | { Bad_Opcode }, | |
f88c9eb0 SP |
6858 | { PREFIX_TABLE (PREFIX_0F3814) }, |
6859 | { PREFIX_TABLE (PREFIX_0F3815) }, | |
592d1631 | 6860 | { Bad_Opcode }, |
f88c9eb0 SP |
6861 | { PREFIX_TABLE (PREFIX_0F3817) }, |
6862 | /* 18 */ | |
592d1631 L |
6863 | { Bad_Opcode }, |
6864 | { Bad_Opcode }, | |
6865 | { Bad_Opcode }, | |
6866 | { Bad_Opcode }, | |
507bd325 L |
6867 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
6868 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
6869 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 6870 | { Bad_Opcode }, |
f88c9eb0 SP |
6871 | /* 20 */ |
6872 | { PREFIX_TABLE (PREFIX_0F3820) }, | |
6873 | { PREFIX_TABLE (PREFIX_0F3821) }, | |
6874 | { PREFIX_TABLE (PREFIX_0F3822) }, | |
6875 | { PREFIX_TABLE (PREFIX_0F3823) }, | |
6876 | { PREFIX_TABLE (PREFIX_0F3824) }, | |
6877 | { PREFIX_TABLE (PREFIX_0F3825) }, | |
592d1631 L |
6878 | { Bad_Opcode }, |
6879 | { Bad_Opcode }, | |
f88c9eb0 SP |
6880 | /* 28 */ |
6881 | { PREFIX_TABLE (PREFIX_0F3828) }, | |
6882 | { PREFIX_TABLE (PREFIX_0F3829) }, | |
6883 | { PREFIX_TABLE (PREFIX_0F382A) }, | |
6884 | { PREFIX_TABLE (PREFIX_0F382B) }, | |
592d1631 L |
6885 | { Bad_Opcode }, |
6886 | { Bad_Opcode }, | |
6887 | { Bad_Opcode }, | |
6888 | { Bad_Opcode }, | |
f88c9eb0 SP |
6889 | /* 30 */ |
6890 | { PREFIX_TABLE (PREFIX_0F3830) }, | |
6891 | { PREFIX_TABLE (PREFIX_0F3831) }, | |
6892 | { PREFIX_TABLE (PREFIX_0F3832) }, | |
6893 | { PREFIX_TABLE (PREFIX_0F3833) }, | |
6894 | { PREFIX_TABLE (PREFIX_0F3834) }, | |
6895 | { PREFIX_TABLE (PREFIX_0F3835) }, | |
592d1631 | 6896 | { Bad_Opcode }, |
f88c9eb0 SP |
6897 | { PREFIX_TABLE (PREFIX_0F3837) }, |
6898 | /* 38 */ | |
6899 | { PREFIX_TABLE (PREFIX_0F3838) }, | |
6900 | { PREFIX_TABLE (PREFIX_0F3839) }, | |
6901 | { PREFIX_TABLE (PREFIX_0F383A) }, | |
6902 | { PREFIX_TABLE (PREFIX_0F383B) }, | |
6903 | { PREFIX_TABLE (PREFIX_0F383C) }, | |
6904 | { PREFIX_TABLE (PREFIX_0F383D) }, | |
6905 | { PREFIX_TABLE (PREFIX_0F383E) }, | |
6906 | { PREFIX_TABLE (PREFIX_0F383F) }, | |
6907 | /* 40 */ | |
6908 | { PREFIX_TABLE (PREFIX_0F3840) }, | |
6909 | { PREFIX_TABLE (PREFIX_0F3841) }, | |
592d1631 L |
6910 | { Bad_Opcode }, |
6911 | { Bad_Opcode }, | |
6912 | { Bad_Opcode }, | |
6913 | { Bad_Opcode }, | |
6914 | { Bad_Opcode }, | |
6915 | { Bad_Opcode }, | |
f88c9eb0 | 6916 | /* 48 */ |
592d1631 L |
6917 | { Bad_Opcode }, |
6918 | { Bad_Opcode }, | |
6919 | { Bad_Opcode }, | |
6920 | { Bad_Opcode }, | |
6921 | { Bad_Opcode }, | |
6922 | { Bad_Opcode }, | |
6923 | { Bad_Opcode }, | |
6924 | { Bad_Opcode }, | |
f88c9eb0 | 6925 | /* 50 */ |
592d1631 L |
6926 | { Bad_Opcode }, |
6927 | { Bad_Opcode }, | |
6928 | { Bad_Opcode }, | |
6929 | { Bad_Opcode }, | |
6930 | { Bad_Opcode }, | |
6931 | { Bad_Opcode }, | |
6932 | { Bad_Opcode }, | |
6933 | { Bad_Opcode }, | |
f88c9eb0 | 6934 | /* 58 */ |
592d1631 L |
6935 | { Bad_Opcode }, |
6936 | { Bad_Opcode }, | |
6937 | { Bad_Opcode }, | |
6938 | { Bad_Opcode }, | |
6939 | { Bad_Opcode }, | |
6940 | { Bad_Opcode }, | |
6941 | { Bad_Opcode }, | |
6942 | { Bad_Opcode }, | |
f88c9eb0 | 6943 | /* 60 */ |
592d1631 L |
6944 | { Bad_Opcode }, |
6945 | { Bad_Opcode }, | |
6946 | { Bad_Opcode }, | |
6947 | { Bad_Opcode }, | |
6948 | { Bad_Opcode }, | |
6949 | { Bad_Opcode }, | |
6950 | { Bad_Opcode }, | |
6951 | { Bad_Opcode }, | |
f88c9eb0 | 6952 | /* 68 */ |
592d1631 L |
6953 | { Bad_Opcode }, |
6954 | { Bad_Opcode }, | |
6955 | { Bad_Opcode }, | |
6956 | { Bad_Opcode }, | |
6957 | { Bad_Opcode }, | |
6958 | { Bad_Opcode }, | |
6959 | { Bad_Opcode }, | |
6960 | { Bad_Opcode }, | |
f88c9eb0 | 6961 | /* 70 */ |
592d1631 L |
6962 | { Bad_Opcode }, |
6963 | { Bad_Opcode }, | |
6964 | { Bad_Opcode }, | |
6965 | { Bad_Opcode }, | |
6966 | { Bad_Opcode }, | |
6967 | { Bad_Opcode }, | |
6968 | { Bad_Opcode }, | |
6969 | { Bad_Opcode }, | |
f88c9eb0 | 6970 | /* 78 */ |
592d1631 L |
6971 | { Bad_Opcode }, |
6972 | { Bad_Opcode }, | |
6973 | { Bad_Opcode }, | |
6974 | { Bad_Opcode }, | |
6975 | { Bad_Opcode }, | |
6976 | { Bad_Opcode }, | |
6977 | { Bad_Opcode }, | |
6978 | { Bad_Opcode }, | |
f88c9eb0 SP |
6979 | /* 80 */ |
6980 | { PREFIX_TABLE (PREFIX_0F3880) }, | |
6981 | { PREFIX_TABLE (PREFIX_0F3881) }, | |
6c30d220 | 6982 | { PREFIX_TABLE (PREFIX_0F3882) }, |
592d1631 L |
6983 | { Bad_Opcode }, |
6984 | { Bad_Opcode }, | |
6985 | { Bad_Opcode }, | |
6986 | { Bad_Opcode }, | |
6987 | { Bad_Opcode }, | |
f88c9eb0 | 6988 | /* 88 */ |
592d1631 L |
6989 | { Bad_Opcode }, |
6990 | { Bad_Opcode }, | |
6991 | { Bad_Opcode }, | |
6992 | { Bad_Opcode }, | |
6993 | { Bad_Opcode }, | |
6994 | { Bad_Opcode }, | |
6995 | { Bad_Opcode }, | |
6996 | { Bad_Opcode }, | |
f88c9eb0 | 6997 | /* 90 */ |
592d1631 L |
6998 | { Bad_Opcode }, |
6999 | { Bad_Opcode }, | |
7000 | { Bad_Opcode }, | |
7001 | { Bad_Opcode }, | |
7002 | { Bad_Opcode }, | |
7003 | { Bad_Opcode }, | |
7004 | { Bad_Opcode }, | |
7005 | { Bad_Opcode }, | |
f88c9eb0 | 7006 | /* 98 */ |
592d1631 L |
7007 | { Bad_Opcode }, |
7008 | { Bad_Opcode }, | |
7009 | { Bad_Opcode }, | |
7010 | { Bad_Opcode }, | |
7011 | { Bad_Opcode }, | |
7012 | { Bad_Opcode }, | |
7013 | { Bad_Opcode }, | |
7014 | { Bad_Opcode }, | |
f88c9eb0 | 7015 | /* a0 */ |
592d1631 L |
7016 | { Bad_Opcode }, |
7017 | { Bad_Opcode }, | |
7018 | { Bad_Opcode }, | |
7019 | { Bad_Opcode }, | |
7020 | { Bad_Opcode }, | |
7021 | { Bad_Opcode }, | |
7022 | { Bad_Opcode }, | |
7023 | { Bad_Opcode }, | |
f88c9eb0 | 7024 | /* a8 */ |
592d1631 L |
7025 | { Bad_Opcode }, |
7026 | { Bad_Opcode }, | |
7027 | { Bad_Opcode }, | |
7028 | { Bad_Opcode }, | |
7029 | { Bad_Opcode }, | |
7030 | { Bad_Opcode }, | |
7031 | { Bad_Opcode }, | |
7032 | { Bad_Opcode }, | |
f88c9eb0 | 7033 | /* b0 */ |
592d1631 L |
7034 | { Bad_Opcode }, |
7035 | { Bad_Opcode }, | |
7036 | { Bad_Opcode }, | |
7037 | { Bad_Opcode }, | |
7038 | { Bad_Opcode }, | |
7039 | { Bad_Opcode }, | |
7040 | { Bad_Opcode }, | |
7041 | { Bad_Opcode }, | |
f88c9eb0 | 7042 | /* b8 */ |
592d1631 L |
7043 | { Bad_Opcode }, |
7044 | { Bad_Opcode }, | |
7045 | { Bad_Opcode }, | |
7046 | { Bad_Opcode }, | |
7047 | { Bad_Opcode }, | |
7048 | { Bad_Opcode }, | |
7049 | { Bad_Opcode }, | |
7050 | { Bad_Opcode }, | |
f88c9eb0 | 7051 | /* c0 */ |
592d1631 L |
7052 | { Bad_Opcode }, |
7053 | { Bad_Opcode }, | |
7054 | { Bad_Opcode }, | |
7055 | { Bad_Opcode }, | |
7056 | { Bad_Opcode }, | |
7057 | { Bad_Opcode }, | |
7058 | { Bad_Opcode }, | |
7059 | { Bad_Opcode }, | |
f88c9eb0 | 7060 | /* c8 */ |
a0046408 L |
7061 | { PREFIX_TABLE (PREFIX_0F38C8) }, |
7062 | { PREFIX_TABLE (PREFIX_0F38C9) }, | |
7063 | { PREFIX_TABLE (PREFIX_0F38CA) }, | |
7064 | { PREFIX_TABLE (PREFIX_0F38CB) }, | |
7065 | { PREFIX_TABLE (PREFIX_0F38CC) }, | |
7066 | { PREFIX_TABLE (PREFIX_0F38CD) }, | |
592d1631 | 7067 | { Bad_Opcode }, |
48521003 | 7068 | { PREFIX_TABLE (PREFIX_0F38CF) }, |
f88c9eb0 | 7069 | /* d0 */ |
592d1631 L |
7070 | { Bad_Opcode }, |
7071 | { Bad_Opcode }, | |
7072 | { Bad_Opcode }, | |
7073 | { Bad_Opcode }, | |
7074 | { Bad_Opcode }, | |
7075 | { Bad_Opcode }, | |
7076 | { Bad_Opcode }, | |
7077 | { Bad_Opcode }, | |
f88c9eb0 | 7078 | /* d8 */ |
592d1631 L |
7079 | { Bad_Opcode }, |
7080 | { Bad_Opcode }, | |
7081 | { Bad_Opcode }, | |
f88c9eb0 SP |
7082 | { PREFIX_TABLE (PREFIX_0F38DB) }, |
7083 | { PREFIX_TABLE (PREFIX_0F38DC) }, | |
7084 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
7085 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
7086 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
7087 | /* e0 */ | |
592d1631 L |
7088 | { Bad_Opcode }, |
7089 | { Bad_Opcode }, | |
7090 | { Bad_Opcode }, | |
7091 | { Bad_Opcode }, | |
7092 | { Bad_Opcode }, | |
7093 | { Bad_Opcode }, | |
7094 | { Bad_Opcode }, | |
7095 | { Bad_Opcode }, | |
f88c9eb0 | 7096 | /* e8 */ |
592d1631 L |
7097 | { Bad_Opcode }, |
7098 | { Bad_Opcode }, | |
7099 | { Bad_Opcode }, | |
7100 | { Bad_Opcode }, | |
7101 | { Bad_Opcode }, | |
7102 | { Bad_Opcode }, | |
7103 | { Bad_Opcode }, | |
7104 | { Bad_Opcode }, | |
f88c9eb0 SP |
7105 | /* f0 */ |
7106 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
7107 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
7108 | { Bad_Opcode }, |
7109 | { Bad_Opcode }, | |
7110 | { Bad_Opcode }, | |
603555e5 | 7111 | { PREFIX_TABLE (PREFIX_0F38F5) }, |
e2e1fcde | 7112 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 7113 | { Bad_Opcode }, |
f88c9eb0 | 7114 | /* f8 */ |
c0a30a9f L |
7115 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
7116 | { PREFIX_TABLE (PREFIX_0F38F9) }, | |
592d1631 L |
7117 | { Bad_Opcode }, |
7118 | { Bad_Opcode }, | |
7119 | { Bad_Opcode }, | |
7120 | { Bad_Opcode }, | |
7121 | { Bad_Opcode }, | |
7122 | { Bad_Opcode }, | |
f88c9eb0 SP |
7123 | }, |
7124 | /* THREE_BYTE_0F3A */ | |
7125 | { | |
7126 | /* 00 */ | |
592d1631 L |
7127 | { Bad_Opcode }, |
7128 | { Bad_Opcode }, | |
7129 | { Bad_Opcode }, | |
7130 | { Bad_Opcode }, | |
7131 | { Bad_Opcode }, | |
7132 | { Bad_Opcode }, | |
7133 | { Bad_Opcode }, | |
7134 | { Bad_Opcode }, | |
f88c9eb0 SP |
7135 | /* 08 */ |
7136 | { PREFIX_TABLE (PREFIX_0F3A08) }, | |
7137 | { PREFIX_TABLE (PREFIX_0F3A09) }, | |
7138 | { PREFIX_TABLE (PREFIX_0F3A0A) }, | |
7139 | { PREFIX_TABLE (PREFIX_0F3A0B) }, | |
7140 | { PREFIX_TABLE (PREFIX_0F3A0C) }, | |
7141 | { PREFIX_TABLE (PREFIX_0F3A0D) }, | |
7142 | { PREFIX_TABLE (PREFIX_0F3A0E) }, | |
507bd325 | 7143 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 7144 | /* 10 */ |
592d1631 L |
7145 | { Bad_Opcode }, |
7146 | { Bad_Opcode }, | |
7147 | { Bad_Opcode }, | |
7148 | { Bad_Opcode }, | |
f88c9eb0 SP |
7149 | { PREFIX_TABLE (PREFIX_0F3A14) }, |
7150 | { PREFIX_TABLE (PREFIX_0F3A15) }, | |
7151 | { PREFIX_TABLE (PREFIX_0F3A16) }, | |
7152 | { PREFIX_TABLE (PREFIX_0F3A17) }, | |
7153 | /* 18 */ | |
592d1631 L |
7154 | { Bad_Opcode }, |
7155 | { Bad_Opcode }, | |
7156 | { Bad_Opcode }, | |
7157 | { Bad_Opcode }, | |
7158 | { Bad_Opcode }, | |
7159 | { Bad_Opcode }, | |
7160 | { Bad_Opcode }, | |
7161 | { Bad_Opcode }, | |
f88c9eb0 SP |
7162 | /* 20 */ |
7163 | { PREFIX_TABLE (PREFIX_0F3A20) }, | |
7164 | { PREFIX_TABLE (PREFIX_0F3A21) }, | |
7165 | { PREFIX_TABLE (PREFIX_0F3A22) }, | |
592d1631 L |
7166 | { Bad_Opcode }, |
7167 | { Bad_Opcode }, | |
7168 | { Bad_Opcode }, | |
7169 | { Bad_Opcode }, | |
7170 | { Bad_Opcode }, | |
f88c9eb0 | 7171 | /* 28 */ |
592d1631 L |
7172 | { Bad_Opcode }, |
7173 | { Bad_Opcode }, | |
7174 | { Bad_Opcode }, | |
7175 | { Bad_Opcode }, | |
7176 | { Bad_Opcode }, | |
7177 | { Bad_Opcode }, | |
7178 | { Bad_Opcode }, | |
7179 | { Bad_Opcode }, | |
f88c9eb0 | 7180 | /* 30 */ |
592d1631 L |
7181 | { Bad_Opcode }, |
7182 | { Bad_Opcode }, | |
7183 | { Bad_Opcode }, | |
7184 | { Bad_Opcode }, | |
7185 | { Bad_Opcode }, | |
7186 | { Bad_Opcode }, | |
7187 | { Bad_Opcode }, | |
7188 | { Bad_Opcode }, | |
f88c9eb0 | 7189 | /* 38 */ |
592d1631 L |
7190 | { Bad_Opcode }, |
7191 | { Bad_Opcode }, | |
7192 | { Bad_Opcode }, | |
7193 | { Bad_Opcode }, | |
7194 | { Bad_Opcode }, | |
7195 | { Bad_Opcode }, | |
7196 | { Bad_Opcode }, | |
7197 | { Bad_Opcode }, | |
f88c9eb0 SP |
7198 | /* 40 */ |
7199 | { PREFIX_TABLE (PREFIX_0F3A40) }, | |
7200 | { PREFIX_TABLE (PREFIX_0F3A41) }, | |
7201 | { PREFIX_TABLE (PREFIX_0F3A42) }, | |
592d1631 | 7202 | { Bad_Opcode }, |
f88c9eb0 | 7203 | { PREFIX_TABLE (PREFIX_0F3A44) }, |
592d1631 L |
7204 | { Bad_Opcode }, |
7205 | { Bad_Opcode }, | |
7206 | { Bad_Opcode }, | |
f88c9eb0 | 7207 | /* 48 */ |
592d1631 L |
7208 | { Bad_Opcode }, |
7209 | { Bad_Opcode }, | |
7210 | { Bad_Opcode }, | |
7211 | { Bad_Opcode }, | |
7212 | { Bad_Opcode }, | |
7213 | { Bad_Opcode }, | |
7214 | { Bad_Opcode }, | |
7215 | { Bad_Opcode }, | |
f88c9eb0 | 7216 | /* 50 */ |
592d1631 L |
7217 | { Bad_Opcode }, |
7218 | { Bad_Opcode }, | |
7219 | { Bad_Opcode }, | |
7220 | { Bad_Opcode }, | |
7221 | { Bad_Opcode }, | |
7222 | { Bad_Opcode }, | |
7223 | { Bad_Opcode }, | |
7224 | { Bad_Opcode }, | |
f88c9eb0 | 7225 | /* 58 */ |
592d1631 L |
7226 | { Bad_Opcode }, |
7227 | { Bad_Opcode }, | |
7228 | { Bad_Opcode }, | |
7229 | { Bad_Opcode }, | |
7230 | { Bad_Opcode }, | |
7231 | { Bad_Opcode }, | |
7232 | { Bad_Opcode }, | |
7233 | { Bad_Opcode }, | |
f88c9eb0 SP |
7234 | /* 60 */ |
7235 | { PREFIX_TABLE (PREFIX_0F3A60) }, | |
7236 | { PREFIX_TABLE (PREFIX_0F3A61) }, | |
7237 | { PREFIX_TABLE (PREFIX_0F3A62) }, | |
7238 | { PREFIX_TABLE (PREFIX_0F3A63) }, | |
592d1631 L |
7239 | { Bad_Opcode }, |
7240 | { Bad_Opcode }, | |
7241 | { Bad_Opcode }, | |
7242 | { Bad_Opcode }, | |
f88c9eb0 | 7243 | /* 68 */ |
592d1631 L |
7244 | { Bad_Opcode }, |
7245 | { Bad_Opcode }, | |
7246 | { Bad_Opcode }, | |
7247 | { Bad_Opcode }, | |
7248 | { Bad_Opcode }, | |
7249 | { Bad_Opcode }, | |
7250 | { Bad_Opcode }, | |
7251 | { Bad_Opcode }, | |
f88c9eb0 | 7252 | /* 70 */ |
592d1631 L |
7253 | { Bad_Opcode }, |
7254 | { Bad_Opcode }, | |
7255 | { Bad_Opcode }, | |
7256 | { Bad_Opcode }, | |
7257 | { Bad_Opcode }, | |
7258 | { Bad_Opcode }, | |
7259 | { Bad_Opcode }, | |
7260 | { Bad_Opcode }, | |
f88c9eb0 | 7261 | /* 78 */ |
592d1631 L |
7262 | { Bad_Opcode }, |
7263 | { Bad_Opcode }, | |
7264 | { Bad_Opcode }, | |
7265 | { Bad_Opcode }, | |
7266 | { Bad_Opcode }, | |
7267 | { Bad_Opcode }, | |
7268 | { Bad_Opcode }, | |
7269 | { Bad_Opcode }, | |
f88c9eb0 | 7270 | /* 80 */ |
592d1631 L |
7271 | { Bad_Opcode }, |
7272 | { Bad_Opcode }, | |
7273 | { Bad_Opcode }, | |
7274 | { Bad_Opcode }, | |
7275 | { Bad_Opcode }, | |
7276 | { Bad_Opcode }, | |
7277 | { Bad_Opcode }, | |
7278 | { Bad_Opcode }, | |
f88c9eb0 | 7279 | /* 88 */ |
592d1631 L |
7280 | { Bad_Opcode }, |
7281 | { Bad_Opcode }, | |
7282 | { Bad_Opcode }, | |
7283 | { Bad_Opcode }, | |
7284 | { Bad_Opcode }, | |
7285 | { Bad_Opcode }, | |
7286 | { Bad_Opcode }, | |
7287 | { Bad_Opcode }, | |
f88c9eb0 | 7288 | /* 90 */ |
592d1631 L |
7289 | { Bad_Opcode }, |
7290 | { Bad_Opcode }, | |
7291 | { Bad_Opcode }, | |
7292 | { Bad_Opcode }, | |
7293 | { Bad_Opcode }, | |
7294 | { Bad_Opcode }, | |
7295 | { Bad_Opcode }, | |
7296 | { Bad_Opcode }, | |
f88c9eb0 | 7297 | /* 98 */ |
592d1631 L |
7298 | { Bad_Opcode }, |
7299 | { Bad_Opcode }, | |
7300 | { Bad_Opcode }, | |
7301 | { Bad_Opcode }, | |
7302 | { Bad_Opcode }, | |
7303 | { Bad_Opcode }, | |
7304 | { Bad_Opcode }, | |
7305 | { Bad_Opcode }, | |
f88c9eb0 | 7306 | /* a0 */ |
592d1631 L |
7307 | { Bad_Opcode }, |
7308 | { Bad_Opcode }, | |
7309 | { Bad_Opcode }, | |
7310 | { Bad_Opcode }, | |
7311 | { Bad_Opcode }, | |
7312 | { Bad_Opcode }, | |
7313 | { Bad_Opcode }, | |
7314 | { Bad_Opcode }, | |
f88c9eb0 | 7315 | /* a8 */ |
592d1631 L |
7316 | { Bad_Opcode }, |
7317 | { Bad_Opcode }, | |
7318 | { Bad_Opcode }, | |
7319 | { Bad_Opcode }, | |
7320 | { Bad_Opcode }, | |
7321 | { Bad_Opcode }, | |
7322 | { Bad_Opcode }, | |
7323 | { Bad_Opcode }, | |
f88c9eb0 | 7324 | /* b0 */ |
592d1631 L |
7325 | { Bad_Opcode }, |
7326 | { Bad_Opcode }, | |
7327 | { Bad_Opcode }, | |
7328 | { Bad_Opcode }, | |
7329 | { Bad_Opcode }, | |
7330 | { Bad_Opcode }, | |
7331 | { Bad_Opcode }, | |
7332 | { Bad_Opcode }, | |
f88c9eb0 | 7333 | /* b8 */ |
592d1631 L |
7334 | { Bad_Opcode }, |
7335 | { Bad_Opcode }, | |
7336 | { Bad_Opcode }, | |
7337 | { Bad_Opcode }, | |
7338 | { Bad_Opcode }, | |
7339 | { Bad_Opcode }, | |
7340 | { Bad_Opcode }, | |
7341 | { Bad_Opcode }, | |
f88c9eb0 | 7342 | /* c0 */ |
592d1631 L |
7343 | { Bad_Opcode }, |
7344 | { Bad_Opcode }, | |
7345 | { Bad_Opcode }, | |
7346 | { Bad_Opcode }, | |
7347 | { Bad_Opcode }, | |
7348 | { Bad_Opcode }, | |
7349 | { Bad_Opcode }, | |
7350 | { Bad_Opcode }, | |
f88c9eb0 | 7351 | /* c8 */ |
592d1631 L |
7352 | { Bad_Opcode }, |
7353 | { Bad_Opcode }, | |
7354 | { Bad_Opcode }, | |
7355 | { Bad_Opcode }, | |
a0046408 | 7356 | { PREFIX_TABLE (PREFIX_0F3ACC) }, |
592d1631 | 7357 | { Bad_Opcode }, |
48521003 IT |
7358 | { PREFIX_TABLE (PREFIX_0F3ACE) }, |
7359 | { PREFIX_TABLE (PREFIX_0F3ACF) }, | |
f88c9eb0 | 7360 | /* d0 */ |
592d1631 L |
7361 | { Bad_Opcode }, |
7362 | { Bad_Opcode }, | |
7363 | { Bad_Opcode }, | |
7364 | { Bad_Opcode }, | |
7365 | { Bad_Opcode }, | |
7366 | { Bad_Opcode }, | |
7367 | { Bad_Opcode }, | |
7368 | { Bad_Opcode }, | |
f88c9eb0 | 7369 | /* d8 */ |
592d1631 L |
7370 | { Bad_Opcode }, |
7371 | { Bad_Opcode }, | |
7372 | { Bad_Opcode }, | |
7373 | { Bad_Opcode }, | |
7374 | { Bad_Opcode }, | |
7375 | { Bad_Opcode }, | |
7376 | { Bad_Opcode }, | |
f88c9eb0 SP |
7377 | { PREFIX_TABLE (PREFIX_0F3ADF) }, |
7378 | /* e0 */ | |
592d1631 L |
7379 | { Bad_Opcode }, |
7380 | { Bad_Opcode }, | |
7381 | { Bad_Opcode }, | |
7382 | { Bad_Opcode }, | |
7383 | { Bad_Opcode }, | |
592d1631 L |
7384 | { Bad_Opcode }, |
7385 | { Bad_Opcode }, | |
7386 | { Bad_Opcode }, | |
85f10a01 | 7387 | /* e8 */ |
592d1631 L |
7388 | { Bad_Opcode }, |
7389 | { Bad_Opcode }, | |
7390 | { Bad_Opcode }, | |
7391 | { Bad_Opcode }, | |
7392 | { Bad_Opcode }, | |
7393 | { Bad_Opcode }, | |
7394 | { Bad_Opcode }, | |
7395 | { Bad_Opcode }, | |
85f10a01 | 7396 | /* f0 */ |
592d1631 L |
7397 | { Bad_Opcode }, |
7398 | { Bad_Opcode }, | |
7399 | { Bad_Opcode }, | |
7400 | { Bad_Opcode }, | |
7401 | { Bad_Opcode }, | |
7402 | { Bad_Opcode }, | |
7403 | { Bad_Opcode }, | |
7404 | { Bad_Opcode }, | |
85f10a01 | 7405 | /* f8 */ |
592d1631 L |
7406 | { Bad_Opcode }, |
7407 | { Bad_Opcode }, | |
7408 | { Bad_Opcode }, | |
7409 | { Bad_Opcode }, | |
7410 | { Bad_Opcode }, | |
7411 | { Bad_Opcode }, | |
7412 | { Bad_Opcode }, | |
7413 | { Bad_Opcode }, | |
85f10a01 | 7414 | }, |
f88c9eb0 SP |
7415 | }; |
7416 | ||
7417 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 7418 | /* XOP_08 */ |
85f10a01 MM |
7419 | { |
7420 | /* 00 */ | |
592d1631 L |
7421 | { Bad_Opcode }, |
7422 | { Bad_Opcode }, | |
7423 | { Bad_Opcode }, | |
7424 | { Bad_Opcode }, | |
7425 | { Bad_Opcode }, | |
7426 | { Bad_Opcode }, | |
7427 | { Bad_Opcode }, | |
7428 | { Bad_Opcode }, | |
85f10a01 | 7429 | /* 08 */ |
592d1631 L |
7430 | { Bad_Opcode }, |
7431 | { Bad_Opcode }, | |
7432 | { Bad_Opcode }, | |
7433 | { Bad_Opcode }, | |
7434 | { Bad_Opcode }, | |
7435 | { Bad_Opcode }, | |
7436 | { Bad_Opcode }, | |
7437 | { Bad_Opcode }, | |
85f10a01 | 7438 | /* 10 */ |
3929df09 | 7439 | { Bad_Opcode }, |
592d1631 L |
7440 | { Bad_Opcode }, |
7441 | { Bad_Opcode }, | |
7442 | { Bad_Opcode }, | |
7443 | { Bad_Opcode }, | |
7444 | { Bad_Opcode }, | |
7445 | { Bad_Opcode }, | |
7446 | { Bad_Opcode }, | |
85f10a01 | 7447 | /* 18 */ |
592d1631 L |
7448 | { Bad_Opcode }, |
7449 | { Bad_Opcode }, | |
7450 | { Bad_Opcode }, | |
7451 | { Bad_Opcode }, | |
7452 | { Bad_Opcode }, | |
7453 | { Bad_Opcode }, | |
7454 | { Bad_Opcode }, | |
7455 | { Bad_Opcode }, | |
85f10a01 | 7456 | /* 20 */ |
592d1631 L |
7457 | { Bad_Opcode }, |
7458 | { Bad_Opcode }, | |
7459 | { Bad_Opcode }, | |
7460 | { Bad_Opcode }, | |
7461 | { Bad_Opcode }, | |
7462 | { Bad_Opcode }, | |
7463 | { Bad_Opcode }, | |
7464 | { Bad_Opcode }, | |
85f10a01 | 7465 | /* 28 */ |
592d1631 L |
7466 | { Bad_Opcode }, |
7467 | { Bad_Opcode }, | |
7468 | { Bad_Opcode }, | |
7469 | { Bad_Opcode }, | |
7470 | { Bad_Opcode }, | |
7471 | { Bad_Opcode }, | |
7472 | { Bad_Opcode }, | |
7473 | { Bad_Opcode }, | |
c0f3af97 | 7474 | /* 30 */ |
592d1631 L |
7475 | { Bad_Opcode }, |
7476 | { Bad_Opcode }, | |
7477 | { Bad_Opcode }, | |
7478 | { Bad_Opcode }, | |
7479 | { Bad_Opcode }, | |
7480 | { Bad_Opcode }, | |
7481 | { Bad_Opcode }, | |
7482 | { Bad_Opcode }, | |
c0f3af97 | 7483 | /* 38 */ |
592d1631 L |
7484 | { Bad_Opcode }, |
7485 | { Bad_Opcode }, | |
7486 | { Bad_Opcode }, | |
7487 | { Bad_Opcode }, | |
7488 | { Bad_Opcode }, | |
7489 | { Bad_Opcode }, | |
7490 | { Bad_Opcode }, | |
7491 | { Bad_Opcode }, | |
c0f3af97 | 7492 | /* 40 */ |
592d1631 L |
7493 | { Bad_Opcode }, |
7494 | { Bad_Opcode }, | |
7495 | { Bad_Opcode }, | |
7496 | { Bad_Opcode }, | |
7497 | { Bad_Opcode }, | |
7498 | { Bad_Opcode }, | |
7499 | { Bad_Opcode }, | |
7500 | { Bad_Opcode }, | |
85f10a01 | 7501 | /* 48 */ |
592d1631 L |
7502 | { Bad_Opcode }, |
7503 | { Bad_Opcode }, | |
7504 | { Bad_Opcode }, | |
7505 | { Bad_Opcode }, | |
7506 | { Bad_Opcode }, | |
7507 | { Bad_Opcode }, | |
7508 | { Bad_Opcode }, | |
7509 | { Bad_Opcode }, | |
c0f3af97 | 7510 | /* 50 */ |
592d1631 L |
7511 | { Bad_Opcode }, |
7512 | { Bad_Opcode }, | |
7513 | { Bad_Opcode }, | |
7514 | { Bad_Opcode }, | |
7515 | { Bad_Opcode }, | |
7516 | { Bad_Opcode }, | |
7517 | { Bad_Opcode }, | |
7518 | { Bad_Opcode }, | |
85f10a01 | 7519 | /* 58 */ |
592d1631 L |
7520 | { Bad_Opcode }, |
7521 | { Bad_Opcode }, | |
7522 | { Bad_Opcode }, | |
7523 | { Bad_Opcode }, | |
7524 | { Bad_Opcode }, | |
7525 | { Bad_Opcode }, | |
7526 | { Bad_Opcode }, | |
7527 | { Bad_Opcode }, | |
c1e679ec | 7528 | /* 60 */ |
592d1631 L |
7529 | { Bad_Opcode }, |
7530 | { Bad_Opcode }, | |
7531 | { Bad_Opcode }, | |
7532 | { Bad_Opcode }, | |
7533 | { Bad_Opcode }, | |
7534 | { Bad_Opcode }, | |
7535 | { Bad_Opcode }, | |
7536 | { Bad_Opcode }, | |
c0f3af97 | 7537 | /* 68 */ |
592d1631 L |
7538 | { Bad_Opcode }, |
7539 | { Bad_Opcode }, | |
7540 | { Bad_Opcode }, | |
7541 | { Bad_Opcode }, | |
7542 | { Bad_Opcode }, | |
7543 | { Bad_Opcode }, | |
7544 | { Bad_Opcode }, | |
7545 | { Bad_Opcode }, | |
85f10a01 | 7546 | /* 70 */ |
592d1631 L |
7547 | { Bad_Opcode }, |
7548 | { Bad_Opcode }, | |
7549 | { Bad_Opcode }, | |
7550 | { Bad_Opcode }, | |
7551 | { Bad_Opcode }, | |
7552 | { Bad_Opcode }, | |
7553 | { Bad_Opcode }, | |
7554 | { Bad_Opcode }, | |
85f10a01 | 7555 | /* 78 */ |
592d1631 L |
7556 | { Bad_Opcode }, |
7557 | { Bad_Opcode }, | |
7558 | { Bad_Opcode }, | |
7559 | { Bad_Opcode }, | |
7560 | { Bad_Opcode }, | |
7561 | { Bad_Opcode }, | |
7562 | { Bad_Opcode }, | |
7563 | { Bad_Opcode }, | |
85f10a01 | 7564 | /* 80 */ |
592d1631 L |
7565 | { Bad_Opcode }, |
7566 | { Bad_Opcode }, | |
7567 | { Bad_Opcode }, | |
7568 | { Bad_Opcode }, | |
7569 | { Bad_Opcode }, | |
b13b1bc0 JB |
7570 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, |
7571 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7572 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
5dd85c99 | 7573 | /* 88 */ |
592d1631 L |
7574 | { Bad_Opcode }, |
7575 | { Bad_Opcode }, | |
7576 | { Bad_Opcode }, | |
7577 | { Bad_Opcode }, | |
7578 | { Bad_Opcode }, | |
7579 | { Bad_Opcode }, | |
b13b1bc0 JB |
7580 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
7581 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
5dd85c99 | 7582 | /* 90 */ |
592d1631 L |
7583 | { Bad_Opcode }, |
7584 | { Bad_Opcode }, | |
7585 | { Bad_Opcode }, | |
7586 | { Bad_Opcode }, | |
7587 | { Bad_Opcode }, | |
b13b1bc0 JB |
7588 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, |
7589 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7590 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
5dd85c99 | 7591 | /* 98 */ |
592d1631 L |
7592 | { Bad_Opcode }, |
7593 | { Bad_Opcode }, | |
7594 | { Bad_Opcode }, | |
7595 | { Bad_Opcode }, | |
7596 | { Bad_Opcode }, | |
7597 | { Bad_Opcode }, | |
b13b1bc0 JB |
7598 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
7599 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
5dd85c99 | 7600 | /* a0 */ |
592d1631 L |
7601 | { Bad_Opcode }, |
7602 | { Bad_Opcode }, | |
b13b1bc0 JB |
7603 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
7604 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
592d1631 L |
7605 | { Bad_Opcode }, |
7606 | { Bad_Opcode }, | |
b13b1bc0 | 7607 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
592d1631 | 7608 | { Bad_Opcode }, |
5dd85c99 | 7609 | /* a8 */ |
592d1631 L |
7610 | { Bad_Opcode }, |
7611 | { Bad_Opcode }, | |
7612 | { Bad_Opcode }, | |
7613 | { Bad_Opcode }, | |
7614 | { Bad_Opcode }, | |
7615 | { Bad_Opcode }, | |
7616 | { Bad_Opcode }, | |
7617 | { Bad_Opcode }, | |
5dd85c99 | 7618 | /* b0 */ |
592d1631 L |
7619 | { Bad_Opcode }, |
7620 | { Bad_Opcode }, | |
7621 | { Bad_Opcode }, | |
7622 | { Bad_Opcode }, | |
7623 | { Bad_Opcode }, | |
7624 | { Bad_Opcode }, | |
b13b1bc0 | 7625 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
592d1631 | 7626 | { Bad_Opcode }, |
5dd85c99 | 7627 | /* b8 */ |
592d1631 L |
7628 | { Bad_Opcode }, |
7629 | { Bad_Opcode }, | |
7630 | { Bad_Opcode }, | |
7631 | { Bad_Opcode }, | |
7632 | { Bad_Opcode }, | |
7633 | { Bad_Opcode }, | |
7634 | { Bad_Opcode }, | |
7635 | { Bad_Opcode }, | |
5dd85c99 | 7636 | /* c0 */ |
bf890a93 IT |
7637 | { "vprotb", { XM, Vex_2src_1, Ib }, 0 }, |
7638 | { "vprotw", { XM, Vex_2src_1, Ib }, 0 }, | |
7639 | { "vprotd", { XM, Vex_2src_1, Ib }, 0 }, | |
7640 | { "vprotq", { XM, Vex_2src_1, Ib }, 0 }, | |
592d1631 L |
7641 | { Bad_Opcode }, |
7642 | { Bad_Opcode }, | |
7643 | { Bad_Opcode }, | |
7644 | { Bad_Opcode }, | |
5dd85c99 | 7645 | /* c8 */ |
592d1631 L |
7646 | { Bad_Opcode }, |
7647 | { Bad_Opcode }, | |
7648 | { Bad_Opcode }, | |
7649 | { Bad_Opcode }, | |
ff688e1f L |
7650 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CC) }, |
7651 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CD) }, | |
7652 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CE) }, | |
7653 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_CF) }, | |
5dd85c99 | 7654 | /* d0 */ |
592d1631 L |
7655 | { Bad_Opcode }, |
7656 | { Bad_Opcode }, | |
7657 | { Bad_Opcode }, | |
7658 | { Bad_Opcode }, | |
7659 | { Bad_Opcode }, | |
7660 | { Bad_Opcode }, | |
7661 | { Bad_Opcode }, | |
7662 | { Bad_Opcode }, | |
5dd85c99 | 7663 | /* d8 */ |
592d1631 L |
7664 | { Bad_Opcode }, |
7665 | { Bad_Opcode }, | |
7666 | { Bad_Opcode }, | |
7667 | { Bad_Opcode }, | |
7668 | { Bad_Opcode }, | |
7669 | { Bad_Opcode }, | |
7670 | { Bad_Opcode }, | |
7671 | { Bad_Opcode }, | |
5dd85c99 | 7672 | /* e0 */ |
592d1631 L |
7673 | { Bad_Opcode }, |
7674 | { Bad_Opcode }, | |
7675 | { Bad_Opcode }, | |
7676 | { Bad_Opcode }, | |
7677 | { Bad_Opcode }, | |
7678 | { Bad_Opcode }, | |
7679 | { Bad_Opcode }, | |
7680 | { Bad_Opcode }, | |
5dd85c99 | 7681 | /* e8 */ |
592d1631 L |
7682 | { Bad_Opcode }, |
7683 | { Bad_Opcode }, | |
7684 | { Bad_Opcode }, | |
7685 | { Bad_Opcode }, | |
ff688e1f L |
7686 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EC) }, |
7687 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_ED) }, | |
7688 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EE) }, | |
7689 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_08_EF) }, | |
5dd85c99 | 7690 | /* f0 */ |
592d1631 L |
7691 | { Bad_Opcode }, |
7692 | { Bad_Opcode }, | |
7693 | { Bad_Opcode }, | |
7694 | { Bad_Opcode }, | |
7695 | { Bad_Opcode }, | |
7696 | { Bad_Opcode }, | |
7697 | { Bad_Opcode }, | |
7698 | { Bad_Opcode }, | |
5dd85c99 | 7699 | /* f8 */ |
592d1631 L |
7700 | { Bad_Opcode }, |
7701 | { Bad_Opcode }, | |
7702 | { Bad_Opcode }, | |
7703 | { Bad_Opcode }, | |
7704 | { Bad_Opcode }, | |
7705 | { Bad_Opcode }, | |
7706 | { Bad_Opcode }, | |
7707 | { Bad_Opcode }, | |
5dd85c99 SP |
7708 | }, |
7709 | /* XOP_09 */ | |
7710 | { | |
7711 | /* 00 */ | |
592d1631 | 7712 | { Bad_Opcode }, |
2a2a0f38 QN |
7713 | { REG_TABLE (REG_XOP_TBM_01) }, |
7714 | { REG_TABLE (REG_XOP_TBM_02) }, | |
592d1631 L |
7715 | { Bad_Opcode }, |
7716 | { Bad_Opcode }, | |
7717 | { Bad_Opcode }, | |
7718 | { Bad_Opcode }, | |
7719 | { Bad_Opcode }, | |
5dd85c99 | 7720 | /* 08 */ |
592d1631 L |
7721 | { Bad_Opcode }, |
7722 | { Bad_Opcode }, | |
7723 | { Bad_Opcode }, | |
7724 | { Bad_Opcode }, | |
7725 | { Bad_Opcode }, | |
7726 | { Bad_Opcode }, | |
7727 | { Bad_Opcode }, | |
7728 | { Bad_Opcode }, | |
5dd85c99 | 7729 | /* 10 */ |
592d1631 L |
7730 | { Bad_Opcode }, |
7731 | { Bad_Opcode }, | |
5dd85c99 | 7732 | { REG_TABLE (REG_XOP_LWPCB) }, |
592d1631 L |
7733 | { Bad_Opcode }, |
7734 | { Bad_Opcode }, | |
7735 | { Bad_Opcode }, | |
7736 | { Bad_Opcode }, | |
7737 | { Bad_Opcode }, | |
5dd85c99 | 7738 | /* 18 */ |
592d1631 L |
7739 | { Bad_Opcode }, |
7740 | { Bad_Opcode }, | |
7741 | { Bad_Opcode }, | |
7742 | { Bad_Opcode }, | |
7743 | { Bad_Opcode }, | |
7744 | { Bad_Opcode }, | |
7745 | { Bad_Opcode }, | |
7746 | { Bad_Opcode }, | |
5dd85c99 | 7747 | /* 20 */ |
592d1631 L |
7748 | { Bad_Opcode }, |
7749 | { Bad_Opcode }, | |
7750 | { Bad_Opcode }, | |
7751 | { Bad_Opcode }, | |
7752 | { Bad_Opcode }, | |
7753 | { Bad_Opcode }, | |
7754 | { Bad_Opcode }, | |
7755 | { Bad_Opcode }, | |
5dd85c99 | 7756 | /* 28 */ |
592d1631 L |
7757 | { Bad_Opcode }, |
7758 | { Bad_Opcode }, | |
7759 | { Bad_Opcode }, | |
7760 | { Bad_Opcode }, | |
7761 | { Bad_Opcode }, | |
7762 | { Bad_Opcode }, | |
7763 | { Bad_Opcode }, | |
7764 | { Bad_Opcode }, | |
5dd85c99 | 7765 | /* 30 */ |
592d1631 L |
7766 | { Bad_Opcode }, |
7767 | { Bad_Opcode }, | |
7768 | { Bad_Opcode }, | |
7769 | { Bad_Opcode }, | |
7770 | { Bad_Opcode }, | |
7771 | { Bad_Opcode }, | |
7772 | { Bad_Opcode }, | |
7773 | { Bad_Opcode }, | |
5dd85c99 | 7774 | /* 38 */ |
592d1631 L |
7775 | { Bad_Opcode }, |
7776 | { Bad_Opcode }, | |
7777 | { Bad_Opcode }, | |
7778 | { Bad_Opcode }, | |
7779 | { Bad_Opcode }, | |
7780 | { Bad_Opcode }, | |
7781 | { Bad_Opcode }, | |
7782 | { Bad_Opcode }, | |
5dd85c99 | 7783 | /* 40 */ |
592d1631 L |
7784 | { Bad_Opcode }, |
7785 | { Bad_Opcode }, | |
7786 | { Bad_Opcode }, | |
7787 | { Bad_Opcode }, | |
7788 | { Bad_Opcode }, | |
7789 | { Bad_Opcode }, | |
7790 | { Bad_Opcode }, | |
7791 | { Bad_Opcode }, | |
5dd85c99 | 7792 | /* 48 */ |
592d1631 L |
7793 | { Bad_Opcode }, |
7794 | { Bad_Opcode }, | |
7795 | { Bad_Opcode }, | |
7796 | { Bad_Opcode }, | |
7797 | { Bad_Opcode }, | |
7798 | { Bad_Opcode }, | |
7799 | { Bad_Opcode }, | |
7800 | { Bad_Opcode }, | |
5dd85c99 | 7801 | /* 50 */ |
592d1631 L |
7802 | { Bad_Opcode }, |
7803 | { Bad_Opcode }, | |
7804 | { Bad_Opcode }, | |
7805 | { Bad_Opcode }, | |
7806 | { Bad_Opcode }, | |
7807 | { Bad_Opcode }, | |
7808 | { Bad_Opcode }, | |
7809 | { Bad_Opcode }, | |
5dd85c99 | 7810 | /* 58 */ |
592d1631 L |
7811 | { Bad_Opcode }, |
7812 | { Bad_Opcode }, | |
7813 | { Bad_Opcode }, | |
7814 | { Bad_Opcode }, | |
7815 | { Bad_Opcode }, | |
7816 | { Bad_Opcode }, | |
7817 | { Bad_Opcode }, | |
7818 | { Bad_Opcode }, | |
5dd85c99 | 7819 | /* 60 */ |
592d1631 L |
7820 | { Bad_Opcode }, |
7821 | { Bad_Opcode }, | |
7822 | { Bad_Opcode }, | |
7823 | { Bad_Opcode }, | |
7824 | { Bad_Opcode }, | |
7825 | { Bad_Opcode }, | |
7826 | { Bad_Opcode }, | |
7827 | { Bad_Opcode }, | |
5dd85c99 | 7828 | /* 68 */ |
592d1631 L |
7829 | { Bad_Opcode }, |
7830 | { Bad_Opcode }, | |
7831 | { Bad_Opcode }, | |
7832 | { Bad_Opcode }, | |
7833 | { Bad_Opcode }, | |
7834 | { Bad_Opcode }, | |
7835 | { Bad_Opcode }, | |
7836 | { Bad_Opcode }, | |
5dd85c99 | 7837 | /* 70 */ |
592d1631 L |
7838 | { Bad_Opcode }, |
7839 | { Bad_Opcode }, | |
7840 | { Bad_Opcode }, | |
7841 | { Bad_Opcode }, | |
7842 | { Bad_Opcode }, | |
7843 | { Bad_Opcode }, | |
7844 | { Bad_Opcode }, | |
7845 | { Bad_Opcode }, | |
5dd85c99 | 7846 | /* 78 */ |
592d1631 L |
7847 | { Bad_Opcode }, |
7848 | { Bad_Opcode }, | |
7849 | { Bad_Opcode }, | |
7850 | { Bad_Opcode }, | |
7851 | { Bad_Opcode }, | |
7852 | { Bad_Opcode }, | |
7853 | { Bad_Opcode }, | |
7854 | { Bad_Opcode }, | |
5dd85c99 | 7855 | /* 80 */ |
b5b098c2 JB |
7856 | { VEX_W_TABLE (VEX_W_0FXOP_09_80) }, |
7857 | { VEX_W_TABLE (VEX_W_0FXOP_09_81) }, | |
7858 | { VEX_W_TABLE (VEX_W_0FXOP_09_82) }, | |
7859 | { VEX_W_TABLE (VEX_W_0FXOP_09_83) }, | |
592d1631 L |
7860 | { Bad_Opcode }, |
7861 | { Bad_Opcode }, | |
7862 | { Bad_Opcode }, | |
7863 | { Bad_Opcode }, | |
5dd85c99 | 7864 | /* 88 */ |
592d1631 L |
7865 | { Bad_Opcode }, |
7866 | { Bad_Opcode }, | |
7867 | { Bad_Opcode }, | |
7868 | { Bad_Opcode }, | |
7869 | { Bad_Opcode }, | |
7870 | { Bad_Opcode }, | |
7871 | { Bad_Opcode }, | |
7872 | { Bad_Opcode }, | |
5dd85c99 | 7873 | /* 90 */ |
bf890a93 IT |
7874 | { "vprotb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7875 | { "vprotw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7876 | { "vprotd", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7877 | { "vprotq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7878 | { "vpshlb", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7879 | { "vpshlw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7880 | { "vpshld", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7881 | { "vpshlq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
5dd85c99 | 7882 | /* 98 */ |
bf890a93 IT |
7883 | { "vpshab", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, |
7884 | { "vpshaw", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7885 | { "vpshad", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
7886 | { "vpshaq", { XM, Vex_2src_1, Vex_2src_2 }, 0 }, | |
592d1631 L |
7887 | { Bad_Opcode }, |
7888 | { Bad_Opcode }, | |
7889 | { Bad_Opcode }, | |
7890 | { Bad_Opcode }, | |
5dd85c99 | 7891 | /* a0 */ |
592d1631 L |
7892 | { Bad_Opcode }, |
7893 | { Bad_Opcode }, | |
7894 | { Bad_Opcode }, | |
7895 | { Bad_Opcode }, | |
7896 | { Bad_Opcode }, | |
7897 | { Bad_Opcode }, | |
7898 | { Bad_Opcode }, | |
7899 | { Bad_Opcode }, | |
5dd85c99 | 7900 | /* a8 */ |
592d1631 L |
7901 | { Bad_Opcode }, |
7902 | { Bad_Opcode }, | |
7903 | { Bad_Opcode }, | |
7904 | { Bad_Opcode }, | |
7905 | { Bad_Opcode }, | |
7906 | { Bad_Opcode }, | |
7907 | { Bad_Opcode }, | |
7908 | { Bad_Opcode }, | |
5dd85c99 | 7909 | /* b0 */ |
592d1631 L |
7910 | { Bad_Opcode }, |
7911 | { Bad_Opcode }, | |
7912 | { Bad_Opcode }, | |
7913 | { Bad_Opcode }, | |
7914 | { Bad_Opcode }, | |
7915 | { Bad_Opcode }, | |
7916 | { Bad_Opcode }, | |
7917 | { Bad_Opcode }, | |
5dd85c99 | 7918 | /* b8 */ |
592d1631 L |
7919 | { Bad_Opcode }, |
7920 | { Bad_Opcode }, | |
7921 | { Bad_Opcode }, | |
7922 | { Bad_Opcode }, | |
7923 | { Bad_Opcode }, | |
7924 | { Bad_Opcode }, | |
7925 | { Bad_Opcode }, | |
7926 | { Bad_Opcode }, | |
5dd85c99 | 7927 | /* c0 */ |
592d1631 | 7928 | { Bad_Opcode }, |
bf890a93 IT |
7929 | { "vphaddbw", { XM, EXxmm }, 0 }, |
7930 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
7931 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7932 | { Bad_Opcode }, |
7933 | { Bad_Opcode }, | |
bf890a93 IT |
7934 | { "vphaddwd", { XM, EXxmm }, 0 }, |
7935 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7936 | /* c8 */ |
592d1631 L |
7937 | { Bad_Opcode }, |
7938 | { Bad_Opcode }, | |
7939 | { Bad_Opcode }, | |
bf890a93 | 7940 | { "vphadddq", { XM, EXxmm }, 0 }, |
592d1631 L |
7941 | { Bad_Opcode }, |
7942 | { Bad_Opcode }, | |
7943 | { Bad_Opcode }, | |
7944 | { Bad_Opcode }, | |
5dd85c99 | 7945 | /* d0 */ |
592d1631 | 7946 | { Bad_Opcode }, |
bf890a93 IT |
7947 | { "vphaddubw", { XM, EXxmm }, 0 }, |
7948 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
7949 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7950 | { Bad_Opcode }, |
7951 | { Bad_Opcode }, | |
bf890a93 IT |
7952 | { "vphadduwd", { XM, EXxmm }, 0 }, |
7953 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
5dd85c99 | 7954 | /* d8 */ |
592d1631 L |
7955 | { Bad_Opcode }, |
7956 | { Bad_Opcode }, | |
7957 | { Bad_Opcode }, | |
bf890a93 | 7958 | { "vphaddudq", { XM, EXxmm }, 0 }, |
592d1631 L |
7959 | { Bad_Opcode }, |
7960 | { Bad_Opcode }, | |
7961 | { Bad_Opcode }, | |
7962 | { Bad_Opcode }, | |
5dd85c99 | 7963 | /* e0 */ |
592d1631 | 7964 | { Bad_Opcode }, |
bf890a93 IT |
7965 | { "vphsubbw", { XM, EXxmm }, 0 }, |
7966 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
7967 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
592d1631 L |
7968 | { Bad_Opcode }, |
7969 | { Bad_Opcode }, | |
7970 | { Bad_Opcode }, | |
7971 | { Bad_Opcode }, | |
4e7d34a6 | 7972 | /* e8 */ |
592d1631 L |
7973 | { Bad_Opcode }, |
7974 | { Bad_Opcode }, | |
7975 | { Bad_Opcode }, | |
7976 | { Bad_Opcode }, | |
7977 | { Bad_Opcode }, | |
7978 | { Bad_Opcode }, | |
7979 | { Bad_Opcode }, | |
7980 | { Bad_Opcode }, | |
4e7d34a6 | 7981 | /* f0 */ |
592d1631 L |
7982 | { Bad_Opcode }, |
7983 | { Bad_Opcode }, | |
7984 | { Bad_Opcode }, | |
7985 | { Bad_Opcode }, | |
7986 | { Bad_Opcode }, | |
7987 | { Bad_Opcode }, | |
7988 | { Bad_Opcode }, | |
7989 | { Bad_Opcode }, | |
4e7d34a6 | 7990 | /* f8 */ |
592d1631 L |
7991 | { Bad_Opcode }, |
7992 | { Bad_Opcode }, | |
7993 | { Bad_Opcode }, | |
7994 | { Bad_Opcode }, | |
7995 | { Bad_Opcode }, | |
7996 | { Bad_Opcode }, | |
7997 | { Bad_Opcode }, | |
7998 | { Bad_Opcode }, | |
4e7d34a6 | 7999 | }, |
f88c9eb0 | 8000 | /* XOP_0A */ |
4e7d34a6 L |
8001 | { |
8002 | /* 00 */ | |
592d1631 L |
8003 | { Bad_Opcode }, |
8004 | { Bad_Opcode }, | |
8005 | { Bad_Opcode }, | |
8006 | { Bad_Opcode }, | |
8007 | { Bad_Opcode }, | |
8008 | { Bad_Opcode }, | |
8009 | { Bad_Opcode }, | |
8010 | { Bad_Opcode }, | |
4e7d34a6 | 8011 | /* 08 */ |
592d1631 L |
8012 | { Bad_Opcode }, |
8013 | { Bad_Opcode }, | |
8014 | { Bad_Opcode }, | |
8015 | { Bad_Opcode }, | |
8016 | { Bad_Opcode }, | |
8017 | { Bad_Opcode }, | |
8018 | { Bad_Opcode }, | |
8019 | { Bad_Opcode }, | |
4e7d34a6 | 8020 | /* 10 */ |
c1dc7af5 | 8021 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 8022 | { Bad_Opcode }, |
f88c9eb0 | 8023 | { REG_TABLE (REG_XOP_LWP) }, |
592d1631 L |
8024 | { Bad_Opcode }, |
8025 | { Bad_Opcode }, | |
8026 | { Bad_Opcode }, | |
8027 | { Bad_Opcode }, | |
8028 | { Bad_Opcode }, | |
4e7d34a6 | 8029 | /* 18 */ |
592d1631 L |
8030 | { Bad_Opcode }, |
8031 | { Bad_Opcode }, | |
8032 | { Bad_Opcode }, | |
8033 | { Bad_Opcode }, | |
8034 | { Bad_Opcode }, | |
8035 | { Bad_Opcode }, | |
8036 | { Bad_Opcode }, | |
8037 | { Bad_Opcode }, | |
4e7d34a6 | 8038 | /* 20 */ |
592d1631 L |
8039 | { Bad_Opcode }, |
8040 | { Bad_Opcode }, | |
8041 | { Bad_Opcode }, | |
8042 | { Bad_Opcode }, | |
8043 | { Bad_Opcode }, | |
8044 | { Bad_Opcode }, | |
8045 | { Bad_Opcode }, | |
8046 | { Bad_Opcode }, | |
4e7d34a6 | 8047 | /* 28 */ |
592d1631 L |
8048 | { Bad_Opcode }, |
8049 | { Bad_Opcode }, | |
8050 | { Bad_Opcode }, | |
8051 | { Bad_Opcode }, | |
8052 | { Bad_Opcode }, | |
8053 | { Bad_Opcode }, | |
8054 | { Bad_Opcode }, | |
8055 | { Bad_Opcode }, | |
4e7d34a6 | 8056 | /* 30 */ |
592d1631 L |
8057 | { Bad_Opcode }, |
8058 | { Bad_Opcode }, | |
8059 | { Bad_Opcode }, | |
8060 | { Bad_Opcode }, | |
8061 | { Bad_Opcode }, | |
8062 | { Bad_Opcode }, | |
8063 | { Bad_Opcode }, | |
8064 | { Bad_Opcode }, | |
c0f3af97 | 8065 | /* 38 */ |
592d1631 L |
8066 | { Bad_Opcode }, |
8067 | { Bad_Opcode }, | |
8068 | { Bad_Opcode }, | |
8069 | { Bad_Opcode }, | |
8070 | { Bad_Opcode }, | |
8071 | { Bad_Opcode }, | |
8072 | { Bad_Opcode }, | |
8073 | { Bad_Opcode }, | |
c0f3af97 | 8074 | /* 40 */ |
592d1631 L |
8075 | { Bad_Opcode }, |
8076 | { Bad_Opcode }, | |
8077 | { Bad_Opcode }, | |
8078 | { Bad_Opcode }, | |
8079 | { Bad_Opcode }, | |
8080 | { Bad_Opcode }, | |
8081 | { Bad_Opcode }, | |
8082 | { Bad_Opcode }, | |
c1e679ec | 8083 | /* 48 */ |
592d1631 L |
8084 | { Bad_Opcode }, |
8085 | { Bad_Opcode }, | |
8086 | { Bad_Opcode }, | |
8087 | { Bad_Opcode }, | |
8088 | { Bad_Opcode }, | |
8089 | { Bad_Opcode }, | |
8090 | { Bad_Opcode }, | |
8091 | { Bad_Opcode }, | |
c1e679ec | 8092 | /* 50 */ |
592d1631 L |
8093 | { Bad_Opcode }, |
8094 | { Bad_Opcode }, | |
8095 | { Bad_Opcode }, | |
8096 | { Bad_Opcode }, | |
8097 | { Bad_Opcode }, | |
8098 | { Bad_Opcode }, | |
8099 | { Bad_Opcode }, | |
8100 | { Bad_Opcode }, | |
4e7d34a6 | 8101 | /* 58 */ |
592d1631 L |
8102 | { Bad_Opcode }, |
8103 | { Bad_Opcode }, | |
8104 | { Bad_Opcode }, | |
8105 | { Bad_Opcode }, | |
8106 | { Bad_Opcode }, | |
8107 | { Bad_Opcode }, | |
8108 | { Bad_Opcode }, | |
8109 | { Bad_Opcode }, | |
4e7d34a6 | 8110 | /* 60 */ |
592d1631 L |
8111 | { Bad_Opcode }, |
8112 | { Bad_Opcode }, | |
8113 | { Bad_Opcode }, | |
8114 | { Bad_Opcode }, | |
8115 | { Bad_Opcode }, | |
8116 | { Bad_Opcode }, | |
8117 | { Bad_Opcode }, | |
8118 | { Bad_Opcode }, | |
4e7d34a6 | 8119 | /* 68 */ |
592d1631 L |
8120 | { Bad_Opcode }, |
8121 | { Bad_Opcode }, | |
8122 | { Bad_Opcode }, | |
8123 | { Bad_Opcode }, | |
8124 | { Bad_Opcode }, | |
8125 | { Bad_Opcode }, | |
8126 | { Bad_Opcode }, | |
8127 | { Bad_Opcode }, | |
4e7d34a6 | 8128 | /* 70 */ |
592d1631 L |
8129 | { Bad_Opcode }, |
8130 | { Bad_Opcode }, | |
8131 | { Bad_Opcode }, | |
8132 | { Bad_Opcode }, | |
8133 | { Bad_Opcode }, | |
8134 | { Bad_Opcode }, | |
8135 | { Bad_Opcode }, | |
8136 | { Bad_Opcode }, | |
4e7d34a6 | 8137 | /* 78 */ |
592d1631 L |
8138 | { Bad_Opcode }, |
8139 | { Bad_Opcode }, | |
8140 | { Bad_Opcode }, | |
8141 | { Bad_Opcode }, | |
8142 | { Bad_Opcode }, | |
8143 | { Bad_Opcode }, | |
8144 | { Bad_Opcode }, | |
8145 | { Bad_Opcode }, | |
4e7d34a6 | 8146 | /* 80 */ |
592d1631 L |
8147 | { Bad_Opcode }, |
8148 | { Bad_Opcode }, | |
8149 | { Bad_Opcode }, | |
8150 | { Bad_Opcode }, | |
8151 | { Bad_Opcode }, | |
8152 | { Bad_Opcode }, | |
8153 | { Bad_Opcode }, | |
8154 | { Bad_Opcode }, | |
4e7d34a6 | 8155 | /* 88 */ |
592d1631 L |
8156 | { Bad_Opcode }, |
8157 | { Bad_Opcode }, | |
8158 | { Bad_Opcode }, | |
8159 | { Bad_Opcode }, | |
8160 | { Bad_Opcode }, | |
8161 | { Bad_Opcode }, | |
8162 | { Bad_Opcode }, | |
8163 | { Bad_Opcode }, | |
4e7d34a6 | 8164 | /* 90 */ |
592d1631 L |
8165 | { Bad_Opcode }, |
8166 | { Bad_Opcode }, | |
8167 | { Bad_Opcode }, | |
8168 | { Bad_Opcode }, | |
8169 | { Bad_Opcode }, | |
8170 | { Bad_Opcode }, | |
8171 | { Bad_Opcode }, | |
8172 | { Bad_Opcode }, | |
4e7d34a6 | 8173 | /* 98 */ |
592d1631 L |
8174 | { Bad_Opcode }, |
8175 | { Bad_Opcode }, | |
8176 | { Bad_Opcode }, | |
8177 | { Bad_Opcode }, | |
8178 | { Bad_Opcode }, | |
8179 | { Bad_Opcode }, | |
8180 | { Bad_Opcode }, | |
8181 | { Bad_Opcode }, | |
4e7d34a6 | 8182 | /* a0 */ |
592d1631 L |
8183 | { Bad_Opcode }, |
8184 | { Bad_Opcode }, | |
8185 | { Bad_Opcode }, | |
8186 | { Bad_Opcode }, | |
8187 | { Bad_Opcode }, | |
8188 | { Bad_Opcode }, | |
8189 | { Bad_Opcode }, | |
8190 | { Bad_Opcode }, | |
4e7d34a6 | 8191 | /* a8 */ |
592d1631 L |
8192 | { Bad_Opcode }, |
8193 | { Bad_Opcode }, | |
8194 | { Bad_Opcode }, | |
8195 | { Bad_Opcode }, | |
8196 | { Bad_Opcode }, | |
8197 | { Bad_Opcode }, | |
8198 | { Bad_Opcode }, | |
8199 | { Bad_Opcode }, | |
d5d7db8e | 8200 | /* b0 */ |
592d1631 L |
8201 | { Bad_Opcode }, |
8202 | { Bad_Opcode }, | |
8203 | { Bad_Opcode }, | |
8204 | { Bad_Opcode }, | |
8205 | { Bad_Opcode }, | |
8206 | { Bad_Opcode }, | |
8207 | { Bad_Opcode }, | |
8208 | { Bad_Opcode }, | |
85f10a01 | 8209 | /* b8 */ |
592d1631 L |
8210 | { Bad_Opcode }, |
8211 | { Bad_Opcode }, | |
8212 | { Bad_Opcode }, | |
8213 | { Bad_Opcode }, | |
8214 | { Bad_Opcode }, | |
8215 | { Bad_Opcode }, | |
8216 | { Bad_Opcode }, | |
8217 | { Bad_Opcode }, | |
85f10a01 | 8218 | /* c0 */ |
592d1631 L |
8219 | { Bad_Opcode }, |
8220 | { Bad_Opcode }, | |
8221 | { Bad_Opcode }, | |
8222 | { Bad_Opcode }, | |
8223 | { Bad_Opcode }, | |
8224 | { Bad_Opcode }, | |
8225 | { Bad_Opcode }, | |
8226 | { Bad_Opcode }, | |
85f10a01 | 8227 | /* c8 */ |
592d1631 L |
8228 | { Bad_Opcode }, |
8229 | { Bad_Opcode }, | |
8230 | { Bad_Opcode }, | |
8231 | { Bad_Opcode }, | |
8232 | { Bad_Opcode }, | |
8233 | { Bad_Opcode }, | |
8234 | { Bad_Opcode }, | |
8235 | { Bad_Opcode }, | |
85f10a01 | 8236 | /* d0 */ |
592d1631 L |
8237 | { Bad_Opcode }, |
8238 | { Bad_Opcode }, | |
8239 | { Bad_Opcode }, | |
8240 | { Bad_Opcode }, | |
8241 | { Bad_Opcode }, | |
8242 | { Bad_Opcode }, | |
8243 | { Bad_Opcode }, | |
8244 | { Bad_Opcode }, | |
85f10a01 | 8245 | /* d8 */ |
592d1631 L |
8246 | { Bad_Opcode }, |
8247 | { Bad_Opcode }, | |
8248 | { Bad_Opcode }, | |
8249 | { Bad_Opcode }, | |
8250 | { Bad_Opcode }, | |
8251 | { Bad_Opcode }, | |
8252 | { Bad_Opcode }, | |
8253 | { Bad_Opcode }, | |
85f10a01 | 8254 | /* e0 */ |
592d1631 L |
8255 | { Bad_Opcode }, |
8256 | { Bad_Opcode }, | |
8257 | { Bad_Opcode }, | |
8258 | { Bad_Opcode }, | |
8259 | { Bad_Opcode }, | |
8260 | { Bad_Opcode }, | |
8261 | { Bad_Opcode }, | |
8262 | { Bad_Opcode }, | |
85f10a01 | 8263 | /* e8 */ |
592d1631 L |
8264 | { Bad_Opcode }, |
8265 | { Bad_Opcode }, | |
8266 | { Bad_Opcode }, | |
8267 | { Bad_Opcode }, | |
8268 | { Bad_Opcode }, | |
8269 | { Bad_Opcode }, | |
8270 | { Bad_Opcode }, | |
8271 | { Bad_Opcode }, | |
85f10a01 | 8272 | /* f0 */ |
592d1631 L |
8273 | { Bad_Opcode }, |
8274 | { Bad_Opcode }, | |
8275 | { Bad_Opcode }, | |
8276 | { Bad_Opcode }, | |
8277 | { Bad_Opcode }, | |
8278 | { Bad_Opcode }, | |
8279 | { Bad_Opcode }, | |
8280 | { Bad_Opcode }, | |
85f10a01 | 8281 | /* f8 */ |
592d1631 L |
8282 | { Bad_Opcode }, |
8283 | { Bad_Opcode }, | |
8284 | { Bad_Opcode }, | |
8285 | { Bad_Opcode }, | |
8286 | { Bad_Opcode }, | |
8287 | { Bad_Opcode }, | |
8288 | { Bad_Opcode }, | |
8289 | { Bad_Opcode }, | |
85f10a01 | 8290 | }, |
c0f3af97 L |
8291 | }; |
8292 | ||
8293 | static const struct dis386 vex_table[][256] = { | |
8294 | /* VEX_0F */ | |
85f10a01 MM |
8295 | { |
8296 | /* 00 */ | |
592d1631 L |
8297 | { Bad_Opcode }, |
8298 | { Bad_Opcode }, | |
8299 | { Bad_Opcode }, | |
8300 | { Bad_Opcode }, | |
8301 | { Bad_Opcode }, | |
8302 | { Bad_Opcode }, | |
8303 | { Bad_Opcode }, | |
8304 | { Bad_Opcode }, | |
85f10a01 | 8305 | /* 08 */ |
592d1631 L |
8306 | { Bad_Opcode }, |
8307 | { Bad_Opcode }, | |
8308 | { Bad_Opcode }, | |
8309 | { Bad_Opcode }, | |
8310 | { Bad_Opcode }, | |
8311 | { Bad_Opcode }, | |
8312 | { Bad_Opcode }, | |
8313 | { Bad_Opcode }, | |
c0f3af97 | 8314 | /* 10 */ |
592a252b L |
8315 | { PREFIX_TABLE (PREFIX_VEX_0F10) }, |
8316 | { PREFIX_TABLE (PREFIX_VEX_0F11) }, | |
8317 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, | |
8318 | { MOD_TABLE (MOD_VEX_0F13) }, | |
bf926894 JB |
8319 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8320 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b L |
8321 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
8322 | { MOD_TABLE (MOD_VEX_0F17) }, | |
c0f3af97 | 8323 | /* 18 */ |
592d1631 L |
8324 | { Bad_Opcode }, |
8325 | { Bad_Opcode }, | |
8326 | { Bad_Opcode }, | |
8327 | { Bad_Opcode }, | |
8328 | { Bad_Opcode }, | |
8329 | { Bad_Opcode }, | |
8330 | { Bad_Opcode }, | |
8331 | { Bad_Opcode }, | |
c0f3af97 | 8332 | /* 20 */ |
592d1631 L |
8333 | { Bad_Opcode }, |
8334 | { Bad_Opcode }, | |
8335 | { Bad_Opcode }, | |
8336 | { Bad_Opcode }, | |
8337 | { Bad_Opcode }, | |
8338 | { Bad_Opcode }, | |
8339 | { Bad_Opcode }, | |
8340 | { Bad_Opcode }, | |
c0f3af97 | 8341 | /* 28 */ |
bf926894 JB |
8342 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
8343 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b L |
8344 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
8345 | { MOD_TABLE (MOD_VEX_0F2B) }, | |
8346 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, | |
8347 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
8348 | { PREFIX_TABLE (PREFIX_VEX_0F2E) }, | |
8349 | { PREFIX_TABLE (PREFIX_VEX_0F2F) }, | |
85f10a01 | 8350 | /* 30 */ |
592d1631 L |
8351 | { Bad_Opcode }, |
8352 | { Bad_Opcode }, | |
8353 | { Bad_Opcode }, | |
8354 | { Bad_Opcode }, | |
8355 | { Bad_Opcode }, | |
8356 | { Bad_Opcode }, | |
8357 | { Bad_Opcode }, | |
8358 | { Bad_Opcode }, | |
4e7d34a6 | 8359 | /* 38 */ |
592d1631 L |
8360 | { Bad_Opcode }, |
8361 | { Bad_Opcode }, | |
8362 | { Bad_Opcode }, | |
8363 | { Bad_Opcode }, | |
8364 | { Bad_Opcode }, | |
8365 | { Bad_Opcode }, | |
8366 | { Bad_Opcode }, | |
8367 | { Bad_Opcode }, | |
d5d7db8e | 8368 | /* 40 */ |
592d1631 | 8369 | { Bad_Opcode }, |
43234a1e L |
8370 | { PREFIX_TABLE (PREFIX_VEX_0F41) }, |
8371 | { PREFIX_TABLE (PREFIX_VEX_0F42) }, | |
592d1631 | 8372 | { Bad_Opcode }, |
43234a1e L |
8373 | { PREFIX_TABLE (PREFIX_VEX_0F44) }, |
8374 | { PREFIX_TABLE (PREFIX_VEX_0F45) }, | |
8375 | { PREFIX_TABLE (PREFIX_VEX_0F46) }, | |
8376 | { PREFIX_TABLE (PREFIX_VEX_0F47) }, | |
85f10a01 | 8377 | /* 48 */ |
592d1631 L |
8378 | { Bad_Opcode }, |
8379 | { Bad_Opcode }, | |
1ba585e8 | 8380 | { PREFIX_TABLE (PREFIX_VEX_0F4A) }, |
43234a1e | 8381 | { PREFIX_TABLE (PREFIX_VEX_0F4B) }, |
592d1631 L |
8382 | { Bad_Opcode }, |
8383 | { Bad_Opcode }, | |
8384 | { Bad_Opcode }, | |
8385 | { Bad_Opcode }, | |
d5d7db8e | 8386 | /* 50 */ |
592a252b L |
8387 | { MOD_TABLE (MOD_VEX_0F50) }, |
8388 | { PREFIX_TABLE (PREFIX_VEX_0F51) }, | |
8389 | { PREFIX_TABLE (PREFIX_VEX_0F52) }, | |
8390 | { PREFIX_TABLE (PREFIX_VEX_0F53) }, | |
bf926894 JB |
8391 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
8392 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8393 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
8394 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 8395 | /* 58 */ |
592a252b L |
8396 | { PREFIX_TABLE (PREFIX_VEX_0F58) }, |
8397 | { PREFIX_TABLE (PREFIX_VEX_0F59) }, | |
8398 | { PREFIX_TABLE (PREFIX_VEX_0F5A) }, | |
8399 | { PREFIX_TABLE (PREFIX_VEX_0F5B) }, | |
8400 | { PREFIX_TABLE (PREFIX_VEX_0F5C) }, | |
8401 | { PREFIX_TABLE (PREFIX_VEX_0F5D) }, | |
8402 | { PREFIX_TABLE (PREFIX_VEX_0F5E) }, | |
8403 | { PREFIX_TABLE (PREFIX_VEX_0F5F) }, | |
c0f3af97 | 8404 | /* 60 */ |
592a252b L |
8405 | { PREFIX_TABLE (PREFIX_VEX_0F60) }, |
8406 | { PREFIX_TABLE (PREFIX_VEX_0F61) }, | |
8407 | { PREFIX_TABLE (PREFIX_VEX_0F62) }, | |
8408 | { PREFIX_TABLE (PREFIX_VEX_0F63) }, | |
8409 | { PREFIX_TABLE (PREFIX_VEX_0F64) }, | |
8410 | { PREFIX_TABLE (PREFIX_VEX_0F65) }, | |
8411 | { PREFIX_TABLE (PREFIX_VEX_0F66) }, | |
8412 | { PREFIX_TABLE (PREFIX_VEX_0F67) }, | |
c0f3af97 | 8413 | /* 68 */ |
592a252b L |
8414 | { PREFIX_TABLE (PREFIX_VEX_0F68) }, |
8415 | { PREFIX_TABLE (PREFIX_VEX_0F69) }, | |
8416 | { PREFIX_TABLE (PREFIX_VEX_0F6A) }, | |
8417 | { PREFIX_TABLE (PREFIX_VEX_0F6B) }, | |
8418 | { PREFIX_TABLE (PREFIX_VEX_0F6C) }, | |
8419 | { PREFIX_TABLE (PREFIX_VEX_0F6D) }, | |
8420 | { PREFIX_TABLE (PREFIX_VEX_0F6E) }, | |
8421 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, | |
c0f3af97 | 8422 | /* 70 */ |
592a252b L |
8423 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
8424 | { REG_TABLE (REG_VEX_0F71) }, | |
8425 | { REG_TABLE (REG_VEX_0F72) }, | |
8426 | { REG_TABLE (REG_VEX_0F73) }, | |
8427 | { PREFIX_TABLE (PREFIX_VEX_0F74) }, | |
8428 | { PREFIX_TABLE (PREFIX_VEX_0F75) }, | |
8429 | { PREFIX_TABLE (PREFIX_VEX_0F76) }, | |
8430 | { PREFIX_TABLE (PREFIX_VEX_0F77) }, | |
c0f3af97 | 8431 | /* 78 */ |
592d1631 L |
8432 | { Bad_Opcode }, |
8433 | { Bad_Opcode }, | |
8434 | { Bad_Opcode }, | |
8435 | { Bad_Opcode }, | |
592a252b L |
8436 | { PREFIX_TABLE (PREFIX_VEX_0F7C) }, |
8437 | { PREFIX_TABLE (PREFIX_VEX_0F7D) }, | |
8438 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, | |
8439 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 8440 | /* 80 */ |
592d1631 L |
8441 | { Bad_Opcode }, |
8442 | { Bad_Opcode }, | |
8443 | { Bad_Opcode }, | |
8444 | { Bad_Opcode }, | |
8445 | { Bad_Opcode }, | |
8446 | { Bad_Opcode }, | |
8447 | { Bad_Opcode }, | |
8448 | { Bad_Opcode }, | |
c0f3af97 | 8449 | /* 88 */ |
592d1631 L |
8450 | { Bad_Opcode }, |
8451 | { Bad_Opcode }, | |
8452 | { Bad_Opcode }, | |
8453 | { Bad_Opcode }, | |
8454 | { Bad_Opcode }, | |
8455 | { Bad_Opcode }, | |
8456 | { Bad_Opcode }, | |
8457 | { Bad_Opcode }, | |
c0f3af97 | 8458 | /* 90 */ |
43234a1e L |
8459 | { PREFIX_TABLE (PREFIX_VEX_0F90) }, |
8460 | { PREFIX_TABLE (PREFIX_VEX_0F91) }, | |
8461 | { PREFIX_TABLE (PREFIX_VEX_0F92) }, | |
8462 | { PREFIX_TABLE (PREFIX_VEX_0F93) }, | |
592d1631 L |
8463 | { Bad_Opcode }, |
8464 | { Bad_Opcode }, | |
8465 | { Bad_Opcode }, | |
8466 | { Bad_Opcode }, | |
c0f3af97 | 8467 | /* 98 */ |
43234a1e | 8468 | { PREFIX_TABLE (PREFIX_VEX_0F98) }, |
1ba585e8 | 8469 | { PREFIX_TABLE (PREFIX_VEX_0F99) }, |
592d1631 L |
8470 | { Bad_Opcode }, |
8471 | { Bad_Opcode }, | |
8472 | { Bad_Opcode }, | |
8473 | { Bad_Opcode }, | |
8474 | { Bad_Opcode }, | |
8475 | { Bad_Opcode }, | |
c0f3af97 | 8476 | /* a0 */ |
592d1631 L |
8477 | { Bad_Opcode }, |
8478 | { Bad_Opcode }, | |
8479 | { Bad_Opcode }, | |
8480 | { Bad_Opcode }, | |
8481 | { Bad_Opcode }, | |
8482 | { Bad_Opcode }, | |
8483 | { Bad_Opcode }, | |
8484 | { Bad_Opcode }, | |
c0f3af97 | 8485 | /* a8 */ |
592d1631 L |
8486 | { Bad_Opcode }, |
8487 | { Bad_Opcode }, | |
8488 | { Bad_Opcode }, | |
8489 | { Bad_Opcode }, | |
8490 | { Bad_Opcode }, | |
8491 | { Bad_Opcode }, | |
592a252b | 8492 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 8493 | { Bad_Opcode }, |
c0f3af97 | 8494 | /* b0 */ |
592d1631 L |
8495 | { Bad_Opcode }, |
8496 | { Bad_Opcode }, | |
8497 | { Bad_Opcode }, | |
8498 | { Bad_Opcode }, | |
8499 | { Bad_Opcode }, | |
8500 | { Bad_Opcode }, | |
8501 | { Bad_Opcode }, | |
8502 | { Bad_Opcode }, | |
c0f3af97 | 8503 | /* b8 */ |
592d1631 L |
8504 | { Bad_Opcode }, |
8505 | { Bad_Opcode }, | |
8506 | { Bad_Opcode }, | |
8507 | { Bad_Opcode }, | |
8508 | { Bad_Opcode }, | |
8509 | { Bad_Opcode }, | |
8510 | { Bad_Opcode }, | |
8511 | { Bad_Opcode }, | |
c0f3af97 | 8512 | /* c0 */ |
592d1631 L |
8513 | { Bad_Opcode }, |
8514 | { Bad_Opcode }, | |
592a252b | 8515 | { PREFIX_TABLE (PREFIX_VEX_0FC2) }, |
592d1631 | 8516 | { Bad_Opcode }, |
592a252b L |
8517 | { PREFIX_TABLE (PREFIX_VEX_0FC4) }, |
8518 | { PREFIX_TABLE (PREFIX_VEX_0FC5) }, | |
bf926894 | 8519 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 8520 | { Bad_Opcode }, |
c0f3af97 | 8521 | /* c8 */ |
592d1631 L |
8522 | { Bad_Opcode }, |
8523 | { Bad_Opcode }, | |
8524 | { Bad_Opcode }, | |
8525 | { Bad_Opcode }, | |
8526 | { Bad_Opcode }, | |
8527 | { Bad_Opcode }, | |
8528 | { Bad_Opcode }, | |
8529 | { Bad_Opcode }, | |
c0f3af97 | 8530 | /* d0 */ |
592a252b L |
8531 | { PREFIX_TABLE (PREFIX_VEX_0FD0) }, |
8532 | { PREFIX_TABLE (PREFIX_VEX_0FD1) }, | |
8533 | { PREFIX_TABLE (PREFIX_VEX_0FD2) }, | |
8534 | { PREFIX_TABLE (PREFIX_VEX_0FD3) }, | |
8535 | { PREFIX_TABLE (PREFIX_VEX_0FD4) }, | |
8536 | { PREFIX_TABLE (PREFIX_VEX_0FD5) }, | |
8537 | { PREFIX_TABLE (PREFIX_VEX_0FD6) }, | |
8538 | { PREFIX_TABLE (PREFIX_VEX_0FD7) }, | |
c0f3af97 | 8539 | /* d8 */ |
592a252b L |
8540 | { PREFIX_TABLE (PREFIX_VEX_0FD8) }, |
8541 | { PREFIX_TABLE (PREFIX_VEX_0FD9) }, | |
8542 | { PREFIX_TABLE (PREFIX_VEX_0FDA) }, | |
8543 | { PREFIX_TABLE (PREFIX_VEX_0FDB) }, | |
8544 | { PREFIX_TABLE (PREFIX_VEX_0FDC) }, | |
8545 | { PREFIX_TABLE (PREFIX_VEX_0FDD) }, | |
8546 | { PREFIX_TABLE (PREFIX_VEX_0FDE) }, | |
8547 | { PREFIX_TABLE (PREFIX_VEX_0FDF) }, | |
c0f3af97 | 8548 | /* e0 */ |
592a252b L |
8549 | { PREFIX_TABLE (PREFIX_VEX_0FE0) }, |
8550 | { PREFIX_TABLE (PREFIX_VEX_0FE1) }, | |
8551 | { PREFIX_TABLE (PREFIX_VEX_0FE2) }, | |
8552 | { PREFIX_TABLE (PREFIX_VEX_0FE3) }, | |
8553 | { PREFIX_TABLE (PREFIX_VEX_0FE4) }, | |
8554 | { PREFIX_TABLE (PREFIX_VEX_0FE5) }, | |
8555 | { PREFIX_TABLE (PREFIX_VEX_0FE6) }, | |
8556 | { PREFIX_TABLE (PREFIX_VEX_0FE7) }, | |
c0f3af97 | 8557 | /* e8 */ |
592a252b L |
8558 | { PREFIX_TABLE (PREFIX_VEX_0FE8) }, |
8559 | { PREFIX_TABLE (PREFIX_VEX_0FE9) }, | |
8560 | { PREFIX_TABLE (PREFIX_VEX_0FEA) }, | |
8561 | { PREFIX_TABLE (PREFIX_VEX_0FEB) }, | |
8562 | { PREFIX_TABLE (PREFIX_VEX_0FEC) }, | |
8563 | { PREFIX_TABLE (PREFIX_VEX_0FED) }, | |
8564 | { PREFIX_TABLE (PREFIX_VEX_0FEE) }, | |
8565 | { PREFIX_TABLE (PREFIX_VEX_0FEF) }, | |
c0f3af97 | 8566 | /* f0 */ |
592a252b L |
8567 | { PREFIX_TABLE (PREFIX_VEX_0FF0) }, |
8568 | { PREFIX_TABLE (PREFIX_VEX_0FF1) }, | |
8569 | { PREFIX_TABLE (PREFIX_VEX_0FF2) }, | |
8570 | { PREFIX_TABLE (PREFIX_VEX_0FF3) }, | |
8571 | { PREFIX_TABLE (PREFIX_VEX_0FF4) }, | |
8572 | { PREFIX_TABLE (PREFIX_VEX_0FF5) }, | |
8573 | { PREFIX_TABLE (PREFIX_VEX_0FF6) }, | |
8574 | { PREFIX_TABLE (PREFIX_VEX_0FF7) }, | |
c0f3af97 | 8575 | /* f8 */ |
592a252b L |
8576 | { PREFIX_TABLE (PREFIX_VEX_0FF8) }, |
8577 | { PREFIX_TABLE (PREFIX_VEX_0FF9) }, | |
8578 | { PREFIX_TABLE (PREFIX_VEX_0FFA) }, | |
8579 | { PREFIX_TABLE (PREFIX_VEX_0FFB) }, | |
8580 | { PREFIX_TABLE (PREFIX_VEX_0FFC) }, | |
8581 | { PREFIX_TABLE (PREFIX_VEX_0FFD) }, | |
8582 | { PREFIX_TABLE (PREFIX_VEX_0FFE) }, | |
592d1631 | 8583 | { Bad_Opcode }, |
c0f3af97 L |
8584 | }, |
8585 | /* VEX_0F38 */ | |
8586 | { | |
8587 | /* 00 */ | |
592a252b L |
8588 | { PREFIX_TABLE (PREFIX_VEX_0F3800) }, |
8589 | { PREFIX_TABLE (PREFIX_VEX_0F3801) }, | |
8590 | { PREFIX_TABLE (PREFIX_VEX_0F3802) }, | |
8591 | { PREFIX_TABLE (PREFIX_VEX_0F3803) }, | |
8592 | { PREFIX_TABLE (PREFIX_VEX_0F3804) }, | |
8593 | { PREFIX_TABLE (PREFIX_VEX_0F3805) }, | |
8594 | { PREFIX_TABLE (PREFIX_VEX_0F3806) }, | |
8595 | { PREFIX_TABLE (PREFIX_VEX_0F3807) }, | |
c0f3af97 | 8596 | /* 08 */ |
592a252b L |
8597 | { PREFIX_TABLE (PREFIX_VEX_0F3808) }, |
8598 | { PREFIX_TABLE (PREFIX_VEX_0F3809) }, | |
8599 | { PREFIX_TABLE (PREFIX_VEX_0F380A) }, | |
8600 | { PREFIX_TABLE (PREFIX_VEX_0F380B) }, | |
8601 | { PREFIX_TABLE (PREFIX_VEX_0F380C) }, | |
8602 | { PREFIX_TABLE (PREFIX_VEX_0F380D) }, | |
8603 | { PREFIX_TABLE (PREFIX_VEX_0F380E) }, | |
8604 | { PREFIX_TABLE (PREFIX_VEX_0F380F) }, | |
c0f3af97 | 8605 | /* 10 */ |
592d1631 L |
8606 | { Bad_Opcode }, |
8607 | { Bad_Opcode }, | |
8608 | { Bad_Opcode }, | |
592a252b | 8609 | { PREFIX_TABLE (PREFIX_VEX_0F3813) }, |
592d1631 L |
8610 | { Bad_Opcode }, |
8611 | { Bad_Opcode }, | |
6c30d220 | 8612 | { PREFIX_TABLE (PREFIX_VEX_0F3816) }, |
592a252b | 8613 | { PREFIX_TABLE (PREFIX_VEX_0F3817) }, |
c0f3af97 | 8614 | /* 18 */ |
592a252b L |
8615 | { PREFIX_TABLE (PREFIX_VEX_0F3818) }, |
8616 | { PREFIX_TABLE (PREFIX_VEX_0F3819) }, | |
8617 | { PREFIX_TABLE (PREFIX_VEX_0F381A) }, | |
592d1631 | 8618 | { Bad_Opcode }, |
592a252b L |
8619 | { PREFIX_TABLE (PREFIX_VEX_0F381C) }, |
8620 | { PREFIX_TABLE (PREFIX_VEX_0F381D) }, | |
8621 | { PREFIX_TABLE (PREFIX_VEX_0F381E) }, | |
592d1631 | 8622 | { Bad_Opcode }, |
c0f3af97 | 8623 | /* 20 */ |
592a252b L |
8624 | { PREFIX_TABLE (PREFIX_VEX_0F3820) }, |
8625 | { PREFIX_TABLE (PREFIX_VEX_0F3821) }, | |
8626 | { PREFIX_TABLE (PREFIX_VEX_0F3822) }, | |
8627 | { PREFIX_TABLE (PREFIX_VEX_0F3823) }, | |
8628 | { PREFIX_TABLE (PREFIX_VEX_0F3824) }, | |
8629 | { PREFIX_TABLE (PREFIX_VEX_0F3825) }, | |
592d1631 L |
8630 | { Bad_Opcode }, |
8631 | { Bad_Opcode }, | |
c0f3af97 | 8632 | /* 28 */ |
592a252b L |
8633 | { PREFIX_TABLE (PREFIX_VEX_0F3828) }, |
8634 | { PREFIX_TABLE (PREFIX_VEX_0F3829) }, | |
8635 | { PREFIX_TABLE (PREFIX_VEX_0F382A) }, | |
8636 | { PREFIX_TABLE (PREFIX_VEX_0F382B) }, | |
8637 | { PREFIX_TABLE (PREFIX_VEX_0F382C) }, | |
8638 | { PREFIX_TABLE (PREFIX_VEX_0F382D) }, | |
8639 | { PREFIX_TABLE (PREFIX_VEX_0F382E) }, | |
8640 | { PREFIX_TABLE (PREFIX_VEX_0F382F) }, | |
c0f3af97 | 8641 | /* 30 */ |
592a252b L |
8642 | { PREFIX_TABLE (PREFIX_VEX_0F3830) }, |
8643 | { PREFIX_TABLE (PREFIX_VEX_0F3831) }, | |
8644 | { PREFIX_TABLE (PREFIX_VEX_0F3832) }, | |
8645 | { PREFIX_TABLE (PREFIX_VEX_0F3833) }, | |
8646 | { PREFIX_TABLE (PREFIX_VEX_0F3834) }, | |
8647 | { PREFIX_TABLE (PREFIX_VEX_0F3835) }, | |
6c30d220 | 8648 | { PREFIX_TABLE (PREFIX_VEX_0F3836) }, |
592a252b | 8649 | { PREFIX_TABLE (PREFIX_VEX_0F3837) }, |
c0f3af97 | 8650 | /* 38 */ |
592a252b L |
8651 | { PREFIX_TABLE (PREFIX_VEX_0F3838) }, |
8652 | { PREFIX_TABLE (PREFIX_VEX_0F3839) }, | |
8653 | { PREFIX_TABLE (PREFIX_VEX_0F383A) }, | |
8654 | { PREFIX_TABLE (PREFIX_VEX_0F383B) }, | |
8655 | { PREFIX_TABLE (PREFIX_VEX_0F383C) }, | |
8656 | { PREFIX_TABLE (PREFIX_VEX_0F383D) }, | |
8657 | { PREFIX_TABLE (PREFIX_VEX_0F383E) }, | |
8658 | { PREFIX_TABLE (PREFIX_VEX_0F383F) }, | |
c0f3af97 | 8659 | /* 40 */ |
592a252b L |
8660 | { PREFIX_TABLE (PREFIX_VEX_0F3840) }, |
8661 | { PREFIX_TABLE (PREFIX_VEX_0F3841) }, | |
592d1631 L |
8662 | { Bad_Opcode }, |
8663 | { Bad_Opcode }, | |
8664 | { Bad_Opcode }, | |
6c30d220 L |
8665 | { PREFIX_TABLE (PREFIX_VEX_0F3845) }, |
8666 | { PREFIX_TABLE (PREFIX_VEX_0F3846) }, | |
8667 | { PREFIX_TABLE (PREFIX_VEX_0F3847) }, | |
c0f3af97 | 8668 | /* 48 */ |
592d1631 L |
8669 | { Bad_Opcode }, |
8670 | { Bad_Opcode }, | |
8671 | { Bad_Opcode }, | |
8672 | { Bad_Opcode }, | |
8673 | { Bad_Opcode }, | |
8674 | { Bad_Opcode }, | |
8675 | { Bad_Opcode }, | |
8676 | { Bad_Opcode }, | |
c0f3af97 | 8677 | /* 50 */ |
592d1631 L |
8678 | { Bad_Opcode }, |
8679 | { Bad_Opcode }, | |
8680 | { Bad_Opcode }, | |
8681 | { Bad_Opcode }, | |
8682 | { Bad_Opcode }, | |
8683 | { Bad_Opcode }, | |
8684 | { Bad_Opcode }, | |
8685 | { Bad_Opcode }, | |
c0f3af97 | 8686 | /* 58 */ |
6c30d220 L |
8687 | { PREFIX_TABLE (PREFIX_VEX_0F3858) }, |
8688 | { PREFIX_TABLE (PREFIX_VEX_0F3859) }, | |
8689 | { PREFIX_TABLE (PREFIX_VEX_0F385A) }, | |
592d1631 L |
8690 | { Bad_Opcode }, |
8691 | { Bad_Opcode }, | |
8692 | { Bad_Opcode }, | |
8693 | { Bad_Opcode }, | |
8694 | { Bad_Opcode }, | |
c0f3af97 | 8695 | /* 60 */ |
592d1631 L |
8696 | { Bad_Opcode }, |
8697 | { Bad_Opcode }, | |
8698 | { Bad_Opcode }, | |
8699 | { Bad_Opcode }, | |
8700 | { Bad_Opcode }, | |
8701 | { Bad_Opcode }, | |
8702 | { Bad_Opcode }, | |
8703 | { Bad_Opcode }, | |
c0f3af97 | 8704 | /* 68 */ |
592d1631 L |
8705 | { Bad_Opcode }, |
8706 | { Bad_Opcode }, | |
8707 | { Bad_Opcode }, | |
8708 | { Bad_Opcode }, | |
8709 | { Bad_Opcode }, | |
8710 | { Bad_Opcode }, | |
8711 | { Bad_Opcode }, | |
8712 | { Bad_Opcode }, | |
c0f3af97 | 8713 | /* 70 */ |
592d1631 L |
8714 | { Bad_Opcode }, |
8715 | { Bad_Opcode }, | |
8716 | { Bad_Opcode }, | |
8717 | { Bad_Opcode }, | |
8718 | { Bad_Opcode }, | |
8719 | { Bad_Opcode }, | |
8720 | { Bad_Opcode }, | |
8721 | { Bad_Opcode }, | |
c0f3af97 | 8722 | /* 78 */ |
6c30d220 L |
8723 | { PREFIX_TABLE (PREFIX_VEX_0F3878) }, |
8724 | { PREFIX_TABLE (PREFIX_VEX_0F3879) }, | |
592d1631 L |
8725 | { Bad_Opcode }, |
8726 | { Bad_Opcode }, | |
8727 | { Bad_Opcode }, | |
8728 | { Bad_Opcode }, | |
8729 | { Bad_Opcode }, | |
8730 | { Bad_Opcode }, | |
c0f3af97 | 8731 | /* 80 */ |
592d1631 L |
8732 | { Bad_Opcode }, |
8733 | { Bad_Opcode }, | |
8734 | { Bad_Opcode }, | |
8735 | { Bad_Opcode }, | |
8736 | { Bad_Opcode }, | |
8737 | { Bad_Opcode }, | |
8738 | { Bad_Opcode }, | |
8739 | { Bad_Opcode }, | |
c0f3af97 | 8740 | /* 88 */ |
592d1631 L |
8741 | { Bad_Opcode }, |
8742 | { Bad_Opcode }, | |
8743 | { Bad_Opcode }, | |
8744 | { Bad_Opcode }, | |
6c30d220 | 8745 | { PREFIX_TABLE (PREFIX_VEX_0F388C) }, |
592d1631 | 8746 | { Bad_Opcode }, |
6c30d220 | 8747 | { PREFIX_TABLE (PREFIX_VEX_0F388E) }, |
592d1631 | 8748 | { Bad_Opcode }, |
c0f3af97 | 8749 | /* 90 */ |
6c30d220 L |
8750 | { PREFIX_TABLE (PREFIX_VEX_0F3890) }, |
8751 | { PREFIX_TABLE (PREFIX_VEX_0F3891) }, | |
8752 | { PREFIX_TABLE (PREFIX_VEX_0F3892) }, | |
8753 | { PREFIX_TABLE (PREFIX_VEX_0F3893) }, | |
592d1631 L |
8754 | { Bad_Opcode }, |
8755 | { Bad_Opcode }, | |
592a252b L |
8756 | { PREFIX_TABLE (PREFIX_VEX_0F3896) }, |
8757 | { PREFIX_TABLE (PREFIX_VEX_0F3897) }, | |
c0f3af97 | 8758 | /* 98 */ |
592a252b L |
8759 | { PREFIX_TABLE (PREFIX_VEX_0F3898) }, |
8760 | { PREFIX_TABLE (PREFIX_VEX_0F3899) }, | |
8761 | { PREFIX_TABLE (PREFIX_VEX_0F389A) }, | |
8762 | { PREFIX_TABLE (PREFIX_VEX_0F389B) }, | |
8763 | { PREFIX_TABLE (PREFIX_VEX_0F389C) }, | |
8764 | { PREFIX_TABLE (PREFIX_VEX_0F389D) }, | |
8765 | { PREFIX_TABLE (PREFIX_VEX_0F389E) }, | |
8766 | { PREFIX_TABLE (PREFIX_VEX_0F389F) }, | |
c0f3af97 | 8767 | /* a0 */ |
592d1631 L |
8768 | { Bad_Opcode }, |
8769 | { Bad_Opcode }, | |
8770 | { Bad_Opcode }, | |
8771 | { Bad_Opcode }, | |
8772 | { Bad_Opcode }, | |
8773 | { Bad_Opcode }, | |
592a252b L |
8774 | { PREFIX_TABLE (PREFIX_VEX_0F38A6) }, |
8775 | { PREFIX_TABLE (PREFIX_VEX_0F38A7) }, | |
c0f3af97 | 8776 | /* a8 */ |
592a252b L |
8777 | { PREFIX_TABLE (PREFIX_VEX_0F38A8) }, |
8778 | { PREFIX_TABLE (PREFIX_VEX_0F38A9) }, | |
8779 | { PREFIX_TABLE (PREFIX_VEX_0F38AA) }, | |
8780 | { PREFIX_TABLE (PREFIX_VEX_0F38AB) }, | |
8781 | { PREFIX_TABLE (PREFIX_VEX_0F38AC) }, | |
8782 | { PREFIX_TABLE (PREFIX_VEX_0F38AD) }, | |
8783 | { PREFIX_TABLE (PREFIX_VEX_0F38AE) }, | |
8784 | { PREFIX_TABLE (PREFIX_VEX_0F38AF) }, | |
c0f3af97 | 8785 | /* b0 */ |
592d1631 L |
8786 | { Bad_Opcode }, |
8787 | { Bad_Opcode }, | |
8788 | { Bad_Opcode }, | |
8789 | { Bad_Opcode }, | |
8790 | { Bad_Opcode }, | |
8791 | { Bad_Opcode }, | |
592a252b L |
8792 | { PREFIX_TABLE (PREFIX_VEX_0F38B6) }, |
8793 | { PREFIX_TABLE (PREFIX_VEX_0F38B7) }, | |
c0f3af97 | 8794 | /* b8 */ |
592a252b L |
8795 | { PREFIX_TABLE (PREFIX_VEX_0F38B8) }, |
8796 | { PREFIX_TABLE (PREFIX_VEX_0F38B9) }, | |
8797 | { PREFIX_TABLE (PREFIX_VEX_0F38BA) }, | |
8798 | { PREFIX_TABLE (PREFIX_VEX_0F38BB) }, | |
8799 | { PREFIX_TABLE (PREFIX_VEX_0F38BC) }, | |
8800 | { PREFIX_TABLE (PREFIX_VEX_0F38BD) }, | |
8801 | { PREFIX_TABLE (PREFIX_VEX_0F38BE) }, | |
8802 | { PREFIX_TABLE (PREFIX_VEX_0F38BF) }, | |
c0f3af97 | 8803 | /* c0 */ |
592d1631 L |
8804 | { Bad_Opcode }, |
8805 | { Bad_Opcode }, | |
8806 | { Bad_Opcode }, | |
8807 | { Bad_Opcode }, | |
8808 | { Bad_Opcode }, | |
8809 | { Bad_Opcode }, | |
8810 | { Bad_Opcode }, | |
8811 | { Bad_Opcode }, | |
c0f3af97 | 8812 | /* c8 */ |
592d1631 L |
8813 | { Bad_Opcode }, |
8814 | { Bad_Opcode }, | |
8815 | { Bad_Opcode }, | |
8816 | { Bad_Opcode }, | |
8817 | { Bad_Opcode }, | |
8818 | { Bad_Opcode }, | |
8819 | { Bad_Opcode }, | |
48521003 | 8820 | { PREFIX_TABLE (PREFIX_VEX_0F38CF) }, |
c0f3af97 | 8821 | /* d0 */ |
592d1631 L |
8822 | { Bad_Opcode }, |
8823 | { Bad_Opcode }, | |
8824 | { Bad_Opcode }, | |
8825 | { Bad_Opcode }, | |
8826 | { Bad_Opcode }, | |
8827 | { Bad_Opcode }, | |
8828 | { Bad_Opcode }, | |
8829 | { Bad_Opcode }, | |
c0f3af97 | 8830 | /* d8 */ |
592d1631 L |
8831 | { Bad_Opcode }, |
8832 | { Bad_Opcode }, | |
8833 | { Bad_Opcode }, | |
592a252b L |
8834 | { PREFIX_TABLE (PREFIX_VEX_0F38DB) }, |
8835 | { PREFIX_TABLE (PREFIX_VEX_0F38DC) }, | |
8836 | { PREFIX_TABLE (PREFIX_VEX_0F38DD) }, | |
8837 | { PREFIX_TABLE (PREFIX_VEX_0F38DE) }, | |
8838 | { PREFIX_TABLE (PREFIX_VEX_0F38DF) }, | |
c0f3af97 | 8839 | /* e0 */ |
592d1631 L |
8840 | { Bad_Opcode }, |
8841 | { Bad_Opcode }, | |
8842 | { Bad_Opcode }, | |
8843 | { Bad_Opcode }, | |
8844 | { Bad_Opcode }, | |
8845 | { Bad_Opcode }, | |
8846 | { Bad_Opcode }, | |
8847 | { Bad_Opcode }, | |
c0f3af97 | 8848 | /* e8 */ |
592d1631 L |
8849 | { Bad_Opcode }, |
8850 | { Bad_Opcode }, | |
8851 | { Bad_Opcode }, | |
8852 | { Bad_Opcode }, | |
8853 | { Bad_Opcode }, | |
8854 | { Bad_Opcode }, | |
8855 | { Bad_Opcode }, | |
8856 | { Bad_Opcode }, | |
c0f3af97 | 8857 | /* f0 */ |
592d1631 L |
8858 | { Bad_Opcode }, |
8859 | { Bad_Opcode }, | |
f12dc422 L |
8860 | { PREFIX_TABLE (PREFIX_VEX_0F38F2) }, |
8861 | { REG_TABLE (REG_VEX_0F38F3) }, | |
592d1631 | 8862 | { Bad_Opcode }, |
6c30d220 L |
8863 | { PREFIX_TABLE (PREFIX_VEX_0F38F5) }, |
8864 | { PREFIX_TABLE (PREFIX_VEX_0F38F6) }, | |
f12dc422 | 8865 | { PREFIX_TABLE (PREFIX_VEX_0F38F7) }, |
c0f3af97 | 8866 | /* f8 */ |
592d1631 L |
8867 | { Bad_Opcode }, |
8868 | { Bad_Opcode }, | |
8869 | { Bad_Opcode }, | |
8870 | { Bad_Opcode }, | |
8871 | { Bad_Opcode }, | |
8872 | { Bad_Opcode }, | |
8873 | { Bad_Opcode }, | |
8874 | { Bad_Opcode }, | |
c0f3af97 L |
8875 | }, |
8876 | /* VEX_0F3A */ | |
8877 | { | |
8878 | /* 00 */ | |
6c30d220 L |
8879 | { PREFIX_TABLE (PREFIX_VEX_0F3A00) }, |
8880 | { PREFIX_TABLE (PREFIX_VEX_0F3A01) }, | |
8881 | { PREFIX_TABLE (PREFIX_VEX_0F3A02) }, | |
592d1631 | 8882 | { Bad_Opcode }, |
592a252b L |
8883 | { PREFIX_TABLE (PREFIX_VEX_0F3A04) }, |
8884 | { PREFIX_TABLE (PREFIX_VEX_0F3A05) }, | |
8885 | { PREFIX_TABLE (PREFIX_VEX_0F3A06) }, | |
592d1631 | 8886 | { Bad_Opcode }, |
c0f3af97 | 8887 | /* 08 */ |
592a252b L |
8888 | { PREFIX_TABLE (PREFIX_VEX_0F3A08) }, |
8889 | { PREFIX_TABLE (PREFIX_VEX_0F3A09) }, | |
8890 | { PREFIX_TABLE (PREFIX_VEX_0F3A0A) }, | |
8891 | { PREFIX_TABLE (PREFIX_VEX_0F3A0B) }, | |
8892 | { PREFIX_TABLE (PREFIX_VEX_0F3A0C) }, | |
8893 | { PREFIX_TABLE (PREFIX_VEX_0F3A0D) }, | |
8894 | { PREFIX_TABLE (PREFIX_VEX_0F3A0E) }, | |
8895 | { PREFIX_TABLE (PREFIX_VEX_0F3A0F) }, | |
c0f3af97 | 8896 | /* 10 */ |
592d1631 L |
8897 | { Bad_Opcode }, |
8898 | { Bad_Opcode }, | |
8899 | { Bad_Opcode }, | |
8900 | { Bad_Opcode }, | |
592a252b L |
8901 | { PREFIX_TABLE (PREFIX_VEX_0F3A14) }, |
8902 | { PREFIX_TABLE (PREFIX_VEX_0F3A15) }, | |
8903 | { PREFIX_TABLE (PREFIX_VEX_0F3A16) }, | |
8904 | { PREFIX_TABLE (PREFIX_VEX_0F3A17) }, | |
c0f3af97 | 8905 | /* 18 */ |
592a252b L |
8906 | { PREFIX_TABLE (PREFIX_VEX_0F3A18) }, |
8907 | { PREFIX_TABLE (PREFIX_VEX_0F3A19) }, | |
592d1631 L |
8908 | { Bad_Opcode }, |
8909 | { Bad_Opcode }, | |
8910 | { Bad_Opcode }, | |
592a252b | 8911 | { PREFIX_TABLE (PREFIX_VEX_0F3A1D) }, |
592d1631 L |
8912 | { Bad_Opcode }, |
8913 | { Bad_Opcode }, | |
c0f3af97 | 8914 | /* 20 */ |
592a252b L |
8915 | { PREFIX_TABLE (PREFIX_VEX_0F3A20) }, |
8916 | { PREFIX_TABLE (PREFIX_VEX_0F3A21) }, | |
8917 | { PREFIX_TABLE (PREFIX_VEX_0F3A22) }, | |
592d1631 L |
8918 | { Bad_Opcode }, |
8919 | { Bad_Opcode }, | |
8920 | { Bad_Opcode }, | |
8921 | { Bad_Opcode }, | |
8922 | { Bad_Opcode }, | |
c0f3af97 | 8923 | /* 28 */ |
592d1631 L |
8924 | { Bad_Opcode }, |
8925 | { Bad_Opcode }, | |
8926 | { Bad_Opcode }, | |
8927 | { Bad_Opcode }, | |
8928 | { Bad_Opcode }, | |
8929 | { Bad_Opcode }, | |
8930 | { Bad_Opcode }, | |
8931 | { Bad_Opcode }, | |
c0f3af97 | 8932 | /* 30 */ |
43234a1e | 8933 | { PREFIX_TABLE (PREFIX_VEX_0F3A30) }, |
1ba585e8 | 8934 | { PREFIX_TABLE (PREFIX_VEX_0F3A31) }, |
43234a1e | 8935 | { PREFIX_TABLE (PREFIX_VEX_0F3A32) }, |
1ba585e8 | 8936 | { PREFIX_TABLE (PREFIX_VEX_0F3A33) }, |
592d1631 L |
8937 | { Bad_Opcode }, |
8938 | { Bad_Opcode }, | |
8939 | { Bad_Opcode }, | |
8940 | { Bad_Opcode }, | |
c0f3af97 | 8941 | /* 38 */ |
6c30d220 L |
8942 | { PREFIX_TABLE (PREFIX_VEX_0F3A38) }, |
8943 | { PREFIX_TABLE (PREFIX_VEX_0F3A39) }, | |
592d1631 L |
8944 | { Bad_Opcode }, |
8945 | { Bad_Opcode }, | |
8946 | { Bad_Opcode }, | |
8947 | { Bad_Opcode }, | |
8948 | { Bad_Opcode }, | |
8949 | { Bad_Opcode }, | |
c0f3af97 | 8950 | /* 40 */ |
592a252b L |
8951 | { PREFIX_TABLE (PREFIX_VEX_0F3A40) }, |
8952 | { PREFIX_TABLE (PREFIX_VEX_0F3A41) }, | |
8953 | { PREFIX_TABLE (PREFIX_VEX_0F3A42) }, | |
592d1631 | 8954 | { Bad_Opcode }, |
592a252b | 8955 | { PREFIX_TABLE (PREFIX_VEX_0F3A44) }, |
592d1631 | 8956 | { Bad_Opcode }, |
6c30d220 | 8957 | { PREFIX_TABLE (PREFIX_VEX_0F3A46) }, |
592d1631 | 8958 | { Bad_Opcode }, |
c0f3af97 | 8959 | /* 48 */ |
592a252b L |
8960 | { PREFIX_TABLE (PREFIX_VEX_0F3A48) }, |
8961 | { PREFIX_TABLE (PREFIX_VEX_0F3A49) }, | |
8962 | { PREFIX_TABLE (PREFIX_VEX_0F3A4A) }, | |
8963 | { PREFIX_TABLE (PREFIX_VEX_0F3A4B) }, | |
8964 | { PREFIX_TABLE (PREFIX_VEX_0F3A4C) }, | |
592d1631 L |
8965 | { Bad_Opcode }, |
8966 | { Bad_Opcode }, | |
8967 | { Bad_Opcode }, | |
c0f3af97 | 8968 | /* 50 */ |
592d1631 L |
8969 | { Bad_Opcode }, |
8970 | { Bad_Opcode }, | |
8971 | { Bad_Opcode }, | |
8972 | { Bad_Opcode }, | |
8973 | { Bad_Opcode }, | |
8974 | { Bad_Opcode }, | |
8975 | { Bad_Opcode }, | |
8976 | { Bad_Opcode }, | |
c0f3af97 | 8977 | /* 58 */ |
592d1631 L |
8978 | { Bad_Opcode }, |
8979 | { Bad_Opcode }, | |
8980 | { Bad_Opcode }, | |
8981 | { Bad_Opcode }, | |
592a252b L |
8982 | { PREFIX_TABLE (PREFIX_VEX_0F3A5C) }, |
8983 | { PREFIX_TABLE (PREFIX_VEX_0F3A5D) }, | |
8984 | { PREFIX_TABLE (PREFIX_VEX_0F3A5E) }, | |
8985 | { PREFIX_TABLE (PREFIX_VEX_0F3A5F) }, | |
c0f3af97 | 8986 | /* 60 */ |
592a252b L |
8987 | { PREFIX_TABLE (PREFIX_VEX_0F3A60) }, |
8988 | { PREFIX_TABLE (PREFIX_VEX_0F3A61) }, | |
8989 | { PREFIX_TABLE (PREFIX_VEX_0F3A62) }, | |
8990 | { PREFIX_TABLE (PREFIX_VEX_0F3A63) }, | |
592d1631 L |
8991 | { Bad_Opcode }, |
8992 | { Bad_Opcode }, | |
8993 | { Bad_Opcode }, | |
8994 | { Bad_Opcode }, | |
c0f3af97 | 8995 | /* 68 */ |
592a252b L |
8996 | { PREFIX_TABLE (PREFIX_VEX_0F3A68) }, |
8997 | { PREFIX_TABLE (PREFIX_VEX_0F3A69) }, | |
8998 | { PREFIX_TABLE (PREFIX_VEX_0F3A6A) }, | |
8999 | { PREFIX_TABLE (PREFIX_VEX_0F3A6B) }, | |
9000 | { PREFIX_TABLE (PREFIX_VEX_0F3A6C) }, | |
9001 | { PREFIX_TABLE (PREFIX_VEX_0F3A6D) }, | |
9002 | { PREFIX_TABLE (PREFIX_VEX_0F3A6E) }, | |
9003 | { PREFIX_TABLE (PREFIX_VEX_0F3A6F) }, | |
c0f3af97 | 9004 | /* 70 */ |
592d1631 L |
9005 | { Bad_Opcode }, |
9006 | { Bad_Opcode }, | |
9007 | { Bad_Opcode }, | |
9008 | { Bad_Opcode }, | |
9009 | { Bad_Opcode }, | |
9010 | { Bad_Opcode }, | |
9011 | { Bad_Opcode }, | |
9012 | { Bad_Opcode }, | |
c0f3af97 | 9013 | /* 78 */ |
592a252b L |
9014 | { PREFIX_TABLE (PREFIX_VEX_0F3A78) }, |
9015 | { PREFIX_TABLE (PREFIX_VEX_0F3A79) }, | |
9016 | { PREFIX_TABLE (PREFIX_VEX_0F3A7A) }, | |
9017 | { PREFIX_TABLE (PREFIX_VEX_0F3A7B) }, | |
9018 | { PREFIX_TABLE (PREFIX_VEX_0F3A7C) }, | |
9019 | { PREFIX_TABLE (PREFIX_VEX_0F3A7D) }, | |
9020 | { PREFIX_TABLE (PREFIX_VEX_0F3A7E) }, | |
9021 | { PREFIX_TABLE (PREFIX_VEX_0F3A7F) }, | |
c0f3af97 | 9022 | /* 80 */ |
592d1631 L |
9023 | { Bad_Opcode }, |
9024 | { Bad_Opcode }, | |
9025 | { Bad_Opcode }, | |
9026 | { Bad_Opcode }, | |
9027 | { Bad_Opcode }, | |
9028 | { Bad_Opcode }, | |
9029 | { Bad_Opcode }, | |
9030 | { Bad_Opcode }, | |
c0f3af97 | 9031 | /* 88 */ |
592d1631 L |
9032 | { Bad_Opcode }, |
9033 | { Bad_Opcode }, | |
9034 | { Bad_Opcode }, | |
9035 | { Bad_Opcode }, | |
9036 | { Bad_Opcode }, | |
9037 | { Bad_Opcode }, | |
9038 | { Bad_Opcode }, | |
9039 | { Bad_Opcode }, | |
c0f3af97 | 9040 | /* 90 */ |
592d1631 L |
9041 | { Bad_Opcode }, |
9042 | { Bad_Opcode }, | |
9043 | { Bad_Opcode }, | |
9044 | { Bad_Opcode }, | |
9045 | { Bad_Opcode }, | |
9046 | { Bad_Opcode }, | |
9047 | { Bad_Opcode }, | |
9048 | { Bad_Opcode }, | |
c0f3af97 | 9049 | /* 98 */ |
592d1631 L |
9050 | { Bad_Opcode }, |
9051 | { Bad_Opcode }, | |
9052 | { Bad_Opcode }, | |
9053 | { Bad_Opcode }, | |
9054 | { Bad_Opcode }, | |
9055 | { Bad_Opcode }, | |
9056 | { Bad_Opcode }, | |
9057 | { Bad_Opcode }, | |
c0f3af97 | 9058 | /* a0 */ |
592d1631 L |
9059 | { Bad_Opcode }, |
9060 | { Bad_Opcode }, | |
9061 | { Bad_Opcode }, | |
9062 | { Bad_Opcode }, | |
9063 | { Bad_Opcode }, | |
9064 | { Bad_Opcode }, | |
9065 | { Bad_Opcode }, | |
9066 | { Bad_Opcode }, | |
c0f3af97 | 9067 | /* a8 */ |
592d1631 L |
9068 | { Bad_Opcode }, |
9069 | { Bad_Opcode }, | |
9070 | { Bad_Opcode }, | |
9071 | { Bad_Opcode }, | |
9072 | { Bad_Opcode }, | |
9073 | { Bad_Opcode }, | |
9074 | { Bad_Opcode }, | |
9075 | { Bad_Opcode }, | |
c0f3af97 | 9076 | /* b0 */ |
592d1631 L |
9077 | { Bad_Opcode }, |
9078 | { Bad_Opcode }, | |
9079 | { Bad_Opcode }, | |
9080 | { Bad_Opcode }, | |
9081 | { Bad_Opcode }, | |
9082 | { Bad_Opcode }, | |
9083 | { Bad_Opcode }, | |
9084 | { Bad_Opcode }, | |
c0f3af97 | 9085 | /* b8 */ |
592d1631 L |
9086 | { Bad_Opcode }, |
9087 | { Bad_Opcode }, | |
9088 | { Bad_Opcode }, | |
9089 | { Bad_Opcode }, | |
9090 | { Bad_Opcode }, | |
9091 | { Bad_Opcode }, | |
9092 | { Bad_Opcode }, | |
9093 | { Bad_Opcode }, | |
c0f3af97 | 9094 | /* c0 */ |
592d1631 L |
9095 | { Bad_Opcode }, |
9096 | { Bad_Opcode }, | |
9097 | { Bad_Opcode }, | |
9098 | { Bad_Opcode }, | |
9099 | { Bad_Opcode }, | |
9100 | { Bad_Opcode }, | |
9101 | { Bad_Opcode }, | |
9102 | { Bad_Opcode }, | |
c0f3af97 | 9103 | /* c8 */ |
592d1631 L |
9104 | { Bad_Opcode }, |
9105 | { Bad_Opcode }, | |
9106 | { Bad_Opcode }, | |
9107 | { Bad_Opcode }, | |
9108 | { Bad_Opcode }, | |
9109 | { Bad_Opcode }, | |
48521003 IT |
9110 | { PREFIX_TABLE(PREFIX_VEX_0F3ACE) }, |
9111 | { PREFIX_TABLE(PREFIX_VEX_0F3ACF) }, | |
c0f3af97 | 9112 | /* d0 */ |
592d1631 L |
9113 | { Bad_Opcode }, |
9114 | { Bad_Opcode }, | |
9115 | { Bad_Opcode }, | |
9116 | { Bad_Opcode }, | |
9117 | { Bad_Opcode }, | |
9118 | { Bad_Opcode }, | |
9119 | { Bad_Opcode }, | |
9120 | { Bad_Opcode }, | |
c0f3af97 | 9121 | /* d8 */ |
592d1631 L |
9122 | { Bad_Opcode }, |
9123 | { Bad_Opcode }, | |
9124 | { Bad_Opcode }, | |
9125 | { Bad_Opcode }, | |
9126 | { Bad_Opcode }, | |
9127 | { Bad_Opcode }, | |
9128 | { Bad_Opcode }, | |
592a252b | 9129 | { PREFIX_TABLE (PREFIX_VEX_0F3ADF) }, |
c0f3af97 | 9130 | /* e0 */ |
592d1631 L |
9131 | { Bad_Opcode }, |
9132 | { Bad_Opcode }, | |
9133 | { Bad_Opcode }, | |
9134 | { Bad_Opcode }, | |
9135 | { Bad_Opcode }, | |
9136 | { Bad_Opcode }, | |
9137 | { Bad_Opcode }, | |
9138 | { Bad_Opcode }, | |
c0f3af97 | 9139 | /* e8 */ |
592d1631 L |
9140 | { Bad_Opcode }, |
9141 | { Bad_Opcode }, | |
9142 | { Bad_Opcode }, | |
9143 | { Bad_Opcode }, | |
9144 | { Bad_Opcode }, | |
9145 | { Bad_Opcode }, | |
9146 | { Bad_Opcode }, | |
9147 | { Bad_Opcode }, | |
c0f3af97 | 9148 | /* f0 */ |
6c30d220 | 9149 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0) }, |
592d1631 L |
9150 | { Bad_Opcode }, |
9151 | { Bad_Opcode }, | |
9152 | { Bad_Opcode }, | |
9153 | { Bad_Opcode }, | |
9154 | { Bad_Opcode }, | |
9155 | { Bad_Opcode }, | |
9156 | { Bad_Opcode }, | |
c0f3af97 | 9157 | /* f8 */ |
592d1631 L |
9158 | { Bad_Opcode }, |
9159 | { Bad_Opcode }, | |
9160 | { Bad_Opcode }, | |
9161 | { Bad_Opcode }, | |
9162 | { Bad_Opcode }, | |
9163 | { Bad_Opcode }, | |
9164 | { Bad_Opcode }, | |
9165 | { Bad_Opcode }, | |
c0f3af97 L |
9166 | }, |
9167 | }; | |
9168 | ||
43234a1e | 9169 | #include "i386-dis-evex.h" |
ad692897 | 9170 | |
c0f3af97 | 9171 | static const struct dis386 vex_len_table[][2] = { |
18897deb | 9172 | /* VEX_LEN_0F12_P_0_M_0 / VEX_LEN_0F12_P_2_M_0 */ |
c0f3af97 | 9173 | { |
18897deb | 9174 | { "vmovlpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9175 | }, |
9176 | ||
592a252b | 9177 | /* VEX_LEN_0F12_P_0_M_1 */ |
c0f3af97 | 9178 | { |
ec6f095a | 9179 | { "vmovhlps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9180 | }, |
9181 | ||
592a252b | 9182 | /* VEX_LEN_0F13_M_0 */ |
c0f3af97 | 9183 | { |
bf926894 | 9184 | { "vmovlpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9185 | }, |
9186 | ||
18897deb | 9187 | /* VEX_LEN_0F16_P_0_M_0 / VEX_LEN_0F16_P_2_M_0 */ |
c0f3af97 | 9188 | { |
18897deb | 9189 | { "vmovhpX", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9190 | }, |
9191 | ||
592a252b | 9192 | /* VEX_LEN_0F16_P_0_M_1 */ |
c0f3af97 | 9193 | { |
ec6f095a | 9194 | { "vmovlhps", { XM, Vex128, EXq }, 0 }, |
c0f3af97 L |
9195 | }, |
9196 | ||
592a252b | 9197 | /* VEX_LEN_0F17_M_0 */ |
c0f3af97 | 9198 | { |
bf926894 | 9199 | { "vmovhpX", { EXq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
9200 | }, |
9201 | ||
43234a1e L |
9202 | /* VEX_LEN_0F41_P_0 */ |
9203 | { | |
9204 | { Bad_Opcode }, | |
9205 | { VEX_W_TABLE (VEX_W_0F41_P_0_LEN_1) }, | |
9206 | }, | |
1ba585e8 IT |
9207 | /* VEX_LEN_0F41_P_2 */ |
9208 | { | |
9209 | { Bad_Opcode }, | |
9210 | { VEX_W_TABLE (VEX_W_0F41_P_2_LEN_1) }, | |
9211 | }, | |
43234a1e L |
9212 | /* VEX_LEN_0F42_P_0 */ |
9213 | { | |
9214 | { Bad_Opcode }, | |
9215 | { VEX_W_TABLE (VEX_W_0F42_P_0_LEN_1) }, | |
9216 | }, | |
1ba585e8 IT |
9217 | /* VEX_LEN_0F42_P_2 */ |
9218 | { | |
9219 | { Bad_Opcode }, | |
9220 | { VEX_W_TABLE (VEX_W_0F42_P_2_LEN_1) }, | |
9221 | }, | |
43234a1e L |
9222 | /* VEX_LEN_0F44_P_0 */ |
9223 | { | |
9224 | { VEX_W_TABLE (VEX_W_0F44_P_0_LEN_0) }, | |
9225 | }, | |
1ba585e8 IT |
9226 | /* VEX_LEN_0F44_P_2 */ |
9227 | { | |
9228 | { VEX_W_TABLE (VEX_W_0F44_P_2_LEN_0) }, | |
9229 | }, | |
43234a1e L |
9230 | /* VEX_LEN_0F45_P_0 */ |
9231 | { | |
9232 | { Bad_Opcode }, | |
9233 | { VEX_W_TABLE (VEX_W_0F45_P_0_LEN_1) }, | |
9234 | }, | |
1ba585e8 IT |
9235 | /* VEX_LEN_0F45_P_2 */ |
9236 | { | |
9237 | { Bad_Opcode }, | |
9238 | { VEX_W_TABLE (VEX_W_0F45_P_2_LEN_1) }, | |
9239 | }, | |
43234a1e L |
9240 | /* VEX_LEN_0F46_P_0 */ |
9241 | { | |
9242 | { Bad_Opcode }, | |
9243 | { VEX_W_TABLE (VEX_W_0F46_P_0_LEN_1) }, | |
9244 | }, | |
1ba585e8 IT |
9245 | /* VEX_LEN_0F46_P_2 */ |
9246 | { | |
9247 | { Bad_Opcode }, | |
9248 | { VEX_W_TABLE (VEX_W_0F46_P_2_LEN_1) }, | |
9249 | }, | |
43234a1e L |
9250 | /* VEX_LEN_0F47_P_0 */ |
9251 | { | |
9252 | { Bad_Opcode }, | |
9253 | { VEX_W_TABLE (VEX_W_0F47_P_0_LEN_1) }, | |
9254 | }, | |
1ba585e8 IT |
9255 | /* VEX_LEN_0F47_P_2 */ |
9256 | { | |
9257 | { Bad_Opcode }, | |
9258 | { VEX_W_TABLE (VEX_W_0F47_P_2_LEN_1) }, | |
9259 | }, | |
9260 | /* VEX_LEN_0F4A_P_0 */ | |
9261 | { | |
9262 | { Bad_Opcode }, | |
9263 | { VEX_W_TABLE (VEX_W_0F4A_P_0_LEN_1) }, | |
9264 | }, | |
9265 | /* VEX_LEN_0F4A_P_2 */ | |
9266 | { | |
9267 | { Bad_Opcode }, | |
9268 | { VEX_W_TABLE (VEX_W_0F4A_P_2_LEN_1) }, | |
9269 | }, | |
9270 | /* VEX_LEN_0F4B_P_0 */ | |
9271 | { | |
9272 | { Bad_Opcode }, | |
9273 | { VEX_W_TABLE (VEX_W_0F4B_P_0_LEN_1) }, | |
9274 | }, | |
43234a1e L |
9275 | /* VEX_LEN_0F4B_P_2 */ |
9276 | { | |
9277 | { Bad_Opcode }, | |
9278 | { VEX_W_TABLE (VEX_W_0F4B_P_2_LEN_1) }, | |
9279 | }, | |
9280 | ||
ec6f095a | 9281 | /* VEX_LEN_0F6E_P_2 */ |
c0f3af97 | 9282 | { |
ec6f095a | 9283 | { "vmovK", { XMScalar, Edq }, 0 }, |
c0f3af97 L |
9284 | }, |
9285 | ||
ec6f095a | 9286 | /* VEX_LEN_0F77_P_1 */ |
c0f3af97 | 9287 | { |
ec6f095a L |
9288 | { "vzeroupper", { XX }, 0 }, |
9289 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
9290 | }, |
9291 | ||
ec6f095a | 9292 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 9293 | { |
5b872f7d | 9294 | { "vmovq", { XMScalar, EXxmm_mq }, 0 }, |
c0f3af97 L |
9295 | }, |
9296 | ||
ec6f095a | 9297 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 9298 | { |
ec6f095a | 9299 | { "vmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
9300 | }, |
9301 | ||
ec6f095a | 9302 | /* VEX_LEN_0F90_P_0 */ |
c0f3af97 | 9303 | { |
ec6f095a | 9304 | { VEX_W_TABLE (VEX_W_0F90_P_0_LEN_0) }, |
c0f3af97 L |
9305 | }, |
9306 | ||
ec6f095a | 9307 | /* VEX_LEN_0F90_P_2 */ |
c0f3af97 | 9308 | { |
ec6f095a | 9309 | { VEX_W_TABLE (VEX_W_0F90_P_2_LEN_0) }, |
c0f3af97 L |
9310 | }, |
9311 | ||
ec6f095a | 9312 | /* VEX_LEN_0F91_P_0 */ |
c0f3af97 | 9313 | { |
ec6f095a | 9314 | { VEX_W_TABLE (VEX_W_0F91_P_0_LEN_0) }, |
c0f3af97 L |
9315 | }, |
9316 | ||
ec6f095a | 9317 | /* VEX_LEN_0F91_P_2 */ |
c0f3af97 | 9318 | { |
ec6f095a | 9319 | { VEX_W_TABLE (VEX_W_0F91_P_2_LEN_0) }, |
c0f3af97 L |
9320 | }, |
9321 | ||
ec6f095a | 9322 | /* VEX_LEN_0F92_P_0 */ |
c0f3af97 | 9323 | { |
ec6f095a | 9324 | { VEX_W_TABLE (VEX_W_0F92_P_0_LEN_0) }, |
c0f3af97 L |
9325 | }, |
9326 | ||
ec6f095a | 9327 | /* VEX_LEN_0F92_P_2 */ |
c0f3af97 | 9328 | { |
ec6f095a | 9329 | { VEX_W_TABLE (VEX_W_0F92_P_2_LEN_0) }, |
c0f3af97 L |
9330 | }, |
9331 | ||
ec6f095a | 9332 | /* VEX_LEN_0F92_P_3 */ |
c0f3af97 | 9333 | { |
58a211d2 | 9334 | { MOD_TABLE (MOD_VEX_0F92_P_3_LEN_0) }, |
c0f3af97 L |
9335 | }, |
9336 | ||
ec6f095a | 9337 | /* VEX_LEN_0F93_P_0 */ |
c0f3af97 | 9338 | { |
ec6f095a | 9339 | { VEX_W_TABLE (VEX_W_0F93_P_0_LEN_0) }, |
c0f3af97 L |
9340 | }, |
9341 | ||
ec6f095a | 9342 | /* VEX_LEN_0F93_P_2 */ |
c0f3af97 | 9343 | { |
ec6f095a | 9344 | { VEX_W_TABLE (VEX_W_0F93_P_2_LEN_0) }, |
c0f3af97 L |
9345 | }, |
9346 | ||
ec6f095a | 9347 | /* VEX_LEN_0F93_P_3 */ |
c0f3af97 | 9348 | { |
58a211d2 | 9349 | { MOD_TABLE (MOD_VEX_0F93_P_3_LEN_0) }, |
c0f3af97 L |
9350 | }, |
9351 | ||
ec6f095a | 9352 | /* VEX_LEN_0F98_P_0 */ |
43234a1e L |
9353 | { |
9354 | { VEX_W_TABLE (VEX_W_0F98_P_0_LEN_0) }, | |
9355 | }, | |
9356 | ||
1ba585e8 IT |
9357 | /* VEX_LEN_0F98_P_2 */ |
9358 | { | |
9359 | { VEX_W_TABLE (VEX_W_0F98_P_2_LEN_0) }, | |
9360 | }, | |
9361 | ||
9362 | /* VEX_LEN_0F99_P_0 */ | |
9363 | { | |
9364 | { VEX_W_TABLE (VEX_W_0F99_P_0_LEN_0) }, | |
9365 | }, | |
9366 | ||
9367 | /* VEX_LEN_0F99_P_2 */ | |
9368 | { | |
9369 | { VEX_W_TABLE (VEX_W_0F99_P_2_LEN_0) }, | |
9370 | }, | |
9371 | ||
6c30d220 | 9372 | /* VEX_LEN_0FAE_R_2_M_0 */ |
c0f3af97 | 9373 | { |
ec6f095a | 9374 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
9375 | }, |
9376 | ||
6c30d220 | 9377 | /* VEX_LEN_0FAE_R_3_M_0 */ |
c0f3af97 | 9378 | { |
ec6f095a | 9379 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
9380 | }, |
9381 | ||
6c30d220 | 9382 | /* VEX_LEN_0FC4_P_2 */ |
c0f3af97 | 9383 | { |
b50c9f31 | 9384 | { "vpinsrw", { XM, Vex128, Edqw, Ib }, 0 }, |
c0f3af97 L |
9385 | }, |
9386 | ||
6c30d220 | 9387 | /* VEX_LEN_0FC5_P_2 */ |
c0f3af97 | 9388 | { |
b50c9f31 | 9389 | { "vpextrw", { Gdq, XS, Ib }, 0 }, |
c0f3af97 L |
9390 | }, |
9391 | ||
6c30d220 | 9392 | /* VEX_LEN_0FD6_P_2 */ |
c0f3af97 | 9393 | { |
39e0f456 | 9394 | { "vmovq", { EXqVexScalarS, XMScalar }, 0 }, |
c0f3af97 L |
9395 | }, |
9396 | ||
6c30d220 | 9397 | /* VEX_LEN_0FF7_P_2 */ |
c0f3af97 | 9398 | { |
ec6f095a | 9399 | { "vmaskmovdqu", { XM, XS }, 0 }, |
c0f3af97 L |
9400 | }, |
9401 | ||
6c30d220 | 9402 | /* VEX_LEN_0F3816_P_2 */ |
c0f3af97 | 9403 | { |
6c30d220 L |
9404 | { Bad_Opcode }, |
9405 | { VEX_W_TABLE (VEX_W_0F3816_P_2) }, | |
c0f3af97 L |
9406 | }, |
9407 | ||
6c30d220 | 9408 | /* VEX_LEN_0F3819_P_2 */ |
c0f3af97 | 9409 | { |
6c30d220 L |
9410 | { Bad_Opcode }, |
9411 | { VEX_W_TABLE (VEX_W_0F3819_P_2) }, | |
c0f3af97 L |
9412 | }, |
9413 | ||
6c30d220 | 9414 | /* VEX_LEN_0F381A_P_2_M_0 */ |
c0f3af97 | 9415 | { |
6c30d220 L |
9416 | { Bad_Opcode }, |
9417 | { VEX_W_TABLE (VEX_W_0F381A_P_2_M_0) }, | |
c0f3af97 L |
9418 | }, |
9419 | ||
6c30d220 | 9420 | /* VEX_LEN_0F3836_P_2 */ |
c0f3af97 | 9421 | { |
6c30d220 L |
9422 | { Bad_Opcode }, |
9423 | { VEX_W_TABLE (VEX_W_0F3836_P_2) }, | |
c0f3af97 L |
9424 | }, |
9425 | ||
592a252b | 9426 | /* VEX_LEN_0F3841_P_2 */ |
c0f3af97 | 9427 | { |
ec6f095a | 9428 | { "vphminposuw", { XM, EXx }, 0 }, |
c0f3af97 L |
9429 | }, |
9430 | ||
6c30d220 L |
9431 | /* VEX_LEN_0F385A_P_2_M_0 */ |
9432 | { | |
9433 | { Bad_Opcode }, | |
9434 | { VEX_W_TABLE (VEX_W_0F385A_P_2_M_0) }, | |
9435 | }, | |
9436 | ||
592a252b | 9437 | /* VEX_LEN_0F38DB_P_2 */ |
a5ff0eb2 | 9438 | { |
ec6f095a | 9439 | { "vaesimc", { XM, EXx }, 0 }, |
a5ff0eb2 L |
9440 | }, |
9441 | ||
f12dc422 L |
9442 | /* VEX_LEN_0F38F2_P_0 */ |
9443 | { | |
bf890a93 | 9444 | { "andnS", { Gdq, VexGdq, Edq }, 0 }, |
f12dc422 L |
9445 | }, |
9446 | ||
9447 | /* VEX_LEN_0F38F3_R_1_P_0 */ | |
9448 | { | |
bf890a93 | 9449 | { "blsrS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9450 | }, |
9451 | ||
9452 | /* VEX_LEN_0F38F3_R_2_P_0 */ | |
9453 | { | |
bf890a93 | 9454 | { "blsmskS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9455 | }, |
9456 | ||
9457 | /* VEX_LEN_0F38F3_R_3_P_0 */ | |
9458 | { | |
bf890a93 | 9459 | { "blsiS", { VexGdq, Edq }, 0 }, |
f12dc422 L |
9460 | }, |
9461 | ||
6c30d220 L |
9462 | /* VEX_LEN_0F38F5_P_0 */ |
9463 | { | |
bf890a93 | 9464 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9465 | }, |
9466 | ||
9467 | /* VEX_LEN_0F38F5_P_1 */ | |
9468 | { | |
bf890a93 | 9469 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9470 | }, |
9471 | ||
9472 | /* VEX_LEN_0F38F5_P_3 */ | |
9473 | { | |
bf890a93 | 9474 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9475 | }, |
9476 | ||
9477 | /* VEX_LEN_0F38F6_P_3 */ | |
9478 | { | |
bf890a93 | 9479 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
6c30d220 L |
9480 | }, |
9481 | ||
f12dc422 L |
9482 | /* VEX_LEN_0F38F7_P_0 */ |
9483 | { | |
bf890a93 | 9484 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
f12dc422 L |
9485 | }, |
9486 | ||
6c30d220 L |
9487 | /* VEX_LEN_0F38F7_P_1 */ |
9488 | { | |
bf890a93 | 9489 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9490 | }, |
9491 | ||
9492 | /* VEX_LEN_0F38F7_P_2 */ | |
9493 | { | |
bf890a93 | 9494 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9495 | }, |
9496 | ||
9497 | /* VEX_LEN_0F38F7_P_3 */ | |
9498 | { | |
bf890a93 | 9499 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, |
6c30d220 L |
9500 | }, |
9501 | ||
9502 | /* VEX_LEN_0F3A00_P_2 */ | |
9503 | { | |
9504 | { Bad_Opcode }, | |
9505 | { VEX_W_TABLE (VEX_W_0F3A00_P_2) }, | |
9506 | }, | |
9507 | ||
9508 | /* VEX_LEN_0F3A01_P_2 */ | |
9509 | { | |
9510 | { Bad_Opcode }, | |
9511 | { VEX_W_TABLE (VEX_W_0F3A01_P_2) }, | |
9512 | }, | |
9513 | ||
592a252b | 9514 | /* VEX_LEN_0F3A06_P_2 */ |
c0f3af97 | 9515 | { |
592d1631 | 9516 | { Bad_Opcode }, |
592a252b | 9517 | { VEX_W_TABLE (VEX_W_0F3A06_P_2) }, |
c0f3af97 L |
9518 | }, |
9519 | ||
592a252b | 9520 | /* VEX_LEN_0F3A14_P_2 */ |
c0f3af97 | 9521 | { |
b50c9f31 | 9522 | { "vpextrb", { Edqb, XM, Ib }, 0 }, |
c0f3af97 L |
9523 | }, |
9524 | ||
592a252b | 9525 | /* VEX_LEN_0F3A15_P_2 */ |
c0f3af97 | 9526 | { |
b50c9f31 | 9527 | { "vpextrw", { Edqw, XM, Ib }, 0 }, |
c0f3af97 L |
9528 | }, |
9529 | ||
592a252b | 9530 | /* VEX_LEN_0F3A16_P_2 */ |
c0f3af97 | 9531 | { |
bf890a93 | 9532 | { "vpextrK", { Edq, XM, Ib }, 0 }, |
c0f3af97 L |
9533 | }, |
9534 | ||
592a252b | 9535 | /* VEX_LEN_0F3A17_P_2 */ |
c0f3af97 | 9536 | { |
bf890a93 | 9537 | { "vextractps", { Edqd, XM, Ib }, 0 }, |
c0f3af97 L |
9538 | }, |
9539 | ||
592a252b | 9540 | /* VEX_LEN_0F3A18_P_2 */ |
c0f3af97 | 9541 | { |
592d1631 | 9542 | { Bad_Opcode }, |
592a252b | 9543 | { VEX_W_TABLE (VEX_W_0F3A18_P_2) }, |
c0f3af97 L |
9544 | }, |
9545 | ||
592a252b | 9546 | /* VEX_LEN_0F3A19_P_2 */ |
c0f3af97 | 9547 | { |
592d1631 | 9548 | { Bad_Opcode }, |
592a252b | 9549 | { VEX_W_TABLE (VEX_W_0F3A19_P_2) }, |
c0f3af97 L |
9550 | }, |
9551 | ||
592a252b | 9552 | /* VEX_LEN_0F3A20_P_2 */ |
c0f3af97 | 9553 | { |
b50c9f31 | 9554 | { "vpinsrb", { XM, Vex128, Edqb, Ib }, 0 }, |
c0f3af97 L |
9555 | }, |
9556 | ||
592a252b | 9557 | /* VEX_LEN_0F3A21_P_2 */ |
c0f3af97 | 9558 | { |
ec6f095a | 9559 | { "vinsertps", { XM, Vex128, EXd, Ib }, 0 }, |
c0f3af97 L |
9560 | }, |
9561 | ||
592a252b | 9562 | /* VEX_LEN_0F3A22_P_2 */ |
c0f3af97 | 9563 | { |
bf890a93 | 9564 | { "vpinsrK", { XM, Vex128, Edq, Ib }, 0 }, |
c0f3af97 L |
9565 | }, |
9566 | ||
43234a1e L |
9567 | /* VEX_LEN_0F3A30_P_2 */ |
9568 | { | |
9569 | { VEX_W_TABLE (VEX_W_0F3A30_P_2_LEN_0) }, | |
9570 | }, | |
9571 | ||
1ba585e8 IT |
9572 | /* VEX_LEN_0F3A31_P_2 */ |
9573 | { | |
9574 | { VEX_W_TABLE (VEX_W_0F3A31_P_2_LEN_0) }, | |
9575 | }, | |
9576 | ||
43234a1e L |
9577 | /* VEX_LEN_0F3A32_P_2 */ |
9578 | { | |
9579 | { VEX_W_TABLE (VEX_W_0F3A32_P_2_LEN_0) }, | |
9580 | }, | |
9581 | ||
1ba585e8 IT |
9582 | /* VEX_LEN_0F3A33_P_2 */ |
9583 | { | |
9584 | { VEX_W_TABLE (VEX_W_0F3A33_P_2_LEN_0) }, | |
9585 | }, | |
9586 | ||
6c30d220 | 9587 | /* VEX_LEN_0F3A38_P_2 */ |
c0f3af97 | 9588 | { |
6c30d220 L |
9589 | { Bad_Opcode }, |
9590 | { VEX_W_TABLE (VEX_W_0F3A38_P_2) }, | |
c0f3af97 L |
9591 | }, |
9592 | ||
6c30d220 | 9593 | /* VEX_LEN_0F3A39_P_2 */ |
c0f3af97 | 9594 | { |
6c30d220 L |
9595 | { Bad_Opcode }, |
9596 | { VEX_W_TABLE (VEX_W_0F3A39_P_2) }, | |
9597 | }, | |
9598 | ||
9599 | /* VEX_LEN_0F3A41_P_2 */ | |
9600 | { | |
ec6f095a | 9601 | { "vdppd", { XM, Vex128, EXx, Ib }, 0 }, |
c0f3af97 L |
9602 | }, |
9603 | ||
6c30d220 | 9604 | /* VEX_LEN_0F3A46_P_2 */ |
c0f3af97 | 9605 | { |
6c30d220 L |
9606 | { Bad_Opcode }, |
9607 | { VEX_W_TABLE (VEX_W_0F3A46_P_2) }, | |
c0f3af97 L |
9608 | }, |
9609 | ||
592a252b | 9610 | /* VEX_LEN_0F3A60_P_2 */ |
c0f3af97 | 9611 | { |
15c7c1d8 | 9612 | { "vpcmpestrm", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9613 | }, |
9614 | ||
592a252b | 9615 | /* VEX_LEN_0F3A61_P_2 */ |
c0f3af97 | 9616 | { |
15c7c1d8 | 9617 | { "vpcmpestri", { XM, { PCMPESTR_Fixup, x_mode }, Ib }, 0 }, |
c0f3af97 L |
9618 | }, |
9619 | ||
592a252b | 9620 | /* VEX_LEN_0F3A62_P_2 */ |
c0f3af97 | 9621 | { |
ec6f095a | 9622 | { "vpcmpistrm", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9623 | }, |
9624 | ||
592a252b | 9625 | /* VEX_LEN_0F3A63_P_2 */ |
c0f3af97 | 9626 | { |
ec6f095a | 9627 | { "vpcmpistri", { XM, EXx, Ib }, 0 }, |
c0f3af97 L |
9628 | }, |
9629 | ||
592a252b | 9630 | /* VEX_LEN_0F3A6A_P_2 */ |
922d8de8 | 9631 | { |
b13b1bc0 | 9632 | { "vfmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 }, |
922d8de8 DR |
9633 | }, |
9634 | ||
592a252b | 9635 | /* VEX_LEN_0F3A6B_P_2 */ |
922d8de8 | 9636 | { |
b13b1bc0 | 9637 | { "vfmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 }, |
922d8de8 DR |
9638 | }, |
9639 | ||
592a252b | 9640 | /* VEX_LEN_0F3A6E_P_2 */ |
922d8de8 | 9641 | { |
b13b1bc0 | 9642 | { "vfmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 }, |
922d8de8 DR |
9643 | }, |
9644 | ||
592a252b | 9645 | /* VEX_LEN_0F3A6F_P_2 */ |
922d8de8 | 9646 | { |
b13b1bc0 | 9647 | { "vfmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 }, |
922d8de8 DR |
9648 | }, |
9649 | ||
592a252b | 9650 | /* VEX_LEN_0F3A7A_P_2 */ |
922d8de8 | 9651 | { |
b13b1bc0 | 9652 | { "vfnmaddss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 }, |
922d8de8 DR |
9653 | }, |
9654 | ||
592a252b | 9655 | /* VEX_LEN_0F3A7B_P_2 */ |
922d8de8 | 9656 | { |
b13b1bc0 | 9657 | { "vfnmaddsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 }, |
922d8de8 DR |
9658 | }, |
9659 | ||
592a252b | 9660 | /* VEX_LEN_0F3A7E_P_2 */ |
922d8de8 | 9661 | { |
b13b1bc0 | 9662 | { "vfnmsubss", { XMScalar, VexScalar, EXxmm_md, XMVexI4 }, 0 }, |
922d8de8 DR |
9663 | }, |
9664 | ||
592a252b | 9665 | /* VEX_LEN_0F3A7F_P_2 */ |
922d8de8 | 9666 | { |
b13b1bc0 | 9667 | { "vfnmsubsd", { XMScalar, VexScalar, EXxmm_mq, XMVexI4 }, 0 }, |
922d8de8 DR |
9668 | }, |
9669 | ||
592a252b | 9670 | /* VEX_LEN_0F3ADF_P_2 */ |
a5ff0eb2 | 9671 | { |
ec6f095a | 9672 | { "vaeskeygenassist", { XM, EXx, Ib }, 0 }, |
a5ff0eb2 | 9673 | }, |
4c807e72 | 9674 | |
6c30d220 L |
9675 | /* VEX_LEN_0F3AF0_P_3 */ |
9676 | { | |
bf890a93 | 9677 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 L |
9678 | }, |
9679 | ||
ff688e1f L |
9680 | /* VEX_LEN_0FXOP_08_CC */ |
9681 | { | |
be92cb14 | 9682 | { "vpcomb", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9683 | }, |
9684 | ||
9685 | /* VEX_LEN_0FXOP_08_CD */ | |
9686 | { | |
be92cb14 | 9687 | { "vpcomw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9688 | }, |
9689 | ||
9690 | /* VEX_LEN_0FXOP_08_CE */ | |
9691 | { | |
be92cb14 | 9692 | { "vpcomd", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9693 | }, |
9694 | ||
9695 | /* VEX_LEN_0FXOP_08_CF */ | |
9696 | { | |
be92cb14 | 9697 | { "vpcomq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9698 | }, |
9699 | ||
9700 | /* VEX_LEN_0FXOP_08_EC */ | |
9701 | { | |
be92cb14 | 9702 | { "vpcomub", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9703 | }, |
9704 | ||
9705 | /* VEX_LEN_0FXOP_08_ED */ | |
9706 | { | |
be92cb14 | 9707 | { "vpcomuw", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9708 | }, |
9709 | ||
9710 | /* VEX_LEN_0FXOP_08_EE */ | |
9711 | { | |
be92cb14 | 9712 | { "vpcomud", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9713 | }, |
9714 | ||
9715 | /* VEX_LEN_0FXOP_08_EF */ | |
9716 | { | |
be92cb14 | 9717 | { "vpcomuq", { XM, Vex128, EXx, VPCOM }, 0 }, |
ff688e1f L |
9718 | }, |
9719 | ||
b5b098c2 | 9720 | /* VEX_LEN_0FXOP_09_82_W_0 */ |
5dd85c99 | 9721 | { |
b5b098c2 | 9722 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 9723 | }, |
4c807e72 | 9724 | |
b5b098c2 | 9725 | /* VEX_LEN_0FXOP_09_83_W_0 */ |
5dd85c99 | 9726 | { |
b5b098c2 | 9727 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 9728 | }, |
331d2d0d L |
9729 | }; |
9730 | ||
ad692897 | 9731 | #include "i386-dis-evex-len.h" |
04e2a182 | 9732 | |
9e30b8e0 | 9733 | static const struct dis386 vex_w_table[][2] = { |
43234a1e L |
9734 | { |
9735 | /* VEX_W_0F41_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9736 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_0_LEN_1) }, |
9737 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_0_LEN_1) }, | |
1ba585e8 IT |
9738 | }, |
9739 | { | |
9740 | /* VEX_W_0F41_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9741 | { MOD_TABLE (MOD_VEX_W_0_0F41_P_2_LEN_1) }, |
9742 | { MOD_TABLE (MOD_VEX_W_1_0F41_P_2_LEN_1) } | |
43234a1e L |
9743 | }, |
9744 | { | |
9745 | /* VEX_W_0F42_P_0_LEN_1 */ | |
ab4e4ed5 AF |
9746 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_0_LEN_1) }, |
9747 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_0_LEN_1) }, | |
1ba585e8 IT |
9748 | }, |
9749 | { | |
9750 | /* VEX_W_0F42_P_2_LEN_1 */ | |
ab4e4ed5 AF |
9751 | { MOD_TABLE (MOD_VEX_W_0_0F42_P_2_LEN_1) }, |
9752 | { MOD_TABLE (MOD_VEX_W_1_0F42_P_2_LEN_1) }, | |
43234a1e L |
9753 | }, |
9754 | { | |
9755 | /* VEX_W_0F44_P_0_LEN_0 */ | |
ab4e4ed5 AF |
9756 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_0_LEN_1) }, |
9757 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_0_LEN_1) }, | |
1ba585e8 IT |
9758 | }, |
9759 | { | |
9760 | /* VEX_W_0F44_P_2_LEN_0 */ | |
ab4e4ed5 AF |
9761 | { MOD_TABLE (MOD_VEX_W_0_0F44_P_2_LEN_1) }, |
9762 | { MOD_TABLE (MOD_VEX_W_1_0F44_P_2_LEN_1) }, | |
43234a1e L |
9763 | }, |
9764 | { | |
ec6f095a L |
9765 | /* VEX_W_0F45_P_0_LEN_1 */ |
9766 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_0_LEN_1) }, | |
9767 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_0_LEN_1) }, | |
9e30b8e0 L |
9768 | }, |
9769 | { | |
ec6f095a L |
9770 | /* VEX_W_0F45_P_2_LEN_1 */ |
9771 | { MOD_TABLE (MOD_VEX_W_0_0F45_P_2_LEN_1) }, | |
9772 | { MOD_TABLE (MOD_VEX_W_1_0F45_P_2_LEN_1) }, | |
9e30b8e0 L |
9773 | }, |
9774 | { | |
ec6f095a L |
9775 | /* VEX_W_0F46_P_0_LEN_1 */ |
9776 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_0_LEN_1) }, | |
9777 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_0_LEN_1) }, | |
9e30b8e0 L |
9778 | }, |
9779 | { | |
ec6f095a L |
9780 | /* VEX_W_0F46_P_2_LEN_1 */ |
9781 | { MOD_TABLE (MOD_VEX_W_0_0F46_P_2_LEN_1) }, | |
9782 | { MOD_TABLE (MOD_VEX_W_1_0F46_P_2_LEN_1) }, | |
9e30b8e0 L |
9783 | }, |
9784 | { | |
ec6f095a L |
9785 | /* VEX_W_0F47_P_0_LEN_1 */ |
9786 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_0_LEN_1) }, | |
9787 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_0_LEN_1) }, | |
9e30b8e0 L |
9788 | }, |
9789 | { | |
ec6f095a L |
9790 | /* VEX_W_0F47_P_2_LEN_1 */ |
9791 | { MOD_TABLE (MOD_VEX_W_0_0F47_P_2_LEN_1) }, | |
9792 | { MOD_TABLE (MOD_VEX_W_1_0F47_P_2_LEN_1) }, | |
9e30b8e0 L |
9793 | }, |
9794 | { | |
ec6f095a L |
9795 | /* VEX_W_0F4A_P_0_LEN_1 */ |
9796 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_0_LEN_1) }, | |
9797 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_0_LEN_1) }, | |
9e30b8e0 L |
9798 | }, |
9799 | { | |
ec6f095a L |
9800 | /* VEX_W_0F4A_P_2_LEN_1 */ |
9801 | { MOD_TABLE (MOD_VEX_W_0_0F4A_P_2_LEN_1) }, | |
9802 | { MOD_TABLE (MOD_VEX_W_1_0F4A_P_2_LEN_1) }, | |
9e30b8e0 L |
9803 | }, |
9804 | { | |
ec6f095a L |
9805 | /* VEX_W_0F4B_P_0_LEN_1 */ |
9806 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_0_LEN_1) }, | |
9807 | { MOD_TABLE (MOD_VEX_W_1_0F4B_P_0_LEN_1) }, | |
9e30b8e0 L |
9808 | }, |
9809 | { | |
ec6f095a L |
9810 | /* VEX_W_0F4B_P_2_LEN_1 */ |
9811 | { MOD_TABLE (MOD_VEX_W_0_0F4B_P_2_LEN_1) }, | |
9e30b8e0 L |
9812 | }, |
9813 | { | |
ec6f095a L |
9814 | /* VEX_W_0F90_P_0_LEN_0 */ |
9815 | { "kmovw", { MaskG, MaskE }, 0 }, | |
9816 | { "kmovq", { MaskG, MaskE }, 0 }, | |
9e30b8e0 L |
9817 | }, |
9818 | { | |
ec6f095a L |
9819 | /* VEX_W_0F90_P_2_LEN_0 */ |
9820 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
9821 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
9e30b8e0 L |
9822 | }, |
9823 | { | |
ec6f095a L |
9824 | /* VEX_W_0F91_P_0_LEN_0 */ |
9825 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_0_LEN_0) }, | |
9826 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_0_LEN_0) }, | |
9e30b8e0 L |
9827 | }, |
9828 | { | |
ec6f095a L |
9829 | /* VEX_W_0F91_P_2_LEN_0 */ |
9830 | { MOD_TABLE (MOD_VEX_W_0_0F91_P_2_LEN_0) }, | |
9831 | { MOD_TABLE (MOD_VEX_W_1_0F91_P_2_LEN_0) }, | |
9e30b8e0 L |
9832 | }, |
9833 | { | |
ec6f095a L |
9834 | /* VEX_W_0F92_P_0_LEN_0 */ |
9835 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_0_LEN_0) }, | |
9e30b8e0 L |
9836 | }, |
9837 | { | |
ec6f095a L |
9838 | /* VEX_W_0F92_P_2_LEN_0 */ |
9839 | { MOD_TABLE (MOD_VEX_W_0_0F92_P_2_LEN_0) }, | |
9e30b8e0 | 9840 | }, |
9e30b8e0 | 9841 | { |
ec6f095a L |
9842 | /* VEX_W_0F93_P_0_LEN_0 */ |
9843 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_0_LEN_0) }, | |
9e30b8e0 L |
9844 | }, |
9845 | { | |
ec6f095a L |
9846 | /* VEX_W_0F93_P_2_LEN_0 */ |
9847 | { MOD_TABLE (MOD_VEX_W_0_0F93_P_2_LEN_0) }, | |
9e30b8e0 | 9848 | }, |
9e30b8e0 | 9849 | { |
ec6f095a L |
9850 | /* VEX_W_0F98_P_0_LEN_0 */ |
9851 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_0_LEN_0) }, | |
9852 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_0_LEN_0) }, | |
9e30b8e0 L |
9853 | }, |
9854 | { | |
ec6f095a L |
9855 | /* VEX_W_0F98_P_2_LEN_0 */ |
9856 | { MOD_TABLE (MOD_VEX_W_0_0F98_P_2_LEN_0) }, | |
9857 | { MOD_TABLE (MOD_VEX_W_1_0F98_P_2_LEN_0) }, | |
9e30b8e0 L |
9858 | }, |
9859 | { | |
ec6f095a L |
9860 | /* VEX_W_0F99_P_0_LEN_0 */ |
9861 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_0_LEN_0) }, | |
9862 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_0_LEN_0) }, | |
9e30b8e0 L |
9863 | }, |
9864 | { | |
ec6f095a L |
9865 | /* VEX_W_0F99_P_2_LEN_0 */ |
9866 | { MOD_TABLE (MOD_VEX_W_0_0F99_P_2_LEN_0) }, | |
9867 | { MOD_TABLE (MOD_VEX_W_1_0F99_P_2_LEN_0) }, | |
9e30b8e0 | 9868 | }, |
9e30b8e0 | 9869 | { |
592a252b | 9870 | /* VEX_W_0F380C_P_2 */ |
bf890a93 | 9871 | { "vpermilps", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9872 | }, |
9873 | { | |
592a252b | 9874 | /* VEX_W_0F380D_P_2 */ |
bf890a93 | 9875 | { "vpermilpd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 L |
9876 | }, |
9877 | { | |
592a252b | 9878 | /* VEX_W_0F380E_P_2 */ |
bf890a93 | 9879 | { "vtestps", { XM, EXx }, 0 }, |
9e30b8e0 L |
9880 | }, |
9881 | { | |
592a252b | 9882 | /* VEX_W_0F380F_P_2 */ |
bf890a93 | 9883 | { "vtestpd", { XM, EXx }, 0 }, |
9e30b8e0 | 9884 | }, |
6431c801 JB |
9885 | { |
9886 | /* VEX_W_0F3813_P_2 */ | |
9887 | { "vcvtph2ps", { XM, EXxmmq }, 0 }, | |
9888 | }, | |
6c30d220 L |
9889 | { |
9890 | /* VEX_W_0F3816_P_2 */ | |
bf890a93 | 9891 | { "vpermps", { XM, Vex, EXx }, 0 }, |
6c30d220 | 9892 | }, |
bcf2684f | 9893 | { |
6c30d220 | 9894 | /* VEX_W_0F3818_P_2 */ |
bf890a93 | 9895 | { "vbroadcastss", { XM, EXxmm_md }, 0 }, |
bcf2684f | 9896 | }, |
9e30b8e0 | 9897 | { |
6c30d220 | 9898 | /* VEX_W_0F3819_P_2 */ |
bf890a93 | 9899 | { "vbroadcastsd", { XM, EXxmm_mq }, 0 }, |
9e30b8e0 L |
9900 | }, |
9901 | { | |
592a252b | 9902 | /* VEX_W_0F381A_P_2_M_0 */ |
bf890a93 | 9903 | { "vbroadcastf128", { XM, Mxmm }, 0 }, |
9e30b8e0 | 9904 | }, |
53aa04a0 | 9905 | { |
592a252b | 9906 | /* VEX_W_0F382C_P_2_M_0 */ |
bf890a93 | 9907 | { "vmaskmovps", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9908 | }, |
9909 | { | |
592a252b | 9910 | /* VEX_W_0F382D_P_2_M_0 */ |
bf890a93 | 9911 | { "vmaskmovpd", { XM, Vex, Mx }, 0 }, |
53aa04a0 L |
9912 | }, |
9913 | { | |
592a252b | 9914 | /* VEX_W_0F382E_P_2_M_0 */ |
bf890a93 | 9915 | { "vmaskmovps", { Mx, Vex, XM }, 0 }, |
53aa04a0 L |
9916 | }, |
9917 | { | |
592a252b | 9918 | /* VEX_W_0F382F_P_2_M_0 */ |
bf890a93 | 9919 | { "vmaskmovpd", { Mx, Vex, XM }, 0 }, |
53aa04a0 | 9920 | }, |
6c30d220 L |
9921 | { |
9922 | /* VEX_W_0F3836_P_2 */ | |
bf890a93 | 9923 | { "vpermd", { XM, Vex, EXx }, 0 }, |
9e30b8e0 | 9924 | }, |
6c30d220 L |
9925 | { |
9926 | /* VEX_W_0F3846_P_2 */ | |
bf890a93 | 9927 | { "vpsravd", { XM, Vex, EXx }, 0 }, |
6c30d220 L |
9928 | }, |
9929 | { | |
9930 | /* VEX_W_0F3858_P_2 */ | |
bf890a93 | 9931 | { "vpbroadcastd", { XM, EXxmm_md }, 0 }, |
6c30d220 L |
9932 | }, |
9933 | { | |
9934 | /* VEX_W_0F3859_P_2 */ | |
bf890a93 | 9935 | { "vpbroadcastq", { XM, EXxmm_mq }, 0 }, |
6c30d220 L |
9936 | }, |
9937 | { | |
9938 | /* VEX_W_0F385A_P_2_M_0 */ | |
bf890a93 | 9939 | { "vbroadcasti128", { XM, Mxmm }, 0 }, |
6c30d220 L |
9940 | }, |
9941 | { | |
9942 | /* VEX_W_0F3878_P_2 */ | |
bf890a93 | 9943 | { "vpbroadcastb", { XM, EXxmm_mb }, 0 }, |
6c30d220 L |
9944 | }, |
9945 | { | |
9946 | /* VEX_W_0F3879_P_2 */ | |
bf890a93 | 9947 | { "vpbroadcastw", { XM, EXxmm_mw }, 0 }, |
6c30d220 | 9948 | }, |
48521003 IT |
9949 | { |
9950 | /* VEX_W_0F38CF_P_2 */ | |
9951 | { "vgf2p8mulb", { XM, Vex, EXx }, 0 }, | |
9952 | }, | |
6c30d220 L |
9953 | { |
9954 | /* VEX_W_0F3A00_P_2 */ | |
9955 | { Bad_Opcode }, | |
bf890a93 | 9956 | { "vpermq", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9957 | }, |
9958 | { | |
9959 | /* VEX_W_0F3A01_P_2 */ | |
9960 | { Bad_Opcode }, | |
bf890a93 | 9961 | { "vpermpd", { XM, EXx, Ib }, 0 }, |
6c30d220 L |
9962 | }, |
9963 | { | |
9964 | /* VEX_W_0F3A02_P_2 */ | |
bf890a93 | 9965 | { "vpblendd", { XM, Vex, EXx, Ib }, 0 }, |
6c30d220 | 9966 | }, |
9e30b8e0 | 9967 | { |
592a252b | 9968 | /* VEX_W_0F3A04_P_2 */ |
bf890a93 | 9969 | { "vpermilps", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
9970 | }, |
9971 | { | |
592a252b | 9972 | /* VEX_W_0F3A05_P_2 */ |
bf890a93 | 9973 | { "vpermilpd", { XM, EXx, Ib }, 0 }, |
9e30b8e0 L |
9974 | }, |
9975 | { | |
592a252b | 9976 | /* VEX_W_0F3A06_P_2 */ |
bf890a93 | 9977 | { "vperm2f128", { XM, Vex256, EXx, Ib }, 0 }, |
9e30b8e0 | 9978 | }, |
9e30b8e0 | 9979 | { |
592a252b | 9980 | /* VEX_W_0F3A18_P_2 */ |
bf890a93 | 9981 | { "vinsertf128", { XM, Vex256, EXxmm, Ib }, 0 }, |
9e30b8e0 L |
9982 | }, |
9983 | { | |
592a252b | 9984 | /* VEX_W_0F3A19_P_2 */ |
bf890a93 | 9985 | { "vextractf128", { EXxmm, XM, Ib }, 0 }, |
9e30b8e0 | 9986 | }, |
6431c801 JB |
9987 | { |
9988 | /* VEX_W_0F3A1D_P_2 */ | |
9989 | { "vcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, 0 }, | |
9990 | }, | |
43234a1e | 9991 | { |
1ba585e8 | 9992 | /* VEX_W_0F3A30_P_2_LEN_0 */ |
ab4e4ed5 AF |
9993 | { MOD_TABLE (MOD_VEX_W_0_0F3A30_P_2_LEN_0) }, |
9994 | { MOD_TABLE (MOD_VEX_W_1_0F3A30_P_2_LEN_0) }, | |
43234a1e L |
9995 | }, |
9996 | { | |
1ba585e8 | 9997 | /* VEX_W_0F3A31_P_2_LEN_0 */ |
ab4e4ed5 AF |
9998 | { MOD_TABLE (MOD_VEX_W_0_0F3A31_P_2_LEN_0) }, |
9999 | { MOD_TABLE (MOD_VEX_W_1_0F3A31_P_2_LEN_0) }, | |
1ba585e8 IT |
10000 | }, |
10001 | { | |
10002 | /* VEX_W_0F3A32_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10003 | { MOD_TABLE (MOD_VEX_W_0_0F3A32_P_2_LEN_0) }, |
10004 | { MOD_TABLE (MOD_VEX_W_1_0F3A32_P_2_LEN_0) }, | |
43234a1e | 10005 | }, |
1ba585e8 IT |
10006 | { |
10007 | /* VEX_W_0F3A33_P_2_LEN_0 */ | |
ab4e4ed5 AF |
10008 | { MOD_TABLE (MOD_VEX_W_0_0F3A33_P_2_LEN_0) }, |
10009 | { MOD_TABLE (MOD_VEX_W_1_0F3A33_P_2_LEN_0) }, | |
1ba585e8 | 10010 | }, |
6c30d220 L |
10011 | { |
10012 | /* VEX_W_0F3A38_P_2 */ | |
bf890a93 | 10013 | { "vinserti128", { XM, Vex256, EXxmm, Ib }, 0 }, |
6c30d220 L |
10014 | }, |
10015 | { | |
10016 | /* VEX_W_0F3A39_P_2 */ | |
bf890a93 | 10017 | { "vextracti128", { EXxmm, XM, Ib }, 0 }, |
6c30d220 | 10018 | }, |
6c30d220 L |
10019 | { |
10020 | /* VEX_W_0F3A46_P_2 */ | |
bf890a93 | 10021 | { "vperm2i128", { XM, Vex256, EXx, Ib }, 0 }, |
6c30d220 | 10022 | }, |
a683cc34 | 10023 | { |
592a252b | 10024 | /* VEX_W_0F3A48_P_2 */ |
bf890a93 IT |
10025 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10026 | { "vpermil2ps", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 SP |
10027 | }, |
10028 | { | |
592a252b | 10029 | /* VEX_W_0F3A49_P_2 */ |
bf890a93 IT |
10030 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, |
10031 | { "vpermil2pd", { XMVexW, Vex, EXVexImmW, EXVexImmW, EXVexImmW }, 0 }, | |
a683cc34 | 10032 | }, |
9e30b8e0 | 10033 | { |
592a252b | 10034 | /* VEX_W_0F3A4A_P_2 */ |
bf890a93 | 10035 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10036 | }, |
10037 | { | |
592a252b | 10038 | /* VEX_W_0F3A4B_P_2 */ |
bf890a93 | 10039 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 L |
10040 | }, |
10041 | { | |
592a252b | 10042 | /* VEX_W_0F3A4C_P_2 */ |
bf890a93 | 10043 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, 0 }, |
9e30b8e0 | 10044 | }, |
48521003 IT |
10045 | { |
10046 | /* VEX_W_0F3ACE_P_2 */ | |
10047 | { Bad_Opcode }, | |
10048 | { "vgf2p8affineqb", { XM, Vex, EXx, Ib }, 0 }, | |
10049 | }, | |
10050 | { | |
10051 | /* VEX_W_0F3ACF_P_2 */ | |
10052 | { Bad_Opcode }, | |
10053 | { "vgf2p8affineinvqb", { XM, Vex, EXx, Ib }, 0 }, | |
10054 | }, | |
b5b098c2 JB |
10055 | /* VEX_W_0FXOP_09_80 */ |
10056 | { | |
10057 | { "vfrczps", { XM, EXx }, 0 }, | |
10058 | }, | |
10059 | /* VEX_W_0FXOP_09_81 */ | |
10060 | { | |
10061 | { "vfrczpd", { XM, EXx }, 0 }, | |
10062 | }, | |
10063 | /* VEX_W_0FXOP_09_82 */ | |
10064 | { | |
10065 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_82_W_0) }, | |
10066 | }, | |
10067 | /* VEX_W_0FXOP_09_83 */ | |
10068 | { | |
10069 | { VEX_LEN_TABLE (VEX_LEN_0FXOP_09_83_W_0) }, | |
10070 | }, | |
ad692897 L |
10071 | |
10072 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
10073 | }; |
10074 | ||
10075 | static const struct dis386 mod_table[][2] = { | |
10076 | { | |
10077 | /* MOD_8D */ | |
bf890a93 | 10078 | { "leaS", { Gv, M }, 0 }, |
9e30b8e0 | 10079 | }, |
42164a71 L |
10080 | { |
10081 | /* MOD_C6_REG_7 */ | |
10082 | { Bad_Opcode }, | |
10083 | { RM_TABLE (RM_C6_REG_7) }, | |
10084 | }, | |
10085 | { | |
10086 | /* MOD_C7_REG_7 */ | |
10087 | { Bad_Opcode }, | |
10088 | { RM_TABLE (RM_C7_REG_7) }, | |
10089 | }, | |
4a357820 MZ |
10090 | { |
10091 | /* MOD_FF_REG_3 */ | |
8f570d62 | 10092 | { "{l|}call^", { indirEp }, 0 }, |
4a357820 MZ |
10093 | }, |
10094 | { | |
10095 | /* MOD_FF_REG_5 */ | |
8f570d62 | 10096 | { "{l|}jmp^", { indirEp }, 0 }, |
4a357820 | 10097 | }, |
9e30b8e0 L |
10098 | { |
10099 | /* MOD_0F01_REG_0 */ | |
10100 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
10101 | { RM_TABLE (RM_0F01_REG_0) }, | |
10102 | }, | |
10103 | { | |
10104 | /* MOD_0F01_REG_1 */ | |
10105 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
10106 | { RM_TABLE (RM_0F01_REG_1) }, | |
10107 | }, | |
10108 | { | |
10109 | /* MOD_0F01_REG_2 */ | |
10110 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
10111 | { RM_TABLE (RM_0F01_REG_2) }, | |
10112 | }, | |
10113 | { | |
10114 | /* MOD_0F01_REG_3 */ | |
10115 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
10116 | { RM_TABLE (RM_0F01_REG_3) }, | |
10117 | }, | |
8eab4136 L |
10118 | { |
10119 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
10120 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
10121 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 10122 | }, |
9e30b8e0 L |
10123 | { |
10124 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 10125 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 10126 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
10127 | }, |
10128 | { | |
10129 | /* MOD_0F12_PREFIX_0 */ | |
18897deb JB |
10130 | { "movlpX", { XM, EXq }, 0 }, |
10131 | { "movhlps", { XM, EXq }, 0 }, | |
10132 | }, | |
10133 | { | |
10134 | /* MOD_0F12_PREFIX_2 */ | |
10135 | { "movlpX", { XM, EXq }, 0 }, | |
9e30b8e0 L |
10136 | }, |
10137 | { | |
10138 | /* MOD_0F13 */ | |
507bd325 | 10139 | { "movlpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10140 | }, |
10141 | { | |
10142 | /* MOD_0F16_PREFIX_0 */ | |
18897deb | 10143 | { "movhpX", { XM, EXq }, 0 }, |
bf890a93 | 10144 | { "movlhps", { XM, EXq }, 0 }, |
9e30b8e0 | 10145 | }, |
18897deb JB |
10146 | { |
10147 | /* MOD_0F16_PREFIX_2 */ | |
10148 | { "movhpX", { XM, EXq }, 0 }, | |
10149 | }, | |
9e30b8e0 L |
10150 | { |
10151 | /* MOD_0F17 */ | |
507bd325 | 10152 | { "movhpX", { EXq, XM }, PREFIX_OPCODE }, |
9e30b8e0 L |
10153 | }, |
10154 | { | |
10155 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 10156 | { "prefetchnta", { Mb }, 0 }, |
9e30b8e0 L |
10157 | }, |
10158 | { | |
10159 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 10160 | { "prefetcht0", { Mb }, 0 }, |
9e30b8e0 L |
10161 | }, |
10162 | { | |
10163 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 10164 | { "prefetcht1", { Mb }, 0 }, |
9e30b8e0 L |
10165 | }, |
10166 | { | |
10167 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 10168 | { "prefetcht2", { Mb }, 0 }, |
9e30b8e0 | 10169 | }, |
d7189fa5 RM |
10170 | { |
10171 | /* MOD_0F18_REG_4 */ | |
bf890a93 | 10172 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10173 | }, |
10174 | { | |
10175 | /* MOD_0F18_REG_5 */ | |
bf890a93 | 10176 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10177 | }, |
10178 | { | |
10179 | /* MOD_0F18_REG_6 */ | |
bf890a93 | 10180 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 RM |
10181 | }, |
10182 | { | |
10183 | /* MOD_0F18_REG_7 */ | |
bf890a93 | 10184 | { "nop/reserved", { Mb }, 0 }, |
d7189fa5 | 10185 | }, |
7e8b059b L |
10186 | { |
10187 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 10188 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10189 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10190 | }, |
10191 | { | |
10192 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 10193 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 10194 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
10195 | }, |
10196 | { | |
10197 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 10198 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 10199 | { "nopQ", { Ev }, 0 }, |
7e8b059b | 10200 | }, |
c48935d7 IT |
10201 | { |
10202 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 10203 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
10204 | { "nopQ", { Ev }, 0 }, |
10205 | }, | |
603555e5 L |
10206 | { |
10207 | /* MOD_0F1E_PREFIX_1 */ | |
10208 | { "nopQ", { Ev }, 0 }, | |
f8687e93 | 10209 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 10210 | }, |
b844680a | 10211 | { |
92fddf8e | 10212 | /* MOD_0F24 */ |
7bb15c6f | 10213 | { Bad_Opcode }, |
bf890a93 | 10214 | { "movL", { Rd, Td }, 0 }, |
b844680a L |
10215 | }, |
10216 | { | |
92fddf8e | 10217 | /* MOD_0F26 */ |
592d1631 | 10218 | { Bad_Opcode }, |
bf890a93 | 10219 | { "movL", { Td, Rd }, 0 }, |
b844680a | 10220 | }, |
75c135a8 L |
10221 | { |
10222 | /* MOD_0F2B_PREFIX_0 */ | |
507bd325 | 10223 | {"movntps", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10224 | }, |
10225 | { | |
10226 | /* MOD_0F2B_PREFIX_1 */ | |
507bd325 | 10227 | {"movntss", { Md, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10228 | }, |
10229 | { | |
10230 | /* MOD_0F2B_PREFIX_2 */ | |
507bd325 | 10231 | {"movntpd", { Mx, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10232 | }, |
10233 | { | |
10234 | /* MOD_0F2B_PREFIX_3 */ | |
507bd325 | 10235 | {"movntsd", { Mq, XM }, PREFIX_OPCODE }, |
75c135a8 L |
10236 | }, |
10237 | { | |
a5aaedb9 | 10238 | /* MOD_0F50 */ |
592d1631 | 10239 | { Bad_Opcode }, |
507bd325 | 10240 | { "movmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
75c135a8 | 10241 | }, |
b844680a | 10242 | { |
1ceb70f8 | 10243 | /* MOD_0F71_REG_2 */ |
592d1631 | 10244 | { Bad_Opcode }, |
bf890a93 | 10245 | { "psrlw", { MS, Ib }, 0 }, |
b844680a L |
10246 | }, |
10247 | { | |
1ceb70f8 | 10248 | /* MOD_0F71_REG_4 */ |
592d1631 | 10249 | { Bad_Opcode }, |
bf890a93 | 10250 | { "psraw", { MS, Ib }, 0 }, |
b844680a L |
10251 | }, |
10252 | { | |
1ceb70f8 | 10253 | /* MOD_0F71_REG_6 */ |
592d1631 | 10254 | { Bad_Opcode }, |
bf890a93 | 10255 | { "psllw", { MS, Ib }, 0 }, |
b844680a L |
10256 | }, |
10257 | { | |
1ceb70f8 | 10258 | /* MOD_0F72_REG_2 */ |
592d1631 | 10259 | { Bad_Opcode }, |
bf890a93 | 10260 | { "psrld", { MS, Ib }, 0 }, |
b844680a L |
10261 | }, |
10262 | { | |
1ceb70f8 | 10263 | /* MOD_0F72_REG_4 */ |
592d1631 | 10264 | { Bad_Opcode }, |
bf890a93 | 10265 | { "psrad", { MS, Ib }, 0 }, |
b844680a L |
10266 | }, |
10267 | { | |
1ceb70f8 | 10268 | /* MOD_0F72_REG_6 */ |
592d1631 | 10269 | { Bad_Opcode }, |
bf890a93 | 10270 | { "pslld", { MS, Ib }, 0 }, |
b844680a L |
10271 | }, |
10272 | { | |
1ceb70f8 | 10273 | /* MOD_0F73_REG_2 */ |
592d1631 | 10274 | { Bad_Opcode }, |
bf890a93 | 10275 | { "psrlq", { MS, Ib }, 0 }, |
b844680a L |
10276 | }, |
10277 | { | |
1ceb70f8 | 10278 | /* MOD_0F73_REG_3 */ |
592d1631 | 10279 | { Bad_Opcode }, |
c0f3af97 L |
10280 | { PREFIX_TABLE (PREFIX_0F73_REG_3) }, |
10281 | }, | |
10282 | { | |
10283 | /* MOD_0F73_REG_6 */ | |
592d1631 | 10284 | { Bad_Opcode }, |
bf890a93 | 10285 | { "psllq", { MS, Ib }, 0 }, |
c0f3af97 L |
10286 | }, |
10287 | { | |
10288 | /* MOD_0F73_REG_7 */ | |
592d1631 | 10289 | { Bad_Opcode }, |
c0f3af97 L |
10290 | { PREFIX_TABLE (PREFIX_0F73_REG_7) }, |
10291 | }, | |
10292 | { | |
10293 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 10294 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 10295 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
10296 | }, |
10297 | { | |
10298 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 10299 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 10300 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
10301 | }, |
10302 | { | |
10303 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 10304 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 10305 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
10306 | }, |
10307 | { | |
10308 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 10309 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 10310 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
10311 | }, |
10312 | { | |
10313 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
10314 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
10315 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
10316 | }, |
10317 | { | |
10318 | /* MOD_0FAE_REG_5 */ | |
f8687e93 JB |
10319 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_0) }, |
10320 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, | |
c0f3af97 L |
10321 | }, |
10322 | { | |
10323 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
10324 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
10325 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
10326 | }, |
10327 | { | |
10328 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
10329 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
10330 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 L |
10331 | }, |
10332 | { | |
10333 | /* MOD_0FB2 */ | |
bf890a93 | 10334 | { "lssS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10335 | }, |
10336 | { | |
10337 | /* MOD_0FB4 */ | |
bf890a93 | 10338 | { "lfsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10339 | }, |
10340 | { | |
10341 | /* MOD_0FB5 */ | |
bf890a93 | 10342 | { "lgsS", { Gv, Mp }, 0 }, |
c0f3af97 | 10343 | }, |
a8484f96 L |
10344 | { |
10345 | /* MOD_0FC3 */ | |
f8687e93 | 10346 | { PREFIX_TABLE (PREFIX_0FC3_MOD_0) }, |
a8484f96 | 10347 | }, |
963f3586 IT |
10348 | { |
10349 | /* MOD_0FC7_REG_3 */ | |
a8484f96 | 10350 | { "xrstors", { FXSAVE }, 0 }, |
963f3586 IT |
10351 | }, |
10352 | { | |
10353 | /* MOD_0FC7_REG_4 */ | |
bf890a93 | 10354 | { "xsavec", { FXSAVE }, 0 }, |
963f3586 IT |
10355 | }, |
10356 | { | |
10357 | /* MOD_0FC7_REG_5 */ | |
bf890a93 | 10358 | { "xsaves", { FXSAVE }, 0 }, |
963f3586 | 10359 | }, |
c0f3af97 L |
10360 | { |
10361 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
10362 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
10363 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
10364 | }, |
10365 | { | |
10366 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 10367 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 10368 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 L |
10369 | }, |
10370 | { | |
10371 | /* MOD_0FD7 */ | |
592d1631 | 10372 | { Bad_Opcode }, |
bf890a93 | 10373 | { "pmovmskb", { Gdq, MS }, 0 }, |
c0f3af97 L |
10374 | }, |
10375 | { | |
10376 | /* MOD_0FE7_PREFIX_2 */ | |
bf890a93 | 10377 | { "movntdq", { Mx, XM }, 0 }, |
c0f3af97 L |
10378 | }, |
10379 | { | |
10380 | /* MOD_0FF0_PREFIX_3 */ | |
bf890a93 | 10381 | { "lddqu", { XM, M }, 0 }, |
c0f3af97 L |
10382 | }, |
10383 | { | |
10384 | /* MOD_0F382A_PREFIX_2 */ | |
bf890a93 | 10385 | { "movntdqa", { XM, Mx }, 0 }, |
c0f3af97 | 10386 | }, |
603555e5 L |
10387 | { |
10388 | /* MOD_0F38F5_PREFIX_2 */ | |
10389 | { "wrussK", { M, Gdq }, PREFIX_OPCODE }, | |
10390 | }, | |
10391 | { | |
10392 | /* MOD_0F38F6_PREFIX_0 */ | |
10393 | { "wrssK", { M, Gdq }, PREFIX_OPCODE }, | |
10394 | }, | |
5d79adc4 L |
10395 | { |
10396 | /* MOD_0F38F8_PREFIX_1 */ | |
10397 | { "enqcmds", { Gva, M }, PREFIX_OPCODE }, | |
10398 | }, | |
c0a30a9f L |
10399 | { |
10400 | /* MOD_0F38F8_PREFIX_2 */ | |
10401 | { "movdir64b", { Gva, M }, PREFIX_OPCODE }, | |
10402 | }, | |
5d79adc4 L |
10403 | { |
10404 | /* MOD_0F38F8_PREFIX_3 */ | |
10405 | { "enqcmd", { Gva, M }, PREFIX_OPCODE }, | |
10406 | }, | |
c0a30a9f L |
10407 | { |
10408 | /* MOD_0F38F9_PREFIX_0 */ | |
77ad8092 | 10409 | { "movdiri", { Ev, Gv }, PREFIX_OPCODE }, |
c0a30a9f | 10410 | }, |
c0f3af97 L |
10411 | { |
10412 | /* MOD_62_32BIT */ | |
bf890a93 | 10413 | { "bound{S|}", { Gv, Ma }, 0 }, |
43234a1e | 10414 | { EVEX_TABLE (EVEX_0F) }, |
c0f3af97 L |
10415 | }, |
10416 | { | |
10417 | /* MOD_C4_32BIT */ | |
bf890a93 | 10418 | { "lesS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10419 | { VEX_C4_TABLE (VEX_0F) }, |
10420 | }, | |
10421 | { | |
10422 | /* MOD_C5_32BIT */ | |
bf890a93 | 10423 | { "ldsS", { Gv, Mp }, 0 }, |
c0f3af97 L |
10424 | { VEX_C5_TABLE (VEX_0F) }, |
10425 | }, | |
10426 | { | |
592a252b L |
10427 | /* MOD_VEX_0F12_PREFIX_0 */ |
10428 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_0) }, | |
10429 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0_M_1) }, | |
c0f3af97 | 10430 | }, |
18897deb JB |
10431 | { |
10432 | /* MOD_VEX_0F12_PREFIX_2 */ | |
10433 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2_M_0) }, | |
10434 | }, | |
c0f3af97 | 10435 | { |
592a252b L |
10436 | /* MOD_VEX_0F13 */ |
10437 | { VEX_LEN_TABLE (VEX_LEN_0F13_M_0) }, | |
c0f3af97 L |
10438 | }, |
10439 | { | |
592a252b L |
10440 | /* MOD_VEX_0F16_PREFIX_0 */ |
10441 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_0) }, | |
10442 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0_M_1) }, | |
c0f3af97 | 10443 | }, |
18897deb JB |
10444 | { |
10445 | /* MOD_VEX_0F16_PREFIX_2 */ | |
10446 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2_M_0) }, | |
10447 | }, | |
c0f3af97 | 10448 | { |
592a252b L |
10449 | /* MOD_VEX_0F17 */ |
10450 | { VEX_LEN_TABLE (VEX_LEN_0F17_M_0) }, | |
c0f3af97 L |
10451 | }, |
10452 | { | |
592a252b | 10453 | /* MOD_VEX_0F2B */ |
bf926894 | 10454 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
c0f3af97 | 10455 | }, |
ab4e4ed5 AF |
10456 | { |
10457 | /* MOD_VEX_W_0_0F41_P_0_LEN_1 */ | |
10458 | { Bad_Opcode }, | |
10459 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, | |
10460 | }, | |
10461 | { | |
10462 | /* MOD_VEX_W_1_0F41_P_0_LEN_1 */ | |
10463 | { Bad_Opcode }, | |
10464 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, | |
10465 | }, | |
10466 | { | |
10467 | /* MOD_VEX_W_0_0F41_P_2_LEN_1 */ | |
10468 | { Bad_Opcode }, | |
10469 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, | |
10470 | }, | |
10471 | { | |
10472 | /* MOD_VEX_W_1_0F41_P_2_LEN_1 */ | |
10473 | { Bad_Opcode }, | |
10474 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, | |
10475 | }, | |
10476 | { | |
10477 | /* MOD_VEX_W_0_0F42_P_0_LEN_1 */ | |
10478 | { Bad_Opcode }, | |
10479 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, | |
10480 | }, | |
10481 | { | |
10482 | /* MOD_VEX_W_1_0F42_P_0_LEN_1 */ | |
10483 | { Bad_Opcode }, | |
10484 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, | |
10485 | }, | |
10486 | { | |
10487 | /* MOD_VEX_W_0_0F42_P_2_LEN_1 */ | |
10488 | { Bad_Opcode }, | |
10489 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, | |
10490 | }, | |
10491 | { | |
10492 | /* MOD_VEX_W_1_0F42_P_2_LEN_1 */ | |
10493 | { Bad_Opcode }, | |
10494 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, | |
10495 | }, | |
10496 | { | |
10497 | /* MOD_VEX_W_0_0F44_P_0_LEN_0 */ | |
10498 | { Bad_Opcode }, | |
10499 | { "knotw", { MaskG, MaskR }, 0 }, | |
10500 | }, | |
10501 | { | |
10502 | /* MOD_VEX_W_1_0F44_P_0_LEN_0 */ | |
10503 | { Bad_Opcode }, | |
10504 | { "knotq", { MaskG, MaskR }, 0 }, | |
10505 | }, | |
10506 | { | |
10507 | /* MOD_VEX_W_0_0F44_P_2_LEN_0 */ | |
10508 | { Bad_Opcode }, | |
10509 | { "knotb", { MaskG, MaskR }, 0 }, | |
10510 | }, | |
10511 | { | |
10512 | /* MOD_VEX_W_1_0F44_P_2_LEN_0 */ | |
10513 | { Bad_Opcode }, | |
10514 | { "knotd", { MaskG, MaskR }, 0 }, | |
10515 | }, | |
10516 | { | |
10517 | /* MOD_VEX_W_0_0F45_P_0_LEN_1 */ | |
10518 | { Bad_Opcode }, | |
10519 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, | |
10520 | }, | |
10521 | { | |
10522 | /* MOD_VEX_W_1_0F45_P_0_LEN_1 */ | |
10523 | { Bad_Opcode }, | |
10524 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, | |
10525 | }, | |
10526 | { | |
10527 | /* MOD_VEX_W_0_0F45_P_2_LEN_1 */ | |
10528 | { Bad_Opcode }, | |
10529 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, | |
10530 | }, | |
10531 | { | |
10532 | /* MOD_VEX_W_1_0F45_P_2_LEN_1 */ | |
10533 | { Bad_Opcode }, | |
10534 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, | |
10535 | }, | |
10536 | { | |
10537 | /* MOD_VEX_W_0_0F46_P_0_LEN_1 */ | |
10538 | { Bad_Opcode }, | |
10539 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10540 | }, | |
10541 | { | |
10542 | /* MOD_VEX_W_1_0F46_P_0_LEN_1 */ | |
10543 | { Bad_Opcode }, | |
10544 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10545 | }, | |
10546 | { | |
10547 | /* MOD_VEX_W_0_0F46_P_2_LEN_1 */ | |
10548 | { Bad_Opcode }, | |
10549 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10550 | }, | |
10551 | { | |
10552 | /* MOD_VEX_W_1_0F46_P_2_LEN_1 */ | |
10553 | { Bad_Opcode }, | |
10554 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, | |
10555 | }, | |
10556 | { | |
10557 | /* MOD_VEX_W_0_0F47_P_0_LEN_1 */ | |
10558 | { Bad_Opcode }, | |
10559 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, | |
10560 | }, | |
10561 | { | |
10562 | /* MOD_VEX_W_1_0F47_P_0_LEN_1 */ | |
10563 | { Bad_Opcode }, | |
10564 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, | |
10565 | }, | |
10566 | { | |
10567 | /* MOD_VEX_W_0_0F47_P_2_LEN_1 */ | |
10568 | { Bad_Opcode }, | |
10569 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, | |
10570 | }, | |
10571 | { | |
10572 | /* MOD_VEX_W_1_0F47_P_2_LEN_1 */ | |
10573 | { Bad_Opcode }, | |
10574 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, | |
10575 | }, | |
10576 | { | |
10577 | /* MOD_VEX_W_0_0F4A_P_0_LEN_1 */ | |
10578 | { Bad_Opcode }, | |
10579 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, | |
10580 | }, | |
10581 | { | |
10582 | /* MOD_VEX_W_1_0F4A_P_0_LEN_1 */ | |
10583 | { Bad_Opcode }, | |
10584 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, | |
10585 | }, | |
10586 | { | |
10587 | /* MOD_VEX_W_0_0F4A_P_2_LEN_1 */ | |
10588 | { Bad_Opcode }, | |
10589 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, | |
10590 | }, | |
10591 | { | |
10592 | /* MOD_VEX_W_1_0F4A_P_2_LEN_1 */ | |
10593 | { Bad_Opcode }, | |
10594 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, | |
10595 | }, | |
10596 | { | |
10597 | /* MOD_VEX_W_0_0F4B_P_0_LEN_1 */ | |
10598 | { Bad_Opcode }, | |
10599 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, | |
10600 | }, | |
10601 | { | |
10602 | /* MOD_VEX_W_1_0F4B_P_0_LEN_1 */ | |
10603 | { Bad_Opcode }, | |
10604 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, | |
10605 | }, | |
10606 | { | |
10607 | /* MOD_VEX_W_0_0F4B_P_2_LEN_1 */ | |
10608 | { Bad_Opcode }, | |
10609 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, | |
10610 | }, | |
c0f3af97 | 10611 | { |
592a252b | 10612 | /* MOD_VEX_0F50 */ |
592d1631 | 10613 | { Bad_Opcode }, |
bf926894 | 10614 | { "vmovmskpX", { Gdq, XS }, PREFIX_OPCODE }, |
c0f3af97 L |
10615 | }, |
10616 | { | |
592a252b | 10617 | /* MOD_VEX_0F71_REG_2 */ |
592d1631 | 10618 | { Bad_Opcode }, |
592a252b | 10619 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_2) }, |
b844680a L |
10620 | }, |
10621 | { | |
592a252b | 10622 | /* MOD_VEX_0F71_REG_4 */ |
592d1631 | 10623 | { Bad_Opcode }, |
592a252b | 10624 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_4) }, |
b844680a L |
10625 | }, |
10626 | { | |
592a252b | 10627 | /* MOD_VEX_0F71_REG_6 */ |
592d1631 | 10628 | { Bad_Opcode }, |
592a252b | 10629 | { PREFIX_TABLE (PREFIX_VEX_0F71_REG_6) }, |
b844680a L |
10630 | }, |
10631 | { | |
592a252b | 10632 | /* MOD_VEX_0F72_REG_2 */ |
592d1631 | 10633 | { Bad_Opcode }, |
592a252b | 10634 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_2) }, |
b844680a | 10635 | }, |
d8faab4e | 10636 | { |
592a252b | 10637 | /* MOD_VEX_0F72_REG_4 */ |
592d1631 | 10638 | { Bad_Opcode }, |
592a252b | 10639 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_4) }, |
d8faab4e L |
10640 | }, |
10641 | { | |
592a252b | 10642 | /* MOD_VEX_0F72_REG_6 */ |
592d1631 | 10643 | { Bad_Opcode }, |
592a252b | 10644 | { PREFIX_TABLE (PREFIX_VEX_0F72_REG_6) }, |
d8faab4e | 10645 | }, |
876d4bfa | 10646 | { |
592a252b | 10647 | /* MOD_VEX_0F73_REG_2 */ |
592d1631 | 10648 | { Bad_Opcode }, |
592a252b | 10649 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_2) }, |
876d4bfa L |
10650 | }, |
10651 | { | |
592a252b | 10652 | /* MOD_VEX_0F73_REG_3 */ |
592d1631 | 10653 | { Bad_Opcode }, |
592a252b | 10654 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_3) }, |
475a2301 L |
10655 | }, |
10656 | { | |
592a252b | 10657 | /* MOD_VEX_0F73_REG_6 */ |
592d1631 | 10658 | { Bad_Opcode }, |
592a252b | 10659 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_6) }, |
876d4bfa L |
10660 | }, |
10661 | { | |
592a252b | 10662 | /* MOD_VEX_0F73_REG_7 */ |
592d1631 | 10663 | { Bad_Opcode }, |
592a252b | 10664 | { PREFIX_TABLE (PREFIX_VEX_0F73_REG_7) }, |
876d4bfa | 10665 | }, |
ab4e4ed5 AF |
10666 | { |
10667 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10668 | { "kmovw", { Ew, MaskG }, 0 }, | |
10669 | { Bad_Opcode }, | |
10670 | }, | |
10671 | { | |
10672 | /* MOD_VEX_W_0_0F91_P_0_LEN_0 */ | |
10673 | { "kmovq", { Eq, MaskG }, 0 }, | |
10674 | { Bad_Opcode }, | |
10675 | }, | |
10676 | { | |
10677 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10678 | { "kmovb", { Eb, MaskG }, 0 }, | |
10679 | { Bad_Opcode }, | |
10680 | }, | |
10681 | { | |
10682 | /* MOD_VEX_W_0_0F91_P_2_LEN_0 */ | |
10683 | { "kmovd", { Ed, MaskG }, 0 }, | |
10684 | { Bad_Opcode }, | |
10685 | }, | |
10686 | { | |
10687 | /* MOD_VEX_W_0_0F92_P_0_LEN_0 */ | |
10688 | { Bad_Opcode }, | |
10689 | { "kmovw", { MaskG, Rdq }, 0 }, | |
10690 | }, | |
10691 | { | |
10692 | /* MOD_VEX_W_0_0F92_P_2_LEN_0 */ | |
10693 | { Bad_Opcode }, | |
10694 | { "kmovb", { MaskG, Rdq }, 0 }, | |
10695 | }, | |
10696 | { | |
58a211d2 | 10697 | /* MOD_VEX_0F92_P_3_LEN_0 */ |
ab4e4ed5 | 10698 | { Bad_Opcode }, |
58a211d2 | 10699 | { "kmovK", { MaskG, Rdq }, 0 }, |
ab4e4ed5 AF |
10700 | }, |
10701 | { | |
10702 | /* MOD_VEX_W_0_0F93_P_0_LEN_0 */ | |
10703 | { Bad_Opcode }, | |
10704 | { "kmovw", { Gdq, MaskR }, 0 }, | |
10705 | }, | |
10706 | { | |
10707 | /* MOD_VEX_W_0_0F93_P_2_LEN_0 */ | |
10708 | { Bad_Opcode }, | |
10709 | { "kmovb", { Gdq, MaskR }, 0 }, | |
10710 | }, | |
10711 | { | |
58a211d2 | 10712 | /* MOD_VEX_0F93_P_3_LEN_0 */ |
ab4e4ed5 | 10713 | { Bad_Opcode }, |
58a211d2 | 10714 | { "kmovK", { Gdq, MaskR }, 0 }, |
ab4e4ed5 AF |
10715 | }, |
10716 | { | |
10717 | /* MOD_VEX_W_0_0F98_P_0_LEN_0 */ | |
10718 | { Bad_Opcode }, | |
10719 | { "kortestw", { MaskG, MaskR }, 0 }, | |
10720 | }, | |
10721 | { | |
10722 | /* MOD_VEX_W_1_0F98_P_0_LEN_0 */ | |
10723 | { Bad_Opcode }, | |
10724 | { "kortestq", { MaskG, MaskR }, 0 }, | |
10725 | }, | |
10726 | { | |
10727 | /* MOD_VEX_W_0_0F98_P_2_LEN_0 */ | |
10728 | { Bad_Opcode }, | |
10729 | { "kortestb", { MaskG, MaskR }, 0 }, | |
10730 | }, | |
10731 | { | |
10732 | /* MOD_VEX_W_1_0F98_P_2_LEN_0 */ | |
10733 | { Bad_Opcode }, | |
10734 | { "kortestd", { MaskG, MaskR }, 0 }, | |
10735 | }, | |
10736 | { | |
10737 | /* MOD_VEX_W_0_0F99_P_0_LEN_0 */ | |
10738 | { Bad_Opcode }, | |
10739 | { "ktestw", { MaskG, MaskR }, 0 }, | |
10740 | }, | |
10741 | { | |
10742 | /* MOD_VEX_W_1_0F99_P_0_LEN_0 */ | |
10743 | { Bad_Opcode }, | |
10744 | { "ktestq", { MaskG, MaskR }, 0 }, | |
10745 | }, | |
10746 | { | |
10747 | /* MOD_VEX_W_0_0F99_P_2_LEN_0 */ | |
10748 | { Bad_Opcode }, | |
10749 | { "ktestb", { MaskG, MaskR }, 0 }, | |
10750 | }, | |
10751 | { | |
10752 | /* MOD_VEX_W_1_0F99_P_2_LEN_0 */ | |
10753 | { Bad_Opcode }, | |
10754 | { "ktestd", { MaskG, MaskR }, 0 }, | |
10755 | }, | |
876d4bfa | 10756 | { |
592a252b L |
10757 | /* MOD_VEX_0FAE_REG_2 */ |
10758 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2_M_0) }, | |
876d4bfa | 10759 | }, |
bbedc832 | 10760 | { |
592a252b L |
10761 | /* MOD_VEX_0FAE_REG_3 */ |
10762 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3_M_0) }, | |
bbedc832 | 10763 | }, |
144c41d9 | 10764 | { |
592a252b | 10765 | /* MOD_VEX_0FD7_PREFIX_2 */ |
592d1631 | 10766 | { Bad_Opcode }, |
ec6f095a | 10767 | { "vpmovmskb", { Gdq, XS }, 0 }, |
144c41d9 | 10768 | }, |
1afd85e3 | 10769 | { |
592a252b | 10770 | /* MOD_VEX_0FE7_PREFIX_2 */ |
ec6f095a | 10771 | { "vmovntdq", { Mx, XM }, 0 }, |
1afd85e3 L |
10772 | }, |
10773 | { | |
592a252b | 10774 | /* MOD_VEX_0FF0_PREFIX_3 */ |
ec6f095a | 10775 | { "vlddqu", { XM, M }, 0 }, |
92fddf8e | 10776 | }, |
75c135a8 | 10777 | { |
592a252b L |
10778 | /* MOD_VEX_0F381A_PREFIX_2 */ |
10779 | { VEX_LEN_TABLE (VEX_LEN_0F381A_P_2_M_0) }, | |
75c135a8 | 10780 | }, |
1afd85e3 | 10781 | { |
592a252b | 10782 | /* MOD_VEX_0F382A_PREFIX_2 */ |
ec6f095a | 10783 | { "vmovntdqa", { XM, Mx }, 0 }, |
1afd85e3 | 10784 | }, |
75c135a8 | 10785 | { |
592a252b L |
10786 | /* MOD_VEX_0F382C_PREFIX_2 */ |
10787 | { VEX_W_TABLE (VEX_W_0F382C_P_2_M_0) }, | |
75c135a8 | 10788 | }, |
1afd85e3 | 10789 | { |
592a252b L |
10790 | /* MOD_VEX_0F382D_PREFIX_2 */ |
10791 | { VEX_W_TABLE (VEX_W_0F382D_P_2_M_0) }, | |
1afd85e3 L |
10792 | }, |
10793 | { | |
592a252b L |
10794 | /* MOD_VEX_0F382E_PREFIX_2 */ |
10795 | { VEX_W_TABLE (VEX_W_0F382E_P_2_M_0) }, | |
1afd85e3 L |
10796 | }, |
10797 | { | |
592a252b L |
10798 | /* MOD_VEX_0F382F_PREFIX_2 */ |
10799 | { VEX_W_TABLE (VEX_W_0F382F_P_2_M_0) }, | |
1afd85e3 | 10800 | }, |
6c30d220 L |
10801 | { |
10802 | /* MOD_VEX_0F385A_PREFIX_2 */ | |
10803 | { VEX_LEN_TABLE (VEX_LEN_0F385A_P_2_M_0) }, | |
10804 | }, | |
10805 | { | |
10806 | /* MOD_VEX_0F388C_PREFIX_2 */ | |
bf890a93 | 10807 | { "vpmaskmov%LW", { XM, Vex, Mx }, 0 }, |
6c30d220 L |
10808 | }, |
10809 | { | |
10810 | /* MOD_VEX_0F388E_PREFIX_2 */ | |
bf890a93 | 10811 | { "vpmaskmov%LW", { Mx, Vex, XM }, 0 }, |
6c30d220 | 10812 | }, |
ab4e4ed5 AF |
10813 | { |
10814 | /* MOD_VEX_W_0_0F3A30_P_2_LEN_0 */ | |
10815 | { Bad_Opcode }, | |
10816 | { "kshiftrb", { MaskG, MaskR, Ib }, 0 }, | |
10817 | }, | |
10818 | { | |
10819 | /* MOD_VEX_W_1_0F3A30_P_2_LEN_0 */ | |
10820 | { Bad_Opcode }, | |
10821 | { "kshiftrw", { MaskG, MaskR, Ib }, 0 }, | |
10822 | }, | |
10823 | { | |
10824 | /* MOD_VEX_W_0_0F3A31_P_2_LEN_0 */ | |
10825 | { Bad_Opcode }, | |
10826 | { "kshiftrd", { MaskG, MaskR, Ib }, 0 }, | |
10827 | }, | |
10828 | { | |
10829 | /* MOD_VEX_W_1_0F3A31_P_2_LEN_0 */ | |
10830 | { Bad_Opcode }, | |
10831 | { "kshiftrq", { MaskG, MaskR, Ib }, 0 }, | |
10832 | }, | |
10833 | { | |
10834 | /* MOD_VEX_W_0_0F3A32_P_2_LEN_0 */ | |
10835 | { Bad_Opcode }, | |
10836 | { "kshiftlb", { MaskG, MaskR, Ib }, 0 }, | |
10837 | }, | |
10838 | { | |
10839 | /* MOD_VEX_W_1_0F3A32_P_2_LEN_0 */ | |
10840 | { Bad_Opcode }, | |
10841 | { "kshiftlw", { MaskG, MaskR, Ib }, 0 }, | |
10842 | }, | |
10843 | { | |
10844 | /* MOD_VEX_W_0_0F3A33_P_2_LEN_0 */ | |
10845 | { Bad_Opcode }, | |
10846 | { "kshiftld", { MaskG, MaskR, Ib }, 0 }, | |
10847 | }, | |
10848 | { | |
10849 | /* MOD_VEX_W_1_0F3A33_P_2_LEN_0 */ | |
10850 | { Bad_Opcode }, | |
10851 | { "kshiftlq", { MaskG, MaskR, Ib }, 0 }, | |
10852 | }, | |
ad692897 L |
10853 | |
10854 | #include "i386-dis-evex-mod.h" | |
b844680a L |
10855 | }; |
10856 | ||
1ceb70f8 | 10857 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
10858 | { |
10859 | /* RM_C6_REG_7 */ | |
bf890a93 | 10860 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
10861 | }, |
10862 | { | |
10863 | /* RM_C7_REG_7 */ | |
376cd056 | 10864 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 10865 | }, |
b844680a | 10866 | { |
1ceb70f8 | 10867 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 10868 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
10869 | { "vmcall", { Skip_MODRM }, 0 }, |
10870 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
10871 | { "vmresume", { Skip_MODRM }, 0 }, | |
10872 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 10873 | { "pconfig", { Skip_MODRM }, 0 }, |
b844680a L |
10874 | }, |
10875 | { | |
1ceb70f8 | 10876 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
10877 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
10878 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
10879 | { "clac", { Skip_MODRM }, 0 }, | |
10880 | { "stac", { Skip_MODRM }, 0 }, | |
2cf200a4 IT |
10881 | { Bad_Opcode }, |
10882 | { Bad_Opcode }, | |
10883 | { Bad_Opcode }, | |
bf890a93 | 10884 | { "encls", { Skip_MODRM }, 0 }, |
b844680a | 10885 | }, |
475a2301 L |
10886 | { |
10887 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
10888 | { "xgetbv", { Skip_MODRM }, 0 }, |
10889 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
10890 | { Bad_Opcode }, |
10891 | { Bad_Opcode }, | |
bf890a93 IT |
10892 | { "vmfunc", { Skip_MODRM }, 0 }, |
10893 | { "xend", { Skip_MODRM }, 0 }, | |
10894 | { "xtest", { Skip_MODRM }, 0 }, | |
10895 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 10896 | }, |
b844680a | 10897 | { |
1ceb70f8 | 10898 | /* RM_0F01_REG_3 */ |
bf890a93 | 10899 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 10900 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
10901 | { "vmload", { Skip_MODRM }, 0 }, |
10902 | { "vmsave", { Skip_MODRM }, 0 }, | |
10903 | { "stgi", { Skip_MODRM }, 0 }, | |
10904 | { "clgi", { Skip_MODRM }, 0 }, | |
10905 | { "skinit", { Skip_MODRM }, 0 }, | |
10906 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 10907 | }, |
8eab4136 | 10908 | { |
f8687e93 JB |
10909 | /* RM_0F01_REG_5_MOD_3 */ |
10910 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 10911 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 10912 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 L |
10913 | { Bad_Opcode }, |
10914 | { Bad_Opcode }, | |
10915 | { Bad_Opcode }, | |
10916 | { "rdpkru", { Skip_MODRM }, 0 }, | |
10917 | { "wrpkru", { Skip_MODRM }, 0 }, | |
10918 | }, | |
4e7d34a6 | 10919 | { |
f8687e93 | 10920 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
10921 | { "swapgs", { Skip_MODRM }, 0 }, |
10922 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 JB |
10923 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
10924 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_3) }, | |
bf890a93 | 10925 | { "clzero", { Skip_MODRM }, 0 }, |
142861df | 10926 | { "rdpru", { Skip_MODRM }, 0 }, |
b844680a | 10927 | }, |
603555e5 | 10928 | { |
f8687e93 | 10929 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
603555e5 L |
10930 | { "nopQ", { Ev }, 0 }, |
10931 | { "nopQ", { Ev }, 0 }, | |
10932 | { "endbr64", { Skip_MODRM }, PREFIX_OPCODE }, | |
10933 | { "endbr32", { Skip_MODRM }, PREFIX_OPCODE }, | |
10934 | { "nopQ", { Ev }, 0 }, | |
10935 | { "nopQ", { Ev }, 0 }, | |
10936 | { "nopQ", { Ev }, 0 }, | |
10937 | { "nopQ", { Ev }, 0 }, | |
10938 | }, | |
b844680a | 10939 | { |
f8687e93 | 10940 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 10941 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 10942 | }, |
bbedc832 | 10943 | { |
f8687e93 | 10944 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca L |
10945 | { "sfence", { Skip_MODRM }, 0 }, |
10946 | ||
144c41d9 | 10947 | }, |
b844680a L |
10948 | }; |
10949 | ||
c608c12e AM |
10950 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
10951 | ||
f16cd0d5 L |
10952 | /* We use the high bit to indicate different name for the same |
10953 | prefix. */ | |
f16cd0d5 | 10954 | #define REP_PREFIX (0xf3 | 0x100) |
42164a71 L |
10955 | #define XACQUIRE_PREFIX (0xf2 | 0x200) |
10956 | #define XRELEASE_PREFIX (0xf3 | 0x400) | |
7e8b059b | 10957 | #define BND_PREFIX (0xf2 | 0x400) |
04ef582a | 10958 | #define NOTRACK_PREFIX (0x3e | 0x100) |
f16cd0d5 | 10959 | |
1d67fe3b TT |
10960 | /* Remember if the current op is a jump instruction. */ |
10961 | static bfd_boolean op_is_jump = FALSE; | |
10962 | ||
f16cd0d5 | 10963 | static int |
26ca5450 | 10964 | ckprefix (void) |
252b5132 | 10965 | { |
f16cd0d5 | 10966 | int newrex, i, length; |
52b15da3 | 10967 | rex = 0; |
252b5132 | 10968 | prefixes = 0; |
7d421014 | 10969 | used_prefixes = 0; |
52b15da3 | 10970 | rex_used = 0; |
f16cd0d5 L |
10971 | last_lock_prefix = -1; |
10972 | last_repz_prefix = -1; | |
10973 | last_repnz_prefix = -1; | |
10974 | last_data_prefix = -1; | |
10975 | last_addr_prefix = -1; | |
10976 | last_rex_prefix = -1; | |
10977 | last_seg_prefix = -1; | |
d9949a36 | 10978 | fwait_prefix = -1; |
285ca992 | 10979 | active_seg_prefix = 0; |
f310f33d L |
10980 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
10981 | all_prefixes[i] = 0; | |
10982 | i = 0; | |
f16cd0d5 L |
10983 | length = 0; |
10984 | /* The maximum instruction length is 15bytes. */ | |
10985 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 RH |
10986 | { |
10987 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 | 10988 | newrex = 0; |
252b5132 RH |
10989 | switch (*codep) |
10990 | { | |
52b15da3 JH |
10991 | /* REX prefixes family. */ |
10992 | case 0x40: | |
10993 | case 0x41: | |
10994 | case 0x42: | |
10995 | case 0x43: | |
10996 | case 0x44: | |
10997 | case 0x45: | |
10998 | case 0x46: | |
10999 | case 0x47: | |
11000 | case 0x48: | |
11001 | case 0x49: | |
11002 | case 0x4a: | |
11003 | case 0x4b: | |
11004 | case 0x4c: | |
11005 | case 0x4d: | |
11006 | case 0x4e: | |
11007 | case 0x4f: | |
f16cd0d5 L |
11008 | if (address_mode == mode_64bit) |
11009 | newrex = *codep; | |
11010 | else | |
11011 | return 1; | |
11012 | last_rex_prefix = i; | |
52b15da3 | 11013 | break; |
252b5132 RH |
11014 | case 0xf3: |
11015 | prefixes |= PREFIX_REPZ; | |
f16cd0d5 | 11016 | last_repz_prefix = i; |
252b5132 RH |
11017 | break; |
11018 | case 0xf2: | |
11019 | prefixes |= PREFIX_REPNZ; | |
f16cd0d5 | 11020 | last_repnz_prefix = i; |
252b5132 RH |
11021 | break; |
11022 | case 0xf0: | |
11023 | prefixes |= PREFIX_LOCK; | |
f16cd0d5 | 11024 | last_lock_prefix = i; |
252b5132 RH |
11025 | break; |
11026 | case 0x2e: | |
11027 | prefixes |= PREFIX_CS; | |
f16cd0d5 | 11028 | last_seg_prefix = i; |
285ca992 | 11029 | active_seg_prefix = PREFIX_CS; |
252b5132 RH |
11030 | break; |
11031 | case 0x36: | |
11032 | prefixes |= PREFIX_SS; | |
f16cd0d5 | 11033 | last_seg_prefix = i; |
285ca992 | 11034 | active_seg_prefix = PREFIX_SS; |
252b5132 RH |
11035 | break; |
11036 | case 0x3e: | |
11037 | prefixes |= PREFIX_DS; | |
f16cd0d5 | 11038 | last_seg_prefix = i; |
285ca992 | 11039 | active_seg_prefix = PREFIX_DS; |
252b5132 RH |
11040 | break; |
11041 | case 0x26: | |
11042 | prefixes |= PREFIX_ES; | |
f16cd0d5 | 11043 | last_seg_prefix = i; |
285ca992 | 11044 | active_seg_prefix = PREFIX_ES; |
252b5132 RH |
11045 | break; |
11046 | case 0x64: | |
11047 | prefixes |= PREFIX_FS; | |
f16cd0d5 | 11048 | last_seg_prefix = i; |
285ca992 | 11049 | active_seg_prefix = PREFIX_FS; |
252b5132 RH |
11050 | break; |
11051 | case 0x65: | |
11052 | prefixes |= PREFIX_GS; | |
f16cd0d5 | 11053 | last_seg_prefix = i; |
285ca992 | 11054 | active_seg_prefix = PREFIX_GS; |
252b5132 RH |
11055 | break; |
11056 | case 0x66: | |
11057 | prefixes |= PREFIX_DATA; | |
f16cd0d5 | 11058 | last_data_prefix = i; |
252b5132 RH |
11059 | break; |
11060 | case 0x67: | |
11061 | prefixes |= PREFIX_ADDR; | |
f16cd0d5 | 11062 | last_addr_prefix = i; |
252b5132 | 11063 | break; |
5076851f | 11064 | case FWAIT_OPCODE: |
252b5132 RH |
11065 | /* fwait is really an instruction. If there are prefixes |
11066 | before the fwait, they belong to the fwait, *not* to the | |
11067 | following instruction. */ | |
d9949a36 | 11068 | fwait_prefix = i; |
3e7d61b2 | 11069 | if (prefixes || rex) |
252b5132 RH |
11070 | { |
11071 | prefixes |= PREFIX_FWAIT; | |
11072 | codep++; | |
6c067bbb RM |
11073 | /* This ensures that the previous REX prefixes are noticed |
11074 | as unused prefixes, as in the return case below. */ | |
11075 | rex_used = rex; | |
f16cd0d5 | 11076 | return 1; |
252b5132 RH |
11077 | } |
11078 | prefixes = PREFIX_FWAIT; | |
11079 | break; | |
11080 | default: | |
f16cd0d5 | 11081 | return 1; |
252b5132 | 11082 | } |
52b15da3 JH |
11083 | /* Rex is ignored when followed by another prefix. */ |
11084 | if (rex) | |
11085 | { | |
3e7d61b2 | 11086 | rex_used = rex; |
f16cd0d5 | 11087 | return 1; |
52b15da3 | 11088 | } |
f16cd0d5 | 11089 | if (*codep != FWAIT_OPCODE) |
4e9ac44a | 11090 | all_prefixes[i++] = *codep; |
52b15da3 | 11091 | rex = newrex; |
252b5132 | 11092 | codep++; |
f16cd0d5 L |
11093 | length++; |
11094 | } | |
11095 | return 0; | |
11096 | } | |
11097 | ||
7d421014 ILT |
11098 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
11099 | prefix byte. */ | |
11100 | ||
11101 | static const char * | |
26ca5450 | 11102 | prefix_name (int pref, int sizeflag) |
7d421014 | 11103 | { |
0003779b L |
11104 | static const char *rexes [16] = |
11105 | { | |
11106 | "rex", /* 0x40 */ | |
11107 | "rex.B", /* 0x41 */ | |
11108 | "rex.X", /* 0x42 */ | |
11109 | "rex.XB", /* 0x43 */ | |
11110 | "rex.R", /* 0x44 */ | |
11111 | "rex.RB", /* 0x45 */ | |
11112 | "rex.RX", /* 0x46 */ | |
11113 | "rex.RXB", /* 0x47 */ | |
11114 | "rex.W", /* 0x48 */ | |
11115 | "rex.WB", /* 0x49 */ | |
11116 | "rex.WX", /* 0x4a */ | |
11117 | "rex.WXB", /* 0x4b */ | |
11118 | "rex.WR", /* 0x4c */ | |
11119 | "rex.WRB", /* 0x4d */ | |
11120 | "rex.WRX", /* 0x4e */ | |
11121 | "rex.WRXB", /* 0x4f */ | |
11122 | }; | |
11123 | ||
7d421014 ILT |
11124 | switch (pref) |
11125 | { | |
52b15da3 JH |
11126 | /* REX prefixes family. */ |
11127 | case 0x40: | |
52b15da3 | 11128 | case 0x41: |
52b15da3 | 11129 | case 0x42: |
52b15da3 | 11130 | case 0x43: |
52b15da3 | 11131 | case 0x44: |
52b15da3 | 11132 | case 0x45: |
52b15da3 | 11133 | case 0x46: |
52b15da3 | 11134 | case 0x47: |
52b15da3 | 11135 | case 0x48: |
52b15da3 | 11136 | case 0x49: |
52b15da3 | 11137 | case 0x4a: |
52b15da3 | 11138 | case 0x4b: |
52b15da3 | 11139 | case 0x4c: |
52b15da3 | 11140 | case 0x4d: |
52b15da3 | 11141 | case 0x4e: |
52b15da3 | 11142 | case 0x4f: |
0003779b | 11143 | return rexes [pref - 0x40]; |
7d421014 ILT |
11144 | case 0xf3: |
11145 | return "repz"; | |
11146 | case 0xf2: | |
11147 | return "repnz"; | |
11148 | case 0xf0: | |
11149 | return "lock"; | |
11150 | case 0x2e: | |
11151 | return "cs"; | |
11152 | case 0x36: | |
11153 | return "ss"; | |
11154 | case 0x3e: | |
11155 | return "ds"; | |
11156 | case 0x26: | |
11157 | return "es"; | |
11158 | case 0x64: | |
11159 | return "fs"; | |
11160 | case 0x65: | |
11161 | return "gs"; | |
11162 | case 0x66: | |
11163 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
11164 | case 0x67: | |
cb712a9e | 11165 | if (address_mode == mode_64bit) |
db6eb5be | 11166 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 11167 | else |
2888cb7a | 11168 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
11169 | case FWAIT_OPCODE: |
11170 | return "fwait"; | |
f16cd0d5 L |
11171 | case REP_PREFIX: |
11172 | return "rep"; | |
42164a71 L |
11173 | case XACQUIRE_PREFIX: |
11174 | return "xacquire"; | |
11175 | case XRELEASE_PREFIX: | |
11176 | return "xrelease"; | |
7e8b059b L |
11177 | case BND_PREFIX: |
11178 | return "bnd"; | |
04ef582a L |
11179 | case NOTRACK_PREFIX: |
11180 | return "notrack"; | |
7d421014 ILT |
11181 | default: |
11182 | return NULL; | |
11183 | } | |
11184 | } | |
11185 | ||
ce518a5f L |
11186 | static char op_out[MAX_OPERANDS][100]; |
11187 | static int op_ad, op_index[MAX_OPERANDS]; | |
1d9f512f | 11188 | static int two_source_ops; |
ce518a5f L |
11189 | static bfd_vma op_address[MAX_OPERANDS]; |
11190 | static bfd_vma op_riprel[MAX_OPERANDS]; | |
52b15da3 | 11191 | static bfd_vma start_pc; |
ce518a5f | 11192 | |
252b5132 RH |
11193 | /* |
11194 | * On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
11195 | * (see topic "Redundant prefixes" in the "Differences from 8086" | |
11196 | * section of the "Virtual 8086 Mode" chapter.) | |
11197 | * 'pc' should be the address of this instruction, it will | |
11198 | * be used to print the target address if this is a relative jump or call | |
11199 | * The function returns the length of this instruction in bytes. | |
11200 | */ | |
11201 | ||
252b5132 | 11202 | static char intel_syntax; |
9d141669 | 11203 | static char intel_mnemonic = !SYSV386_COMPAT; |
252b5132 RH |
11204 | static char open_char; |
11205 | static char close_char; | |
11206 | static char separator_char; | |
11207 | static char scale_char; | |
11208 | ||
5db04b09 L |
11209 | enum x86_64_isa |
11210 | { | |
d835a58b | 11211 | amd64 = 1, |
5db04b09 L |
11212 | intel64 |
11213 | }; | |
11214 | ||
11215 | static enum x86_64_isa isa64; | |
11216 | ||
e396998b AM |
11217 | /* Here for backwards compatibility. When gdb stops using |
11218 | print_insn_i386_att and print_insn_i386_intel these functions can | |
11219 | disappear, and print_insn_i386 be merged into print_insn. */ | |
252b5132 | 11220 | int |
26ca5450 | 11221 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11222 | { |
11223 | intel_syntax = 0; | |
e396998b AM |
11224 | |
11225 | return print_insn (pc, info); | |
252b5132 RH |
11226 | } |
11227 | ||
11228 | int | |
26ca5450 | 11229 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) |
252b5132 RH |
11230 | { |
11231 | intel_syntax = 1; | |
e396998b AM |
11232 | |
11233 | return print_insn (pc, info); | |
252b5132 RH |
11234 | } |
11235 | ||
e396998b | 11236 | int |
26ca5450 | 11237 | print_insn_i386 (bfd_vma pc, disassemble_info *info) |
e396998b AM |
11238 | { |
11239 | intel_syntax = -1; | |
11240 | ||
11241 | return print_insn (pc, info); | |
11242 | } | |
11243 | ||
f59a29b9 L |
11244 | void |
11245 | print_i386_disassembler_options (FILE *stream) | |
11246 | { | |
11247 | fprintf (stream, _("\n\ | |
11248 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
11249 | with the -M switch (multiple options should be separated by commas):\n")); | |
11250 | ||
11251 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
11252 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
11253 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
11254 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
11255 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
11256 | fprintf (stream, _(" att-mnemonic\n" |
11257 | " Display instruction in AT&T mnemonic\n")); | |
11258 | fprintf (stream, _(" intel-mnemonic\n" | |
11259 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
11260 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
11261 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
11262 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
11263 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
11264 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
11265 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
11266 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
11267 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
11268 | } |
11269 | ||
592d1631 | 11270 | /* Bad opcode. */ |
bf890a93 | 11271 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 11272 | |
b844680a L |
11273 | /* Get a pointer to struct dis386 with a valid name. */ |
11274 | ||
11275 | static const struct dis386 * | |
8bb15339 | 11276 | get_valid_dis386 (const struct dis386 *dp, disassemble_info *info) |
b844680a | 11277 | { |
91d6fa6a | 11278 | int vindex, vex_table_index; |
b844680a L |
11279 | |
11280 | if (dp->name != NULL) | |
11281 | return dp; | |
11282 | ||
11283 | switch (dp->op[0].bytemode) | |
11284 | { | |
1ceb70f8 L |
11285 | case USE_REG_TABLE: |
11286 | dp = ®_table[dp->op[1].bytemode][modrm.reg]; | |
11287 | break; | |
11288 | ||
11289 | case USE_MOD_TABLE: | |
91d6fa6a NC |
11290 | vindex = modrm.mod == 0x3 ? 1 : 0; |
11291 | dp = &mod_table[dp->op[1].bytemode][vindex]; | |
1ceb70f8 L |
11292 | break; |
11293 | ||
11294 | case USE_RM_TABLE: | |
11295 | dp = &rm_table[dp->op[1].bytemode][modrm.rm]; | |
b844680a L |
11296 | break; |
11297 | ||
4e7d34a6 | 11298 | case USE_PREFIX_TABLE: |
c0f3af97 | 11299 | if (need_vex) |
b844680a | 11300 | { |
c0f3af97 L |
11301 | /* The prefix in VEX is implicit. */ |
11302 | switch (vex.prefix) | |
11303 | { | |
11304 | case 0: | |
91d6fa6a | 11305 | vindex = 0; |
c0f3af97 L |
11306 | break; |
11307 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 11308 | vindex = 1; |
c0f3af97 L |
11309 | break; |
11310 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 11311 | vindex = 2; |
c0f3af97 L |
11312 | break; |
11313 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 11314 | vindex = 3; |
c0f3af97 L |
11315 | break; |
11316 | default: | |
11317 | abort (); | |
11318 | break; | |
11319 | } | |
b844680a | 11320 | } |
7bb15c6f | 11321 | else |
b844680a | 11322 | { |
285ca992 L |
11323 | int last_prefix = -1; |
11324 | int prefix = 0; | |
91d6fa6a | 11325 | vindex = 0; |
285ca992 L |
11326 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
11327 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
11328 | last one wins. */ | |
11329 | if ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
b844680a | 11330 | { |
285ca992 | 11331 | if (last_repz_prefix > last_repnz_prefix) |
c0f3af97 | 11332 | { |
285ca992 L |
11333 | vindex = 1; |
11334 | prefix = PREFIX_REPZ; | |
11335 | last_prefix = last_repz_prefix; | |
c0f3af97 L |
11336 | } |
11337 | else | |
b844680a | 11338 | { |
285ca992 L |
11339 | vindex = 3; |
11340 | prefix = PREFIX_REPNZ; | |
11341 | last_prefix = last_repnz_prefix; | |
b844680a | 11342 | } |
285ca992 | 11343 | |
507bd325 L |
11344 | /* Check if prefix should be ignored. */ |
11345 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
11346 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
11347 | & prefix) != 0) | |
285ca992 L |
11348 | vindex = 0; |
11349 | } | |
11350 | ||
11351 | if (vindex == 0 && (prefixes & PREFIX_DATA) != 0) | |
11352 | { | |
11353 | vindex = 2; | |
11354 | prefix = PREFIX_DATA; | |
11355 | last_prefix = last_data_prefix; | |
11356 | } | |
11357 | ||
11358 | if (vindex != 0) | |
11359 | { | |
11360 | used_prefixes |= prefix; | |
11361 | all_prefixes[last_prefix] = 0; | |
b844680a L |
11362 | } |
11363 | } | |
91d6fa6a | 11364 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
11365 | break; |
11366 | ||
4e7d34a6 | 11367 | case USE_X86_64_TABLE: |
91d6fa6a NC |
11368 | vindex = address_mode == mode_64bit ? 1 : 0; |
11369 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; | |
b844680a L |
11370 | break; |
11371 | ||
4e7d34a6 | 11372 | case USE_3BYTE_TABLE: |
8bb15339 | 11373 | FETCH_DATA (info, codep + 2); |
91d6fa6a NC |
11374 | vindex = *codep++; |
11375 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11376 | end_codep = codep; |
8bb15339 L |
11377 | modrm.mod = (*codep >> 6) & 3; |
11378 | modrm.reg = (*codep >> 3) & 7; | |
11379 | modrm.rm = *codep & 7; | |
11380 | break; | |
11381 | ||
c0f3af97 L |
11382 | case USE_VEX_LEN_TABLE: |
11383 | if (!need_vex) | |
11384 | abort (); | |
11385 | ||
11386 | switch (vex.length) | |
11387 | { | |
11388 | case 128: | |
91d6fa6a | 11389 | vindex = 0; |
c0f3af97 L |
11390 | break; |
11391 | case 256: | |
91d6fa6a | 11392 | vindex = 1; |
c0f3af97 L |
11393 | break; |
11394 | default: | |
11395 | abort (); | |
11396 | break; | |
11397 | } | |
11398 | ||
91d6fa6a | 11399 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
11400 | break; |
11401 | ||
04e2a182 L |
11402 | case USE_EVEX_LEN_TABLE: |
11403 | if (!vex.evex) | |
11404 | abort (); | |
11405 | ||
11406 | switch (vex.length) | |
11407 | { | |
11408 | case 128: | |
11409 | vindex = 0; | |
11410 | break; | |
11411 | case 256: | |
11412 | vindex = 1; | |
11413 | break; | |
11414 | case 512: | |
11415 | vindex = 2; | |
11416 | break; | |
11417 | default: | |
11418 | abort (); | |
11419 | break; | |
11420 | } | |
11421 | ||
11422 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
11423 | break; | |
11424 | ||
f88c9eb0 SP |
11425 | case USE_XOP_8F_TABLE: |
11426 | FETCH_DATA (info, codep + 3); | |
f88c9eb0 SP |
11427 | rex = ~(*codep >> 5) & 0x7; |
11428 | ||
11429 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
11430 | switch ((*codep & 0x1f)) | |
11431 | { | |
11432 | default: | |
f07af43e L |
11433 | dp = &bad_opcode; |
11434 | return dp; | |
5dd85c99 SP |
11435 | case 0x8: |
11436 | vex_table_index = XOP_08; | |
11437 | break; | |
f88c9eb0 SP |
11438 | case 0x9: |
11439 | vex_table_index = XOP_09; | |
11440 | break; | |
11441 | case 0xa: | |
11442 | vex_table_index = XOP_0A; | |
11443 | break; | |
11444 | } | |
11445 | codep++; | |
11446 | vex.w = *codep & 0x80; | |
11447 | if (vex.w && address_mode == mode_64bit) | |
11448 | rex |= REX_W; | |
11449 | ||
11450 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
abfcb414 | 11451 | if (address_mode != mode_64bit) |
f07af43e | 11452 | { |
abfcb414 AP |
11453 | /* In 16/32-bit mode REX_B is silently ignored. */ |
11454 | rex &= ~REX_B; | |
f07af43e | 11455 | } |
f88c9eb0 SP |
11456 | |
11457 | vex.length = (*codep & 0x4) ? 256 : 128; | |
11458 | switch ((*codep & 0x3)) | |
11459 | { | |
11460 | case 0: | |
f88c9eb0 SP |
11461 | break; |
11462 | case 1: | |
11463 | vex.prefix = DATA_PREFIX_OPCODE; | |
11464 | break; | |
11465 | case 2: | |
11466 | vex.prefix = REPE_PREFIX_OPCODE; | |
11467 | break; | |
11468 | case 3: | |
11469 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11470 | break; | |
11471 | } | |
11472 | need_vex = 1; | |
11473 | need_vex_reg = 1; | |
11474 | codep++; | |
91d6fa6a NC |
11475 | vindex = *codep++; |
11476 | dp = &xop_table[vex_table_index][vindex]; | |
c48244a5 | 11477 | |
285ca992 | 11478 | end_codep = codep; |
c48244a5 SP |
11479 | FETCH_DATA (info, codep + 1); |
11480 | modrm.mod = (*codep >> 6) & 3; | |
11481 | modrm.reg = (*codep >> 3) & 7; | |
11482 | modrm.rm = *codep & 7; | |
b5b098c2 JB |
11483 | |
11484 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
11485 | having to decode the bits for every otherwise valid encoding. */ | |
11486 | if (vex.prefix) | |
11487 | return &bad_opcode; | |
f88c9eb0 SP |
11488 | break; |
11489 | ||
c0f3af97 | 11490 | case USE_VEX_C4_TABLE: |
43234a1e | 11491 | /* VEX prefix. */ |
c0f3af97 | 11492 | FETCH_DATA (info, codep + 3); |
c0f3af97 L |
11493 | rex = ~(*codep >> 5) & 0x7; |
11494 | switch ((*codep & 0x1f)) | |
11495 | { | |
11496 | default: | |
f07af43e L |
11497 | dp = &bad_opcode; |
11498 | return dp; | |
c0f3af97 | 11499 | case 0x1: |
f88c9eb0 | 11500 | vex_table_index = VEX_0F; |
c0f3af97 L |
11501 | break; |
11502 | case 0x2: | |
f88c9eb0 | 11503 | vex_table_index = VEX_0F38; |
c0f3af97 L |
11504 | break; |
11505 | case 0x3: | |
f88c9eb0 | 11506 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
11507 | break; |
11508 | } | |
11509 | codep++; | |
11510 | vex.w = *codep & 0x80; | |
9889cbb1 | 11511 | if (address_mode == mode_64bit) |
f07af43e | 11512 | { |
9889cbb1 L |
11513 | if (vex.w) |
11514 | rex |= REX_W; | |
9889cbb1 L |
11515 | } |
11516 | else | |
11517 | { | |
11518 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
11519 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 11520 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
9889cbb1 | 11521 | rex = 0; |
f07af43e | 11522 | } |
5f847646 | 11523 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11524 | vex.length = (*codep & 0x4) ? 256 : 128; |
11525 | switch ((*codep & 0x3)) | |
11526 | { | |
11527 | case 0: | |
c0f3af97 L |
11528 | break; |
11529 | case 1: | |
11530 | vex.prefix = DATA_PREFIX_OPCODE; | |
11531 | break; | |
11532 | case 2: | |
11533 | vex.prefix = REPE_PREFIX_OPCODE; | |
11534 | break; | |
11535 | case 3: | |
11536 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11537 | break; | |
11538 | } | |
11539 | need_vex = 1; | |
11540 | need_vex_reg = 1; | |
11541 | codep++; | |
91d6fa6a NC |
11542 | vindex = *codep++; |
11543 | dp = &vex_table[vex_table_index][vindex]; | |
285ca992 | 11544 | end_codep = codep; |
53c4d625 JB |
11545 | /* There is no MODRM byte for VEX0F 77. */ |
11546 | if (vex_table_index != VEX_0F || vindex != 0x77) | |
c0f3af97 L |
11547 | { |
11548 | FETCH_DATA (info, codep + 1); | |
11549 | modrm.mod = (*codep >> 6) & 3; | |
11550 | modrm.reg = (*codep >> 3) & 7; | |
11551 | modrm.rm = *codep & 7; | |
11552 | } | |
11553 | break; | |
11554 | ||
11555 | case USE_VEX_C5_TABLE: | |
43234a1e | 11556 | /* VEX prefix. */ |
c0f3af97 | 11557 | FETCH_DATA (info, codep + 2); |
c0f3af97 L |
11558 | rex = (*codep & 0x80) ? 0 : REX_R; |
11559 | ||
9889cbb1 L |
11560 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
11561 | VEX.vvvv is 1. */ | |
c0f3af97 | 11562 | vex.register_specifier = (~(*codep >> 3)) & 0xf; |
c0f3af97 L |
11563 | vex.length = (*codep & 0x4) ? 256 : 128; |
11564 | switch ((*codep & 0x3)) | |
11565 | { | |
11566 | case 0: | |
c0f3af97 L |
11567 | break; |
11568 | case 1: | |
11569 | vex.prefix = DATA_PREFIX_OPCODE; | |
11570 | break; | |
11571 | case 2: | |
11572 | vex.prefix = REPE_PREFIX_OPCODE; | |
11573 | break; | |
11574 | case 3: | |
11575 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11576 | break; | |
11577 | } | |
11578 | need_vex = 1; | |
11579 | need_vex_reg = 1; | |
11580 | codep++; | |
91d6fa6a NC |
11581 | vindex = *codep++; |
11582 | dp = &vex_table[dp->op[1].bytemode][vindex]; | |
285ca992 | 11583 | end_codep = codep; |
53c4d625 JB |
11584 | /* There is no MODRM byte for VEX 77. */ |
11585 | if (vindex != 0x77) | |
c0f3af97 L |
11586 | { |
11587 | FETCH_DATA (info, codep + 1); | |
11588 | modrm.mod = (*codep >> 6) & 3; | |
11589 | modrm.reg = (*codep >> 3) & 7; | |
11590 | modrm.rm = *codep & 7; | |
11591 | } | |
11592 | break; | |
11593 | ||
9e30b8e0 L |
11594 | case USE_VEX_W_TABLE: |
11595 | if (!need_vex) | |
11596 | abort (); | |
11597 | ||
11598 | dp = &vex_w_table[dp->op[1].bytemode][vex.w ? 1 : 0]; | |
11599 | break; | |
11600 | ||
43234a1e L |
11601 | case USE_EVEX_TABLE: |
11602 | two_source_ops = 0; | |
11603 | /* EVEX prefix. */ | |
11604 | vex.evex = 1; | |
11605 | FETCH_DATA (info, codep + 4); | |
43234a1e L |
11606 | /* The first byte after 0x62. */ |
11607 | rex = ~(*codep >> 5) & 0x7; | |
11608 | vex.r = *codep & 0x10; | |
11609 | switch ((*codep & 0xf)) | |
11610 | { | |
11611 | default: | |
11612 | return &bad_opcode; | |
11613 | case 0x1: | |
11614 | vex_table_index = EVEX_0F; | |
11615 | break; | |
11616 | case 0x2: | |
11617 | vex_table_index = EVEX_0F38; | |
11618 | break; | |
11619 | case 0x3: | |
11620 | vex_table_index = EVEX_0F3A; | |
11621 | break; | |
11622 | } | |
11623 | ||
11624 | /* The second byte after 0x62. */ | |
11625 | codep++; | |
11626 | vex.w = *codep & 0x80; | |
11627 | if (vex.w && address_mode == mode_64bit) | |
11628 | rex |= REX_W; | |
11629 | ||
11630 | vex.register_specifier = (~(*codep >> 3)) & 0xf; | |
43234a1e L |
11631 | |
11632 | /* The U bit. */ | |
11633 | if (!(*codep & 0x4)) | |
11634 | return &bad_opcode; | |
11635 | ||
11636 | switch ((*codep & 0x3)) | |
11637 | { | |
11638 | case 0: | |
43234a1e L |
11639 | break; |
11640 | case 1: | |
11641 | vex.prefix = DATA_PREFIX_OPCODE; | |
11642 | break; | |
11643 | case 2: | |
11644 | vex.prefix = REPE_PREFIX_OPCODE; | |
11645 | break; | |
11646 | case 3: | |
11647 | vex.prefix = REPNE_PREFIX_OPCODE; | |
11648 | break; | |
11649 | } | |
11650 | ||
11651 | /* The third byte after 0x62. */ | |
11652 | codep++; | |
11653 | ||
11654 | /* Remember the static rounding bits. */ | |
11655 | vex.ll = (*codep >> 5) & 3; | |
11656 | vex.b = (*codep & 0x10) != 0; | |
11657 | ||
11658 | vex.v = *codep & 0x8; | |
11659 | vex.mask_register_specifier = *codep & 0x7; | |
11660 | vex.zeroing = *codep & 0x80; | |
11661 | ||
5f847646 JB |
11662 | if (address_mode != mode_64bit) |
11663 | { | |
11664 | /* In 16/32-bit mode silently ignore following bits. */ | |
11665 | rex &= ~REX_B; | |
11666 | vex.r = 1; | |
11667 | vex.v = 1; | |
11668 | } | |
11669 | ||
43234a1e L |
11670 | need_vex = 1; |
11671 | need_vex_reg = 1; | |
11672 | codep++; | |
11673 | vindex = *codep++; | |
11674 | dp = &evex_table[vex_table_index][vindex]; | |
285ca992 | 11675 | end_codep = codep; |
43234a1e L |
11676 | FETCH_DATA (info, codep + 1); |
11677 | modrm.mod = (*codep >> 6) & 3; | |
11678 | modrm.reg = (*codep >> 3) & 7; | |
11679 | modrm.rm = *codep & 7; | |
11680 | ||
11681 | /* Set vector length. */ | |
11682 | if (modrm.mod == 3 && vex.b) | |
11683 | vex.length = 512; | |
11684 | else | |
11685 | { | |
11686 | switch (vex.ll) | |
11687 | { | |
11688 | case 0x0: | |
11689 | vex.length = 128; | |
11690 | break; | |
11691 | case 0x1: | |
11692 | vex.length = 256; | |
11693 | break; | |
11694 | case 0x2: | |
11695 | vex.length = 512; | |
11696 | break; | |
11697 | default: | |
11698 | return &bad_opcode; | |
11699 | } | |
11700 | } | |
11701 | break; | |
11702 | ||
592d1631 L |
11703 | case 0: |
11704 | dp = &bad_opcode; | |
11705 | break; | |
11706 | ||
b844680a | 11707 | default: |
d34b5006 | 11708 | abort (); |
b844680a L |
11709 | } |
11710 | ||
11711 | if (dp->name != NULL) | |
11712 | return dp; | |
11713 | else | |
8bb15339 | 11714 | return get_valid_dis386 (dp, info); |
b844680a L |
11715 | } |
11716 | ||
dfc8cf43 | 11717 | static void |
55cf16e1 | 11718 | get_sib (disassemble_info *info, int sizeflag) |
dfc8cf43 L |
11719 | { |
11720 | /* If modrm.mod == 3, operand must be register. */ | |
11721 | if (need_modrm | |
55cf16e1 | 11722 | && ((sizeflag & AFLAG) || address_mode == mode_64bit) |
dfc8cf43 L |
11723 | && modrm.mod != 3 |
11724 | && modrm.rm == 4) | |
11725 | { | |
11726 | FETCH_DATA (info, codep + 2); | |
11727 | sib.index = (codep [1] >> 3) & 7; | |
11728 | sib.scale = (codep [1] >> 6) & 3; | |
11729 | sib.base = codep [1] & 7; | |
11730 | } | |
11731 | } | |
11732 | ||
e396998b | 11733 | static int |
26ca5450 | 11734 | print_insn (bfd_vma pc, disassemble_info *info) |
252b5132 | 11735 | { |
2da11e11 | 11736 | const struct dis386 *dp; |
252b5132 | 11737 | int i; |
ce518a5f | 11738 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 11739 | int needcomma; |
df18fdba | 11740 | int sizeflag, orig_sizeflag; |
e396998b | 11741 | const char *p; |
252b5132 | 11742 | struct dis_private priv; |
f16cd0d5 | 11743 | int prefix_length; |
252b5132 | 11744 | |
d7921315 L |
11745 | priv.orig_sizeflag = AFLAG | DFLAG; |
11746 | if ((info->mach & bfd_mach_i386_i386) != 0) | |
cb712a9e | 11747 | address_mode = mode_32bit; |
2da11e11 | 11748 | else if (info->mach == bfd_mach_i386_i8086) |
d7921315 L |
11749 | { |
11750 | address_mode = mode_16bit; | |
11751 | priv.orig_sizeflag = 0; | |
11752 | } | |
2da11e11 | 11753 | else |
d7921315 L |
11754 | address_mode = mode_64bit; |
11755 | ||
11756 | if (intel_syntax == (char) -1) | |
11757 | intel_syntax = (info->mach & bfd_mach_i386_intel_syntax) != 0; | |
e396998b AM |
11758 | |
11759 | for (p = info->disassembler_options; p != NULL; ) | |
11760 | { | |
5db04b09 L |
11761 | if (CONST_STRNEQ (p, "amd64")) |
11762 | isa64 = amd64; | |
11763 | else if (CONST_STRNEQ (p, "intel64")) | |
11764 | isa64 = intel64; | |
11765 | else if (CONST_STRNEQ (p, "x86-64")) | |
e396998b | 11766 | { |
cb712a9e | 11767 | address_mode = mode_64bit; |
2a1bb84c | 11768 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11769 | } |
0112cd26 | 11770 | else if (CONST_STRNEQ (p, "i386")) |
e396998b | 11771 | { |
cb712a9e | 11772 | address_mode = mode_32bit; |
2a1bb84c | 11773 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 11774 | } |
0112cd26 | 11775 | else if (CONST_STRNEQ (p, "i8086")) |
e396998b | 11776 | { |
cb712a9e | 11777 | address_mode = mode_16bit; |
2a1bb84c | 11778 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 11779 | } |
0112cd26 | 11780 | else if (CONST_STRNEQ (p, "intel")) |
e396998b AM |
11781 | { |
11782 | intel_syntax = 1; | |
9d141669 L |
11783 | if (CONST_STRNEQ (p + 5, "-mnemonic")) |
11784 | intel_mnemonic = 1; | |
e396998b | 11785 | } |
0112cd26 | 11786 | else if (CONST_STRNEQ (p, "att")) |
e396998b AM |
11787 | { |
11788 | intel_syntax = 0; | |
9d141669 L |
11789 | if (CONST_STRNEQ (p + 3, "-mnemonic")) |
11790 | intel_mnemonic = 0; | |
e396998b | 11791 | } |
0112cd26 | 11792 | else if (CONST_STRNEQ (p, "addr")) |
e396998b | 11793 | { |
f59a29b9 L |
11794 | if (address_mode == mode_64bit) |
11795 | { | |
11796 | if (p[4] == '3' && p[5] == '2') | |
11797 | priv.orig_sizeflag &= ~AFLAG; | |
11798 | else if (p[4] == '6' && p[5] == '4') | |
11799 | priv.orig_sizeflag |= AFLAG; | |
11800 | } | |
11801 | else | |
11802 | { | |
11803 | if (p[4] == '1' && p[5] == '6') | |
11804 | priv.orig_sizeflag &= ~AFLAG; | |
11805 | else if (p[4] == '3' && p[5] == '2') | |
11806 | priv.orig_sizeflag |= AFLAG; | |
11807 | } | |
e396998b | 11808 | } |
0112cd26 | 11809 | else if (CONST_STRNEQ (p, "data")) |
e396998b AM |
11810 | { |
11811 | if (p[4] == '1' && p[5] == '6') | |
11812 | priv.orig_sizeflag &= ~DFLAG; | |
11813 | else if (p[4] == '3' && p[5] == '2') | |
11814 | priv.orig_sizeflag |= DFLAG; | |
11815 | } | |
0112cd26 | 11816 | else if (CONST_STRNEQ (p, "suffix")) |
e396998b AM |
11817 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
11818 | ||
11819 | p = strchr (p, ','); | |
11820 | if (p != NULL) | |
11821 | p++; | |
11822 | } | |
11823 | ||
c0f92bf9 L |
11824 | if (address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
11825 | { | |
11826 | (*info->fprintf_func) (info->stream, | |
11827 | _("64-bit address is disabled")); | |
11828 | return -1; | |
11829 | } | |
11830 | ||
e396998b AM |
11831 | if (intel_syntax) |
11832 | { | |
11833 | names64 = intel_names64; | |
11834 | names32 = intel_names32; | |
11835 | names16 = intel_names16; | |
11836 | names8 = intel_names8; | |
11837 | names8rex = intel_names8rex; | |
11838 | names_seg = intel_names_seg; | |
b9733481 | 11839 | names_mm = intel_names_mm; |
7e8b059b | 11840 | names_bnd = intel_names_bnd; |
b9733481 L |
11841 | names_xmm = intel_names_xmm; |
11842 | names_ymm = intel_names_ymm; | |
43234a1e | 11843 | names_zmm = intel_names_zmm; |
db51cc60 L |
11844 | index64 = intel_index64; |
11845 | index32 = intel_index32; | |
43234a1e | 11846 | names_mask = intel_names_mask; |
e396998b AM |
11847 | index16 = intel_index16; |
11848 | open_char = '['; | |
11849 | close_char = ']'; | |
11850 | separator_char = '+'; | |
11851 | scale_char = '*'; | |
11852 | } | |
11853 | else | |
11854 | { | |
11855 | names64 = att_names64; | |
11856 | names32 = att_names32; | |
11857 | names16 = att_names16; | |
11858 | names8 = att_names8; | |
11859 | names8rex = att_names8rex; | |
11860 | names_seg = att_names_seg; | |
b9733481 | 11861 | names_mm = att_names_mm; |
7e8b059b | 11862 | names_bnd = att_names_bnd; |
b9733481 L |
11863 | names_xmm = att_names_xmm; |
11864 | names_ymm = att_names_ymm; | |
43234a1e | 11865 | names_zmm = att_names_zmm; |
db51cc60 L |
11866 | index64 = att_index64; |
11867 | index32 = att_index32; | |
43234a1e | 11868 | names_mask = att_names_mask; |
e396998b AM |
11869 | index16 = att_index16; |
11870 | open_char = '('; | |
11871 | close_char = ')'; | |
11872 | separator_char = ','; | |
11873 | scale_char = ','; | |
11874 | } | |
2da11e11 | 11875 | |
4fe53c98 | 11876 | /* The output looks better if we put 7 bytes on a line, since that |
8a9036a4 L |
11877 | puts most long word instructions on a single line. Use 8 bytes |
11878 | for Intel L1OM. */ | |
d7921315 | 11879 | if ((info->mach & bfd_mach_l1om) != 0) |
8a9036a4 L |
11880 | info->bytes_per_line = 8; |
11881 | else | |
11882 | info->bytes_per_line = 7; | |
252b5132 | 11883 | |
26ca5450 | 11884 | info->private_data = &priv; |
252b5132 RH |
11885 | priv.max_fetched = priv.the_buffer; |
11886 | priv.insn_start = pc; | |
252b5132 RH |
11887 | |
11888 | obuf[0] = 0; | |
ce518a5f L |
11889 | for (i = 0; i < MAX_OPERANDS; ++i) |
11890 | { | |
11891 | op_out[i][0] = 0; | |
11892 | op_index[i] = -1; | |
11893 | } | |
252b5132 RH |
11894 | |
11895 | the_info = info; | |
11896 | start_pc = pc; | |
e396998b AM |
11897 | start_codep = priv.the_buffer; |
11898 | codep = priv.the_buffer; | |
252b5132 | 11899 | |
8df14d78 | 11900 | if (OPCODES_SIGSETJMP (priv.bailout) != 0) |
5076851f | 11901 | { |
7d421014 ILT |
11902 | const char *name; |
11903 | ||
5076851f | 11904 | /* Getting here means we tried for data but didn't get it. That |
e396998b AM |
11905 | means we have an incomplete instruction of some sort. Just |
11906 | print the first byte as a prefix or a .byte pseudo-op. */ | |
11907 | if (codep > priv.the_buffer) | |
5076851f | 11908 | { |
e396998b | 11909 | name = prefix_name (priv.the_buffer[0], priv.orig_sizeflag); |
7d421014 ILT |
11910 | if (name != NULL) |
11911 | (*info->fprintf_func) (info->stream, "%s", name); | |
11912 | else | |
5076851f | 11913 | { |
7d421014 ILT |
11914 | /* Just print the first byte as a .byte instruction. */ |
11915 | (*info->fprintf_func) (info->stream, ".byte 0x%x", | |
e396998b | 11916 | (unsigned int) priv.the_buffer[0]); |
5076851f | 11917 | } |
5076851f | 11918 | |
7d421014 | 11919 | return 1; |
5076851f ILT |
11920 | } |
11921 | ||
11922 | return -1; | |
11923 | } | |
11924 | ||
52b15da3 | 11925 | obufp = obuf; |
f16cd0d5 L |
11926 | sizeflag = priv.orig_sizeflag; |
11927 | ||
11928 | if (!ckprefix () || rex_used) | |
11929 | { | |
11930 | /* Too many prefixes or unused REX prefixes. */ | |
11931 | for (i = 0; | |
f6dd4781 | 11932 | i < (int) ARRAY_SIZE (all_prefixes) && all_prefixes[i]; |
f16cd0d5 | 11933 | i++) |
de882298 | 11934 | (*info->fprintf_func) (info->stream, "%s%s", |
6c067bbb | 11935 | i == 0 ? "" : " ", |
f16cd0d5 | 11936 | prefix_name (all_prefixes[i], sizeflag)); |
de882298 | 11937 | return i; |
f16cd0d5 | 11938 | } |
252b5132 RH |
11939 | |
11940 | insn_codep = codep; | |
11941 | ||
11942 | FETCH_DATA (info, codep + 1); | |
11943 | two_source_ops = (*codep == 0x62) || (*codep == 0xc8); | |
11944 | ||
3e7d61b2 | 11945 | if (((prefixes & PREFIX_FWAIT) |
f16cd0d5 | 11946 | && ((*codep < 0xd8) || (*codep > 0xdf)))) |
252b5132 | 11947 | { |
86a80a50 | 11948 | /* Handle prefixes before fwait. */ |
d9949a36 | 11949 | for (i = 0; i < fwait_prefix && all_prefixes[i]; |
86a80a50 L |
11950 | i++) |
11951 | (*info->fprintf_func) (info->stream, "%s ", | |
11952 | prefix_name (all_prefixes[i], sizeflag)); | |
f16cd0d5 | 11953 | (*info->fprintf_func) (info->stream, "fwait"); |
86a80a50 | 11954 | return i + 1; |
252b5132 RH |
11955 | } |
11956 | ||
252b5132 RH |
11957 | if (*codep == 0x0f) |
11958 | { | |
eec0f4ca | 11959 | unsigned char threebyte; |
5f40e14d JS |
11960 | |
11961 | codep++; | |
11962 | FETCH_DATA (info, codep + 1); | |
11963 | threebyte = *codep; | |
eec0f4ca | 11964 | dp = &dis386_twobyte[threebyte]; |
252b5132 | 11965 | need_modrm = twobyte_has_modrm[*codep]; |
eec0f4ca | 11966 | codep++; |
252b5132 RH |
11967 | } |
11968 | else | |
11969 | { | |
6439fc28 | 11970 | dp = &dis386[*codep]; |
252b5132 | 11971 | need_modrm = onebyte_has_modrm[*codep]; |
eec0f4ca | 11972 | codep++; |
252b5132 | 11973 | } |
246c51aa | 11974 | |
df18fdba L |
11975 | /* Save sizeflag for printing the extra prefixes later before updating |
11976 | it for mnemonic and operand processing. The prefix names depend | |
11977 | only on the address mode. */ | |
11978 | orig_sizeflag = sizeflag; | |
c608c12e | 11979 | if (prefixes & PREFIX_ADDR) |
df18fdba | 11980 | sizeflag ^= AFLAG; |
b844680a | 11981 | if ((prefixes & PREFIX_DATA)) |
df18fdba | 11982 | sizeflag ^= DFLAG; |
3ffd33cf | 11983 | |
285ca992 | 11984 | end_codep = codep; |
8bb15339 | 11985 | if (need_modrm) |
252b5132 RH |
11986 | { |
11987 | FETCH_DATA (info, codep + 1); | |
7967e09e L |
11988 | modrm.mod = (*codep >> 6) & 3; |
11989 | modrm.reg = (*codep >> 3) & 7; | |
11990 | modrm.rm = *codep & 7; | |
252b5132 RH |
11991 | } |
11992 | ||
42d5f9c6 MS |
11993 | need_vex = 0; |
11994 | need_vex_reg = 0; | |
11995 | vex_w_done = 0; | |
caf0678c | 11996 | memset (&vex, 0, sizeof (vex)); |
55b126d4 | 11997 | |
ce518a5f | 11998 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 11999 | { |
55cf16e1 | 12000 | get_sib (info, sizeflag); |
252b5132 RH |
12001 | dofloat (sizeflag); |
12002 | } | |
12003 | else | |
12004 | { | |
8bb15339 | 12005 | dp = get_valid_dis386 (dp, info); |
b844680a | 12006 | if (dp != NULL && putop (dp->name, sizeflag) == 0) |
6c067bbb | 12007 | { |
55cf16e1 | 12008 | get_sib (info, sizeflag); |
ce518a5f L |
12009 | for (i = 0; i < MAX_OPERANDS; ++i) |
12010 | { | |
246c51aa | 12011 | obufp = op_out[i]; |
ce518a5f L |
12012 | op_ad = MAX_OPERANDS - 1 - i; |
12013 | if (dp->op[i].rtn) | |
12014 | (*dp->op[i].rtn) (dp->op[i].bytemode, sizeflag); | |
43234a1e L |
12015 | /* For EVEX instruction after the last operand masking |
12016 | should be printed. */ | |
12017 | if (i == 0 && vex.evex) | |
12018 | { | |
12019 | /* Don't print {%k0}. */ | |
12020 | if (vex.mask_register_specifier) | |
12021 | { | |
12022 | oappend ("{"); | |
12023 | oappend (names_mask[vex.mask_register_specifier]); | |
12024 | oappend ("}"); | |
12025 | } | |
12026 | if (vex.zeroing) | |
12027 | oappend ("{z}"); | |
12028 | } | |
ce518a5f | 12029 | } |
6439fc28 | 12030 | } |
252b5132 RH |
12031 | } |
12032 | ||
1d67fe3b TT |
12033 | /* Clear instruction information. */ |
12034 | if (the_info) | |
12035 | { | |
12036 | the_info->insn_info_valid = 0; | |
12037 | the_info->branch_delay_insns = 0; | |
12038 | the_info->data_size = 0; | |
12039 | the_info->insn_type = dis_noninsn; | |
12040 | the_info->target = 0; | |
12041 | the_info->target2 = 0; | |
12042 | } | |
12043 | ||
12044 | /* Reset jump operation indicator. */ | |
12045 | op_is_jump = FALSE; | |
12046 | ||
12047 | { | |
12048 | int jump_detection = 0; | |
12049 | ||
12050 | /* Extract flags. */ | |
12051 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12052 | { | |
12053 | if ((dp->op[i].rtn == OP_J) | |
12054 | || (dp->op[i].rtn == OP_indirE)) | |
12055 | jump_detection |= 1; | |
12056 | else if ((dp->op[i].rtn == BND_Fixup) | |
12057 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
12058 | jump_detection |= 2; | |
12059 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
12060 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
12061 | jump_detection |= 4; | |
12062 | } | |
12063 | ||
12064 | /* Determine if this is a jump or branch. */ | |
12065 | if ((jump_detection & 0x3) == 0x3) | |
12066 | { | |
12067 | op_is_jump = TRUE; | |
12068 | if (jump_detection & 0x4) | |
12069 | the_info->insn_type = dis_condbranch; | |
12070 | else | |
12071 | the_info->insn_type = | |
12072 | (dp->name && !strncmp(dp->name, "call", 4)) | |
12073 | ? dis_jsr : dis_branch; | |
12074 | } | |
12075 | } | |
12076 | ||
63c6fc6c L |
12077 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
12078 | are all 0s in inverted form. */ | |
12079 | if (need_vex && vex.register_specifier != 0) | |
12080 | { | |
12081 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12082 | return end_codep - priv.the_buffer; | |
12083 | } | |
12084 | ||
d869730d | 12085 | /* Check if the REX prefix is used. */ |
73239888 | 12086 | if ((rex ^ rex_used) == 0 && !need_vex && last_rex_prefix >= 0) |
f16cd0d5 L |
12087 | all_prefixes[last_rex_prefix] = 0; |
12088 | ||
5e6718e4 | 12089 | /* Check if the SEG prefix is used. */ |
f16cd0d5 L |
12090 | if ((prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
12091 | | PREFIX_FS | PREFIX_GS)) != 0 | |
285ca992 | 12092 | && (used_prefixes & active_seg_prefix) != 0) |
f16cd0d5 L |
12093 | all_prefixes[last_seg_prefix] = 0; |
12094 | ||
5e6718e4 | 12095 | /* Check if the ADDR prefix is used. */ |
f16cd0d5 L |
12096 | if ((prefixes & PREFIX_ADDR) != 0 |
12097 | && (used_prefixes & PREFIX_ADDR) != 0) | |
12098 | all_prefixes[last_addr_prefix] = 0; | |
12099 | ||
df18fdba L |
12100 | /* Check if the DATA prefix is used. */ |
12101 | if ((prefixes & PREFIX_DATA) != 0 | |
73239888 JB |
12102 | && (used_prefixes & PREFIX_DATA) != 0 |
12103 | && !need_vex) | |
df18fdba | 12104 | all_prefixes[last_data_prefix] = 0; |
f16cd0d5 | 12105 | |
df18fdba | 12106 | /* Print the extra prefixes. */ |
f16cd0d5 | 12107 | prefix_length = 0; |
f310f33d | 12108 | for (i = 0; i < (int) ARRAY_SIZE (all_prefixes); i++) |
f16cd0d5 L |
12109 | if (all_prefixes[i]) |
12110 | { | |
12111 | const char *name; | |
df18fdba | 12112 | name = prefix_name (all_prefixes[i], orig_sizeflag); |
f16cd0d5 L |
12113 | if (name == NULL) |
12114 | abort (); | |
12115 | prefix_length += strlen (name) + 1; | |
12116 | (*info->fprintf_func) (info->stream, "%s ", name); | |
12117 | } | |
b844680a | 12118 | |
285ca992 L |
12119 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is |
12120 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
12121 | used by putop and MMX/SSE operand and may be overriden by the | |
12122 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
12123 | separately. */ | |
3888916d | 12124 | if (dp->prefix_requirement == PREFIX_OPCODE |
bf926894 JB |
12125 | && (((need_vex |
12126 | ? vex.prefix == REPE_PREFIX_OPCODE | |
12127 | || vex.prefix == REPNE_PREFIX_OPCODE | |
12128 | : (prefixes | |
12129 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) | |
285ca992 L |
12130 | && (used_prefixes |
12131 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) | |
bf926894 JB |
12132 | || (((need_vex |
12133 | ? vex.prefix == DATA_PREFIX_OPCODE | |
12134 | : ((prefixes | |
12135 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) | |
12136 | == PREFIX_DATA)) | |
97e6786a JB |
12137 | && (used_prefixes & PREFIX_DATA) == 0)) |
12138 | || (vex.evex && !vex.w != !(used_prefixes & PREFIX_DATA)))) | |
285ca992 L |
12139 | { |
12140 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12141 | return end_codep - priv.the_buffer; | |
12142 | } | |
12143 | ||
f16cd0d5 L |
12144 | /* Check maximum code length. */ |
12145 | if ((codep - start_codep) > MAX_CODE_LENGTH) | |
12146 | { | |
12147 | (*info->fprintf_func) (info->stream, "(bad)"); | |
12148 | return MAX_CODE_LENGTH; | |
12149 | } | |
b844680a | 12150 | |
ea397f5b | 12151 | obufp = mnemonicendp; |
f16cd0d5 | 12152 | for (i = strlen (obuf) + prefix_length; i < 6; i++) |
252b5132 RH |
12153 | oappend (" "); |
12154 | oappend (" "); | |
12155 | (*info->fprintf_func) (info->stream, "%s", obuf); | |
12156 | ||
12157 | /* The enter and bound instructions are printed with operands in the same | |
12158 | order as the intel book; everything else is printed in reverse order. */ | |
2da11e11 | 12159 | if (intel_syntax || two_source_ops) |
252b5132 | 12160 | { |
185b1163 L |
12161 | bfd_vma riprel; |
12162 | ||
ce518a5f | 12163 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12164 | op_txt[i] = op_out[i]; |
246c51aa | 12165 | |
3a8547d2 JB |
12166 | if (intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
12167 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) | |
12168 | { | |
12169 | op_txt[2] = op_out[3]; | |
12170 | op_txt[3] = op_out[2]; | |
12171 | } | |
12172 | ||
ce518a5f L |
12173 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
12174 | { | |
6c067bbb RM |
12175 | op_ad = op_index[i]; |
12176 | op_index[i] = op_index[MAX_OPERANDS - 1 - i]; | |
12177 | op_index[MAX_OPERANDS - 1 - i] = op_ad; | |
185b1163 L |
12178 | riprel = op_riprel[i]; |
12179 | op_riprel[i] = op_riprel [MAX_OPERANDS - 1 - i]; | |
12180 | op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 12181 | } |
252b5132 RH |
12182 | } |
12183 | else | |
12184 | { | |
ce518a5f | 12185 | for (i = 0; i < MAX_OPERANDS; ++i) |
6c067bbb | 12186 | op_txt[MAX_OPERANDS - 1 - i] = op_out[i]; |
050dfa73 MM |
12187 | } |
12188 | ||
ce518a5f L |
12189 | needcomma = 0; |
12190 | for (i = 0; i < MAX_OPERANDS; ++i) | |
12191 | if (*op_txt[i]) | |
12192 | { | |
12193 | if (needcomma) | |
12194 | (*info->fprintf_func) (info->stream, ","); | |
12195 | if (op_index[i] != -1 && !op_riprel[i]) | |
1d67fe3b TT |
12196 | { |
12197 | bfd_vma target = (bfd_vma) op_address[op_index[i]]; | |
12198 | ||
12199 | if (the_info && op_is_jump) | |
12200 | { | |
12201 | the_info->insn_info_valid = 1; | |
12202 | the_info->branch_delay_insns = 0; | |
12203 | the_info->data_size = 0; | |
12204 | the_info->target = target; | |
12205 | the_info->target2 = 0; | |
12206 | } | |
12207 | (*info->print_address_func) (target, info); | |
12208 | } | |
ce518a5f L |
12209 | else |
12210 | (*info->fprintf_func) (info->stream, "%s", op_txt[i]); | |
12211 | needcomma = 1; | |
12212 | } | |
050dfa73 | 12213 | |
ce518a5f | 12214 | for (i = 0; i < MAX_OPERANDS; i++) |
52b15da3 JH |
12215 | if (op_index[i] != -1 && op_riprel[i]) |
12216 | { | |
12217 | (*info->fprintf_func) (info->stream, " # "); | |
4fd7268a | 12218 | (*info->print_address_func) ((bfd_vma) (start_pc + (codep - start_codep) |
52b15da3 | 12219 | + op_address[op_index[i]]), info); |
185b1163 | 12220 | break; |
52b15da3 | 12221 | } |
e396998b | 12222 | return codep - priv.the_buffer; |
252b5132 RH |
12223 | } |
12224 | ||
6439fc28 | 12225 | static const char *float_mem[] = { |
252b5132 | 12226 | /* d8 */ |
7c52e0e8 L |
12227 | "fadd{s|}", |
12228 | "fmul{s|}", | |
12229 | "fcom{s|}", | |
12230 | "fcomp{s|}", | |
12231 | "fsub{s|}", | |
12232 | "fsubr{s|}", | |
12233 | "fdiv{s|}", | |
12234 | "fdivr{s|}", | |
db6eb5be | 12235 | /* d9 */ |
7c52e0e8 | 12236 | "fld{s|}", |
252b5132 | 12237 | "(bad)", |
7c52e0e8 L |
12238 | "fst{s|}", |
12239 | "fstp{s|}", | |
d1c36125 | 12240 | "fldenv{C|C}", |
252b5132 | 12241 | "fldcw", |
d1c36125 | 12242 | "fNstenv{C|C}", |
252b5132 RH |
12243 | "fNstcw", |
12244 | /* da */ | |
7c52e0e8 L |
12245 | "fiadd{l|}", |
12246 | "fimul{l|}", | |
12247 | "ficom{l|}", | |
12248 | "ficomp{l|}", | |
12249 | "fisub{l|}", | |
12250 | "fisubr{l|}", | |
12251 | "fidiv{l|}", | |
12252 | "fidivr{l|}", | |
252b5132 | 12253 | /* db */ |
7c52e0e8 L |
12254 | "fild{l|}", |
12255 | "fisttp{l|}", | |
12256 | "fist{l|}", | |
12257 | "fistp{l|}", | |
252b5132 | 12258 | "(bad)", |
464dc4af | 12259 | "fld{t|}", |
252b5132 | 12260 | "(bad)", |
464dc4af | 12261 | "fstp{t|}", |
252b5132 | 12262 | /* dc */ |
7c52e0e8 L |
12263 | "fadd{l|}", |
12264 | "fmul{l|}", | |
12265 | "fcom{l|}", | |
12266 | "fcomp{l|}", | |
12267 | "fsub{l|}", | |
12268 | "fsubr{l|}", | |
12269 | "fdiv{l|}", | |
12270 | "fdivr{l|}", | |
252b5132 | 12271 | /* dd */ |
7c52e0e8 L |
12272 | "fld{l|}", |
12273 | "fisttp{ll|}", | |
12274 | "fst{l||}", | |
12275 | "fstp{l|}", | |
d1c36125 | 12276 | "frstor{C|C}", |
252b5132 | 12277 | "(bad)", |
d1c36125 | 12278 | "fNsave{C|C}", |
252b5132 RH |
12279 | "fNstsw", |
12280 | /* de */ | |
ac465521 JB |
12281 | "fiadd{s|}", |
12282 | "fimul{s|}", | |
12283 | "ficom{s|}", | |
12284 | "ficomp{s|}", | |
12285 | "fisub{s|}", | |
12286 | "fisubr{s|}", | |
12287 | "fidiv{s|}", | |
12288 | "fidivr{s|}", | |
252b5132 | 12289 | /* df */ |
ac465521 JB |
12290 | "fild{s|}", |
12291 | "fisttp{s|}", | |
12292 | "fist{s|}", | |
12293 | "fistp{s|}", | |
252b5132 | 12294 | "fbld", |
7c52e0e8 | 12295 | "fild{ll|}", |
252b5132 | 12296 | "fbstp", |
7c52e0e8 | 12297 | "fistp{ll|}", |
1d9f512f AM |
12298 | }; |
12299 | ||
12300 | static const unsigned char float_mem_mode[] = { | |
12301 | /* d8 */ | |
12302 | d_mode, | |
12303 | d_mode, | |
12304 | d_mode, | |
12305 | d_mode, | |
12306 | d_mode, | |
12307 | d_mode, | |
12308 | d_mode, | |
12309 | d_mode, | |
12310 | /* d9 */ | |
12311 | d_mode, | |
12312 | 0, | |
12313 | d_mode, | |
12314 | d_mode, | |
12315 | 0, | |
12316 | w_mode, | |
12317 | 0, | |
12318 | w_mode, | |
12319 | /* da */ | |
12320 | d_mode, | |
12321 | d_mode, | |
12322 | d_mode, | |
12323 | d_mode, | |
12324 | d_mode, | |
12325 | d_mode, | |
12326 | d_mode, | |
12327 | d_mode, | |
12328 | /* db */ | |
12329 | d_mode, | |
12330 | d_mode, | |
12331 | d_mode, | |
12332 | d_mode, | |
12333 | 0, | |
9306ca4a | 12334 | t_mode, |
1d9f512f | 12335 | 0, |
9306ca4a | 12336 | t_mode, |
1d9f512f AM |
12337 | /* dc */ |
12338 | q_mode, | |
12339 | q_mode, | |
12340 | q_mode, | |
12341 | q_mode, | |
12342 | q_mode, | |
12343 | q_mode, | |
12344 | q_mode, | |
12345 | q_mode, | |
12346 | /* dd */ | |
12347 | q_mode, | |
12348 | q_mode, | |
12349 | q_mode, | |
12350 | q_mode, | |
12351 | 0, | |
12352 | 0, | |
12353 | 0, | |
12354 | w_mode, | |
12355 | /* de */ | |
12356 | w_mode, | |
12357 | w_mode, | |
12358 | w_mode, | |
12359 | w_mode, | |
12360 | w_mode, | |
12361 | w_mode, | |
12362 | w_mode, | |
12363 | w_mode, | |
12364 | /* df */ | |
12365 | w_mode, | |
12366 | w_mode, | |
12367 | w_mode, | |
12368 | w_mode, | |
9306ca4a | 12369 | t_mode, |
1d9f512f | 12370 | q_mode, |
9306ca4a | 12371 | t_mode, |
1d9f512f | 12372 | q_mode |
252b5132 RH |
12373 | }; |
12374 | ||
ce518a5f L |
12375 | #define ST { OP_ST, 0 } |
12376 | #define STi { OP_STi, 0 } | |
252b5132 | 12377 | |
48c97fa1 L |
12378 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
12379 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
12380 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
12381 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
12382 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
12383 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
12384 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
12385 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
12386 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 12387 | |
2da11e11 | 12388 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
12389 | /* d8 */ |
12390 | { | |
bf890a93 IT |
12391 | { "fadd", { ST, STi }, 0 }, |
12392 | { "fmul", { ST, STi }, 0 }, | |
12393 | { "fcom", { STi }, 0 }, | |
12394 | { "fcomp", { STi }, 0 }, | |
12395 | { "fsub", { ST, STi }, 0 }, | |
12396 | { "fsubr", { ST, STi }, 0 }, | |
12397 | { "fdiv", { ST, STi }, 0 }, | |
12398 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
12399 | }, |
12400 | /* d9 */ | |
12401 | { | |
bf890a93 IT |
12402 | { "fld", { STi }, 0 }, |
12403 | { "fxch", { STi }, 0 }, | |
252b5132 | 12404 | { FGRPd9_2 }, |
592d1631 | 12405 | { Bad_Opcode }, |
252b5132 RH |
12406 | { FGRPd9_4 }, |
12407 | { FGRPd9_5 }, | |
12408 | { FGRPd9_6 }, | |
12409 | { FGRPd9_7 }, | |
12410 | }, | |
12411 | /* da */ | |
12412 | { | |
bf890a93 IT |
12413 | { "fcmovb", { ST, STi }, 0 }, |
12414 | { "fcmove", { ST, STi }, 0 }, | |
12415 | { "fcmovbe",{ ST, STi }, 0 }, | |
12416 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 12417 | { Bad_Opcode }, |
252b5132 | 12418 | { FGRPda_5 }, |
592d1631 L |
12419 | { Bad_Opcode }, |
12420 | { Bad_Opcode }, | |
252b5132 RH |
12421 | }, |
12422 | /* db */ | |
12423 | { | |
bf890a93 IT |
12424 | { "fcmovnb",{ ST, STi }, 0 }, |
12425 | { "fcmovne",{ ST, STi }, 0 }, | |
12426 | { "fcmovnbe",{ ST, STi }, 0 }, | |
12427 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 12428 | { FGRPdb_4 }, |
bf890a93 IT |
12429 | { "fucomi", { ST, STi }, 0 }, |
12430 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 12431 | { Bad_Opcode }, |
252b5132 RH |
12432 | }, |
12433 | /* dc */ | |
12434 | { | |
bf890a93 IT |
12435 | { "fadd", { STi, ST }, 0 }, |
12436 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
12437 | { Bad_Opcode }, |
12438 | { Bad_Opcode }, | |
d53e6b98 JB |
12439 | { "fsub{!M|r}", { STi, ST }, 0 }, |
12440 | { "fsub{M|}", { STi, ST }, 0 }, | |
12441 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
12442 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
12443 | }, |
12444 | /* dd */ | |
12445 | { | |
bf890a93 | 12446 | { "ffree", { STi }, 0 }, |
592d1631 | 12447 | { Bad_Opcode }, |
bf890a93 IT |
12448 | { "fst", { STi }, 0 }, |
12449 | { "fstp", { STi }, 0 }, | |
12450 | { "fucom", { STi }, 0 }, | |
12451 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
12452 | { Bad_Opcode }, |
12453 | { Bad_Opcode }, | |
252b5132 RH |
12454 | }, |
12455 | /* de */ | |
12456 | { | |
bf890a93 IT |
12457 | { "faddp", { STi, ST }, 0 }, |
12458 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 12459 | { Bad_Opcode }, |
252b5132 | 12460 | { FGRPde_3 }, |
d53e6b98 JB |
12461 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
12462 | { "fsub{M|}p", { STi, ST }, 0 }, | |
12463 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
12464 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
12465 | }, |
12466 | /* df */ | |
12467 | { | |
bf890a93 | 12468 | { "ffreep", { STi }, 0 }, |
592d1631 L |
12469 | { Bad_Opcode }, |
12470 | { Bad_Opcode }, | |
12471 | { Bad_Opcode }, | |
252b5132 | 12472 | { FGRPdf_4 }, |
bf890a93 IT |
12473 | { "fucomip", { ST, STi }, 0 }, |
12474 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 12475 | { Bad_Opcode }, |
252b5132 RH |
12476 | }, |
12477 | }; | |
12478 | ||
252b5132 | 12479 | static char *fgrps[][8] = { |
48c97fa1 L |
12480 | /* Bad opcode 0 */ |
12481 | { | |
12482 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12483 | }, | |
12484 | ||
12485 | /* d9_2 1 */ | |
252b5132 RH |
12486 | { |
12487 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12488 | }, | |
12489 | ||
48c97fa1 | 12490 | /* d9_4 2 */ |
252b5132 RH |
12491 | { |
12492 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
12493 | }, | |
12494 | ||
48c97fa1 | 12495 | /* d9_5 3 */ |
252b5132 RH |
12496 | { |
12497 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
12498 | }, | |
12499 | ||
48c97fa1 | 12500 | /* d9_6 4 */ |
252b5132 RH |
12501 | { |
12502 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
12503 | }, | |
12504 | ||
48c97fa1 | 12505 | /* d9_7 5 */ |
252b5132 RH |
12506 | { |
12507 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
12508 | }, | |
12509 | ||
48c97fa1 | 12510 | /* da_5 6 */ |
252b5132 RH |
12511 | { |
12512 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12513 | }, | |
12514 | ||
48c97fa1 | 12515 | /* db_4 7 */ |
252b5132 | 12516 | { |
309d3373 JB |
12517 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
12518 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
12519 | }, |
12520 | ||
48c97fa1 | 12521 | /* de_3 8 */ |
252b5132 RH |
12522 | { |
12523 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12524 | }, | |
12525 | ||
48c97fa1 | 12526 | /* df_4 9 */ |
252b5132 RH |
12527 | { |
12528 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
12529 | }, | |
12530 | }; | |
12531 | ||
b6169b20 L |
12532 | static void |
12533 | swap_operand (void) | |
12534 | { | |
12535 | mnemonicendp[0] = '.'; | |
12536 | mnemonicendp[1] = 's'; | |
12537 | mnemonicendp += 2; | |
12538 | } | |
12539 | ||
b844680a L |
12540 | static void |
12541 | OP_Skip_MODRM (int bytemode ATTRIBUTE_UNUSED, | |
12542 | int sizeflag ATTRIBUTE_UNUSED) | |
12543 | { | |
12544 | /* Skip mod/rm byte. */ | |
12545 | MODRM_CHECK; | |
12546 | codep++; | |
12547 | } | |
12548 | ||
252b5132 | 12549 | static void |
26ca5450 | 12550 | dofloat (int sizeflag) |
252b5132 | 12551 | { |
2da11e11 | 12552 | const struct dis386 *dp; |
252b5132 RH |
12553 | unsigned char floatop; |
12554 | ||
12555 | floatop = codep[-1]; | |
12556 | ||
7967e09e | 12557 | if (modrm.mod != 3) |
252b5132 | 12558 | { |
7967e09e | 12559 | int fp_indx = (floatop - 0xd8) * 8 + modrm.reg; |
1d9f512f AM |
12560 | |
12561 | putop (float_mem[fp_indx], sizeflag); | |
ce518a5f | 12562 | obufp = op_out[0]; |
6e50d963 | 12563 | op_ad = 2; |
1d9f512f | 12564 | OP_E (float_mem_mode[fp_indx], sizeflag); |
252b5132 RH |
12565 | return; |
12566 | } | |
6608db57 | 12567 | /* Skip mod/rm byte. */ |
4bba6815 | 12568 | MODRM_CHECK; |
252b5132 RH |
12569 | codep++; |
12570 | ||
7967e09e | 12571 | dp = &float_reg[floatop - 0xd8][modrm.reg]; |
252b5132 RH |
12572 | if (dp->name == NULL) |
12573 | { | |
7967e09e | 12574 | putop (fgrps[dp->op[0].bytemode][modrm.rm], sizeflag); |
252b5132 | 12575 | |
6608db57 | 12576 | /* Instruction fnstsw is only one with strange arg. */ |
252b5132 | 12577 | if (floatop == 0xdf && codep[-1] == 0xe0) |
ce518a5f | 12578 | strcpy (op_out[0], names16[0]); |
252b5132 RH |
12579 | } |
12580 | else | |
12581 | { | |
12582 | putop (dp->name, sizeflag); | |
12583 | ||
ce518a5f | 12584 | obufp = op_out[0]; |
6e50d963 | 12585 | op_ad = 2; |
ce518a5f L |
12586 | if (dp->op[0].rtn) |
12587 | (*dp->op[0].rtn) (dp->op[0].bytemode, sizeflag); | |
6e50d963 | 12588 | |
ce518a5f | 12589 | obufp = op_out[1]; |
6e50d963 | 12590 | op_ad = 1; |
ce518a5f L |
12591 | if (dp->op[1].rtn) |
12592 | (*dp->op[1].rtn) (dp->op[1].bytemode, sizeflag); | |
252b5132 RH |
12593 | } |
12594 | } | |
12595 | ||
9ce09ba2 RM |
12596 | /* Like oappend (below), but S is a string starting with '%'. |
12597 | In Intel syntax, the '%' is elided. */ | |
12598 | static void | |
12599 | oappend_maybe_intel (const char *s) | |
12600 | { | |
12601 | oappend (s + intel_syntax); | |
12602 | } | |
12603 | ||
252b5132 | 12604 | static void |
26ca5450 | 12605 | OP_ST (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12606 | { |
9ce09ba2 | 12607 | oappend_maybe_intel ("%st"); |
252b5132 RH |
12608 | } |
12609 | ||
252b5132 | 12610 | static void |
26ca5450 | 12611 | OP_STi (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 12612 | { |
7967e09e | 12613 | sprintf (scratchbuf, "%%st(%d)", modrm.rm); |
9ce09ba2 | 12614 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
12615 | } |
12616 | ||
6608db57 | 12617 | /* Capital letters in template are macros. */ |
6439fc28 | 12618 | static int |
d3ce72d0 | 12619 | putop (const char *in_template, int sizeflag) |
252b5132 | 12620 | { |
2da11e11 | 12621 | const char *p; |
9306ca4a | 12622 | int alt = 0; |
9d141669 | 12623 | int cond = 1; |
21a3faeb | 12624 | unsigned int l = 0, len = 0; |
98b528ac L |
12625 | char last[4]; |
12626 | ||
d3ce72d0 | 12627 | for (p = in_template; *p; p++) |
252b5132 | 12628 | { |
21a3faeb JB |
12629 | if (len > l) |
12630 | { | |
12631 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
12632 | abort (); | |
12633 | last[l++] = *p; | |
12634 | continue; | |
12635 | } | |
252b5132 RH |
12636 | switch (*p) |
12637 | { | |
12638 | default: | |
12639 | *obufp++ = *p; | |
12640 | break; | |
98b528ac L |
12641 | case '%': |
12642 | len++; | |
12643 | break; | |
9d141669 L |
12644 | case '!': |
12645 | cond = 0; | |
12646 | break; | |
6439fc28 | 12647 | case '{': |
6439fc28 | 12648 | if (intel_syntax) |
6439fc28 AM |
12649 | { |
12650 | while (*++p != '|') | |
7c52e0e8 L |
12651 | if (*p == '}' || *p == '\0') |
12652 | abort (); | |
d1c36125 | 12653 | alt = 1; |
6439fc28 | 12654 | } |
d1c36125 | 12655 | break; |
6439fc28 AM |
12656 | case '|': |
12657 | while (*++p != '}') | |
12658 | { | |
12659 | if (*p == '\0') | |
12660 | abort (); | |
12661 | } | |
12662 | break; | |
12663 | case '}': | |
d1c36125 | 12664 | alt = 0; |
6439fc28 | 12665 | break; |
252b5132 | 12666 | case 'A': |
db6eb5be AM |
12667 | if (intel_syntax) |
12668 | break; | |
7967e09e | 12669 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
252b5132 RH |
12670 | *obufp++ = 'b'; |
12671 | break; | |
12672 | case 'B': | |
21a3faeb | 12673 | if (l == 0) |
4b06377f | 12674 | { |
dc1e8a47 | 12675 | case_B: |
4b06377f L |
12676 | if (intel_syntax) |
12677 | break; | |
12678 | if (sizeflag & SUFFIX_ALWAYS) | |
12679 | *obufp++ = 'b'; | |
12680 | } | |
21a3faeb | 12681 | else if (l == 1 && last[0] == 'L') |
4b06377f | 12682 | { |
4b06377f L |
12683 | if (address_mode == mode_64bit |
12684 | && !(prefixes & PREFIX_ADDR)) | |
12685 | { | |
12686 | *obufp++ = 'a'; | |
12687 | *obufp++ = 'b'; | |
12688 | *obufp++ = 's'; | |
12689 | } | |
12690 | ||
12691 | goto case_B; | |
12692 | } | |
21a3faeb JB |
12693 | else |
12694 | abort (); | |
252b5132 | 12695 | break; |
9306ca4a JB |
12696 | case 'C': |
12697 | if (intel_syntax && !alt) | |
12698 | break; | |
12699 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) | |
12700 | { | |
12701 | if (sizeflag & DFLAG) | |
12702 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12703 | else | |
12704 | *obufp++ = intel_syntax ? 'w' : 's'; | |
12705 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12706 | } | |
12707 | break; | |
ed7841b3 JB |
12708 | case 'D': |
12709 | if (intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) | |
12710 | break; | |
161a04f6 | 12711 | USED_REX (REX_W); |
7967e09e | 12712 | if (modrm.mod == 3) |
ed7841b3 | 12713 | { |
161a04f6 | 12714 | if (rex & REX_W) |
ed7841b3 | 12715 | *obufp++ = 'q'; |
ed7841b3 | 12716 | else |
f16cd0d5 L |
12717 | { |
12718 | if (sizeflag & DFLAG) | |
12719 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12720 | else | |
12721 | *obufp++ = 'w'; | |
12722 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12723 | } | |
ed7841b3 JB |
12724 | } |
12725 | else | |
12726 | *obufp++ = 'w'; | |
12727 | break; | |
252b5132 | 12728 | case 'E': /* For jcxz/jecxz */ |
cb712a9e | 12729 | if (address_mode == mode_64bit) |
c1a64871 JH |
12730 | { |
12731 | if (sizeflag & AFLAG) | |
12732 | *obufp++ = 'r'; | |
12733 | else | |
12734 | *obufp++ = 'e'; | |
12735 | } | |
12736 | else | |
12737 | if (sizeflag & AFLAG) | |
12738 | *obufp++ = 'e'; | |
3ffd33cf AM |
12739 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12740 | break; | |
12741 | case 'F': | |
db6eb5be AM |
12742 | if (intel_syntax) |
12743 | break; | |
e396998b | 12744 | if ((prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
12745 | { |
12746 | if (sizeflag & AFLAG) | |
cb712a9e | 12747 | *obufp++ = address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 12748 | else |
cb712a9e | 12749 | *obufp++ = address_mode == mode_64bit ? 'l' : 'w'; |
3ffd33cf AM |
12750 | used_prefixes |= (prefixes & PREFIX_ADDR); |
12751 | } | |
252b5132 | 12752 | break; |
52fd6d94 JB |
12753 | case 'G': |
12754 | if (intel_syntax || (obufp[-1] != 's' && !(sizeflag & SUFFIX_ALWAYS))) | |
12755 | break; | |
161a04f6 | 12756 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
12757 | *obufp++ = 'l'; |
12758 | else | |
12759 | *obufp++ = 'w'; | |
161a04f6 | 12760 | if (!(rex & REX_W)) |
52fd6d94 JB |
12761 | used_prefixes |= (prefixes & PREFIX_DATA); |
12762 | break; | |
5dd0794d | 12763 | case 'H': |
db6eb5be AM |
12764 | if (intel_syntax) |
12765 | break; | |
5dd0794d AM |
12766 | if ((prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
12767 | || (prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
12768 | { | |
12769 | used_prefixes |= prefixes & (PREFIX_CS | PREFIX_DS); | |
12770 | *obufp++ = ','; | |
12771 | *obufp++ = 'p'; | |
12772 | if (prefixes & PREFIX_DS) | |
12773 | *obufp++ = 't'; | |
12774 | else | |
12775 | *obufp++ = 'n'; | |
12776 | } | |
12777 | break; | |
42903f7f L |
12778 | case 'K': |
12779 | USED_REX (REX_W); | |
12780 | if (rex & REX_W) | |
12781 | *obufp++ = 'q'; | |
12782 | else | |
12783 | *obufp++ = 'd'; | |
12784 | break; | |
6dd5059a | 12785 | case 'Z': |
21a3faeb | 12786 | if (l != 0) |
04d824a4 | 12787 | { |
21a3faeb JB |
12788 | if (l != 1 || last[0] != 'X') |
12789 | abort (); | |
04d824a4 JB |
12790 | if (!need_vex || !vex.evex) |
12791 | abort (); | |
12792 | if (intel_syntax | |
12793 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) | |
12794 | break; | |
12795 | switch (vex.length) | |
12796 | { | |
12797 | case 128: | |
12798 | *obufp++ = 'x'; | |
12799 | break; | |
12800 | case 256: | |
12801 | *obufp++ = 'y'; | |
12802 | break; | |
12803 | case 512: | |
12804 | *obufp++ = 'z'; | |
12805 | break; | |
12806 | default: | |
12807 | abort (); | |
12808 | } | |
12809 | break; | |
12810 | } | |
6dd5059a L |
12811 | if (intel_syntax) |
12812 | break; | |
12813 | if (address_mode == mode_64bit && (sizeflag & SUFFIX_ALWAYS)) | |
12814 | { | |
12815 | *obufp++ = 'q'; | |
12816 | break; | |
12817 | } | |
12818 | /* Fall through. */ | |
98b528ac | 12819 | goto case_L; |
252b5132 | 12820 | case 'L': |
21a3faeb JB |
12821 | if (l != 0) |
12822 | abort (); | |
dc1e8a47 | 12823 | case_L: |
db6eb5be AM |
12824 | if (intel_syntax) |
12825 | break; | |
252b5132 RH |
12826 | if (sizeflag & SUFFIX_ALWAYS) |
12827 | *obufp++ = 'l'; | |
252b5132 | 12828 | break; |
9d141669 L |
12829 | case 'M': |
12830 | if (intel_mnemonic != cond) | |
12831 | *obufp++ = 'r'; | |
12832 | break; | |
252b5132 RH |
12833 | case 'N': |
12834 | if ((prefixes & PREFIX_FWAIT) == 0) | |
12835 | *obufp++ = 'n'; | |
7d421014 ILT |
12836 | else |
12837 | used_prefixes |= PREFIX_FWAIT; | |
252b5132 | 12838 | break; |
52b15da3 | 12839 | case 'O': |
161a04f6 L |
12840 | USED_REX (REX_W); |
12841 | if (rex & REX_W) | |
6439fc28 | 12842 | *obufp++ = 'o'; |
a35ca55a JB |
12843 | else if (intel_syntax && (sizeflag & DFLAG)) |
12844 | *obufp++ = 'q'; | |
52b15da3 JH |
12845 | else |
12846 | *obufp++ = 'd'; | |
161a04f6 | 12847 | if (!(rex & REX_W)) |
a35ca55a | 12848 | used_prefixes |= (prefixes & PREFIX_DATA); |
52b15da3 | 12849 | break; |
07f5af7d L |
12850 | case '&': |
12851 | if (!intel_syntax | |
12852 | && address_mode == mode_64bit | |
12853 | && isa64 == intel64) | |
12854 | { | |
12855 | *obufp++ = 'q'; | |
12856 | break; | |
12857 | } | |
12858 | /* Fall through. */ | |
6439fc28 | 12859 | case 'T': |
d9e3625e L |
12860 | if (!intel_syntax |
12861 | && address_mode == mode_64bit | |
7bb15c6f | 12862 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
12863 | { |
12864 | *obufp++ = 'q'; | |
12865 | break; | |
12866 | } | |
6608db57 | 12867 | /* Fall through. */ |
4b4c407a | 12868 | goto case_P; |
252b5132 | 12869 | case 'P': |
21a3faeb | 12870 | if (l == 0) |
d9e3625e | 12871 | { |
dc1e8a47 | 12872 | case_P: |
4b4c407a | 12873 | if (intel_syntax) |
d9e3625e | 12874 | { |
4b4c407a L |
12875 | if ((rex & REX_W) == 0 |
12876 | && (prefixes & PREFIX_DATA)) | |
12877 | { | |
12878 | if ((sizeflag & DFLAG) == 0) | |
12879 | *obufp++ = 'w'; | |
12880 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12881 | } | |
12882 | break; | |
12883 | } | |
12884 | if ((prefixes & PREFIX_DATA) | |
12885 | || (rex & REX_W) | |
12886 | || (sizeflag & SUFFIX_ALWAYS)) | |
12887 | { | |
12888 | USED_REX (REX_W); | |
12889 | if (rex & REX_W) | |
12890 | *obufp++ = 'q'; | |
12891 | else | |
12892 | { | |
12893 | if (sizeflag & DFLAG) | |
12894 | *obufp++ = 'l'; | |
12895 | else | |
12896 | *obufp++ = 'w'; | |
12897 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12898 | } | |
d9e3625e | 12899 | } |
d9e3625e | 12900 | } |
21a3faeb | 12901 | else if (l == 1 && last[0] == 'L') |
252b5132 | 12902 | { |
4b4c407a L |
12903 | if ((prefixes & PREFIX_DATA) |
12904 | || (rex & REX_W) | |
12905 | || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12906 | { |
4b4c407a L |
12907 | USED_REX (REX_W); |
12908 | if (rex & REX_W) | |
12909 | *obufp++ = 'q'; | |
12910 | else | |
12911 | { | |
12912 | if (sizeflag & DFLAG) | |
12913 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12914 | else | |
12915 | *obufp++ = 'w'; | |
12916 | used_prefixes |= (prefixes & PREFIX_DATA); | |
12917 | } | |
52b15da3 | 12918 | } |
252b5132 | 12919 | } |
21a3faeb JB |
12920 | else |
12921 | abort (); | |
252b5132 | 12922 | break; |
6439fc28 | 12923 | case 'U': |
db6eb5be AM |
12924 | if (intel_syntax) |
12925 | break; | |
7bb15c6f | 12926 | if (address_mode == mode_64bit |
6c067bbb | 12927 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 | 12928 | { |
7967e09e | 12929 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) |
1a114b12 | 12930 | *obufp++ = 'q'; |
6439fc28 AM |
12931 | break; |
12932 | } | |
6608db57 | 12933 | /* Fall through. */ |
98b528ac | 12934 | goto case_Q; |
252b5132 | 12935 | case 'Q': |
21a3faeb | 12936 | if (l == 0) |
252b5132 | 12937 | { |
dc1e8a47 | 12938 | case_Q: |
98b528ac L |
12939 | if (intel_syntax && !alt) |
12940 | break; | |
12941 | USED_REX (REX_W); | |
12942 | if (modrm.mod != 3 || (sizeflag & SUFFIX_ALWAYS)) | |
52b15da3 | 12943 | { |
98b528ac L |
12944 | if (rex & REX_W) |
12945 | *obufp++ = 'q'; | |
52b15da3 | 12946 | else |
98b528ac L |
12947 | { |
12948 | if (sizeflag & DFLAG) | |
12949 | *obufp++ = intel_syntax ? 'd' : 'l'; | |
12950 | else | |
12951 | *obufp++ = 'w'; | |
f16cd0d5 | 12952 | used_prefixes |= (prefixes & PREFIX_DATA); |
98b528ac | 12953 | } |
52b15da3 | 12954 | } |
98b528ac | 12955 | } |
21a3faeb | 12956 | else if (l == 1 && last[0] == 'L') |
98b528ac | 12957 | { |
589958d6 | 12958 | if ((intel_syntax && need_modrm) |
98b528ac L |
12959 | || (modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS))) |
12960 | break; | |
12961 | if ((rex & REX_W)) | |
12962 | { | |
12963 | USED_REX (REX_W); | |
12964 | *obufp++ = 'q'; | |
12965 | } | |
589958d6 JB |
12966 | else if((address_mode == mode_64bit && need_modrm) |
12967 | || (sizeflag & SUFFIX_ALWAYS)) | |
12968 | *obufp++ = intel_syntax? 'd' : 'l'; | |
252b5132 | 12969 | } |
21a3faeb JB |
12970 | else |
12971 | abort (); | |
252b5132 RH |
12972 | break; |
12973 | case 'R': | |
161a04f6 L |
12974 | USED_REX (REX_W); |
12975 | if (rex & REX_W) | |
a35ca55a JB |
12976 | *obufp++ = 'q'; |
12977 | else if (sizeflag & DFLAG) | |
c608c12e | 12978 | { |
a35ca55a | 12979 | if (intel_syntax) |
c608c12e | 12980 | *obufp++ = 'd'; |
c608c12e | 12981 | else |
a35ca55a | 12982 | *obufp++ = 'l'; |
c608c12e | 12983 | } |
252b5132 | 12984 | else |
a35ca55a JB |
12985 | *obufp++ = 'w'; |
12986 | if (intel_syntax && !p[1] | |
161a04f6 | 12987 | && ((rex & REX_W) || (sizeflag & DFLAG))) |
a35ca55a | 12988 | *obufp++ = 'e'; |
161a04f6 | 12989 | if (!(rex & REX_W)) |
52b15da3 | 12990 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 | 12991 | break; |
1a114b12 | 12992 | case 'V': |
21a3faeb | 12993 | if (l == 0) |
1a114b12 | 12994 | { |
4b06377f L |
12995 | if (intel_syntax) |
12996 | break; | |
7bb15c6f | 12997 | if (address_mode == mode_64bit |
6c067bbb | 12998 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
4b06377f L |
12999 | { |
13000 | if (sizeflag & SUFFIX_ALWAYS) | |
13001 | *obufp++ = 'q'; | |
13002 | break; | |
13003 | } | |
13004 | } | |
21a3faeb | 13005 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13006 | { |
4b06377f L |
13007 | if (rex & REX_W) |
13008 | { | |
13009 | *obufp++ = 'a'; | |
13010 | *obufp++ = 'b'; | |
13011 | *obufp++ = 's'; | |
13012 | } | |
1a114b12 | 13013 | } |
21a3faeb JB |
13014 | else |
13015 | abort (); | |
1a114b12 | 13016 | /* Fall through. */ |
4b06377f | 13017 | goto case_S; |
252b5132 | 13018 | case 'S': |
21a3faeb | 13019 | if (l == 0) |
252b5132 | 13020 | { |
dc1e8a47 | 13021 | case_S: |
4b06377f L |
13022 | if (intel_syntax) |
13023 | break; | |
13024 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 13025 | { |
4b06377f L |
13026 | if (rex & REX_W) |
13027 | *obufp++ = 'q'; | |
52b15da3 | 13028 | else |
4b06377f L |
13029 | { |
13030 | if (sizeflag & DFLAG) | |
13031 | *obufp++ = 'l'; | |
13032 | else | |
13033 | *obufp++ = 'w'; | |
13034 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13035 | } | |
13036 | } | |
13037 | } | |
21a3faeb | 13038 | else if (l == 1 && last[0] == 'L') |
4b06377f | 13039 | { |
4b06377f L |
13040 | if (address_mode == mode_64bit |
13041 | && !(prefixes & PREFIX_ADDR)) | |
13042 | { | |
13043 | *obufp++ = 'a'; | |
13044 | *obufp++ = 'b'; | |
13045 | *obufp++ = 's'; | |
13046 | } | |
13047 | ||
13048 | goto case_S; | |
252b5132 | 13049 | } |
21a3faeb JB |
13050 | else |
13051 | abort (); | |
252b5132 | 13052 | break; |
041bd2e0 | 13053 | case 'X': |
21a3faeb JB |
13054 | if (l != 0) |
13055 | abort (); | |
bf926894 JB |
13056 | if (need_vex |
13057 | ? vex.prefix == DATA_PREFIX_OPCODE | |
13058 | : prefixes & PREFIX_DATA) | |
c0f3af97 | 13059 | { |
bf926894 JB |
13060 | *obufp++ = 'd'; |
13061 | used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 13062 | } |
041bd2e0 | 13063 | else |
bf926894 | 13064 | *obufp++ = 's'; |
041bd2e0 | 13065 | break; |
76f227a5 | 13066 | case 'Y': |
21a3faeb | 13067 | if (l == 1 && last[0] == 'X') |
c0f3af97 | 13068 | { |
c0f3af97 L |
13069 | if (!need_vex) |
13070 | abort (); | |
13071 | if (intel_syntax | |
04d824a4 | 13072 | || ((modrm.mod == 3 || vex.b) && !(sizeflag & SUFFIX_ALWAYS))) |
c0f3af97 L |
13073 | break; |
13074 | switch (vex.length) | |
13075 | { | |
13076 | case 128: | |
13077 | *obufp++ = 'x'; | |
13078 | break; | |
13079 | case 256: | |
13080 | *obufp++ = 'y'; | |
13081 | break; | |
04d824a4 JB |
13082 | case 512: |
13083 | if (!vex.evex) | |
c0f3af97 | 13084 | default: |
04d824a4 | 13085 | abort (); |
c0f3af97 | 13086 | } |
76f227a5 | 13087 | } |
21a3faeb JB |
13088 | else |
13089 | abort (); | |
76f227a5 | 13090 | break; |
252b5132 | 13091 | case 'W': |
21a3faeb | 13092 | if (l == 0) |
a35ca55a | 13093 | { |
0bfee649 L |
13094 | /* operand size flag for cwtl, cbtw */ |
13095 | USED_REX (REX_W); | |
13096 | if (rex & REX_W) | |
13097 | { | |
13098 | if (intel_syntax) | |
13099 | *obufp++ = 'd'; | |
13100 | else | |
13101 | *obufp++ = 'l'; | |
13102 | } | |
13103 | else if (sizeflag & DFLAG) | |
13104 | *obufp++ = 'w'; | |
a35ca55a | 13105 | else |
0bfee649 L |
13106 | *obufp++ = 'b'; |
13107 | if (!(rex & REX_W)) | |
13108 | used_prefixes |= (prefixes & PREFIX_DATA); | |
a35ca55a | 13109 | } |
21a3faeb | 13110 | else if (l == 1) |
0bfee649 | 13111 | { |
0bfee649 L |
13112 | if (!need_vex) |
13113 | abort (); | |
6c30d220 L |
13114 | if (last[0] == 'X') |
13115 | *obufp++ = vex.w ? 'd': 's'; | |
21a3faeb | 13116 | else if (last[0] == 'L') |
6c30d220 | 13117 | *obufp++ = vex.w ? 'q': 'd'; |
931452b6 JB |
13118 | else if (last[0] == 'B') |
13119 | *obufp++ = vex.w ? 'w': 'b'; | |
21a3faeb JB |
13120 | else |
13121 | abort (); | |
0bfee649 | 13122 | } |
21a3faeb JB |
13123 | else |
13124 | abort (); | |
252b5132 | 13125 | break; |
a72d2af2 L |
13126 | case '^': |
13127 | if (intel_syntax) | |
13128 | break; | |
5990e377 JB |
13129 | if (isa64 == intel64 && (rex & REX_W)) |
13130 | { | |
13131 | USED_REX (REX_W); | |
13132 | *obufp++ = 'q'; | |
13133 | break; | |
13134 | } | |
a72d2af2 L |
13135 | if ((prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
13136 | { | |
13137 | if (sizeflag & DFLAG) | |
13138 | *obufp++ = 'l'; | |
13139 | else | |
13140 | *obufp++ = 'w'; | |
13141 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13142 | } | |
13143 | break; | |
5db04b09 L |
13144 | case '@': |
13145 | if (intel_syntax) | |
13146 | break; | |
13147 | if (address_mode == mode_64bit | |
13148 | && (isa64 == intel64 | |
13149 | || ((sizeflag & DFLAG) || (rex & REX_W)))) | |
13150 | *obufp++ = 'q'; | |
13151 | else if ((prefixes & PREFIX_DATA)) | |
13152 | { | |
13153 | if (!(sizeflag & DFLAG)) | |
13154 | *obufp++ = 'w'; | |
13155 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13156 | } | |
13157 | break; | |
252b5132 | 13158 | } |
21a3faeb JB |
13159 | |
13160 | if (len == l) | |
13161 | len = l = 0; | |
252b5132 RH |
13162 | } |
13163 | *obufp = 0; | |
ea397f5b | 13164 | mnemonicendp = obufp; |
6439fc28 | 13165 | return 0; |
252b5132 RH |
13166 | } |
13167 | ||
13168 | static void | |
26ca5450 | 13169 | oappend (const char *s) |
252b5132 | 13170 | { |
ea397f5b | 13171 | obufp = stpcpy (obufp, s); |
252b5132 RH |
13172 | } |
13173 | ||
13174 | static void | |
26ca5450 | 13175 | append_seg (void) |
252b5132 | 13176 | { |
285ca992 L |
13177 | /* Only print the active segment register. */ |
13178 | if (!active_seg_prefix) | |
13179 | return; | |
13180 | ||
13181 | used_prefixes |= active_seg_prefix; | |
13182 | switch (active_seg_prefix) | |
7d421014 | 13183 | { |
285ca992 | 13184 | case PREFIX_CS: |
9ce09ba2 | 13185 | oappend_maybe_intel ("%cs:"); |
285ca992 L |
13186 | break; |
13187 | case PREFIX_DS: | |
9ce09ba2 | 13188 | oappend_maybe_intel ("%ds:"); |
285ca992 L |
13189 | break; |
13190 | case PREFIX_SS: | |
9ce09ba2 | 13191 | oappend_maybe_intel ("%ss:"); |
285ca992 L |
13192 | break; |
13193 | case PREFIX_ES: | |
9ce09ba2 | 13194 | oappend_maybe_intel ("%es:"); |
285ca992 L |
13195 | break; |
13196 | case PREFIX_FS: | |
9ce09ba2 | 13197 | oappend_maybe_intel ("%fs:"); |
285ca992 L |
13198 | break; |
13199 | case PREFIX_GS: | |
9ce09ba2 | 13200 | oappend_maybe_intel ("%gs:"); |
285ca992 L |
13201 | break; |
13202 | default: | |
13203 | break; | |
7d421014 | 13204 | } |
252b5132 RH |
13205 | } |
13206 | ||
13207 | static void | |
26ca5450 | 13208 | OP_indirE (int bytemode, int sizeflag) |
252b5132 RH |
13209 | { |
13210 | if (!intel_syntax) | |
13211 | oappend ("*"); | |
13212 | OP_E (bytemode, sizeflag); | |
13213 | } | |
13214 | ||
52b15da3 | 13215 | static void |
26ca5450 | 13216 | print_operand_value (char *buf, int hex, bfd_vma disp) |
52b15da3 | 13217 | { |
cb712a9e | 13218 | if (address_mode == mode_64bit) |
52b15da3 JH |
13219 | { |
13220 | if (hex) | |
13221 | { | |
13222 | char tmp[30]; | |
13223 | int i; | |
13224 | buf[0] = '0'; | |
13225 | buf[1] = 'x'; | |
13226 | sprintf_vma (tmp, disp); | |
6608db57 | 13227 | for (i = 0; tmp[i] == '0' && tmp[i + 1]; i++); |
52b15da3 JH |
13228 | strcpy (buf + 2, tmp + i); |
13229 | } | |
13230 | else | |
13231 | { | |
13232 | bfd_signed_vma v = disp; | |
13233 | char tmp[30]; | |
13234 | int i; | |
13235 | if (v < 0) | |
13236 | { | |
13237 | *(buf++) = '-'; | |
13238 | v = -disp; | |
6608db57 | 13239 | /* Check for possible overflow on 0x8000000000000000. */ |
52b15da3 JH |
13240 | if (v < 0) |
13241 | { | |
13242 | strcpy (buf, "9223372036854775808"); | |
13243 | return; | |
13244 | } | |
13245 | } | |
13246 | if (!v) | |
13247 | { | |
13248 | strcpy (buf, "0"); | |
13249 | return; | |
13250 | } | |
13251 | ||
13252 | i = 0; | |
13253 | tmp[29] = 0; | |
13254 | while (v) | |
13255 | { | |
6608db57 | 13256 | tmp[28 - i] = (v % 10) + '0'; |
52b15da3 JH |
13257 | v /= 10; |
13258 | i++; | |
13259 | } | |
13260 | strcpy (buf, tmp + 29 - i); | |
13261 | } | |
13262 | } | |
13263 | else | |
13264 | { | |
13265 | if (hex) | |
13266 | sprintf (buf, "0x%x", (unsigned int) disp); | |
13267 | else | |
13268 | sprintf (buf, "%d", (int) disp); | |
13269 | } | |
13270 | } | |
13271 | ||
5d669648 L |
13272 | /* Put DISP in BUF as signed hex number. */ |
13273 | ||
13274 | static void | |
13275 | print_displacement (char *buf, bfd_vma disp) | |
13276 | { | |
13277 | bfd_signed_vma val = disp; | |
13278 | char tmp[30]; | |
13279 | int i, j = 0; | |
13280 | ||
13281 | if (val < 0) | |
13282 | { | |
13283 | buf[j++] = '-'; | |
13284 | val = -disp; | |
13285 | ||
13286 | /* Check for possible overflow. */ | |
13287 | if (val < 0) | |
13288 | { | |
13289 | switch (address_mode) | |
13290 | { | |
13291 | case mode_64bit: | |
13292 | strcpy (buf + j, "0x8000000000000000"); | |
13293 | break; | |
13294 | case mode_32bit: | |
13295 | strcpy (buf + j, "0x80000000"); | |
13296 | break; | |
13297 | case mode_16bit: | |
13298 | strcpy (buf + j, "0x8000"); | |
13299 | break; | |
13300 | } | |
13301 | return; | |
13302 | } | |
13303 | } | |
13304 | ||
13305 | buf[j++] = '0'; | |
13306 | buf[j++] = 'x'; | |
13307 | ||
0af1713e | 13308 | sprintf_vma (tmp, (bfd_vma) val); |
5d669648 L |
13309 | for (i = 0; tmp[i] == '0'; i++) |
13310 | continue; | |
13311 | if (tmp[i] == '\0') | |
13312 | i--; | |
13313 | strcpy (buf + j, tmp + i); | |
13314 | } | |
13315 | ||
3f31e633 JB |
13316 | static void |
13317 | intel_operand_size (int bytemode, int sizeflag) | |
13318 | { | |
43234a1e L |
13319 | if (vex.evex |
13320 | && vex.b | |
13321 | && (bytemode == x_mode | |
13322 | || bytemode == evex_half_bcst_xmmq_mode)) | |
13323 | { | |
13324 | if (vex.w) | |
13325 | oappend ("QWORD PTR "); | |
13326 | else | |
13327 | oappend ("DWORD PTR "); | |
13328 | return; | |
13329 | } | |
3f31e633 JB |
13330 | switch (bytemode) |
13331 | { | |
13332 | case b_mode: | |
b6169b20 | 13333 | case b_swap_mode: |
42903f7f | 13334 | case dqb_mode: |
1ba585e8 | 13335 | case db_mode: |
3f31e633 JB |
13336 | oappend ("BYTE PTR "); |
13337 | break; | |
13338 | case w_mode: | |
1ba585e8 | 13339 | case dw_mode: |
3f31e633 JB |
13340 | case dqw_mode: |
13341 | oappend ("WORD PTR "); | |
13342 | break; | |
07f5af7d L |
13343 | case indir_v_mode: |
13344 | if (address_mode == mode_64bit && isa64 == intel64) | |
13345 | { | |
13346 | oappend ("QWORD PTR "); | |
13347 | break; | |
13348 | } | |
1a0670f3 | 13349 | /* Fall through. */ |
1a114b12 | 13350 | case stack_v_mode: |
7bb15c6f | 13351 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
3f31e633 JB |
13352 | { |
13353 | oappend ("QWORD PTR "); | |
3f31e633 JB |
13354 | break; |
13355 | } | |
1a0670f3 | 13356 | /* Fall through. */ |
3f31e633 | 13357 | case v_mode: |
b6169b20 | 13358 | case v_swap_mode: |
3f31e633 | 13359 | case dq_mode: |
161a04f6 L |
13360 | USED_REX (REX_W); |
13361 | if (rex & REX_W) | |
3f31e633 | 13362 | oappend ("QWORD PTR "); |
3f31e633 | 13363 | else |
f16cd0d5 L |
13364 | { |
13365 | if ((sizeflag & DFLAG) || bytemode == dq_mode) | |
13366 | oappend ("DWORD PTR "); | |
13367 | else | |
13368 | oappend ("WORD PTR "); | |
13369 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13370 | } | |
3f31e633 | 13371 | break; |
52fd6d94 | 13372 | case z_mode: |
161a04f6 | 13373 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
13374 | *obufp++ = 'D'; |
13375 | oappend ("WORD PTR "); | |
161a04f6 | 13376 | if (!(rex & REX_W)) |
52fd6d94 JB |
13377 | used_prefixes |= (prefixes & PREFIX_DATA); |
13378 | break; | |
34b772a6 JB |
13379 | case a_mode: |
13380 | if (sizeflag & DFLAG) | |
13381 | oappend ("QWORD PTR "); | |
13382 | else | |
13383 | oappend ("DWORD PTR "); | |
13384 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13385 | break; | |
bc31405e L |
13386 | case movsxd_mode: |
13387 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13388 | oappend ("WORD PTR "); | |
13389 | else | |
13390 | oappend ("DWORD PTR "); | |
13391 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13392 | break; | |
3f31e633 | 13393 | case d_mode: |
539f890d | 13394 | case d_scalar_swap_mode: |
fa99fab2 | 13395 | case d_swap_mode: |
42903f7f | 13396 | case dqd_mode: |
3f31e633 JB |
13397 | oappend ("DWORD PTR "); |
13398 | break; | |
13399 | case q_mode: | |
539f890d | 13400 | case q_scalar_swap_mode: |
b6169b20 | 13401 | case q_swap_mode: |
3f31e633 JB |
13402 | oappend ("QWORD PTR "); |
13403 | break; | |
13404 | case m_mode: | |
cb712a9e | 13405 | if (address_mode == mode_64bit) |
3f31e633 JB |
13406 | oappend ("QWORD PTR "); |
13407 | else | |
13408 | oappend ("DWORD PTR "); | |
13409 | break; | |
13410 | case f_mode: | |
13411 | if (sizeflag & DFLAG) | |
13412 | oappend ("FWORD PTR "); | |
13413 | else | |
13414 | oappend ("DWORD PTR "); | |
13415 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13416 | break; | |
13417 | case t_mode: | |
13418 | oappend ("TBYTE PTR "); | |
13419 | break; | |
13420 | case x_mode: | |
b6169b20 | 13421 | case x_swap_mode: |
43234a1e L |
13422 | case evex_x_gscat_mode: |
13423 | case evex_x_nobcst_mode: | |
53467f57 IT |
13424 | case b_scalar_mode: |
13425 | case w_scalar_mode: | |
c0f3af97 L |
13426 | if (need_vex) |
13427 | { | |
13428 | switch (vex.length) | |
13429 | { | |
13430 | case 128: | |
13431 | oappend ("XMMWORD PTR "); | |
13432 | break; | |
13433 | case 256: | |
13434 | oappend ("YMMWORD PTR "); | |
13435 | break; | |
43234a1e L |
13436 | case 512: |
13437 | oappend ("ZMMWORD PTR "); | |
13438 | break; | |
c0f3af97 L |
13439 | default: |
13440 | abort (); | |
13441 | } | |
13442 | } | |
13443 | else | |
13444 | oappend ("XMMWORD PTR "); | |
13445 | break; | |
13446 | case xmm_mode: | |
3f31e633 JB |
13447 | oappend ("XMMWORD PTR "); |
13448 | break; | |
43234a1e L |
13449 | case ymm_mode: |
13450 | oappend ("YMMWORD PTR "); | |
13451 | break; | |
c0f3af97 | 13452 | case xmmq_mode: |
43234a1e | 13453 | case evex_half_bcst_xmmq_mode: |
c0f3af97 L |
13454 | if (!need_vex) |
13455 | abort (); | |
13456 | ||
13457 | switch (vex.length) | |
13458 | { | |
13459 | case 128: | |
13460 | oappend ("QWORD PTR "); | |
13461 | break; | |
13462 | case 256: | |
13463 | oappend ("XMMWORD PTR "); | |
13464 | break; | |
43234a1e L |
13465 | case 512: |
13466 | oappend ("YMMWORD PTR "); | |
13467 | break; | |
c0f3af97 L |
13468 | default: |
13469 | abort (); | |
13470 | } | |
13471 | break; | |
6c30d220 L |
13472 | case xmm_mb_mode: |
13473 | if (!need_vex) | |
13474 | abort (); | |
13475 | ||
13476 | switch (vex.length) | |
13477 | { | |
13478 | case 128: | |
13479 | case 256: | |
43234a1e | 13480 | case 512: |
6c30d220 L |
13481 | oappend ("BYTE PTR "); |
13482 | break; | |
13483 | default: | |
13484 | abort (); | |
13485 | } | |
13486 | break; | |
13487 | case xmm_mw_mode: | |
13488 | if (!need_vex) | |
13489 | abort (); | |
13490 | ||
13491 | switch (vex.length) | |
13492 | { | |
13493 | case 128: | |
13494 | case 256: | |
43234a1e | 13495 | case 512: |
6c30d220 L |
13496 | oappend ("WORD PTR "); |
13497 | break; | |
13498 | default: | |
13499 | abort (); | |
13500 | } | |
13501 | break; | |
13502 | case xmm_md_mode: | |
13503 | if (!need_vex) | |
13504 | abort (); | |
13505 | ||
13506 | switch (vex.length) | |
13507 | { | |
13508 | case 128: | |
13509 | case 256: | |
43234a1e | 13510 | case 512: |
6c30d220 L |
13511 | oappend ("DWORD PTR "); |
13512 | break; | |
13513 | default: | |
13514 | abort (); | |
13515 | } | |
13516 | break; | |
13517 | case xmm_mq_mode: | |
13518 | if (!need_vex) | |
13519 | abort (); | |
13520 | ||
13521 | switch (vex.length) | |
13522 | { | |
13523 | case 128: | |
13524 | case 256: | |
43234a1e | 13525 | case 512: |
6c30d220 L |
13526 | oappend ("QWORD PTR "); |
13527 | break; | |
13528 | default: | |
13529 | abort (); | |
13530 | } | |
13531 | break; | |
13532 | case xmmdw_mode: | |
13533 | if (!need_vex) | |
13534 | abort (); | |
13535 | ||
13536 | switch (vex.length) | |
13537 | { | |
13538 | case 128: | |
13539 | oappend ("WORD PTR "); | |
13540 | break; | |
13541 | case 256: | |
13542 | oappend ("DWORD PTR "); | |
13543 | break; | |
43234a1e L |
13544 | case 512: |
13545 | oappend ("QWORD PTR "); | |
13546 | break; | |
6c30d220 L |
13547 | default: |
13548 | abort (); | |
13549 | } | |
13550 | break; | |
13551 | case xmmqd_mode: | |
13552 | if (!need_vex) | |
13553 | abort (); | |
13554 | ||
13555 | switch (vex.length) | |
13556 | { | |
13557 | case 128: | |
13558 | oappend ("DWORD PTR "); | |
13559 | break; | |
13560 | case 256: | |
13561 | oappend ("QWORD PTR "); | |
13562 | break; | |
43234a1e L |
13563 | case 512: |
13564 | oappend ("XMMWORD PTR "); | |
13565 | break; | |
6c30d220 L |
13566 | default: |
13567 | abort (); | |
13568 | } | |
13569 | break; | |
c0f3af97 L |
13570 | case ymmq_mode: |
13571 | if (!need_vex) | |
13572 | abort (); | |
13573 | ||
13574 | switch (vex.length) | |
13575 | { | |
13576 | case 128: | |
13577 | oappend ("QWORD PTR "); | |
13578 | break; | |
13579 | case 256: | |
13580 | oappend ("YMMWORD PTR "); | |
13581 | break; | |
43234a1e L |
13582 | case 512: |
13583 | oappend ("ZMMWORD PTR "); | |
13584 | break; | |
c0f3af97 L |
13585 | default: |
13586 | abort (); | |
13587 | } | |
13588 | break; | |
6c30d220 L |
13589 | case ymmxmm_mode: |
13590 | if (!need_vex) | |
13591 | abort (); | |
13592 | ||
13593 | switch (vex.length) | |
13594 | { | |
13595 | case 128: | |
13596 | case 256: | |
13597 | oappend ("XMMWORD PTR "); | |
13598 | break; | |
13599 | default: | |
13600 | abort (); | |
13601 | } | |
13602 | break; | |
fb9c77c7 L |
13603 | case o_mode: |
13604 | oappend ("OWORD PTR "); | |
13605 | break; | |
1c480963 | 13606 | case vex_scalar_w_dq_mode: |
0bfee649 L |
13607 | if (!need_vex) |
13608 | abort (); | |
13609 | ||
13610 | if (vex.w) | |
13611 | oappend ("QWORD PTR "); | |
13612 | else | |
13613 | oappend ("DWORD PTR "); | |
13614 | break; | |
43234a1e L |
13615 | case vex_vsib_d_w_dq_mode: |
13616 | case vex_vsib_q_w_dq_mode: | |
13617 | if (!need_vex) | |
13618 | abort (); | |
13619 | ||
13620 | if (!vex.evex) | |
13621 | { | |
13622 | if (vex.w) | |
13623 | oappend ("QWORD PTR "); | |
13624 | else | |
13625 | oappend ("DWORD PTR "); | |
13626 | } | |
13627 | else | |
13628 | { | |
b28d1bda IT |
13629 | switch (vex.length) |
13630 | { | |
13631 | case 128: | |
13632 | oappend ("XMMWORD PTR "); | |
13633 | break; | |
13634 | case 256: | |
13635 | oappend ("YMMWORD PTR "); | |
13636 | break; | |
13637 | case 512: | |
13638 | oappend ("ZMMWORD PTR "); | |
13639 | break; | |
13640 | default: | |
13641 | abort (); | |
13642 | } | |
43234a1e L |
13643 | } |
13644 | break; | |
5fc35d96 IT |
13645 | case vex_vsib_q_w_d_mode: |
13646 | case vex_vsib_d_w_d_mode: | |
b28d1bda | 13647 | if (!need_vex || !vex.evex) |
5fc35d96 IT |
13648 | abort (); |
13649 | ||
b28d1bda IT |
13650 | switch (vex.length) |
13651 | { | |
13652 | case 128: | |
13653 | oappend ("QWORD PTR "); | |
13654 | break; | |
13655 | case 256: | |
13656 | oappend ("XMMWORD PTR "); | |
13657 | break; | |
13658 | case 512: | |
13659 | oappend ("YMMWORD PTR "); | |
13660 | break; | |
13661 | default: | |
13662 | abort (); | |
13663 | } | |
5fc35d96 IT |
13664 | |
13665 | break; | |
1ba585e8 IT |
13666 | case mask_bd_mode: |
13667 | if (!need_vex || vex.length != 128) | |
13668 | abort (); | |
13669 | if (vex.w) | |
13670 | oappend ("DWORD PTR "); | |
13671 | else | |
13672 | oappend ("BYTE PTR "); | |
13673 | break; | |
43234a1e L |
13674 | case mask_mode: |
13675 | if (!need_vex) | |
13676 | abort (); | |
1ba585e8 IT |
13677 | if (vex.w) |
13678 | oappend ("QWORD PTR "); | |
13679 | else | |
13680 | oappend ("WORD PTR "); | |
43234a1e | 13681 | break; |
6c75cc62 | 13682 | case v_bnd_mode: |
d276ec69 | 13683 | case v_bndmk_mode: |
3f31e633 JB |
13684 | default: |
13685 | break; | |
13686 | } | |
13687 | } | |
13688 | ||
252b5132 | 13689 | static void |
c0f3af97 | 13690 | OP_E_register (int bytemode, int sizeflag) |
252b5132 | 13691 | { |
c0f3af97 L |
13692 | int reg = modrm.rm; |
13693 | const char **names; | |
252b5132 | 13694 | |
c0f3af97 L |
13695 | USED_REX (REX_B); |
13696 | if ((rex & REX_B)) | |
13697 | reg += 8; | |
252b5132 | 13698 | |
b6169b20 | 13699 | if ((sizeflag & SUFFIX_ALWAYS) |
1ba585e8 | 13700 | && (bytemode == b_swap_mode |
9f79e886 | 13701 | || bytemode == bnd_swap_mode |
60227d64 | 13702 | || bytemode == v_swap_mode)) |
b6169b20 L |
13703 | swap_operand (); |
13704 | ||
c0f3af97 | 13705 | switch (bytemode) |
252b5132 | 13706 | { |
c0f3af97 | 13707 | case b_mode: |
b6169b20 | 13708 | case b_swap_mode: |
c0f3af97 L |
13709 | USED_REX (0); |
13710 | if (rex) | |
13711 | names = names8rex; | |
13712 | else | |
13713 | names = names8; | |
13714 | break; | |
13715 | case w_mode: | |
13716 | names = names16; | |
13717 | break; | |
13718 | case d_mode: | |
1ba585e8 IT |
13719 | case dw_mode: |
13720 | case db_mode: | |
c0f3af97 L |
13721 | names = names32; |
13722 | break; | |
13723 | case q_mode: | |
13724 | names = names64; | |
13725 | break; | |
13726 | case m_mode: | |
6c75cc62 | 13727 | case v_bnd_mode: |
c0f3af97 L |
13728 | names = address_mode == mode_64bit ? names64 : names32; |
13729 | break; | |
7e8b059b | 13730 | case bnd_mode: |
9f79e886 | 13731 | case bnd_swap_mode: |
0d96e4df L |
13732 | if (reg > 0x3) |
13733 | { | |
13734 | oappend ("(bad)"); | |
13735 | return; | |
13736 | } | |
7e8b059b L |
13737 | names = names_bnd; |
13738 | break; | |
07f5af7d L |
13739 | case indir_v_mode: |
13740 | if (address_mode == mode_64bit && isa64 == intel64) | |
13741 | { | |
13742 | names = names64; | |
13743 | break; | |
13744 | } | |
1a0670f3 | 13745 | /* Fall through. */ |
c0f3af97 | 13746 | case stack_v_mode: |
7bb15c6f | 13747 | if (address_mode == mode_64bit && ((sizeflag & DFLAG) || (rex & REX_W))) |
252b5132 | 13748 | { |
c0f3af97 | 13749 | names = names64; |
252b5132 | 13750 | break; |
252b5132 | 13751 | } |
c0f3af97 | 13752 | bytemode = v_mode; |
1a0670f3 | 13753 | /* Fall through. */ |
c0f3af97 | 13754 | case v_mode: |
b6169b20 | 13755 | case v_swap_mode: |
c0f3af97 L |
13756 | case dq_mode: |
13757 | case dqb_mode: | |
13758 | case dqd_mode: | |
13759 | case dqw_mode: | |
13760 | USED_REX (REX_W); | |
13761 | if (rex & REX_W) | |
13762 | names = names64; | |
c0f3af97 | 13763 | else |
f16cd0d5 | 13764 | { |
7bb15c6f | 13765 | if ((sizeflag & DFLAG) |
f16cd0d5 L |
13766 | || (bytemode != v_mode |
13767 | && bytemode != v_swap_mode)) | |
13768 | names = names32; | |
13769 | else | |
13770 | names = names16; | |
13771 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13772 | } | |
c0f3af97 | 13773 | break; |
bc31405e L |
13774 | case movsxd_mode: |
13775 | if (!(sizeflag & DFLAG) && isa64 == intel64) | |
13776 | names = names16; | |
13777 | else | |
13778 | names = names32; | |
13779 | used_prefixes |= (prefixes & PREFIX_DATA); | |
13780 | break; | |
de89d0a3 IT |
13781 | case va_mode: |
13782 | names = (address_mode == mode_64bit | |
13783 | ? names64 : names32); | |
13784 | if (!(prefixes & PREFIX_ADDR)) | |
aa178437 IT |
13785 | names = (address_mode == mode_16bit |
13786 | ? names16 : names); | |
de89d0a3 IT |
13787 | else |
13788 | { | |
13789 | /* Remove "addr16/addr32". */ | |
13790 | all_prefixes[last_addr_prefix] = 0; | |
13791 | names = (address_mode != mode_32bit | |
13792 | ? names32 : names16); | |
13793 | used_prefixes |= PREFIX_ADDR; | |
13794 | } | |
13795 | break; | |
1ba585e8 | 13796 | case mask_bd_mode: |
43234a1e | 13797 | case mask_mode: |
9889cbb1 L |
13798 | if (reg > 0x7) |
13799 | { | |
13800 | oappend ("(bad)"); | |
13801 | return; | |
13802 | } | |
43234a1e L |
13803 | names = names_mask; |
13804 | break; | |
c0f3af97 L |
13805 | case 0: |
13806 | return; | |
13807 | default: | |
13808 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
252b5132 RH |
13809 | return; |
13810 | } | |
c0f3af97 L |
13811 | oappend (names[reg]); |
13812 | } | |
13813 | ||
13814 | static void | |
c1e679ec | 13815 | OP_E_memory (int bytemode, int sizeflag) |
c0f3af97 L |
13816 | { |
13817 | bfd_vma disp = 0; | |
13818 | int add = (rex & REX_B) ? 8 : 0; | |
13819 | int riprel = 0; | |
43234a1e L |
13820 | int shift; |
13821 | ||
13822 | if (vex.evex) | |
13823 | { | |
13824 | /* In EVEX, if operand doesn't allow broadcast, vex.b should be 0. */ | |
13825 | if (vex.b | |
13826 | && bytemode != x_mode | |
90a915bf | 13827 | && bytemode != xmmq_mode |
43234a1e L |
13828 | && bytemode != evex_half_bcst_xmmq_mode) |
13829 | { | |
13830 | BadOp (); | |
13831 | return; | |
13832 | } | |
13833 | switch (bytemode) | |
13834 | { | |
1ba585e8 IT |
13835 | case dqw_mode: |
13836 | case dw_mode: | |
1ba585e8 IT |
13837 | shift = 1; |
13838 | break; | |
13839 | case dqb_mode: | |
13840 | case db_mode: | |
13841 | shift = 0; | |
13842 | break; | |
b50c9f31 JB |
13843 | case dq_mode: |
13844 | if (address_mode != mode_64bit) | |
13845 | { | |
13846 | shift = 2; | |
13847 | break; | |
13848 | } | |
13849 | /* fall through */ | |
4102be5c | 13850 | case vex_scalar_w_dq_mode: |
43234a1e | 13851 | case vex_vsib_d_w_dq_mode: |
5fc35d96 | 13852 | case vex_vsib_d_w_d_mode: |
eaa9d1ad | 13853 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13854 | case vex_vsib_q_w_d_mode: |
43234a1e | 13855 | case evex_x_gscat_mode: |
43234a1e L |
13856 | shift = vex.w ? 3 : 2; |
13857 | break; | |
43234a1e L |
13858 | case x_mode: |
13859 | case evex_half_bcst_xmmq_mode: | |
90a915bf | 13860 | case xmmq_mode: |
43234a1e L |
13861 | if (vex.b) |
13862 | { | |
13863 | shift = vex.w ? 3 : 2; | |
13864 | break; | |
13865 | } | |
1a0670f3 | 13866 | /* Fall through. */ |
43234a1e L |
13867 | case xmmqd_mode: |
13868 | case xmmdw_mode: | |
43234a1e L |
13869 | case ymmq_mode: |
13870 | case evex_x_nobcst_mode: | |
13871 | case x_swap_mode: | |
13872 | switch (vex.length) | |
13873 | { | |
13874 | case 128: | |
13875 | shift = 4; | |
13876 | break; | |
13877 | case 256: | |
13878 | shift = 5; | |
13879 | break; | |
13880 | case 512: | |
13881 | shift = 6; | |
13882 | break; | |
13883 | default: | |
13884 | abort (); | |
13885 | } | |
13886 | break; | |
13887 | case ymm_mode: | |
13888 | shift = 5; | |
13889 | break; | |
13890 | case xmm_mode: | |
13891 | shift = 4; | |
13892 | break; | |
13893 | case xmm_mq_mode: | |
13894 | case q_mode: | |
43234a1e L |
13895 | case q_swap_mode: |
13896 | case q_scalar_swap_mode: | |
13897 | shift = 3; | |
13898 | break; | |
13899 | case dqd_mode: | |
13900 | case xmm_md_mode: | |
13901 | case d_mode: | |
43234a1e L |
13902 | case d_swap_mode: |
13903 | case d_scalar_swap_mode: | |
13904 | shift = 2; | |
13905 | break; | |
5074ad8a | 13906 | case w_scalar_mode: |
43234a1e L |
13907 | case xmm_mw_mode: |
13908 | shift = 1; | |
13909 | break; | |
5074ad8a | 13910 | case b_scalar_mode: |
43234a1e L |
13911 | case xmm_mb_mode: |
13912 | shift = 0; | |
13913 | break; | |
13914 | default: | |
13915 | abort (); | |
13916 | } | |
13917 | /* Make necessary corrections to shift for modes that need it. | |
13918 | For these modes we currently have shift 4, 5 or 6 depending on | |
13919 | vex.length (it corresponds to xmmword, ymmword or zmmword | |
13920 | operand). We might want to make it 3, 4 or 5 (e.g. for | |
13921 | xmmq_mode). In case of broadcast enabled the corrections | |
13922 | aren't needed, as element size is always 32 or 64 bits. */ | |
90a915bf IT |
13923 | if (!vex.b |
13924 | && (bytemode == xmmq_mode | |
13925 | || bytemode == evex_half_bcst_xmmq_mode)) | |
43234a1e L |
13926 | shift -= 1; |
13927 | else if (bytemode == xmmqd_mode) | |
13928 | shift -= 2; | |
13929 | else if (bytemode == xmmdw_mode) | |
13930 | shift -= 3; | |
b28d1bda IT |
13931 | else if (bytemode == ymmq_mode && vex.length == 128) |
13932 | shift -= 1; | |
43234a1e L |
13933 | } |
13934 | else | |
13935 | shift = 0; | |
252b5132 | 13936 | |
c0f3af97 | 13937 | USED_REX (REX_B); |
3f31e633 JB |
13938 | if (intel_syntax) |
13939 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
13940 | append_seg (); |
13941 | ||
5d669648 | 13942 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 | 13943 | { |
5d669648 L |
13944 | /* 32/64 bit address mode */ |
13945 | int havedisp; | |
252b5132 RH |
13946 | int havesib; |
13947 | int havebase; | |
0f7da397 | 13948 | int haveindex; |
20afcfb7 | 13949 | int needindex; |
1bc60e56 | 13950 | int needaddr32; |
82c18208 | 13951 | int base, rbase; |
91d6fa6a | 13952 | int vindex = 0; |
252b5132 | 13953 | int scale = 0; |
7e8b059b L |
13954 | int addr32flag = !((sizeflag & AFLAG) |
13955 | || bytemode == v_bnd_mode | |
d276ec69 | 13956 | || bytemode == v_bndmk_mode |
9f79e886 JB |
13957 | || bytemode == bnd_mode |
13958 | || bytemode == bnd_swap_mode); | |
6c30d220 L |
13959 | const char **indexes64 = names64; |
13960 | const char **indexes32 = names32; | |
252b5132 RH |
13961 | |
13962 | havesib = 0; | |
13963 | havebase = 1; | |
0f7da397 | 13964 | haveindex = 0; |
7967e09e | 13965 | base = modrm.rm; |
252b5132 RH |
13966 | |
13967 | if (base == 4) | |
13968 | { | |
13969 | havesib = 1; | |
dfc8cf43 | 13970 | vindex = sib.index; |
161a04f6 L |
13971 | USED_REX (REX_X); |
13972 | if (rex & REX_X) | |
91d6fa6a | 13973 | vindex += 8; |
6c30d220 L |
13974 | switch (bytemode) |
13975 | { | |
13976 | case vex_vsib_d_w_dq_mode: | |
5fc35d96 | 13977 | case vex_vsib_d_w_d_mode: |
6c30d220 | 13978 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 13979 | case vex_vsib_q_w_d_mode: |
6c30d220 L |
13980 | if (!need_vex) |
13981 | abort (); | |
43234a1e L |
13982 | if (vex.evex) |
13983 | { | |
13984 | if (!vex.v) | |
13985 | vindex += 16; | |
13986 | } | |
6c30d220 L |
13987 | |
13988 | haveindex = 1; | |
13989 | switch (vex.length) | |
13990 | { | |
13991 | case 128: | |
7bb15c6f | 13992 | indexes64 = indexes32 = names_xmm; |
6c30d220 L |
13993 | break; |
13994 | case 256: | |
5fc35d96 IT |
13995 | if (!vex.w |
13996 | || bytemode == vex_vsib_q_w_dq_mode | |
13997 | || bytemode == vex_vsib_q_w_d_mode) | |
7bb15c6f | 13998 | indexes64 = indexes32 = names_ymm; |
6c30d220 | 13999 | else |
7bb15c6f | 14000 | indexes64 = indexes32 = names_xmm; |
6c30d220 | 14001 | break; |
43234a1e | 14002 | case 512: |
5fc35d96 IT |
14003 | if (!vex.w |
14004 | || bytemode == vex_vsib_q_w_dq_mode | |
14005 | || bytemode == vex_vsib_q_w_d_mode) | |
43234a1e L |
14006 | indexes64 = indexes32 = names_zmm; |
14007 | else | |
14008 | indexes64 = indexes32 = names_ymm; | |
14009 | break; | |
6c30d220 L |
14010 | default: |
14011 | abort (); | |
14012 | } | |
14013 | break; | |
14014 | default: | |
14015 | haveindex = vindex != 4; | |
14016 | break; | |
14017 | } | |
14018 | scale = sib.scale; | |
14019 | base = sib.base; | |
252b5132 RH |
14020 | codep++; |
14021 | } | |
82c18208 | 14022 | rbase = base + add; |
252b5132 | 14023 | |
7967e09e | 14024 | switch (modrm.mod) |
252b5132 RH |
14025 | { |
14026 | case 0: | |
82c18208 | 14027 | if (base == 5) |
252b5132 RH |
14028 | { |
14029 | havebase = 0; | |
cb712a9e | 14030 | if (address_mode == mode_64bit && !havesib) |
52b15da3 JH |
14031 | riprel = 1; |
14032 | disp = get32s (); | |
d276ec69 JB |
14033 | if (riprel && bytemode == v_bndmk_mode) |
14034 | { | |
14035 | oappend ("(bad)"); | |
14036 | return; | |
14037 | } | |
252b5132 RH |
14038 | } |
14039 | break; | |
14040 | case 1: | |
14041 | FETCH_DATA (the_info, codep + 1); | |
14042 | disp = *codep++; | |
14043 | if ((disp & 0x80) != 0) | |
14044 | disp -= 0x100; | |
43234a1e L |
14045 | if (vex.evex && shift > 0) |
14046 | disp <<= shift; | |
252b5132 RH |
14047 | break; |
14048 | case 2: | |
52b15da3 | 14049 | disp = get32s (); |
252b5132 RH |
14050 | break; |
14051 | } | |
14052 | ||
1bc60e56 L |
14053 | needindex = 0; |
14054 | needaddr32 = 0; | |
14055 | if (havesib | |
14056 | && !havebase | |
14057 | && !haveindex | |
14058 | && address_mode != mode_16bit) | |
14059 | { | |
14060 | if (address_mode == mode_64bit) | |
14061 | { | |
14062 | /* Display eiz instead of addr32. */ | |
14063 | needindex = addr32flag; | |
14064 | needaddr32 = 1; | |
14065 | } | |
14066 | else | |
14067 | { | |
14068 | /* In 32-bit mode, we need index register to tell [offset] | |
14069 | from [eiz*1 + offset]. */ | |
14070 | needindex = 1; | |
14071 | } | |
14072 | } | |
14073 | ||
20afcfb7 L |
14074 | havedisp = (havebase |
14075 | || needindex | |
14076 | || (havesib && (haveindex || scale != 0))); | |
5d669648 | 14077 | |
252b5132 | 14078 | if (!intel_syntax) |
82c18208 | 14079 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14080 | { |
5d669648 L |
14081 | if (havedisp || riprel) |
14082 | print_displacement (scratchbuf, disp); | |
14083 | else | |
14084 | print_operand_value (scratchbuf, 1, disp); | |
db6eb5be | 14085 | oappend (scratchbuf); |
52b15da3 JH |
14086 | if (riprel) |
14087 | { | |
14088 | set_op (disp, 1); | |
28596323 | 14089 | oappend (!addr32flag ? "(%rip)" : "(%eip)"); |
52b15da3 | 14090 | } |
db6eb5be | 14091 | } |
2da11e11 | 14092 | |
c1dc7af5 | 14093 | if ((havebase || haveindex || needindex || needaddr32 || riprel) |
a23b33b3 JB |
14094 | && (address_mode != mode_64bit |
14095 | || ((bytemode != v_bnd_mode) | |
14096 | && (bytemode != v_bndmk_mode) | |
14097 | && (bytemode != bnd_mode) | |
14098 | && (bytemode != bnd_swap_mode)))) | |
87767711 JB |
14099 | used_prefixes |= PREFIX_ADDR; |
14100 | ||
5d669648 | 14101 | if (havedisp || (intel_syntax && riprel)) |
252b5132 | 14102 | { |
252b5132 | 14103 | *obufp++ = open_char; |
52b15da3 | 14104 | if (intel_syntax && riprel) |
185b1163 L |
14105 | { |
14106 | set_op (disp, 1); | |
28596323 | 14107 | oappend (!addr32flag ? "rip" : "eip"); |
185b1163 | 14108 | } |
db6eb5be | 14109 | *obufp = '\0'; |
252b5132 | 14110 | if (havebase) |
7e8b059b | 14111 | oappend (address_mode == mode_64bit && !addr32flag |
82c18208 | 14112 | ? names64[rbase] : names32[rbase]); |
252b5132 RH |
14113 | if (havesib) |
14114 | { | |
db51cc60 L |
14115 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
14116 | print index to tell base + index from base. */ | |
14117 | if (scale != 0 | |
20afcfb7 | 14118 | || needindex |
db51cc60 L |
14119 | || haveindex |
14120 | || (havebase && base != ESP_REG_NUM)) | |
252b5132 | 14121 | { |
9306ca4a | 14122 | if (!intel_syntax || havebase) |
db6eb5be | 14123 | { |
9306ca4a JB |
14124 | *obufp++ = separator_char; |
14125 | *obufp = '\0'; | |
db6eb5be | 14126 | } |
db51cc60 | 14127 | if (haveindex) |
7e8b059b | 14128 | oappend (address_mode == mode_64bit && !addr32flag |
6c30d220 | 14129 | ? indexes64[vindex] : indexes32[vindex]); |
db51cc60 | 14130 | else |
7e8b059b | 14131 | oappend (address_mode == mode_64bit && !addr32flag |
db51cc60 L |
14132 | ? index64 : index32); |
14133 | ||
db6eb5be AM |
14134 | *obufp++ = scale_char; |
14135 | *obufp = '\0'; | |
14136 | sprintf (scratchbuf, "%d", 1 << scale); | |
14137 | oappend (scratchbuf); | |
14138 | } | |
252b5132 | 14139 | } |
185b1163 | 14140 | if (intel_syntax |
82c18208 | 14141 | && (disp || modrm.mod != 0 || base == 5)) |
3d456fa1 | 14142 | { |
db51cc60 | 14143 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14144 | { |
14145 | *obufp++ = '+'; | |
14146 | *obufp = '\0'; | |
14147 | } | |
05203043 | 14148 | else if (modrm.mod != 1 && disp != -disp) |
3d456fa1 JB |
14149 | { |
14150 | *obufp++ = '-'; | |
14151 | *obufp = '\0'; | |
14152 | disp = - (bfd_signed_vma) disp; | |
14153 | } | |
14154 | ||
db51cc60 L |
14155 | if (havedisp) |
14156 | print_displacement (scratchbuf, disp); | |
14157 | else | |
14158 | print_operand_value (scratchbuf, 1, disp); | |
3d456fa1 JB |
14159 | oappend (scratchbuf); |
14160 | } | |
252b5132 RH |
14161 | |
14162 | *obufp++ = close_char; | |
db6eb5be | 14163 | *obufp = '\0'; |
252b5132 RH |
14164 | } |
14165 | else if (intel_syntax) | |
db6eb5be | 14166 | { |
82c18208 | 14167 | if (modrm.mod != 0 || base == 5) |
db6eb5be | 14168 | { |
285ca992 | 14169 | if (!active_seg_prefix) |
252b5132 | 14170 | { |
d708bcba | 14171 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14172 | oappend (":"); |
14173 | } | |
52b15da3 | 14174 | print_operand_value (scratchbuf, 1, disp); |
db6eb5be AM |
14175 | oappend (scratchbuf); |
14176 | } | |
14177 | } | |
252b5132 | 14178 | } |
a23b33b3 JB |
14179 | else if (bytemode == v_bnd_mode |
14180 | || bytemode == v_bndmk_mode | |
14181 | || bytemode == bnd_mode | |
14182 | || bytemode == bnd_swap_mode) | |
14183 | { | |
14184 | oappend ("(bad)"); | |
14185 | return; | |
14186 | } | |
252b5132 | 14187 | else |
f16cd0d5 L |
14188 | { |
14189 | /* 16 bit address mode */ | |
14190 | used_prefixes |= prefixes & PREFIX_ADDR; | |
7967e09e | 14191 | switch (modrm.mod) |
252b5132 RH |
14192 | { |
14193 | case 0: | |
7967e09e | 14194 | if (modrm.rm == 6) |
252b5132 RH |
14195 | { |
14196 | disp = get16 (); | |
14197 | if ((disp & 0x8000) != 0) | |
14198 | disp -= 0x10000; | |
14199 | } | |
14200 | break; | |
14201 | case 1: | |
14202 | FETCH_DATA (the_info, codep + 1); | |
14203 | disp = *codep++; | |
14204 | if ((disp & 0x80) != 0) | |
14205 | disp -= 0x100; | |
65f3ed04 JB |
14206 | if (vex.evex && shift > 0) |
14207 | disp <<= shift; | |
252b5132 RH |
14208 | break; |
14209 | case 2: | |
14210 | disp = get16 (); | |
14211 | if ((disp & 0x8000) != 0) | |
14212 | disp -= 0x10000; | |
14213 | break; | |
14214 | } | |
14215 | ||
14216 | if (!intel_syntax) | |
7967e09e | 14217 | if (modrm.mod != 0 || modrm.rm == 6) |
db6eb5be | 14218 | { |
5d669648 | 14219 | print_displacement (scratchbuf, disp); |
db6eb5be AM |
14220 | oappend (scratchbuf); |
14221 | } | |
252b5132 | 14222 | |
7967e09e | 14223 | if (modrm.mod != 0 || modrm.rm != 6) |
252b5132 RH |
14224 | { |
14225 | *obufp++ = open_char; | |
db6eb5be | 14226 | *obufp = '\0'; |
7967e09e | 14227 | oappend (index16[modrm.rm]); |
5d669648 L |
14228 | if (intel_syntax |
14229 | && (disp || modrm.mod != 0 || modrm.rm == 6)) | |
3d456fa1 | 14230 | { |
5d669648 | 14231 | if ((bfd_signed_vma) disp >= 0) |
3d456fa1 JB |
14232 | { |
14233 | *obufp++ = '+'; | |
14234 | *obufp = '\0'; | |
14235 | } | |
7967e09e | 14236 | else if (modrm.mod != 1) |
3d456fa1 JB |
14237 | { |
14238 | *obufp++ = '-'; | |
14239 | *obufp = '\0'; | |
14240 | disp = - (bfd_signed_vma) disp; | |
14241 | } | |
14242 | ||
5d669648 | 14243 | print_displacement (scratchbuf, disp); |
3d456fa1 JB |
14244 | oappend (scratchbuf); |
14245 | } | |
14246 | ||
db6eb5be AM |
14247 | *obufp++ = close_char; |
14248 | *obufp = '\0'; | |
252b5132 | 14249 | } |
3d456fa1 JB |
14250 | else if (intel_syntax) |
14251 | { | |
285ca992 | 14252 | if (!active_seg_prefix) |
3d456fa1 JB |
14253 | { |
14254 | oappend (names_seg[ds_reg - es_reg]); | |
14255 | oappend (":"); | |
14256 | } | |
14257 | print_operand_value (scratchbuf, 1, disp & 0xffff); | |
14258 | oappend (scratchbuf); | |
14259 | } | |
252b5132 | 14260 | } |
43234a1e L |
14261 | if (vex.evex && vex.b |
14262 | && (bytemode == x_mode | |
90a915bf | 14263 | || bytemode == xmmq_mode |
43234a1e L |
14264 | || bytemode == evex_half_bcst_xmmq_mode)) |
14265 | { | |
90a915bf IT |
14266 | if (vex.w |
14267 | || bytemode == xmmq_mode | |
14268 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda IT |
14269 | { |
14270 | switch (vex.length) | |
14271 | { | |
14272 | case 128: | |
14273 | oappend ("{1to2}"); | |
14274 | break; | |
14275 | case 256: | |
14276 | oappend ("{1to4}"); | |
14277 | break; | |
14278 | case 512: | |
14279 | oappend ("{1to8}"); | |
14280 | break; | |
14281 | default: | |
14282 | abort (); | |
14283 | } | |
14284 | } | |
43234a1e | 14285 | else |
b28d1bda IT |
14286 | { |
14287 | switch (vex.length) | |
14288 | { | |
14289 | case 128: | |
14290 | oappend ("{1to4}"); | |
14291 | break; | |
14292 | case 256: | |
14293 | oappend ("{1to8}"); | |
14294 | break; | |
14295 | case 512: | |
14296 | oappend ("{1to16}"); | |
14297 | break; | |
14298 | default: | |
14299 | abort (); | |
14300 | } | |
14301 | } | |
43234a1e | 14302 | } |
252b5132 RH |
14303 | } |
14304 | ||
c0f3af97 | 14305 | static void |
8b3f93e7 | 14306 | OP_E (int bytemode, int sizeflag) |
c0f3af97 L |
14307 | { |
14308 | /* Skip mod/rm byte. */ | |
14309 | MODRM_CHECK; | |
14310 | codep++; | |
14311 | ||
14312 | if (modrm.mod == 3) | |
14313 | OP_E_register (bytemode, sizeflag); | |
14314 | else | |
c1e679ec | 14315 | OP_E_memory (bytemode, sizeflag); |
c0f3af97 L |
14316 | } |
14317 | ||
252b5132 | 14318 | static void |
26ca5450 | 14319 | OP_G (int bytemode, int sizeflag) |
252b5132 | 14320 | { |
52b15da3 | 14321 | int add = 0; |
c0a30a9f | 14322 | const char **names; |
161a04f6 L |
14323 | USED_REX (REX_R); |
14324 | if (rex & REX_R) | |
52b15da3 | 14325 | add += 8; |
252b5132 RH |
14326 | switch (bytemode) |
14327 | { | |
14328 | case b_mode: | |
52b15da3 JH |
14329 | USED_REX (0); |
14330 | if (rex) | |
7967e09e | 14331 | oappend (names8rex[modrm.reg + add]); |
52b15da3 | 14332 | else |
7967e09e | 14333 | oappend (names8[modrm.reg + add]); |
252b5132 RH |
14334 | break; |
14335 | case w_mode: | |
7967e09e | 14336 | oappend (names16[modrm.reg + add]); |
252b5132 RH |
14337 | break; |
14338 | case d_mode: | |
1ba585e8 IT |
14339 | case db_mode: |
14340 | case dw_mode: | |
7967e09e | 14341 | oappend (names32[modrm.reg + add]); |
52b15da3 JH |
14342 | break; |
14343 | case q_mode: | |
7967e09e | 14344 | oappend (names64[modrm.reg + add]); |
252b5132 | 14345 | break; |
7e8b059b | 14346 | case bnd_mode: |
0d96e4df L |
14347 | if (modrm.reg > 0x3) |
14348 | { | |
14349 | oappend ("(bad)"); | |
14350 | return; | |
14351 | } | |
7e8b059b L |
14352 | oappend (names_bnd[modrm.reg]); |
14353 | break; | |
252b5132 | 14354 | case v_mode: |
9306ca4a | 14355 | case dq_mode: |
42903f7f L |
14356 | case dqb_mode: |
14357 | case dqd_mode: | |
9306ca4a | 14358 | case dqw_mode: |
bc31405e | 14359 | case movsxd_mode: |
161a04f6 L |
14360 | USED_REX (REX_W); |
14361 | if (rex & REX_W) | |
7967e09e | 14362 | oappend (names64[modrm.reg + add]); |
252b5132 | 14363 | else |
f16cd0d5 | 14364 | { |
bc31405e L |
14365 | if ((sizeflag & DFLAG) |
14366 | || (bytemode != v_mode && bytemode != movsxd_mode)) | |
f16cd0d5 L |
14367 | oappend (names32[modrm.reg + add]); |
14368 | else | |
14369 | oappend (names16[modrm.reg + add]); | |
14370 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14371 | } | |
252b5132 | 14372 | break; |
c0a30a9f L |
14373 | case va_mode: |
14374 | names = (address_mode == mode_64bit | |
14375 | ? names64 : names32); | |
14376 | if (!(prefixes & PREFIX_ADDR)) | |
14377 | { | |
14378 | if (address_mode == mode_16bit) | |
14379 | names = names16; | |
14380 | } | |
14381 | else | |
14382 | { | |
14383 | /* Remove "addr16/addr32". */ | |
14384 | all_prefixes[last_addr_prefix] = 0; | |
14385 | names = (address_mode != mode_32bit | |
14386 | ? names32 : names16); | |
14387 | used_prefixes |= PREFIX_ADDR; | |
14388 | } | |
14389 | oappend (names[modrm.reg + add]); | |
14390 | break; | |
90700ea2 | 14391 | case m_mode: |
cb712a9e | 14392 | if (address_mode == mode_64bit) |
7967e09e | 14393 | oappend (names64[modrm.reg + add]); |
90700ea2 | 14394 | else |
7967e09e | 14395 | oappend (names32[modrm.reg + add]); |
90700ea2 | 14396 | break; |
1ba585e8 | 14397 | case mask_bd_mode: |
43234a1e | 14398 | case mask_mode: |
9889cbb1 L |
14399 | if ((modrm.reg + add) > 0x7) |
14400 | { | |
14401 | oappend ("(bad)"); | |
14402 | return; | |
14403 | } | |
43234a1e L |
14404 | oappend (names_mask[modrm.reg + add]); |
14405 | break; | |
252b5132 RH |
14406 | default: |
14407 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14408 | break; | |
14409 | } | |
14410 | } | |
14411 | ||
52b15da3 | 14412 | static bfd_vma |
26ca5450 | 14413 | get64 (void) |
52b15da3 | 14414 | { |
5dd0794d | 14415 | bfd_vma x; |
52b15da3 | 14416 | #ifdef BFD64 |
5dd0794d AM |
14417 | unsigned int a; |
14418 | unsigned int b; | |
14419 | ||
52b15da3 JH |
14420 | FETCH_DATA (the_info, codep + 8); |
14421 | a = *codep++ & 0xff; | |
14422 | a |= (*codep++ & 0xff) << 8; | |
14423 | a |= (*codep++ & 0xff) << 16; | |
070fe95d | 14424 | a |= (*codep++ & 0xffu) << 24; |
5dd0794d | 14425 | b = *codep++ & 0xff; |
52b15da3 JH |
14426 | b |= (*codep++ & 0xff) << 8; |
14427 | b |= (*codep++ & 0xff) << 16; | |
070fe95d | 14428 | b |= (*codep++ & 0xffu) << 24; |
52b15da3 JH |
14429 | x = a + ((bfd_vma) b << 32); |
14430 | #else | |
6608db57 | 14431 | abort (); |
5dd0794d | 14432 | x = 0; |
52b15da3 JH |
14433 | #endif |
14434 | return x; | |
14435 | } | |
14436 | ||
14437 | static bfd_signed_vma | |
26ca5450 | 14438 | get32 (void) |
252b5132 | 14439 | { |
52b15da3 | 14440 | bfd_signed_vma x = 0; |
252b5132 RH |
14441 | |
14442 | FETCH_DATA (the_info, codep + 4); | |
52b15da3 JH |
14443 | x = *codep++ & (bfd_signed_vma) 0xff; |
14444 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14445 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14446 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14447 | return x; | |
14448 | } | |
14449 | ||
14450 | static bfd_signed_vma | |
26ca5450 | 14451 | get32s (void) |
52b15da3 JH |
14452 | { |
14453 | bfd_signed_vma x = 0; | |
14454 | ||
14455 | FETCH_DATA (the_info, codep + 4); | |
14456 | x = *codep++ & (bfd_signed_vma) 0xff; | |
14457 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 8; | |
14458 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 16; | |
14459 | x |= (*codep++ & (bfd_signed_vma) 0xff) << 24; | |
14460 | ||
14461 | x = (x ^ ((bfd_signed_vma) 1 << 31)) - ((bfd_signed_vma) 1 << 31); | |
14462 | ||
252b5132 RH |
14463 | return x; |
14464 | } | |
14465 | ||
14466 | static int | |
26ca5450 | 14467 | get16 (void) |
252b5132 RH |
14468 | { |
14469 | int x = 0; | |
14470 | ||
14471 | FETCH_DATA (the_info, codep + 2); | |
14472 | x = *codep++ & 0xff; | |
14473 | x |= (*codep++ & 0xff) << 8; | |
14474 | return x; | |
14475 | } | |
14476 | ||
14477 | static void | |
26ca5450 | 14478 | set_op (bfd_vma op, int riprel) |
252b5132 RH |
14479 | { |
14480 | op_index[op_ad] = op_ad; | |
cb712a9e | 14481 | if (address_mode == mode_64bit) |
7081ff04 AJ |
14482 | { |
14483 | op_address[op_ad] = op; | |
14484 | op_riprel[op_ad] = riprel; | |
14485 | } | |
14486 | else | |
14487 | { | |
14488 | /* Mask to get a 32-bit address. */ | |
14489 | op_address[op_ad] = op & 0xffffffff; | |
14490 | op_riprel[op_ad] = riprel & 0xffffffff; | |
14491 | } | |
252b5132 RH |
14492 | } |
14493 | ||
14494 | static void | |
26ca5450 | 14495 | OP_REG (int code, int sizeflag) |
252b5132 | 14496 | { |
2da11e11 | 14497 | const char *s; |
9b60702d | 14498 | int add; |
de882298 RM |
14499 | |
14500 | switch (code) | |
14501 | { | |
14502 | case es_reg: case ss_reg: case cs_reg: | |
14503 | case ds_reg: case fs_reg: case gs_reg: | |
14504 | oappend (names_seg[code - es_reg]); | |
14505 | return; | |
14506 | } | |
14507 | ||
161a04f6 L |
14508 | USED_REX (REX_B); |
14509 | if (rex & REX_B) | |
52b15da3 | 14510 | add = 8; |
9b60702d L |
14511 | else |
14512 | add = 0; | |
52b15da3 JH |
14513 | |
14514 | switch (code) | |
14515 | { | |
52b15da3 JH |
14516 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
14517 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14518 | s = names16[code - ax_reg + add]; | |
14519 | break; | |
52b15da3 JH |
14520 | case al_reg: case ah_reg: case cl_reg: case ch_reg: |
14521 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
14522 | USED_REX (0); | |
14523 | if (rex) | |
14524 | s = names8rex[code - al_reg + add]; | |
14525 | else | |
14526 | s = names8[code - al_reg]; | |
14527 | break; | |
6439fc28 AM |
14528 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
14529 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
7bb15c6f | 14530 | if (address_mode == mode_64bit |
6c067bbb | 14531 | && ((sizeflag & DFLAG) || (rex & REX_W))) |
6439fc28 AM |
14532 | { |
14533 | s = names64[code - rAX_reg + add]; | |
14534 | break; | |
14535 | } | |
14536 | code += eAX_reg - rAX_reg; | |
6608db57 | 14537 | /* Fall through. */ |
52b15da3 JH |
14538 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
14539 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14540 | USED_REX (REX_W); |
14541 | if (rex & REX_W) | |
52b15da3 | 14542 | s = names64[code - eAX_reg + add]; |
52b15da3 | 14543 | else |
f16cd0d5 L |
14544 | { |
14545 | if (sizeflag & DFLAG) | |
14546 | s = names32[code - eAX_reg + add]; | |
14547 | else | |
14548 | s = names16[code - eAX_reg + add]; | |
14549 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14550 | } | |
52b15da3 | 14551 | break; |
52b15da3 JH |
14552 | default: |
14553 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14554 | break; | |
14555 | } | |
14556 | oappend (s); | |
14557 | } | |
14558 | ||
14559 | static void | |
26ca5450 | 14560 | OP_IMREG (int code, int sizeflag) |
52b15da3 JH |
14561 | { |
14562 | const char *s; | |
252b5132 RH |
14563 | |
14564 | switch (code) | |
14565 | { | |
14566 | case indir_dx_reg: | |
d708bcba | 14567 | if (intel_syntax) |
52fd6d94 | 14568 | s = "dx"; |
d708bcba | 14569 | else |
db6eb5be | 14570 | s = "(%dx)"; |
252b5132 RH |
14571 | break; |
14572 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: | |
14573 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
14574 | s = names16[code - ax_reg]; | |
14575 | break; | |
14576 | case es_reg: case ss_reg: case cs_reg: | |
14577 | case ds_reg: case fs_reg: case gs_reg: | |
14578 | s = names_seg[code - es_reg]; | |
14579 | break; | |
14580 | case al_reg: case ah_reg: case cl_reg: case ch_reg: | |
14581 | case dl_reg: case dh_reg: case bl_reg: case bh_reg: | |
52b15da3 JH |
14582 | USED_REX (0); |
14583 | if (rex) | |
14584 | s = names8rex[code - al_reg]; | |
14585 | else | |
14586 | s = names8[code - al_reg]; | |
252b5132 RH |
14587 | break; |
14588 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: | |
14589 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 L |
14590 | USED_REX (REX_W); |
14591 | if (rex & REX_W) | |
52b15da3 | 14592 | s = names64[code - eAX_reg]; |
252b5132 | 14593 | else |
f16cd0d5 L |
14594 | { |
14595 | if (sizeflag & DFLAG) | |
14596 | s = names32[code - eAX_reg]; | |
14597 | else | |
14598 | s = names16[code - eAX_reg]; | |
14599 | used_prefixes |= (prefixes & PREFIX_DATA); | |
14600 | } | |
252b5132 | 14601 | break; |
52fd6d94 | 14602 | case z_mode_ax_reg: |
161a04f6 | 14603 | if ((rex & REX_W) || (sizeflag & DFLAG)) |
52fd6d94 JB |
14604 | s = *names32; |
14605 | else | |
14606 | s = *names16; | |
161a04f6 | 14607 | if (!(rex & REX_W)) |
52fd6d94 JB |
14608 | used_prefixes |= (prefixes & PREFIX_DATA); |
14609 | break; | |
252b5132 RH |
14610 | default: |
14611 | s = INTERNAL_DISASSEMBLER_ERROR; | |
14612 | break; | |
14613 | } | |
14614 | oappend (s); | |
14615 | } | |
14616 | ||
14617 | static void | |
26ca5450 | 14618 | OP_I (int bytemode, int sizeflag) |
252b5132 | 14619 | { |
52b15da3 JH |
14620 | bfd_signed_vma op; |
14621 | bfd_signed_vma mask = -1; | |
252b5132 RH |
14622 | |
14623 | switch (bytemode) | |
14624 | { | |
14625 | case b_mode: | |
14626 | FETCH_DATA (the_info, codep + 1); | |
52b15da3 JH |
14627 | op = *codep++; |
14628 | mask = 0xff; | |
14629 | break; | |
252b5132 | 14630 | case v_mode: |
161a04f6 L |
14631 | USED_REX (REX_W); |
14632 | if (rex & REX_W) | |
52b15da3 | 14633 | op = get32s (); |
252b5132 | 14634 | else |
52b15da3 | 14635 | { |
f16cd0d5 L |
14636 | if (sizeflag & DFLAG) |
14637 | { | |
14638 | op = get32 (); | |
14639 | mask = 0xffffffff; | |
14640 | } | |
14641 | else | |
14642 | { | |
14643 | op = get16 (); | |
14644 | mask = 0xfffff; | |
14645 | } | |
14646 | used_prefixes |= (prefixes & PREFIX_DATA); | |
52b15da3 | 14647 | } |
252b5132 | 14648 | break; |
c1dc7af5 JB |
14649 | case d_mode: |
14650 | mask = 0xffffffff; | |
14651 | op = get32 (); | |
14652 | break; | |
252b5132 | 14653 | case w_mode: |
52b15da3 | 14654 | mask = 0xfffff; |
252b5132 RH |
14655 | op = get16 (); |
14656 | break; | |
9306ca4a JB |
14657 | case const_1_mode: |
14658 | if (intel_syntax) | |
6c067bbb | 14659 | oappend ("1"); |
9306ca4a | 14660 | return; |
252b5132 RH |
14661 | default: |
14662 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14663 | return; | |
14664 | } | |
14665 | ||
52b15da3 JH |
14666 | op &= mask; |
14667 | scratchbuf[0] = '$'; | |
d708bcba | 14668 | print_operand_value (scratchbuf + 1, 1, op); |
9ce09ba2 | 14669 | oappend_maybe_intel (scratchbuf); |
52b15da3 JH |
14670 | scratchbuf[0] = '\0'; |
14671 | } | |
14672 | ||
14673 | static void | |
26ca5450 | 14674 | OP_I64 (int bytemode, int sizeflag) |
52b15da3 | 14675 | { |
a280ab8e | 14676 | if (bytemode != v_mode || address_mode != mode_64bit || !(rex & REX_W)) |
6439fc28 AM |
14677 | { |
14678 | OP_I (bytemode, sizeflag); | |
14679 | return; | |
14680 | } | |
14681 | ||
a280ab8e | 14682 | USED_REX (REX_W); |
52b15da3 | 14683 | |
52b15da3 | 14684 | scratchbuf[0] = '$'; |
a280ab8e | 14685 | print_operand_value (scratchbuf + 1, 1, get64 ()); |
9ce09ba2 | 14686 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14687 | scratchbuf[0] = '\0'; |
14688 | } | |
14689 | ||
14690 | static void | |
26ca5450 | 14691 | OP_sI (int bytemode, int sizeflag) |
252b5132 | 14692 | { |
52b15da3 | 14693 | bfd_signed_vma op; |
252b5132 RH |
14694 | |
14695 | switch (bytemode) | |
14696 | { | |
14697 | case b_mode: | |
e3949f17 | 14698 | case b_T_mode: |
252b5132 RH |
14699 | FETCH_DATA (the_info, codep + 1); |
14700 | op = *codep++; | |
14701 | if ((op & 0x80) != 0) | |
14702 | op -= 0x100; | |
e3949f17 L |
14703 | if (bytemode == b_T_mode) |
14704 | { | |
14705 | if (address_mode != mode_64bit | |
7bb15c6f | 14706 | || !((sizeflag & DFLAG) || (rex & REX_W))) |
e3949f17 | 14707 | { |
6c067bbb RM |
14708 | /* The operand-size prefix is overridden by a REX prefix. */ |
14709 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
e3949f17 L |
14710 | op &= 0xffffffff; |
14711 | else | |
14712 | op &= 0xffff; | |
14713 | } | |
14714 | } | |
14715 | else | |
14716 | { | |
14717 | if (!(rex & REX_W)) | |
14718 | { | |
14719 | if (sizeflag & DFLAG) | |
14720 | op &= 0xffffffff; | |
14721 | else | |
14722 | op &= 0xffff; | |
14723 | } | |
14724 | } | |
252b5132 RH |
14725 | break; |
14726 | case v_mode: | |
7bb15c6f RM |
14727 | /* The operand-size prefix is overridden by a REX prefix. */ |
14728 | if ((sizeflag & DFLAG) || (rex & REX_W)) | |
52b15da3 | 14729 | op = get32s (); |
252b5132 | 14730 | else |
d9e3625e | 14731 | op = get16 (); |
252b5132 RH |
14732 | break; |
14733 | default: | |
14734 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14735 | return; | |
14736 | } | |
52b15da3 JH |
14737 | |
14738 | scratchbuf[0] = '$'; | |
14739 | print_operand_value (scratchbuf + 1, 1, op); | |
9ce09ba2 | 14740 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14741 | } |
14742 | ||
14743 | static void | |
26ca5450 | 14744 | OP_J (int bytemode, int sizeflag) |
252b5132 | 14745 | { |
52b15da3 | 14746 | bfd_vma disp; |
7081ff04 | 14747 | bfd_vma mask = -1; |
65ca155d | 14748 | bfd_vma segment = 0; |
252b5132 RH |
14749 | |
14750 | switch (bytemode) | |
14751 | { | |
14752 | case b_mode: | |
14753 | FETCH_DATA (the_info, codep + 1); | |
14754 | disp = *codep++; | |
14755 | if ((disp & 0x80) != 0) | |
14756 | disp -= 0x100; | |
14757 | break; | |
14758 | case v_mode: | |
d835a58b | 14759 | if (isa64 != intel64) |
376cd056 | 14760 | case dqw_mode: |
5db04b09 L |
14761 | USED_REX (REX_W); |
14762 | if ((sizeflag & DFLAG) | |
14763 | || (address_mode == mode_64bit | |
d835a58b | 14764 | && ((isa64 == intel64 && bytemode != dqw_mode) |
376cd056 | 14765 | || (rex & REX_W)))) |
52b15da3 | 14766 | disp = get32s (); |
252b5132 RH |
14767 | else |
14768 | { | |
14769 | disp = get16 (); | |
206717e8 L |
14770 | if ((disp & 0x8000) != 0) |
14771 | disp -= 0x10000; | |
65ca155d L |
14772 | /* In 16bit mode, address is wrapped around at 64k within |
14773 | the same segment. Otherwise, a data16 prefix on a jump | |
14774 | instruction means that the pc is masked to 16 bits after | |
14775 | the displacement is added! */ | |
14776 | mask = 0xffff; | |
14777 | if ((prefixes & PREFIX_DATA) == 0) | |
4fd7268a | 14778 | segment = ((start_pc + (codep - start_codep)) |
65ca155d | 14779 | & ~((bfd_vma) 0xffff)); |
252b5132 | 14780 | } |
5db04b09 | 14781 | if (address_mode != mode_64bit |
d835a58b | 14782 | || (isa64 != intel64 && !(rex & REX_W))) |
f16cd0d5 | 14783 | used_prefixes |= (prefixes & PREFIX_DATA); |
252b5132 RH |
14784 | break; |
14785 | default: | |
14786 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
14787 | return; | |
14788 | } | |
42d5f9c6 | 14789 | disp = ((start_pc + (codep - start_codep) + disp) & mask) | segment; |
52b15da3 JH |
14790 | set_op (disp, 0); |
14791 | print_operand_value (scratchbuf, 1, disp); | |
252b5132 RH |
14792 | oappend (scratchbuf); |
14793 | } | |
14794 | ||
252b5132 | 14795 | static void |
ed7841b3 | 14796 | OP_SEG (int bytemode, int sizeflag) |
252b5132 | 14797 | { |
ed7841b3 | 14798 | if (bytemode == w_mode) |
7967e09e | 14799 | oappend (names_seg[modrm.reg]); |
ed7841b3 | 14800 | else |
7967e09e | 14801 | OP_E (modrm.mod == 3 ? bytemode : w_mode, sizeflag); |
252b5132 RH |
14802 | } |
14803 | ||
14804 | static void | |
26ca5450 | 14805 | OP_DIR (int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 RH |
14806 | { |
14807 | int seg, offset; | |
14808 | ||
c608c12e | 14809 | if (sizeflag & DFLAG) |
252b5132 | 14810 | { |
c608c12e AM |
14811 | offset = get32 (); |
14812 | seg = get16 (); | |
252b5132 | 14813 | } |
c608c12e AM |
14814 | else |
14815 | { | |
14816 | offset = get16 (); | |
14817 | seg = get16 (); | |
14818 | } | |
7d421014 | 14819 | used_prefixes |= (prefixes & PREFIX_DATA); |
d708bcba | 14820 | if (intel_syntax) |
3f31e633 | 14821 | sprintf (scratchbuf, "0x%x:0x%x", seg, offset); |
d708bcba AM |
14822 | else |
14823 | sprintf (scratchbuf, "$0x%x,$0x%x", seg, offset); | |
c608c12e | 14824 | oappend (scratchbuf); |
252b5132 RH |
14825 | } |
14826 | ||
252b5132 | 14827 | static void |
3f31e633 | 14828 | OP_OFF (int bytemode, int sizeflag) |
252b5132 | 14829 | { |
52b15da3 | 14830 | bfd_vma off; |
252b5132 | 14831 | |
3f31e633 JB |
14832 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14833 | intel_operand_size (bytemode, sizeflag); | |
252b5132 RH |
14834 | append_seg (); |
14835 | ||
cb712a9e | 14836 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) |
252b5132 RH |
14837 | off = get32 (); |
14838 | else | |
14839 | off = get16 (); | |
14840 | ||
14841 | if (intel_syntax) | |
14842 | { | |
285ca992 | 14843 | if (!active_seg_prefix) |
252b5132 | 14844 | { |
d708bcba | 14845 | oappend (names_seg[ds_reg - es_reg]); |
252b5132 RH |
14846 | oappend (":"); |
14847 | } | |
14848 | } | |
52b15da3 JH |
14849 | print_operand_value (scratchbuf, 1, off); |
14850 | oappend (scratchbuf); | |
14851 | } | |
6439fc28 | 14852 | |
52b15da3 | 14853 | static void |
3f31e633 | 14854 | OP_OFF64 (int bytemode, int sizeflag) |
52b15da3 JH |
14855 | { |
14856 | bfd_vma off; | |
14857 | ||
539e75ad L |
14858 | if (address_mode != mode_64bit |
14859 | || (prefixes & PREFIX_ADDR)) | |
6439fc28 AM |
14860 | { |
14861 | OP_OFF (bytemode, sizeflag); | |
14862 | return; | |
14863 | } | |
14864 | ||
3f31e633 JB |
14865 | if (intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
14866 | intel_operand_size (bytemode, sizeflag); | |
52b15da3 JH |
14867 | append_seg (); |
14868 | ||
6608db57 | 14869 | off = get64 (); |
52b15da3 JH |
14870 | |
14871 | if (intel_syntax) | |
14872 | { | |
285ca992 | 14873 | if (!active_seg_prefix) |
52b15da3 | 14874 | { |
d708bcba | 14875 | oappend (names_seg[ds_reg - es_reg]); |
52b15da3 JH |
14876 | oappend (":"); |
14877 | } | |
14878 | } | |
14879 | print_operand_value (scratchbuf, 1, off); | |
252b5132 RH |
14880 | oappend (scratchbuf); |
14881 | } | |
14882 | ||
14883 | static void | |
26ca5450 | 14884 | ptr_reg (int code, int sizeflag) |
252b5132 | 14885 | { |
2da11e11 | 14886 | const char *s; |
d708bcba | 14887 | |
1d9f512f | 14888 | *obufp++ = open_char; |
20f0a1fc | 14889 | used_prefixes |= (prefixes & PREFIX_ADDR); |
cb712a9e | 14890 | if (address_mode == mode_64bit) |
c1a64871 JH |
14891 | { |
14892 | if (!(sizeflag & AFLAG)) | |
db6eb5be | 14893 | s = names32[code - eAX_reg]; |
c1a64871 | 14894 | else |
db6eb5be | 14895 | s = names64[code - eAX_reg]; |
c1a64871 | 14896 | } |
52b15da3 | 14897 | else if (sizeflag & AFLAG) |
252b5132 RH |
14898 | s = names32[code - eAX_reg]; |
14899 | else | |
14900 | s = names16[code - eAX_reg]; | |
14901 | oappend (s); | |
1d9f512f AM |
14902 | *obufp++ = close_char; |
14903 | *obufp = 0; | |
252b5132 RH |
14904 | } |
14905 | ||
14906 | static void | |
26ca5450 | 14907 | OP_ESreg (int code, int sizeflag) |
252b5132 | 14908 | { |
9306ca4a | 14909 | if (intel_syntax) |
52fd6d94 JB |
14910 | { |
14911 | switch (codep[-1]) | |
14912 | { | |
14913 | case 0x6d: /* insw/insl */ | |
14914 | intel_operand_size (z_mode, sizeflag); | |
14915 | break; | |
14916 | case 0xa5: /* movsw/movsl/movsq */ | |
14917 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14918 | case 0xab: /* stosw/stosl */ | |
14919 | case 0xaf: /* scasw/scasl */ | |
14920 | intel_operand_size (v_mode, sizeflag); | |
14921 | break; | |
14922 | default: | |
14923 | intel_operand_size (b_mode, sizeflag); | |
14924 | } | |
14925 | } | |
9ce09ba2 | 14926 | oappend_maybe_intel ("%es:"); |
252b5132 RH |
14927 | ptr_reg (code, sizeflag); |
14928 | } | |
14929 | ||
14930 | static void | |
26ca5450 | 14931 | OP_DSreg (int code, int sizeflag) |
252b5132 | 14932 | { |
9306ca4a | 14933 | if (intel_syntax) |
52fd6d94 JB |
14934 | { |
14935 | switch (codep[-1]) | |
14936 | { | |
14937 | case 0x6f: /* outsw/outsl */ | |
14938 | intel_operand_size (z_mode, sizeflag); | |
14939 | break; | |
14940 | case 0xa5: /* movsw/movsl/movsq */ | |
14941 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
14942 | case 0xad: /* lodsw/lodsl/lodsq */ | |
14943 | intel_operand_size (v_mode, sizeflag); | |
14944 | break; | |
14945 | default: | |
14946 | intel_operand_size (b_mode, sizeflag); | |
14947 | } | |
14948 | } | |
285ca992 L |
14949 | /* Set active_seg_prefix to PREFIX_DS if it is unset so that the |
14950 | default segment register DS is printed. */ | |
14951 | if (!active_seg_prefix) | |
14952 | active_seg_prefix = PREFIX_DS; | |
6608db57 | 14953 | append_seg (); |
252b5132 RH |
14954 | ptr_reg (code, sizeflag); |
14955 | } | |
14956 | ||
252b5132 | 14957 | static void |
26ca5450 | 14958 | OP_C (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14959 | { |
9b60702d | 14960 | int add; |
161a04f6 | 14961 | if (rex & REX_R) |
c4a530c5 | 14962 | { |
161a04f6 | 14963 | USED_REX (REX_R); |
c4a530c5 JB |
14964 | add = 8; |
14965 | } | |
cb712a9e | 14966 | else if (address_mode != mode_64bit && (prefixes & PREFIX_LOCK)) |
c4a530c5 | 14967 | { |
f16cd0d5 | 14968 | all_prefixes[last_lock_prefix] = 0; |
c4a530c5 JB |
14969 | used_prefixes |= PREFIX_LOCK; |
14970 | add = 8; | |
14971 | } | |
9b60702d L |
14972 | else |
14973 | add = 0; | |
7967e09e | 14974 | sprintf (scratchbuf, "%%cr%d", modrm.reg + add); |
9ce09ba2 | 14975 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14976 | } |
14977 | ||
252b5132 | 14978 | static void |
26ca5450 | 14979 | OP_D (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14980 | { |
9b60702d | 14981 | int add; |
161a04f6 L |
14982 | USED_REX (REX_R); |
14983 | if (rex & REX_R) | |
52b15da3 | 14984 | add = 8; |
9b60702d L |
14985 | else |
14986 | add = 0; | |
d708bcba | 14987 | if (intel_syntax) |
7967e09e | 14988 | sprintf (scratchbuf, "db%d", modrm.reg + add); |
d708bcba | 14989 | else |
7967e09e | 14990 | sprintf (scratchbuf, "%%db%d", modrm.reg + add); |
252b5132 RH |
14991 | oappend (scratchbuf); |
14992 | } | |
14993 | ||
252b5132 | 14994 | static void |
26ca5450 | 14995 | OP_T (int dummy ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 14996 | { |
7967e09e | 14997 | sprintf (scratchbuf, "%%tr%d", modrm.reg); |
9ce09ba2 | 14998 | oappend_maybe_intel (scratchbuf); |
252b5132 RH |
14999 | } |
15000 | ||
15001 | static void | |
6f74c397 | 15002 | OP_R (int bytemode, int sizeflag) |
252b5132 | 15003 | { |
68f34464 L |
15004 | /* Skip mod/rm byte. */ |
15005 | MODRM_CHECK; | |
15006 | codep++; | |
15007 | OP_E_register (bytemode, sizeflag); | |
252b5132 RH |
15008 | } |
15009 | ||
15010 | static void | |
26ca5450 | 15011 | OP_MMX (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 | 15012 | { |
b9733481 L |
15013 | int reg = modrm.reg; |
15014 | const char **names; | |
15015 | ||
041bd2e0 JH |
15016 | used_prefixes |= (prefixes & PREFIX_DATA); |
15017 | if (prefixes & PREFIX_DATA) | |
20f0a1fc | 15018 | { |
b9733481 | 15019 | names = names_xmm; |
161a04f6 L |
15020 | USED_REX (REX_R); |
15021 | if (rex & REX_R) | |
b9733481 | 15022 | reg += 8; |
20f0a1fc | 15023 | } |
041bd2e0 | 15024 | else |
b9733481 L |
15025 | names = names_mm; |
15026 | oappend (names[reg]); | |
252b5132 RH |
15027 | } |
15028 | ||
c608c12e | 15029 | static void |
c0f3af97 | 15030 | OP_XMM (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e | 15031 | { |
b9733481 L |
15032 | int reg = modrm.reg; |
15033 | const char **names; | |
15034 | ||
161a04f6 L |
15035 | USED_REX (REX_R); |
15036 | if (rex & REX_R) | |
b9733481 | 15037 | reg += 8; |
43234a1e L |
15038 | if (vex.evex) |
15039 | { | |
15040 | if (!vex.r) | |
15041 | reg += 16; | |
15042 | } | |
15043 | ||
539f890d L |
15044 | if (need_vex |
15045 | && bytemode != xmm_mode | |
43234a1e L |
15046 | && bytemode != xmmq_mode |
15047 | && bytemode != evex_half_bcst_xmmq_mode | |
15048 | && bytemode != ymm_mode | |
539f890d | 15049 | && bytemode != scalar_mode) |
c0f3af97 L |
15050 | { |
15051 | switch (vex.length) | |
15052 | { | |
15053 | case 128: | |
b9733481 | 15054 | names = names_xmm; |
c0f3af97 L |
15055 | break; |
15056 | case 256: | |
5fc35d96 IT |
15057 | if (vex.w |
15058 | || (bytemode != vex_vsib_q_w_dq_mode | |
15059 | && bytemode != vex_vsib_q_w_d_mode)) | |
6c30d220 L |
15060 | names = names_ymm; |
15061 | else | |
15062 | names = names_xmm; | |
c0f3af97 | 15063 | break; |
43234a1e L |
15064 | case 512: |
15065 | names = names_zmm; | |
15066 | break; | |
c0f3af97 L |
15067 | default: |
15068 | abort (); | |
15069 | } | |
15070 | } | |
43234a1e L |
15071 | else if (bytemode == xmmq_mode |
15072 | || bytemode == evex_half_bcst_xmmq_mode) | |
15073 | { | |
15074 | switch (vex.length) | |
15075 | { | |
15076 | case 128: | |
15077 | case 256: | |
15078 | names = names_xmm; | |
15079 | break; | |
15080 | case 512: | |
15081 | names = names_ymm; | |
15082 | break; | |
15083 | default: | |
15084 | abort (); | |
15085 | } | |
15086 | } | |
15087 | else if (bytemode == ymm_mode) | |
15088 | names = names_ymm; | |
c0f3af97 | 15089 | else |
b9733481 L |
15090 | names = names_xmm; |
15091 | oappend (names[reg]); | |
c608c12e AM |
15092 | } |
15093 | ||
252b5132 | 15094 | static void |
26ca5450 | 15095 | OP_EM (int bytemode, int sizeflag) |
252b5132 | 15096 | { |
b9733481 L |
15097 | int reg; |
15098 | const char **names; | |
15099 | ||
7967e09e | 15100 | if (modrm.mod != 3) |
252b5132 | 15101 | { |
b6169b20 L |
15102 | if (intel_syntax |
15103 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
9306ca4a JB |
15104 | { |
15105 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15106 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15107 | } |
252b5132 RH |
15108 | OP_E (bytemode, sizeflag); |
15109 | return; | |
15110 | } | |
15111 | ||
b6169b20 L |
15112 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
15113 | swap_operand (); | |
15114 | ||
6608db57 | 15115 | /* Skip mod/rm byte. */ |
4bba6815 | 15116 | MODRM_CHECK; |
252b5132 | 15117 | codep++; |
041bd2e0 | 15118 | used_prefixes |= (prefixes & PREFIX_DATA); |
b9733481 | 15119 | reg = modrm.rm; |
041bd2e0 | 15120 | if (prefixes & PREFIX_DATA) |
20f0a1fc | 15121 | { |
b9733481 | 15122 | names = names_xmm; |
161a04f6 L |
15123 | USED_REX (REX_B); |
15124 | if (rex & REX_B) | |
b9733481 | 15125 | reg += 8; |
20f0a1fc | 15126 | } |
041bd2e0 | 15127 | else |
b9733481 L |
15128 | names = names_mm; |
15129 | oappend (names[reg]); | |
252b5132 RH |
15130 | } |
15131 | ||
246c51aa L |
15132 | /* cvt* are the only instructions in sse2 which have |
15133 | both SSE and MMX operands and also have 0x66 prefix | |
15134 | in their opcode. 0x66 was originally used to differentiate | |
15135 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 MM |
15136 | cvt* separately using OP_EMC and OP_MXC */ |
15137 | static void | |
15138 | OP_EMC (int bytemode, int sizeflag) | |
15139 | { | |
7967e09e | 15140 | if (modrm.mod != 3) |
4d9567e0 MM |
15141 | { |
15142 | if (intel_syntax && bytemode == v_mode) | |
15143 | { | |
15144 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
15145 | used_prefixes |= (prefixes & PREFIX_DATA); | |
6c067bbb | 15146 | } |
4d9567e0 MM |
15147 | OP_E (bytemode, sizeflag); |
15148 | return; | |
15149 | } | |
246c51aa | 15150 | |
4d9567e0 MM |
15151 | /* Skip mod/rm byte. */ |
15152 | MODRM_CHECK; | |
15153 | codep++; | |
15154 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15155 | oappend (names_mm[modrm.rm]); |
4d9567e0 MM |
15156 | } |
15157 | ||
15158 | static void | |
15159 | OP_MXC (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15160 | { | |
15161 | used_prefixes |= (prefixes & PREFIX_DATA); | |
b9733481 | 15162 | oappend (names_mm[modrm.reg]); |
4d9567e0 MM |
15163 | } |
15164 | ||
c608c12e | 15165 | static void |
26ca5450 | 15166 | OP_EX (int bytemode, int sizeflag) |
c608c12e | 15167 | { |
b9733481 L |
15168 | int reg; |
15169 | const char **names; | |
d6f574e0 L |
15170 | |
15171 | /* Skip mod/rm byte. */ | |
15172 | MODRM_CHECK; | |
15173 | codep++; | |
15174 | ||
7967e09e | 15175 | if (modrm.mod != 3) |
c608c12e | 15176 | { |
c1e679ec | 15177 | OP_E_memory (bytemode, sizeflag); |
c608c12e AM |
15178 | return; |
15179 | } | |
d6f574e0 | 15180 | |
b9733481 | 15181 | reg = modrm.rm; |
161a04f6 L |
15182 | USED_REX (REX_B); |
15183 | if (rex & REX_B) | |
b9733481 | 15184 | reg += 8; |
43234a1e L |
15185 | if (vex.evex) |
15186 | { | |
15187 | USED_REX (REX_X); | |
15188 | if ((rex & REX_X)) | |
15189 | reg += 16; | |
15190 | } | |
c608c12e | 15191 | |
b6169b20 | 15192 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 L |
15193 | && (bytemode == x_swap_mode |
15194 | || bytemode == d_swap_mode | |
7bb15c6f | 15195 | || bytemode == d_scalar_swap_mode |
539f890d L |
15196 | || bytemode == q_swap_mode |
15197 | || bytemode == q_scalar_swap_mode)) | |
b6169b20 L |
15198 | swap_operand (); |
15199 | ||
c0f3af97 L |
15200 | if (need_vex |
15201 | && bytemode != xmm_mode | |
6c30d220 L |
15202 | && bytemode != xmmdw_mode |
15203 | && bytemode != xmmqd_mode | |
15204 | && bytemode != xmm_mb_mode | |
15205 | && bytemode != xmm_mw_mode | |
15206 | && bytemode != xmm_md_mode | |
15207 | && bytemode != xmm_mq_mode | |
539f890d | 15208 | && bytemode != xmmq_mode |
43234a1e L |
15209 | && bytemode != evex_half_bcst_xmmq_mode |
15210 | && bytemode != ymm_mode | |
7bb15c6f | 15211 | && bytemode != d_scalar_swap_mode |
1c480963 L |
15212 | && bytemode != q_scalar_swap_mode |
15213 | && bytemode != vex_scalar_w_dq_mode) | |
c0f3af97 L |
15214 | { |
15215 | switch (vex.length) | |
15216 | { | |
15217 | case 128: | |
b9733481 | 15218 | names = names_xmm; |
c0f3af97 L |
15219 | break; |
15220 | case 256: | |
b9733481 | 15221 | names = names_ymm; |
c0f3af97 | 15222 | break; |
43234a1e L |
15223 | case 512: |
15224 | names = names_zmm; | |
15225 | break; | |
c0f3af97 L |
15226 | default: |
15227 | abort (); | |
15228 | } | |
15229 | } | |
43234a1e L |
15230 | else if (bytemode == xmmq_mode |
15231 | || bytemode == evex_half_bcst_xmmq_mode) | |
15232 | { | |
15233 | switch (vex.length) | |
15234 | { | |
15235 | case 128: | |
15236 | case 256: | |
15237 | names = names_xmm; | |
15238 | break; | |
15239 | case 512: | |
15240 | names = names_ymm; | |
15241 | break; | |
15242 | default: | |
15243 | abort (); | |
15244 | } | |
15245 | } | |
15246 | else if (bytemode == ymm_mode) | |
15247 | names = names_ymm; | |
c0f3af97 | 15248 | else |
b9733481 L |
15249 | names = names_xmm; |
15250 | oappend (names[reg]); | |
c608c12e AM |
15251 | } |
15252 | ||
252b5132 | 15253 | static void |
26ca5450 | 15254 | OP_MS (int bytemode, int sizeflag) |
252b5132 | 15255 | { |
7967e09e | 15256 | if (modrm.mod == 3) |
2da11e11 AM |
15257 | OP_EM (bytemode, sizeflag); |
15258 | else | |
6608db57 | 15259 | BadOp (); |
252b5132 RH |
15260 | } |
15261 | ||
992aaec9 | 15262 | static void |
26ca5450 | 15263 | OP_XS (int bytemode, int sizeflag) |
992aaec9 | 15264 | { |
7967e09e | 15265 | if (modrm.mod == 3) |
992aaec9 AM |
15266 | OP_EX (bytemode, sizeflag); |
15267 | else | |
6608db57 | 15268 | BadOp (); |
992aaec9 AM |
15269 | } |
15270 | ||
cc0ec051 AM |
15271 | static void |
15272 | OP_M (int bytemode, int sizeflag) | |
15273 | { | |
7967e09e | 15274 | if (modrm.mod == 3) |
75413a22 L |
15275 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
15276 | BadOp (); | |
cc0ec051 AM |
15277 | else |
15278 | OP_E (bytemode, sizeflag); | |
15279 | } | |
15280 | ||
15281 | static void | |
15282 | OP_0f07 (int bytemode, int sizeflag) | |
15283 | { | |
7967e09e | 15284 | if (modrm.mod != 3 || modrm.rm != 0) |
cc0ec051 AM |
15285 | BadOp (); |
15286 | else | |
15287 | OP_E (bytemode, sizeflag); | |
15288 | } | |
15289 | ||
46e883c5 | 15290 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 15291 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 15292 | |
cc0ec051 | 15293 | static void |
46e883c5 | 15294 | NOP_Fixup1 (int bytemode, int sizeflag) |
cc0ec051 | 15295 | { |
8b38ad71 L |
15296 | if ((prefixes & PREFIX_DATA) != 0 |
15297 | || (rex != 0 | |
15298 | && rex != 0x48 | |
15299 | && address_mode == mode_64bit)) | |
46e883c5 L |
15300 | OP_REG (bytemode, sizeflag); |
15301 | else | |
15302 | strcpy (obuf, "nop"); | |
15303 | } | |
15304 | ||
15305 | static void | |
15306 | NOP_Fixup2 (int bytemode, int sizeflag) | |
15307 | { | |
8b38ad71 L |
15308 | if ((prefixes & PREFIX_DATA) != 0 |
15309 | || (rex != 0 | |
15310 | && rex != 0x48 | |
15311 | && address_mode == mode_64bit)) | |
46e883c5 | 15312 | OP_IMREG (bytemode, sizeflag); |
cc0ec051 AM |
15313 | } |
15314 | ||
84037f8c | 15315 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
15316 | /* 00 */ NULL, NULL, NULL, NULL, |
15317 | /* 04 */ NULL, NULL, NULL, NULL, | |
15318 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15319 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
15320 | /* 10 */ NULL, NULL, NULL, NULL, |
15321 | /* 14 */ NULL, NULL, NULL, NULL, | |
15322 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 15323 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
15324 | /* 20 */ NULL, NULL, NULL, NULL, |
15325 | /* 24 */ NULL, NULL, NULL, NULL, | |
15326 | /* 28 */ NULL, NULL, NULL, NULL, | |
15327 | /* 2C */ NULL, NULL, NULL, NULL, | |
15328 | /* 30 */ NULL, NULL, NULL, NULL, | |
15329 | /* 34 */ NULL, NULL, NULL, NULL, | |
15330 | /* 38 */ NULL, NULL, NULL, NULL, | |
15331 | /* 3C */ NULL, NULL, NULL, NULL, | |
15332 | /* 40 */ NULL, NULL, NULL, NULL, | |
15333 | /* 44 */ NULL, NULL, NULL, NULL, | |
15334 | /* 48 */ NULL, NULL, NULL, NULL, | |
15335 | /* 4C */ NULL, NULL, NULL, NULL, | |
15336 | /* 50 */ NULL, NULL, NULL, NULL, | |
15337 | /* 54 */ NULL, NULL, NULL, NULL, | |
15338 | /* 58 */ NULL, NULL, NULL, NULL, | |
15339 | /* 5C */ NULL, NULL, NULL, NULL, | |
15340 | /* 60 */ NULL, NULL, NULL, NULL, | |
15341 | /* 64 */ NULL, NULL, NULL, NULL, | |
15342 | /* 68 */ NULL, NULL, NULL, NULL, | |
15343 | /* 6C */ NULL, NULL, NULL, NULL, | |
15344 | /* 70 */ NULL, NULL, NULL, NULL, | |
15345 | /* 74 */ NULL, NULL, NULL, NULL, | |
15346 | /* 78 */ NULL, NULL, NULL, NULL, | |
15347 | /* 7C */ NULL, NULL, NULL, NULL, | |
15348 | /* 80 */ NULL, NULL, NULL, NULL, | |
15349 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
15350 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
15351 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
15352 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
15353 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
15354 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
15355 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
15356 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
15357 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
15358 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
15359 | /* AC */ NULL, NULL, "pfacc", NULL, | |
15360 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 15361 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 15362 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
15363 | /* BC */ NULL, NULL, NULL, "pavgusb", |
15364 | /* C0 */ NULL, NULL, NULL, NULL, | |
15365 | /* C4 */ NULL, NULL, NULL, NULL, | |
15366 | /* C8 */ NULL, NULL, NULL, NULL, | |
15367 | /* CC */ NULL, NULL, NULL, NULL, | |
15368 | /* D0 */ NULL, NULL, NULL, NULL, | |
15369 | /* D4 */ NULL, NULL, NULL, NULL, | |
15370 | /* D8 */ NULL, NULL, NULL, NULL, | |
15371 | /* DC */ NULL, NULL, NULL, NULL, | |
15372 | /* E0 */ NULL, NULL, NULL, NULL, | |
15373 | /* E4 */ NULL, NULL, NULL, NULL, | |
15374 | /* E8 */ NULL, NULL, NULL, NULL, | |
15375 | /* EC */ NULL, NULL, NULL, NULL, | |
15376 | /* F0 */ NULL, NULL, NULL, NULL, | |
15377 | /* F4 */ NULL, NULL, NULL, NULL, | |
15378 | /* F8 */ NULL, NULL, NULL, NULL, | |
15379 | /* FC */ NULL, NULL, NULL, NULL, | |
15380 | }; | |
15381 | ||
15382 | static void | |
26ca5450 | 15383 | OP_3DNowSuffix (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
252b5132 RH |
15384 | { |
15385 | const char *mnemonic; | |
15386 | ||
15387 | FETCH_DATA (the_info, codep + 1); | |
15388 | /* AMD 3DNow! instructions are specified by an opcode suffix in the | |
15389 | place where an 8-bit immediate would normally go. ie. the last | |
15390 | byte of the instruction. */ | |
ea397f5b | 15391 | obufp = mnemonicendp; |
c608c12e | 15392 | mnemonic = Suffix3DNow[*codep++ & 0xff]; |
252b5132 | 15393 | if (mnemonic) |
2da11e11 | 15394 | oappend (mnemonic); |
252b5132 RH |
15395 | else |
15396 | { | |
15397 | /* Since a variable sized modrm/sib chunk is between the start | |
15398 | of the opcode (0x0f0f) and the opcode suffix, we need to do | |
15399 | all the modrm processing first, and don't know until now that | |
15400 | we have a bad opcode. This necessitates some cleaning up. */ | |
ce518a5f L |
15401 | op_out[0][0] = '\0'; |
15402 | op_out[1][0] = '\0'; | |
6608db57 | 15403 | BadOp (); |
252b5132 | 15404 | } |
ea397f5b | 15405 | mnemonicendp = obufp; |
252b5132 | 15406 | } |
c608c12e | 15407 | |
ea397f5b L |
15408 | static struct op simd_cmp_op[] = |
15409 | { | |
15410 | { STRING_COMMA_LEN ("eq") }, | |
15411 | { STRING_COMMA_LEN ("lt") }, | |
15412 | { STRING_COMMA_LEN ("le") }, | |
15413 | { STRING_COMMA_LEN ("unord") }, | |
15414 | { STRING_COMMA_LEN ("neq") }, | |
15415 | { STRING_COMMA_LEN ("nlt") }, | |
15416 | { STRING_COMMA_LEN ("nle") }, | |
15417 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
15418 | }; |
15419 | ||
15420 | static void | |
ad19981d | 15421 | CMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) |
c608c12e AM |
15422 | { |
15423 | unsigned int cmp_type; | |
15424 | ||
15425 | FETCH_DATA (the_info, codep + 1); | |
15426 | cmp_type = *codep++ & 0xff; | |
c0f3af97 | 15427 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 15428 | { |
ad19981d | 15429 | char suffix [3]; |
ea397f5b | 15430 | char *p = mnemonicendp - 2; |
ad19981d L |
15431 | suffix[0] = p[0]; |
15432 | suffix[1] = p[1]; | |
15433 | suffix[2] = '\0'; | |
ea397f5b L |
15434 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
15435 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
c608c12e AM |
15436 | } |
15437 | else | |
15438 | { | |
ad19981d L |
15439 | /* We have a reserved extension byte. Output it directly. */ |
15440 | scratchbuf[0] = '$'; | |
15441 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 15442 | oappend_maybe_intel (scratchbuf); |
ad19981d | 15443 | scratchbuf[0] = '\0'; |
c608c12e AM |
15444 | } |
15445 | } | |
15446 | ||
9916071f | 15447 | static void |
7abb8d81 | 15448 | OP_Mwait (int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 15449 | { |
7abb8d81 | 15450 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
b844680a L |
15451 | if (!intel_syntax) |
15452 | { | |
081e283f JB |
15453 | strcpy (op_out[0], names32[0]); |
15454 | strcpy (op_out[1], names32[1]); | |
7abb8d81 | 15455 | if (bytemode == eBX_reg) |
081e283f | 15456 | strcpy (op_out[2], names32[3]); |
b844680a L |
15457 | two_source_ops = 1; |
15458 | } | |
15459 | /* Skip mod/rm byte. */ | |
15460 | MODRM_CHECK; | |
15461 | codep++; | |
15462 | } | |
15463 | ||
15464 | static void | |
15465 | OP_Monitor (int bytemode ATTRIBUTE_UNUSED, | |
15466 | int sizeflag ATTRIBUTE_UNUSED) | |
ca164297 | 15467 | { |
081e283f | 15468 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
b844680a | 15469 | if (!intel_syntax) |
ca164297 | 15470 | { |
cb712a9e L |
15471 | const char **names = (address_mode == mode_64bit |
15472 | ? names64 : names32); | |
1d9f512f | 15473 | |
081e283f | 15474 | if (prefixes & PREFIX_ADDR) |
ca164297 | 15475 | { |
b844680a | 15476 | /* Remove "addr16/addr32". */ |
f16cd0d5 | 15477 | all_prefixes[last_addr_prefix] = 0; |
081e283f JB |
15478 | names = (address_mode != mode_32bit |
15479 | ? names32 : names16); | |
b844680a | 15480 | used_prefixes |= PREFIX_ADDR; |
ca164297 | 15481 | } |
081e283f JB |
15482 | else if (address_mode == mode_16bit) |
15483 | names = names16; | |
15484 | strcpy (op_out[0], names[0]); | |
15485 | strcpy (op_out[1], names32[1]); | |
15486 | strcpy (op_out[2], names32[2]); | |
b844680a | 15487 | two_source_ops = 1; |
ca164297 | 15488 | } |
b844680a L |
15489 | /* Skip mod/rm byte. */ |
15490 | MODRM_CHECK; | |
15491 | codep++; | |
30123838 JB |
15492 | } |
15493 | ||
6608db57 KH |
15494 | static void |
15495 | BadOp (void) | |
2da11e11 | 15496 | { |
6608db57 KH |
15497 | /* Throw away prefixes and 1st. opcode byte. */ |
15498 | codep = insn_codep + 1; | |
2da11e11 AM |
15499 | oappend ("(bad)"); |
15500 | } | |
4cc91dba | 15501 | |
35c52694 L |
15502 | static void |
15503 | REP_Fixup (int bytemode, int sizeflag) | |
15504 | { | |
15505 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
15506 | lods and stos. */ | |
35c52694 | 15507 | if (prefixes & PREFIX_REPZ) |
f16cd0d5 | 15508 | all_prefixes[last_repz_prefix] = REP_PREFIX; |
35c52694 L |
15509 | |
15510 | switch (bytemode) | |
15511 | { | |
15512 | case al_reg: | |
15513 | case eAX_reg: | |
15514 | case indir_dx_reg: | |
15515 | OP_IMREG (bytemode, sizeflag); | |
15516 | break; | |
15517 | case eDI_reg: | |
15518 | OP_ESreg (bytemode, sizeflag); | |
15519 | break; | |
15520 | case eSI_reg: | |
15521 | OP_DSreg (bytemode, sizeflag); | |
15522 | break; | |
15523 | default: | |
15524 | abort (); | |
15525 | break; | |
15526 | } | |
15527 | } | |
f5804c90 | 15528 | |
d835a58b JB |
15529 | static void |
15530 | SEP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15531 | { | |
15532 | if ( isa64 != amd64 ) | |
15533 | return; | |
15534 | ||
15535 | obufp = obuf; | |
15536 | BadOp (); | |
15537 | mnemonicendp = obufp; | |
15538 | ++codep; | |
15539 | } | |
15540 | ||
7e8b059b L |
15541 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
15542 | "bnd". */ | |
15543 | ||
15544 | static void | |
15545 | BND_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
15546 | { | |
15547 | if (prefixes & PREFIX_REPNZ) | |
15548 | all_prefixes[last_repnz_prefix] = BND_PREFIX; | |
15549 | } | |
15550 | ||
04ef582a L |
15551 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
15552 | "notrack". */ | |
15553 | ||
15554 | static void | |
15555 | NOTRACK_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
15556 | int sizeflag ATTRIBUTE_UNUSED) | |
15557 | { | |
9fef80d6 | 15558 | if (active_seg_prefix == PREFIX_DS |
04ef582a L |
15559 | && (address_mode != mode_64bit || last_data_prefix < 0)) |
15560 | { | |
4e9ac44a | 15561 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 15562 | NB: DATA prefix is unsupported for Intel64. */ |
04ef582a L |
15563 | active_seg_prefix = 0; |
15564 | all_prefixes[last_seg_prefix] = NOTRACK_PREFIX; | |
15565 | } | |
15566 | } | |
15567 | ||
42164a71 L |
15568 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as |
15569 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. | |
15570 | */ | |
15571 | ||
15572 | static void | |
15573 | HLE_Fixup1 (int bytemode, int sizeflag) | |
15574 | { | |
15575 | if (modrm.mod != 3 | |
15576 | && (prefixes & PREFIX_LOCK) != 0) | |
15577 | { | |
15578 | if (prefixes & PREFIX_REPZ) | |
15579 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15580 | if (prefixes & PREFIX_REPNZ) | |
15581 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15582 | } | |
15583 | ||
15584 | OP_E (bytemode, sizeflag); | |
15585 | } | |
15586 | ||
15587 | /* Similar to OP_E. But the 0xf2/0xf3 prefixes should be displayed as | |
15588 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. | |
15589 | */ | |
15590 | ||
15591 | static void | |
15592 | HLE_Fixup2 (int bytemode, int sizeflag) | |
15593 | { | |
15594 | if (modrm.mod != 3) | |
15595 | { | |
15596 | if (prefixes & PREFIX_REPZ) | |
15597 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15598 | if (prefixes & PREFIX_REPNZ) | |
15599 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15600 | } | |
15601 | ||
15602 | OP_E (bytemode, sizeflag); | |
15603 | } | |
15604 | ||
15605 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
15606 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
15607 | ||
15608 | static void | |
15609 | HLE_Fixup3 (int bytemode, int sizeflag) | |
15610 | { | |
15611 | if (modrm.mod != 3 | |
15612 | && last_repz_prefix > last_repnz_prefix | |
15613 | && (prefixes & PREFIX_REPZ) != 0) | |
15614 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15615 | ||
15616 | OP_E (bytemode, sizeflag); | |
15617 | } | |
15618 | ||
f5804c90 L |
15619 | static void |
15620 | CMPXCHG8B_Fixup (int bytemode, int sizeflag) | |
15621 | { | |
161a04f6 L |
15622 | USED_REX (REX_W); |
15623 | if (rex & REX_W) | |
f5804c90 L |
15624 | { |
15625 | /* Change cmpxchg8b to cmpxchg16b. */ | |
ea397f5b L |
15626 | char *p = mnemonicendp - 2; |
15627 | mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 15628 | bytemode = o_mode; |
f5804c90 | 15629 | } |
42164a71 L |
15630 | else if ((prefixes & PREFIX_LOCK) != 0) |
15631 | { | |
15632 | if (prefixes & PREFIX_REPZ) | |
15633 | all_prefixes[last_repz_prefix] = XRELEASE_PREFIX; | |
15634 | if (prefixes & PREFIX_REPNZ) | |
15635 | all_prefixes[last_repnz_prefix] = XACQUIRE_PREFIX; | |
15636 | } | |
15637 | ||
f5804c90 L |
15638 | OP_M (bytemode, sizeflag); |
15639 | } | |
42903f7f L |
15640 | |
15641 | static void | |
15642 | XMM_Fixup (int reg, int sizeflag ATTRIBUTE_UNUSED) | |
15643 | { | |
b9733481 L |
15644 | const char **names; |
15645 | ||
c0f3af97 L |
15646 | if (need_vex) |
15647 | { | |
15648 | switch (vex.length) | |
15649 | { | |
15650 | case 128: | |
b9733481 | 15651 | names = names_xmm; |
c0f3af97 L |
15652 | break; |
15653 | case 256: | |
b9733481 | 15654 | names = names_ymm; |
c0f3af97 L |
15655 | break; |
15656 | default: | |
15657 | abort (); | |
15658 | } | |
15659 | } | |
15660 | else | |
b9733481 L |
15661 | names = names_xmm; |
15662 | oappend (names[reg]); | |
42903f7f | 15663 | } |
381d071f L |
15664 | |
15665 | static void | |
15666 | CRC32_Fixup (int bytemode, int sizeflag) | |
15667 | { | |
15668 | /* Add proper suffix to "crc32". */ | |
ea397f5b | 15669 | char *p = mnemonicendp; |
381d071f L |
15670 | |
15671 | switch (bytemode) | |
15672 | { | |
15673 | case b_mode: | |
20592a94 | 15674 | if (intel_syntax) |
ea397f5b | 15675 | goto skip; |
20592a94 | 15676 | |
381d071f L |
15677 | *p++ = 'b'; |
15678 | break; | |
15679 | case v_mode: | |
20592a94 | 15680 | if (intel_syntax) |
ea397f5b | 15681 | goto skip; |
20592a94 | 15682 | |
381d071f L |
15683 | USED_REX (REX_W); |
15684 | if (rex & REX_W) | |
15685 | *p++ = 'q'; | |
7bb15c6f | 15686 | else |
f16cd0d5 L |
15687 | { |
15688 | if (sizeflag & DFLAG) | |
15689 | *p++ = 'l'; | |
15690 | else | |
15691 | *p++ = 'w'; | |
15692 | used_prefixes |= (prefixes & PREFIX_DATA); | |
15693 | } | |
381d071f L |
15694 | break; |
15695 | default: | |
15696 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
15697 | break; | |
15698 | } | |
ea397f5b | 15699 | mnemonicendp = p; |
381d071f L |
15700 | *p = '\0'; |
15701 | ||
dc1e8a47 | 15702 | skip: |
381d071f L |
15703 | if (modrm.mod == 3) |
15704 | { | |
15705 | int add; | |
15706 | ||
15707 | /* Skip mod/rm byte. */ | |
15708 | MODRM_CHECK; | |
15709 | codep++; | |
15710 | ||
15711 | USED_REX (REX_B); | |
15712 | add = (rex & REX_B) ? 8 : 0; | |
15713 | if (bytemode == b_mode) | |
15714 | { | |
15715 | USED_REX (0); | |
15716 | if (rex) | |
15717 | oappend (names8rex[modrm.rm + add]); | |
15718 | else | |
15719 | oappend (names8[modrm.rm + add]); | |
15720 | } | |
15721 | else | |
15722 | { | |
15723 | USED_REX (REX_W); | |
15724 | if (rex & REX_W) | |
15725 | oappend (names64[modrm.rm + add]); | |
15726 | else if ((prefixes & PREFIX_DATA)) | |
15727 | oappend (names16[modrm.rm + add]); | |
15728 | else | |
15729 | oappend (names32[modrm.rm + add]); | |
15730 | } | |
15731 | } | |
15732 | else | |
9344ff29 | 15733 | OP_E (bytemode, sizeflag); |
381d071f | 15734 | } |
85f10a01 | 15735 | |
eacc9c89 L |
15736 | static void |
15737 | FXSAVE_Fixup (int bytemode, int sizeflag) | |
15738 | { | |
15739 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
15740 | USED_REX (REX_W); | |
15741 | if (rex & REX_W) | |
15742 | { | |
15743 | char *p = mnemonicendp; | |
15744 | *p++ = '6'; | |
15745 | *p++ = '4'; | |
15746 | *p = '\0'; | |
15747 | mnemonicendp = p; | |
15748 | } | |
15749 | OP_M (bytemode, sizeflag); | |
15750 | } | |
15751 | ||
15c7c1d8 JB |
15752 | static void |
15753 | PCMPESTR_Fixup (int bytemode, int sizeflag) | |
15754 | { | |
15755 | /* Add proper suffix to "{,v}pcmpestr{i,m}". */ | |
15756 | if (!intel_syntax) | |
15757 | { | |
15758 | char *p = mnemonicendp; | |
15759 | ||
15760 | USED_REX (REX_W); | |
15761 | if (rex & REX_W) | |
15762 | *p++ = 'q'; | |
15763 | else if (sizeflag & SUFFIX_ALWAYS) | |
15764 | *p++ = 'l'; | |
15765 | ||
15766 | *p = '\0'; | |
15767 | mnemonicendp = p; | |
15768 | } | |
15769 | ||
15770 | OP_EX (bytemode, sizeflag); | |
15771 | } | |
15772 | ||
c0f3af97 L |
15773 | /* Display the destination register operand for instructions with |
15774 | VEX. */ | |
15775 | ||
15776 | static void | |
15777 | OP_VEX (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
15778 | { | |
539f890d | 15779 | int reg; |
b9733481 L |
15780 | const char **names; |
15781 | ||
c0f3af97 L |
15782 | if (!need_vex) |
15783 | abort (); | |
15784 | ||
15785 | if (!need_vex_reg) | |
15786 | return; | |
15787 | ||
539f890d | 15788 | reg = vex.register_specifier; |
63c6fc6c | 15789 | vex.register_specifier = 0; |
5f847646 JB |
15790 | if (address_mode != mode_64bit) |
15791 | reg &= 7; | |
15792 | else if (vex.evex && !vex.v) | |
15793 | reg += 16; | |
43234a1e | 15794 | |
539f890d L |
15795 | if (bytemode == vex_scalar_mode) |
15796 | { | |
15797 | oappend (names_xmm[reg]); | |
15798 | return; | |
15799 | } | |
15800 | ||
c0f3af97 L |
15801 | switch (vex.length) |
15802 | { | |
15803 | case 128: | |
15804 | switch (bytemode) | |
15805 | { | |
15806 | case vex_mode: | |
15807 | case vex128_mode: | |
6c30d220 | 15808 | case vex_vsib_q_w_dq_mode: |
5fc35d96 | 15809 | case vex_vsib_q_w_d_mode: |
cb21baef L |
15810 | names = names_xmm; |
15811 | break; | |
15812 | case dq_mode: | |
390a6789 | 15813 | if (rex & REX_W) |
cb21baef L |
15814 | names = names64; |
15815 | else | |
15816 | names = names32; | |
c0f3af97 | 15817 | break; |
1ba585e8 | 15818 | case mask_bd_mode: |
43234a1e | 15819 | case mask_mode: |
9889cbb1 L |
15820 | if (reg > 0x7) |
15821 | { | |
15822 | oappend ("(bad)"); | |
15823 | return; | |
15824 | } | |
43234a1e L |
15825 | names = names_mask; |
15826 | break; | |
c0f3af97 L |
15827 | default: |
15828 | abort (); | |
15829 | return; | |
15830 | } | |
c0f3af97 L |
15831 | break; |
15832 | case 256: | |
15833 | switch (bytemode) | |
15834 | { | |
15835 | case vex_mode: | |
15836 | case vex256_mode: | |
6c30d220 L |
15837 | names = names_ymm; |
15838 | break; | |
15839 | case vex_vsib_q_w_dq_mode: | |
5fc35d96 | 15840 | case vex_vsib_q_w_d_mode: |
6c30d220 | 15841 | names = vex.w ? names_ymm : names_xmm; |
c0f3af97 | 15842 | break; |
1ba585e8 | 15843 | case mask_bd_mode: |
43234a1e | 15844 | case mask_mode: |
9889cbb1 L |
15845 | if (reg > 0x7) |
15846 | { | |
15847 | oappend ("(bad)"); | |
15848 | return; | |
15849 | } | |
43234a1e L |
15850 | names = names_mask; |
15851 | break; | |
c0f3af97 | 15852 | default: |
a37a2806 NC |
15853 | /* See PR binutils/20893 for a reproducer. */ |
15854 | oappend ("(bad)"); | |
c0f3af97 L |
15855 | return; |
15856 | } | |
c0f3af97 | 15857 | break; |
43234a1e L |
15858 | case 512: |
15859 | names = names_zmm; | |
15860 | break; | |
c0f3af97 L |
15861 | default: |
15862 | abort (); | |
15863 | break; | |
15864 | } | |
539f890d | 15865 | oappend (names[reg]); |
c0f3af97 L |
15866 | } |
15867 | ||
922d8de8 DR |
15868 | /* Get the VEX immediate byte without moving codep. */ |
15869 | ||
15870 | static unsigned char | |
ccc5981b | 15871 | get_vex_imm8 (int sizeflag, int opnum) |
922d8de8 DR |
15872 | { |
15873 | int bytes_before_imm = 0; | |
15874 | ||
922d8de8 DR |
15875 | if (modrm.mod != 3) |
15876 | { | |
15877 | /* There are SIB/displacement bytes. */ | |
15878 | if ((sizeflag & AFLAG) || address_mode == mode_64bit) | |
6c067bbb | 15879 | { |
922d8de8 | 15880 | /* 32/64 bit address mode */ |
6c067bbb | 15881 | int base = modrm.rm; |
922d8de8 DR |
15882 | |
15883 | /* Check SIB byte. */ | |
6c067bbb RM |
15884 | if (base == 4) |
15885 | { | |
15886 | FETCH_DATA (the_info, codep + 1); | |
15887 | base = *codep & 7; | |
15888 | /* When decoding the third source, don't increase | |
15889 | bytes_before_imm as this has already been incremented | |
15890 | by one in OP_E_memory while decoding the second | |
15891 | source operand. */ | |
15892 | if (opnum == 0) | |
15893 | bytes_before_imm++; | |
15894 | } | |
15895 | ||
15896 | /* Don't increase bytes_before_imm when decoding the third source, | |
15897 | it has already been incremented by OP_E_memory while decoding | |
15898 | the second source operand. */ | |
15899 | if (opnum == 0) | |
15900 | { | |
15901 | switch (modrm.mod) | |
15902 | { | |
15903 | case 0: | |
15904 | /* When modrm.rm == 5 or modrm.rm == 4 and base in | |
15905 | SIB == 5, there is a 4 byte displacement. */ | |
15906 | if (base != 5) | |
15907 | /* No displacement. */ | |
15908 | break; | |
1a0670f3 | 15909 | /* Fall through. */ |
6c067bbb RM |
15910 | case 2: |
15911 | /* 4 byte displacement. */ | |
15912 | bytes_before_imm += 4; | |
15913 | break; | |
15914 | case 1: | |
15915 | /* 1 byte displacement. */ | |
15916 | bytes_before_imm++; | |
15917 | break; | |
15918 | } | |
15919 | } | |
15920 | } | |
922d8de8 | 15921 | else |
02e647f9 SP |
15922 | { |
15923 | /* 16 bit address mode */ | |
6c067bbb RM |
15924 | /* Don't increase bytes_before_imm when decoding the third source, |
15925 | it has already been incremented by OP_E_memory while decoding | |
15926 | the second source operand. */ | |
15927 | if (opnum == 0) | |
15928 | { | |
02e647f9 SP |
15929 | switch (modrm.mod) |
15930 | { | |
15931 | case 0: | |
15932 | /* When modrm.rm == 6, there is a 2 byte displacement. */ | |
15933 | if (modrm.rm != 6) | |
15934 | /* No displacement. */ | |
15935 | break; | |
1a0670f3 | 15936 | /* Fall through. */ |
02e647f9 SP |
15937 | case 2: |
15938 | /* 2 byte displacement. */ | |
15939 | bytes_before_imm += 2; | |
15940 | break; | |
15941 | case 1: | |
15942 | /* 1 byte displacement: when decoding the third source, | |
15943 | don't increase bytes_before_imm as this has already | |
15944 | been incremented by one in OP_E_memory while decoding | |
15945 | the second source operand. */ | |
15946 | if (opnum == 0) | |
15947 | bytes_before_imm++; | |
ccc5981b | 15948 | |
02e647f9 SP |
15949 | break; |
15950 | } | |
922d8de8 DR |
15951 | } |
15952 | } | |
15953 | } | |
15954 | ||
15955 | FETCH_DATA (the_info, codep + bytes_before_imm + 1); | |
15956 | return codep [bytes_before_imm]; | |
15957 | } | |
15958 | ||
15959 | static void | |
15960 | OP_EX_VexReg (int bytemode, int sizeflag, int reg) | |
15961 | { | |
b9733481 L |
15962 | const char **names; |
15963 | ||
922d8de8 DR |
15964 | if (reg == -1 && modrm.mod != 3) |
15965 | { | |
15966 | OP_E_memory (bytemode, sizeflag); | |
15967 | return; | |
15968 | } | |
15969 | else | |
15970 | { | |
15971 | if (reg == -1) | |
15972 | { | |
15973 | reg = modrm.rm; | |
15974 | USED_REX (REX_B); | |
15975 | if (rex & REX_B) | |
15976 | reg += 8; | |
15977 | } | |
5f847646 JB |
15978 | if (address_mode != mode_64bit) |
15979 | reg &= 7; | |
922d8de8 DR |
15980 | } |
15981 | ||
15982 | switch (vex.length) | |
15983 | { | |
15984 | case 128: | |
b9733481 | 15985 | names = names_xmm; |
922d8de8 DR |
15986 | break; |
15987 | case 256: | |
b9733481 | 15988 | names = names_ymm; |
922d8de8 DR |
15989 | break; |
15990 | default: | |
15991 | abort (); | |
15992 | } | |
b9733481 | 15993 | oappend (names[reg]); |
922d8de8 DR |
15994 | } |
15995 | ||
a683cc34 SP |
15996 | static void |
15997 | OP_EX_VexImmW (int bytemode, int sizeflag) | |
15998 | { | |
15999 | int reg = -1; | |
16000 | static unsigned char vex_imm8; | |
16001 | ||
16002 | if (vex_w_done == 0) | |
16003 | { | |
16004 | vex_w_done = 1; | |
16005 | ||
16006 | /* Skip mod/rm byte. */ | |
16007 | MODRM_CHECK; | |
16008 | codep++; | |
16009 | ||
16010 | vex_imm8 = get_vex_imm8 (sizeflag, 0); | |
16011 | ||
16012 | if (vex.w) | |
16013 | reg = vex_imm8 >> 4; | |
16014 | ||
16015 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16016 | } | |
16017 | else if (vex_w_done == 1) | |
16018 | { | |
16019 | vex_w_done = 2; | |
16020 | ||
16021 | if (!vex.w) | |
16022 | reg = vex_imm8 >> 4; | |
16023 | ||
16024 | OP_EX_VexReg (bytemode, sizeflag, reg); | |
16025 | } | |
16026 | else | |
16027 | { | |
16028 | /* Output the imm8 directly. */ | |
16029 | scratchbuf[0] = '$'; | |
16030 | print_operand_value (scratchbuf + 1, 1, vex_imm8 & 0xf); | |
9ce09ba2 | 16031 | oappend_maybe_intel (scratchbuf); |
a683cc34 SP |
16032 | scratchbuf[0] = '\0'; |
16033 | codep++; | |
16034 | } | |
16035 | } | |
16036 | ||
5dd85c99 SP |
16037 | static void |
16038 | OP_Vex_2src (int bytemode, int sizeflag) | |
16039 | { | |
16040 | if (modrm.mod == 3) | |
16041 | { | |
b9733481 | 16042 | int reg = modrm.rm; |
5dd85c99 | 16043 | USED_REX (REX_B); |
b9733481 L |
16044 | if (rex & REX_B) |
16045 | reg += 8; | |
16046 | oappend (names_xmm[reg]); | |
5dd85c99 SP |
16047 | } |
16048 | else | |
16049 | { | |
16050 | if (intel_syntax | |
16051 | && (bytemode == v_mode || bytemode == v_swap_mode)) | |
16052 | { | |
16053 | bytemode = (prefixes & PREFIX_DATA) ? x_mode : q_mode; | |
16054 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16055 | } | |
16056 | OP_E (bytemode, sizeflag); | |
16057 | } | |
16058 | } | |
16059 | ||
16060 | static void | |
16061 | OP_Vex_2src_1 (int bytemode, int sizeflag) | |
16062 | { | |
16063 | if (modrm.mod == 3) | |
16064 | { | |
16065 | /* Skip mod/rm byte. */ | |
16066 | MODRM_CHECK; | |
16067 | codep++; | |
16068 | } | |
16069 | ||
16070 | if (vex.w) | |
5f847646 JB |
16071 | { |
16072 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16073 | vex.register_specifier = 0; |
5f847646 JB |
16074 | |
16075 | if (address_mode != mode_64bit) | |
16076 | reg &= 7; | |
16077 | oappend (names_xmm[reg]); | |
16078 | } | |
5dd85c99 SP |
16079 | else |
16080 | OP_Vex_2src (bytemode, sizeflag); | |
16081 | } | |
16082 | ||
16083 | static void | |
16084 | OP_Vex_2src_2 (int bytemode, int sizeflag) | |
16085 | { | |
16086 | if (vex.w) | |
16087 | OP_Vex_2src (bytemode, sizeflag); | |
16088 | else | |
5f847646 JB |
16089 | { |
16090 | unsigned int reg = vex.register_specifier; | |
63c6fc6c | 16091 | vex.register_specifier = 0; |
5f847646 JB |
16092 | |
16093 | if (address_mode != mode_64bit) | |
16094 | reg &= 7; | |
16095 | oappend (names_xmm[reg]); | |
16096 | } | |
5dd85c99 SP |
16097 | } |
16098 | ||
c0f3af97 L |
16099 | static void |
16100 | OP_REG_VexI4 (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16101 | { | |
16102 | int reg; | |
b9733481 L |
16103 | const char **names; |
16104 | ||
c0f3af97 L |
16105 | FETCH_DATA (the_info, codep + 1); |
16106 | reg = *codep++; | |
16107 | ||
16108 | if (bytemode != x_mode) | |
16109 | abort (); | |
16110 | ||
c0f3af97 | 16111 | reg >>= 4; |
5f847646 JB |
16112 | if (address_mode != mode_64bit) |
16113 | reg &= 7; | |
dae39acc | 16114 | |
c0f3af97 L |
16115 | switch (vex.length) |
16116 | { | |
16117 | case 128: | |
b9733481 | 16118 | names = names_xmm; |
c0f3af97 L |
16119 | break; |
16120 | case 256: | |
b9733481 | 16121 | names = names_ymm; |
c0f3af97 L |
16122 | break; |
16123 | default: | |
16124 | abort (); | |
16125 | } | |
b9733481 | 16126 | oappend (names[reg]); |
b13b1bc0 JB |
16127 | |
16128 | if (vex.w) | |
16129 | { | |
16130 | /* Swap 3rd and 4th operands. */ | |
16131 | strcpy (scratchbuf, op_out[3]); | |
16132 | strcpy (op_out[3], op_out[2]); | |
16133 | strcpy (op_out[2], scratchbuf); | |
16134 | } | |
c0f3af97 L |
16135 | } |
16136 | ||
922d8de8 DR |
16137 | static void |
16138 | OP_XMM_VexW (int bytemode, int sizeflag) | |
16139 | { | |
16140 | /* Turn off the REX.W bit since it is used for swapping operands | |
16141 | now. */ | |
16142 | rex &= ~REX_W; | |
16143 | OP_XMM (bytemode, sizeflag); | |
16144 | } | |
16145 | ||
c0f3af97 L |
16146 | static void |
16147 | OP_EX_Vex (int bytemode, int sizeflag) | |
16148 | { | |
16149 | if (modrm.mod != 3) | |
63c6fc6c | 16150 | need_vex_reg = 0; |
c0f3af97 L |
16151 | OP_EX (bytemode, sizeflag); |
16152 | } | |
16153 | ||
16154 | static void | |
16155 | OP_XMM_Vex (int bytemode, int sizeflag) | |
16156 | { | |
16157 | if (modrm.mod != 3) | |
63c6fc6c | 16158 | need_vex_reg = 0; |
c0f3af97 L |
16159 | OP_XMM (bytemode, sizeflag); |
16160 | } | |
16161 | ||
ea397f5b L |
16162 | static struct op vex_cmp_op[] = |
16163 | { | |
16164 | { STRING_COMMA_LEN ("eq") }, | |
16165 | { STRING_COMMA_LEN ("lt") }, | |
16166 | { STRING_COMMA_LEN ("le") }, | |
16167 | { STRING_COMMA_LEN ("unord") }, | |
16168 | { STRING_COMMA_LEN ("neq") }, | |
16169 | { STRING_COMMA_LEN ("nlt") }, | |
16170 | { STRING_COMMA_LEN ("nle") }, | |
16171 | { STRING_COMMA_LEN ("ord") }, | |
16172 | { STRING_COMMA_LEN ("eq_uq") }, | |
16173 | { STRING_COMMA_LEN ("nge") }, | |
16174 | { STRING_COMMA_LEN ("ngt") }, | |
16175 | { STRING_COMMA_LEN ("false") }, | |
16176 | { STRING_COMMA_LEN ("neq_oq") }, | |
16177 | { STRING_COMMA_LEN ("ge") }, | |
16178 | { STRING_COMMA_LEN ("gt") }, | |
16179 | { STRING_COMMA_LEN ("true") }, | |
16180 | { STRING_COMMA_LEN ("eq_os") }, | |
16181 | { STRING_COMMA_LEN ("lt_oq") }, | |
16182 | { STRING_COMMA_LEN ("le_oq") }, | |
16183 | { STRING_COMMA_LEN ("unord_s") }, | |
16184 | { STRING_COMMA_LEN ("neq_us") }, | |
16185 | { STRING_COMMA_LEN ("nlt_uq") }, | |
16186 | { STRING_COMMA_LEN ("nle_uq") }, | |
16187 | { STRING_COMMA_LEN ("ord_s") }, | |
16188 | { STRING_COMMA_LEN ("eq_us") }, | |
16189 | { STRING_COMMA_LEN ("nge_uq") }, | |
16190 | { STRING_COMMA_LEN ("ngt_uq") }, | |
16191 | { STRING_COMMA_LEN ("false_os") }, | |
16192 | { STRING_COMMA_LEN ("neq_os") }, | |
16193 | { STRING_COMMA_LEN ("ge_oq") }, | |
16194 | { STRING_COMMA_LEN ("gt_oq") }, | |
16195 | { STRING_COMMA_LEN ("true_us") }, | |
c0f3af97 L |
16196 | }; |
16197 | ||
16198 | static void | |
16199 | VCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16200 | { | |
16201 | unsigned int cmp_type; | |
16202 | ||
16203 | FETCH_DATA (the_info, codep + 1); | |
16204 | cmp_type = *codep++ & 0xff; | |
16205 | if (cmp_type < ARRAY_SIZE (vex_cmp_op)) | |
16206 | { | |
16207 | char suffix [3]; | |
ea397f5b | 16208 | char *p = mnemonicendp - 2; |
c0f3af97 L |
16209 | suffix[0] = p[0]; |
16210 | suffix[1] = p[1]; | |
16211 | suffix[2] = '\0'; | |
ea397f5b L |
16212 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); |
16213 | mnemonicendp += vex_cmp_op[cmp_type].len; | |
c0f3af97 L |
16214 | } |
16215 | else | |
16216 | { | |
16217 | /* We have a reserved extension byte. Output it directly. */ | |
16218 | scratchbuf[0] = '$'; | |
16219 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16220 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16221 | scratchbuf[0] = '\0'; |
16222 | } | |
16223 | } | |
16224 | ||
43234a1e L |
16225 | static void |
16226 | VPCMP_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16227 | int sizeflag ATTRIBUTE_UNUSED) | |
16228 | { | |
16229 | unsigned int cmp_type; | |
16230 | ||
16231 | if (!vex.evex) | |
16232 | abort (); | |
16233 | ||
16234 | FETCH_DATA (the_info, codep + 1); | |
16235 | cmp_type = *codep++ & 0xff; | |
16236 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. | |
16237 | If it's the case, print suffix, otherwise - print the immediate. */ | |
16238 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
16239 | && cmp_type != 3 | |
16240 | && cmp_type != 7) | |
16241 | { | |
16242 | char suffix [3]; | |
16243 | char *p = mnemonicendp - 2; | |
16244 | ||
16245 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
16246 | if (p[0] == 'p') | |
16247 | { | |
16248 | p++; | |
16249 | suffix[0] = p[0]; | |
16250 | suffix[1] = '\0'; | |
16251 | } | |
16252 | else | |
16253 | { | |
16254 | suffix[0] = p[0]; | |
16255 | suffix[1] = p[1]; | |
16256 | suffix[2] = '\0'; | |
16257 | } | |
16258 | ||
16259 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
16260 | mnemonicendp += simd_cmp_op[cmp_type].len; | |
16261 | } | |
be92cb14 JB |
16262 | else |
16263 | { | |
16264 | /* We have a reserved extension byte. Output it directly. */ | |
16265 | scratchbuf[0] = '$'; | |
16266 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
16267 | oappend_maybe_intel (scratchbuf); | |
16268 | scratchbuf[0] = '\0'; | |
16269 | } | |
16270 | } | |
16271 | ||
16272 | static const struct op xop_cmp_op[] = | |
16273 | { | |
16274 | { STRING_COMMA_LEN ("lt") }, | |
16275 | { STRING_COMMA_LEN ("le") }, | |
16276 | { STRING_COMMA_LEN ("gt") }, | |
16277 | { STRING_COMMA_LEN ("ge") }, | |
16278 | { STRING_COMMA_LEN ("eq") }, | |
16279 | { STRING_COMMA_LEN ("neq") }, | |
16280 | { STRING_COMMA_LEN ("false") }, | |
16281 | { STRING_COMMA_LEN ("true") } | |
16282 | }; | |
16283 | ||
16284 | static void | |
16285 | VPCOM_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16286 | int sizeflag ATTRIBUTE_UNUSED) | |
16287 | { | |
16288 | unsigned int cmp_type; | |
16289 | ||
16290 | FETCH_DATA (the_info, codep + 1); | |
16291 | cmp_type = *codep++ & 0xff; | |
16292 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) | |
16293 | { | |
16294 | char suffix[3]; | |
16295 | char *p = mnemonicendp - 2; | |
16296 | ||
16297 | /* vpcom* can have both one- and two-lettered suffix. */ | |
16298 | if (p[0] == 'm') | |
16299 | { | |
16300 | p++; | |
16301 | suffix[0] = p[0]; | |
16302 | suffix[1] = '\0'; | |
16303 | } | |
16304 | else | |
16305 | { | |
16306 | suffix[0] = p[0]; | |
16307 | suffix[1] = p[1]; | |
16308 | suffix[2] = '\0'; | |
16309 | } | |
16310 | ||
16311 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
16312 | mnemonicendp += xop_cmp_op[cmp_type].len; | |
16313 | } | |
43234a1e L |
16314 | else |
16315 | { | |
16316 | /* We have a reserved extension byte. Output it directly. */ | |
16317 | scratchbuf[0] = '$'; | |
16318 | print_operand_value (scratchbuf + 1, 1, cmp_type); | |
9ce09ba2 | 16319 | oappend_maybe_intel (scratchbuf); |
43234a1e L |
16320 | scratchbuf[0] = '\0'; |
16321 | } | |
16322 | } | |
16323 | ||
ea397f5b L |
16324 | static const struct op pclmul_op[] = |
16325 | { | |
16326 | { STRING_COMMA_LEN ("lql") }, | |
16327 | { STRING_COMMA_LEN ("hql") }, | |
16328 | { STRING_COMMA_LEN ("lqh") }, | |
16329 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
16330 | }; |
16331 | ||
16332 | static void | |
16333 | PCLMUL_Fixup (int bytemode ATTRIBUTE_UNUSED, | |
16334 | int sizeflag ATTRIBUTE_UNUSED) | |
16335 | { | |
16336 | unsigned int pclmul_type; | |
16337 | ||
16338 | FETCH_DATA (the_info, codep + 1); | |
16339 | pclmul_type = *codep++ & 0xff; | |
16340 | switch (pclmul_type) | |
16341 | { | |
16342 | case 0x10: | |
16343 | pclmul_type = 2; | |
16344 | break; | |
16345 | case 0x11: | |
16346 | pclmul_type = 3; | |
16347 | break; | |
16348 | default: | |
16349 | break; | |
7bb15c6f | 16350 | } |
c0f3af97 L |
16351 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
16352 | { | |
16353 | char suffix [4]; | |
ea397f5b | 16354 | char *p = mnemonicendp - 3; |
c0f3af97 L |
16355 | suffix[0] = p[0]; |
16356 | suffix[1] = p[1]; | |
16357 | suffix[2] = p[2]; | |
16358 | suffix[3] = '\0'; | |
ea397f5b L |
16359 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
16360 | mnemonicendp += pclmul_op[pclmul_type].len; | |
c0f3af97 L |
16361 | } |
16362 | else | |
16363 | { | |
16364 | /* We have a reserved extension byte. Output it directly. */ | |
16365 | scratchbuf[0] = '$'; | |
16366 | print_operand_value (scratchbuf + 1, 1, pclmul_type); | |
9ce09ba2 | 16367 | oappend_maybe_intel (scratchbuf); |
c0f3af97 L |
16368 | scratchbuf[0] = '\0'; |
16369 | } | |
16370 | } | |
16371 | ||
f1f8f695 L |
16372 | static void |
16373 | MOVBE_Fixup (int bytemode, int sizeflag) | |
16374 | { | |
16375 | /* Add proper suffix to "movbe". */ | |
ea397f5b | 16376 | char *p = mnemonicendp; |
f1f8f695 L |
16377 | |
16378 | switch (bytemode) | |
16379 | { | |
16380 | case v_mode: | |
16381 | if (intel_syntax) | |
ea397f5b | 16382 | goto skip; |
f1f8f695 L |
16383 | |
16384 | USED_REX (REX_W); | |
16385 | if (sizeflag & SUFFIX_ALWAYS) | |
16386 | { | |
16387 | if (rex & REX_W) | |
16388 | *p++ = 'q'; | |
f1f8f695 | 16389 | else |
f16cd0d5 L |
16390 | { |
16391 | if (sizeflag & DFLAG) | |
16392 | *p++ = 'l'; | |
16393 | else | |
16394 | *p++ = 'w'; | |
16395 | used_prefixes |= (prefixes & PREFIX_DATA); | |
16396 | } | |
f1f8f695 | 16397 | } |
f1f8f695 L |
16398 | break; |
16399 | default: | |
16400 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16401 | break; | |
16402 | } | |
ea397f5b | 16403 | mnemonicendp = p; |
f1f8f695 L |
16404 | *p = '\0'; |
16405 | ||
dc1e8a47 | 16406 | skip: |
f1f8f695 L |
16407 | OP_M (bytemode, sizeflag); |
16408 | } | |
f88c9eb0 | 16409 | |
bc31405e L |
16410 | static void |
16411 | MOVSXD_Fixup (int bytemode, int sizeflag) | |
16412 | { | |
16413 | /* Add proper suffix to "movsxd". */ | |
16414 | char *p = mnemonicendp; | |
16415 | ||
16416 | switch (bytemode) | |
16417 | { | |
16418 | case movsxd_mode: | |
16419 | if (intel_syntax) | |
16420 | { | |
16421 | *p++ = 'x'; | |
16422 | *p++ = 'd'; | |
16423 | goto skip; | |
16424 | } | |
16425 | ||
16426 | USED_REX (REX_W); | |
16427 | if (rex & REX_W) | |
16428 | { | |
16429 | *p++ = 'l'; | |
16430 | *p++ = 'q'; | |
16431 | } | |
16432 | else | |
16433 | { | |
16434 | *p++ = 'x'; | |
16435 | *p++ = 'd'; | |
16436 | } | |
16437 | break; | |
16438 | default: | |
16439 | oappend (INTERNAL_DISASSEMBLER_ERROR); | |
16440 | break; | |
16441 | } | |
16442 | ||
dc1e8a47 | 16443 | skip: |
bc31405e L |
16444 | mnemonicendp = p; |
16445 | *p = '\0'; | |
16446 | OP_E (bytemode, sizeflag); | |
16447 | } | |
16448 | ||
f88c9eb0 SP |
16449 | static void |
16450 | OP_LWPCB_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16451 | { | |
16452 | int reg; | |
16453 | const char **names; | |
16454 | ||
16455 | /* Skip mod/rm byte. */ | |
16456 | MODRM_CHECK; | |
16457 | codep++; | |
16458 | ||
390a6789 | 16459 | if (rex & REX_W) |
f88c9eb0 | 16460 | names = names64; |
f88c9eb0 | 16461 | else |
ce7d077e | 16462 | names = names32; |
f88c9eb0 SP |
16463 | |
16464 | reg = modrm.rm; | |
16465 | USED_REX (REX_B); | |
16466 | if (rex & REX_B) | |
16467 | reg += 8; | |
16468 | ||
16469 | oappend (names[reg]); | |
16470 | } | |
16471 | ||
16472 | static void | |
16473 | OP_LWP_E (int bytemode ATTRIBUTE_UNUSED, int sizeflag ATTRIBUTE_UNUSED) | |
16474 | { | |
16475 | const char **names; | |
5f847646 | 16476 | unsigned int reg = vex.register_specifier; |
63c6fc6c | 16477 | vex.register_specifier = 0; |
f88c9eb0 | 16478 | |
390a6789 | 16479 | if (rex & REX_W) |
f88c9eb0 | 16480 | names = names64; |
f88c9eb0 | 16481 | else |
ce7d077e | 16482 | names = names32; |
f88c9eb0 | 16483 | |
5f847646 JB |
16484 | if (address_mode != mode_64bit) |
16485 | reg &= 7; | |
16486 | oappend (names[reg]); | |
f88c9eb0 | 16487 | } |
43234a1e L |
16488 | |
16489 | static void | |
16490 | OP_Mask (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16491 | { | |
16492 | if (!vex.evex | |
1ba585e8 | 16493 | || (bytemode != mask_mode && bytemode != mask_bd_mode)) |
43234a1e L |
16494 | abort (); |
16495 | ||
16496 | USED_REX (REX_R); | |
16497 | if ((rex & REX_R) != 0 || !vex.r) | |
16498 | { | |
16499 | BadOp (); | |
16500 | return; | |
16501 | } | |
16502 | ||
16503 | oappend (names_mask [modrm.reg]); | |
16504 | } | |
16505 | ||
16506 | static void | |
16507 | OP_Rounding (int bytemode, int sizeflag ATTRIBUTE_UNUSED) | |
16508 | { | |
43234a1e L |
16509 | if (modrm.mod == 3 && vex.b) |
16510 | switch (bytemode) | |
16511 | { | |
70df6fc9 L |
16512 | case evex_rounding_64_mode: |
16513 | if (address_mode != mode_64bit) | |
16514 | { | |
16515 | oappend ("(bad)"); | |
16516 | break; | |
16517 | } | |
16518 | /* Fall through. */ | |
43234a1e L |
16519 | case evex_rounding_mode: |
16520 | oappend (names_rounding[vex.ll]); | |
16521 | break; | |
16522 | case evex_sae_mode: | |
16523 | oappend ("{sae}"); | |
16524 | break; | |
16525 | default: | |
6df22cf6 | 16526 | abort (); |
43234a1e L |
16527 | break; |
16528 | } | |
16529 | } |