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252b5132 | 1 | /* Print i386 instructions for GDB, the GNU debugger. |
d87bef3a | 2 | Copyright (C) 1988-2023 Free Software Foundation, Inc. |
252b5132 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
20f0a1fc | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
20f0a1fc | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 NC |
8 | the Free Software Foundation; either version 3, or (at your option) |
9 | any later version. | |
20f0a1fc | 10 | |
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
20f0a1fc NC |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with this program; if not, write to the Free Software | |
9b201bb5 NC |
18 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
19 | MA 02110-1301, USA. */ | |
20 | ||
20f0a1fc NC |
21 | |
22 | /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu) | |
23 | July 1988 | |
24 | modified by John Hassey (hassey@dg-rtp.dg.com) | |
25 | x86-64 support added by Jan Hubicka (jh@suse.cz) | |
26 | VIA PadLock support by Michal Ludvig (mludvig@suse.cz). */ | |
27 | ||
28 | /* The main tables describing the instructions is essentially a copy | |
29 | of the "Opcode Map" chapter (Appendix A) of the Intel 80386 | |
30 | Programmers Manual. Usually, there is a capital letter, followed | |
31 | by a small letter. The capital letter tell the addressing mode, | |
32 | and the small letter tells about the operand size. Refer to | |
33 | the Intel manual for details. */ | |
252b5132 | 34 | |
252b5132 | 35 | #include "sysdep.h" |
88c1242d | 36 | #include "disassemble.h" |
252b5132 | 37 | #include "opintl.h" |
0b1cf022 | 38 | #include "opcode/i386.h" |
85f10a01 | 39 | #include "libiberty.h" |
5b872f7d | 40 | #include "safe-ctype.h" |
252b5132 | 41 | |
39fb3698 VM |
42 | typedef struct instr_info instr_info; |
43 | ||
97601363 | 44 | static bool dofloat (instr_info *, int); |
39fb3698 | 45 | static int putop (instr_info *, const char *, int); |
2c3b9a91 AB |
46 | static void oappend_with_style (instr_info *, const char *, |
47 | enum disassembler_style); | |
97601363 JB |
48 | |
49 | static bool OP_E (instr_info *, int, int); | |
50 | static bool OP_E_memory (instr_info *, int, int); | |
51 | static bool OP_indirE (instr_info *, int, int); | |
52 | static bool OP_G (instr_info *, int, int); | |
53 | static bool OP_ST (instr_info *, int, int); | |
54 | static bool OP_STi (instr_info *, int, int); | |
55 | static bool OP_Skip_MODRM (instr_info *, int, int); | |
56 | static bool OP_REG (instr_info *, int, int); | |
57 | static bool OP_IMREG (instr_info *, int, int); | |
58 | static bool OP_I (instr_info *, int, int); | |
59 | static bool OP_I64 (instr_info *, int, int); | |
60 | static bool OP_sI (instr_info *, int, int); | |
61 | static bool OP_J (instr_info *, int, int); | |
62 | static bool OP_SEG (instr_info *, int, int); | |
63 | static bool OP_DIR (instr_info *, int, int); | |
64 | static bool OP_OFF (instr_info *, int, int); | |
65 | static bool OP_OFF64 (instr_info *, int, int); | |
66 | static bool OP_ESreg (instr_info *, int, int); | |
67 | static bool OP_DSreg (instr_info *, int, int); | |
68 | static bool OP_C (instr_info *, int, int); | |
69 | static bool OP_D (instr_info *, int, int); | |
70 | static bool OP_T (instr_info *, int, int); | |
71 | static bool OP_MMX (instr_info *, int, int); | |
72 | static bool OP_XMM (instr_info *, int, int); | |
73 | static bool OP_EM (instr_info *, int, int); | |
74 | static bool OP_EX (instr_info *, int, int); | |
75 | static bool OP_EMC (instr_info *, int,int); | |
76 | static bool OP_MXC (instr_info *, int,int); | |
b5c37946 | 77 | static bool OP_R (instr_info *, int, int); |
97601363 JB |
78 | static bool OP_M (instr_info *, int, int); |
79 | static bool OP_VEX (instr_info *, int, int); | |
80 | static bool OP_VexR (instr_info *, int, int); | |
81 | static bool OP_VexW (instr_info *, int, int); | |
82 | static bool OP_Rounding (instr_info *, int, int); | |
83 | static bool OP_REG_VexI4 (instr_info *, int, int); | |
84 | static bool OP_VexI4 (instr_info *, int, int); | |
85 | static bool OP_0f07 (instr_info *, int, int); | |
86 | static bool OP_Monitor (instr_info *, int, int); | |
87 | static bool OP_Mwait (instr_info *, int, int); | |
88 | ||
97601363 JB |
89 | static bool PCLMUL_Fixup (instr_info *, int, int); |
90 | static bool VPCMP_Fixup (instr_info *, int, int); | |
91 | static bool VPCOM_Fixup (instr_info *, int, int); | |
92 | static bool NOP_Fixup (instr_info *, int, int); | |
93 | static bool OP_3DNowSuffix (instr_info *, int, int); | |
94 | static bool CMP_Fixup (instr_info *, int, int); | |
95 | static bool REP_Fixup (instr_info *, int, int); | |
96 | static bool SEP_Fixup (instr_info *, int, int); | |
97 | static bool BND_Fixup (instr_info *, int, int); | |
98 | static bool NOTRACK_Fixup (instr_info *, int, int); | |
99 | static bool HLE_Fixup1 (instr_info *, int, int); | |
100 | static bool HLE_Fixup2 (instr_info *, int, int); | |
101 | static bool HLE_Fixup3 (instr_info *, int, int); | |
102 | static bool CMPXCHG8B_Fixup (instr_info *, int, int); | |
103 | static bool XMM_Fixup (instr_info *, int, int); | |
104 | static bool FXSAVE_Fixup (instr_info *, int, int); | |
105 | static bool MOVSXD_Fixup (instr_info *, int, int); | |
106 | static bool DistinctDest_Fixup (instr_info *, int, int); | |
107 | static bool PREFETCHI_Fixup (instr_info *, int, int); | |
252b5132 | 108 | |
e4452aa6 | 109 | static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *, |
4bcbe86c JB |
110 | enum disassembler_style, |
111 | const char *, ...); | |
4bcbe86c | 112 | |
2c3b9a91 AB |
113 | /* This character is used to encode style information within the output |
114 | buffers. See oappend_insert_style for more details. */ | |
115 | #define STYLE_MARKER_CHAR '\002' | |
116 | ||
9096fc28 L |
117 | /* The maximum operand buffer size. */ |
118 | #define MAX_OPERAND_BUFFER_SIZE 128 | |
119 | ||
cb712a9e L |
120 | enum address_mode |
121 | { | |
122 | mode_16bit, | |
123 | mode_32bit, | |
124 | mode_64bit | |
125 | }; | |
126 | ||
a4aa034a | 127 | static const char *prefix_name (enum address_mode, uint8_t, int); |
ffe983ed | 128 | |
39fb3698 VM |
129 | enum x86_64_isa |
130 | { | |
131 | amd64 = 1, | |
132 | intel64 | |
133 | }; | |
134 | ||
135 | struct instr_info | |
136 | { | |
137 | enum address_mode address_mode; | |
138 | ||
139 | /* Flags for the prefixes for the current instruction. See below. */ | |
140 | int prefixes; | |
141 | ||
142 | /* REX prefix the current instruction. See below. */ | |
a4aa034a | 143 | uint8_t rex; |
39fb3698 | 144 | /* Bits of REX we've already used. */ |
a4aa034a | 145 | uint8_t rex_used; |
ab31da6a JB |
146 | |
147 | bool need_modrm; | |
b5c37946 | 148 | unsigned char need_vex; |
ce20459e | 149 | bool has_sib; |
39fb3698 VM |
150 | |
151 | /* Flags for ins->prefixes which we somehow handled when printing the | |
152 | current instruction. */ | |
153 | int used_prefixes; | |
154 | ||
155 | /* Flags for EVEX bits which we somehow handled when printing the | |
156 | current instruction. */ | |
157 | int evex_used; | |
158 | ||
9096fc28 | 159 | char obuf[MAX_OPERAND_BUFFER_SIZE]; |
39fb3698 VM |
160 | char *obufp; |
161 | char *mnemonicendp; | |
a4aa034a | 162 | const uint8_t *start_codep; |
a4aa034a JB |
163 | uint8_t *codep; |
164 | const uint8_t *end_codep; | |
1a3b4f90 | 165 | unsigned char nr_prefixes; |
eebc56d6 JB |
166 | signed char last_lock_prefix; |
167 | signed char last_repz_prefix; | |
168 | signed char last_repnz_prefix; | |
169 | signed char last_data_prefix; | |
170 | signed char last_addr_prefix; | |
171 | signed char last_rex_prefix; | |
172 | signed char last_seg_prefix; | |
173 | signed char fwait_prefix; | |
39fb3698 | 174 | /* The active segment register prefix. */ |
eebc56d6 | 175 | unsigned char active_seg_prefix; |
39fb3698 VM |
176 | |
177 | #define MAX_CODE_LENGTH 15 | |
178 | /* We can up to 14 ins->prefixes since the maximum instruction length is | |
179 | 15bytes. */ | |
a4aa034a | 180 | uint8_t all_prefixes[MAX_CODE_LENGTH - 1]; |
39fb3698 VM |
181 | disassemble_info *info; |
182 | ||
183 | struct | |
184 | { | |
185 | int mod; | |
186 | int reg; | |
187 | int rm; | |
188 | } | |
189 | modrm; | |
39fb3698 VM |
190 | |
191 | struct | |
192 | { | |
193 | int scale; | |
194 | int index; | |
195 | int base; | |
196 | } | |
197 | sib; | |
198 | ||
199 | struct | |
200 | { | |
201 | int register_specifier; | |
202 | int length; | |
203 | int prefix; | |
39fb3698 | 204 | int mask_register_specifier; |
39fb3698 | 205 | int ll; |
ab31da6a JB |
206 | bool w; |
207 | bool evex; | |
208 | bool r; | |
209 | bool v; | |
210 | bool zeroing; | |
211 | bool b; | |
212 | bool no_broadcast; | |
39fb3698 VM |
213 | } |
214 | vex; | |
39fb3698 | 215 | |
39fb3698 VM |
216 | /* Remember if the current op is a jump instruction. */ |
217 | bool op_is_jump; | |
218 | ||
ab31da6a JB |
219 | bool two_source_ops; |
220 | ||
b5c37946 SJ |
221 | /* Record whether EVEX masking is used incorrectly. */ |
222 | bool illegal_masking; | |
223 | ||
ab31da6a JB |
224 | unsigned char op_ad; |
225 | signed char op_index[MAX_OPERANDS]; | |
4bb8b8e9 | 226 | bool op_riprel[MAX_OPERANDS]; |
384e201e | 227 | char *op_out[MAX_OPERANDS]; |
39fb3698 | 228 | bfd_vma op_address[MAX_OPERANDS]; |
39fb3698 VM |
229 | bfd_vma start_pc; |
230 | ||
231 | /* On the 386's of 1988, the maximum length of an instruction is 15 bytes. | |
232 | * (see topic "Redundant ins->prefixes" in the "Differences from 8086" | |
233 | * section of the "Virtual 8086 Mode" chapter.) | |
234 | * 'pc' should be the address of this instruction, it will | |
235 | * be used to print the target address if this is a relative jump or call | |
236 | * The function returns the length of this instruction in bytes. | |
237 | */ | |
238 | char intel_syntax; | |
ab31da6a | 239 | bool intel_mnemonic; |
39fb3698 VM |
240 | char open_char; |
241 | char close_char; | |
242 | char separator_char; | |
243 | char scale_char; | |
244 | ||
245 | enum x86_64_isa isa64; | |
39fb3698 | 246 | }; |
5076851f | 247 | |
d8acf376 JB |
248 | struct dis_private { |
249 | bfd_vma insn_start; | |
250 | int orig_sizeflag; | |
251 | ||
1a3b4f90 JB |
252 | /* Indexes first byte not fetched. */ |
253 | unsigned int fetched; | |
d8acf376 JB |
254 | uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1]; |
255 | }; | |
256 | ||
52b15da3 JH |
257 | /* Mark parts used in the REX prefix. When we are testing for |
258 | empty prefix (for 8bit register REX extension), just mask it | |
259 | out. Otherwise test for REX bit is excuse for existence of REX | |
260 | only in case value is nonzero. */ | |
261 | #define USED_REX(value) \ | |
262 | { \ | |
263 | if (value) \ | |
161a04f6 | 264 | { \ |
39fb3698 VM |
265 | if ((ins->rex & value)) \ |
266 | ins->rex_used |= (value) | REX_OPCODE; \ | |
161a04f6 | 267 | } \ |
52b15da3 | 268 | else \ |
39fb3698 | 269 | ins->rex_used |= REX_OPCODE; \ |
52b15da3 JH |
270 | } |
271 | ||
7d421014 | 272 | |
0e4cc773 | 273 | #define EVEX_b_used 1 |
811f61d4 | 274 | #define EVEX_len_used 2 |
0e4cc773 | 275 | |
5076851f ILT |
276 | /* Flags stored in PREFIXES. */ |
277 | #define PREFIX_REPZ 1 | |
278 | #define PREFIX_REPNZ 2 | |
eebc56d6 JB |
279 | #define PREFIX_CS 4 |
280 | #define PREFIX_SS 8 | |
281 | #define PREFIX_DS 0x10 | |
282 | #define PREFIX_ES 0x20 | |
283 | #define PREFIX_FS 0x40 | |
284 | #define PREFIX_GS 0x80 | |
285 | #define PREFIX_LOCK 0x100 | |
5076851f ILT |
286 | #define PREFIX_DATA 0x200 |
287 | #define PREFIX_ADDR 0x400 | |
288 | #define PREFIX_FWAIT 0x800 | |
289 | ||
252b5132 | 290 | /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive) |
a82b3c56 | 291 | to ADDR (exclusive) are valid. Returns true for success, false |
252b5132 | 292 | on error. */ |
06173b5d | 293 | static bool |
1a3b4f90 | 294 | fetch_code (struct disassemble_info *info, const uint8_t *until) |
06173b5d JB |
295 | { |
296 | int status = -1; | |
297 | struct dis_private *priv = info->private_data; | |
1a3b4f90 JB |
298 | bfd_vma start = priv->insn_start + priv->fetched; |
299 | uint8_t *fetch_end = priv->the_buffer + priv->fetched; | |
300 | ptrdiff_t needed = until - fetch_end; | |
06173b5d | 301 | |
1a3b4f90 | 302 | if (needed <= 0) |
06173b5d JB |
303 | return true; |
304 | ||
93497bf9 | 305 | if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer)) |
1a3b4f90 | 306 | status = (*info->read_memory_func) (start, fetch_end, needed, info); |
06173b5d JB |
307 | if (status != 0) |
308 | { | |
309 | /* If we did manage to read at least one byte, then | |
310 | print_insn_i386 will do something sensible. Otherwise, print | |
311 | an error. We do that here because this is where we know | |
312 | STATUS. */ | |
1a3b4f90 | 313 | if (!priv->fetched) |
06173b5d JB |
314 | (*info->memory_error_func) (status, start, info); |
315 | return false; | |
316 | } | |
317 | ||
1a3b4f90 | 318 | priv->fetched += needed; |
06173b5d JB |
319 | return true; |
320 | } | |
321 | ||
322 | static bool | |
323 | fetch_modrm (instr_info *ins) | |
324 | { | |
325 | if (!fetch_code (ins->info, ins->codep + 1)) | |
326 | return false; | |
327 | ||
328 | ins->modrm.mod = (*ins->codep >> 6) & 3; | |
329 | ins->modrm.reg = (*ins->codep >> 3) & 7; | |
330 | ins->modrm.rm = *ins->codep & 7; | |
331 | ||
332 | return true; | |
333 | } | |
334 | ||
4bcbe86c JB |
335 | static int |
336 | fetch_error (const instr_info *ins) | |
337 | { | |
338 | /* Getting here means we tried for data but didn't get it. That | |
339 | means we have an incomplete instruction of some sort. Just | |
340 | print the first byte as a prefix or a .byte pseudo-op. */ | |
341 | const struct dis_private *priv = ins->info->private_data; | |
342 | const char *name = NULL; | |
343 | ||
344 | if (ins->codep <= priv->the_buffer) | |
345 | return -1; | |
346 | ||
347 | if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE)) | |
ffe983ed JB |
348 | name = prefix_name (ins->address_mode, priv->the_buffer[0], |
349 | priv->orig_sizeflag); | |
4bcbe86c | 350 | if (name != NULL) |
e4452aa6 | 351 | i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name); |
4bcbe86c JB |
352 | else |
353 | { | |
354 | /* Just print the first byte as a .byte instruction. */ | |
e4452aa6 JB |
355 | i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte "); |
356 | i386_dis_printf (ins->info, dis_style_immediate, "%#x", | |
4bcbe86c JB |
357 | (unsigned int) priv->the_buffer[0]); |
358 | } | |
359 | ||
360 | return 1; | |
361 | } | |
362 | ||
bf890a93 | 363 | /* Possible values for prefix requirement. */ |
507bd325 L |
364 | #define PREFIX_IGNORED_SHIFT 16 |
365 | #define PREFIX_IGNORED_REPZ (PREFIX_REPZ << PREFIX_IGNORED_SHIFT) | |
366 | #define PREFIX_IGNORED_REPNZ (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT) | |
367 | #define PREFIX_IGNORED_DATA (PREFIX_DATA << PREFIX_IGNORED_SHIFT) | |
368 | #define PREFIX_IGNORED_ADDR (PREFIX_ADDR << PREFIX_IGNORED_SHIFT) | |
369 | #define PREFIX_IGNORED_LOCK (PREFIX_LOCK << PREFIX_IGNORED_SHIFT) | |
370 | ||
371 | /* Opcode prefixes. */ | |
372 | #define PREFIX_OPCODE (PREFIX_REPZ \ | |
373 | | PREFIX_REPNZ \ | |
374 | | PREFIX_DATA) | |
375 | ||
376 | /* Prefixes ignored. */ | |
377 | #define PREFIX_IGNORED (PREFIX_IGNORED_REPZ \ | |
378 | | PREFIX_IGNORED_REPNZ \ | |
379 | | PREFIX_IGNORED_DATA) | |
bf890a93 | 380 | |
ce518a5f | 381 | #define XX { NULL, 0 } |
507bd325 | 382 | #define Bad_Opcode NULL, { { NULL, 0 } }, 0 |
ce518a5f L |
383 | |
384 | #define Eb { OP_E, b_mode } | |
7e8b059b | 385 | #define Ebnd { OP_E, bnd_mode } |
b6169b20 | 386 | #define EbS { OP_E, b_swap_mode } |
9f79e886 | 387 | #define EbndS { OP_E, bnd_swap_mode } |
ce518a5f | 388 | #define Ev { OP_E, v_mode } |
de89d0a3 | 389 | #define Eva { OP_E, va_mode } |
7e8b059b | 390 | #define Ev_bnd { OP_E, v_bnd_mode } |
b6169b20 | 391 | #define EvS { OP_E, v_swap_mode } |
ce518a5f L |
392 | #define Ed { OP_E, d_mode } |
393 | #define Edq { OP_E, dq_mode } | |
1ba585e8 IT |
394 | #define Edb { OP_E, db_mode } |
395 | #define Edw { OP_E, dw_mode } | |
09335d05 | 396 | #define Eq { OP_E, q_mode } |
07f5af7d | 397 | #define indirEv { OP_indirE, indir_v_mode } |
ce518a5f L |
398 | #define indirEp { OP_indirE, f_mode } |
399 | #define stackEv { OP_E, stack_v_mode } | |
400 | #define Em { OP_E, m_mode } | |
401 | #define Ew { OP_E, w_mode } | |
402 | #define M { OP_M, 0 } /* lea, lgdt, etc. */ | |
34b772a6 | 403 | #define Ma { OP_M, a_mode } |
b844680a | 404 | #define Mb { OP_M, b_mode } |
d9a5e5e5 | 405 | #define Md { OP_M, d_mode } |
a93e3234 | 406 | #define Mdq { OP_M, dq_mode } |
f1f8f695 | 407 | #define Mo { OP_M, o_mode } |
ce518a5f L |
408 | #define Mp { OP_M, f_mode } /* 32 or 48 bit memory operand for LDS, LES etc */ |
409 | #define Mq { OP_M, q_mode } | |
9ab00b61 | 410 | #define Mv { OP_M, v_mode } |
d276ec69 | 411 | #define Mv_bnd { OP_M, v_bndmk_mode } |
01d8ce74 | 412 | #define Mw { OP_M, w_mode } |
4ee52178 | 413 | #define Mx { OP_M, x_mode } |
c0f3af97 | 414 | #define Mxmm { OP_M, xmm_mode } |
b5c37946 | 415 | #define Mymm { OP_M, ymm_mode } |
ce518a5f | 416 | #define Gb { OP_G, b_mode } |
7e8b059b | 417 | #define Gbnd { OP_G, bnd_mode } |
ce518a5f L |
418 | #define Gv { OP_G, v_mode } |
419 | #define Gd { OP_G, d_mode } | |
420 | #define Gdq { OP_G, dq_mode } | |
421 | #define Gm { OP_G, m_mode } | |
c0a30a9f | 422 | #define Gva { OP_G, va_mode } |
ce518a5f | 423 | #define Gw { OP_G, w_mode } |
ce518a5f L |
424 | #define Ib { OP_I, b_mode } |
425 | #define sIb { OP_sI, b_mode } /* sign extened byte */ | |
e3949f17 | 426 | #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */ |
ce518a5f | 427 | #define Iv { OP_I, v_mode } |
7bb15c6f | 428 | #define sIv { OP_sI, v_mode } |
ce518a5f | 429 | #define Iv64 { OP_I64, v_mode } |
c1dc7af5 | 430 | #define Id { OP_I, d_mode } |
ce518a5f L |
431 | #define Iw { OP_I, w_mode } |
432 | #define I1 { OP_I, const_1_mode } | |
433 | #define Jb { OP_J, b_mode } | |
434 | #define Jv { OP_J, v_mode } | |
376cd056 | 435 | #define Jdqw { OP_J, dqw_mode } |
ce518a5f L |
436 | #define Cm { OP_C, m_mode } |
437 | #define Dm { OP_D, m_mode } | |
438 | #define Td { OP_T, d_mode } | |
b844680a | 439 | #define Skip_MODRM { OP_Skip_MODRM, 0 } |
ce518a5f L |
440 | |
441 | #define RMeAX { OP_REG, eAX_reg } | |
442 | #define RMeBX { OP_REG, eBX_reg } | |
443 | #define RMeCX { OP_REG, eCX_reg } | |
444 | #define RMeDX { OP_REG, eDX_reg } | |
445 | #define RMeSP { OP_REG, eSP_reg } | |
446 | #define RMeBP { OP_REG, eBP_reg } | |
447 | #define RMeSI { OP_REG, eSI_reg } | |
448 | #define RMeDI { OP_REG, eDI_reg } | |
449 | #define RMrAX { OP_REG, rAX_reg } | |
450 | #define RMrBX { OP_REG, rBX_reg } | |
451 | #define RMrCX { OP_REG, rCX_reg } | |
452 | #define RMrDX { OP_REG, rDX_reg } | |
453 | #define RMrSP { OP_REG, rSP_reg } | |
454 | #define RMrBP { OP_REG, rBP_reg } | |
455 | #define RMrSI { OP_REG, rSI_reg } | |
456 | #define RMrDI { OP_REG, rDI_reg } | |
457 | #define RMAL { OP_REG, al_reg } | |
ce518a5f L |
458 | #define RMCL { OP_REG, cl_reg } |
459 | #define RMDL { OP_REG, dl_reg } | |
460 | #define RMBL { OP_REG, bl_reg } | |
461 | #define RMAH { OP_REG, ah_reg } | |
462 | #define RMCH { OP_REG, ch_reg } | |
463 | #define RMDH { OP_REG, dh_reg } | |
464 | #define RMBH { OP_REG, bh_reg } | |
465 | #define RMAX { OP_REG, ax_reg } | |
466 | #define RMDX { OP_REG, dx_reg } | |
467 | ||
468 | #define eAX { OP_IMREG, eAX_reg } | |
ce518a5f L |
469 | #define AL { OP_IMREG, al_reg } |
470 | #define CL { OP_IMREG, cl_reg } | |
ce518a5f L |
471 | #define zAX { OP_IMREG, z_mode_ax_reg } |
472 | #define indirDX { OP_IMREG, indir_dx_reg } | |
473 | ||
474 | #define Sw { OP_SEG, w_mode } | |
475 | #define Sv { OP_SEG, v_mode } | |
476 | #define Ap { OP_DIR, 0 } | |
477 | #define Ob { OP_OFF64, b_mode } | |
478 | #define Ov { OP_OFF64, v_mode } | |
479 | #define Xb { OP_DSreg, eSI_reg } | |
480 | #define Xv { OP_DSreg, eSI_reg } | |
481 | #define Xz { OP_DSreg, eSI_reg } | |
482 | #define Yb { OP_ESreg, eDI_reg } | |
483 | #define Yv { OP_ESreg, eDI_reg } | |
484 | #define DSBX { OP_DSreg, eBX_reg } | |
485 | ||
486 | #define es { OP_REG, es_reg } | |
487 | #define ss { OP_REG, ss_reg } | |
488 | #define cs { OP_REG, cs_reg } | |
489 | #define ds { OP_REG, ds_reg } | |
490 | #define fs { OP_REG, fs_reg } | |
491 | #define gs { OP_REG, gs_reg } | |
492 | ||
493 | #define MX { OP_MMX, 0 } | |
494 | #define XM { OP_XMM, 0 } | |
539f890d | 495 | #define XMScalar { OP_XMM, scalar_mode } |
596a02ff | 496 | #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode } |
6c30d220 | 497 | #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode } |
c0f3af97 | 498 | #define XMM { OP_XMM, xmm_mode } |
260cd341 | 499 | #define TMM { OP_XMM, tmm_mode } |
43234a1e | 500 | #define XMxmmq { OP_XMM, xmmq_mode } |
ce518a5f | 501 | #define EM { OP_EM, v_mode } |
b6169b20 | 502 | #define EMS { OP_EM, v_swap_mode } |
09a2c6cf | 503 | #define EMd { OP_EM, d_mode } |
14051056 | 504 | #define EMx { OP_EM, x_mode } |
4726e9a4 | 505 | #define EXbwUnit { OP_EX, bw_unit_mode } |
c1d66d5f | 506 | #define EXb { OP_EX, b_mode } |
8976381e | 507 | #define EXw { OP_EX, w_mode } |
09a2c6cf | 508 | #define EXd { OP_EX, d_mode } |
fa99fab2 | 509 | #define EXdS { OP_EX, d_swap_mode } |
0cc78721 | 510 | #define EXwS { OP_EX, w_swap_mode } |
09a2c6cf | 511 | #define EXq { OP_EX, q_mode } |
b6169b20 | 512 | #define EXqS { OP_EX, q_swap_mode } |
eb34d29b | 513 | #define EXdq { OP_EX, dq_mode } |
09a2c6cf | 514 | #define EXx { OP_EX, x_mode } |
0cc78721 | 515 | #define EXxh { OP_EX, xh_mode } |
b6169b20 | 516 | #define EXxS { OP_EX, x_swap_mode } |
c0f3af97 | 517 | #define EXxmm { OP_EX, xmm_mode } |
43234a1e | 518 | #define EXymm { OP_EX, ymm_mode } |
c0f3af97 | 519 | #define EXxmmq { OP_EX, xmmq_mode } |
0cc78721 | 520 | #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode } |
43234a1e | 521 | #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode } |
6c30d220 L |
522 | #define EXxmmdw { OP_EX, xmmdw_mode } |
523 | #define EXxmmqd { OP_EX, xmmqd_mode } | |
0cc78721 | 524 | #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode } |
c0f3af97 | 525 | #define EXymmq { OP_EX, ymmq_mode } |
43234a1e L |
526 | #define EXEvexXGscat { OP_EX, evex_x_gscat_mode } |
527 | #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode } | |
b5c37946 SJ |
528 | #define Rd { OP_R, d_mode } |
529 | #define Rdq { OP_R, dq_mode } | |
530 | #define Nq { OP_R, q_mode } | |
531 | #define Ux { OP_R, x_mode } | |
532 | #define Uxmm { OP_R, xmm_mode } | |
533 | #define Rxmmq { OP_R, xmmq_mode } | |
534 | #define Rymm { OP_R, ymm_mode } | |
535 | #define Rtmm { OP_R, tmm_mode } | |
09335d05 | 536 | #define EMCq { OP_EMC, q_mode } |
ce518a5f | 537 | #define MXC { OP_MXC, 0 } |
ce518a5f | 538 | #define OPSUF { OP_3DNowSuffix, 0 } |
d835a58b | 539 | #define SEP { SEP_Fixup, 0 } |
ad19981d | 540 | #define CMP { CMP_Fixup, 0 } |
42903f7f | 541 | #define XMM0 { XMM_Fixup, 0 } |
eacc9c89 | 542 | #define FXSAVE { FXSAVE_Fixup, 0 } |
252b5132 | 543 | |
605228fc JB |
544 | #define Vex { OP_VEX, x_mode } |
545 | #define VexW { OP_VexW, x_mode } | |
546 | #define VexScalar { OP_VEX, scalar_mode } | |
547 | #define VexScalarR { OP_VexR, scalar_mode } | |
596a02ff | 548 | #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode } |
6c30d220 | 549 | #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode } |
cb21baef | 550 | #define VexGdq { OP_VEX, dq_mode } |
260cd341 | 551 | #define VexTmm { OP_VEX, tmm_mode } |
c0f3af97 | 552 | #define XMVexI4 { OP_REG_VexI4, x_mode } |
6384fd9e | 553 | #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode } |
93abb146 | 554 | #define VexI4 { OP_VexI4, 0 } |
c0f3af97 | 555 | #define PCLMUL { PCLMUL_Fixup, 0 } |
43234a1e | 556 | #define VPCMP { VPCMP_Fixup, 0 } |
be92cb14 | 557 | #define VPCOM { VPCOM_Fixup, 0 } |
43234a1e L |
558 | |
559 | #define EXxEVexR { OP_Rounding, evex_rounding_mode } | |
70df6fc9 | 560 | #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode } |
43234a1e L |
561 | #define EXxEVexS { OP_Rounding, evex_sae_mode } |
562 | ||
43234a1e L |
563 | #define MaskG { OP_G, mask_mode } |
564 | #define MaskE { OP_E, mask_mode } | |
b5c37946 | 565 | #define MaskR { OP_R, mask_mode } |
1ba585e8 | 566 | #define MaskBDE { OP_E, mask_bd_mode } |
43234a1e | 567 | #define MaskVex { OP_VEX, mask_mode } |
c0f3af97 | 568 | |
6c30d220 L |
569 | #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode } |
570 | #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode } | |
571 | ||
260cd341 LC |
572 | #define MVexSIBMEM { OP_M, vex_sibmem_mode } |
573 | ||
35c52694 | 574 | /* Used handle "rep" prefix for string instructions. */ |
ce518a5f L |
575 | #define Xbr { REP_Fixup, eSI_reg } |
576 | #define Xvr { REP_Fixup, eSI_reg } | |
577 | #define Ybr { REP_Fixup, eDI_reg } | |
578 | #define Yvr { REP_Fixup, eDI_reg } | |
579 | #define Yzr { REP_Fixup, eDI_reg } | |
580 | #define indirDXr { REP_Fixup, indir_dx_reg } | |
581 | #define ALr { REP_Fixup, al_reg } | |
582 | #define eAXr { REP_Fixup, eAX_reg } | |
583 | ||
42164a71 L |
584 | /* Used handle HLE prefix for lockable instructions. */ |
585 | #define Ebh1 { HLE_Fixup1, b_mode } | |
586 | #define Evh1 { HLE_Fixup1, v_mode } | |
587 | #define Ebh2 { HLE_Fixup2, b_mode } | |
588 | #define Evh2 { HLE_Fixup2, v_mode } | |
589 | #define Ebh3 { HLE_Fixup3, b_mode } | |
590 | #define Evh3 { HLE_Fixup3, v_mode } | |
591 | ||
7e8b059b | 592 | #define BND { BND_Fixup, 0 } |
04ef582a | 593 | #define NOTRACK { NOTRACK_Fixup, 0 } |
7e8b059b | 594 | |
ce518a5f L |
595 | #define cond_jump_flag { NULL, cond_jump_mode } |
596 | #define loop_jcxz_flag { NULL, loop_jcxz_mode } | |
3ffd33cf | 597 | |
252b5132 | 598 | /* bits in sizeflag */ |
252b5132 | 599 | #define SUFFIX_ALWAYS 4 |
252b5132 RH |
600 | #define AFLAG 2 |
601 | #define DFLAG 1 | |
602 | ||
51e7da1b L |
603 | enum |
604 | { | |
605 | /* byte operand */ | |
606 | b_mode = 1, | |
607 | /* byte operand with operand swapped */ | |
3873ba12 | 608 | b_swap_mode, |
e3949f17 L |
609 | /* byte operand, sign extend like 'T' suffix */ |
610 | b_T_mode, | |
51e7da1b | 611 | /* operand size depends on prefixes */ |
3873ba12 | 612 | v_mode, |
51e7da1b | 613 | /* operand size depends on prefixes with operand swapped */ |
3873ba12 | 614 | v_swap_mode, |
de89d0a3 IT |
615 | /* operand size depends on address prefix */ |
616 | va_mode, | |
51e7da1b | 617 | /* word operand */ |
3873ba12 | 618 | w_mode, |
51e7da1b | 619 | /* double word operand */ |
3873ba12 | 620 | d_mode, |
0cc78721 CL |
621 | /* word operand with operand swapped */ |
622 | w_swap_mode, | |
51e7da1b | 623 | /* double word operand with operand swapped */ |
3873ba12 | 624 | d_swap_mode, |
51e7da1b | 625 | /* quad word operand */ |
3873ba12 | 626 | q_mode, |
51e7da1b | 627 | /* quad word operand with operand swapped */ |
3873ba12 | 628 | q_swap_mode, |
51e7da1b | 629 | /* ten-byte operand */ |
3873ba12 | 630 | t_mode, |
43234a1e L |
631 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
632 | broadcast enabled. */ | |
3873ba12 | 633 | x_mode, |
43234a1e L |
634 | /* Similar to x_mode, but with different EVEX mem shifts. */ |
635 | evex_x_gscat_mode, | |
4726e9a4 JB |
636 | /* Similar to x_mode, but with yet different EVEX mem shifts. */ |
637 | bw_unit_mode, | |
43234a1e L |
638 | /* Similar to x_mode, but with disabled broadcast. */ |
639 | evex_x_nobcst_mode, | |
640 | /* Similar to x_mode, but with operands swapped and disabled broadcast | |
641 | in EVEX. */ | |
3873ba12 | 642 | x_swap_mode, |
0cc78721 CL |
643 | /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand. In EVEX with |
644 | broadcast of 16bit enabled. */ | |
645 | xh_mode, | |
51e7da1b | 646 | /* 16-byte XMM operand */ |
3873ba12 | 647 | xmm_mode, |
43234a1e L |
648 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
649 | memory operand (depending on vector length). Broadcast isn't | |
650 | allowed. */ | |
3873ba12 | 651 | xmmq_mode, |
43234a1e L |
652 | /* Same as xmmq_mode, but broadcast is allowed. */ |
653 | evex_half_bcst_xmmq_mode, | |
0cc78721 CL |
654 | /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword |
655 | memory operand (depending on vector length). 16bit broadcast. */ | |
656 | evex_half_bcst_xmmqh_mode, | |
43234a1e | 657 | /* 16-byte XMM, word, double word or quad word operand. */ |
6c30d220 | 658 | xmmdw_mode, |
43234a1e | 659 | /* 16-byte XMM, double word, quad word operand or xmm word operand. */ |
6c30d220 | 660 | xmmqd_mode, |
0cc78721 CL |
661 | /* 16-byte XMM, double word, quad word operand or xmm word operand. |
662 | 16bit broadcast. */ | |
663 | evex_half_bcst_xmmqdh_mode, | |
43234a1e L |
664 | /* 32-byte YMM operand */ |
665 | ymm_mode, | |
666 | /* quad word, ymmword or zmmword memory operand. */ | |
3873ba12 | 667 | ymmq_mode, |
260cd341 LC |
668 | /* TMM operand */ |
669 | tmm_mode, | |
51e7da1b | 670 | /* d_mode in 32bit, q_mode in 64bit mode. */ |
3873ba12 | 671 | m_mode, |
51e7da1b | 672 | /* pair of v_mode operands */ |
3873ba12 L |
673 | a_mode, |
674 | cond_jump_mode, | |
675 | loop_jcxz_mode, | |
bc31405e | 676 | movsxd_mode, |
7e8b059b | 677 | v_bnd_mode, |
d276ec69 JB |
678 | /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode. */ |
679 | v_bndmk_mode, | |
eb34d29b | 680 | /* operand size depends on REX.W / VEX.W. */ |
3873ba12 | 681 | dq_mode, |
5fbe0f28 | 682 | /* Displacements like v_mode without considering Intel64 ISA. */ |
3873ba12 | 683 | dqw_mode, |
9f79e886 | 684 | /* bounds operand */ |
7e8b059b | 685 | bnd_mode, |
9f79e886 JB |
686 | /* bounds operand with operand swapped */ |
687 | bnd_swap_mode, | |
51e7da1b | 688 | /* 4- or 6-byte pointer operand */ |
3873ba12 L |
689 | f_mode, |
690 | const_1_mode, | |
07f5af7d L |
691 | /* v_mode for indirect branch opcodes. */ |
692 | indir_v_mode, | |
51e7da1b | 693 | /* v_mode for stack-related opcodes. */ |
3873ba12 | 694 | stack_v_mode, |
51e7da1b | 695 | /* non-quad operand size depends on prefixes */ |
3873ba12 | 696 | z_mode, |
51e7da1b | 697 | /* 16-byte operand */ |
3873ba12 | 698 | o_mode, |
1ba585e8 IT |
699 | /* registers like d_mode, memory like b_mode. */ |
700 | db_mode, | |
701 | /* registers like d_mode, memory like w_mode. */ | |
702 | dw_mode, | |
d55ee72f | 703 | |
825bd36c | 704 | /* Operand size depends on the VEX.W bit, with VSIB dword indices. */ |
6c30d220 | 705 | vex_vsib_d_w_dq_mode, |
825bd36c | 706 | /* Operand size depends on the VEX.W bit, with VSIB qword indices. */ |
6c30d220 | 707 | vex_vsib_q_w_dq_mode, |
260cd341 LC |
708 | /* mandatory non-vector SIB. */ |
709 | vex_sibmem_mode, | |
6c30d220 | 710 | |
539f890d L |
711 | /* scalar, ignore vector length. */ |
712 | scalar_mode, | |
539f890d | 713 | |
43234a1e L |
714 | /* Static rounding. */ |
715 | evex_rounding_mode, | |
70df6fc9 L |
716 | /* Static rounding, 64-bit mode only. */ |
717 | evex_rounding_64_mode, | |
43234a1e L |
718 | /* Supress all exceptions. */ |
719 | evex_sae_mode, | |
720 | ||
721 | /* Mask register operand. */ | |
722 | mask_mode, | |
1ba585e8 IT |
723 | /* Mask register operand. */ |
724 | mask_bd_mode, | |
43234a1e | 725 | |
3873ba12 L |
726 | es_reg, |
727 | cs_reg, | |
728 | ss_reg, | |
729 | ds_reg, | |
730 | fs_reg, | |
731 | gs_reg, | |
d55ee72f | 732 | |
3873ba12 L |
733 | eAX_reg, |
734 | eCX_reg, | |
735 | eDX_reg, | |
736 | eBX_reg, | |
737 | eSP_reg, | |
738 | eBP_reg, | |
739 | eSI_reg, | |
740 | eDI_reg, | |
d55ee72f | 741 | |
3873ba12 L |
742 | al_reg, |
743 | cl_reg, | |
744 | dl_reg, | |
745 | bl_reg, | |
746 | ah_reg, | |
747 | ch_reg, | |
748 | dh_reg, | |
749 | bh_reg, | |
d55ee72f | 750 | |
3873ba12 L |
751 | ax_reg, |
752 | cx_reg, | |
753 | dx_reg, | |
754 | bx_reg, | |
755 | sp_reg, | |
756 | bp_reg, | |
757 | si_reg, | |
758 | di_reg, | |
d55ee72f | 759 | |
3873ba12 L |
760 | rAX_reg, |
761 | rCX_reg, | |
762 | rDX_reg, | |
763 | rBX_reg, | |
764 | rSP_reg, | |
765 | rBP_reg, | |
766 | rSI_reg, | |
767 | rDI_reg, | |
d55ee72f | 768 | |
3873ba12 L |
769 | z_mode_ax_reg, |
770 | indir_dx_reg | |
51e7da1b | 771 | }; |
252b5132 | 772 | |
51e7da1b L |
773 | enum |
774 | { | |
775 | FLOATCODE = 1, | |
3873ba12 L |
776 | USE_REG_TABLE, |
777 | USE_MOD_TABLE, | |
778 | USE_RM_TABLE, | |
779 | USE_PREFIX_TABLE, | |
780 | USE_X86_64_TABLE, | |
781 | USE_3BYTE_TABLE, | |
f88c9eb0 | 782 | USE_XOP_8F_TABLE, |
3873ba12 L |
783 | USE_VEX_C4_TABLE, |
784 | USE_VEX_C5_TABLE, | |
9e30b8e0 | 785 | USE_VEX_LEN_TABLE, |
43234a1e | 786 | USE_VEX_W_TABLE, |
04e2a182 L |
787 | USE_EVEX_TABLE, |
788 | USE_EVEX_LEN_TABLE | |
51e7da1b | 789 | }; |
6439fc28 | 790 | |
bf890a93 | 791 | #define FLOAT NULL, { { NULL, FLOATCODE } }, 0 |
4efba78c | 792 | |
bf890a93 | 793 | #define DIS386(T, I) NULL, { { NULL, (T)}, { NULL, (I) } }, 0 |
1ceb70f8 L |
794 | #define REG_TABLE(I) DIS386 (USE_REG_TABLE, (I)) |
795 | #define MOD_TABLE(I) DIS386 (USE_MOD_TABLE, (I)) | |
796 | #define RM_TABLE(I) DIS386 (USE_RM_TABLE, (I)) | |
797 | #define PREFIX_TABLE(I) DIS386 (USE_PREFIX_TABLE, (I)) | |
4e7d34a6 L |
798 | #define X86_64_TABLE(I) DIS386 (USE_X86_64_TABLE, (I)) |
799 | #define THREE_BYTE_TABLE(I) DIS386 (USE_3BYTE_TABLE, (I)) | |
b5c37946 SJ |
800 | #define XOP_8F_TABLE() DIS386 (USE_XOP_8F_TABLE, 0) |
801 | #define VEX_C4_TABLE() DIS386 (USE_VEX_C4_TABLE, 0) | |
802 | #define VEX_C5_TABLE() DIS386 (USE_VEX_C5_TABLE, 0) | |
c0f3af97 | 803 | #define VEX_LEN_TABLE(I) DIS386 (USE_VEX_LEN_TABLE, (I)) |
9e30b8e0 | 804 | #define VEX_W_TABLE(I) DIS386 (USE_VEX_W_TABLE, (I)) |
b5c37946 | 805 | #define EVEX_TABLE() DIS386 (USE_EVEX_TABLE, 0) |
04e2a182 | 806 | #define EVEX_LEN_TABLE(I) DIS386 (USE_EVEX_LEN_TABLE, (I)) |
1ceb70f8 | 807 | |
51e7da1b L |
808 | enum |
809 | { | |
810 | REG_80 = 0, | |
3873ba12 | 811 | REG_81, |
7148c369 | 812 | REG_83, |
3873ba12 L |
813 | REG_8F, |
814 | REG_C0, | |
815 | REG_C1, | |
816 | REG_C6, | |
817 | REG_C7, | |
818 | REG_D0, | |
819 | REG_D1, | |
820 | REG_D2, | |
821 | REG_D3, | |
822 | REG_F6, | |
823 | REG_F7, | |
824 | REG_FE, | |
825 | REG_FF, | |
826 | REG_0F00, | |
827 | REG_0F01, | |
828 | REG_0F0D, | |
829 | REG_0F18, | |
f8687e93 JB |
830 | REG_0F1C_P_0_MOD_0, |
831 | REG_0F1E_P_1_MOD_3, | |
c4694f17 | 832 | REG_0F38D8_PREFIX_1, |
b5c37946 SJ |
833 | REG_0F3A0F_P_1, |
834 | REG_0F71, | |
835 | REG_0F72, | |
836 | REG_0F73, | |
3873ba12 L |
837 | REG_0FA6, |
838 | REG_0FA7, | |
839 | REG_0FAE, | |
840 | REG_0FBA, | |
841 | REG_0FC7, | |
b5c37946 SJ |
842 | REG_VEX_0F71, |
843 | REG_VEX_0F72, | |
844 | REG_VEX_0F73, | |
592a252b | 845 | REG_VEX_0FAE, |
1f506c06 | 846 | REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0, |
14d10c6c | 847 | REG_VEX_0F38F3_L_0, |
467bbef0 | 848 | |
32e31ad7 JB |
849 | REG_XOP_09_01_L_0, |
850 | REG_XOP_09_02_L_0, | |
b5c37946 | 851 | REG_XOP_09_12_L_0, |
32e31ad7 | 852 | REG_XOP_0A_12_L_0, |
43234a1e | 853 | |
1ba585e8 | 854 | REG_EVEX_0F71, |
43234a1e L |
855 | REG_EVEX_0F72, |
856 | REG_EVEX_0F73, | |
b5c37946 SJ |
857 | REG_EVEX_0F38C6_L_2, |
858 | REG_EVEX_0F38C7_L_2 | |
51e7da1b | 859 | }; |
1ceb70f8 | 860 | |
51e7da1b L |
861 | enum |
862 | { | |
32e31ad7 | 863 | MOD_62_32BIT = 0, |
32e31ad7 JB |
864 | MOD_C4_32BIT, |
865 | MOD_C5_32BIT, | |
3873ba12 L |
866 | MOD_0F01_REG_0, |
867 | MOD_0F01_REG_1, | |
868 | MOD_0F01_REG_2, | |
869 | MOD_0F01_REG_3, | |
8eab4136 | 870 | MOD_0F01_REG_5, |
3873ba12 L |
871 | MOD_0F01_REG_7, |
872 | MOD_0F12_PREFIX_0, | |
3873ba12 | 873 | MOD_0F16_PREFIX_0, |
3873ba12 L |
874 | MOD_0F18_REG_0, |
875 | MOD_0F18_REG_1, | |
876 | MOD_0F18_REG_2, | |
877 | MOD_0F18_REG_3, | |
ef07be45 CL |
878 | MOD_0F18_REG_6, |
879 | MOD_0F18_REG_7, | |
7e8b059b L |
880 | MOD_0F1A_PREFIX_0, |
881 | MOD_0F1B_PREFIX_0, | |
882 | MOD_0F1B_PREFIX_1, | |
c48935d7 | 883 | MOD_0F1C_PREFIX_0, |
603555e5 | 884 | MOD_0F1E_PREFIX_1, |
3873ba12 L |
885 | MOD_0FAE_REG_0, |
886 | MOD_0FAE_REG_1, | |
887 | MOD_0FAE_REG_2, | |
888 | MOD_0FAE_REG_3, | |
889 | MOD_0FAE_REG_4, | |
890 | MOD_0FAE_REG_5, | |
891 | MOD_0FAE_REG_6, | |
892 | MOD_0FAE_REG_7, | |
3873ba12 L |
893 | MOD_0FC7_REG_6, |
894 | MOD_0FC7_REG_7, | |
c4694f17 | 895 | MOD_0F38DC_PREFIX_1, |
b5c37946 | 896 | |
1f506c06 | 897 | MOD_VEX_0F3849_X86_64_L_0_W_0, |
51e7da1b | 898 | }; |
1ceb70f8 | 899 | |
51e7da1b L |
900 | enum |
901 | { | |
42164a71 L |
902 | RM_C6_REG_7 = 0, |
903 | RM_C7_REG_7, | |
904 | RM_0F01_REG_0, | |
3873ba12 L |
905 | RM_0F01_REG_1, |
906 | RM_0F01_REG_2, | |
907 | RM_0F01_REG_3, | |
f8687e93 JB |
908 | RM_0F01_REG_5_MOD_3, |
909 | RM_0F01_REG_7_MOD_3, | |
910 | RM_0F1E_P_1_MOD_3_REG_7, | |
911 | RM_0FAE_REG_6_MOD_3_P_0, | |
912 | RM_0FAE_REG_7_MOD_3, | |
b5c37946 | 913 | RM_0F3A0F_P_1_R_0, |
32e31ad7 | 914 | |
1f506c06 JB |
915 | RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0, |
916 | RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3, | |
51e7da1b | 917 | }; |
1ceb70f8 | 918 | |
51e7da1b L |
919 | enum |
920 | { | |
921 | PREFIX_90 = 0, | |
c88ed92f | 922 | PREFIX_0F00_REG_6_X86_64, |
941f0833 | 923 | PREFIX_0F01_REG_0_MOD_3_RM_6, |
b5c37946 | 924 | PREFIX_0F01_REG_0_MOD_3_RM_7, |
c88ed92f | 925 | PREFIX_0F01_REG_1_RM_2, |
81d54bb7 CL |
926 | PREFIX_0F01_REG_1_RM_4, |
927 | PREFIX_0F01_REG_1_RM_5, | |
928 | PREFIX_0F01_REG_1_RM_6, | |
929 | PREFIX_0F01_REG_1_RM_7, | |
a847e322 | 930 | PREFIX_0F01_REG_3_RM_1, |
f8687e93 JB |
931 | PREFIX_0F01_REG_5_MOD_0, |
932 | PREFIX_0F01_REG_5_MOD_3_RM_0, | |
bb651e8b | 933 | PREFIX_0F01_REG_5_MOD_3_RM_1, |
f8687e93 | 934 | PREFIX_0F01_REG_5_MOD_3_RM_2, |
f64c42a9 LC |
935 | PREFIX_0F01_REG_5_MOD_3_RM_4, |
936 | PREFIX_0F01_REG_5_MOD_3_RM_5, | |
937 | PREFIX_0F01_REG_5_MOD_3_RM_6, | |
938 | PREFIX_0F01_REG_5_MOD_3_RM_7, | |
267b8516 | 939 | PREFIX_0F01_REG_7_MOD_3_RM_2, |
b0e8fa7f | 940 | PREFIX_0F01_REG_7_MOD_3_RM_5, |
646cc3e0 GG |
941 | PREFIX_0F01_REG_7_MOD_3_RM_6, |
942 | PREFIX_0F01_REG_7_MOD_3_RM_7, | |
3233d7d0 | 943 | PREFIX_0F09, |
3873ba12 L |
944 | PREFIX_0F10, |
945 | PREFIX_0F11, | |
946 | PREFIX_0F12, | |
947 | PREFIX_0F16, | |
ef07be45 CL |
948 | PREFIX_0F18_REG_6_MOD_0_X86_64, |
949 | PREFIX_0F18_REG_7_MOD_0_X86_64, | |
7e8b059b L |
950 | PREFIX_0F1A, |
951 | PREFIX_0F1B, | |
c48935d7 | 952 | PREFIX_0F1C, |
603555e5 | 953 | PREFIX_0F1E, |
3873ba12 L |
954 | PREFIX_0F2A, |
955 | PREFIX_0F2B, | |
956 | PREFIX_0F2C, | |
957 | PREFIX_0F2D, | |
958 | PREFIX_0F2E, | |
959 | PREFIX_0F2F, | |
960 | PREFIX_0F51, | |
961 | PREFIX_0F52, | |
962 | PREFIX_0F53, | |
963 | PREFIX_0F58, | |
964 | PREFIX_0F59, | |
965 | PREFIX_0F5A, | |
966 | PREFIX_0F5B, | |
967 | PREFIX_0F5C, | |
968 | PREFIX_0F5D, | |
969 | PREFIX_0F5E, | |
970 | PREFIX_0F5F, | |
971 | PREFIX_0F60, | |
972 | PREFIX_0F61, | |
973 | PREFIX_0F62, | |
3873ba12 L |
974 | PREFIX_0F6F, |
975 | PREFIX_0F70, | |
3873ba12 L |
976 | PREFIX_0F78, |
977 | PREFIX_0F79, | |
978 | PREFIX_0F7C, | |
979 | PREFIX_0F7D, | |
980 | PREFIX_0F7E, | |
981 | PREFIX_0F7F, | |
f8687e93 JB |
982 | PREFIX_0FAE_REG_0_MOD_3, |
983 | PREFIX_0FAE_REG_1_MOD_3, | |
984 | PREFIX_0FAE_REG_2_MOD_3, | |
985 | PREFIX_0FAE_REG_3_MOD_3, | |
986 | PREFIX_0FAE_REG_4_MOD_0, | |
987 | PREFIX_0FAE_REG_4_MOD_3, | |
f8687e93 JB |
988 | PREFIX_0FAE_REG_5_MOD_3, |
989 | PREFIX_0FAE_REG_6_MOD_0, | |
990 | PREFIX_0FAE_REG_6_MOD_3, | |
991 | PREFIX_0FAE_REG_7_MOD_0, | |
3873ba12 | 992 | PREFIX_0FB8, |
f12dc422 | 993 | PREFIX_0FBC, |
3873ba12 L |
994 | PREFIX_0FBD, |
995 | PREFIX_0FC2, | |
f8687e93 JB |
996 | PREFIX_0FC7_REG_6_MOD_0, |
997 | PREFIX_0FC7_REG_6_MOD_3, | |
998 | PREFIX_0FC7_REG_7_MOD_3, | |
3873ba12 L |
999 | PREFIX_0FD0, |
1000 | PREFIX_0FD6, | |
1001 | PREFIX_0FE6, | |
1002 | PREFIX_0FE7, | |
1003 | PREFIX_0FF0, | |
1004 | PREFIX_0FF7, | |
c4694f17 TG |
1005 | PREFIX_0F38D8, |
1006 | PREFIX_0F38DC, | |
1007 | PREFIX_0F38DD, | |
1008 | PREFIX_0F38DE, | |
1009 | PREFIX_0F38DF, | |
3873ba12 L |
1010 | PREFIX_0F38F0, |
1011 | PREFIX_0F38F1, | |
e2e1fcde | 1012 | PREFIX_0F38F6, |
c0a30a9f | 1013 | PREFIX_0F38F8, |
c4694f17 TG |
1014 | PREFIX_0F38FA, |
1015 | PREFIX_0F38FB, | |
b06311ad | 1016 | PREFIX_0F38FC, |
c1fa250a | 1017 | PREFIX_0F3A0F, |
592a252b L |
1018 | PREFIX_VEX_0F12, |
1019 | PREFIX_VEX_0F16, | |
1020 | PREFIX_VEX_0F2A, | |
1021 | PREFIX_VEX_0F2C, | |
1022 | PREFIX_VEX_0F2D, | |
b5c37946 SJ |
1023 | PREFIX_VEX_0F41_L_1_W_0, |
1024 | PREFIX_VEX_0F41_L_1_W_1, | |
1025 | PREFIX_VEX_0F42_L_1_W_0, | |
1026 | PREFIX_VEX_0F42_L_1_W_1, | |
1027 | PREFIX_VEX_0F44_L_0_W_0, | |
1028 | PREFIX_VEX_0F44_L_0_W_1, | |
1029 | PREFIX_VEX_0F45_L_1_W_0, | |
1030 | PREFIX_VEX_0F45_L_1_W_1, | |
1031 | PREFIX_VEX_0F46_L_1_W_0, | |
1032 | PREFIX_VEX_0F46_L_1_W_1, | |
1033 | PREFIX_VEX_0F47_L_1_W_0, | |
1034 | PREFIX_VEX_0F47_L_1_W_1, | |
1035 | PREFIX_VEX_0F4A_L_1_W_0, | |
1036 | PREFIX_VEX_0F4A_L_1_W_1, | |
1037 | PREFIX_VEX_0F4B_L_1_W_0, | |
1038 | PREFIX_VEX_0F4B_L_1_W_1, | |
592a252b L |
1039 | PREFIX_VEX_0F6F, |
1040 | PREFIX_VEX_0F70, | |
592a252b L |
1041 | PREFIX_VEX_0F7E, |
1042 | PREFIX_VEX_0F7F, | |
13954a31 JB |
1043 | PREFIX_VEX_0F90_L_0_W_0, |
1044 | PREFIX_VEX_0F90_L_0_W_1, | |
b5c37946 SJ |
1045 | PREFIX_VEX_0F91_L_0_W_0, |
1046 | PREFIX_VEX_0F91_L_0_W_1, | |
1047 | PREFIX_VEX_0F92_L_0_W_0, | |
1048 | PREFIX_VEX_0F92_L_0_W_1, | |
1049 | PREFIX_VEX_0F93_L_0_W_0, | |
1050 | PREFIX_VEX_0F93_L_0_W_1, | |
1051 | PREFIX_VEX_0F98_L_0_W_0, | |
1052 | PREFIX_VEX_0F98_L_0_W_1, | |
1053 | PREFIX_VEX_0F99_L_0_W_0, | |
1054 | PREFIX_VEX_0F99_L_0_W_1, | |
1f506c06 JB |
1055 | PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0, |
1056 | PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1, | |
b5c37946 | 1057 | PREFIX_VEX_0F384B_X86_64_L_0_W_0, |
23ae61ad CL |
1058 | PREFIX_VEX_0F3850_W_0, |
1059 | PREFIX_VEX_0F3851_W_0, | |
b5c37946 SJ |
1060 | PREFIX_VEX_0F385C_X86_64_L_0_W_0, |
1061 | PREFIX_VEX_0F385E_X86_64_L_0_W_0, | |
1062 | PREFIX_VEX_0F386C_X86_64_L_0_W_0, | |
01d8ce74 | 1063 | PREFIX_VEX_0F3872, |
1064 | PREFIX_VEX_0F38B0_W_0, | |
1065 | PREFIX_VEX_0F38B1_W_0, | |
b5c37946 SJ |
1066 | PREFIX_VEX_0F38D2_W_0, |
1067 | PREFIX_VEX_0F38D3_W_0, | |
1068 | PREFIX_VEX_0F38CB, | |
1069 | PREFIX_VEX_0F38CC, | |
1070 | PREFIX_VEX_0F38CD, | |
1071 | PREFIX_VEX_0F38DA_W_0, | |
14d10c6c JB |
1072 | PREFIX_VEX_0F38F5_L_0, |
1073 | PREFIX_VEX_0F38F6_L_0, | |
1074 | PREFIX_VEX_0F38F7_L_0, | |
1075 | PREFIX_VEX_0F3AF0_L_0, | |
43234a1e | 1076 | |
43234a1e | 1077 | PREFIX_EVEX_0F5B, |
43234a1e L |
1078 | PREFIX_EVEX_0F6F, |
1079 | PREFIX_EVEX_0F70, | |
43234a1e L |
1080 | PREFIX_EVEX_0F78, |
1081 | PREFIX_EVEX_0F79, | |
1082 | PREFIX_EVEX_0F7A, | |
1083 | PREFIX_EVEX_0F7B, | |
1084 | PREFIX_EVEX_0F7E, | |
1085 | PREFIX_EVEX_0F7F, | |
1086 | PREFIX_EVEX_0FC2, | |
43234a1e | 1087 | PREFIX_EVEX_0FE6, |
1ba585e8 | 1088 | PREFIX_EVEX_0F3810, |
43234a1e L |
1089 | PREFIX_EVEX_0F3811, |
1090 | PREFIX_EVEX_0F3812, | |
1091 | PREFIX_EVEX_0F3813, | |
1092 | PREFIX_EVEX_0F3814, | |
1093 | PREFIX_EVEX_0F3815, | |
1ba585e8 | 1094 | PREFIX_EVEX_0F3820, |
43234a1e L |
1095 | PREFIX_EVEX_0F3821, |
1096 | PREFIX_EVEX_0F3822, | |
1097 | PREFIX_EVEX_0F3823, | |
1098 | PREFIX_EVEX_0F3824, | |
1099 | PREFIX_EVEX_0F3825, | |
1ba585e8 | 1100 | PREFIX_EVEX_0F3826, |
43234a1e L |
1101 | PREFIX_EVEX_0F3827, |
1102 | PREFIX_EVEX_0F3828, | |
1103 | PREFIX_EVEX_0F3829, | |
1104 | PREFIX_EVEX_0F382A, | |
1ba585e8 | 1105 | PREFIX_EVEX_0F3830, |
43234a1e L |
1106 | PREFIX_EVEX_0F3831, |
1107 | PREFIX_EVEX_0F3832, | |
1108 | PREFIX_EVEX_0F3833, | |
1109 | PREFIX_EVEX_0F3834, | |
1110 | PREFIX_EVEX_0F3835, | |
1ba585e8 | 1111 | PREFIX_EVEX_0F3838, |
43234a1e L |
1112 | PREFIX_EVEX_0F3839, |
1113 | PREFIX_EVEX_0F383A, | |
47acf0bd IT |
1114 | PREFIX_EVEX_0F3852, |
1115 | PREFIX_EVEX_0F3853, | |
9186c494 | 1116 | PREFIX_EVEX_0F3868, |
53467f57 | 1117 | PREFIX_EVEX_0F3872, |
43234a1e L |
1118 | PREFIX_EVEX_0F389A, |
1119 | PREFIX_EVEX_0F389B, | |
43234a1e L |
1120 | PREFIX_EVEX_0F38AA, |
1121 | PREFIX_EVEX_0F38AB, | |
0cc78721 | 1122 | |
2235ecb8 JB |
1123 | PREFIX_EVEX_0F3A08, |
1124 | PREFIX_EVEX_0F3A0A, | |
0cc78721 CL |
1125 | PREFIX_EVEX_0F3A26, |
1126 | PREFIX_EVEX_0F3A27, | |
1127 | PREFIX_EVEX_0F3A56, | |
1128 | PREFIX_EVEX_0F3A57, | |
1129 | PREFIX_EVEX_0F3A66, | |
1130 | PREFIX_EVEX_0F3A67, | |
1131 | PREFIX_EVEX_0F3AC2, | |
1132 | ||
1133 | PREFIX_EVEX_MAP5_10, | |
1134 | PREFIX_EVEX_MAP5_11, | |
1135 | PREFIX_EVEX_MAP5_1D, | |
1136 | PREFIX_EVEX_MAP5_2A, | |
1137 | PREFIX_EVEX_MAP5_2C, | |
1138 | PREFIX_EVEX_MAP5_2D, | |
1139 | PREFIX_EVEX_MAP5_2E, | |
1140 | PREFIX_EVEX_MAP5_2F, | |
1141 | PREFIX_EVEX_MAP5_51, | |
1142 | PREFIX_EVEX_MAP5_58, | |
1143 | PREFIX_EVEX_MAP5_59, | |
2235ecb8 JB |
1144 | PREFIX_EVEX_MAP5_5A, |
1145 | PREFIX_EVEX_MAP5_5B, | |
0cc78721 CL |
1146 | PREFIX_EVEX_MAP5_5C, |
1147 | PREFIX_EVEX_MAP5_5D, | |
1148 | PREFIX_EVEX_MAP5_5E, | |
1149 | PREFIX_EVEX_MAP5_5F, | |
1150 | PREFIX_EVEX_MAP5_78, | |
1151 | PREFIX_EVEX_MAP5_79, | |
1152 | PREFIX_EVEX_MAP5_7A, | |
1153 | PREFIX_EVEX_MAP5_7B, | |
1154 | PREFIX_EVEX_MAP5_7C, | |
2235ecb8 | 1155 | PREFIX_EVEX_MAP5_7D, |
0cc78721 CL |
1156 | |
1157 | PREFIX_EVEX_MAP6_13, | |
1158 | PREFIX_EVEX_MAP6_56, | |
1159 | PREFIX_EVEX_MAP6_57, | |
1160 | PREFIX_EVEX_MAP6_D6, | |
1161 | PREFIX_EVEX_MAP6_D7, | |
51e7da1b | 1162 | }; |
4e7d34a6 | 1163 | |
51e7da1b L |
1164 | enum |
1165 | { | |
1166 | X86_64_06 = 0, | |
3873ba12 | 1167 | X86_64_07, |
1673df32 | 1168 | X86_64_0E, |
3873ba12 L |
1169 | X86_64_16, |
1170 | X86_64_17, | |
1171 | X86_64_1E, | |
1172 | X86_64_1F, | |
1173 | X86_64_27, | |
1174 | X86_64_2F, | |
1175 | X86_64_37, | |
1176 | X86_64_3F, | |
1177 | X86_64_60, | |
1178 | X86_64_61, | |
1179 | X86_64_62, | |
1180 | X86_64_63, | |
1181 | X86_64_6D, | |
1182 | X86_64_6F, | |
d039fef3 | 1183 | X86_64_82, |
3873ba12 | 1184 | X86_64_9A, |
aeab2b26 JB |
1185 | X86_64_C2, |
1186 | X86_64_C3, | |
3873ba12 L |
1187 | X86_64_C4, |
1188 | X86_64_C5, | |
1189 | X86_64_CE, | |
1190 | X86_64_D4, | |
1191 | X86_64_D5, | |
a72d2af2 L |
1192 | X86_64_E8, |
1193 | X86_64_E9, | |
3873ba12 | 1194 | X86_64_EA, |
c88ed92f | 1195 | X86_64_0F00_REG_6, |
3873ba12 | 1196 | X86_64_0F01_REG_0, |
2188d6ea HL |
1197 | X86_64_0F01_REG_0_MOD_3_RM_6_P_1, |
1198 | X86_64_0F01_REG_0_MOD_3_RM_6_P_3, | |
b5c37946 | 1199 | X86_64_0F01_REG_0_MOD_3_RM_7_P_0, |
3873ba12 | 1200 | X86_64_0F01_REG_1, |
c88ed92f ZJ |
1201 | X86_64_0F01_REG_1_RM_2_PREFIX_1, |
1202 | X86_64_0F01_REG_1_RM_2_PREFIX_3, | |
81d54bb7 CL |
1203 | X86_64_0F01_REG_1_RM_5_PREFIX_2, |
1204 | X86_64_0F01_REG_1_RM_6_PREFIX_2, | |
1205 | X86_64_0F01_REG_1_RM_7_PREFIX_2, | |
3873ba12 | 1206 | X86_64_0F01_REG_2, |
260cd341 | 1207 | X86_64_0F01_REG_3, |
f64c42a9 LC |
1208 | X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1, |
1209 | X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1, | |
1210 | X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1, | |
1211 | X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1, | |
b0e8fa7f | 1212 | X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1, |
646cc3e0 GG |
1213 | X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1, |
1214 | X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3, | |
1215 | X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1, | |
ef07be45 CL |
1216 | X86_64_0F18_REG_6_MOD_0, |
1217 | X86_64_0F18_REG_7_MOD_0, | |
32e31ad7 JB |
1218 | X86_64_0F24, |
1219 | X86_64_0F26, | |
1220 | X86_64_0FC7_REG_6_MOD_3_PREFIX_1, | |
1221 | ||
1222 | X86_64_VEX_0F3849, | |
1223 | X86_64_VEX_0F384B, | |
1224 | X86_64_VEX_0F385C, | |
a93e3234 | 1225 | X86_64_VEX_0F385E, |
d100d8c1 | 1226 | X86_64_VEX_0F386C, |
a93e3234 HJ |
1227 | X86_64_VEX_0F38E0, |
1228 | X86_64_VEX_0F38E1, | |
1229 | X86_64_VEX_0F38E2, | |
1230 | X86_64_VEX_0F38E3, | |
1231 | X86_64_VEX_0F38E4, | |
1232 | X86_64_VEX_0F38E5, | |
1233 | X86_64_VEX_0F38E6, | |
1234 | X86_64_VEX_0F38E7, | |
1235 | X86_64_VEX_0F38E8, | |
1236 | X86_64_VEX_0F38E9, | |
1237 | X86_64_VEX_0F38EA, | |
1238 | X86_64_VEX_0F38EB, | |
1239 | X86_64_VEX_0F38EC, | |
1240 | X86_64_VEX_0F38ED, | |
1241 | X86_64_VEX_0F38EE, | |
1242 | X86_64_VEX_0F38EF, | |
51e7da1b | 1243 | }; |
4e7d34a6 | 1244 | |
51e7da1b L |
1245 | enum |
1246 | { | |
1247 | THREE_BYTE_0F38 = 0, | |
1f334aeb | 1248 | THREE_BYTE_0F3A |
51e7da1b | 1249 | }; |
4e7d34a6 | 1250 | |
f88c9eb0 SP |
1251 | enum |
1252 | { | |
5dd85c99 SP |
1253 | XOP_08 = 0, |
1254 | XOP_09, | |
f88c9eb0 SP |
1255 | XOP_0A |
1256 | }; | |
1257 | ||
51e7da1b L |
1258 | enum |
1259 | { | |
1260 | VEX_0F = 0, | |
3873ba12 L |
1261 | VEX_0F38, |
1262 | VEX_0F3A | |
51e7da1b | 1263 | }; |
c0f3af97 | 1264 | |
43234a1e L |
1265 | enum |
1266 | { | |
1267 | EVEX_0F = 0, | |
1268 | EVEX_0F38, | |
0cc78721 CL |
1269 | EVEX_0F3A, |
1270 | EVEX_MAP5, | |
1271 | EVEX_MAP6, | |
43234a1e L |
1272 | }; |
1273 | ||
51e7da1b L |
1274 | enum |
1275 | { | |
b5c37946 SJ |
1276 | VEX_LEN_0F12_P_0 = 0, |
1277 | VEX_LEN_0F12_P_2, | |
1278 | VEX_LEN_0F13, | |
1279 | VEX_LEN_0F16_P_0, | |
1280 | VEX_LEN_0F16_P_2, | |
1281 | VEX_LEN_0F17, | |
13954a31 JB |
1282 | VEX_LEN_0F41, |
1283 | VEX_LEN_0F42, | |
1284 | VEX_LEN_0F44, | |
1285 | VEX_LEN_0F45, | |
1286 | VEX_LEN_0F46, | |
1287 | VEX_LEN_0F47, | |
1288 | VEX_LEN_0F4A, | |
1289 | VEX_LEN_0F4B, | |
7531c613 | 1290 | VEX_LEN_0F6E, |
035e7389 | 1291 | VEX_LEN_0F77, |
592a252b L |
1292 | VEX_LEN_0F7E_P_1, |
1293 | VEX_LEN_0F7E_P_2, | |
13954a31 JB |
1294 | VEX_LEN_0F90, |
1295 | VEX_LEN_0F91, | |
1296 | VEX_LEN_0F92, | |
1297 | VEX_LEN_0F93, | |
1298 | VEX_LEN_0F98, | |
1299 | VEX_LEN_0F99, | |
b5c37946 SJ |
1300 | VEX_LEN_0FAE_R_2, |
1301 | VEX_LEN_0FAE_R_3, | |
7531c613 | 1302 | VEX_LEN_0FC4, |
7531c613 | 1303 | VEX_LEN_0FD6, |
7531c613 JB |
1304 | VEX_LEN_0F3816, |
1305 | VEX_LEN_0F3819, | |
b5c37946 | 1306 | VEX_LEN_0F381A, |
7531c613 JB |
1307 | VEX_LEN_0F3836, |
1308 | VEX_LEN_0F3841, | |
1f506c06 JB |
1309 | VEX_LEN_0F3849_X86_64, |
1310 | VEX_LEN_0F384B_X86_64, | |
b5c37946 SJ |
1311 | VEX_LEN_0F385A, |
1312 | VEX_LEN_0F385C_X86_64, | |
1313 | VEX_LEN_0F385E_X86_64, | |
1314 | VEX_LEN_0F386C_X86_64, | |
1315 | VEX_LEN_0F38CB_P_3_W_0, | |
1316 | VEX_LEN_0F38CC_P_3_W_0, | |
1317 | VEX_LEN_0F38CD_P_3_W_0, | |
1318 | VEX_LEN_0F38DA_W_0_P_0, | |
1319 | VEX_LEN_0F38DA_W_0_P_2, | |
7531c613 | 1320 | VEX_LEN_0F38DB, |
035e7389 | 1321 | VEX_LEN_0F38F2, |
14d10c6c JB |
1322 | VEX_LEN_0F38F3, |
1323 | VEX_LEN_0F38F5, | |
1324 | VEX_LEN_0F38F6, | |
1325 | VEX_LEN_0F38F7, | |
7531c613 JB |
1326 | VEX_LEN_0F3A00, |
1327 | VEX_LEN_0F3A01, | |
1328 | VEX_LEN_0F3A06, | |
1329 | VEX_LEN_0F3A14, | |
1330 | VEX_LEN_0F3A15, | |
1331 | VEX_LEN_0F3A16, | |
1332 | VEX_LEN_0F3A17, | |
1333 | VEX_LEN_0F3A18, | |
1334 | VEX_LEN_0F3A19, | |
1335 | VEX_LEN_0F3A20, | |
1336 | VEX_LEN_0F3A21, | |
1337 | VEX_LEN_0F3A22, | |
1338 | VEX_LEN_0F3A30, | |
1339 | VEX_LEN_0F3A31, | |
1340 | VEX_LEN_0F3A32, | |
1341 | VEX_LEN_0F3A33, | |
1342 | VEX_LEN_0F3A38, | |
1343 | VEX_LEN_0F3A39, | |
1344 | VEX_LEN_0F3A41, | |
1345 | VEX_LEN_0F3A46, | |
1346 | VEX_LEN_0F3A60, | |
1347 | VEX_LEN_0F3A61, | |
1348 | VEX_LEN_0F3A62, | |
1349 | VEX_LEN_0F3A63, | |
b5c37946 | 1350 | VEX_LEN_0F3ADE_W_0, |
7531c613 | 1351 | VEX_LEN_0F3ADF, |
14d10c6c | 1352 | VEX_LEN_0F3AF0, |
b5c37946 SJ |
1353 | VEX_LEN_XOP_08_85, |
1354 | VEX_LEN_XOP_08_86, | |
1355 | VEX_LEN_XOP_08_87, | |
1356 | VEX_LEN_XOP_08_8E, | |
1357 | VEX_LEN_XOP_08_8F, | |
1358 | VEX_LEN_XOP_08_95, | |
1359 | VEX_LEN_XOP_08_96, | |
1360 | VEX_LEN_XOP_08_97, | |
1361 | VEX_LEN_XOP_08_9E, | |
1362 | VEX_LEN_XOP_08_9F, | |
1363 | VEX_LEN_XOP_08_A3, | |
1364 | VEX_LEN_XOP_08_A6, | |
1365 | VEX_LEN_XOP_08_B6, | |
1366 | VEX_LEN_XOP_08_C0, | |
1367 | VEX_LEN_XOP_08_C1, | |
1368 | VEX_LEN_XOP_08_C2, | |
1369 | VEX_LEN_XOP_08_C3, | |
1370 | VEX_LEN_XOP_08_CC, | |
1371 | VEX_LEN_XOP_08_CD, | |
1372 | VEX_LEN_XOP_08_CE, | |
1373 | VEX_LEN_XOP_08_CF, | |
1374 | VEX_LEN_XOP_08_EC, | |
1375 | VEX_LEN_XOP_08_ED, | |
1376 | VEX_LEN_XOP_08_EE, | |
1377 | VEX_LEN_XOP_08_EF, | |
1378 | VEX_LEN_XOP_09_01, | |
1379 | VEX_LEN_XOP_09_02, | |
1380 | VEX_LEN_XOP_09_12, | |
1381 | VEX_LEN_XOP_09_82_W_0, | |
1382 | VEX_LEN_XOP_09_83_W_0, | |
1383 | VEX_LEN_XOP_09_90, | |
1384 | VEX_LEN_XOP_09_91, | |
1385 | VEX_LEN_XOP_09_92, | |
1386 | VEX_LEN_XOP_09_93, | |
1387 | VEX_LEN_XOP_09_94, | |
1388 | VEX_LEN_XOP_09_95, | |
1389 | VEX_LEN_XOP_09_96, | |
1390 | VEX_LEN_XOP_09_97, | |
1391 | VEX_LEN_XOP_09_98, | |
1392 | VEX_LEN_XOP_09_99, | |
1393 | VEX_LEN_XOP_09_9A, | |
1394 | VEX_LEN_XOP_09_9B, | |
1395 | VEX_LEN_XOP_09_C1, | |
1396 | VEX_LEN_XOP_09_C2, | |
1397 | VEX_LEN_XOP_09_C3, | |
1398 | VEX_LEN_XOP_09_C6, | |
1399 | VEX_LEN_XOP_09_C7, | |
1400 | VEX_LEN_XOP_09_CB, | |
1401 | VEX_LEN_XOP_09_D1, | |
1402 | VEX_LEN_XOP_09_D2, | |
1403 | VEX_LEN_XOP_09_D3, | |
1404 | VEX_LEN_XOP_09_D6, | |
1405 | VEX_LEN_XOP_09_D7, | |
1406 | VEX_LEN_XOP_09_DB, | |
1407 | VEX_LEN_XOP_09_E1, | |
1408 | VEX_LEN_XOP_09_E2, | |
1409 | VEX_LEN_XOP_09_E3, | |
1410 | VEX_LEN_XOP_0A_12, | |
51e7da1b | 1411 | }; |
c0f3af97 | 1412 | |
04e2a182 L |
1413 | enum |
1414 | { | |
85ba7507 | 1415 | EVEX_LEN_0F3816 = 0, |
fc681dd6 | 1416 | EVEX_LEN_0F3819, |
b5c37946 SJ |
1417 | EVEX_LEN_0F381A, |
1418 | EVEX_LEN_0F381B, | |
7531c613 | 1419 | EVEX_LEN_0F3836, |
b5c37946 SJ |
1420 | EVEX_LEN_0F385A, |
1421 | EVEX_LEN_0F385B, | |
1422 | EVEX_LEN_0F38C6, | |
1423 | EVEX_LEN_0F38C7, | |
066f82b9 JB |
1424 | EVEX_LEN_0F3A00, |
1425 | EVEX_LEN_0F3A01, | |
fc681dd6 JB |
1426 | EVEX_LEN_0F3A18, |
1427 | EVEX_LEN_0F3A19, | |
1428 | EVEX_LEN_0F3A1A, | |
1429 | EVEX_LEN_0F3A1B, | |
fc681dd6 JB |
1430 | EVEX_LEN_0F3A23, |
1431 | EVEX_LEN_0F3A38, | |
1432 | EVEX_LEN_0F3A39, | |
1433 | EVEX_LEN_0F3A3A, | |
1434 | EVEX_LEN_0F3A3B, | |
1435 | EVEX_LEN_0F3A43 | |
04e2a182 L |
1436 | }; |
1437 | ||
9e30b8e0 L |
1438 | enum |
1439 | { | |
b5c37946 SJ |
1440 | VEX_W_0F41_L_1 = 0, |
1441 | VEX_W_0F42_L_1, | |
1442 | VEX_W_0F44_L_0, | |
1443 | VEX_W_0F45_L_1, | |
1444 | VEX_W_0F46_L_1, | |
1445 | VEX_W_0F47_L_1, | |
1446 | VEX_W_0F4A_L_1, | |
1447 | VEX_W_0F4B_L_1, | |
13954a31 | 1448 | VEX_W_0F90_L_0, |
b5c37946 SJ |
1449 | VEX_W_0F91_L_0, |
1450 | VEX_W_0F92_L_0, | |
1451 | VEX_W_0F93_L_0, | |
1452 | VEX_W_0F98_L_0, | |
1453 | VEX_W_0F99_L_0, | |
7531c613 JB |
1454 | VEX_W_0F380C, |
1455 | VEX_W_0F380D, | |
1456 | VEX_W_0F380E, | |
1457 | VEX_W_0F380F, | |
1458 | VEX_W_0F3813, | |
1459 | VEX_W_0F3816_L_1, | |
1460 | VEX_W_0F3818, | |
1461 | VEX_W_0F3819_L_1, | |
b5c37946 SJ |
1462 | VEX_W_0F381A_L_1, |
1463 | VEX_W_0F382C, | |
1464 | VEX_W_0F382D, | |
1465 | VEX_W_0F382E, | |
1466 | VEX_W_0F382F, | |
7531c613 JB |
1467 | VEX_W_0F3836, |
1468 | VEX_W_0F3846, | |
1f506c06 JB |
1469 | VEX_W_0F3849_X86_64_L_0, |
1470 | VEX_W_0F384B_X86_64_L_0, | |
58bf9b6a L |
1471 | VEX_W_0F3850, |
1472 | VEX_W_0F3851, | |
1473 | VEX_W_0F3852, | |
1474 | VEX_W_0F3853, | |
7531c613 JB |
1475 | VEX_W_0F3858, |
1476 | VEX_W_0F3859, | |
b5c37946 SJ |
1477 | VEX_W_0F385A_L_0, |
1478 | VEX_W_0F385C_X86_64_L_0, | |
1479 | VEX_W_0F385E_X86_64_L_0, | |
1480 | VEX_W_0F386C_X86_64_L_0, | |
01d8ce74 | 1481 | VEX_W_0F3872_P_1, |
7531c613 JB |
1482 | VEX_W_0F3878, |
1483 | VEX_W_0F3879, | |
01d8ce74 | 1484 | VEX_W_0F38B0, |
1485 | VEX_W_0F38B1, | |
4321af3e HW |
1486 | VEX_W_0F38B4, |
1487 | VEX_W_0F38B5, | |
b5c37946 SJ |
1488 | VEX_W_0F38CB_P_3, |
1489 | VEX_W_0F38CC_P_3, | |
1490 | VEX_W_0F38CD_P_3, | |
7531c613 | 1491 | VEX_W_0F38CF, |
b5c37946 SJ |
1492 | VEX_W_0F38D2, |
1493 | VEX_W_0F38D3, | |
1494 | VEX_W_0F38DA, | |
7531c613 JB |
1495 | VEX_W_0F3A00_L_1, |
1496 | VEX_W_0F3A01_L_1, | |
1497 | VEX_W_0F3A02, | |
1498 | VEX_W_0F3A04, | |
1499 | VEX_W_0F3A05, | |
1500 | VEX_W_0F3A06_L_1, | |
1501 | VEX_W_0F3A18_L_1, | |
1502 | VEX_W_0F3A19_L_1, | |
1503 | VEX_W_0F3A1D, | |
7531c613 JB |
1504 | VEX_W_0F3A38_L_1, |
1505 | VEX_W_0F3A39_L_1, | |
1506 | VEX_W_0F3A46_L_1, | |
1507 | VEX_W_0F3A4A, | |
1508 | VEX_W_0F3A4B, | |
1509 | VEX_W_0F3A4C, | |
1510 | VEX_W_0F3ACE, | |
1511 | VEX_W_0F3ACF, | |
b5c37946 SJ |
1512 | VEX_W_0F3ADE, |
1513 | ||
1514 | VEX_W_XOP_08_85_L_0, | |
1515 | VEX_W_XOP_08_86_L_0, | |
1516 | VEX_W_XOP_08_87_L_0, | |
1517 | VEX_W_XOP_08_8E_L_0, | |
1518 | VEX_W_XOP_08_8F_L_0, | |
1519 | VEX_W_XOP_08_95_L_0, | |
1520 | VEX_W_XOP_08_96_L_0, | |
1521 | VEX_W_XOP_08_97_L_0, | |
1522 | VEX_W_XOP_08_9E_L_0, | |
1523 | VEX_W_XOP_08_9F_L_0, | |
1524 | VEX_W_XOP_08_A6_L_0, | |
1525 | VEX_W_XOP_08_B6_L_0, | |
1526 | VEX_W_XOP_08_C0_L_0, | |
1527 | VEX_W_XOP_08_C1_L_0, | |
1528 | VEX_W_XOP_08_C2_L_0, | |
1529 | VEX_W_XOP_08_C3_L_0, | |
1530 | VEX_W_XOP_08_CC_L_0, | |
1531 | VEX_W_XOP_08_CD_L_0, | |
1532 | VEX_W_XOP_08_CE_L_0, | |
1533 | VEX_W_XOP_08_CF_L_0, | |
1534 | VEX_W_XOP_08_EC_L_0, | |
1535 | VEX_W_XOP_08_ED_L_0, | |
1536 | VEX_W_XOP_08_EE_L_0, | |
1537 | VEX_W_XOP_08_EF_L_0, | |
1538 | ||
1539 | VEX_W_XOP_09_80, | |
1540 | VEX_W_XOP_09_81, | |
1541 | VEX_W_XOP_09_82, | |
1542 | VEX_W_XOP_09_83, | |
1543 | VEX_W_XOP_09_C1_L_0, | |
1544 | VEX_W_XOP_09_C2_L_0, | |
1545 | VEX_W_XOP_09_C3_L_0, | |
1546 | VEX_W_XOP_09_C6_L_0, | |
1547 | VEX_W_XOP_09_C7_L_0, | |
1548 | VEX_W_XOP_09_CB_L_0, | |
1549 | VEX_W_XOP_09_D1_L_0, | |
1550 | VEX_W_XOP_09_D2_L_0, | |
1551 | VEX_W_XOP_09_D3_L_0, | |
1552 | VEX_W_XOP_09_D6_L_0, | |
1553 | VEX_W_XOP_09_D7_L_0, | |
1554 | VEX_W_XOP_09_DB_L_0, | |
1555 | VEX_W_XOP_09_E1_L_0, | |
1556 | VEX_W_XOP_09_E2_L_0, | |
1557 | VEX_W_XOP_09_E3_L_0, | |
b5b098c2 | 1558 | |
43234a1e | 1559 | EVEX_W_0F5B_P_0, |
fedfb81e | 1560 | EVEX_W_0F62, |
7531c613 | 1561 | EVEX_W_0F66, |
fedfb81e JB |
1562 | EVEX_W_0F6A, |
1563 | EVEX_W_0F6B, | |
1564 | EVEX_W_0F6C, | |
1565 | EVEX_W_0F6D, | |
43234a1e L |
1566 | EVEX_W_0F6F_P_1, |
1567 | EVEX_W_0F6F_P_2, | |
1ba585e8 | 1568 | EVEX_W_0F6F_P_3, |
43234a1e | 1569 | EVEX_W_0F70_P_2, |
7531c613 JB |
1570 | EVEX_W_0F72_R_2, |
1571 | EVEX_W_0F72_R_6, | |
1572 | EVEX_W_0F73_R_2, | |
1573 | EVEX_W_0F73_R_6, | |
1574 | EVEX_W_0F76, | |
43234a1e | 1575 | EVEX_W_0F78_P_0, |
90a915bf | 1576 | EVEX_W_0F78_P_2, |
43234a1e | 1577 | EVEX_W_0F79_P_0, |
90a915bf | 1578 | EVEX_W_0F79_P_2, |
43234a1e | 1579 | EVEX_W_0F7A_P_1, |
90a915bf | 1580 | EVEX_W_0F7A_P_2, |
43234a1e | 1581 | EVEX_W_0F7A_P_3, |
90a915bf | 1582 | EVEX_W_0F7B_P_2, |
43234a1e | 1583 | EVEX_W_0F7E_P_1, |
43234a1e L |
1584 | EVEX_W_0F7F_P_1, |
1585 | EVEX_W_0F7F_P_2, | |
1ba585e8 | 1586 | EVEX_W_0F7F_P_3, |
fedfb81e JB |
1587 | EVEX_W_0FD2, |
1588 | EVEX_W_0FD3, | |
1589 | EVEX_W_0FD4, | |
85ba7507 | 1590 | EVEX_W_0FD6, |
43234a1e | 1591 | EVEX_W_0FE6_P_1, |
7531c613 | 1592 | EVEX_W_0FE7, |
fedfb81e JB |
1593 | EVEX_W_0FF2, |
1594 | EVEX_W_0FF3, | |
1595 | EVEX_W_0FF4, | |
1596 | EVEX_W_0FFA, | |
1597 | EVEX_W_0FFB, | |
1598 | EVEX_W_0FFE, | |
740a1e79 | 1599 | |
1ba585e8 IT |
1600 | EVEX_W_0F3810_P_1, |
1601 | EVEX_W_0F3810_P_2, | |
43234a1e | 1602 | EVEX_W_0F3811_P_1, |
1ba585e8 | 1603 | EVEX_W_0F3811_P_2, |
43234a1e | 1604 | EVEX_W_0F3812_P_1, |
1ba585e8 | 1605 | EVEX_W_0F3812_P_2, |
43234a1e | 1606 | EVEX_W_0F3813_P_1, |
43234a1e L |
1607 | EVEX_W_0F3814_P_1, |
1608 | EVEX_W_0F3815_P_1, | |
fc681dd6 | 1609 | EVEX_W_0F3819_L_n, |
b5c37946 SJ |
1610 | EVEX_W_0F381A_L_n, |
1611 | EVEX_W_0F381B_L_2, | |
7531c613 JB |
1612 | EVEX_W_0F381E, |
1613 | EVEX_W_0F381F, | |
1ba585e8 | 1614 | EVEX_W_0F3820_P_1, |
43234a1e L |
1615 | EVEX_W_0F3821_P_1, |
1616 | EVEX_W_0F3822_P_1, | |
1617 | EVEX_W_0F3823_P_1, | |
1618 | EVEX_W_0F3824_P_1, | |
1619 | EVEX_W_0F3825_P_1, | |
1620 | EVEX_W_0F3825_P_2, | |
1621 | EVEX_W_0F3828_P_2, | |
1622 | EVEX_W_0F3829_P_2, | |
1623 | EVEX_W_0F382A_P_1, | |
1624 | EVEX_W_0F382A_P_2, | |
fedfb81e | 1625 | EVEX_W_0F382B, |
1ba585e8 | 1626 | EVEX_W_0F3830_P_1, |
43234a1e L |
1627 | EVEX_W_0F3831_P_1, |
1628 | EVEX_W_0F3832_P_1, | |
1629 | EVEX_W_0F3833_P_1, | |
1630 | EVEX_W_0F3834_P_1, | |
1631 | EVEX_W_0F3835_P_1, | |
1632 | EVEX_W_0F3835_P_2, | |
7531c613 | 1633 | EVEX_W_0F3837, |
43234a1e | 1634 | EVEX_W_0F383A_P_1, |
7531c613 | 1635 | EVEX_W_0F3859, |
b5c37946 SJ |
1636 | EVEX_W_0F385A_L_n, |
1637 | EVEX_W_0F385B_L_2, | |
7531c613 | 1638 | EVEX_W_0F3870, |
53467f57 | 1639 | EVEX_W_0F3872_P_2, |
7531c613 JB |
1640 | EVEX_W_0F387A, |
1641 | EVEX_W_0F387B, | |
1642 | EVEX_W_0F3883, | |
7531c613 | 1643 | |
fc681dd6 JB |
1644 | EVEX_W_0F3A18_L_n, |
1645 | EVEX_W_0F3A19_L_n, | |
1646 | EVEX_W_0F3A1A_L_2, | |
1647 | EVEX_W_0F3A1B_L_2, | |
7531c613 | 1648 | EVEX_W_0F3A21, |
fc681dd6 JB |
1649 | EVEX_W_0F3A23_L_n, |
1650 | EVEX_W_0F3A38_L_n, | |
1651 | EVEX_W_0F3A39_L_n, | |
1652 | EVEX_W_0F3A3A_L_2, | |
1653 | EVEX_W_0F3A3B_L_2, | |
7531c613 | 1654 | EVEX_W_0F3A42, |
fc681dd6 | 1655 | EVEX_W_0F3A43_L_n, |
7531c613 JB |
1656 | EVEX_W_0F3A70, |
1657 | EVEX_W_0F3A72, | |
0cc78721 | 1658 | |
2235ecb8 | 1659 | EVEX_W_MAP5_5B_P_0, |
0cc78721 | 1660 | EVEX_W_MAP5_7A_P_3, |
9e30b8e0 L |
1661 | }; |
1662 | ||
97601363 | 1663 | typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag); |
252b5132 RH |
1664 | |
1665 | struct dis386 { | |
2da11e11 | 1666 | const char *name; |
ce518a5f L |
1667 | struct |
1668 | { | |
1669 | op_rtn rtn; | |
1670 | int bytemode; | |
1671 | } op[MAX_OPERANDS]; | |
bf890a93 | 1672 | unsigned int prefix_requirement; |
252b5132 RH |
1673 | }; |
1674 | ||
1675 | /* Upper case letters in the instruction names here are macros. | |
1676 | 'A' => print 'b' if no register operands or suffix_always is true | |
1677 | 'B' => print 'b' if suffix_always is true | |
9306ca4a | 1678 | 'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand |
98b528ac | 1679 | size prefix |
ed7841b3 | 1680 | 'D' => print 'w' if no register operands or 'w', 'l' or 'q', if |
98b528ac | 1681 | suffix_always is true |
252b5132 | 1682 | 'E' => print 'e' if 32-bit form of jcxz |
3ffd33cf | 1683 | 'F' => print 'w' or 'l' depending on address size prefix (loop insns) |
52fd6d94 | 1684 | 'G' => print 'w' or 'l' depending on operand size prefix (i/o insns) |
5dd0794d | 1685 | 'H' => print ",pt" or ",pn" branch hint |
d1c36125 | 1686 | 'I' unused. |
8f570d62 | 1687 | 'J' unused. |
42903f7f | 1688 | 'K' => print 'd' or 'q' if rex prefix is present. |
78467458 | 1689 | 'L' unused. |
9d141669 | 1690 | 'M' => print 'r' if intel_mnemonic is false. |
252b5132 | 1691 | 'N' => print 'n' if instruction has no wait "prefix" |
a35ca55a | 1692 | 'O' => print 'd' or 'o' (or 'q' in Intel mode) |
36938cab JB |
1693 | 'P' => behave as 'T' except with register operand outside of suffix_always |
1694 | mode | |
98b528ac L |
1695 | 'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always |
1696 | is true | |
a35ca55a | 1697 | 'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode) |
52b15da3 | 1698 | 'S' => print 'w', 'l' or 'q' if suffix_always is true |
36938cab JB |
1699 | 'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size |
1700 | prefix or if suffix_always is true. | |
1701 | 'U' unused. | |
b5c37946 | 1702 | 'V' => print 'v' for VEX/EVEX and nothing for legacy encodings. |
a35ca55a | 1703 | 'W' => print 'b', 'w' or 'l' ('d' in Intel mode) |
9306ca4a | 1704 | 'X' => print 's', 'd' depending on data16 prefix (for XMM) |
b5c37946 | 1705 | 'Y' => no output, mark EVEX.aaa != 0 as bad. |
78467458 | 1706 | 'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true. |
9d141669 | 1707 | '!' => change condition from true to false or from false to true. |
98b528ac | 1708 | '%' => add 1 upper case letter to the macro. |
5990e377 JB |
1709 | '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size |
1710 | prefix or suffix_always is true (lcall/ljmp). | |
36938cab JB |
1711 | '@' => in 64bit mode for Intel64 ISA or if instruction |
1712 | has no operand sizing prefix, print 'q' if suffix_always is true or | |
1713 | nothing otherwise; behave as 'P' in all other cases | |
98b528ac L |
1714 | |
1715 | 2 upper case letter macros: | |
04d824a4 JB |
1716 | "XY" => print 'x' or 'y' if suffix_always is true or no register |
1717 | operands and no broadcast. | |
1718 | "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no | |
1719 | register operands and no broadcast. | |
4b06377f | 1720 | "XW" => print 's', 'd' depending on the VEX.W bit (for FMA) |
e6cfa893 | 1721 | "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding |
0cc78721 | 1722 | "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16) |
e6cfa893 | 1723 | "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding |
995bca23 | 1724 | "XV" => print "{vex} " pseudo prefix |
f7cfcddd JB |
1725 | "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is |
1726 | is used by an EVEX-encoded (AVX512VL) instruction. | |
b5c37946 SJ |
1727 | "YK" keep unused, to avoid ambiguity with the combined use of Y and K. |
1728 | "YX" keep unused, to avoid ambiguity with the combined use of Y and X. | |
b24d668c JB |
1729 | "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond |
1730 | being false, or no operand at all in 64bit mode, or if suffix_always | |
589958d6 | 1731 | is true. |
4b06377f L |
1732 | "LB" => print "abs" in 64bit mode and behave as 'B' otherwise |
1733 | "LS" => print "abs" in 64bit mode and behave as 'S' otherwise | |
1734 | "LV" => print "abs" for 64bit operand and behave as 'S' otherwise | |
492a76aa | 1735 | "DQ" => print 'd' or 'q' depending on the VEX.W bit |
bb5b3501 | 1736 | "BW" => print 'b' or 'w' depending on the VEX.W bit |
4b4c407a L |
1737 | "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has |
1738 | an operand size prefix, or suffix_always is true. print | |
1739 | 'q' if rex prefix is present. | |
52b15da3 | 1740 | |
6439fc28 AM |
1741 | Many of the above letters print nothing in Intel mode. See "putop" |
1742 | for the details. | |
52b15da3 | 1743 | |
6439fc28 | 1744 | Braces '{' and '}', and vertical bars '|', indicate alternative |
7c52e0e8 | 1745 | mnemonic strings for AT&T and Intel. */ |
252b5132 | 1746 | |
6439fc28 | 1747 | static const struct dis386 dis386[] = { |
252b5132 | 1748 | /* 00 */ |
bf890a93 IT |
1749 | { "addB", { Ebh1, Gb }, 0 }, |
1750 | { "addS", { Evh1, Gv }, 0 }, | |
1751 | { "addB", { Gb, EbS }, 0 }, | |
1752 | { "addS", { Gv, EvS }, 0 }, | |
1753 | { "addB", { AL, Ib }, 0 }, | |
1754 | { "addS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1755 | { X86_64_TABLE (X86_64_06) }, |
1756 | { X86_64_TABLE (X86_64_07) }, | |
252b5132 | 1757 | /* 08 */ |
bf890a93 IT |
1758 | { "orB", { Ebh1, Gb }, 0 }, |
1759 | { "orS", { Evh1, Gv }, 0 }, | |
1760 | { "orB", { Gb, EbS }, 0 }, | |
1761 | { "orS", { Gv, EvS }, 0 }, | |
1762 | { "orB", { AL, Ib }, 0 }, | |
1763 | { "orS", { eAX, Iv }, 0 }, | |
1673df32 | 1764 | { X86_64_TABLE (X86_64_0E) }, |
592d1631 | 1765 | { Bad_Opcode }, /* 0x0f extended opcode escape */ |
252b5132 | 1766 | /* 10 */ |
bf890a93 IT |
1767 | { "adcB", { Ebh1, Gb }, 0 }, |
1768 | { "adcS", { Evh1, Gv }, 0 }, | |
1769 | { "adcB", { Gb, EbS }, 0 }, | |
1770 | { "adcS", { Gv, EvS }, 0 }, | |
1771 | { "adcB", { AL, Ib }, 0 }, | |
1772 | { "adcS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1773 | { X86_64_TABLE (X86_64_16) }, |
1774 | { X86_64_TABLE (X86_64_17) }, | |
252b5132 | 1775 | /* 18 */ |
bf890a93 IT |
1776 | { "sbbB", { Ebh1, Gb }, 0 }, |
1777 | { "sbbS", { Evh1, Gv }, 0 }, | |
1778 | { "sbbB", { Gb, EbS }, 0 }, | |
1779 | { "sbbS", { Gv, EvS }, 0 }, | |
1780 | { "sbbB", { AL, Ib }, 0 }, | |
1781 | { "sbbS", { eAX, Iv }, 0 }, | |
4e7d34a6 L |
1782 | { X86_64_TABLE (X86_64_1E) }, |
1783 | { X86_64_TABLE (X86_64_1F) }, | |
252b5132 | 1784 | /* 20 */ |
bf890a93 IT |
1785 | { "andB", { Ebh1, Gb }, 0 }, |
1786 | { "andS", { Evh1, Gv }, 0 }, | |
1787 | { "andB", { Gb, EbS }, 0 }, | |
1788 | { "andS", { Gv, EvS }, 0 }, | |
1789 | { "andB", { AL, Ib }, 0 }, | |
1790 | { "andS", { eAX, Iv }, 0 }, | |
592d1631 | 1791 | { Bad_Opcode }, /* SEG ES prefix */ |
4e7d34a6 | 1792 | { X86_64_TABLE (X86_64_27) }, |
252b5132 | 1793 | /* 28 */ |
bf890a93 IT |
1794 | { "subB", { Ebh1, Gb }, 0 }, |
1795 | { "subS", { Evh1, Gv }, 0 }, | |
1796 | { "subB", { Gb, EbS }, 0 }, | |
1797 | { "subS", { Gv, EvS }, 0 }, | |
1798 | { "subB", { AL, Ib }, 0 }, | |
1799 | { "subS", { eAX, Iv }, 0 }, | |
592d1631 | 1800 | { Bad_Opcode }, /* SEG CS prefix */ |
4e7d34a6 | 1801 | { X86_64_TABLE (X86_64_2F) }, |
252b5132 | 1802 | /* 30 */ |
bf890a93 IT |
1803 | { "xorB", { Ebh1, Gb }, 0 }, |
1804 | { "xorS", { Evh1, Gv }, 0 }, | |
1805 | { "xorB", { Gb, EbS }, 0 }, | |
1806 | { "xorS", { Gv, EvS }, 0 }, | |
1807 | { "xorB", { AL, Ib }, 0 }, | |
1808 | { "xorS", { eAX, Iv }, 0 }, | |
592d1631 | 1809 | { Bad_Opcode }, /* SEG SS prefix */ |
4e7d34a6 | 1810 | { X86_64_TABLE (X86_64_37) }, |
252b5132 | 1811 | /* 38 */ |
bf890a93 IT |
1812 | { "cmpB", { Eb, Gb }, 0 }, |
1813 | { "cmpS", { Ev, Gv }, 0 }, | |
1814 | { "cmpB", { Gb, EbS }, 0 }, | |
1815 | { "cmpS", { Gv, EvS }, 0 }, | |
1816 | { "cmpB", { AL, Ib }, 0 }, | |
1817 | { "cmpS", { eAX, Iv }, 0 }, | |
592d1631 | 1818 | { Bad_Opcode }, /* SEG DS prefix */ |
4e7d34a6 | 1819 | { X86_64_TABLE (X86_64_3F) }, |
252b5132 | 1820 | /* 40 */ |
bf890a93 IT |
1821 | { "inc{S|}", { RMeAX }, 0 }, |
1822 | { "inc{S|}", { RMeCX }, 0 }, | |
1823 | { "inc{S|}", { RMeDX }, 0 }, | |
1824 | { "inc{S|}", { RMeBX }, 0 }, | |
1825 | { "inc{S|}", { RMeSP }, 0 }, | |
1826 | { "inc{S|}", { RMeBP }, 0 }, | |
1827 | { "inc{S|}", { RMeSI }, 0 }, | |
1828 | { "inc{S|}", { RMeDI }, 0 }, | |
252b5132 | 1829 | /* 48 */ |
bf890a93 IT |
1830 | { "dec{S|}", { RMeAX }, 0 }, |
1831 | { "dec{S|}", { RMeCX }, 0 }, | |
1832 | { "dec{S|}", { RMeDX }, 0 }, | |
1833 | { "dec{S|}", { RMeBX }, 0 }, | |
1834 | { "dec{S|}", { RMeSP }, 0 }, | |
1835 | { "dec{S|}", { RMeBP }, 0 }, | |
1836 | { "dec{S|}", { RMeSI }, 0 }, | |
1837 | { "dec{S|}", { RMeDI }, 0 }, | |
252b5132 | 1838 | /* 50 */ |
c3f5525f JB |
1839 | { "push{!P|}", { RMrAX }, 0 }, |
1840 | { "push{!P|}", { RMrCX }, 0 }, | |
1841 | { "push{!P|}", { RMrDX }, 0 }, | |
1842 | { "push{!P|}", { RMrBX }, 0 }, | |
1843 | { "push{!P|}", { RMrSP }, 0 }, | |
1844 | { "push{!P|}", { RMrBP }, 0 }, | |
1845 | { "push{!P|}", { RMrSI }, 0 }, | |
1846 | { "push{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1847 | /* 58 */ |
c3f5525f JB |
1848 | { "pop{!P|}", { RMrAX }, 0 }, |
1849 | { "pop{!P|}", { RMrCX }, 0 }, | |
1850 | { "pop{!P|}", { RMrDX }, 0 }, | |
1851 | { "pop{!P|}", { RMrBX }, 0 }, | |
1852 | { "pop{!P|}", { RMrSP }, 0 }, | |
1853 | { "pop{!P|}", { RMrBP }, 0 }, | |
1854 | { "pop{!P|}", { RMrSI }, 0 }, | |
1855 | { "pop{!P|}", { RMrDI }, 0 }, | |
252b5132 | 1856 | /* 60 */ |
4e7d34a6 L |
1857 | { X86_64_TABLE (X86_64_60) }, |
1858 | { X86_64_TABLE (X86_64_61) }, | |
1859 | { X86_64_TABLE (X86_64_62) }, | |
1860 | { X86_64_TABLE (X86_64_63) }, | |
592d1631 L |
1861 | { Bad_Opcode }, /* seg fs */ |
1862 | { Bad_Opcode }, /* seg gs */ | |
1863 | { Bad_Opcode }, /* op size prefix */ | |
1864 | { Bad_Opcode }, /* adr size prefix */ | |
252b5132 | 1865 | /* 68 */ |
36938cab | 1866 | { "pushP", { sIv }, 0 }, |
bf890a93 | 1867 | { "imulS", { Gv, Ev, Iv }, 0 }, |
36938cab | 1868 | { "pushP", { sIbT }, 0 }, |
bf890a93 IT |
1869 | { "imulS", { Gv, Ev, sIb }, 0 }, |
1870 | { "ins{b|}", { Ybr, indirDX }, 0 }, | |
4e7d34a6 | 1871 | { X86_64_TABLE (X86_64_6D) }, |
bf890a93 | 1872 | { "outs{b|}", { indirDXr, Xb }, 0 }, |
4e7d34a6 | 1873 | { X86_64_TABLE (X86_64_6F) }, |
252b5132 | 1874 | /* 70 */ |
bf890a93 IT |
1875 | { "joH", { Jb, BND, cond_jump_flag }, 0 }, |
1876 | { "jnoH", { Jb, BND, cond_jump_flag }, 0 }, | |
1877 | { "jbH", { Jb, BND, cond_jump_flag }, 0 }, | |
1878 | { "jaeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1879 | { "jeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1880 | { "jneH", { Jb, BND, cond_jump_flag }, 0 }, | |
1881 | { "jbeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1882 | { "jaH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1883 | /* 78 */ |
bf890a93 IT |
1884 | { "jsH", { Jb, BND, cond_jump_flag }, 0 }, |
1885 | { "jnsH", { Jb, BND, cond_jump_flag }, 0 }, | |
1886 | { "jpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1887 | { "jnpH", { Jb, BND, cond_jump_flag }, 0 }, | |
1888 | { "jlH", { Jb, BND, cond_jump_flag }, 0 }, | |
1889 | { "jgeH", { Jb, BND, cond_jump_flag }, 0 }, | |
1890 | { "jleH", { Jb, BND, cond_jump_flag }, 0 }, | |
1891 | { "jgH", { Jb, BND, cond_jump_flag }, 0 }, | |
252b5132 | 1892 | /* 80 */ |
1ceb70f8 L |
1893 | { REG_TABLE (REG_80) }, |
1894 | { REG_TABLE (REG_81) }, | |
d039fef3 | 1895 | { X86_64_TABLE (X86_64_82) }, |
7148c369 | 1896 | { REG_TABLE (REG_83) }, |
bf890a93 IT |
1897 | { "testB", { Eb, Gb }, 0 }, |
1898 | { "testS", { Ev, Gv }, 0 }, | |
1899 | { "xchgB", { Ebh2, Gb }, 0 }, | |
1900 | { "xchgS", { Evh2, Gv }, 0 }, | |
252b5132 | 1901 | /* 88 */ |
bf890a93 IT |
1902 | { "movB", { Ebh3, Gb }, 0 }, |
1903 | { "movS", { Evh3, Gv }, 0 }, | |
1904 | { "movB", { Gb, EbS }, 0 }, | |
1905 | { "movS", { Gv, EvS }, 0 }, | |
1906 | { "movD", { Sv, Sw }, 0 }, | |
b5c37946 | 1907 | { "leaS", { Gv, M }, 0 }, |
bf890a93 | 1908 | { "movD", { Sw, Sv }, 0 }, |
1ceb70f8 | 1909 | { REG_TABLE (REG_8F) }, |
252b5132 | 1910 | /* 90 */ |
1ceb70f8 | 1911 | { PREFIX_TABLE (PREFIX_90) }, |
bf890a93 IT |
1912 | { "xchgS", { RMeCX, eAX }, 0 }, |
1913 | { "xchgS", { RMeDX, eAX }, 0 }, | |
1914 | { "xchgS", { RMeBX, eAX }, 0 }, | |
1915 | { "xchgS", { RMeSP, eAX }, 0 }, | |
1916 | { "xchgS", { RMeBP, eAX }, 0 }, | |
1917 | { "xchgS", { RMeSI, eAX }, 0 }, | |
1918 | { "xchgS", { RMeDI, eAX }, 0 }, | |
252b5132 | 1919 | /* 98 */ |
bf890a93 IT |
1920 | { "cW{t|}R", { XX }, 0 }, |
1921 | { "cR{t|}O", { XX }, 0 }, | |
4e7d34a6 | 1922 | { X86_64_TABLE (X86_64_9A) }, |
592d1631 | 1923 | { Bad_Opcode }, /* fwait */ |
36938cab JB |
1924 | { "pushfP", { XX }, 0 }, |
1925 | { "popfP", { XX }, 0 }, | |
bf890a93 IT |
1926 | { "sahf", { XX }, 0 }, |
1927 | { "lahf", { XX }, 0 }, | |
252b5132 | 1928 | /* a0 */ |
bf890a93 IT |
1929 | { "mov%LB", { AL, Ob }, 0 }, |
1930 | { "mov%LS", { eAX, Ov }, 0 }, | |
1931 | { "mov%LB", { Ob, AL }, 0 }, | |
1932 | { "mov%LS", { Ov, eAX }, 0 }, | |
1933 | { "movs{b|}", { Ybr, Xb }, 0 }, | |
1934 | { "movs{R|}", { Yvr, Xv }, 0 }, | |
1935 | { "cmps{b|}", { Xb, Yb }, 0 }, | |
1936 | { "cmps{R|}", { Xv, Yv }, 0 }, | |
252b5132 | 1937 | /* a8 */ |
bf890a93 IT |
1938 | { "testB", { AL, Ib }, 0 }, |
1939 | { "testS", { eAX, Iv }, 0 }, | |
1940 | { "stosB", { Ybr, AL }, 0 }, | |
1941 | { "stosS", { Yvr, eAX }, 0 }, | |
1942 | { "lodsB", { ALr, Xb }, 0 }, | |
1943 | { "lodsS", { eAXr, Xv }, 0 }, | |
1944 | { "scasB", { AL, Yb }, 0 }, | |
1945 | { "scasS", { eAX, Yv }, 0 }, | |
252b5132 | 1946 | /* b0 */ |
bf890a93 IT |
1947 | { "movB", { RMAL, Ib }, 0 }, |
1948 | { "movB", { RMCL, Ib }, 0 }, | |
1949 | { "movB", { RMDL, Ib }, 0 }, | |
1950 | { "movB", { RMBL, Ib }, 0 }, | |
1951 | { "movB", { RMAH, Ib }, 0 }, | |
1952 | { "movB", { RMCH, Ib }, 0 }, | |
1953 | { "movB", { RMDH, Ib }, 0 }, | |
1954 | { "movB", { RMBH, Ib }, 0 }, | |
252b5132 | 1955 | /* b8 */ |
bf890a93 IT |
1956 | { "mov%LV", { RMeAX, Iv64 }, 0 }, |
1957 | { "mov%LV", { RMeCX, Iv64 }, 0 }, | |
1958 | { "mov%LV", { RMeDX, Iv64 }, 0 }, | |
1959 | { "mov%LV", { RMeBX, Iv64 }, 0 }, | |
1960 | { "mov%LV", { RMeSP, Iv64 }, 0 }, | |
1961 | { "mov%LV", { RMeBP, Iv64 }, 0 }, | |
1962 | { "mov%LV", { RMeSI, Iv64 }, 0 }, | |
1963 | { "mov%LV", { RMeDI, Iv64 }, 0 }, | |
252b5132 | 1964 | /* c0 */ |
1ceb70f8 L |
1965 | { REG_TABLE (REG_C0) }, |
1966 | { REG_TABLE (REG_C1) }, | |
aeab2b26 JB |
1967 | { X86_64_TABLE (X86_64_C2) }, |
1968 | { X86_64_TABLE (X86_64_C3) }, | |
4e7d34a6 L |
1969 | { X86_64_TABLE (X86_64_C4) }, |
1970 | { X86_64_TABLE (X86_64_C5) }, | |
1ceb70f8 L |
1971 | { REG_TABLE (REG_C6) }, |
1972 | { REG_TABLE (REG_C7) }, | |
252b5132 | 1973 | /* c8 */ |
36938cab JB |
1974 | { "enterP", { Iw, Ib }, 0 }, |
1975 | { "leaveP", { XX }, 0 }, | |
1976 | { "{l|}ret{|f}%LP", { Iw }, 0 }, | |
1977 | { "{l|}ret{|f}%LP", { XX }, 0 }, | |
bf890a93 IT |
1978 | { "int3", { XX }, 0 }, |
1979 | { "int", { Ib }, 0 }, | |
4e7d34a6 | 1980 | { X86_64_TABLE (X86_64_CE) }, |
bf890a93 | 1981 | { "iret%LP", { XX }, 0 }, |
252b5132 | 1982 | /* d0 */ |
1ceb70f8 L |
1983 | { REG_TABLE (REG_D0) }, |
1984 | { REG_TABLE (REG_D1) }, | |
1985 | { REG_TABLE (REG_D2) }, | |
1986 | { REG_TABLE (REG_D3) }, | |
4e7d34a6 L |
1987 | { X86_64_TABLE (X86_64_D4) }, |
1988 | { X86_64_TABLE (X86_64_D5) }, | |
592d1631 | 1989 | { Bad_Opcode }, |
bf890a93 | 1990 | { "xlat", { DSBX }, 0 }, |
252b5132 RH |
1991 | /* d8 */ |
1992 | { FLOAT }, | |
1993 | { FLOAT }, | |
1994 | { FLOAT }, | |
1995 | { FLOAT }, | |
1996 | { FLOAT }, | |
1997 | { FLOAT }, | |
1998 | { FLOAT }, | |
1999 | { FLOAT }, | |
2000 | /* e0 */ | |
bf890a93 IT |
2001 | { "loopneFH", { Jb, XX, loop_jcxz_flag }, 0 }, |
2002 | { "loopeFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2003 | { "loopFH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2004 | { "jEcxzH", { Jb, XX, loop_jcxz_flag }, 0 }, | |
2005 | { "inB", { AL, Ib }, 0 }, | |
2006 | { "inG", { zAX, Ib }, 0 }, | |
2007 | { "outB", { Ib, AL }, 0 }, | |
2008 | { "outG", { Ib, zAX }, 0 }, | |
252b5132 | 2009 | /* e8 */ |
a72d2af2 L |
2010 | { X86_64_TABLE (X86_64_E8) }, |
2011 | { X86_64_TABLE (X86_64_E9) }, | |
4e7d34a6 | 2012 | { X86_64_TABLE (X86_64_EA) }, |
bf890a93 IT |
2013 | { "jmp", { Jb, BND }, 0 }, |
2014 | { "inB", { AL, indirDX }, 0 }, | |
2015 | { "inG", { zAX, indirDX }, 0 }, | |
2016 | { "outB", { indirDX, AL }, 0 }, | |
2017 | { "outG", { indirDX, zAX }, 0 }, | |
252b5132 | 2018 | /* f0 */ |
592d1631 | 2019 | { Bad_Opcode }, /* lock prefix */ |
154b353f | 2020 | { "int1", { XX }, 0 }, |
592d1631 L |
2021 | { Bad_Opcode }, /* repne */ |
2022 | { Bad_Opcode }, /* repz */ | |
bf890a93 IT |
2023 | { "hlt", { XX }, 0 }, |
2024 | { "cmc", { XX }, 0 }, | |
1ceb70f8 L |
2025 | { REG_TABLE (REG_F6) }, |
2026 | { REG_TABLE (REG_F7) }, | |
252b5132 | 2027 | /* f8 */ |
bf890a93 IT |
2028 | { "clc", { XX }, 0 }, |
2029 | { "stc", { XX }, 0 }, | |
2030 | { "cli", { XX }, 0 }, | |
2031 | { "sti", { XX }, 0 }, | |
2032 | { "cld", { XX }, 0 }, | |
2033 | { "std", { XX }, 0 }, | |
1ceb70f8 L |
2034 | { REG_TABLE (REG_FE) }, |
2035 | { REG_TABLE (REG_FF) }, | |
252b5132 RH |
2036 | }; |
2037 | ||
6439fc28 | 2038 | static const struct dis386 dis386_twobyte[] = { |
252b5132 | 2039 | /* 00 */ |
1ceb70f8 L |
2040 | { REG_TABLE (REG_0F00 ) }, |
2041 | { REG_TABLE (REG_0F01 ) }, | |
b5c37946 SJ |
2042 | { "larS", { Gv, Sv }, 0 }, |
2043 | { "lslS", { Gv, Sv }, 0 }, | |
592d1631 | 2044 | { Bad_Opcode }, |
bf890a93 IT |
2045 | { "syscall", { XX }, 0 }, |
2046 | { "clts", { XX }, 0 }, | |
589958d6 | 2047 | { "sysret%LQ", { XX }, 0 }, |
252b5132 | 2048 | /* 08 */ |
bf890a93 | 2049 | { "invd", { XX }, 0 }, |
3233d7d0 | 2050 | { PREFIX_TABLE (PREFIX_0F09) }, |
592d1631 | 2051 | { Bad_Opcode }, |
bf890a93 | 2052 | { "ud2", { XX }, 0 }, |
592d1631 | 2053 | { Bad_Opcode }, |
b5b1fc4f | 2054 | { REG_TABLE (REG_0F0D) }, |
bf890a93 IT |
2055 | { "femms", { XX }, 0 }, |
2056 | { "", { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix. */ | |
252b5132 | 2057 | /* 10 */ |
1ceb70f8 L |
2058 | { PREFIX_TABLE (PREFIX_0F10) }, |
2059 | { PREFIX_TABLE (PREFIX_0F11) }, | |
2060 | { PREFIX_TABLE (PREFIX_0F12) }, | |
b5c37946 | 2061 | { "movlpX", { Mq, XM }, PREFIX_OPCODE }, |
507bd325 L |
2062 | { "unpcklpX", { XM, EXx }, PREFIX_OPCODE }, |
2063 | { "unpckhpX", { XM, EXx }, PREFIX_OPCODE }, | |
1ceb70f8 | 2064 | { PREFIX_TABLE (PREFIX_0F16) }, |
b5c37946 | 2065 | { "movhpX", { Mq, XM }, PREFIX_OPCODE }, |
252b5132 | 2066 | /* 18 */ |
1ceb70f8 | 2067 | { REG_TABLE (REG_0F18) }, |
bf890a93 | 2068 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
2069 | { PREFIX_TABLE (PREFIX_0F1A) }, |
2070 | { PREFIX_TABLE (PREFIX_0F1B) }, | |
c48935d7 | 2071 | { PREFIX_TABLE (PREFIX_0F1C) }, |
bf890a93 | 2072 | { "nopQ", { Ev }, 0 }, |
603555e5 | 2073 | { PREFIX_TABLE (PREFIX_0F1E) }, |
bf890a93 | 2074 | { "nopQ", { Ev }, 0 }, |
252b5132 | 2075 | /* 20 */ |
78467458 JB |
2076 | { "movZ", { Em, Cm }, 0 }, |
2077 | { "movZ", { Em, Dm }, 0 }, | |
2078 | { "movZ", { Cm, Em }, 0 }, | |
2079 | { "movZ", { Dm, Em }, 0 }, | |
2080 | { X86_64_TABLE (X86_64_0F24) }, | |
592d1631 | 2081 | { Bad_Opcode }, |
78467458 | 2082 | { X86_64_TABLE (X86_64_0F26) }, |
592d1631 | 2083 | { Bad_Opcode }, |
252b5132 | 2084 | /* 28 */ |
507bd325 L |
2085 | { "movapX", { XM, EXx }, PREFIX_OPCODE }, |
2086 | { "movapX", { EXxS, XM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2087 | { PREFIX_TABLE (PREFIX_0F2A) }, |
2088 | { PREFIX_TABLE (PREFIX_0F2B) }, | |
2089 | { PREFIX_TABLE (PREFIX_0F2C) }, | |
2090 | { PREFIX_TABLE (PREFIX_0F2D) }, | |
2091 | { PREFIX_TABLE (PREFIX_0F2E) }, | |
2092 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
252b5132 | 2093 | /* 30 */ |
bf890a93 IT |
2094 | { "wrmsr", { XX }, 0 }, |
2095 | { "rdtsc", { XX }, 0 }, | |
2096 | { "rdmsr", { XX }, 0 }, | |
2097 | { "rdpmc", { XX }, 0 }, | |
d835a58b | 2098 | { "sysenter", { SEP }, 0 }, |
e93a3b27 | 2099 | { "sysexit%LQ", { SEP }, 0 }, |
592d1631 | 2100 | { Bad_Opcode }, |
bf890a93 | 2101 | { "getsec", { XX }, 0 }, |
252b5132 | 2102 | /* 38 */ |
b5c37946 | 2103 | { THREE_BYTE_TABLE (THREE_BYTE_0F38) }, |
592d1631 | 2104 | { Bad_Opcode }, |
b5c37946 | 2105 | { THREE_BYTE_TABLE (THREE_BYTE_0F3A) }, |
592d1631 L |
2106 | { Bad_Opcode }, |
2107 | { Bad_Opcode }, | |
2108 | { Bad_Opcode }, | |
2109 | { Bad_Opcode }, | |
2110 | { Bad_Opcode }, | |
252b5132 | 2111 | /* 40 */ |
bf890a93 IT |
2112 | { "cmovoS", { Gv, Ev }, 0 }, |
2113 | { "cmovnoS", { Gv, Ev }, 0 }, | |
2114 | { "cmovbS", { Gv, Ev }, 0 }, | |
2115 | { "cmovaeS", { Gv, Ev }, 0 }, | |
2116 | { "cmoveS", { Gv, Ev }, 0 }, | |
2117 | { "cmovneS", { Gv, Ev }, 0 }, | |
2118 | { "cmovbeS", { Gv, Ev }, 0 }, | |
2119 | { "cmovaS", { Gv, Ev }, 0 }, | |
252b5132 | 2120 | /* 48 */ |
bf890a93 IT |
2121 | { "cmovsS", { Gv, Ev }, 0 }, |
2122 | { "cmovnsS", { Gv, Ev }, 0 }, | |
2123 | { "cmovpS", { Gv, Ev }, 0 }, | |
2124 | { "cmovnpS", { Gv, Ev }, 0 }, | |
2125 | { "cmovlS", { Gv, Ev }, 0 }, | |
2126 | { "cmovgeS", { Gv, Ev }, 0 }, | |
2127 | { "cmovleS", { Gv, Ev }, 0 }, | |
2128 | { "cmovgS", { Gv, Ev }, 0 }, | |
252b5132 | 2129 | /* 50 */ |
b5c37946 | 2130 | { "movmskpX", { Gdq, Ux }, PREFIX_OPCODE }, |
1ceb70f8 L |
2131 | { PREFIX_TABLE (PREFIX_0F51) }, |
2132 | { PREFIX_TABLE (PREFIX_0F52) }, | |
2133 | { PREFIX_TABLE (PREFIX_0F53) }, | |
507bd325 L |
2134 | { "andpX", { XM, EXx }, PREFIX_OPCODE }, |
2135 | { "andnpX", { XM, EXx }, PREFIX_OPCODE }, | |
2136 | { "orpX", { XM, EXx }, PREFIX_OPCODE }, | |
2137 | { "xorpX", { XM, EXx }, PREFIX_OPCODE }, | |
252b5132 | 2138 | /* 58 */ |
1ceb70f8 L |
2139 | { PREFIX_TABLE (PREFIX_0F58) }, |
2140 | { PREFIX_TABLE (PREFIX_0F59) }, | |
2141 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
2142 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
2143 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
2144 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
2145 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
2146 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
252b5132 | 2147 | /* 60 */ |
1ceb70f8 L |
2148 | { PREFIX_TABLE (PREFIX_0F60) }, |
2149 | { PREFIX_TABLE (PREFIX_0F61) }, | |
2150 | { PREFIX_TABLE (PREFIX_0F62) }, | |
507bd325 L |
2151 | { "packsswb", { MX, EM }, PREFIX_OPCODE }, |
2152 | { "pcmpgtb", { MX, EM }, PREFIX_OPCODE }, | |
2153 | { "pcmpgtw", { MX, EM }, PREFIX_OPCODE }, | |
2154 | { "pcmpgtd", { MX, EM }, PREFIX_OPCODE }, | |
2155 | { "packuswb", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2156 | /* 68 */ |
507bd325 L |
2157 | { "punpckhbw", { MX, EM }, PREFIX_OPCODE }, |
2158 | { "punpckhwd", { MX, EM }, PREFIX_OPCODE }, | |
2159 | { "punpckhdq", { MX, EM }, PREFIX_OPCODE }, | |
2160 | { "packssdw", { MX, EM }, PREFIX_OPCODE }, | |
7531c613 JB |
2161 | { "punpcklqdq", { XM, EXx }, PREFIX_DATA }, |
2162 | { "punpckhqdq", { XM, EXx }, PREFIX_DATA }, | |
507bd325 | 2163 | { "movK", { MX, Edq }, PREFIX_OPCODE }, |
1ceb70f8 | 2164 | { PREFIX_TABLE (PREFIX_0F6F) }, |
252b5132 | 2165 | /* 70 */ |
1ceb70f8 | 2166 | { PREFIX_TABLE (PREFIX_0F70) }, |
b5c37946 SJ |
2167 | { REG_TABLE (REG_0F71) }, |
2168 | { REG_TABLE (REG_0F72) }, | |
2169 | { REG_TABLE (REG_0F73) }, | |
507bd325 L |
2170 | { "pcmpeqb", { MX, EM }, PREFIX_OPCODE }, |
2171 | { "pcmpeqw", { MX, EM }, PREFIX_OPCODE }, | |
2172 | { "pcmpeqd", { MX, EM }, PREFIX_OPCODE }, | |
2173 | { "emms", { XX }, PREFIX_OPCODE }, | |
252b5132 | 2174 | /* 78 */ |
1ceb70f8 L |
2175 | { PREFIX_TABLE (PREFIX_0F78) }, |
2176 | { PREFIX_TABLE (PREFIX_0F79) }, | |
1f334aeb | 2177 | { Bad_Opcode }, |
592d1631 | 2178 | { Bad_Opcode }, |
1ceb70f8 L |
2179 | { PREFIX_TABLE (PREFIX_0F7C) }, |
2180 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
2181 | { PREFIX_TABLE (PREFIX_0F7E) }, | |
2182 | { PREFIX_TABLE (PREFIX_0F7F) }, | |
252b5132 | 2183 | /* 80 */ |
bf890a93 IT |
2184 | { "joH", { Jv, BND, cond_jump_flag }, 0 }, |
2185 | { "jnoH", { Jv, BND, cond_jump_flag }, 0 }, | |
2186 | { "jbH", { Jv, BND, cond_jump_flag }, 0 }, | |
2187 | { "jaeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2188 | { "jeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2189 | { "jneH", { Jv, BND, cond_jump_flag }, 0 }, | |
2190 | { "jbeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2191 | { "jaH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2192 | /* 88 */ |
bf890a93 IT |
2193 | { "jsH", { Jv, BND, cond_jump_flag }, 0 }, |
2194 | { "jnsH", { Jv, BND, cond_jump_flag }, 0 }, | |
2195 | { "jpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2196 | { "jnpH", { Jv, BND, cond_jump_flag }, 0 }, | |
2197 | { "jlH", { Jv, BND, cond_jump_flag }, 0 }, | |
2198 | { "jgeH", { Jv, BND, cond_jump_flag }, 0 }, | |
2199 | { "jleH", { Jv, BND, cond_jump_flag }, 0 }, | |
2200 | { "jgH", { Jv, BND, cond_jump_flag }, 0 }, | |
252b5132 | 2201 | /* 90 */ |
bf890a93 IT |
2202 | { "seto", { Eb }, 0 }, |
2203 | { "setno", { Eb }, 0 }, | |
2204 | { "setb", { Eb }, 0 }, | |
2205 | { "setae", { Eb }, 0 }, | |
2206 | { "sete", { Eb }, 0 }, | |
2207 | { "setne", { Eb }, 0 }, | |
2208 | { "setbe", { Eb }, 0 }, | |
2209 | { "seta", { Eb }, 0 }, | |
252b5132 | 2210 | /* 98 */ |
bf890a93 IT |
2211 | { "sets", { Eb }, 0 }, |
2212 | { "setns", { Eb }, 0 }, | |
2213 | { "setp", { Eb }, 0 }, | |
2214 | { "setnp", { Eb }, 0 }, | |
2215 | { "setl", { Eb }, 0 }, | |
2216 | { "setge", { Eb }, 0 }, | |
2217 | { "setle", { Eb }, 0 }, | |
2218 | { "setg", { Eb }, 0 }, | |
252b5132 | 2219 | /* a0 */ |
36938cab JB |
2220 | { "pushP", { fs }, 0 }, |
2221 | { "popP", { fs }, 0 }, | |
bf890a93 IT |
2222 | { "cpuid", { XX }, 0 }, |
2223 | { "btS", { Ev, Gv }, 0 }, | |
2224 | { "shldS", { Ev, Gv, Ib }, 0 }, | |
2225 | { "shldS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 L |
2226 | { REG_TABLE (REG_0FA6) }, |
2227 | { REG_TABLE (REG_0FA7) }, | |
252b5132 | 2228 | /* a8 */ |
36938cab JB |
2229 | { "pushP", { gs }, 0 }, |
2230 | { "popP", { gs }, 0 }, | |
bf890a93 IT |
2231 | { "rsm", { XX }, 0 }, |
2232 | { "btsS", { Evh1, Gv }, 0 }, | |
2233 | { "shrdS", { Ev, Gv, Ib }, 0 }, | |
2234 | { "shrdS", { Ev, Gv, CL }, 0 }, | |
1ceb70f8 | 2235 | { REG_TABLE (REG_0FAE) }, |
bf890a93 | 2236 | { "imulS", { Gv, Ev }, 0 }, |
252b5132 | 2237 | /* b0 */ |
bf890a93 IT |
2238 | { "cmpxchgB", { Ebh1, Gb }, 0 }, |
2239 | { "cmpxchgS", { Evh1, Gv }, 0 }, | |
b5c37946 | 2240 | { "lssS", { Gv, Mp }, 0 }, |
bf890a93 | 2241 | { "btrS", { Evh1, Gv }, 0 }, |
b5c37946 SJ |
2242 | { "lfsS", { Gv, Mp }, 0 }, |
2243 | { "lgsS", { Gv, Mp }, 0 }, | |
bf890a93 IT |
2244 | { "movz{bR|x}", { Gv, Eb }, 0 }, |
2245 | { "movz{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movzww ! */ | |
252b5132 | 2246 | /* b8 */ |
1ceb70f8 | 2247 | { PREFIX_TABLE (PREFIX_0FB8) }, |
66f1eba0 | 2248 | { "ud1S", { Gv, Ev }, 0 }, |
1ceb70f8 | 2249 | { REG_TABLE (REG_0FBA) }, |
bf890a93 | 2250 | { "btcS", { Evh1, Gv }, 0 }, |
f12dc422 | 2251 | { PREFIX_TABLE (PREFIX_0FBC) }, |
1ceb70f8 | 2252 | { PREFIX_TABLE (PREFIX_0FBD) }, |
bf890a93 IT |
2253 | { "movs{bR|x}", { Gv, Eb }, 0 }, |
2254 | { "movs{wR|x}", { Gv, Ew }, 0 }, /* yes, there really is movsww ! */ | |
252b5132 | 2255 | /* c0 */ |
bf890a93 IT |
2256 | { "xaddB", { Ebh1, Gb }, 0 }, |
2257 | { "xaddS", { Evh1, Gv }, 0 }, | |
1ceb70f8 | 2258 | { PREFIX_TABLE (PREFIX_0FC2) }, |
b5c37946 | 2259 | { "movntiS", { Mdq, Gdq }, PREFIX_OPCODE }, |
5fbe0f28 | 2260 | { "pinsrw", { MX, Edw, Ib }, PREFIX_OPCODE }, |
b5c37946 | 2261 | { "pextrw", { Gd, Nq, Ib }, PREFIX_OPCODE }, |
507bd325 | 2262 | { "shufpX", { XM, EXx, Ib }, PREFIX_OPCODE }, |
1ceb70f8 | 2263 | { REG_TABLE (REG_0FC7) }, |
252b5132 | 2264 | /* c8 */ |
bf890a93 IT |
2265 | { "bswap", { RMeAX }, 0 }, |
2266 | { "bswap", { RMeCX }, 0 }, | |
2267 | { "bswap", { RMeDX }, 0 }, | |
2268 | { "bswap", { RMeBX }, 0 }, | |
2269 | { "bswap", { RMeSP }, 0 }, | |
2270 | { "bswap", { RMeBP }, 0 }, | |
2271 | { "bswap", { RMeSI }, 0 }, | |
2272 | { "bswap", { RMeDI }, 0 }, | |
252b5132 | 2273 | /* d0 */ |
1ceb70f8 | 2274 | { PREFIX_TABLE (PREFIX_0FD0) }, |
507bd325 L |
2275 | { "psrlw", { MX, EM }, PREFIX_OPCODE }, |
2276 | { "psrld", { MX, EM }, PREFIX_OPCODE }, | |
2277 | { "psrlq", { MX, EM }, PREFIX_OPCODE }, | |
2278 | { "paddq", { MX, EM }, PREFIX_OPCODE }, | |
2279 | { "pmullw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2280 | { PREFIX_TABLE (PREFIX_0FD6) }, |
b5c37946 | 2281 | { "pmovmskb", { Gdq, Nq }, PREFIX_OPCODE }, |
252b5132 | 2282 | /* d8 */ |
507bd325 L |
2283 | { "psubusb", { MX, EM }, PREFIX_OPCODE }, |
2284 | { "psubusw", { MX, EM }, PREFIX_OPCODE }, | |
2285 | { "pminub", { MX, EM }, PREFIX_OPCODE }, | |
2286 | { "pand", { MX, EM }, PREFIX_OPCODE }, | |
2287 | { "paddusb", { MX, EM }, PREFIX_OPCODE }, | |
2288 | { "paddusw", { MX, EM }, PREFIX_OPCODE }, | |
2289 | { "pmaxub", { MX, EM }, PREFIX_OPCODE }, | |
2290 | { "pandn", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2291 | /* e0 */ |
507bd325 L |
2292 | { "pavgb", { MX, EM }, PREFIX_OPCODE }, |
2293 | { "psraw", { MX, EM }, PREFIX_OPCODE }, | |
2294 | { "psrad", { MX, EM }, PREFIX_OPCODE }, | |
2295 | { "pavgw", { MX, EM }, PREFIX_OPCODE }, | |
2296 | { "pmulhuw", { MX, EM }, PREFIX_OPCODE }, | |
2297 | { "pmulhw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 L |
2298 | { PREFIX_TABLE (PREFIX_0FE6) }, |
2299 | { PREFIX_TABLE (PREFIX_0FE7) }, | |
252b5132 | 2300 | /* e8 */ |
507bd325 L |
2301 | { "psubsb", { MX, EM }, PREFIX_OPCODE }, |
2302 | { "psubsw", { MX, EM }, PREFIX_OPCODE }, | |
2303 | { "pminsw", { MX, EM }, PREFIX_OPCODE }, | |
2304 | { "por", { MX, EM }, PREFIX_OPCODE }, | |
2305 | { "paddsb", { MX, EM }, PREFIX_OPCODE }, | |
2306 | { "paddsw", { MX, EM }, PREFIX_OPCODE }, | |
2307 | { "pmaxsw", { MX, EM }, PREFIX_OPCODE }, | |
2308 | { "pxor", { MX, EM }, PREFIX_OPCODE }, | |
252b5132 | 2309 | /* f0 */ |
1ceb70f8 | 2310 | { PREFIX_TABLE (PREFIX_0FF0) }, |
507bd325 L |
2311 | { "psllw", { MX, EM }, PREFIX_OPCODE }, |
2312 | { "pslld", { MX, EM }, PREFIX_OPCODE }, | |
2313 | { "psllq", { MX, EM }, PREFIX_OPCODE }, | |
2314 | { "pmuludq", { MX, EM }, PREFIX_OPCODE }, | |
2315 | { "pmaddwd", { MX, EM }, PREFIX_OPCODE }, | |
2316 | { "psadbw", { MX, EM }, PREFIX_OPCODE }, | |
1ceb70f8 | 2317 | { PREFIX_TABLE (PREFIX_0FF7) }, |
252b5132 | 2318 | /* f8 */ |
507bd325 L |
2319 | { "psubb", { MX, EM }, PREFIX_OPCODE }, |
2320 | { "psubw", { MX, EM }, PREFIX_OPCODE }, | |
2321 | { "psubd", { MX, EM }, PREFIX_OPCODE }, | |
2322 | { "psubq", { MX, EM }, PREFIX_OPCODE }, | |
2323 | { "paddb", { MX, EM }, PREFIX_OPCODE }, | |
2324 | { "paddw", { MX, EM }, PREFIX_OPCODE }, | |
2325 | { "paddd", { MX, EM }, PREFIX_OPCODE }, | |
66f1eba0 | 2326 | { "ud0S", { Gv, Ev }, 0 }, |
252b5132 RH |
2327 | }; |
2328 | ||
ab31da6a | 2329 | static const bool onebyte_has_modrm[256] = { |
c608c12e AM |
2330 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2331 | /* ------------------------------- */ | |
2332 | /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */ | |
2333 | /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */ | |
2334 | /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */ | |
2335 | /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */ | |
2336 | /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */ | |
2337 | /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */ | |
2338 | /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */ | |
2339 | /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */ | |
2340 | /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */ | |
2341 | /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */ | |
2342 | /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */ | |
2343 | /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */ | |
2344 | /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */ | |
2345 | /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */ | |
2346 | /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */ | |
2347 | /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1 /* f0 */ | |
2348 | /* ------------------------------- */ | |
2349 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
252b5132 RH |
2350 | }; |
2351 | ||
ab31da6a | 2352 | static const bool twobyte_has_modrm[256] = { |
c608c12e AM |
2353 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ |
2354 | /* ------------------------------- */ | |
252b5132 | 2355 | /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */ |
b5b1fc4f | 2356 | /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */ |
85f10a01 | 2357 | /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */ |
331d2d0d | 2358 | /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */ |
252b5132 | 2359 | /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */ |
4bba6815 AM |
2360 | /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */ |
2361 | /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */ | |
85f10a01 | 2362 | /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */ |
252b5132 RH |
2363 | /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */ |
2364 | /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */ | |
30d1c836 | 2365 | /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */ |
66f1eba0 | 2366 | /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */ |
252b5132 | 2367 | /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */ |
ca164297 | 2368 | /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */ |
4bba6815 | 2369 | /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */ |
66f1eba0 | 2370 | /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1 /* ff */ |
c608c12e AM |
2371 | /* ------------------------------- */ |
2372 | /* 0 1 2 3 4 5 6 7 8 9 a b c d e f */ | |
2373 | }; | |
2374 | ||
252b5132 | 2375 | |
ea397f5b L |
2376 | struct op |
2377 | { | |
2378 | const char *name; | |
2379 | unsigned int len; | |
2380 | }; | |
2381 | ||
4bba6815 AM |
2382 | /* If we are accessing mod/rm/reg without need_modrm set, then the |
2383 | values are stale. Hitting this abort likely indicates that you | |
2384 | need to update onebyte_has_modrm or twobyte_has_modrm. */ | |
39fb3698 | 2385 | #define MODRM_CHECK if (!ins->need_modrm) abort () |
d708bcba | 2386 | |
2d9e0890 | 2387 | static const char intel_index16[][6] = { |
d708bcba AM |
2388 | "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx" |
2389 | }; | |
2390 | ||
2d9e0890 | 2391 | static const char att_names64[][8] = { |
d708bcba | 2392 | "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi", |
52b15da3 JH |
2393 | "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15" |
2394 | }; | |
2d9e0890 | 2395 | static const char att_names32[][8] = { |
d708bcba | 2396 | "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi", |
52b15da3 | 2397 | "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d" |
252b5132 | 2398 | }; |
2d9e0890 | 2399 | static const char att_names16[][8] = { |
d708bcba | 2400 | "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di", |
52b15da3 | 2401 | "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w" |
252b5132 | 2402 | }; |
2d9e0890 | 2403 | static const char att_names8[][8] = { |
d708bcba | 2404 | "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh", |
252b5132 | 2405 | }; |
2d9e0890 | 2406 | static const char att_names8rex[][8] = { |
d708bcba | 2407 | "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil", |
52b15da3 JH |
2408 | "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b" |
2409 | }; | |
2d9e0890 | 2410 | static const char att_names_seg[][4] = { |
d708bcba | 2411 | "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?", |
252b5132 | 2412 | }; |
2a78304e JB |
2413 | static const char att_index64[] = "%riz"; |
2414 | static const char att_index32[] = "%eiz"; | |
2d9e0890 | 2415 | static const char att_index16[][8] = { |
d708bcba | 2416 | "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx" |
252b5132 RH |
2417 | }; |
2418 | ||
2d9e0890 | 2419 | static const char att_names_mm[][8] = { |
b9733481 L |
2420 | "%mm0", "%mm1", "%mm2", "%mm3", |
2421 | "%mm4", "%mm5", "%mm6", "%mm7" | |
2422 | }; | |
2423 | ||
2d9e0890 | 2424 | static const char att_names_bnd[][8] = { |
7e8b059b L |
2425 | "%bnd0", "%bnd1", "%bnd2", "%bnd3" |
2426 | }; | |
2427 | ||
2d9e0890 | 2428 | static const char att_names_xmm[][8] = { |
b9733481 L |
2429 | "%xmm0", "%xmm1", "%xmm2", "%xmm3", |
2430 | "%xmm4", "%xmm5", "%xmm6", "%xmm7", | |
2431 | "%xmm8", "%xmm9", "%xmm10", "%xmm11", | |
43234a1e L |
2432 | "%xmm12", "%xmm13", "%xmm14", "%xmm15", |
2433 | "%xmm16", "%xmm17", "%xmm18", "%xmm19", | |
2434 | "%xmm20", "%xmm21", "%xmm22", "%xmm23", | |
2435 | "%xmm24", "%xmm25", "%xmm26", "%xmm27", | |
2436 | "%xmm28", "%xmm29", "%xmm30", "%xmm31" | |
b9733481 L |
2437 | }; |
2438 | ||
2d9e0890 | 2439 | static const char att_names_ymm[][8] = { |
b9733481 L |
2440 | "%ymm0", "%ymm1", "%ymm2", "%ymm3", |
2441 | "%ymm4", "%ymm5", "%ymm6", "%ymm7", | |
2442 | "%ymm8", "%ymm9", "%ymm10", "%ymm11", | |
43234a1e L |
2443 | "%ymm12", "%ymm13", "%ymm14", "%ymm15", |
2444 | "%ymm16", "%ymm17", "%ymm18", "%ymm19", | |
2445 | "%ymm20", "%ymm21", "%ymm22", "%ymm23", | |
2446 | "%ymm24", "%ymm25", "%ymm26", "%ymm27", | |
2447 | "%ymm28", "%ymm29", "%ymm30", "%ymm31" | |
2448 | }; | |
2449 | ||
2d9e0890 | 2450 | static const char att_names_zmm[][8] = { |
43234a1e L |
2451 | "%zmm0", "%zmm1", "%zmm2", "%zmm3", |
2452 | "%zmm4", "%zmm5", "%zmm6", "%zmm7", | |
2453 | "%zmm8", "%zmm9", "%zmm10", "%zmm11", | |
2454 | "%zmm12", "%zmm13", "%zmm14", "%zmm15", | |
2455 | "%zmm16", "%zmm17", "%zmm18", "%zmm19", | |
2456 | "%zmm20", "%zmm21", "%zmm22", "%zmm23", | |
2457 | "%zmm24", "%zmm25", "%zmm26", "%zmm27", | |
2458 | "%zmm28", "%zmm29", "%zmm30", "%zmm31" | |
2459 | }; | |
2460 | ||
2d9e0890 | 2461 | static const char att_names_tmm[][8] = { |
260cd341 LC |
2462 | "%tmm0", "%tmm1", "%tmm2", "%tmm3", |
2463 | "%tmm4", "%tmm5", "%tmm6", "%tmm7" | |
2464 | }; | |
2465 | ||
2d9e0890 | 2466 | static const char att_names_mask[][8] = { |
43234a1e L |
2467 | "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7" |
2468 | }; | |
2469 | ||
0e4cc773 | 2470 | static const char *const names_rounding[] = |
43234a1e | 2471 | { |
0e4cc773 JB |
2472 | "{rn-", |
2473 | "{rd-", | |
2474 | "{ru-", | |
2475 | "{rz-" | |
b9733481 L |
2476 | }; |
2477 | ||
1ceb70f8 L |
2478 | static const struct dis386 reg_table[][8] = { |
2479 | /* REG_80 */ | |
252b5132 | 2480 | { |
bf890a93 IT |
2481 | { "addA", { Ebh1, Ib }, 0 }, |
2482 | { "orA", { Ebh1, Ib }, 0 }, | |
2483 | { "adcA", { Ebh1, Ib }, 0 }, | |
2484 | { "sbbA", { Ebh1, Ib }, 0 }, | |
2485 | { "andA", { Ebh1, Ib }, 0 }, | |
2486 | { "subA", { Ebh1, Ib }, 0 }, | |
2487 | { "xorA", { Ebh1, Ib }, 0 }, | |
2488 | { "cmpA", { Eb, Ib }, 0 }, | |
252b5132 | 2489 | }, |
1ceb70f8 | 2490 | /* REG_81 */ |
252b5132 | 2491 | { |
bf890a93 IT |
2492 | { "addQ", { Evh1, Iv }, 0 }, |
2493 | { "orQ", { Evh1, Iv }, 0 }, | |
2494 | { "adcQ", { Evh1, Iv }, 0 }, | |
2495 | { "sbbQ", { Evh1, Iv }, 0 }, | |
2496 | { "andQ", { Evh1, Iv }, 0 }, | |
2497 | { "subQ", { Evh1, Iv }, 0 }, | |
2498 | { "xorQ", { Evh1, Iv }, 0 }, | |
2499 | { "cmpQ", { Ev, Iv }, 0 }, | |
252b5132 | 2500 | }, |
7148c369 | 2501 | /* REG_83 */ |
252b5132 | 2502 | { |
bf890a93 IT |
2503 | { "addQ", { Evh1, sIb }, 0 }, |
2504 | { "orQ", { Evh1, sIb }, 0 }, | |
2505 | { "adcQ", { Evh1, sIb }, 0 }, | |
2506 | { "sbbQ", { Evh1, sIb }, 0 }, | |
2507 | { "andQ", { Evh1, sIb }, 0 }, | |
2508 | { "subQ", { Evh1, sIb }, 0 }, | |
2509 | { "xorQ", { Evh1, sIb }, 0 }, | |
2510 | { "cmpQ", { Ev, sIb }, 0 }, | |
252b5132 | 2511 | }, |
1ceb70f8 | 2512 | /* REG_8F */ |
4e7d34a6 | 2513 | { |
36938cab | 2514 | { "pop{P|}", { stackEv }, 0 }, |
b5c37946 | 2515 | { XOP_8F_TABLE () }, |
592d1631 L |
2516 | { Bad_Opcode }, |
2517 | { Bad_Opcode }, | |
2518 | { Bad_Opcode }, | |
b5c37946 | 2519 | { XOP_8F_TABLE () }, |
4e7d34a6 | 2520 | }, |
1ceb70f8 | 2521 | /* REG_C0 */ |
252b5132 | 2522 | { |
bf890a93 IT |
2523 | { "rolA", { Eb, Ib }, 0 }, |
2524 | { "rorA", { Eb, Ib }, 0 }, | |
2525 | { "rclA", { Eb, Ib }, 0 }, | |
2526 | { "rcrA", { Eb, Ib }, 0 }, | |
2527 | { "shlA", { Eb, Ib }, 0 }, | |
2528 | { "shrA", { Eb, Ib }, 0 }, | |
e4bdd679 | 2529 | { "shlA", { Eb, Ib }, 0 }, |
bf890a93 | 2530 | { "sarA", { Eb, Ib }, 0 }, |
252b5132 | 2531 | }, |
1ceb70f8 | 2532 | /* REG_C1 */ |
252b5132 | 2533 | { |
bf890a93 IT |
2534 | { "rolQ", { Ev, Ib }, 0 }, |
2535 | { "rorQ", { Ev, Ib }, 0 }, | |
2536 | { "rclQ", { Ev, Ib }, 0 }, | |
2537 | { "rcrQ", { Ev, Ib }, 0 }, | |
2538 | { "shlQ", { Ev, Ib }, 0 }, | |
2539 | { "shrQ", { Ev, Ib }, 0 }, | |
e4bdd679 | 2540 | { "shlQ", { Ev, Ib }, 0 }, |
bf890a93 | 2541 | { "sarQ", { Ev, Ib }, 0 }, |
252b5132 | 2542 | }, |
1ceb70f8 | 2543 | /* REG_C6 */ |
4e7d34a6 | 2544 | { |
bf890a93 | 2545 | { "movA", { Ebh3, Ib }, 0 }, |
42164a71 L |
2546 | { Bad_Opcode }, |
2547 | { Bad_Opcode }, | |
2548 | { Bad_Opcode }, | |
2549 | { Bad_Opcode }, | |
2550 | { Bad_Opcode }, | |
2551 | { Bad_Opcode }, | |
b5c37946 | 2552 | { RM_TABLE (RM_C6_REG_7) }, |
4e7d34a6 | 2553 | }, |
1ceb70f8 | 2554 | /* REG_C7 */ |
4e7d34a6 | 2555 | { |
bf890a93 | 2556 | { "movQ", { Evh3, Iv }, 0 }, |
42164a71 L |
2557 | { Bad_Opcode }, |
2558 | { Bad_Opcode }, | |
2559 | { Bad_Opcode }, | |
2560 | { Bad_Opcode }, | |
2561 | { Bad_Opcode }, | |
2562 | { Bad_Opcode }, | |
b5c37946 | 2563 | { RM_TABLE (RM_C7_REG_7) }, |
4e7d34a6 | 2564 | }, |
1ceb70f8 | 2565 | /* REG_D0 */ |
252b5132 | 2566 | { |
bf890a93 IT |
2567 | { "rolA", { Eb, I1 }, 0 }, |
2568 | { "rorA", { Eb, I1 }, 0 }, | |
2569 | { "rclA", { Eb, I1 }, 0 }, | |
2570 | { "rcrA", { Eb, I1 }, 0 }, | |
2571 | { "shlA", { Eb, I1 }, 0 }, | |
2572 | { "shrA", { Eb, I1 }, 0 }, | |
e4bdd679 | 2573 | { "shlA", { Eb, I1 }, 0 }, |
bf890a93 | 2574 | { "sarA", { Eb, I1 }, 0 }, |
252b5132 | 2575 | }, |
1ceb70f8 | 2576 | /* REG_D1 */ |
252b5132 | 2577 | { |
bf890a93 IT |
2578 | { "rolQ", { Ev, I1 }, 0 }, |
2579 | { "rorQ", { Ev, I1 }, 0 }, | |
2580 | { "rclQ", { Ev, I1 }, 0 }, | |
2581 | { "rcrQ", { Ev, I1 }, 0 }, | |
2582 | { "shlQ", { Ev, I1 }, 0 }, | |
2583 | { "shrQ", { Ev, I1 }, 0 }, | |
e4bdd679 | 2584 | { "shlQ", { Ev, I1 }, 0 }, |
bf890a93 | 2585 | { "sarQ", { Ev, I1 }, 0 }, |
252b5132 | 2586 | }, |
1ceb70f8 | 2587 | /* REG_D2 */ |
252b5132 | 2588 | { |
bf890a93 IT |
2589 | { "rolA", { Eb, CL }, 0 }, |
2590 | { "rorA", { Eb, CL }, 0 }, | |
2591 | { "rclA", { Eb, CL }, 0 }, | |
2592 | { "rcrA", { Eb, CL }, 0 }, | |
2593 | { "shlA", { Eb, CL }, 0 }, | |
2594 | { "shrA", { Eb, CL }, 0 }, | |
e4bdd679 | 2595 | { "shlA", { Eb, CL }, 0 }, |
bf890a93 | 2596 | { "sarA", { Eb, CL }, 0 }, |
252b5132 | 2597 | }, |
1ceb70f8 | 2598 | /* REG_D3 */ |
252b5132 | 2599 | { |
bf890a93 IT |
2600 | { "rolQ", { Ev, CL }, 0 }, |
2601 | { "rorQ", { Ev, CL }, 0 }, | |
2602 | { "rclQ", { Ev, CL }, 0 }, | |
2603 | { "rcrQ", { Ev, CL }, 0 }, | |
2604 | { "shlQ", { Ev, CL }, 0 }, | |
2605 | { "shrQ", { Ev, CL }, 0 }, | |
e4bdd679 | 2606 | { "shlQ", { Ev, CL }, 0 }, |
bf890a93 | 2607 | { "sarQ", { Ev, CL }, 0 }, |
252b5132 | 2608 | }, |
1ceb70f8 | 2609 | /* REG_F6 */ |
252b5132 | 2610 | { |
bf890a93 | 2611 | { "testA", { Eb, Ib }, 0 }, |
7db2c588 | 2612 | { "testA", { Eb, Ib }, 0 }, |
bf890a93 IT |
2613 | { "notA", { Ebh1 }, 0 }, |
2614 | { "negA", { Ebh1 }, 0 }, | |
2615 | { "mulA", { Eb }, 0 }, /* Don't print the implicit %al register, */ | |
2616 | { "imulA", { Eb }, 0 }, /* to distinguish these opcodes from other */ | |
2617 | { "divA", { Eb }, 0 }, /* mul/imul opcodes. Do the same for div */ | |
2618 | { "idivA", { Eb }, 0 }, /* and idiv for consistency. */ | |
252b5132 | 2619 | }, |
1ceb70f8 | 2620 | /* REG_F7 */ |
252b5132 | 2621 | { |
bf890a93 | 2622 | { "testQ", { Ev, Iv }, 0 }, |
7db2c588 | 2623 | { "testQ", { Ev, Iv }, 0 }, |
bf890a93 IT |
2624 | { "notQ", { Evh1 }, 0 }, |
2625 | { "negQ", { Evh1 }, 0 }, | |
2626 | { "mulQ", { Ev }, 0 }, /* Don't print the implicit register. */ | |
2627 | { "imulQ", { Ev }, 0 }, | |
2628 | { "divQ", { Ev }, 0 }, | |
2629 | { "idivQ", { Ev }, 0 }, | |
252b5132 | 2630 | }, |
1ceb70f8 | 2631 | /* REG_FE */ |
252b5132 | 2632 | { |
bf890a93 IT |
2633 | { "incA", { Ebh1 }, 0 }, |
2634 | { "decA", { Ebh1 }, 0 }, | |
252b5132 | 2635 | }, |
1ceb70f8 | 2636 | /* REG_FF */ |
252b5132 | 2637 | { |
bf890a93 IT |
2638 | { "incQ", { Evh1 }, 0 }, |
2639 | { "decQ", { Evh1 }, 0 }, | |
36938cab | 2640 | { "call{@|}", { NOTRACK, indirEv, BND }, 0 }, |
b5c37946 | 2641 | { "{l|}call^", { indirEp }, 0 }, |
36938cab | 2642 | { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 }, |
b5c37946 | 2643 | { "{l|}jmp^", { indirEp }, 0 }, |
36938cab | 2644 | { "push{P|}", { stackEv }, 0 }, |
592d1631 | 2645 | { Bad_Opcode }, |
252b5132 | 2646 | }, |
1ceb70f8 | 2647 | /* REG_0F00 */ |
252b5132 | 2648 | { |
bf890a93 IT |
2649 | { "sldtD", { Sv }, 0 }, |
2650 | { "strD", { Sv }, 0 }, | |
b5c37946 SJ |
2651 | { "lldtD", { Sv }, 0 }, |
2652 | { "ltrD", { Sv }, 0 }, | |
2653 | { "verrD", { Sv }, 0 }, | |
2654 | { "verwD", { Sv }, 0 }, | |
c88ed92f | 2655 | { X86_64_TABLE (X86_64_0F00_REG_6) }, |
592d1631 | 2656 | { Bad_Opcode }, |
252b5132 | 2657 | }, |
1ceb70f8 | 2658 | /* REG_0F01 */ |
252b5132 | 2659 | { |
1ceb70f8 L |
2660 | { MOD_TABLE (MOD_0F01_REG_0) }, |
2661 | { MOD_TABLE (MOD_0F01_REG_1) }, | |
2662 | { MOD_TABLE (MOD_0F01_REG_2) }, | |
2663 | { MOD_TABLE (MOD_0F01_REG_3) }, | |
bf890a93 | 2664 | { "smswD", { Sv }, 0 }, |
8eab4136 | 2665 | { MOD_TABLE (MOD_0F01_REG_5) }, |
bf890a93 | 2666 | { "lmsw", { Ew }, 0 }, |
1ceb70f8 | 2667 | { MOD_TABLE (MOD_0F01_REG_7) }, |
252b5132 | 2668 | }, |
b5b1fc4f | 2669 | /* REG_0F0D */ |
252b5132 | 2670 | { |
bf890a93 IT |
2671 | { "prefetch", { Mb }, 0 }, |
2672 | { "prefetchw", { Mb }, 0 }, | |
2673 | { "prefetchwt1", { Mb }, 0 }, | |
2674 | { "prefetch", { Mb }, 0 }, | |
2675 | { "prefetch", { Mb }, 0 }, | |
2676 | { "prefetch", { Mb }, 0 }, | |
2677 | { "prefetch", { Mb }, 0 }, | |
2678 | { "prefetch", { Mb }, 0 }, | |
252b5132 | 2679 | }, |
1ceb70f8 | 2680 | /* REG_0F18 */ |
252b5132 | 2681 | { |
1ceb70f8 L |
2682 | { MOD_TABLE (MOD_0F18_REG_0) }, |
2683 | { MOD_TABLE (MOD_0F18_REG_1) }, | |
2684 | { MOD_TABLE (MOD_0F18_REG_2) }, | |
2685 | { MOD_TABLE (MOD_0F18_REG_3) }, | |
31941983 JB |
2686 | { "nopQ", { Ev }, 0 }, |
2687 | { "nopQ", { Ev }, 0 }, | |
ef07be45 CL |
2688 | { MOD_TABLE (MOD_0F18_REG_6) }, |
2689 | { MOD_TABLE (MOD_0F18_REG_7) }, | |
252b5132 | 2690 | }, |
f8687e93 | 2691 | /* REG_0F1C_P_0_MOD_0 */ |
c48935d7 IT |
2692 | { |
2693 | { "cldemote", { Mb }, 0 }, | |
2694 | { "nopQ", { Ev }, 0 }, | |
2695 | { "nopQ", { Ev }, 0 }, | |
2696 | { "nopQ", { Ev }, 0 }, | |
2697 | { "nopQ", { Ev }, 0 }, | |
2698 | { "nopQ", { Ev }, 0 }, | |
2699 | { "nopQ", { Ev }, 0 }, | |
2700 | { "nopQ", { Ev }, 0 }, | |
2701 | }, | |
f8687e93 | 2702 | /* REG_0F1E_P_1_MOD_3 */ |
603555e5 | 2703 | { |
31941983 JB |
2704 | { "nopQ", { Ev }, PREFIX_IGNORED }, |
2705 | { "rdsspK", { Edq }, 0 }, | |
2706 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
2707 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
2708 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
2709 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
2710 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
f8687e93 | 2711 | { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) }, |
603555e5 | 2712 | }, |
c4694f17 TG |
2713 | /* REG_0F38D8_PREFIX_1 */ |
2714 | { | |
2715 | { "aesencwide128kl", { M }, 0 }, | |
2716 | { "aesdecwide128kl", { M }, 0 }, | |
2717 | { "aesencwide256kl", { M }, 0 }, | |
2718 | { "aesdecwide256kl", { M }, 0 }, | |
2719 | }, | |
b5c37946 | 2720 | /* REG_0F3A0F_P_1 */ |
c1fa250a | 2721 | { |
b5c37946 | 2722 | { RM_TABLE (RM_0F3A0F_P_1_R_0) }, |
c1fa250a | 2723 | }, |
b5c37946 | 2724 | /* REG_0F71 */ |
a6bd098c | 2725 | { |
592d1631 L |
2726 | { Bad_Opcode }, |
2727 | { Bad_Opcode }, | |
b5c37946 | 2728 | { "psrlw", { Nq, Ib }, PREFIX_OPCODE }, |
592d1631 | 2729 | { Bad_Opcode }, |
b5c37946 | 2730 | { "psraw", { Nq, Ib }, PREFIX_OPCODE }, |
592d1631 | 2731 | { Bad_Opcode }, |
b5c37946 | 2732 | { "psllw", { Nq, Ib }, PREFIX_OPCODE }, |
a6bd098c | 2733 | }, |
b5c37946 | 2734 | /* REG_0F72 */ |
a6bd098c | 2735 | { |
592d1631 L |
2736 | { Bad_Opcode }, |
2737 | { Bad_Opcode }, | |
b5c37946 | 2738 | { "psrld", { Nq, Ib }, PREFIX_OPCODE }, |
592d1631 | 2739 | { Bad_Opcode }, |
b5c37946 | 2740 | { "psrad", { Nq, Ib }, PREFIX_OPCODE }, |
592d1631 | 2741 | { Bad_Opcode }, |
b5c37946 | 2742 | { "pslld", { Nq, Ib }, PREFIX_OPCODE }, |
a6bd098c | 2743 | }, |
b5c37946 | 2744 | /* REG_0F73 */ |
252b5132 | 2745 | { |
592d1631 L |
2746 | { Bad_Opcode }, |
2747 | { Bad_Opcode }, | |
b5c37946 SJ |
2748 | { "psrlq", { Nq, Ib }, PREFIX_OPCODE }, |
2749 | { "psrldq", { Ux, Ib }, PREFIX_DATA }, | |
592d1631 L |
2750 | { Bad_Opcode }, |
2751 | { Bad_Opcode }, | |
b5c37946 SJ |
2752 | { "psllq", { Nq, Ib }, PREFIX_OPCODE }, |
2753 | { "pslldq", { Ux, Ib }, PREFIX_DATA }, | |
252b5132 | 2754 | }, |
1ceb70f8 | 2755 | /* REG_0FA6 */ |
252b5132 | 2756 | { |
bf890a93 IT |
2757 | { "montmul", { { OP_0f07, 0 } }, 0 }, |
2758 | { "xsha1", { { OP_0f07, 0 } }, 0 }, | |
2759 | { "xsha256", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2760 | }, |
1ceb70f8 | 2761 | /* REG_0FA7 */ |
4e7d34a6 | 2762 | { |
bf890a93 IT |
2763 | { "xstore-rng", { { OP_0f07, 0 } }, 0 }, |
2764 | { "xcrypt-ecb", { { OP_0f07, 0 } }, 0 }, | |
2765 | { "xcrypt-cbc", { { OP_0f07, 0 } }, 0 }, | |
2766 | { "xcrypt-ctr", { { OP_0f07, 0 } }, 0 }, | |
2767 | { "xcrypt-cfb", { { OP_0f07, 0 } }, 0 }, | |
2768 | { "xcrypt-ofb", { { OP_0f07, 0 } }, 0 }, | |
4e7d34a6 | 2769 | }, |
1ceb70f8 | 2770 | /* REG_0FAE */ |
4e7d34a6 | 2771 | { |
1ceb70f8 L |
2772 | { MOD_TABLE (MOD_0FAE_REG_0) }, |
2773 | { MOD_TABLE (MOD_0FAE_REG_1) }, | |
2774 | { MOD_TABLE (MOD_0FAE_REG_2) }, | |
2775 | { MOD_TABLE (MOD_0FAE_REG_3) }, | |
475a2301 | 2776 | { MOD_TABLE (MOD_0FAE_REG_4) }, |
1ceb70f8 L |
2777 | { MOD_TABLE (MOD_0FAE_REG_5) }, |
2778 | { MOD_TABLE (MOD_0FAE_REG_6) }, | |
2779 | { MOD_TABLE (MOD_0FAE_REG_7) }, | |
252b5132 | 2780 | }, |
1ceb70f8 | 2781 | /* REG_0FBA */ |
252b5132 | 2782 | { |
592d1631 L |
2783 | { Bad_Opcode }, |
2784 | { Bad_Opcode }, | |
2785 | { Bad_Opcode }, | |
2786 | { Bad_Opcode }, | |
bf890a93 IT |
2787 | { "btQ", { Ev, Ib }, 0 }, |
2788 | { "btsQ", { Evh1, Ib }, 0 }, | |
2789 | { "btrQ", { Evh1, Ib }, 0 }, | |
2790 | { "btcQ", { Evh1, Ib }, 0 }, | |
c608c12e | 2791 | }, |
1ceb70f8 | 2792 | /* REG_0FC7 */ |
c608c12e | 2793 | { |
592d1631 | 2794 | { Bad_Opcode }, |
bf890a93 | 2795 | { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 }, |
592d1631 | 2796 | { Bad_Opcode }, |
b5c37946 SJ |
2797 | { "xrstors", { FXSAVE }, 0 }, |
2798 | { "xsavec", { FXSAVE }, 0 }, | |
2799 | { "xsaves", { FXSAVE }, 0 }, | |
1ceb70f8 L |
2800 | { MOD_TABLE (MOD_0FC7_REG_6) }, |
2801 | { MOD_TABLE (MOD_0FC7_REG_7) }, | |
252b5132 | 2802 | }, |
b5c37946 | 2803 | /* REG_VEX_0F71 */ |
c0f3af97 | 2804 | { |
592d1631 L |
2805 | { Bad_Opcode }, |
2806 | { Bad_Opcode }, | |
b5c37946 | 2807 | { "vpsrlw", { Vex, Ux, Ib }, PREFIX_DATA }, |
592d1631 | 2808 | { Bad_Opcode }, |
b5c37946 | 2809 | { "vpsraw", { Vex, Ux, Ib }, PREFIX_DATA }, |
592d1631 | 2810 | { Bad_Opcode }, |
b5c37946 | 2811 | { "vpsllw", { Vex, Ux, Ib }, PREFIX_DATA }, |
c0f3af97 | 2812 | }, |
b5c37946 | 2813 | /* REG_VEX_0F72 */ |
c0f3af97 | 2814 | { |
592d1631 L |
2815 | { Bad_Opcode }, |
2816 | { Bad_Opcode }, | |
b5c37946 | 2817 | { "vpsrld", { Vex, Ux, Ib }, PREFIX_DATA }, |
592d1631 | 2818 | { Bad_Opcode }, |
b5c37946 | 2819 | { "vpsrad", { Vex, Ux, Ib }, PREFIX_DATA }, |
592d1631 | 2820 | { Bad_Opcode }, |
b5c37946 | 2821 | { "vpslld", { Vex, Ux, Ib }, PREFIX_DATA }, |
c0f3af97 | 2822 | }, |
b5c37946 | 2823 | /* REG_VEX_0F73 */ |
c0f3af97 | 2824 | { |
592d1631 L |
2825 | { Bad_Opcode }, |
2826 | { Bad_Opcode }, | |
b5c37946 SJ |
2827 | { "vpsrlq", { Vex, Ux, Ib }, PREFIX_DATA }, |
2828 | { "vpsrldq", { Vex, Ux, Ib }, PREFIX_DATA }, | |
592d1631 L |
2829 | { Bad_Opcode }, |
2830 | { Bad_Opcode }, | |
b5c37946 SJ |
2831 | { "vpsllq", { Vex, Ux, Ib }, PREFIX_DATA }, |
2832 | { "vpslldq", { Vex, Ux, Ib }, PREFIX_DATA }, | |
c0f3af97 | 2833 | }, |
592a252b | 2834 | /* REG_VEX_0FAE */ |
c0f3af97 | 2835 | { |
592d1631 L |
2836 | { Bad_Opcode }, |
2837 | { Bad_Opcode }, | |
b5c37946 SJ |
2838 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) }, |
2839 | { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) }, | |
c0f3af97 | 2840 | }, |
1f506c06 | 2841 | /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */ |
260cd341 | 2842 | { |
1f506c06 | 2843 | { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) }, |
260cd341 | 2844 | }, |
14d10c6c | 2845 | /* REG_VEX_0F38F3_L_0 */ |
f12dc422 L |
2846 | { |
2847 | { Bad_Opcode }, | |
14d10c6c JB |
2848 | { "blsrS", { VexGdq, Edq }, PREFIX_OPCODE }, |
2849 | { "blsmskS", { VexGdq, Edq }, PREFIX_OPCODE }, | |
2850 | { "blsiS", { VexGdq, Edq }, PREFIX_OPCODE }, | |
f12dc422 | 2851 | }, |
32e31ad7 | 2852 | /* REG_XOP_09_01_L_0 */ |
2a2a0f38 QN |
2853 | { |
2854 | { Bad_Opcode }, | |
467bbef0 JB |
2855 | { "blcfill", { VexGdq, Edq }, 0 }, |
2856 | { "blsfill", { VexGdq, Edq }, 0 }, | |
2857 | { "blcs", { VexGdq, Edq }, 0 }, | |
2858 | { "tzmsk", { VexGdq, Edq }, 0 }, | |
2859 | { "blcic", { VexGdq, Edq }, 0 }, | |
2860 | { "blsic", { VexGdq, Edq }, 0 }, | |
2861 | { "t1mskc", { VexGdq, Edq }, 0 }, | |
2a2a0f38 | 2862 | }, |
32e31ad7 | 2863 | /* REG_XOP_09_02_L_0 */ |
2a2a0f38 QN |
2864 | { |
2865 | { Bad_Opcode }, | |
467bbef0 | 2866 | { "blcmsk", { VexGdq, Edq }, 0 }, |
2a2a0f38 QN |
2867 | { Bad_Opcode }, |
2868 | { Bad_Opcode }, | |
2869 | { Bad_Opcode }, | |
2870 | { Bad_Opcode }, | |
467bbef0 JB |
2871 | { "blci", { VexGdq, Edq }, 0 }, |
2872 | }, | |
b5c37946 | 2873 | /* REG_XOP_09_12_L_0 */ |
467bbef0 | 2874 | { |
b5c37946 SJ |
2875 | { "llwpcb", { Rdq }, 0 }, |
2876 | { "slwpcb", { Rdq }, 0 }, | |
467bbef0 | 2877 | }, |
32e31ad7 | 2878 | /* REG_XOP_0A_12_L_0 */ |
467bbef0 JB |
2879 | { |
2880 | { "lwpins", { VexGdq, Ed, Id }, 0 }, | |
2881 | { "lwpval", { VexGdq, Ed, Id }, 0 }, | |
2a2a0f38 | 2882 | }, |
ad692897 L |
2883 | |
2884 | #include "i386-dis-evex-reg.h" | |
4e7d34a6 L |
2885 | }; |
2886 | ||
1ceb70f8 L |
2887 | static const struct dis386 prefix_table[][4] = { |
2888 | /* PREFIX_90 */ | |
252b5132 | 2889 | { |
2f399d99 | 2890 | { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 }, |
bf890a93 | 2891 | { "pause", { XX }, 0 }, |
2f399d99 | 2892 | { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 }, |
507bd325 | 2893 | { NULL, { { NULL, 0 } }, PREFIX_IGNORED } |
0f10071e | 2894 | }, |
4e7d34a6 | 2895 | |
c88ed92f ZJ |
2896 | /* PREFIX_0F00_REG_6_X86_64 */ |
2897 | { | |
2898 | { Bad_Opcode }, | |
2899 | { Bad_Opcode }, | |
2900 | { Bad_Opcode }, | |
b5c37946 | 2901 | { "lkgsD", { Sv }, 0 }, |
c88ed92f ZJ |
2902 | }, |
2903 | ||
941f0833 HL |
2904 | /* PREFIX_0F01_REG_0_MOD_3_RM_6 */ |
2905 | { | |
2906 | { "wrmsrns", { Skip_MODRM }, 0 }, | |
2188d6ea HL |
2907 | { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) }, |
2908 | { Bad_Opcode }, | |
2909 | { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) }, | |
941f0833 HL |
2910 | }, |
2911 | ||
b5c37946 SJ |
2912 | /* PREFIX_0F01_REG_0_MOD_3_RM_7 */ |
2913 | { | |
2914 | { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) }, | |
2915 | }, | |
2916 | ||
c88ed92f ZJ |
2917 | /* PREFIX_0F01_REG_1_RM_2 */ |
2918 | { | |
2919 | { "clac", { Skip_MODRM }, 0 }, | |
2920 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) }, | |
2921 | { Bad_Opcode }, | |
2922 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)}, | |
2923 | }, | |
2924 | ||
81d54bb7 CL |
2925 | /* PREFIX_0F01_REG_1_RM_4 */ |
2926 | { | |
2927 | { Bad_Opcode }, | |
2928 | { Bad_Opcode }, | |
2929 | { "tdcall", { Skip_MODRM }, 0 }, | |
2930 | { Bad_Opcode }, | |
2931 | }, | |
2932 | ||
2933 | /* PREFIX_0F01_REG_1_RM_5 */ | |
2934 | { | |
2935 | { Bad_Opcode }, | |
2936 | { Bad_Opcode }, | |
2937 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) }, | |
2938 | { Bad_Opcode }, | |
2939 | }, | |
2940 | ||
2941 | /* PREFIX_0F01_REG_1_RM_6 */ | |
2942 | { | |
2943 | { Bad_Opcode }, | |
2944 | { Bad_Opcode }, | |
2945 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) }, | |
2946 | { Bad_Opcode }, | |
2947 | }, | |
2948 | ||
2949 | /* PREFIX_0F01_REG_1_RM_7 */ | |
2950 | { | |
2951 | { "encls", { Skip_MODRM }, 0 }, | |
2952 | { Bad_Opcode }, | |
2953 | { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) }, | |
2954 | { Bad_Opcode }, | |
2955 | }, | |
2956 | ||
f9630fa6 | 2957 | /* PREFIX_0F01_REG_3_RM_1 */ |
a847e322 JB |
2958 | { |
2959 | { "vmmcall", { Skip_MODRM }, 0 }, | |
2960 | { "vmgexit", { Skip_MODRM }, 0 }, | |
d27c357a JB |
2961 | { Bad_Opcode }, |
2962 | { "vmgexit", { Skip_MODRM }, 0 }, | |
a847e322 JB |
2963 | }, |
2964 | ||
f8687e93 | 2965 | /* PREFIX_0F01_REG_5_MOD_0 */ |
603555e5 L |
2966 | { |
2967 | { Bad_Opcode }, | |
2968 | { "rstorssp", { Mq }, PREFIX_OPCODE }, | |
2969 | }, | |
2970 | ||
f8687e93 | 2971 | /* PREFIX_0F01_REG_5_MOD_3_RM_0 */ |
603555e5 | 2972 | { |
4b27d27c | 2973 | { "serialize", { Skip_MODRM }, PREFIX_OPCODE }, |
2234eee6 | 2974 | { "setssbsy", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b | 2975 | { Bad_Opcode }, |
efe30057 | 2976 | { "xsusldtrk", { Skip_MODRM }, PREFIX_OPCODE }, |
bb651e8b CL |
2977 | }, |
2978 | ||
2979 | /* PREFIX_0F01_REG_5_MOD_3_RM_1 */ | |
2980 | { | |
2981 | { Bad_Opcode }, | |
2982 | { Bad_Opcode }, | |
2983 | { Bad_Opcode }, | |
2984 | { "xresldtrk", { Skip_MODRM }, PREFIX_OPCODE }, | |
603555e5 L |
2985 | }, |
2986 | ||
f8687e93 | 2987 | /* PREFIX_0F01_REG_5_MOD_3_RM_2 */ |
603555e5 L |
2988 | { |
2989 | { Bad_Opcode }, | |
c2f76402 | 2990 | { "saveprevssp", { Skip_MODRM }, PREFIX_OPCODE }, |
603555e5 L |
2991 | }, |
2992 | ||
f64c42a9 LC |
2993 | /* PREFIX_0F01_REG_5_MOD_3_RM_4 */ |
2994 | { | |
2995 | { Bad_Opcode }, | |
2996 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) }, | |
2997 | }, | |
2998 | ||
2999 | /* PREFIX_0F01_REG_5_MOD_3_RM_5 */ | |
3000 | { | |
3001 | { Bad_Opcode }, | |
3002 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) }, | |
3003 | }, | |
3004 | ||
3005 | /* PREFIX_0F01_REG_5_MOD_3_RM_6 */ | |
3006 | { | |
3007 | { "rdpkru", { Skip_MODRM }, 0 }, | |
3008 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) }, | |
3009 | }, | |
3010 | ||
3011 | /* PREFIX_0F01_REG_5_MOD_3_RM_7 */ | |
3012 | { | |
3013 | { "wrpkru", { Skip_MODRM }, 0 }, | |
3014 | { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) }, | |
3015 | }, | |
3016 | ||
267b8516 JB |
3017 | /* PREFIX_0F01_REG_7_MOD_3_RM_2 */ |
3018 | { | |
3019 | { "monitorx", { { OP_Monitor, 0 } }, 0 }, | |
142861df | 3020 | { "mcommit", { Skip_MODRM }, 0 }, |
267b8516 JB |
3021 | }, |
3022 | ||
b0e8fa7f TJ |
3023 | /* PREFIX_0F01_REG_7_MOD_3_RM_5 */ |
3024 | { | |
3025 | { "rdpru", { Skip_MODRM }, 0 }, | |
3026 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) }, | |
3027 | }, | |
3028 | ||
646cc3e0 GG |
3029 | /* PREFIX_0F01_REG_7_MOD_3_RM_6 */ |
3030 | { | |
3031 | { "invlpgb", { Skip_MODRM }, 0 }, | |
3032 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) }, | |
3033 | { Bad_Opcode }, | |
3034 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) }, | |
3035 | }, | |
3036 | ||
3037 | /* PREFIX_0F01_REG_7_MOD_3_RM_7 */ | |
3038 | { | |
3039 | { "tlbsync", { Skip_MODRM }, 0 }, | |
3040 | { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) }, | |
3041 | { Bad_Opcode }, | |
3042 | { "pvalidate", { Skip_MODRM }, 0 }, | |
3043 | }, | |
3044 | ||
3233d7d0 IT |
3045 | /* PREFIX_0F09 */ |
3046 | { | |
3047 | { "wbinvd", { XX }, 0 }, | |
3048 | { "wbnoinvd", { XX }, 0 }, | |
3049 | }, | |
3050 | ||
1ceb70f8 | 3051 | /* PREFIX_0F10 */ |
cc0ec051 | 3052 | { |
b5c37946 SJ |
3053 | { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 }, |
3054 | { "%XEVmovs%XS", { XMScalar, VexScalarR, EXd }, 0 }, | |
3055 | { "%XEVmovupX", { XM, EXEvexXNoBcst }, 0 }, | |
3056 | { "%XEVmovs%XD", { XMScalar, VexScalarR, EXq }, 0 }, | |
30d1c836 | 3057 | }, |
4e7d34a6 | 3058 | |
1ceb70f8 | 3059 | /* PREFIX_0F11 */ |
30d1c836 | 3060 | { |
b5c37946 SJ |
3061 | { "%XEVmovupX", { EXxS, XM }, 0 }, |
3062 | { "%XEVmovs%XS", { EXdS, VexScalarR, XMScalar }, 0 }, | |
3063 | { "%XEVmovupX", { EXxS, XM }, 0 }, | |
3064 | { "%XEVmovs%XD", { EXqS, VexScalarR, XMScalar }, 0 }, | |
4e7d34a6 | 3065 | }, |
252b5132 | 3066 | |
1ceb70f8 | 3067 | /* PREFIX_0F12 */ |
c608c12e | 3068 | { |
1ceb70f8 | 3069 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
b5c37946 SJ |
3070 | { "movsldup", { XM, EXx }, 0 }, |
3071 | { "%XEVmovlpYX", { XM, Vex, Mq }, 0 }, | |
3072 | { "movddup", { XM, EXq }, 0 }, | |
c608c12e | 3073 | }, |
4e7d34a6 | 3074 | |
1ceb70f8 | 3075 | /* PREFIX_0F16 */ |
c608c12e | 3076 | { |
1ceb70f8 | 3077 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
b5c37946 SJ |
3078 | { "movshdup", { XM, EXx }, 0 }, |
3079 | { "%XEVmovhpYX", { XM, Vex, Mq }, 0 }, | |
c608c12e | 3080 | }, |
4e7d34a6 | 3081 | |
ef07be45 CL |
3082 | /* PREFIX_0F18_REG_6_MOD_0_X86_64 */ |
3083 | { | |
3084 | { "prefetchit1", { { PREFETCHI_Fixup, b_mode } }, 0 }, | |
3085 | { "nopQ", { Ev }, 0 }, | |
3086 | { "nopQ", { Ev }, 0 }, | |
3087 | { "nopQ", { Ev }, 0 }, | |
3088 | }, | |
3089 | ||
3090 | /* PREFIX_0F18_REG_7_MOD_0_X86_64 */ | |
3091 | { | |
3092 | { "prefetchit0", { { PREFETCHI_Fixup, b_mode } }, 0 }, | |
3093 | { "nopQ", { Ev }, 0 }, | |
3094 | { "nopQ", { Ev }, 0 }, | |
3095 | { "nopQ", { Ev }, 0 }, | |
3096 | }, | |
3097 | ||
7e8b059b L |
3098 | /* PREFIX_0F1A */ |
3099 | { | |
3100 | { MOD_TABLE (MOD_0F1A_PREFIX_0) }, | |
bf890a93 IT |
3101 | { "bndcl", { Gbnd, Ev_bnd }, 0 }, |
3102 | { "bndmov", { Gbnd, Ebnd }, 0 }, | |
3103 | { "bndcu", { Gbnd, Ev_bnd }, 0 }, | |
7e8b059b L |
3104 | }, |
3105 | ||
3106 | /* PREFIX_0F1B */ | |
3107 | { | |
3108 | { MOD_TABLE (MOD_0F1B_PREFIX_0) }, | |
3109 | { MOD_TABLE (MOD_0F1B_PREFIX_1) }, | |
9f79e886 | 3110 | { "bndmov", { EbndS, Gbnd }, 0 }, |
bf890a93 | 3111 | { "bndcn", { Gbnd, Ev_bnd }, 0 }, |
7e8b059b L |
3112 | }, |
3113 | ||
c48935d7 IT |
3114 | /* PREFIX_0F1C */ |
3115 | { | |
3116 | { MOD_TABLE (MOD_0F1C_PREFIX_0) }, | |
31941983 JB |
3117 | { "nopQ", { Ev }, PREFIX_IGNORED }, |
3118 | { "nopQ", { Ev }, 0 }, | |
3119 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
c48935d7 IT |
3120 | }, |
3121 | ||
603555e5 L |
3122 | /* PREFIX_0F1E */ |
3123 | { | |
31941983 | 3124 | { "nopQ", { Ev }, 0 }, |
603555e5 | 3125 | { MOD_TABLE (MOD_0F1E_PREFIX_1) }, |
31941983 JB |
3126 | { "nopQ", { Ev }, 0 }, |
3127 | { NULL, { XX }, PREFIX_IGNORED }, | |
603555e5 L |
3128 | }, |
3129 | ||
1ceb70f8 | 3130 | /* PREFIX_0F2A */ |
c608c12e | 3131 | { |
507bd325 | 3132 | { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3133 | { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE }, |
507bd325 | 3134 | { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE }, |
b24d668c | 3135 | { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 }, |
c608c12e | 3136 | }, |
4e7d34a6 | 3137 | |
1ceb70f8 | 3138 | /* PREFIX_0F2B */ |
c608c12e | 3139 | { |
b5c37946 SJ |
3140 | { "movntps", { Mx, XM }, 0 }, |
3141 | { "movntss", { Md, XM }, 0 }, | |
3142 | { "movntpd", { Mx, XM }, 0 }, | |
3143 | { "movntsd", { Mq, XM }, 0 }, | |
c608c12e | 3144 | }, |
4e7d34a6 | 3145 | |
1ceb70f8 | 3146 | /* PREFIX_0F2C */ |
c608c12e | 3147 | { |
507bd325 | 3148 | { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3149 | { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3150 | { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3151 | { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3152 | }, |
4e7d34a6 | 3153 | |
1ceb70f8 | 3154 | /* PREFIX_0F2D */ |
c608c12e | 3155 | { |
507bd325 | 3156 | { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE }, |
e1a1babd | 3157 | { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE }, |
507bd325 | 3158 | { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE }, |
e1a1babd | 3159 | { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE }, |
c608c12e | 3160 | }, |
4e7d34a6 | 3161 | |
1ceb70f8 | 3162 | /* PREFIX_0F2E */ |
c608c12e | 3163 | { |
b5c37946 | 3164 | { "%XEVucomisYX", { XMScalar, EXd, EXxEVexS }, 0 }, |
592d1631 | 3165 | { Bad_Opcode }, |
b5c37946 | 3166 | { "%XEVucomisYX", { XMScalar, EXq, EXxEVexS }, 0 }, |
c608c12e | 3167 | }, |
4e7d34a6 | 3168 | |
1ceb70f8 | 3169 | /* PREFIX_0F2F */ |
c608c12e | 3170 | { |
b5c37946 | 3171 | { "%XEVcomisYX", { XMScalar, EXd, EXxEVexS }, 0 }, |
592d1631 | 3172 | { Bad_Opcode }, |
b5c37946 | 3173 | { "%XEVcomisYX", { XMScalar, EXq, EXxEVexS }, 0 }, |
c608c12e | 3174 | }, |
4e7d34a6 | 3175 | |
1ceb70f8 | 3176 | /* PREFIX_0F51 */ |
c608c12e | 3177 | { |
b5c37946 SJ |
3178 | { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 }, |
3179 | { "%XEVsqrts%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, | |
3180 | { "%XEVsqrtpX", { XM, EXx, EXxEVexR }, 0 }, | |
3181 | { "%XEVsqrts%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, | |
c608c12e | 3182 | }, |
4e7d34a6 | 3183 | |
1ceb70f8 | 3184 | /* PREFIX_0F52 */ |
c608c12e | 3185 | { |
b5c37946 SJ |
3186 | { "Vrsqrtps", { XM, EXx }, 0 }, |
3187 | { "Vrsqrtss", { XMScalar, VexScalar, EXd }, 0 }, | |
c608c12e | 3188 | }, |
4e7d34a6 | 3189 | |
1ceb70f8 | 3190 | /* PREFIX_0F53 */ |
c608c12e | 3191 | { |
b5c37946 SJ |
3192 | { "Vrcpps", { XM, EXx }, 0 }, |
3193 | { "Vrcpss", { XMScalar, VexScalar, EXd }, 0 }, | |
c608c12e | 3194 | }, |
4e7d34a6 | 3195 | |
1ceb70f8 | 3196 | /* PREFIX_0F58 */ |
c608c12e | 3197 | { |
b5c37946 SJ |
3198 | { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 }, |
3199 | { "%XEVadds%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, | |
3200 | { "%XEVaddpX", { XM, Vex, EXx, EXxEVexR }, 0 }, | |
3201 | { "%XEVadds%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, | |
c608c12e | 3202 | }, |
4e7d34a6 | 3203 | |
1ceb70f8 | 3204 | /* PREFIX_0F59 */ |
c608c12e | 3205 | { |
b5c37946 SJ |
3206 | { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 }, |
3207 | { "%XEVmuls%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, | |
3208 | { "%XEVmulpX", { XM, Vex, EXx, EXxEVexR }, 0 }, | |
3209 | { "%XEVmuls%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, | |
041bd2e0 | 3210 | }, |
4e7d34a6 | 3211 | |
1ceb70f8 | 3212 | /* PREFIX_0F5A */ |
041bd2e0 | 3213 | { |
b5c37946 SJ |
3214 | { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 }, |
3215 | { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, | |
3216 | { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 }, | |
3217 | { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, | |
041bd2e0 | 3218 | }, |
4e7d34a6 | 3219 | |
1ceb70f8 | 3220 | /* PREFIX_0F5B */ |
041bd2e0 | 3221 | { |
b5c37946 SJ |
3222 | { "Vcvtdq2ps", { XM, EXx }, 0 }, |
3223 | { "Vcvttps2dq", { XM, EXx }, 0 }, | |
3224 | { "Vcvtps2dq", { XM, EXx }, 0 }, | |
041bd2e0 | 3225 | }, |
4e7d34a6 | 3226 | |
1ceb70f8 | 3227 | /* PREFIX_0F5C */ |
041bd2e0 | 3228 | { |
b5c37946 SJ |
3229 | { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 }, |
3230 | { "%XEVsubs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, | |
3231 | { "%XEVsubpX", { XM, Vex, EXx, EXxEVexR }, 0 }, | |
3232 | { "%XEVsubs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, | |
041bd2e0 | 3233 | }, |
4e7d34a6 | 3234 | |
1ceb70f8 | 3235 | /* PREFIX_0F5D */ |
041bd2e0 | 3236 | { |
b5c37946 SJ |
3237 | { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 }, |
3238 | { "%XEVmins%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, | |
3239 | { "%XEVminpX", { XM, Vex, EXx, EXxEVexS }, 0 }, | |
3240 | { "%XEVmins%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 }, | |
041bd2e0 | 3241 | }, |
4e7d34a6 | 3242 | |
1ceb70f8 | 3243 | /* PREFIX_0F5E */ |
041bd2e0 | 3244 | { |
b5c37946 SJ |
3245 | { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 }, |
3246 | { "%XEVdivs%XS", { XMScalar, VexScalar, EXd, EXxEVexR }, 0 }, | |
3247 | { "%XEVdivpX", { XM, Vex, EXx, EXxEVexR }, 0 }, | |
3248 | { "%XEVdivs%XD", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 }, | |
041bd2e0 | 3249 | }, |
4e7d34a6 | 3250 | |
1ceb70f8 | 3251 | /* PREFIX_0F5F */ |
041bd2e0 | 3252 | { |
b5c37946 SJ |
3253 | { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 }, |
3254 | { "%XEVmaxs%XS", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 }, | |
3255 | { "%XEVmaxpX", { XM, Vex, EXx, EXxEVexS }, 0 }, | |
3256 | { "%XEVmaxs%XD", { XMScalar, VexScalar, EXq, EXxEVexS }, 0 }, | |
041bd2e0 | 3257 | }, |
4e7d34a6 | 3258 | |
1ceb70f8 | 3259 | /* PREFIX_0F60 */ |
041bd2e0 | 3260 | { |
507bd325 | 3261 | { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3262 | { Bad_Opcode }, |
507bd325 | 3263 | { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3264 | }, |
4e7d34a6 | 3265 | |
1ceb70f8 | 3266 | /* PREFIX_0F61 */ |
041bd2e0 | 3267 | { |
507bd325 | 3268 | { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3269 | { Bad_Opcode }, |
507bd325 | 3270 | { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3271 | }, |
4e7d34a6 | 3272 | |
1ceb70f8 | 3273 | /* PREFIX_0F62 */ |
041bd2e0 | 3274 | { |
507bd325 | 3275 | { "punpckldq",{ MX, EMd }, PREFIX_OPCODE }, |
592d1631 | 3276 | { Bad_Opcode }, |
507bd325 | 3277 | { "punpckldq",{ MX, EMx }, PREFIX_OPCODE }, |
041bd2e0 | 3278 | }, |
4e7d34a6 | 3279 | |
1ceb70f8 | 3280 | /* PREFIX_0F6F */ |
ca164297 | 3281 | { |
507bd325 L |
3282 | { "movq", { MX, EM }, PREFIX_OPCODE }, |
3283 | { "movdqu", { XM, EXx }, PREFIX_OPCODE }, | |
3284 | { "movdqa", { XM, EXx }, PREFIX_OPCODE }, | |
ca164297 | 3285 | }, |
4e7d34a6 | 3286 | |
1ceb70f8 | 3287 | /* PREFIX_0F70 */ |
4e7d34a6 | 3288 | { |
507bd325 L |
3289 | { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE }, |
3290 | { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
3291 | { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE }, | |
3292 | { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE }, | |
4e7d34a6 L |
3293 | }, |
3294 | ||
1ceb70f8 | 3295 | /* PREFIX_0F78 */ |
4e7d34a6 | 3296 | { |
bf890a93 | 3297 | {"vmread", { Em, Gm }, 0 }, |
592d1631 | 3298 | { Bad_Opcode }, |
b5c37946 SJ |
3299 | {"extrq", { Uxmm, Ib, Ib }, 0 }, |
3300 | {"insertq", { XM, Uxmm, Ib, Ib }, 0 }, | |
4e7d34a6 L |
3301 | }, |
3302 | ||
1ceb70f8 | 3303 | /* PREFIX_0F79 */ |
4e7d34a6 | 3304 | { |
bf890a93 | 3305 | {"vmwrite", { Gm, Em }, 0 }, |
592d1631 | 3306 | { Bad_Opcode }, |
b5c37946 SJ |
3307 | {"extrq", { XM, Uxmm }, 0 }, |
3308 | {"insertq", { XM, Uxmm }, 0 }, | |
4e7d34a6 L |
3309 | }, |
3310 | ||
1ceb70f8 | 3311 | /* PREFIX_0F7C */ |
ca164297 | 3312 | { |
592d1631 L |
3313 | { Bad_Opcode }, |
3314 | { Bad_Opcode }, | |
b5c37946 SJ |
3315 | { "Vhaddpd", { XM, Vex, EXx }, 0 }, |
3316 | { "Vhaddps", { XM, Vex, EXx }, 0 }, | |
ca164297 | 3317 | }, |
4e7d34a6 | 3318 | |
1ceb70f8 | 3319 | /* PREFIX_0F7D */ |
ca164297 | 3320 | { |
592d1631 L |
3321 | { Bad_Opcode }, |
3322 | { Bad_Opcode }, | |
b5c37946 SJ |
3323 | { "Vhsubpd", { XM, Vex, EXx }, 0 }, |
3324 | { "Vhsubps", { XM, Vex, EXx }, 0 }, | |
ca164297 | 3325 | }, |
4e7d34a6 | 3326 | |
1ceb70f8 | 3327 | /* PREFIX_0F7E */ |
ca164297 | 3328 | { |
507bd325 L |
3329 | { "movK", { Edq, MX }, PREFIX_OPCODE }, |
3330 | { "movq", { XM, EXq }, PREFIX_OPCODE }, | |
3331 | { "movK", { Edq, XM }, PREFIX_OPCODE }, | |
ca164297 | 3332 | }, |
4e7d34a6 | 3333 | |
1ceb70f8 | 3334 | /* PREFIX_0F7F */ |
ca164297 | 3335 | { |
507bd325 L |
3336 | { "movq", { EMS, MX }, PREFIX_OPCODE }, |
3337 | { "movdqu", { EXxS, XM }, PREFIX_OPCODE }, | |
3338 | { "movdqa", { EXxS, XM }, PREFIX_OPCODE }, | |
ca164297 | 3339 | }, |
4e7d34a6 | 3340 | |
f8687e93 | 3341 | /* PREFIX_0FAE_REG_0_MOD_3 */ |
c7b8aa3a L |
3342 | { |
3343 | { Bad_Opcode }, | |
bf890a93 | 3344 | { "rdfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3345 | }, |
3346 | ||
f8687e93 | 3347 | /* PREFIX_0FAE_REG_1_MOD_3 */ |
c7b8aa3a L |
3348 | { |
3349 | { Bad_Opcode }, | |
bf890a93 | 3350 | { "rdgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3351 | }, |
3352 | ||
f8687e93 | 3353 | /* PREFIX_0FAE_REG_2_MOD_3 */ |
c7b8aa3a L |
3354 | { |
3355 | { Bad_Opcode }, | |
bf890a93 | 3356 | { "wrfsbase", { Ev }, 0 }, |
c7b8aa3a L |
3357 | }, |
3358 | ||
f8687e93 | 3359 | /* PREFIX_0FAE_REG_3_MOD_3 */ |
c7b8aa3a L |
3360 | { |
3361 | { Bad_Opcode }, | |
bf890a93 | 3362 | { "wrgsbase", { Ev }, 0 }, |
c7b8aa3a L |
3363 | }, |
3364 | ||
f8687e93 | 3365 | /* PREFIX_0FAE_REG_4_MOD_0 */ |
6b40c462 L |
3366 | { |
3367 | { "xsave", { FXSAVE }, 0 }, | |
b24d668c | 3368 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3369 | }, |
3370 | ||
f8687e93 | 3371 | /* PREFIX_0FAE_REG_4_MOD_3 */ |
6b40c462 L |
3372 | { |
3373 | { Bad_Opcode }, | |
b24d668c | 3374 | { "ptwrite{%LQ|}", { Edq }, 0 }, |
6b40c462 L |
3375 | }, |
3376 | ||
f8687e93 | 3377 | /* PREFIX_0FAE_REG_5_MOD_3 */ |
2234eee6 L |
3378 | { |
3379 | { "lfence", { Skip_MODRM }, 0 }, | |
464d2b65 | 3380 | { "incsspK", { Edq }, PREFIX_OPCODE }, |
603555e5 L |
3381 | }, |
3382 | ||
f8687e93 | 3383 | /* PREFIX_0FAE_REG_6_MOD_0 */ |
c5e7287a | 3384 | { |
603555e5 L |
3385 | { "xsaveopt", { FXSAVE }, PREFIX_OPCODE }, |
3386 | { "clrssbsy", { Mq }, PREFIX_OPCODE }, | |
3387 | { "clwb", { Mb }, PREFIX_OPCODE }, | |
c5e7287a IT |
3388 | }, |
3389 | ||
f8687e93 | 3390 | /* PREFIX_0FAE_REG_6_MOD_3 */ |
de89d0a3 | 3391 | { |
f8687e93 | 3392 | { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) }, |
de89d0a3 | 3393 | { "umonitor", { Eva }, PREFIX_OPCODE }, |
ae1d3843 L |
3394 | { "tpause", { Edq }, PREFIX_OPCODE }, |
3395 | { "umwait", { Edq }, PREFIX_OPCODE }, | |
de89d0a3 IT |
3396 | }, |
3397 | ||
f8687e93 | 3398 | /* PREFIX_0FAE_REG_7_MOD_0 */ |
963f3586 | 3399 | { |
bf890a93 | 3400 | { "clflush", { Mb }, 0 }, |
963f3586 | 3401 | { Bad_Opcode }, |
bf890a93 | 3402 | { "clflushopt", { Mb }, 0 }, |
963f3586 IT |
3403 | }, |
3404 | ||
1ceb70f8 | 3405 | /* PREFIX_0FB8 */ |
ca164297 | 3406 | { |
592d1631 | 3407 | { Bad_Opcode }, |
bf890a93 | 3408 | { "popcntS", { Gv, Ev }, 0 }, |
ca164297 | 3409 | }, |
4e7d34a6 | 3410 | |
f12dc422 L |
3411 | /* PREFIX_0FBC */ |
3412 | { | |
bf890a93 IT |
3413 | { "bsfS", { Gv, Ev }, 0 }, |
3414 | { "tzcntS", { Gv, Ev }, 0 }, | |
3415 | { "bsfS", { Gv, Ev }, 0 }, | |
f12dc422 L |
3416 | }, |
3417 | ||
1ceb70f8 | 3418 | /* PREFIX_0FBD */ |
050dfa73 | 3419 | { |
bf890a93 IT |
3420 | { "bsrS", { Gv, Ev }, 0 }, |
3421 | { "lzcntS", { Gv, Ev }, 0 }, | |
3422 | { "bsrS", { Gv, Ev }, 0 }, | |
050dfa73 MM |
3423 | }, |
3424 | ||
1ceb70f8 | 3425 | /* PREFIX_0FC2 */ |
050dfa73 | 3426 | { |
b5c37946 SJ |
3427 | { "VcmppX", { XM, Vex, EXx, CMP }, 0 }, |
3428 | { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 }, | |
3429 | { "VcmppX", { XM, Vex, EXx, CMP }, 0 }, | |
3430 | { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 }, | |
050dfa73 | 3431 | }, |
246c51aa | 3432 | |
f8687e93 | 3433 | /* PREFIX_0FC7_REG_6_MOD_0 */ |
92fddf8e | 3434 | { |
bf890a93 IT |
3435 | { "vmptrld",{ Mq }, 0 }, |
3436 | { "vmxon", { Mq }, 0 }, | |
3437 | { "vmclear",{ Mq }, 0 }, | |
92fddf8e L |
3438 | }, |
3439 | ||
f8687e93 | 3440 | /* PREFIX_0FC7_REG_6_MOD_3 */ |
f24bcbaa L |
3441 | { |
3442 | { "rdrand", { Ev }, 0 }, | |
f64c42a9 | 3443 | { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) }, |
f24bcbaa L |
3444 | { "rdrand", { Ev }, 0 } |
3445 | }, | |
3446 | ||
f8687e93 | 3447 | /* PREFIX_0FC7_REG_7_MOD_3 */ |
f24bcbaa L |
3448 | { |
3449 | { "rdseed", { Ev }, 0 }, | |
8bc52696 | 3450 | { "rdpid", { Em }, 0 }, |
f24bcbaa L |
3451 | { "rdseed", { Ev }, 0 }, |
3452 | }, | |
3453 | ||
1ceb70f8 | 3454 | /* PREFIX_0FD0 */ |
050dfa73 | 3455 | { |
592d1631 L |
3456 | { Bad_Opcode }, |
3457 | { Bad_Opcode }, | |
b5c37946 SJ |
3458 | { "VaddsubpX", { XM, Vex, EXx }, 0 }, |
3459 | { "VaddsubpX", { XM, Vex, EXx }, 0 }, | |
246c51aa | 3460 | }, |
050dfa73 | 3461 | |
1ceb70f8 | 3462 | /* PREFIX_0FD6 */ |
050dfa73 | 3463 | { |
592d1631 | 3464 | { Bad_Opcode }, |
b5c37946 | 3465 | { "movq2dq",{ XM, Nq }, 0 }, |
bf890a93 | 3466 | { "movq", { EXqS, XM }, 0 }, |
b5c37946 | 3467 | { "movdq2q",{ MX, Ux }, 0 }, |
050dfa73 MM |
3468 | }, |
3469 | ||
1ceb70f8 | 3470 | /* PREFIX_0FE6 */ |
7918206c | 3471 | { |
592d1631 | 3472 | { Bad_Opcode }, |
b5c37946 SJ |
3473 | { "Vcvtdq2pd", { XM, EXxmmq }, 0 }, |
3474 | { "Vcvttpd2dq%XY", { XMM, EXx }, 0 }, | |
3475 | { "Vcvtpd2dq%XY", { XMM, EXx }, 0 }, | |
7918206c | 3476 | }, |
8b38ad71 | 3477 | |
1ceb70f8 | 3478 | /* PREFIX_0FE7 */ |
8b38ad71 | 3479 | { |
b5c37946 | 3480 | { "movntq", { Mq, MX }, 0 }, |
592d1631 | 3481 | { Bad_Opcode }, |
b5c37946 | 3482 | { "movntdq", { Mx, XM }, 0 }, |
4e7d34a6 L |
3483 | }, |
3484 | ||
1ceb70f8 | 3485 | /* PREFIX_0FF0 */ |
4e7d34a6 | 3486 | { |
592d1631 L |
3487 | { Bad_Opcode }, |
3488 | { Bad_Opcode }, | |
3489 | { Bad_Opcode }, | |
b5c37946 | 3490 | { "Vlddqu", { XM, M }, 0 }, |
4e7d34a6 L |
3491 | }, |
3492 | ||
1ceb70f8 | 3493 | /* PREFIX_0FF7 */ |
4e7d34a6 | 3494 | { |
b5c37946 | 3495 | { "maskmovq", { MX, Nq }, PREFIX_OPCODE }, |
592d1631 | 3496 | { Bad_Opcode }, |
b5c37946 | 3497 | { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE }, |
8b38ad71 | 3498 | }, |
42903f7f | 3499 | |
c4694f17 TG |
3500 | /* PREFIX_0F38D8 */ |
3501 | { | |
3502 | { Bad_Opcode }, | |
3503 | { REG_TABLE (REG_0F38D8_PREFIX_1) }, | |
3504 | }, | |
3505 | ||
3506 | /* PREFIX_0F38DC */ | |
3507 | { | |
3508 | { Bad_Opcode }, | |
3509 | { MOD_TABLE (MOD_0F38DC_PREFIX_1) }, | |
3510 | { "aesenc", { XM, EXx }, 0 }, | |
3511 | }, | |
3512 | ||
3513 | /* PREFIX_0F38DD */ | |
3514 | { | |
3515 | { Bad_Opcode }, | |
b5c37946 | 3516 | { "aesdec128kl", { XM, M }, 0 }, |
c4694f17 TG |
3517 | { "aesenclast", { XM, EXx }, 0 }, |
3518 | }, | |
3519 | ||
3520 | /* PREFIX_0F38DE */ | |
3521 | { | |
3522 | { Bad_Opcode }, | |
b5c37946 | 3523 | { "aesenc256kl", { XM, M }, 0 }, |
c4694f17 TG |
3524 | { "aesdec", { XM, EXx }, 0 }, |
3525 | }, | |
3526 | ||
3527 | /* PREFIX_0F38DF */ | |
3528 | { | |
3529 | { Bad_Opcode }, | |
b5c37946 | 3530 | { "aesdec256kl", { XM, M }, 0 }, |
c4694f17 TG |
3531 | { "aesdeclast", { XM, EXx }, 0 }, |
3532 | }, | |
3533 | ||
1ceb70f8 | 3534 | /* PREFIX_0F38F0 */ |
4e7d34a6 | 3535 | { |
9ab00b61 | 3536 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
592d1631 | 3537 | { Bad_Opcode }, |
9ab00b61 | 3538 | { "movbeS", { Gv, Mv }, PREFIX_OPCODE }, |
2875b28a | 3539 | { "crc32A", { Gdq, Eb }, PREFIX_OPCODE }, |
4e7d34a6 L |
3540 | }, |
3541 | ||
1ceb70f8 | 3542 | /* PREFIX_0F38F1 */ |
4e7d34a6 | 3543 | { |
9ab00b61 | 3544 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
592d1631 | 3545 | { Bad_Opcode }, |
9ab00b61 | 3546 | { "movbeS", { Mv, Gv }, PREFIX_OPCODE }, |
2875b28a | 3547 | { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE }, |
4e7d34a6 L |
3548 | }, |
3549 | ||
603555e5 L |
3550 | /* PREFIX_0F38F6 */ |
3551 | { | |
b5c37946 SJ |
3552 | { "wrssK", { M, Gdq }, 0 }, |
3553 | { "adoxS", { Gdq, Edq}, 0 }, | |
3554 | { "adcxS", { Gdq, Edq}, 0 }, | |
e2e1fcde L |
3555 | { Bad_Opcode }, |
3556 | }, | |
3557 | ||
c0a30a9f L |
3558 | /* PREFIX_0F38F8 */ |
3559 | { | |
3560 | { Bad_Opcode }, | |
b5c37946 SJ |
3561 | { "enqcmds", { Gva, M }, 0 }, |
3562 | { "movdir64b", { Gva, M }, 0 }, | |
3563 | { "enqcmd", { Gva, M }, 0 }, | |
c0a30a9f | 3564 | }, |
c4694f17 TG |
3565 | /* PREFIX_0F38FA */ |
3566 | { | |
3567 | { Bad_Opcode }, | |
b5c37946 | 3568 | { "encodekey128", { Gd, Rd }, 0 }, |
c4694f17 TG |
3569 | }, |
3570 | ||
3571 | /* PREFIX_0F38FB */ | |
3572 | { | |
3573 | { Bad_Opcode }, | |
b5c37946 | 3574 | { "encodekey256", { Gd, Rd }, 0 }, |
c4694f17 | 3575 | }, |
c0a30a9f | 3576 | |
b06311ad KL |
3577 | /* PREFIX_0F38FC */ |
3578 | { | |
3579 | { "aadd", { Mdq, Gdq }, 0 }, | |
3580 | { "axor", { Mdq, Gdq }, 0 }, | |
3581 | { "aand", { Mdq, Gdq }, 0 }, | |
3582 | { "aor", { Mdq, Gdq }, 0 }, | |
3583 | }, | |
3584 | ||
c1fa250a LC |
3585 | /* PREFIX_0F3A0F */ |
3586 | { | |
3587 | { Bad_Opcode }, | |
b5c37946 | 3588 | { REG_TABLE (REG_0F3A0F_P_1) }, |
c1fa250a LC |
3589 | }, |
3590 | ||
7531c613 | 3591 | /* PREFIX_VEX_0F12 */ |
42903f7f | 3592 | { |
b5c37946 | 3593 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) }, |
f7cfcddd | 3594 | { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 }, |
b5c37946 | 3595 | { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) }, |
f7cfcddd | 3596 | { "%XEvmov%XDdup", { XM, EXymmq }, 0 }, |
42903f7f L |
3597 | }, |
3598 | ||
7531c613 | 3599 | /* PREFIX_VEX_0F16 */ |
42903f7f | 3600 | { |
b5c37946 | 3601 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) }, |
f7cfcddd | 3602 | { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 }, |
b5c37946 | 3603 | { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) }, |
5f754f58 | 3604 | }, |
7c52e0e8 | 3605 | |
592a252b | 3606 | /* PREFIX_VEX_0F2A */ |
5f754f58 | 3607 | { |
592d1631 | 3608 | { Bad_Opcode }, |
b5c37946 | 3609 | { "%XEvcvtsi2ssY{%LQ|}", { XMScalar, VexScalar, EXxEVexR, Edq }, 0 }, |
592d1631 | 3610 | { Bad_Opcode }, |
b5c37946 | 3611 | { "%XEvcvtsi2sdY{%LQ|}", { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 }, |
5f754f58 | 3612 | }, |
7c52e0e8 | 3613 | |
592a252b | 3614 | /* PREFIX_VEX_0F2C */ |
5f754f58 | 3615 | { |
592d1631 | 3616 | { Bad_Opcode }, |
f7cfcddd | 3617 | { "%XEvcvttss2si", { Gdq, EXd, EXxEVexS }, 0 }, |
592d1631 | 3618 | { Bad_Opcode }, |
f7cfcddd | 3619 | { "%XEvcvttsd2si", { Gdq, EXq, EXxEVexS }, 0 }, |
5f754f58 | 3620 | }, |
7c52e0e8 | 3621 | |
592a252b | 3622 | /* PREFIX_VEX_0F2D */ |
7c52e0e8 | 3623 | { |
592d1631 | 3624 | { Bad_Opcode }, |
f7cfcddd | 3625 | { "%XEvcvtss2si", { Gdq, EXd, EXxEVexR }, 0 }, |
592d1631 | 3626 | { Bad_Opcode }, |
f7cfcddd | 3627 | { "%XEvcvtsd2si", { Gdq, EXq, EXxEVexR }, 0 }, |
7c52e0e8 L |
3628 | }, |
3629 | ||
b5c37946 | 3630 | /* PREFIX_VEX_0F41_L_1_W_0 */ |
43234a1e | 3631 | { |
b5c37946 | 3632 | { "kandw", { MaskG, MaskVex, MaskR }, 0 }, |
1ba585e8 | 3633 | { Bad_Opcode }, |
b5c37946 | 3634 | { "kandb", { MaskG, MaskVex, MaskR }, 0 }, |
43234a1e L |
3635 | }, |
3636 | ||
b5c37946 | 3637 | /* PREFIX_VEX_0F41_L_1_W_1 */ |
43234a1e | 3638 | { |
b5c37946 | 3639 | { "kandq", { MaskG, MaskVex, MaskR }, 0 }, |
1ba585e8 | 3640 | { Bad_Opcode }, |
b5c37946 | 3641 | { "kandd", { MaskG, MaskVex, MaskR }, 0 }, |
43234a1e L |
3642 | }, |
3643 | ||
b5c37946 | 3644 | /* PREFIX_VEX_0F42_L_1_W_0 */ |
c0f3af97 | 3645 | { |
b5c37946 | 3646 | { "kandnw", { MaskG, MaskVex, MaskR }, 0 }, |
592d1631 | 3647 | { Bad_Opcode }, |
b5c37946 | 3648 | { "kandnb", { MaskG, MaskVex, MaskR }, 0 }, |
c0f3af97 L |
3649 | }, |
3650 | ||
b5c37946 | 3651 | /* PREFIX_VEX_0F42_L_1_W_1 */ |
0bfee649 | 3652 | { |
b5c37946 | 3653 | { "kandnq", { MaskG, MaskVex, MaskR }, 0 }, |
592d1631 | 3654 | { Bad_Opcode }, |
b5c37946 | 3655 | { "kandnd", { MaskG, MaskVex, MaskR }, 0 }, |
0bfee649 L |
3656 | }, |
3657 | ||
b5c37946 | 3658 | /* PREFIX_VEX_0F44_L_0_W_0 */ |
43234a1e | 3659 | { |
b5c37946 | 3660 | { "knotw", { MaskG, MaskR }, 0 }, |
43234a1e | 3661 | { Bad_Opcode }, |
b5c37946 | 3662 | { "knotb", { MaskG, MaskR }, 0 }, |
43234a1e L |
3663 | }, |
3664 | ||
b5c37946 | 3665 | /* PREFIX_VEX_0F44_L_0_W_1 */ |
1ba585e8 | 3666 | { |
b5c37946 | 3667 | { "knotq", { MaskG, MaskR }, 0 }, |
1ba585e8 | 3668 | { Bad_Opcode }, |
b5c37946 | 3669 | { "knotd", { MaskG, MaskR }, 0 }, |
1ba585e8 IT |
3670 | }, |
3671 | ||
b5c37946 | 3672 | /* PREFIX_VEX_0F45_L_1_W_0 */ |
43234a1e | 3673 | { |
b5c37946 | 3674 | { "korw", { MaskG, MaskVex, MaskR }, 0 }, |
43234a1e | 3675 | { Bad_Opcode }, |
b5c37946 | 3676 | { "korb", { MaskG, MaskVex, MaskR }, 0 }, |
43234a1e L |
3677 | }, |
3678 | ||
b5c37946 | 3679 | /* PREFIX_VEX_0F45_L_1_W_1 */ |
1ba585e8 | 3680 | { |
b5c37946 | 3681 | { "korq", { MaskG, MaskVex, MaskR }, 0 }, |
1ba585e8 | 3682 | { Bad_Opcode }, |
b5c37946 | 3683 | { "kord", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3684 | }, |
3685 | ||
b5c37946 | 3686 | /* PREFIX_VEX_0F46_L_1_W_0 */ |
13954a31 | 3687 | { |
b5c37946 | 3688 | { "kxnorw", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3689 | { Bad_Opcode }, |
b5c37946 | 3690 | { "kxnorb", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3691 | }, |
3692 | ||
b5c37946 | 3693 | /* PREFIX_VEX_0F46_L_1_W_1 */ |
13954a31 | 3694 | { |
b5c37946 | 3695 | { "kxnorq", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3696 | { Bad_Opcode }, |
b5c37946 | 3697 | { "kxnord", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3698 | }, |
3699 | ||
b5c37946 | 3700 | /* PREFIX_VEX_0F47_L_1_W_0 */ |
13954a31 | 3701 | { |
b5c37946 | 3702 | { "kxorw", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3703 | { Bad_Opcode }, |
b5c37946 | 3704 | { "kxorb", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3705 | }, |
3706 | ||
b5c37946 | 3707 | /* PREFIX_VEX_0F47_L_1_W_1 */ |
13954a31 | 3708 | { |
b5c37946 | 3709 | { "kxorq", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3710 | { Bad_Opcode }, |
b5c37946 | 3711 | { "kxord", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3712 | }, |
3713 | ||
b5c37946 | 3714 | /* PREFIX_VEX_0F4A_L_1_W_0 */ |
13954a31 | 3715 | { |
b5c37946 | 3716 | { "kaddw", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3717 | { Bad_Opcode }, |
b5c37946 | 3718 | { "kaddb", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3719 | }, |
3720 | ||
b5c37946 | 3721 | /* PREFIX_VEX_0F4A_L_1_W_1 */ |
13954a31 | 3722 | { |
b5c37946 | 3723 | { "kaddq", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3724 | { Bad_Opcode }, |
b5c37946 | 3725 | { "kaddd", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3726 | }, |
3727 | ||
b5c37946 | 3728 | /* PREFIX_VEX_0F4B_L_1_W_0 */ |
13954a31 | 3729 | { |
b5c37946 | 3730 | { "kunpckwd", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 | 3731 | { Bad_Opcode }, |
b5c37946 | 3732 | { "kunpckbw", { MaskG, MaskVex, MaskR }, 0 }, |
13954a31 JB |
3733 | }, |
3734 | ||
b5c37946 | 3735 | /* PREFIX_VEX_0F4B_L_1_W_1 */ |
13954a31 | 3736 | { |
b5c37946 | 3737 | { "kunpckdq", { MaskG, MaskVex, MaskR }, 0 }, |
1ba585e8 IT |
3738 | }, |
3739 | ||
7531c613 | 3740 | /* PREFIX_VEX_0F6F */ |
c0f3af97 | 3741 | { |
592d1631 | 3742 | { Bad_Opcode }, |
7531c613 JB |
3743 | { "vmovdqu", { XM, EXx }, 0 }, |
3744 | { "vmovdqa", { XM, EXx }, 0 }, | |
c0f3af97 L |
3745 | }, |
3746 | ||
7531c613 | 3747 | /* PREFIX_VEX_0F70 */ |
922d8de8 | 3748 | { |
592d1631 | 3749 | { Bad_Opcode }, |
7531c613 JB |
3750 | { "vpshufhw", { XM, EXx, Ib }, 0 }, |
3751 | { "vpshufd", { XM, EXx, Ib }, 0 }, | |
3752 | { "vpshuflw", { XM, EXx, Ib }, 0 }, | |
922d8de8 DR |
3753 | }, |
3754 | ||
7531c613 | 3755 | /* PREFIX_VEX_0F7E */ |
c0f3af97 | 3756 | { |
592d1631 | 3757 | { Bad_Opcode }, |
7531c613 JB |
3758 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) }, |
3759 | { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) }, | |
c0f3af97 L |
3760 | }, |
3761 | ||
7531c613 | 3762 | /* PREFIX_VEX_0F7F */ |
c0f3af97 | 3763 | { |
592d1631 | 3764 | { Bad_Opcode }, |
7531c613 JB |
3765 | { "vmovdqu", { EXxS, XM }, 0 }, |
3766 | { "vmovdqa", { EXxS, XM }, 0 }, | |
c0f3af97 L |
3767 | }, |
3768 | ||
13954a31 JB |
3769 | /* PREFIX_VEX_0F90_L_0_W_0 */ |
3770 | { | |
3771 | { "kmovw", { MaskG, MaskE }, 0 }, | |
3772 | { Bad_Opcode }, | |
3773 | { "kmovb", { MaskG, MaskBDE }, 0 }, | |
3774 | }, | |
3775 | ||
3776 | /* PREFIX_VEX_0F90_L_0_W_1 */ | |
3777 | { | |
3778 | { "kmovq", { MaskG, MaskE }, 0 }, | |
3779 | { Bad_Opcode }, | |
3780 | { "kmovd", { MaskG, MaskBDE }, 0 }, | |
3781 | }, | |
3782 | ||
b5c37946 | 3783 | /* PREFIX_VEX_0F91_L_0_W_0 */ |
13954a31 | 3784 | { |
b5c37946 | 3785 | { "kmovw", { Mw, MaskG }, 0 }, |
13954a31 | 3786 | { Bad_Opcode }, |
b5c37946 | 3787 | { "kmovb", { Mb, MaskG }, 0 }, |
13954a31 JB |
3788 | }, |
3789 | ||
b5c37946 | 3790 | /* PREFIX_VEX_0F91_L_0_W_1 */ |
13954a31 | 3791 | { |
b5c37946 | 3792 | { "kmovq", { Mq, MaskG }, 0 }, |
13954a31 | 3793 | { Bad_Opcode }, |
b5c37946 | 3794 | { "kmovd", { Md, MaskG }, 0 }, |
13954a31 JB |
3795 | }, |
3796 | ||
b5c37946 | 3797 | /* PREFIX_VEX_0F92_L_0_W_0 */ |
13954a31 | 3798 | { |
b5c37946 | 3799 | { "kmovw", { MaskG, Rdq }, 0 }, |
13954a31 | 3800 | { Bad_Opcode }, |
b5c37946 SJ |
3801 | { "kmovb", { MaskG, Rdq }, 0 }, |
3802 | { "kmovd", { MaskG, Rdq }, 0 }, | |
13954a31 JB |
3803 | }, |
3804 | ||
b5c37946 | 3805 | /* PREFIX_VEX_0F92_L_0_W_1 */ |
c0f3af97 | 3806 | { |
592d1631 | 3807 | { Bad_Opcode }, |
13954a31 JB |
3808 | { Bad_Opcode }, |
3809 | { Bad_Opcode }, | |
b5c37946 | 3810 | { "kmovK", { MaskG, Rdq }, 0 }, |
c0f3af97 L |
3811 | }, |
3812 | ||
b5c37946 | 3813 | /* PREFIX_VEX_0F93_L_0_W_0 */ |
c0f3af97 | 3814 | { |
b5c37946 | 3815 | { "kmovw", { Gdq, MaskR }, 0 }, |
592d1631 | 3816 | { Bad_Opcode }, |
b5c37946 SJ |
3817 | { "kmovb", { Gdq, MaskR }, 0 }, |
3818 | { "kmovd", { Gdq, MaskR }, 0 }, | |
c0f3af97 | 3819 | }, |
a5ff0eb2 | 3820 | |
b5c37946 | 3821 | /* PREFIX_VEX_0F93_L_0_W_1 */ |
922d8de8 | 3822 | { |
592d1631 | 3823 | { Bad_Opcode }, |
13954a31 JB |
3824 | { Bad_Opcode }, |
3825 | { Bad_Opcode }, | |
b5c37946 | 3826 | { "kmovK", { Gdq, MaskR }, 0 }, |
922d8de8 DR |
3827 | }, |
3828 | ||
b5c37946 | 3829 | /* PREFIX_VEX_0F98_L_0_W_0 */ |
922d8de8 | 3830 | { |
b5c37946 | 3831 | { "kortestw", { MaskG, MaskR }, 0 }, |
592d1631 | 3832 | { Bad_Opcode }, |
b5c37946 | 3833 | { "kortestb", { MaskG, MaskR }, 0 }, |
922d8de8 DR |
3834 | }, |
3835 | ||
b5c37946 | 3836 | /* PREFIX_VEX_0F98_L_0_W_1 */ |
922d8de8 | 3837 | { |
b5c37946 | 3838 | { "kortestq", { MaskG, MaskR }, 0 }, |
592d1631 | 3839 | { Bad_Opcode }, |
b5c37946 | 3840 | { "kortestd", { MaskG, MaskR }, 0 }, |
922d8de8 DR |
3841 | }, |
3842 | ||
b5c37946 | 3843 | /* PREFIX_VEX_0F99_L_0_W_0 */ |
922d8de8 | 3844 | { |
b5c37946 | 3845 | { "ktestw", { MaskG, MaskR }, 0 }, |
592d1631 | 3846 | { Bad_Opcode }, |
b5c37946 | 3847 | { "ktestb", { MaskG, MaskR }, 0 }, |
13954a31 JB |
3848 | }, |
3849 | ||
b5c37946 | 3850 | /* PREFIX_VEX_0F99_L_0_W_1 */ |
13954a31 | 3851 | { |
b5c37946 | 3852 | { "ktestq", { MaskG, MaskR }, 0 }, |
13954a31 | 3853 | { Bad_Opcode }, |
b5c37946 | 3854 | { "ktestd", { MaskG, MaskR }, 0 }, |
922d8de8 DR |
3855 | }, |
3856 | ||
1f506c06 | 3857 | /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */ |
922d8de8 | 3858 | { |
1f506c06 | 3859 | { "ldtilecfg", { M }, 0 }, |
592d1631 | 3860 | { Bad_Opcode }, |
1f506c06 | 3861 | { "sttilecfg", { M }, 0 }, |
922d8de8 DR |
3862 | }, |
3863 | ||
1f506c06 | 3864 | /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */ |
922d8de8 | 3865 | { |
1f506c06 JB |
3866 | { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) }, |
3867 | { Bad_Opcode }, | |
592d1631 | 3868 | { Bad_Opcode }, |
1f506c06 JB |
3869 | { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) }, |
3870 | }, | |
3871 | ||
b5c37946 | 3872 | /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */ |
1f506c06 JB |
3873 | { |
3874 | { Bad_Opcode }, | |
3875 | { "tilestored", { MVexSIBMEM, TMM }, 0 }, | |
3876 | { "tileloaddt1", { TMM, MVexSIBMEM }, 0 }, | |
3877 | { "tileloadd", { TMM, MVexSIBMEM }, 0 }, | |
922d8de8 DR |
3878 | }, |
3879 | ||
23ae61ad CL |
3880 | /* PREFIX_VEX_0F3850_W_0 */ |
3881 | { | |
3882 | { "vpdpbuud", { XM, Vex, EXx }, 0 }, | |
3883 | { "vpdpbsud", { XM, Vex, EXx }, 0 }, | |
3884 | { "%XVvpdpbusd", { XM, Vex, EXx }, 0 }, | |
3885 | { "vpdpbssd", { XM, Vex, EXx }, 0 }, | |
3886 | }, | |
3887 | ||
3888 | /* PREFIX_VEX_0F3851_W_0 */ | |
3889 | { | |
3890 | { "vpdpbuuds", { XM, Vex, EXx }, 0 }, | |
3891 | { "vpdpbsuds", { XM, Vex, EXx }, 0 }, | |
3892 | { "%XVvpdpbusds", { XM, Vex, EXx }, 0 }, | |
3893 | { "vpdpbssds", { XM, Vex, EXx }, 0 }, | |
3894 | }, | |
b5c37946 | 3895 | /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */ |
922d8de8 | 3896 | { |
592d1631 | 3897 | { Bad_Opcode }, |
b5c37946 | 3898 | { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 }, |
592d1631 | 3899 | { Bad_Opcode }, |
b5c37946 | 3900 | { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 }, |
922d8de8 DR |
3901 | }, |
3902 | ||
b5c37946 | 3903 | /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */ |
922d8de8 | 3904 | { |
b5c37946 SJ |
3905 | { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 }, |
3906 | { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 }, | |
3907 | { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 }, | |
3908 | { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 }, | |
922d8de8 DR |
3909 | }, |
3910 | ||
b5c37946 | 3911 | /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */ |
d100d8c1 | 3912 | { |
b5c37946 | 3913 | { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 }, |
d100d8c1 | 3914 | { Bad_Opcode }, |
b5c37946 | 3915 | { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 }, |
d100d8c1 HJ |
3916 | }, |
3917 | ||
01d8ce74 | 3918 | /* PREFIX_VEX_0F3872 */ |
3919 | { | |
3920 | { Bad_Opcode }, | |
3921 | { VEX_W_TABLE (VEX_W_0F3872_P_1) }, | |
3922 | }, | |
3923 | ||
3924 | /* PREFIX_VEX_0F38B0_W_0 */ | |
3925 | { | |
3926 | { "vcvtneoph2ps", { XM, Mx }, 0 }, | |
3927 | { "vcvtneebf162ps", { XM, Mx }, 0 }, | |
3928 | { "vcvtneeph2ps", { XM, Mx }, 0 }, | |
3929 | { "vcvtneobf162ps", { XM, Mx }, 0 }, | |
3930 | }, | |
3931 | ||
3932 | /* PREFIX_VEX_0F38B1_W_0 */ | |
3933 | { | |
3934 | { Bad_Opcode }, | |
3935 | { "vbcstnebf162ps", { XM, Mw }, 0 }, | |
3936 | { "vbcstnesh2ps", { XM, Mw }, 0 }, | |
3937 | }, | |
3938 | ||
b5c37946 SJ |
3939 | /* PREFIX_VEX_0F38D2_W_0 */ |
3940 | { | |
3941 | { "vpdpwuud", { XM, Vex, EXx }, 0 }, | |
3942 | { "vpdpwsud", { XM, Vex, EXx }, 0 }, | |
3943 | { "vpdpwusd", { XM, Vex, EXx }, 0 }, | |
3944 | }, | |
3945 | ||
3946 | /* PREFIX_VEX_0F38D3_W_0 */ | |
3947 | { | |
3948 | { "vpdpwuuds", { XM, Vex, EXx }, 0 }, | |
3949 | { "vpdpwsuds", { XM, Vex, EXx }, 0 }, | |
3950 | { "vpdpwusds", { XM, Vex, EXx }, 0 }, | |
3951 | }, | |
3952 | ||
3953 | /* PREFIX_VEX_0F38CB */ | |
3954 | { | |
3955 | { Bad_Opcode }, | |
3956 | { Bad_Opcode }, | |
3957 | { Bad_Opcode }, | |
3958 | { VEX_W_TABLE (VEX_W_0F38CB_P_3) }, | |
3959 | }, | |
3960 | ||
3961 | /* PREFIX_VEX_0F38CC */ | |
3962 | { | |
3963 | { Bad_Opcode }, | |
3964 | { Bad_Opcode }, | |
3965 | { Bad_Opcode }, | |
3966 | { VEX_W_TABLE (VEX_W_0F38CC_P_3) }, | |
3967 | }, | |
3968 | ||
3969 | /* PREFIX_VEX_0F38CD */ | |
3970 | { | |
3971 | { Bad_Opcode }, | |
3972 | { Bad_Opcode }, | |
3973 | { Bad_Opcode }, | |
3974 | { VEX_W_TABLE (VEX_W_0F38CD_P_3) }, | |
3975 | }, | |
3976 | ||
3977 | /* PREFIX_VEX_0F38DA_W_0 */ | |
3978 | { | |
3979 | { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) }, | |
3980 | { "vsm4key4", { XM, Vex, EXx }, 0 }, | |
3981 | { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) }, | |
3982 | { "vsm4rnds4", { XM, Vex, EXx }, 0 }, | |
3983 | }, | |
3984 | ||
14d10c6c | 3985 | /* PREFIX_VEX_0F38F5_L_0 */ |
48521003 | 3986 | { |
14d10c6c JB |
3987 | { "bzhiS", { Gdq, Edq, VexGdq }, 0 }, |
3988 | { "pextS", { Gdq, VexGdq, Edq }, 0 }, | |
48521003 | 3989 | { Bad_Opcode }, |
14d10c6c | 3990 | { "pdepS", { Gdq, VexGdq, Edq }, 0 }, |
48521003 IT |
3991 | }, |
3992 | ||
14d10c6c | 3993 | /* PREFIX_VEX_0F38F6_L_0 */ |
48521003 IT |
3994 | { |
3995 | { Bad_Opcode }, | |
3996 | { Bad_Opcode }, | |
7531c613 | 3997 | { Bad_Opcode }, |
14d10c6c | 3998 | { "mulxS", { Gdq, VexGdq, Edq }, 0 }, |
48521003 IT |
3999 | }, |
4000 | ||
14d10c6c | 4001 | /* PREFIX_VEX_0F38F7_L_0 */ |
a5ff0eb2 | 4002 | { |
14d10c6c JB |
4003 | { "bextrS", { Gdq, Edq, VexGdq }, 0 }, |
4004 | { "sarxS", { Gdq, Edq, VexGdq }, 0 }, | |
4005 | { "shlxS", { Gdq, Edq, VexGdq }, 0 }, | |
4006 | { "shrxS", { Gdq, Edq, VexGdq }, 0 }, | |
a5ff0eb2 | 4007 | }, |
6c30d220 | 4008 | |
14d10c6c | 4009 | /* PREFIX_VEX_0F3AF0_L_0 */ |
6c30d220 L |
4010 | { |
4011 | { Bad_Opcode }, | |
4012 | { Bad_Opcode }, | |
4013 | { Bad_Opcode }, | |
14d10c6c | 4014 | { "rorxS", { Gdq, Edq, Ib }, 0 }, |
6c30d220 | 4015 | }, |
43234a1e | 4016 | |
ad692897 | 4017 | #include "i386-dis-evex-prefix.h" |
c0f3af97 L |
4018 | }; |
4019 | ||
4020 | static const struct dis386 x86_64_table[][2] = { | |
4021 | /* X86_64_06 */ | |
4022 | { | |
bf890a93 | 4023 | { "pushP", { es }, 0 }, |
c0f3af97 L |
4024 | }, |
4025 | ||
4026 | /* X86_64_07 */ | |
4027 | { | |
bf890a93 | 4028 | { "popP", { es }, 0 }, |
c0f3af97 L |
4029 | }, |
4030 | ||
1673df32 | 4031 | /* X86_64_0E */ |
c0f3af97 | 4032 | { |
bf890a93 | 4033 | { "pushP", { cs }, 0 }, |
c0f3af97 L |
4034 | }, |
4035 | ||
4036 | /* X86_64_16 */ | |
4037 | { | |
bf890a93 | 4038 | { "pushP", { ss }, 0 }, |
c0f3af97 L |
4039 | }, |
4040 | ||
4041 | /* X86_64_17 */ | |
4042 | { | |
bf890a93 | 4043 | { "popP", { ss }, 0 }, |
c0f3af97 L |
4044 | }, |
4045 | ||
4046 | /* X86_64_1E */ | |
4047 | { | |
bf890a93 | 4048 | { "pushP", { ds }, 0 }, |
c0f3af97 L |
4049 | }, |
4050 | ||
4051 | /* X86_64_1F */ | |
4052 | { | |
bf890a93 | 4053 | { "popP", { ds }, 0 }, |
c0f3af97 L |
4054 | }, |
4055 | ||
4056 | /* X86_64_27 */ | |
4057 | { | |
bf890a93 | 4058 | { "daa", { XX }, 0 }, |
c0f3af97 L |
4059 | }, |
4060 | ||
4061 | /* X86_64_2F */ | |
4062 | { | |
bf890a93 | 4063 | { "das", { XX }, 0 }, |
c0f3af97 L |
4064 | }, |
4065 | ||
4066 | /* X86_64_37 */ | |
4067 | { | |
bf890a93 | 4068 | { "aaa", { XX }, 0 }, |
c0f3af97 L |
4069 | }, |
4070 | ||
4071 | /* X86_64_3F */ | |
4072 | { | |
bf890a93 | 4073 | { "aas", { XX }, 0 }, |
c0f3af97 L |
4074 | }, |
4075 | ||
4076 | /* X86_64_60 */ | |
4077 | { | |
bf890a93 | 4078 | { "pushaP", { XX }, 0 }, |
c0f3af97 L |
4079 | }, |
4080 | ||
4081 | /* X86_64_61 */ | |
4082 | { | |
bf890a93 | 4083 | { "popaP", { XX }, 0 }, |
c0f3af97 L |
4084 | }, |
4085 | ||
4086 | /* X86_64_62 */ | |
4087 | { | |
4088 | { MOD_TABLE (MOD_62_32BIT) }, | |
b5c37946 | 4089 | { EVEX_TABLE () }, |
c0f3af97 L |
4090 | }, |
4091 | ||
4092 | /* X86_64_63 */ | |
4093 | { | |
b5c37946 | 4094 | { "arplS", { Sv, Gv }, 0 }, |
5f6b8397 | 4095 | { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 }, |
c0f3af97 L |
4096 | }, |
4097 | ||
4098 | /* X86_64_6D */ | |
4099 | { | |
bf890a93 IT |
4100 | { "ins{R|}", { Yzr, indirDX }, 0 }, |
4101 | { "ins{G|}", { Yzr, indirDX }, 0 }, | |
c0f3af97 L |
4102 | }, |
4103 | ||
4104 | /* X86_64_6F */ | |
4105 | { | |
bf890a93 IT |
4106 | { "outs{R|}", { indirDXr, Xz }, 0 }, |
4107 | { "outs{G|}", { indirDXr, Xz }, 0 }, | |
c0f3af97 L |
4108 | }, |
4109 | ||
d039fef3 | 4110 | /* X86_64_82 */ |
8b89fe14 | 4111 | { |
de194d85 | 4112 | /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode. */ |
d039fef3 | 4113 | { REG_TABLE (REG_80) }, |
8b89fe14 L |
4114 | }, |
4115 | ||
c0f3af97 L |
4116 | /* X86_64_9A */ |
4117 | { | |
36938cab | 4118 | { "{l|}call{P|}", { Ap }, 0 }, |
c0f3af97 L |
4119 | }, |
4120 | ||
aeab2b26 JB |
4121 | /* X86_64_C2 */ |
4122 | { | |
4123 | { "retP", { Iw, BND }, 0 }, | |
4124 | { "ret@", { Iw, BND }, 0 }, | |
4125 | }, | |
4126 | ||
4127 | /* X86_64_C3 */ | |
4128 | { | |
4129 | { "retP", { BND }, 0 }, | |
4130 | { "ret@", { BND }, 0 }, | |
4131 | }, | |
4132 | ||
c0f3af97 L |
4133 | /* X86_64_C4 */ |
4134 | { | |
4135 | { MOD_TABLE (MOD_C4_32BIT) }, | |
b5c37946 | 4136 | { VEX_C4_TABLE () }, |
c0f3af97 L |
4137 | }, |
4138 | ||
4139 | /* X86_64_C5 */ | |
4140 | { | |
4141 | { MOD_TABLE (MOD_C5_32BIT) }, | |
b5c37946 | 4142 | { VEX_C5_TABLE () }, |
c0f3af97 L |
4143 | }, |
4144 | ||
4145 | /* X86_64_CE */ | |
4146 | { | |
bf890a93 | 4147 | { "into", { XX }, 0 }, |
c0f3af97 L |
4148 | }, |
4149 | ||
4150 | /* X86_64_D4 */ | |
4151 | { | |
bf890a93 | 4152 | { "aam", { Ib }, 0 }, |
c0f3af97 L |
4153 | }, |
4154 | ||
4155 | /* X86_64_D5 */ | |
4156 | { | |
bf890a93 | 4157 | { "aad", { Ib }, 0 }, |
c0f3af97 L |
4158 | }, |
4159 | ||
a72d2af2 L |
4160 | /* X86_64_E8 */ |
4161 | { | |
4162 | { "callP", { Jv, BND }, 0 }, | |
5db04b09 | 4163 | { "call@", { Jv, BND }, 0 } |
a72d2af2 L |
4164 | }, |
4165 | ||
4166 | /* X86_64_E9 */ | |
4167 | { | |
4168 | { "jmpP", { Jv, BND }, 0 }, | |
5db04b09 | 4169 | { "jmp@", { Jv, BND }, 0 } |
a72d2af2 L |
4170 | }, |
4171 | ||
c0f3af97 L |
4172 | /* X86_64_EA */ |
4173 | { | |
36938cab | 4174 | { "{l|}jmp{P|}", { Ap }, 0 }, |
c0f3af97 L |
4175 | }, |
4176 | ||
c88ed92f ZJ |
4177 | /* X86_64_0F00_REG_6 */ |
4178 | { | |
4179 | { Bad_Opcode }, | |
4180 | { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) }, | |
4181 | }, | |
4182 | ||
c0f3af97 L |
4183 | /* X86_64_0F01_REG_0 */ |
4184 | { | |
d1c36125 | 4185 | { "sgdt{Q|Q}", { M }, 0 }, |
bf890a93 | 4186 | { "sgdt", { M }, 0 }, |
c0f3af97 L |
4187 | }, |
4188 | ||
2188d6ea HL |
4189 | /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */ |
4190 | { | |
4191 | { Bad_Opcode }, | |
4192 | { "wrmsrlist", { Skip_MODRM }, 0 }, | |
4193 | }, | |
4194 | ||
4195 | /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */ | |
4196 | { | |
4197 | { Bad_Opcode }, | |
4198 | { "rdmsrlist", { Skip_MODRM }, 0 }, | |
4199 | }, | |
4200 | ||
b5c37946 SJ |
4201 | /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */ |
4202 | { | |
4203 | { Bad_Opcode }, | |
4204 | { "pbndkb", { Skip_MODRM }, 0 }, | |
4205 | }, | |
4206 | ||
c0f3af97 L |
4207 | /* X86_64_0F01_REG_1 */ |
4208 | { | |
d1c36125 | 4209 | { "sidt{Q|Q}", { M }, 0 }, |
bf890a93 | 4210 | { "sidt", { M }, 0 }, |
c0f3af97 L |
4211 | }, |
4212 | ||
c88ed92f ZJ |
4213 | /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */ |
4214 | { | |
4215 | { Bad_Opcode }, | |
4216 | { "eretu", { Skip_MODRM }, 0 }, | |
4217 | }, | |
4218 | ||
4219 | /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */ | |
4220 | { | |
4221 | { Bad_Opcode }, | |
4222 | { "erets", { Skip_MODRM }, 0 }, | |
4223 | }, | |
4224 | ||
81d54bb7 CL |
4225 | /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */ |
4226 | { | |
4227 | { Bad_Opcode }, | |
4228 | { "seamret", { Skip_MODRM }, 0 }, | |
4229 | }, | |
4230 | ||
4231 | /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */ | |
4232 | { | |
4233 | { Bad_Opcode }, | |
4234 | { "seamops", { Skip_MODRM }, 0 }, | |
4235 | }, | |
4236 | ||
4237 | /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */ | |
4238 | { | |
4239 | { Bad_Opcode }, | |
4240 | { "seamcall", { Skip_MODRM }, 0 }, | |
4241 | }, | |
4242 | ||
c0f3af97 L |
4243 | /* X86_64_0F01_REG_2 */ |
4244 | { | |
bf890a93 IT |
4245 | { "lgdt{Q|Q}", { M }, 0 }, |
4246 | { "lgdt", { M }, 0 }, | |
c0f3af97 L |
4247 | }, |
4248 | ||
4249 | /* X86_64_0F01_REG_3 */ | |
4250 | { | |
bf890a93 IT |
4251 | { "lidt{Q|Q}", { M }, 0 }, |
4252 | { "lidt", { M }, 0 }, | |
c0f3af97 | 4253 | }, |
260cd341 | 4254 | |
32e31ad7 | 4255 | /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */ |
78467458 | 4256 | { |
32e31ad7 JB |
4257 | { Bad_Opcode }, |
4258 | { "uiret", { Skip_MODRM }, 0 }, | |
78467458 JB |
4259 | }, |
4260 | ||
32e31ad7 | 4261 | /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */ |
78467458 | 4262 | { |
32e31ad7 JB |
4263 | { Bad_Opcode }, |
4264 | { "testui", { Skip_MODRM }, 0 }, | |
78467458 JB |
4265 | }, |
4266 | ||
32e31ad7 | 4267 | /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */ |
260cd341 LC |
4268 | { |
4269 | { Bad_Opcode }, | |
32e31ad7 | 4270 | { "clui", { Skip_MODRM }, 0 }, |
260cd341 LC |
4271 | }, |
4272 | ||
32e31ad7 | 4273 | /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */ |
260cd341 LC |
4274 | { |
4275 | { Bad_Opcode }, | |
32e31ad7 | 4276 | { "stui", { Skip_MODRM }, 0 }, |
260cd341 LC |
4277 | }, |
4278 | ||
b0e8fa7f TJ |
4279 | /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */ |
4280 | { | |
4281 | { Bad_Opcode }, | |
4282 | { "rmpquery", { Skip_MODRM }, 0 }, | |
4283 | }, | |
4284 | ||
32e31ad7 | 4285 | /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */ |
260cd341 LC |
4286 | { |
4287 | { Bad_Opcode }, | |
32e31ad7 | 4288 | { "rmpadjust", { Skip_MODRM }, 0 }, |
260cd341 LC |
4289 | }, |
4290 | ||
32e31ad7 | 4291 | /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */ |
260cd341 LC |
4292 | { |
4293 | { Bad_Opcode }, | |
32e31ad7 | 4294 | { "rmpupdate", { Skip_MODRM }, 0 }, |
260cd341 | 4295 | }, |
f64c42a9 | 4296 | |
32e31ad7 | 4297 | /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */ |
f64c42a9 LC |
4298 | { |
4299 | { Bad_Opcode }, | |
32e31ad7 | 4300 | { "psmash", { Skip_MODRM }, 0 }, |
f64c42a9 LC |
4301 | }, |
4302 | ||
ef07be45 CL |
4303 | /* X86_64_0F18_REG_6_MOD_0 */ |
4304 | { | |
4305 | { "nopQ", { Ev }, 0 }, | |
4306 | { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) }, | |
4307 | }, | |
4308 | ||
4309 | /* X86_64_0F18_REG_7_MOD_0 */ | |
4310 | { | |
4311 | { "nopQ", { Ev }, 0 }, | |
4312 | { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) }, | |
4313 | }, | |
4314 | ||
f64c42a9 | 4315 | { |
32e31ad7 JB |
4316 | /* X86_64_0F24 */ |
4317 | { "movZ", { Em, Td }, 0 }, | |
f64c42a9 LC |
4318 | }, |
4319 | ||
f64c42a9 | 4320 | { |
32e31ad7 JB |
4321 | /* X86_64_0F26 */ |
4322 | { "movZ", { Td, Em }, 0 }, | |
f64c42a9 LC |
4323 | }, |
4324 | ||
32e31ad7 | 4325 | /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */ |
f64c42a9 LC |
4326 | { |
4327 | { Bad_Opcode }, | |
32e31ad7 | 4328 | { "senduipi", { Eq }, 0 }, |
f64c42a9 LC |
4329 | }, |
4330 | ||
32e31ad7 | 4331 | /* X86_64_VEX_0F3849 */ |
646cc3e0 GG |
4332 | { |
4333 | { Bad_Opcode }, | |
1f506c06 | 4334 | { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) }, |
646cc3e0 GG |
4335 | }, |
4336 | ||
32e31ad7 | 4337 | /* X86_64_VEX_0F384B */ |
646cc3e0 GG |
4338 | { |
4339 | { Bad_Opcode }, | |
1f506c06 | 4340 | { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) }, |
646cc3e0 GG |
4341 | }, |
4342 | ||
32e31ad7 | 4343 | /* X86_64_VEX_0F385C */ |
646cc3e0 GG |
4344 | { |
4345 | { Bad_Opcode }, | |
b5c37946 | 4346 | { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) }, |
646cc3e0 GG |
4347 | }, |
4348 | ||
32e31ad7 | 4349 | /* X86_64_VEX_0F385E */ |
f64c42a9 LC |
4350 | { |
4351 | { Bad_Opcode }, | |
b5c37946 | 4352 | { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) }, |
f64c42a9 | 4353 | }, |
a93e3234 | 4354 | |
d100d8c1 HJ |
4355 | /* X86_64_VEX_0F386C */ |
4356 | { | |
4357 | { Bad_Opcode }, | |
b5c37946 | 4358 | { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) }, |
d100d8c1 HJ |
4359 | }, |
4360 | ||
a93e3234 HJ |
4361 | /* X86_64_VEX_0F38E0 */ |
4362 | { | |
4363 | { Bad_Opcode }, | |
4364 | { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4365 | }, | |
4366 | ||
4367 | /* X86_64_VEX_0F38E1 */ | |
4368 | { | |
4369 | { Bad_Opcode }, | |
4370 | { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4371 | }, | |
4372 | ||
4373 | /* X86_64_VEX_0F38E2 */ | |
4374 | { | |
4375 | { Bad_Opcode }, | |
4376 | { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4377 | }, | |
4378 | ||
4379 | /* X86_64_VEX_0F38E3 */ | |
4380 | { | |
4381 | { Bad_Opcode }, | |
4382 | { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4383 | }, | |
4384 | ||
4385 | /* X86_64_VEX_0F38E4 */ | |
4386 | { | |
4387 | { Bad_Opcode }, | |
4388 | { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4389 | }, | |
4390 | ||
4391 | /* X86_64_VEX_0F38E5 */ | |
4392 | { | |
4393 | { Bad_Opcode }, | |
4394 | { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4395 | }, | |
4396 | ||
4397 | /* X86_64_VEX_0F38E6 */ | |
4398 | { | |
4399 | { Bad_Opcode }, | |
4400 | { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4401 | }, | |
4402 | ||
4403 | /* X86_64_VEX_0F38E7 */ | |
4404 | { | |
4405 | { Bad_Opcode }, | |
4406 | { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4407 | }, | |
4408 | ||
4409 | /* X86_64_VEX_0F38E8 */ | |
4410 | { | |
4411 | { Bad_Opcode }, | |
4412 | { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4413 | }, | |
4414 | ||
4415 | /* X86_64_VEX_0F38E9 */ | |
4416 | { | |
4417 | { Bad_Opcode }, | |
4418 | { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4419 | }, | |
4420 | ||
4421 | /* X86_64_VEX_0F38EA */ | |
4422 | { | |
4423 | { Bad_Opcode }, | |
4424 | { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4425 | }, | |
4426 | ||
4427 | /* X86_64_VEX_0F38EB */ | |
4428 | { | |
4429 | { Bad_Opcode }, | |
4430 | { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4431 | }, | |
4432 | ||
4433 | /* X86_64_VEX_0F38EC */ | |
4434 | { | |
4435 | { Bad_Opcode }, | |
4436 | { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4437 | }, | |
4438 | ||
4439 | /* X86_64_VEX_0F38ED */ | |
4440 | { | |
4441 | { Bad_Opcode }, | |
4442 | { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4443 | }, | |
4444 | ||
4445 | /* X86_64_VEX_0F38EE */ | |
4446 | { | |
4447 | { Bad_Opcode }, | |
4448 | { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4449 | }, | |
4450 | ||
4451 | /* X86_64_VEX_0F38EF */ | |
4452 | { | |
4453 | { Bad_Opcode }, | |
4454 | { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA }, | |
4455 | }, | |
c0f3af97 L |
4456 | }; |
4457 | ||
4458 | static const struct dis386 three_byte_table[][256] = { | |
c1e679ec DR |
4459 | |
4460 | /* THREE_BYTE_0F38 */ | |
c0f3af97 L |
4461 | { |
4462 | /* 00 */ | |
507bd325 L |
4463 | { "pshufb", { MX, EM }, PREFIX_OPCODE }, |
4464 | { "phaddw", { MX, EM }, PREFIX_OPCODE }, | |
4465 | { "phaddd", { MX, EM }, PREFIX_OPCODE }, | |
4466 | { "phaddsw", { MX, EM }, PREFIX_OPCODE }, | |
4467 | { "pmaddubsw", { MX, EM }, PREFIX_OPCODE }, | |
4468 | { "phsubw", { MX, EM }, PREFIX_OPCODE }, | |
4469 | { "phsubd", { MX, EM }, PREFIX_OPCODE }, | |
4470 | { "phsubsw", { MX, EM }, PREFIX_OPCODE }, | |
c0f3af97 | 4471 | /* 08 */ |
507bd325 L |
4472 | { "psignb", { MX, EM }, PREFIX_OPCODE }, |
4473 | { "psignw", { MX, EM }, PREFIX_OPCODE }, | |
4474 | { "psignd", { MX, EM }, PREFIX_OPCODE }, | |
4475 | { "pmulhrsw", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 L |
4476 | { Bad_Opcode }, |
4477 | { Bad_Opcode }, | |
4478 | { Bad_Opcode }, | |
4479 | { Bad_Opcode }, | |
f88c9eb0 | 4480 | /* 10 */ |
7531c613 | 4481 | { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA }, |
592d1631 L |
4482 | { Bad_Opcode }, |
4483 | { Bad_Opcode }, | |
4484 | { Bad_Opcode }, | |
7531c613 JB |
4485 | { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA }, |
4486 | { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA }, | |
592d1631 | 4487 | { Bad_Opcode }, |
7531c613 | 4488 | { "ptest", { XM, EXx }, PREFIX_DATA }, |
f88c9eb0 | 4489 | /* 18 */ |
592d1631 L |
4490 | { Bad_Opcode }, |
4491 | { Bad_Opcode }, | |
4492 | { Bad_Opcode }, | |
4493 | { Bad_Opcode }, | |
507bd325 L |
4494 | { "pabsb", { MX, EM }, PREFIX_OPCODE }, |
4495 | { "pabsw", { MX, EM }, PREFIX_OPCODE }, | |
4496 | { "pabsd", { MX, EM }, PREFIX_OPCODE }, | |
592d1631 | 4497 | { Bad_Opcode }, |
f88c9eb0 | 4498 | /* 20 */ |
7531c613 JB |
4499 | { "pmovsxbw", { XM, EXq }, PREFIX_DATA }, |
4500 | { "pmovsxbd", { XM, EXd }, PREFIX_DATA }, | |
4501 | { "pmovsxbq", { XM, EXw }, PREFIX_DATA }, | |
4502 | { "pmovsxwd", { XM, EXq }, PREFIX_DATA }, | |
4503 | { "pmovsxwq", { XM, EXd }, PREFIX_DATA }, | |
4504 | { "pmovsxdq", { XM, EXq }, PREFIX_DATA }, | |
592d1631 L |
4505 | { Bad_Opcode }, |
4506 | { Bad_Opcode }, | |
f88c9eb0 | 4507 | /* 28 */ |
7531c613 JB |
4508 | { "pmuldq", { XM, EXx }, PREFIX_DATA }, |
4509 | { "pcmpeqq", { XM, EXx }, PREFIX_DATA }, | |
b5c37946 | 4510 | { "movntdqa", { XM, Mx }, PREFIX_DATA }, |
7531c613 | 4511 | { "packusdw", { XM, EXx }, PREFIX_DATA }, |
592d1631 L |
4512 | { Bad_Opcode }, |
4513 | { Bad_Opcode }, | |
4514 | { Bad_Opcode }, | |
4515 | { Bad_Opcode }, | |
f88c9eb0 | 4516 | /* 30 */ |
7531c613 JB |
4517 | { "pmovzxbw", { XM, EXq }, PREFIX_DATA }, |
4518 | { "pmovzxbd", { XM, EXd }, PREFIX_DATA }, | |
4519 | { "pmovzxbq", { XM, EXw }, PREFIX_DATA }, | |
4520 | { "pmovzxwd", { XM, EXq }, PREFIX_DATA }, | |
4521 | { "pmovzxwq", { XM, EXd }, PREFIX_DATA }, | |
4522 | { "pmovzxdq", { XM, EXq }, PREFIX_DATA }, | |
4523 | { Bad_Opcode }, | |
4524 | { "pcmpgtq", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4525 | /* 38 */ |
7531c613 JB |
4526 | { "pminsb", { XM, EXx }, PREFIX_DATA }, |
4527 | { "pminsd", { XM, EXx }, PREFIX_DATA }, | |
4528 | { "pminuw", { XM, EXx }, PREFIX_DATA }, | |
4529 | { "pminud", { XM, EXx }, PREFIX_DATA }, | |
4530 | { "pmaxsb", { XM, EXx }, PREFIX_DATA }, | |
4531 | { "pmaxsd", { XM, EXx }, PREFIX_DATA }, | |
4532 | { "pmaxuw", { XM, EXx }, PREFIX_DATA }, | |
4533 | { "pmaxud", { XM, EXx }, PREFIX_DATA }, | |
f88c9eb0 | 4534 | /* 40 */ |
7531c613 JB |
4535 | { "pmulld", { XM, EXx }, PREFIX_DATA }, |
4536 | { "phminposuw", { XM, EXx }, PREFIX_DATA }, | |
592d1631 L |
4537 | { Bad_Opcode }, |
4538 | { Bad_Opcode }, | |
4539 | { Bad_Opcode }, | |
4540 | { Bad_Opcode }, | |
4541 | { Bad_Opcode }, | |
4542 | { Bad_Opcode }, | |
f88c9eb0 | 4543 | /* 48 */ |
592d1631 L |
4544 | { Bad_Opcode }, |
4545 | { Bad_Opcode }, | |
4546 | { Bad_Opcode }, | |
4547 | { Bad_Opcode }, | |
4548 | { Bad_Opcode }, | |
4549 | { Bad_Opcode }, | |
4550 | { Bad_Opcode }, | |
4551 | { Bad_Opcode }, | |
f88c9eb0 | 4552 | /* 50 */ |
592d1631 L |
4553 | { Bad_Opcode }, |
4554 | { Bad_Opcode }, | |
4555 | { Bad_Opcode }, | |
4556 | { Bad_Opcode }, | |
4557 | { Bad_Opcode }, | |
4558 | { Bad_Opcode }, | |
4559 | { Bad_Opcode }, | |
4560 | { Bad_Opcode }, | |
f88c9eb0 | 4561 | /* 58 */ |
592d1631 L |
4562 | { Bad_Opcode }, |
4563 | { Bad_Opcode }, | |
4564 | { Bad_Opcode }, | |
4565 | { Bad_Opcode }, | |
4566 | { Bad_Opcode }, | |
4567 | { Bad_Opcode }, | |
4568 | { Bad_Opcode }, | |
4569 | { Bad_Opcode }, | |
f88c9eb0 | 4570 | /* 60 */ |
592d1631 L |
4571 | { Bad_Opcode }, |
4572 | { Bad_Opcode }, | |
4573 | { Bad_Opcode }, | |
4574 | { Bad_Opcode }, | |
4575 | { Bad_Opcode }, | |
4576 | { Bad_Opcode }, | |
4577 | { Bad_Opcode }, | |
4578 | { Bad_Opcode }, | |
f88c9eb0 | 4579 | /* 68 */ |
592d1631 L |
4580 | { Bad_Opcode }, |
4581 | { Bad_Opcode }, | |
4582 | { Bad_Opcode }, | |
4583 | { Bad_Opcode }, | |
4584 | { Bad_Opcode }, | |
4585 | { Bad_Opcode }, | |
4586 | { Bad_Opcode }, | |
4587 | { Bad_Opcode }, | |
f88c9eb0 | 4588 | /* 70 */ |
592d1631 L |
4589 | { Bad_Opcode }, |
4590 | { Bad_Opcode }, | |
4591 | { Bad_Opcode }, | |
4592 | { Bad_Opcode }, | |
4593 | { Bad_Opcode }, | |
4594 | { Bad_Opcode }, | |
4595 | { Bad_Opcode }, | |
4596 | { Bad_Opcode }, | |
f88c9eb0 | 4597 | /* 78 */ |
592d1631 L |
4598 | { Bad_Opcode }, |
4599 | { Bad_Opcode }, | |
4600 | { Bad_Opcode }, | |
4601 | { Bad_Opcode }, | |
4602 | { Bad_Opcode }, | |
4603 | { Bad_Opcode }, | |
4604 | { Bad_Opcode }, | |
4605 | { Bad_Opcode }, | |
f88c9eb0 | 4606 | /* 80 */ |
7531c613 JB |
4607 | { "invept", { Gm, Mo }, PREFIX_DATA }, |
4608 | { "invvpid", { Gm, Mo }, PREFIX_DATA }, | |
4609 | { "invpcid", { Gm, M }, PREFIX_DATA }, | |
592d1631 L |
4610 | { Bad_Opcode }, |
4611 | { Bad_Opcode }, | |
4612 | { Bad_Opcode }, | |
4613 | { Bad_Opcode }, | |
4614 | { Bad_Opcode }, | |
f88c9eb0 | 4615 | /* 88 */ |
592d1631 L |
4616 | { Bad_Opcode }, |
4617 | { Bad_Opcode }, | |
4618 | { Bad_Opcode }, | |
4619 | { Bad_Opcode }, | |
4620 | { Bad_Opcode }, | |
4621 | { Bad_Opcode }, | |
4622 | { Bad_Opcode }, | |
4623 | { Bad_Opcode }, | |
f88c9eb0 | 4624 | /* 90 */ |
592d1631 L |
4625 | { Bad_Opcode }, |
4626 | { Bad_Opcode }, | |
4627 | { Bad_Opcode }, | |
4628 | { Bad_Opcode }, | |
4629 | { Bad_Opcode }, | |
4630 | { Bad_Opcode }, | |
4631 | { Bad_Opcode }, | |
4632 | { Bad_Opcode }, | |
f88c9eb0 | 4633 | /* 98 */ |
592d1631 L |
4634 | { Bad_Opcode }, |
4635 | { Bad_Opcode }, | |
4636 | { Bad_Opcode }, | |
4637 | { Bad_Opcode }, | |
4638 | { Bad_Opcode }, | |
4639 | { Bad_Opcode }, | |
4640 | { Bad_Opcode }, | |
4641 | { Bad_Opcode }, | |
f88c9eb0 | 4642 | /* a0 */ |
592d1631 L |
4643 | { Bad_Opcode }, |
4644 | { Bad_Opcode }, | |
4645 | { Bad_Opcode }, | |
4646 | { Bad_Opcode }, | |
4647 | { Bad_Opcode }, | |
4648 | { Bad_Opcode }, | |
4649 | { Bad_Opcode }, | |
4650 | { Bad_Opcode }, | |
f88c9eb0 | 4651 | /* a8 */ |
592d1631 L |
4652 | { Bad_Opcode }, |
4653 | { Bad_Opcode }, | |
4654 | { Bad_Opcode }, | |
4655 | { Bad_Opcode }, | |
4656 | { Bad_Opcode }, | |
4657 | { Bad_Opcode }, | |
4658 | { Bad_Opcode }, | |
4659 | { Bad_Opcode }, | |
f88c9eb0 | 4660 | /* b0 */ |
592d1631 L |
4661 | { Bad_Opcode }, |
4662 | { Bad_Opcode }, | |
4663 | { Bad_Opcode }, | |
4664 | { Bad_Opcode }, | |
4665 | { Bad_Opcode }, | |
4666 | { Bad_Opcode }, | |
4667 | { Bad_Opcode }, | |
4668 | { Bad_Opcode }, | |
f88c9eb0 | 4669 | /* b8 */ |
592d1631 L |
4670 | { Bad_Opcode }, |
4671 | { Bad_Opcode }, | |
4672 | { Bad_Opcode }, | |
4673 | { Bad_Opcode }, | |
4674 | { Bad_Opcode }, | |
4675 | { Bad_Opcode }, | |
4676 | { Bad_Opcode }, | |
4677 | { Bad_Opcode }, | |
f88c9eb0 | 4678 | /* c0 */ |
592d1631 L |
4679 | { Bad_Opcode }, |
4680 | { Bad_Opcode }, | |
4681 | { Bad_Opcode }, | |
4682 | { Bad_Opcode }, | |
4683 | { Bad_Opcode }, | |
4684 | { Bad_Opcode }, | |
4685 | { Bad_Opcode }, | |
4686 | { Bad_Opcode }, | |
f88c9eb0 | 4687 | /* c8 */ |
035e7389 JB |
4688 | { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE }, |
4689 | { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4690 | { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
4691 | { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE }, | |
4692 | { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE }, | |
4693 | { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE }, | |
592d1631 | 4694 | { Bad_Opcode }, |
7531c613 | 4695 | { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA }, |
f88c9eb0 | 4696 | /* d0 */ |
592d1631 L |
4697 | { Bad_Opcode }, |
4698 | { Bad_Opcode }, | |
4699 | { Bad_Opcode }, | |
4700 | { Bad_Opcode }, | |
4701 | { Bad_Opcode }, | |
4702 | { Bad_Opcode }, | |
4703 | { Bad_Opcode }, | |
4704 | { Bad_Opcode }, | |
f88c9eb0 | 4705 | /* d8 */ |
c4694f17 | 4706 | { PREFIX_TABLE (PREFIX_0F38D8) }, |
592d1631 L |
4707 | { Bad_Opcode }, |
4708 | { Bad_Opcode }, | |
7531c613 | 4709 | { "aesimc", { XM, EXx }, PREFIX_DATA }, |
c4694f17 TG |
4710 | { PREFIX_TABLE (PREFIX_0F38DC) }, |
4711 | { PREFIX_TABLE (PREFIX_0F38DD) }, | |
4712 | { PREFIX_TABLE (PREFIX_0F38DE) }, | |
4713 | { PREFIX_TABLE (PREFIX_0F38DF) }, | |
f88c9eb0 | 4714 | /* e0 */ |
592d1631 L |
4715 | { Bad_Opcode }, |
4716 | { Bad_Opcode }, | |
4717 | { Bad_Opcode }, | |
4718 | { Bad_Opcode }, | |
4719 | { Bad_Opcode }, | |
4720 | { Bad_Opcode }, | |
4721 | { Bad_Opcode }, | |
4722 | { Bad_Opcode }, | |
f88c9eb0 | 4723 | /* e8 */ |
592d1631 L |
4724 | { Bad_Opcode }, |
4725 | { Bad_Opcode }, | |
4726 | { Bad_Opcode }, | |
4727 | { Bad_Opcode }, | |
4728 | { Bad_Opcode }, | |
4729 | { Bad_Opcode }, | |
4730 | { Bad_Opcode }, | |
4731 | { Bad_Opcode }, | |
f88c9eb0 SP |
4732 | /* f0 */ |
4733 | { PREFIX_TABLE (PREFIX_0F38F0) }, | |
4734 | { PREFIX_TABLE (PREFIX_0F38F1) }, | |
592d1631 L |
4735 | { Bad_Opcode }, |
4736 | { Bad_Opcode }, | |
4737 | { Bad_Opcode }, | |
b5c37946 | 4738 | { "wrussK", { M, Gdq }, PREFIX_DATA }, |
e2e1fcde | 4739 | { PREFIX_TABLE (PREFIX_0F38F6) }, |
592d1631 | 4740 | { Bad_Opcode }, |
f88c9eb0 | 4741 | /* f8 */ |
c0a30a9f | 4742 | { PREFIX_TABLE (PREFIX_0F38F8) }, |
b5c37946 | 4743 | { "movdiri", { Mdq, Gdq }, PREFIX_OPCODE }, |
c4694f17 TG |
4744 | { PREFIX_TABLE (PREFIX_0F38FA) }, |
4745 | { PREFIX_TABLE (PREFIX_0F38FB) }, | |
b06311ad | 4746 | { PREFIX_TABLE (PREFIX_0F38FC) }, |
592d1631 L |
4747 | { Bad_Opcode }, |
4748 | { Bad_Opcode }, | |
4749 | { Bad_Opcode }, | |
f88c9eb0 SP |
4750 | }, |
4751 | /* THREE_BYTE_0F3A */ | |
4752 | { | |
4753 | /* 00 */ | |
592d1631 L |
4754 | { Bad_Opcode }, |
4755 | { Bad_Opcode }, | |
4756 | { Bad_Opcode }, | |
4757 | { Bad_Opcode }, | |
4758 | { Bad_Opcode }, | |
4759 | { Bad_Opcode }, | |
4760 | { Bad_Opcode }, | |
4761 | { Bad_Opcode }, | |
f88c9eb0 | 4762 | /* 08 */ |
7531c613 JB |
4763 | { "roundps", { XM, EXx, Ib }, PREFIX_DATA }, |
4764 | { "roundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4765 | { "roundss", { XM, EXd, Ib }, PREFIX_DATA }, | |
4766 | { "roundsd", { XM, EXq, Ib }, PREFIX_DATA }, | |
4767 | { "blendps", { XM, EXx, Ib }, PREFIX_DATA }, | |
4768 | { "blendpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4769 | { "pblendw", { XM, EXx, Ib }, PREFIX_DATA }, | |
507bd325 | 4770 | { "palignr", { MX, EM, Ib }, PREFIX_OPCODE }, |
f88c9eb0 | 4771 | /* 10 */ |
592d1631 L |
4772 | { Bad_Opcode }, |
4773 | { Bad_Opcode }, | |
4774 | { Bad_Opcode }, | |
4775 | { Bad_Opcode }, | |
5fbe0f28 JB |
4776 | { "pextrb", { Edb, XM, Ib }, PREFIX_DATA }, |
4777 | { "pextrw", { Edw, XM, Ib }, PREFIX_DATA }, | |
7531c613 | 4778 | { "pextrK", { Edq, XM, Ib }, PREFIX_DATA }, |
5fbe0f28 | 4779 | { "extractps", { Ed, XM, Ib }, PREFIX_DATA }, |
f88c9eb0 | 4780 | /* 18 */ |
592d1631 L |
4781 | { Bad_Opcode }, |
4782 | { Bad_Opcode }, | |
4783 | { Bad_Opcode }, | |
4784 | { Bad_Opcode }, | |
4785 | { Bad_Opcode }, | |
4786 | { Bad_Opcode }, | |
4787 | { Bad_Opcode }, | |
4788 | { Bad_Opcode }, | |
f88c9eb0 | 4789 | /* 20 */ |
5fbe0f28 | 4790 | { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA }, |
7531c613 JB |
4791 | { "insertps", { XM, EXd, Ib }, PREFIX_DATA }, |
4792 | { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA }, | |
592d1631 L |
4793 | { Bad_Opcode }, |
4794 | { Bad_Opcode }, | |
4795 | { Bad_Opcode }, | |
4796 | { Bad_Opcode }, | |
4797 | { Bad_Opcode }, | |
f88c9eb0 | 4798 | /* 28 */ |
592d1631 L |
4799 | { Bad_Opcode }, |
4800 | { Bad_Opcode }, | |
4801 | { Bad_Opcode }, | |
4802 | { Bad_Opcode }, | |
4803 | { Bad_Opcode }, | |
4804 | { Bad_Opcode }, | |
4805 | { Bad_Opcode }, | |
4806 | { Bad_Opcode }, | |
f88c9eb0 | 4807 | /* 30 */ |
592d1631 L |
4808 | { Bad_Opcode }, |
4809 | { Bad_Opcode }, | |
4810 | { Bad_Opcode }, | |
4811 | { Bad_Opcode }, | |
4812 | { Bad_Opcode }, | |
4813 | { Bad_Opcode }, | |
4814 | { Bad_Opcode }, | |
4815 | { Bad_Opcode }, | |
f88c9eb0 | 4816 | /* 38 */ |
592d1631 L |
4817 | { Bad_Opcode }, |
4818 | { Bad_Opcode }, | |
4819 | { Bad_Opcode }, | |
4820 | { Bad_Opcode }, | |
4821 | { Bad_Opcode }, | |
4822 | { Bad_Opcode }, | |
4823 | { Bad_Opcode }, | |
4824 | { Bad_Opcode }, | |
f88c9eb0 | 4825 | /* 40 */ |
7531c613 JB |
4826 | { "dpps", { XM, EXx, Ib }, PREFIX_DATA }, |
4827 | { "dppd", { XM, EXx, Ib }, PREFIX_DATA }, | |
4828 | { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 4829 | { Bad_Opcode }, |
7531c613 | 4830 | { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 L |
4831 | { Bad_Opcode }, |
4832 | { Bad_Opcode }, | |
4833 | { Bad_Opcode }, | |
f88c9eb0 | 4834 | /* 48 */ |
592d1631 L |
4835 | { Bad_Opcode }, |
4836 | { Bad_Opcode }, | |
4837 | { Bad_Opcode }, | |
4838 | { Bad_Opcode }, | |
4839 | { Bad_Opcode }, | |
4840 | { Bad_Opcode }, | |
4841 | { Bad_Opcode }, | |
4842 | { Bad_Opcode }, | |
f88c9eb0 | 4843 | /* 50 */ |
592d1631 L |
4844 | { Bad_Opcode }, |
4845 | { Bad_Opcode }, | |
4846 | { Bad_Opcode }, | |
4847 | { Bad_Opcode }, | |
4848 | { Bad_Opcode }, | |
4849 | { Bad_Opcode }, | |
4850 | { Bad_Opcode }, | |
4851 | { Bad_Opcode }, | |
f88c9eb0 | 4852 | /* 58 */ |
592d1631 L |
4853 | { Bad_Opcode }, |
4854 | { Bad_Opcode }, | |
4855 | { Bad_Opcode }, | |
4856 | { Bad_Opcode }, | |
4857 | { Bad_Opcode }, | |
4858 | { Bad_Opcode }, | |
4859 | { Bad_Opcode }, | |
4860 | { Bad_Opcode }, | |
f88c9eb0 | 4861 | /* 60 */ |
7531c613 JB |
4862 | { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
4863 | { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, | |
4864 | { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, | |
4865 | { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, | |
592d1631 L |
4866 | { Bad_Opcode }, |
4867 | { Bad_Opcode }, | |
4868 | { Bad_Opcode }, | |
4869 | { Bad_Opcode }, | |
f88c9eb0 | 4870 | /* 68 */ |
592d1631 L |
4871 | { Bad_Opcode }, |
4872 | { Bad_Opcode }, | |
4873 | { Bad_Opcode }, | |
4874 | { Bad_Opcode }, | |
4875 | { Bad_Opcode }, | |
4876 | { Bad_Opcode }, | |
4877 | { Bad_Opcode }, | |
4878 | { Bad_Opcode }, | |
f88c9eb0 | 4879 | /* 70 */ |
592d1631 L |
4880 | { Bad_Opcode }, |
4881 | { Bad_Opcode }, | |
4882 | { Bad_Opcode }, | |
4883 | { Bad_Opcode }, | |
4884 | { Bad_Opcode }, | |
4885 | { Bad_Opcode }, | |
4886 | { Bad_Opcode }, | |
4887 | { Bad_Opcode }, | |
f88c9eb0 | 4888 | /* 78 */ |
592d1631 L |
4889 | { Bad_Opcode }, |
4890 | { Bad_Opcode }, | |
4891 | { Bad_Opcode }, | |
4892 | { Bad_Opcode }, | |
4893 | { Bad_Opcode }, | |
4894 | { Bad_Opcode }, | |
4895 | { Bad_Opcode }, | |
4896 | { Bad_Opcode }, | |
f88c9eb0 | 4897 | /* 80 */ |
592d1631 L |
4898 | { Bad_Opcode }, |
4899 | { Bad_Opcode }, | |
4900 | { Bad_Opcode }, | |
4901 | { Bad_Opcode }, | |
4902 | { Bad_Opcode }, | |
4903 | { Bad_Opcode }, | |
4904 | { Bad_Opcode }, | |
4905 | { Bad_Opcode }, | |
f88c9eb0 | 4906 | /* 88 */ |
592d1631 L |
4907 | { Bad_Opcode }, |
4908 | { Bad_Opcode }, | |
4909 | { Bad_Opcode }, | |
4910 | { Bad_Opcode }, | |
4911 | { Bad_Opcode }, | |
4912 | { Bad_Opcode }, | |
4913 | { Bad_Opcode }, | |
4914 | { Bad_Opcode }, | |
f88c9eb0 | 4915 | /* 90 */ |
592d1631 L |
4916 | { Bad_Opcode }, |
4917 | { Bad_Opcode }, | |
4918 | { Bad_Opcode }, | |
4919 | { Bad_Opcode }, | |
4920 | { Bad_Opcode }, | |
4921 | { Bad_Opcode }, | |
4922 | { Bad_Opcode }, | |
4923 | { Bad_Opcode }, | |
f88c9eb0 | 4924 | /* 98 */ |
592d1631 L |
4925 | { Bad_Opcode }, |
4926 | { Bad_Opcode }, | |
4927 | { Bad_Opcode }, | |
4928 | { Bad_Opcode }, | |
4929 | { Bad_Opcode }, | |
4930 | { Bad_Opcode }, | |
4931 | { Bad_Opcode }, | |
4932 | { Bad_Opcode }, | |
f88c9eb0 | 4933 | /* a0 */ |
592d1631 L |
4934 | { Bad_Opcode }, |
4935 | { Bad_Opcode }, | |
4936 | { Bad_Opcode }, | |
4937 | { Bad_Opcode }, | |
4938 | { Bad_Opcode }, | |
4939 | { Bad_Opcode }, | |
4940 | { Bad_Opcode }, | |
4941 | { Bad_Opcode }, | |
f88c9eb0 | 4942 | /* a8 */ |
592d1631 L |
4943 | { Bad_Opcode }, |
4944 | { Bad_Opcode }, | |
4945 | { Bad_Opcode }, | |
4946 | { Bad_Opcode }, | |
4947 | { Bad_Opcode }, | |
4948 | { Bad_Opcode }, | |
4949 | { Bad_Opcode }, | |
4950 | { Bad_Opcode }, | |
f88c9eb0 | 4951 | /* b0 */ |
592d1631 L |
4952 | { Bad_Opcode }, |
4953 | { Bad_Opcode }, | |
4954 | { Bad_Opcode }, | |
4955 | { Bad_Opcode }, | |
4956 | { Bad_Opcode }, | |
4957 | { Bad_Opcode }, | |
4958 | { Bad_Opcode }, | |
4959 | { Bad_Opcode }, | |
f88c9eb0 | 4960 | /* b8 */ |
592d1631 L |
4961 | { Bad_Opcode }, |
4962 | { Bad_Opcode }, | |
4963 | { Bad_Opcode }, | |
4964 | { Bad_Opcode }, | |
4965 | { Bad_Opcode }, | |
4966 | { Bad_Opcode }, | |
4967 | { Bad_Opcode }, | |
4968 | { Bad_Opcode }, | |
f88c9eb0 | 4969 | /* c0 */ |
592d1631 L |
4970 | { Bad_Opcode }, |
4971 | { Bad_Opcode }, | |
4972 | { Bad_Opcode }, | |
4973 | { Bad_Opcode }, | |
4974 | { Bad_Opcode }, | |
4975 | { Bad_Opcode }, | |
4976 | { Bad_Opcode }, | |
4977 | { Bad_Opcode }, | |
f88c9eb0 | 4978 | /* c8 */ |
592d1631 L |
4979 | { Bad_Opcode }, |
4980 | { Bad_Opcode }, | |
4981 | { Bad_Opcode }, | |
4982 | { Bad_Opcode }, | |
035e7389 | 4983 | { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE }, |
592d1631 | 4984 | { Bad_Opcode }, |
7531c613 JB |
4985 | { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA }, |
4986 | { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA }, | |
f88c9eb0 | 4987 | /* d0 */ |
592d1631 L |
4988 | { Bad_Opcode }, |
4989 | { Bad_Opcode }, | |
4990 | { Bad_Opcode }, | |
4991 | { Bad_Opcode }, | |
4992 | { Bad_Opcode }, | |
4993 | { Bad_Opcode }, | |
4994 | { Bad_Opcode }, | |
4995 | { Bad_Opcode }, | |
f88c9eb0 | 4996 | /* d8 */ |
592d1631 L |
4997 | { Bad_Opcode }, |
4998 | { Bad_Opcode }, | |
4999 | { Bad_Opcode }, | |
5000 | { Bad_Opcode }, | |
5001 | { Bad_Opcode }, | |
5002 | { Bad_Opcode }, | |
5003 | { Bad_Opcode }, | |
7531c613 | 5004 | { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
f88c9eb0 | 5005 | /* e0 */ |
592d1631 L |
5006 | { Bad_Opcode }, |
5007 | { Bad_Opcode }, | |
5008 | { Bad_Opcode }, | |
5009 | { Bad_Opcode }, | |
5010 | { Bad_Opcode }, | |
592d1631 L |
5011 | { Bad_Opcode }, |
5012 | { Bad_Opcode }, | |
5013 | { Bad_Opcode }, | |
85f10a01 | 5014 | /* e8 */ |
592d1631 L |
5015 | { Bad_Opcode }, |
5016 | { Bad_Opcode }, | |
5017 | { Bad_Opcode }, | |
5018 | { Bad_Opcode }, | |
5019 | { Bad_Opcode }, | |
5020 | { Bad_Opcode }, | |
5021 | { Bad_Opcode }, | |
5022 | { Bad_Opcode }, | |
85f10a01 | 5023 | /* f0 */ |
c1fa250a | 5024 | { PREFIX_TABLE (PREFIX_0F3A0F) }, |
592d1631 L |
5025 | { Bad_Opcode }, |
5026 | { Bad_Opcode }, | |
5027 | { Bad_Opcode }, | |
5028 | { Bad_Opcode }, | |
5029 | { Bad_Opcode }, | |
5030 | { Bad_Opcode }, | |
5031 | { Bad_Opcode }, | |
85f10a01 | 5032 | /* f8 */ |
592d1631 L |
5033 | { Bad_Opcode }, |
5034 | { Bad_Opcode }, | |
5035 | { Bad_Opcode }, | |
5036 | { Bad_Opcode }, | |
5037 | { Bad_Opcode }, | |
5038 | { Bad_Opcode }, | |
5039 | { Bad_Opcode }, | |
5040 | { Bad_Opcode }, | |
85f10a01 | 5041 | }, |
f88c9eb0 SP |
5042 | }; |
5043 | ||
5044 | static const struct dis386 xop_table[][256] = { | |
5dd85c99 | 5045 | /* XOP_08 */ |
85f10a01 MM |
5046 | { |
5047 | /* 00 */ | |
592d1631 L |
5048 | { Bad_Opcode }, |
5049 | { Bad_Opcode }, | |
5050 | { Bad_Opcode }, | |
5051 | { Bad_Opcode }, | |
5052 | { Bad_Opcode }, | |
5053 | { Bad_Opcode }, | |
5054 | { Bad_Opcode }, | |
5055 | { Bad_Opcode }, | |
85f10a01 | 5056 | /* 08 */ |
592d1631 L |
5057 | { Bad_Opcode }, |
5058 | { Bad_Opcode }, | |
5059 | { Bad_Opcode }, | |
5060 | { Bad_Opcode }, | |
5061 | { Bad_Opcode }, | |
5062 | { Bad_Opcode }, | |
5063 | { Bad_Opcode }, | |
5064 | { Bad_Opcode }, | |
85f10a01 | 5065 | /* 10 */ |
3929df09 | 5066 | { Bad_Opcode }, |
592d1631 L |
5067 | { Bad_Opcode }, |
5068 | { Bad_Opcode }, | |
5069 | { Bad_Opcode }, | |
5070 | { Bad_Opcode }, | |
5071 | { Bad_Opcode }, | |
5072 | { Bad_Opcode }, | |
5073 | { Bad_Opcode }, | |
85f10a01 | 5074 | /* 18 */ |
592d1631 L |
5075 | { Bad_Opcode }, |
5076 | { Bad_Opcode }, | |
5077 | { Bad_Opcode }, | |
5078 | { Bad_Opcode }, | |
5079 | { Bad_Opcode }, | |
5080 | { Bad_Opcode }, | |
5081 | { Bad_Opcode }, | |
5082 | { Bad_Opcode }, | |
85f10a01 | 5083 | /* 20 */ |
592d1631 L |
5084 | { Bad_Opcode }, |
5085 | { Bad_Opcode }, | |
5086 | { Bad_Opcode }, | |
5087 | { Bad_Opcode }, | |
5088 | { Bad_Opcode }, | |
5089 | { Bad_Opcode }, | |
5090 | { Bad_Opcode }, | |
5091 | { Bad_Opcode }, | |
85f10a01 | 5092 | /* 28 */ |
592d1631 L |
5093 | { Bad_Opcode }, |
5094 | { Bad_Opcode }, | |
5095 | { Bad_Opcode }, | |
5096 | { Bad_Opcode }, | |
5097 | { Bad_Opcode }, | |
5098 | { Bad_Opcode }, | |
5099 | { Bad_Opcode }, | |
5100 | { Bad_Opcode }, | |
c0f3af97 | 5101 | /* 30 */ |
592d1631 L |
5102 | { Bad_Opcode }, |
5103 | { Bad_Opcode }, | |
5104 | { Bad_Opcode }, | |
5105 | { Bad_Opcode }, | |
5106 | { Bad_Opcode }, | |
5107 | { Bad_Opcode }, | |
5108 | { Bad_Opcode }, | |
5109 | { Bad_Opcode }, | |
c0f3af97 | 5110 | /* 38 */ |
592d1631 L |
5111 | { Bad_Opcode }, |
5112 | { Bad_Opcode }, | |
5113 | { Bad_Opcode }, | |
5114 | { Bad_Opcode }, | |
5115 | { Bad_Opcode }, | |
5116 | { Bad_Opcode }, | |
5117 | { Bad_Opcode }, | |
5118 | { Bad_Opcode }, | |
c0f3af97 | 5119 | /* 40 */ |
592d1631 L |
5120 | { Bad_Opcode }, |
5121 | { Bad_Opcode }, | |
5122 | { Bad_Opcode }, | |
5123 | { Bad_Opcode }, | |
5124 | { Bad_Opcode }, | |
5125 | { Bad_Opcode }, | |
5126 | { Bad_Opcode }, | |
5127 | { Bad_Opcode }, | |
85f10a01 | 5128 | /* 48 */ |
592d1631 L |
5129 | { Bad_Opcode }, |
5130 | { Bad_Opcode }, | |
5131 | { Bad_Opcode }, | |
5132 | { Bad_Opcode }, | |
5133 | { Bad_Opcode }, | |
5134 | { Bad_Opcode }, | |
5135 | { Bad_Opcode }, | |
5136 | { Bad_Opcode }, | |
c0f3af97 | 5137 | /* 50 */ |
592d1631 L |
5138 | { Bad_Opcode }, |
5139 | { Bad_Opcode }, | |
5140 | { Bad_Opcode }, | |
5141 | { Bad_Opcode }, | |
5142 | { Bad_Opcode }, | |
5143 | { Bad_Opcode }, | |
5144 | { Bad_Opcode }, | |
5145 | { Bad_Opcode }, | |
85f10a01 | 5146 | /* 58 */ |
592d1631 L |
5147 | { Bad_Opcode }, |
5148 | { Bad_Opcode }, | |
5149 | { Bad_Opcode }, | |
5150 | { Bad_Opcode }, | |
5151 | { Bad_Opcode }, | |
5152 | { Bad_Opcode }, | |
5153 | { Bad_Opcode }, | |
5154 | { Bad_Opcode }, | |
c1e679ec | 5155 | /* 60 */ |
592d1631 L |
5156 | { Bad_Opcode }, |
5157 | { Bad_Opcode }, | |
5158 | { Bad_Opcode }, | |
5159 | { Bad_Opcode }, | |
5160 | { Bad_Opcode }, | |
5161 | { Bad_Opcode }, | |
5162 | { Bad_Opcode }, | |
5163 | { Bad_Opcode }, | |
c0f3af97 | 5164 | /* 68 */ |
592d1631 L |
5165 | { Bad_Opcode }, |
5166 | { Bad_Opcode }, | |
5167 | { Bad_Opcode }, | |
5168 | { Bad_Opcode }, | |
5169 | { Bad_Opcode }, | |
5170 | { Bad_Opcode }, | |
5171 | { Bad_Opcode }, | |
5172 | { Bad_Opcode }, | |
85f10a01 | 5173 | /* 70 */ |
592d1631 L |
5174 | { Bad_Opcode }, |
5175 | { Bad_Opcode }, | |
5176 | { Bad_Opcode }, | |
5177 | { Bad_Opcode }, | |
5178 | { Bad_Opcode }, | |
5179 | { Bad_Opcode }, | |
5180 | { Bad_Opcode }, | |
5181 | { Bad_Opcode }, | |
85f10a01 | 5182 | /* 78 */ |
592d1631 L |
5183 | { Bad_Opcode }, |
5184 | { Bad_Opcode }, | |
5185 | { Bad_Opcode }, | |
5186 | { Bad_Opcode }, | |
5187 | { Bad_Opcode }, | |
5188 | { Bad_Opcode }, | |
5189 | { Bad_Opcode }, | |
5190 | { Bad_Opcode }, | |
85f10a01 | 5191 | /* 80 */ |
592d1631 L |
5192 | { Bad_Opcode }, |
5193 | { Bad_Opcode }, | |
5194 | { Bad_Opcode }, | |
5195 | { Bad_Opcode }, | |
5196 | { Bad_Opcode }, | |
b5c37946 SJ |
5197 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) }, |
5198 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) }, | |
5199 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) }, | |
5dd85c99 | 5200 | /* 88 */ |
592d1631 L |
5201 | { Bad_Opcode }, |
5202 | { Bad_Opcode }, | |
5203 | { Bad_Opcode }, | |
5204 | { Bad_Opcode }, | |
5205 | { Bad_Opcode }, | |
5206 | { Bad_Opcode }, | |
b5c37946 SJ |
5207 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) }, |
5208 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) }, | |
5dd85c99 | 5209 | /* 90 */ |
592d1631 L |
5210 | { Bad_Opcode }, |
5211 | { Bad_Opcode }, | |
5212 | { Bad_Opcode }, | |
5213 | { Bad_Opcode }, | |
5214 | { Bad_Opcode }, | |
b5c37946 SJ |
5215 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) }, |
5216 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) }, | |
5217 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) }, | |
5dd85c99 | 5218 | /* 98 */ |
592d1631 L |
5219 | { Bad_Opcode }, |
5220 | { Bad_Opcode }, | |
5221 | { Bad_Opcode }, | |
5222 | { Bad_Opcode }, | |
5223 | { Bad_Opcode }, | |
5224 | { Bad_Opcode }, | |
b5c37946 SJ |
5225 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) }, |
5226 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) }, | |
5dd85c99 | 5227 | /* a0 */ |
592d1631 L |
5228 | { Bad_Opcode }, |
5229 | { Bad_Opcode }, | |
b13b1bc0 | 5230 | { "vpcmov", { XM, Vex, EXx, XMVexI4 }, 0 }, |
b5c37946 | 5231 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) }, |
592d1631 L |
5232 | { Bad_Opcode }, |
5233 | { Bad_Opcode }, | |
b5c37946 | 5234 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) }, |
592d1631 | 5235 | { Bad_Opcode }, |
5dd85c99 | 5236 | /* a8 */ |
592d1631 L |
5237 | { Bad_Opcode }, |
5238 | { Bad_Opcode }, | |
5239 | { Bad_Opcode }, | |
5240 | { Bad_Opcode }, | |
5241 | { Bad_Opcode }, | |
5242 | { Bad_Opcode }, | |
5243 | { Bad_Opcode }, | |
5244 | { Bad_Opcode }, | |
5dd85c99 | 5245 | /* b0 */ |
592d1631 L |
5246 | { Bad_Opcode }, |
5247 | { Bad_Opcode }, | |
5248 | { Bad_Opcode }, | |
5249 | { Bad_Opcode }, | |
5250 | { Bad_Opcode }, | |
5251 | { Bad_Opcode }, | |
b5c37946 | 5252 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) }, |
592d1631 | 5253 | { Bad_Opcode }, |
5dd85c99 | 5254 | /* b8 */ |
592d1631 L |
5255 | { Bad_Opcode }, |
5256 | { Bad_Opcode }, | |
5257 | { Bad_Opcode }, | |
5258 | { Bad_Opcode }, | |
5259 | { Bad_Opcode }, | |
5260 | { Bad_Opcode }, | |
5261 | { Bad_Opcode }, | |
5262 | { Bad_Opcode }, | |
5dd85c99 | 5263 | /* c0 */ |
b5c37946 SJ |
5264 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) }, |
5265 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) }, | |
5266 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) }, | |
5267 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) }, | |
592d1631 L |
5268 | { Bad_Opcode }, |
5269 | { Bad_Opcode }, | |
5270 | { Bad_Opcode }, | |
5271 | { Bad_Opcode }, | |
5dd85c99 | 5272 | /* c8 */ |
592d1631 L |
5273 | { Bad_Opcode }, |
5274 | { Bad_Opcode }, | |
5275 | { Bad_Opcode }, | |
5276 | { Bad_Opcode }, | |
b5c37946 SJ |
5277 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) }, |
5278 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) }, | |
5279 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) }, | |
5280 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) }, | |
5dd85c99 | 5281 | /* d0 */ |
592d1631 L |
5282 | { Bad_Opcode }, |
5283 | { Bad_Opcode }, | |
5284 | { Bad_Opcode }, | |
5285 | { Bad_Opcode }, | |
5286 | { Bad_Opcode }, | |
5287 | { Bad_Opcode }, | |
5288 | { Bad_Opcode }, | |
5289 | { Bad_Opcode }, | |
5dd85c99 | 5290 | /* d8 */ |
592d1631 L |
5291 | { Bad_Opcode }, |
5292 | { Bad_Opcode }, | |
5293 | { Bad_Opcode }, | |
5294 | { Bad_Opcode }, | |
5295 | { Bad_Opcode }, | |
5296 | { Bad_Opcode }, | |
5297 | { Bad_Opcode }, | |
5298 | { Bad_Opcode }, | |
5dd85c99 | 5299 | /* e0 */ |
592d1631 L |
5300 | { Bad_Opcode }, |
5301 | { Bad_Opcode }, | |
5302 | { Bad_Opcode }, | |
5303 | { Bad_Opcode }, | |
5304 | { Bad_Opcode }, | |
5305 | { Bad_Opcode }, | |
5306 | { Bad_Opcode }, | |
5307 | { Bad_Opcode }, | |
5dd85c99 | 5308 | /* e8 */ |
592d1631 L |
5309 | { Bad_Opcode }, |
5310 | { Bad_Opcode }, | |
5311 | { Bad_Opcode }, | |
5312 | { Bad_Opcode }, | |
b5c37946 SJ |
5313 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) }, |
5314 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) }, | |
5315 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) }, | |
5316 | { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) }, | |
5dd85c99 | 5317 | /* f0 */ |
592d1631 L |
5318 | { Bad_Opcode }, |
5319 | { Bad_Opcode }, | |
5320 | { Bad_Opcode }, | |
5321 | { Bad_Opcode }, | |
5322 | { Bad_Opcode }, | |
5323 | { Bad_Opcode }, | |
5324 | { Bad_Opcode }, | |
5325 | { Bad_Opcode }, | |
5dd85c99 | 5326 | /* f8 */ |
592d1631 L |
5327 | { Bad_Opcode }, |
5328 | { Bad_Opcode }, | |
5329 | { Bad_Opcode }, | |
5330 | { Bad_Opcode }, | |
5331 | { Bad_Opcode }, | |
5332 | { Bad_Opcode }, | |
5333 | { Bad_Opcode }, | |
5334 | { Bad_Opcode }, | |
5dd85c99 SP |
5335 | }, |
5336 | /* XOP_09 */ | |
5337 | { | |
5338 | /* 00 */ | |
592d1631 | 5339 | { Bad_Opcode }, |
b5c37946 SJ |
5340 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) }, |
5341 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) }, | |
592d1631 L |
5342 | { Bad_Opcode }, |
5343 | { Bad_Opcode }, | |
5344 | { Bad_Opcode }, | |
5345 | { Bad_Opcode }, | |
5346 | { Bad_Opcode }, | |
5dd85c99 | 5347 | /* 08 */ |
592d1631 L |
5348 | { Bad_Opcode }, |
5349 | { Bad_Opcode }, | |
5350 | { Bad_Opcode }, | |
5351 | { Bad_Opcode }, | |
5352 | { Bad_Opcode }, | |
5353 | { Bad_Opcode }, | |
5354 | { Bad_Opcode }, | |
5355 | { Bad_Opcode }, | |
5dd85c99 | 5356 | /* 10 */ |
592d1631 L |
5357 | { Bad_Opcode }, |
5358 | { Bad_Opcode }, | |
b5c37946 | 5359 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) }, |
592d1631 L |
5360 | { Bad_Opcode }, |
5361 | { Bad_Opcode }, | |
5362 | { Bad_Opcode }, | |
5363 | { Bad_Opcode }, | |
5364 | { Bad_Opcode }, | |
5dd85c99 | 5365 | /* 18 */ |
592d1631 L |
5366 | { Bad_Opcode }, |
5367 | { Bad_Opcode }, | |
5368 | { Bad_Opcode }, | |
5369 | { Bad_Opcode }, | |
5370 | { Bad_Opcode }, | |
5371 | { Bad_Opcode }, | |
5372 | { Bad_Opcode }, | |
5373 | { Bad_Opcode }, | |
5dd85c99 | 5374 | /* 20 */ |
592d1631 L |
5375 | { Bad_Opcode }, |
5376 | { Bad_Opcode }, | |
5377 | { Bad_Opcode }, | |
5378 | { Bad_Opcode }, | |
5379 | { Bad_Opcode }, | |
5380 | { Bad_Opcode }, | |
5381 | { Bad_Opcode }, | |
5382 | { Bad_Opcode }, | |
5dd85c99 | 5383 | /* 28 */ |
592d1631 L |
5384 | { Bad_Opcode }, |
5385 | { Bad_Opcode }, | |
5386 | { Bad_Opcode }, | |
5387 | { Bad_Opcode }, | |
5388 | { Bad_Opcode }, | |
5389 | { Bad_Opcode }, | |
5390 | { Bad_Opcode }, | |
5391 | { Bad_Opcode }, | |
5dd85c99 | 5392 | /* 30 */ |
592d1631 L |
5393 | { Bad_Opcode }, |
5394 | { Bad_Opcode }, | |
5395 | { Bad_Opcode }, | |
5396 | { Bad_Opcode }, | |
5397 | { Bad_Opcode }, | |
5398 | { Bad_Opcode }, | |
5399 | { Bad_Opcode }, | |
5400 | { Bad_Opcode }, | |
5dd85c99 | 5401 | /* 38 */ |
592d1631 L |
5402 | { Bad_Opcode }, |
5403 | { Bad_Opcode }, | |
5404 | { Bad_Opcode }, | |
5405 | { Bad_Opcode }, | |
5406 | { Bad_Opcode }, | |
5407 | { Bad_Opcode }, | |
5408 | { Bad_Opcode }, | |
5409 | { Bad_Opcode }, | |
5dd85c99 | 5410 | /* 40 */ |
592d1631 L |
5411 | { Bad_Opcode }, |
5412 | { Bad_Opcode }, | |
5413 | { Bad_Opcode }, | |
5414 | { Bad_Opcode }, | |
5415 | { Bad_Opcode }, | |
5416 | { Bad_Opcode }, | |
5417 | { Bad_Opcode }, | |
5418 | { Bad_Opcode }, | |
5dd85c99 | 5419 | /* 48 */ |
592d1631 L |
5420 | { Bad_Opcode }, |
5421 | { Bad_Opcode }, | |
5422 | { Bad_Opcode }, | |
5423 | { Bad_Opcode }, | |
5424 | { Bad_Opcode }, | |
5425 | { Bad_Opcode }, | |
5426 | { Bad_Opcode }, | |
5427 | { Bad_Opcode }, | |
5dd85c99 | 5428 | /* 50 */ |
592d1631 L |
5429 | { Bad_Opcode }, |
5430 | { Bad_Opcode }, | |
5431 | { Bad_Opcode }, | |
5432 | { Bad_Opcode }, | |
5433 | { Bad_Opcode }, | |
5434 | { Bad_Opcode }, | |
5435 | { Bad_Opcode }, | |
5436 | { Bad_Opcode }, | |
5dd85c99 | 5437 | /* 58 */ |
592d1631 L |
5438 | { Bad_Opcode }, |
5439 | { Bad_Opcode }, | |
5440 | { Bad_Opcode }, | |
5441 | { Bad_Opcode }, | |
5442 | { Bad_Opcode }, | |
5443 | { Bad_Opcode }, | |
5444 | { Bad_Opcode }, | |
5445 | { Bad_Opcode }, | |
5dd85c99 | 5446 | /* 60 */ |
592d1631 L |
5447 | { Bad_Opcode }, |
5448 | { Bad_Opcode }, | |
5449 | { Bad_Opcode }, | |
5450 | { Bad_Opcode }, | |
5451 | { Bad_Opcode }, | |
5452 | { Bad_Opcode }, | |
5453 | { Bad_Opcode }, | |
5454 | { Bad_Opcode }, | |
5dd85c99 | 5455 | /* 68 */ |
592d1631 L |
5456 | { Bad_Opcode }, |
5457 | { Bad_Opcode }, | |
5458 | { Bad_Opcode }, | |
5459 | { Bad_Opcode }, | |
5460 | { Bad_Opcode }, | |
5461 | { Bad_Opcode }, | |
5462 | { Bad_Opcode }, | |
5463 | { Bad_Opcode }, | |
5dd85c99 | 5464 | /* 70 */ |
592d1631 L |
5465 | { Bad_Opcode }, |
5466 | { Bad_Opcode }, | |
5467 | { Bad_Opcode }, | |
5468 | { Bad_Opcode }, | |
5469 | { Bad_Opcode }, | |
5470 | { Bad_Opcode }, | |
5471 | { Bad_Opcode }, | |
5472 | { Bad_Opcode }, | |
5dd85c99 | 5473 | /* 78 */ |
592d1631 L |
5474 | { Bad_Opcode }, |
5475 | { Bad_Opcode }, | |
5476 | { Bad_Opcode }, | |
5477 | { Bad_Opcode }, | |
5478 | { Bad_Opcode }, | |
5479 | { Bad_Opcode }, | |
5480 | { Bad_Opcode }, | |
5481 | { Bad_Opcode }, | |
5dd85c99 | 5482 | /* 80 */ |
b5c37946 SJ |
5483 | { VEX_W_TABLE (VEX_W_XOP_09_80) }, |
5484 | { VEX_W_TABLE (VEX_W_XOP_09_81) }, | |
5485 | { VEX_W_TABLE (VEX_W_XOP_09_82) }, | |
5486 | { VEX_W_TABLE (VEX_W_XOP_09_83) }, | |
592d1631 L |
5487 | { Bad_Opcode }, |
5488 | { Bad_Opcode }, | |
5489 | { Bad_Opcode }, | |
5490 | { Bad_Opcode }, | |
5dd85c99 | 5491 | /* 88 */ |
592d1631 L |
5492 | { Bad_Opcode }, |
5493 | { Bad_Opcode }, | |
5494 | { Bad_Opcode }, | |
5495 | { Bad_Opcode }, | |
5496 | { Bad_Opcode }, | |
5497 | { Bad_Opcode }, | |
5498 | { Bad_Opcode }, | |
5499 | { Bad_Opcode }, | |
5dd85c99 | 5500 | /* 90 */ |
b5c37946 SJ |
5501 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) }, |
5502 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) }, | |
5503 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) }, | |
5504 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) }, | |
5505 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) }, | |
5506 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) }, | |
5507 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) }, | |
5508 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) }, | |
5dd85c99 | 5509 | /* 98 */ |
b5c37946 SJ |
5510 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) }, |
5511 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) }, | |
5512 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) }, | |
5513 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) }, | |
592d1631 L |
5514 | { Bad_Opcode }, |
5515 | { Bad_Opcode }, | |
5516 | { Bad_Opcode }, | |
5517 | { Bad_Opcode }, | |
5dd85c99 | 5518 | /* a0 */ |
592d1631 L |
5519 | { Bad_Opcode }, |
5520 | { Bad_Opcode }, | |
5521 | { Bad_Opcode }, | |
5522 | { Bad_Opcode }, | |
5523 | { Bad_Opcode }, | |
5524 | { Bad_Opcode }, | |
5525 | { Bad_Opcode }, | |
5526 | { Bad_Opcode }, | |
5dd85c99 | 5527 | /* a8 */ |
592d1631 L |
5528 | { Bad_Opcode }, |
5529 | { Bad_Opcode }, | |
5530 | { Bad_Opcode }, | |
5531 | { Bad_Opcode }, | |
5532 | { Bad_Opcode }, | |
5533 | { Bad_Opcode }, | |
5534 | { Bad_Opcode }, | |
5535 | { Bad_Opcode }, | |
5dd85c99 | 5536 | /* b0 */ |
592d1631 L |
5537 | { Bad_Opcode }, |
5538 | { Bad_Opcode }, | |
5539 | { Bad_Opcode }, | |
5540 | { Bad_Opcode }, | |
5541 | { Bad_Opcode }, | |
5542 | { Bad_Opcode }, | |
5543 | { Bad_Opcode }, | |
5544 | { Bad_Opcode }, | |
5dd85c99 | 5545 | /* b8 */ |
592d1631 L |
5546 | { Bad_Opcode }, |
5547 | { Bad_Opcode }, | |
5548 | { Bad_Opcode }, | |
5549 | { Bad_Opcode }, | |
5550 | { Bad_Opcode }, | |
5551 | { Bad_Opcode }, | |
5552 | { Bad_Opcode }, | |
5553 | { Bad_Opcode }, | |
5dd85c99 | 5554 | /* c0 */ |
592d1631 | 5555 | { Bad_Opcode }, |
b5c37946 SJ |
5556 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) }, |
5557 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) }, | |
5558 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) }, | |
592d1631 L |
5559 | { Bad_Opcode }, |
5560 | { Bad_Opcode }, | |
b5c37946 SJ |
5561 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) }, |
5562 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) }, | |
5dd85c99 | 5563 | /* c8 */ |
592d1631 L |
5564 | { Bad_Opcode }, |
5565 | { Bad_Opcode }, | |
5566 | { Bad_Opcode }, | |
b5c37946 | 5567 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) }, |
592d1631 L |
5568 | { Bad_Opcode }, |
5569 | { Bad_Opcode }, | |
5570 | { Bad_Opcode }, | |
5571 | { Bad_Opcode }, | |
5dd85c99 | 5572 | /* d0 */ |
592d1631 | 5573 | { Bad_Opcode }, |
b5c37946 SJ |
5574 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) }, |
5575 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) }, | |
5576 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) }, | |
592d1631 L |
5577 | { Bad_Opcode }, |
5578 | { Bad_Opcode }, | |
b5c37946 SJ |
5579 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) }, |
5580 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) }, | |
5dd85c99 | 5581 | /* d8 */ |
592d1631 L |
5582 | { Bad_Opcode }, |
5583 | { Bad_Opcode }, | |
5584 | { Bad_Opcode }, | |
b5c37946 | 5585 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) }, |
592d1631 L |
5586 | { Bad_Opcode }, |
5587 | { Bad_Opcode }, | |
5588 | { Bad_Opcode }, | |
5589 | { Bad_Opcode }, | |
5dd85c99 | 5590 | /* e0 */ |
592d1631 | 5591 | { Bad_Opcode }, |
b5c37946 SJ |
5592 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) }, |
5593 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) }, | |
5594 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) }, | |
592d1631 L |
5595 | { Bad_Opcode }, |
5596 | { Bad_Opcode }, | |
5597 | { Bad_Opcode }, | |
5598 | { Bad_Opcode }, | |
4e7d34a6 | 5599 | /* e8 */ |
592d1631 L |
5600 | { Bad_Opcode }, |
5601 | { Bad_Opcode }, | |
5602 | { Bad_Opcode }, | |
5603 | { Bad_Opcode }, | |
5604 | { Bad_Opcode }, | |
5605 | { Bad_Opcode }, | |
5606 | { Bad_Opcode }, | |
5607 | { Bad_Opcode }, | |
4e7d34a6 | 5608 | /* f0 */ |
592d1631 L |
5609 | { Bad_Opcode }, |
5610 | { Bad_Opcode }, | |
5611 | { Bad_Opcode }, | |
5612 | { Bad_Opcode }, | |
5613 | { Bad_Opcode }, | |
5614 | { Bad_Opcode }, | |
5615 | { Bad_Opcode }, | |
5616 | { Bad_Opcode }, | |
4e7d34a6 | 5617 | /* f8 */ |
592d1631 L |
5618 | { Bad_Opcode }, |
5619 | { Bad_Opcode }, | |
5620 | { Bad_Opcode }, | |
5621 | { Bad_Opcode }, | |
5622 | { Bad_Opcode }, | |
5623 | { Bad_Opcode }, | |
5624 | { Bad_Opcode }, | |
5625 | { Bad_Opcode }, | |
4e7d34a6 | 5626 | }, |
f88c9eb0 | 5627 | /* XOP_0A */ |
4e7d34a6 L |
5628 | { |
5629 | /* 00 */ | |
592d1631 L |
5630 | { Bad_Opcode }, |
5631 | { Bad_Opcode }, | |
5632 | { Bad_Opcode }, | |
5633 | { Bad_Opcode }, | |
5634 | { Bad_Opcode }, | |
5635 | { Bad_Opcode }, | |
5636 | { Bad_Opcode }, | |
5637 | { Bad_Opcode }, | |
4e7d34a6 | 5638 | /* 08 */ |
592d1631 L |
5639 | { Bad_Opcode }, |
5640 | { Bad_Opcode }, | |
5641 | { Bad_Opcode }, | |
5642 | { Bad_Opcode }, | |
5643 | { Bad_Opcode }, | |
5644 | { Bad_Opcode }, | |
5645 | { Bad_Opcode }, | |
5646 | { Bad_Opcode }, | |
4e7d34a6 | 5647 | /* 10 */ |
c1dc7af5 | 5648 | { "bextrS", { Gdq, Edq, Id }, 0 }, |
592d1631 | 5649 | { Bad_Opcode }, |
b5c37946 | 5650 | { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) }, |
592d1631 L |
5651 | { Bad_Opcode }, |
5652 | { Bad_Opcode }, | |
5653 | { Bad_Opcode }, | |
5654 | { Bad_Opcode }, | |
5655 | { Bad_Opcode }, | |
4e7d34a6 | 5656 | /* 18 */ |
592d1631 L |
5657 | { Bad_Opcode }, |
5658 | { Bad_Opcode }, | |
5659 | { Bad_Opcode }, | |
5660 | { Bad_Opcode }, | |
5661 | { Bad_Opcode }, | |
5662 | { Bad_Opcode }, | |
5663 | { Bad_Opcode }, | |
5664 | { Bad_Opcode }, | |
4e7d34a6 | 5665 | /* 20 */ |
592d1631 L |
5666 | { Bad_Opcode }, |
5667 | { Bad_Opcode }, | |
5668 | { Bad_Opcode }, | |
5669 | { Bad_Opcode }, | |
5670 | { Bad_Opcode }, | |
5671 | { Bad_Opcode }, | |
5672 | { Bad_Opcode }, | |
5673 | { Bad_Opcode }, | |
4e7d34a6 | 5674 | /* 28 */ |
592d1631 L |
5675 | { Bad_Opcode }, |
5676 | { Bad_Opcode }, | |
5677 | { Bad_Opcode }, | |
5678 | { Bad_Opcode }, | |
5679 | { Bad_Opcode }, | |
5680 | { Bad_Opcode }, | |
5681 | { Bad_Opcode }, | |
5682 | { Bad_Opcode }, | |
4e7d34a6 | 5683 | /* 30 */ |
592d1631 L |
5684 | { Bad_Opcode }, |
5685 | { Bad_Opcode }, | |
5686 | { Bad_Opcode }, | |
5687 | { Bad_Opcode }, | |
5688 | { Bad_Opcode }, | |
5689 | { Bad_Opcode }, | |
5690 | { Bad_Opcode }, | |
5691 | { Bad_Opcode }, | |
c0f3af97 | 5692 | /* 38 */ |
592d1631 L |
5693 | { Bad_Opcode }, |
5694 | { Bad_Opcode }, | |
5695 | { Bad_Opcode }, | |
5696 | { Bad_Opcode }, | |
5697 | { Bad_Opcode }, | |
5698 | { Bad_Opcode }, | |
5699 | { Bad_Opcode }, | |
5700 | { Bad_Opcode }, | |
c0f3af97 | 5701 | /* 40 */ |
592d1631 L |
5702 | { Bad_Opcode }, |
5703 | { Bad_Opcode }, | |
5704 | { Bad_Opcode }, | |
5705 | { Bad_Opcode }, | |
5706 | { Bad_Opcode }, | |
5707 | { Bad_Opcode }, | |
5708 | { Bad_Opcode }, | |
5709 | { Bad_Opcode }, | |
c1e679ec | 5710 | /* 48 */ |
592d1631 L |
5711 | { Bad_Opcode }, |
5712 | { Bad_Opcode }, | |
5713 | { Bad_Opcode }, | |
5714 | { Bad_Opcode }, | |
5715 | { Bad_Opcode }, | |
5716 | { Bad_Opcode }, | |
5717 | { Bad_Opcode }, | |
5718 | { Bad_Opcode }, | |
c1e679ec | 5719 | /* 50 */ |
592d1631 L |
5720 | { Bad_Opcode }, |
5721 | { Bad_Opcode }, | |
5722 | { Bad_Opcode }, | |
5723 | { Bad_Opcode }, | |
5724 | { Bad_Opcode }, | |
5725 | { Bad_Opcode }, | |
5726 | { Bad_Opcode }, | |
5727 | { Bad_Opcode }, | |
4e7d34a6 | 5728 | /* 58 */ |
592d1631 L |
5729 | { Bad_Opcode }, |
5730 | { Bad_Opcode }, | |
5731 | { Bad_Opcode }, | |
5732 | { Bad_Opcode }, | |
5733 | { Bad_Opcode }, | |
5734 | { Bad_Opcode }, | |
5735 | { Bad_Opcode }, | |
5736 | { Bad_Opcode }, | |
4e7d34a6 | 5737 | /* 60 */ |
592d1631 L |
5738 | { Bad_Opcode }, |
5739 | { Bad_Opcode }, | |
5740 | { Bad_Opcode }, | |
5741 | { Bad_Opcode }, | |
5742 | { Bad_Opcode }, | |
5743 | { Bad_Opcode }, | |
5744 | { Bad_Opcode }, | |
5745 | { Bad_Opcode }, | |
4e7d34a6 | 5746 | /* 68 */ |
592d1631 L |
5747 | { Bad_Opcode }, |
5748 | { Bad_Opcode }, | |
5749 | { Bad_Opcode }, | |
5750 | { Bad_Opcode }, | |
5751 | { Bad_Opcode }, | |
5752 | { Bad_Opcode }, | |
5753 | { Bad_Opcode }, | |
5754 | { Bad_Opcode }, | |
4e7d34a6 | 5755 | /* 70 */ |
592d1631 L |
5756 | { Bad_Opcode }, |
5757 | { Bad_Opcode }, | |
5758 | { Bad_Opcode }, | |
5759 | { Bad_Opcode }, | |
5760 | { Bad_Opcode }, | |
5761 | { Bad_Opcode }, | |
5762 | { Bad_Opcode }, | |
5763 | { Bad_Opcode }, | |
4e7d34a6 | 5764 | /* 78 */ |
592d1631 L |
5765 | { Bad_Opcode }, |
5766 | { Bad_Opcode }, | |
5767 | { Bad_Opcode }, | |
5768 | { Bad_Opcode }, | |
5769 | { Bad_Opcode }, | |
5770 | { Bad_Opcode }, | |
5771 | { Bad_Opcode }, | |
5772 | { Bad_Opcode }, | |
4e7d34a6 | 5773 | /* 80 */ |
592d1631 L |
5774 | { Bad_Opcode }, |
5775 | { Bad_Opcode }, | |
5776 | { Bad_Opcode }, | |
5777 | { Bad_Opcode }, | |
5778 | { Bad_Opcode }, | |
5779 | { Bad_Opcode }, | |
5780 | { Bad_Opcode }, | |
5781 | { Bad_Opcode }, | |
4e7d34a6 | 5782 | /* 88 */ |
592d1631 L |
5783 | { Bad_Opcode }, |
5784 | { Bad_Opcode }, | |
5785 | { Bad_Opcode }, | |
5786 | { Bad_Opcode }, | |
5787 | { Bad_Opcode }, | |
5788 | { Bad_Opcode }, | |
5789 | { Bad_Opcode }, | |
5790 | { Bad_Opcode }, | |
4e7d34a6 | 5791 | /* 90 */ |
592d1631 L |
5792 | { Bad_Opcode }, |
5793 | { Bad_Opcode }, | |
5794 | { Bad_Opcode }, | |
5795 | { Bad_Opcode }, | |
5796 | { Bad_Opcode }, | |
5797 | { Bad_Opcode }, | |
5798 | { Bad_Opcode }, | |
5799 | { Bad_Opcode }, | |
4e7d34a6 | 5800 | /* 98 */ |
592d1631 L |
5801 | { Bad_Opcode }, |
5802 | { Bad_Opcode }, | |
5803 | { Bad_Opcode }, | |
5804 | { Bad_Opcode }, | |
5805 | { Bad_Opcode }, | |
5806 | { Bad_Opcode }, | |
5807 | { Bad_Opcode }, | |
5808 | { Bad_Opcode }, | |
4e7d34a6 | 5809 | /* a0 */ |
592d1631 L |
5810 | { Bad_Opcode }, |
5811 | { Bad_Opcode }, | |
5812 | { Bad_Opcode }, | |
5813 | { Bad_Opcode }, | |
5814 | { Bad_Opcode }, | |
5815 | { Bad_Opcode }, | |
5816 | { Bad_Opcode }, | |
5817 | { Bad_Opcode }, | |
4e7d34a6 | 5818 | /* a8 */ |
592d1631 L |
5819 | { Bad_Opcode }, |
5820 | { Bad_Opcode }, | |
5821 | { Bad_Opcode }, | |
5822 | { Bad_Opcode }, | |
5823 | { Bad_Opcode }, | |
5824 | { Bad_Opcode }, | |
5825 | { Bad_Opcode }, | |
5826 | { Bad_Opcode }, | |
d5d7db8e | 5827 | /* b0 */ |
592d1631 L |
5828 | { Bad_Opcode }, |
5829 | { Bad_Opcode }, | |
5830 | { Bad_Opcode }, | |
5831 | { Bad_Opcode }, | |
5832 | { Bad_Opcode }, | |
5833 | { Bad_Opcode }, | |
5834 | { Bad_Opcode }, | |
5835 | { Bad_Opcode }, | |
85f10a01 | 5836 | /* b8 */ |
592d1631 L |
5837 | { Bad_Opcode }, |
5838 | { Bad_Opcode }, | |
5839 | { Bad_Opcode }, | |
5840 | { Bad_Opcode }, | |
5841 | { Bad_Opcode }, | |
5842 | { Bad_Opcode }, | |
5843 | { Bad_Opcode }, | |
5844 | { Bad_Opcode }, | |
85f10a01 | 5845 | /* c0 */ |
592d1631 L |
5846 | { Bad_Opcode }, |
5847 | { Bad_Opcode }, | |
5848 | { Bad_Opcode }, | |
5849 | { Bad_Opcode }, | |
5850 | { Bad_Opcode }, | |
5851 | { Bad_Opcode }, | |
5852 | { Bad_Opcode }, | |
5853 | { Bad_Opcode }, | |
85f10a01 | 5854 | /* c8 */ |
592d1631 L |
5855 | { Bad_Opcode }, |
5856 | { Bad_Opcode }, | |
5857 | { Bad_Opcode }, | |
5858 | { Bad_Opcode }, | |
5859 | { Bad_Opcode }, | |
5860 | { Bad_Opcode }, | |
5861 | { Bad_Opcode }, | |
5862 | { Bad_Opcode }, | |
85f10a01 | 5863 | /* d0 */ |
592d1631 L |
5864 | { Bad_Opcode }, |
5865 | { Bad_Opcode }, | |
5866 | { Bad_Opcode }, | |
5867 | { Bad_Opcode }, | |
5868 | { Bad_Opcode }, | |
5869 | { Bad_Opcode }, | |
5870 | { Bad_Opcode }, | |
5871 | { Bad_Opcode }, | |
85f10a01 | 5872 | /* d8 */ |
592d1631 L |
5873 | { Bad_Opcode }, |
5874 | { Bad_Opcode }, | |
5875 | { Bad_Opcode }, | |
5876 | { Bad_Opcode }, | |
5877 | { Bad_Opcode }, | |
5878 | { Bad_Opcode }, | |
5879 | { Bad_Opcode }, | |
5880 | { Bad_Opcode }, | |
85f10a01 | 5881 | /* e0 */ |
592d1631 L |
5882 | { Bad_Opcode }, |
5883 | { Bad_Opcode }, | |
5884 | { Bad_Opcode }, | |
5885 | { Bad_Opcode }, | |
5886 | { Bad_Opcode }, | |
5887 | { Bad_Opcode }, | |
5888 | { Bad_Opcode }, | |
5889 | { Bad_Opcode }, | |
85f10a01 | 5890 | /* e8 */ |
592d1631 L |
5891 | { Bad_Opcode }, |
5892 | { Bad_Opcode }, | |
5893 | { Bad_Opcode }, | |
5894 | { Bad_Opcode }, | |
5895 | { Bad_Opcode }, | |
5896 | { Bad_Opcode }, | |
5897 | { Bad_Opcode }, | |
5898 | { Bad_Opcode }, | |
85f10a01 | 5899 | /* f0 */ |
592d1631 L |
5900 | { Bad_Opcode }, |
5901 | { Bad_Opcode }, | |
5902 | { Bad_Opcode }, | |
5903 | { Bad_Opcode }, | |
5904 | { Bad_Opcode }, | |
5905 | { Bad_Opcode }, | |
5906 | { Bad_Opcode }, | |
5907 | { Bad_Opcode }, | |
85f10a01 | 5908 | /* f8 */ |
592d1631 L |
5909 | { Bad_Opcode }, |
5910 | { Bad_Opcode }, | |
5911 | { Bad_Opcode }, | |
5912 | { Bad_Opcode }, | |
5913 | { Bad_Opcode }, | |
5914 | { Bad_Opcode }, | |
5915 | { Bad_Opcode }, | |
5916 | { Bad_Opcode }, | |
85f10a01 | 5917 | }, |
c0f3af97 L |
5918 | }; |
5919 | ||
5920 | static const struct dis386 vex_table[][256] = { | |
5921 | /* VEX_0F */ | |
85f10a01 MM |
5922 | { |
5923 | /* 00 */ | |
592d1631 L |
5924 | { Bad_Opcode }, |
5925 | { Bad_Opcode }, | |
5926 | { Bad_Opcode }, | |
5927 | { Bad_Opcode }, | |
5928 | { Bad_Opcode }, | |
5929 | { Bad_Opcode }, | |
5930 | { Bad_Opcode }, | |
5931 | { Bad_Opcode }, | |
85f10a01 | 5932 | /* 08 */ |
592d1631 L |
5933 | { Bad_Opcode }, |
5934 | { Bad_Opcode }, | |
5935 | { Bad_Opcode }, | |
5936 | { Bad_Opcode }, | |
5937 | { Bad_Opcode }, | |
5938 | { Bad_Opcode }, | |
5939 | { Bad_Opcode }, | |
5940 | { Bad_Opcode }, | |
c0f3af97 | 5941 | /* 10 */ |
b5c37946 SJ |
5942 | { PREFIX_TABLE (PREFIX_0F10) }, |
5943 | { PREFIX_TABLE (PREFIX_0F11) }, | |
592a252b | 5944 | { PREFIX_TABLE (PREFIX_VEX_0F12) }, |
b5c37946 | 5945 | { VEX_LEN_TABLE (VEX_LEN_0F13) }, |
bf926894 JB |
5946 | { "vunpcklpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
5947 | { "vunpckhpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
592a252b | 5948 | { PREFIX_TABLE (PREFIX_VEX_0F16) }, |
b5c37946 | 5949 | { VEX_LEN_TABLE (VEX_LEN_0F17) }, |
c0f3af97 | 5950 | /* 18 */ |
592d1631 L |
5951 | { Bad_Opcode }, |
5952 | { Bad_Opcode }, | |
5953 | { Bad_Opcode }, | |
5954 | { Bad_Opcode }, | |
5955 | { Bad_Opcode }, | |
5956 | { Bad_Opcode }, | |
5957 | { Bad_Opcode }, | |
5958 | { Bad_Opcode }, | |
c0f3af97 | 5959 | /* 20 */ |
592d1631 L |
5960 | { Bad_Opcode }, |
5961 | { Bad_Opcode }, | |
5962 | { Bad_Opcode }, | |
5963 | { Bad_Opcode }, | |
5964 | { Bad_Opcode }, | |
5965 | { Bad_Opcode }, | |
5966 | { Bad_Opcode }, | |
5967 | { Bad_Opcode }, | |
c0f3af97 | 5968 | /* 28 */ |
bf926894 JB |
5969 | { "vmovapX", { XM, EXx }, PREFIX_OPCODE }, |
5970 | { "vmovapX", { EXxS, XM }, PREFIX_OPCODE }, | |
592a252b | 5971 | { PREFIX_TABLE (PREFIX_VEX_0F2A) }, |
b5c37946 | 5972 | { "vmovntpX", { Mx, XM }, PREFIX_OPCODE }, |
592a252b L |
5973 | { PREFIX_TABLE (PREFIX_VEX_0F2C) }, |
5974 | { PREFIX_TABLE (PREFIX_VEX_0F2D) }, | |
b5c37946 SJ |
5975 | { PREFIX_TABLE (PREFIX_0F2E) }, |
5976 | { PREFIX_TABLE (PREFIX_0F2F) }, | |
85f10a01 | 5977 | /* 30 */ |
592d1631 L |
5978 | { Bad_Opcode }, |
5979 | { Bad_Opcode }, | |
5980 | { Bad_Opcode }, | |
5981 | { Bad_Opcode }, | |
5982 | { Bad_Opcode }, | |
5983 | { Bad_Opcode }, | |
5984 | { Bad_Opcode }, | |
5985 | { Bad_Opcode }, | |
4e7d34a6 | 5986 | /* 38 */ |
592d1631 L |
5987 | { Bad_Opcode }, |
5988 | { Bad_Opcode }, | |
5989 | { Bad_Opcode }, | |
5990 | { Bad_Opcode }, | |
5991 | { Bad_Opcode }, | |
5992 | { Bad_Opcode }, | |
5993 | { Bad_Opcode }, | |
5994 | { Bad_Opcode }, | |
d5d7db8e | 5995 | /* 40 */ |
592d1631 | 5996 | { Bad_Opcode }, |
13954a31 JB |
5997 | { VEX_LEN_TABLE (VEX_LEN_0F41) }, |
5998 | { VEX_LEN_TABLE (VEX_LEN_0F42) }, | |
592d1631 | 5999 | { Bad_Opcode }, |
13954a31 JB |
6000 | { VEX_LEN_TABLE (VEX_LEN_0F44) }, |
6001 | { VEX_LEN_TABLE (VEX_LEN_0F45) }, | |
6002 | { VEX_LEN_TABLE (VEX_LEN_0F46) }, | |
6003 | { VEX_LEN_TABLE (VEX_LEN_0F47) }, | |
85f10a01 | 6004 | /* 48 */ |
592d1631 L |
6005 | { Bad_Opcode }, |
6006 | { Bad_Opcode }, | |
13954a31 JB |
6007 | { VEX_LEN_TABLE (VEX_LEN_0F4A) }, |
6008 | { VEX_LEN_TABLE (VEX_LEN_0F4B) }, | |
592d1631 L |
6009 | { Bad_Opcode }, |
6010 | { Bad_Opcode }, | |
6011 | { Bad_Opcode }, | |
6012 | { Bad_Opcode }, | |
d5d7db8e | 6013 | /* 50 */ |
b5c37946 SJ |
6014 | { "vmovmskpX", { Gdq, Ux }, PREFIX_OPCODE }, |
6015 | { PREFIX_TABLE (PREFIX_0F51) }, | |
6016 | { PREFIX_TABLE (PREFIX_0F52) }, | |
6017 | { PREFIX_TABLE (PREFIX_0F53) }, | |
bf926894 JB |
6018 | { "vandpX", { XM, Vex, EXx }, PREFIX_OPCODE }, |
6019 | { "vandnpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
6020 | { "vorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
6021 | { "vxorpX", { XM, Vex, EXx }, PREFIX_OPCODE }, | |
c0f3af97 | 6022 | /* 58 */ |
b5c37946 SJ |
6023 | { PREFIX_TABLE (PREFIX_0F58) }, |
6024 | { PREFIX_TABLE (PREFIX_0F59) }, | |
6025 | { PREFIX_TABLE (PREFIX_0F5A) }, | |
6026 | { PREFIX_TABLE (PREFIX_0F5B) }, | |
6027 | { PREFIX_TABLE (PREFIX_0F5C) }, | |
6028 | { PREFIX_TABLE (PREFIX_0F5D) }, | |
6029 | { PREFIX_TABLE (PREFIX_0F5E) }, | |
6030 | { PREFIX_TABLE (PREFIX_0F5F) }, | |
c0f3af97 | 6031 | /* 60 */ |
7531c613 JB |
6032 | { "vpunpcklbw", { XM, Vex, EXx }, PREFIX_DATA }, |
6033 | { "vpunpcklwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6034 | { "vpunpckldq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6035 | { "vpacksswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6036 | { "vpcmpgtb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6037 | { "vpcmpgtw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6038 | { "vpcmpgtd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6039 | { "vpackuswb", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6040 | /* 68 */ |
7531c613 JB |
6041 | { "vpunpckhbw", { XM, Vex, EXx }, PREFIX_DATA }, |
6042 | { "vpunpckhwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6043 | { "vpunpckhdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6044 | { "vpackssdw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6045 | { "vpunpcklqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6046 | { "vpunpckhqdq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6047 | { VEX_LEN_TABLE (VEX_LEN_0F6E) }, | |
592a252b | 6048 | { PREFIX_TABLE (PREFIX_VEX_0F6F) }, |
c0f3af97 | 6049 | /* 70 */ |
592a252b | 6050 | { PREFIX_TABLE (PREFIX_VEX_0F70) }, |
b5c37946 SJ |
6051 | { REG_TABLE (REG_VEX_0F71) }, |
6052 | { REG_TABLE (REG_VEX_0F72) }, | |
6053 | { REG_TABLE (REG_VEX_0F73) }, | |
7531c613 JB |
6054 | { "vpcmpeqb", { XM, Vex, EXx }, PREFIX_DATA }, |
6055 | { "vpcmpeqw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6056 | { "vpcmpeqd", { XM, Vex, EXx }, PREFIX_DATA }, | |
035e7389 | 6057 | { VEX_LEN_TABLE (VEX_LEN_0F77) }, |
c0f3af97 | 6058 | /* 78 */ |
592d1631 L |
6059 | { Bad_Opcode }, |
6060 | { Bad_Opcode }, | |
6061 | { Bad_Opcode }, | |
6062 | { Bad_Opcode }, | |
b5c37946 SJ |
6063 | { PREFIX_TABLE (PREFIX_0F7C) }, |
6064 | { PREFIX_TABLE (PREFIX_0F7D) }, | |
592a252b L |
6065 | { PREFIX_TABLE (PREFIX_VEX_0F7E) }, |
6066 | { PREFIX_TABLE (PREFIX_VEX_0F7F) }, | |
c0f3af97 | 6067 | /* 80 */ |
592d1631 L |
6068 | { Bad_Opcode }, |
6069 | { Bad_Opcode }, | |
6070 | { Bad_Opcode }, | |
6071 | { Bad_Opcode }, | |
6072 | { Bad_Opcode }, | |
6073 | { Bad_Opcode }, | |
6074 | { Bad_Opcode }, | |
6075 | { Bad_Opcode }, | |
c0f3af97 | 6076 | /* 88 */ |
592d1631 L |
6077 | { Bad_Opcode }, |
6078 | { Bad_Opcode }, | |
6079 | { Bad_Opcode }, | |
6080 | { Bad_Opcode }, | |
6081 | { Bad_Opcode }, | |
6082 | { Bad_Opcode }, | |
6083 | { Bad_Opcode }, | |
6084 | { Bad_Opcode }, | |
c0f3af97 | 6085 | /* 90 */ |
13954a31 JB |
6086 | { VEX_LEN_TABLE (VEX_LEN_0F90) }, |
6087 | { VEX_LEN_TABLE (VEX_LEN_0F91) }, | |
6088 | { VEX_LEN_TABLE (VEX_LEN_0F92) }, | |
6089 | { VEX_LEN_TABLE (VEX_LEN_0F93) }, | |
592d1631 L |
6090 | { Bad_Opcode }, |
6091 | { Bad_Opcode }, | |
6092 | { Bad_Opcode }, | |
6093 | { Bad_Opcode }, | |
c0f3af97 | 6094 | /* 98 */ |
13954a31 JB |
6095 | { VEX_LEN_TABLE (VEX_LEN_0F98) }, |
6096 | { VEX_LEN_TABLE (VEX_LEN_0F99) }, | |
592d1631 L |
6097 | { Bad_Opcode }, |
6098 | { Bad_Opcode }, | |
6099 | { Bad_Opcode }, | |
6100 | { Bad_Opcode }, | |
6101 | { Bad_Opcode }, | |
6102 | { Bad_Opcode }, | |
c0f3af97 | 6103 | /* a0 */ |
592d1631 L |
6104 | { Bad_Opcode }, |
6105 | { Bad_Opcode }, | |
6106 | { Bad_Opcode }, | |
6107 | { Bad_Opcode }, | |
6108 | { Bad_Opcode }, | |
6109 | { Bad_Opcode }, | |
6110 | { Bad_Opcode }, | |
6111 | { Bad_Opcode }, | |
c0f3af97 | 6112 | /* a8 */ |
592d1631 L |
6113 | { Bad_Opcode }, |
6114 | { Bad_Opcode }, | |
6115 | { Bad_Opcode }, | |
6116 | { Bad_Opcode }, | |
6117 | { Bad_Opcode }, | |
6118 | { Bad_Opcode }, | |
592a252b | 6119 | { REG_TABLE (REG_VEX_0FAE) }, |
592d1631 | 6120 | { Bad_Opcode }, |
c0f3af97 | 6121 | /* b0 */ |
592d1631 L |
6122 | { Bad_Opcode }, |
6123 | { Bad_Opcode }, | |
6124 | { Bad_Opcode }, | |
6125 | { Bad_Opcode }, | |
6126 | { Bad_Opcode }, | |
6127 | { Bad_Opcode }, | |
6128 | { Bad_Opcode }, | |
6129 | { Bad_Opcode }, | |
c0f3af97 | 6130 | /* b8 */ |
592d1631 L |
6131 | { Bad_Opcode }, |
6132 | { Bad_Opcode }, | |
6133 | { Bad_Opcode }, | |
6134 | { Bad_Opcode }, | |
6135 | { Bad_Opcode }, | |
6136 | { Bad_Opcode }, | |
6137 | { Bad_Opcode }, | |
6138 | { Bad_Opcode }, | |
c0f3af97 | 6139 | /* c0 */ |
592d1631 L |
6140 | { Bad_Opcode }, |
6141 | { Bad_Opcode }, | |
b5c37946 | 6142 | { PREFIX_TABLE (PREFIX_0FC2) }, |
592d1631 | 6143 | { Bad_Opcode }, |
7531c613 | 6144 | { VEX_LEN_TABLE (VEX_LEN_0FC4) }, |
b5c37946 | 6145 | { "vpextrw", { Gd, Uxmm, Ib }, PREFIX_DATA }, |
bf926894 | 6146 | { "vshufpX", { XM, Vex, EXx, Ib }, PREFIX_OPCODE }, |
592d1631 | 6147 | { Bad_Opcode }, |
c0f3af97 | 6148 | /* c8 */ |
592d1631 L |
6149 | { Bad_Opcode }, |
6150 | { Bad_Opcode }, | |
6151 | { Bad_Opcode }, | |
6152 | { Bad_Opcode }, | |
6153 | { Bad_Opcode }, | |
6154 | { Bad_Opcode }, | |
6155 | { Bad_Opcode }, | |
6156 | { Bad_Opcode }, | |
c0f3af97 | 6157 | /* d0 */ |
b5c37946 | 6158 | { PREFIX_TABLE (PREFIX_0FD0) }, |
7531c613 JB |
6159 | { "vpsrlw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
6160 | { "vpsrld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6161 | { "vpsrlq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6162 | { "vpaddq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6163 | { "vpmullw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6164 | { VEX_LEN_TABLE (VEX_LEN_0FD6) }, | |
b5c37946 | 6165 | { "vpmovmskb", { Gdq, Ux }, PREFIX_DATA }, |
c0f3af97 | 6166 | /* d8 */ |
7531c613 JB |
6167 | { "vpsubusb", { XM, Vex, EXx }, PREFIX_DATA }, |
6168 | { "vpsubusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6169 | { "vpminub", { XM, Vex, EXx }, PREFIX_DATA }, | |
6170 | { "vpand", { XM, Vex, EXx }, PREFIX_DATA }, | |
6171 | { "vpaddusb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6172 | { "vpaddusw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6173 | { "vpmaxub", { XM, Vex, EXx }, PREFIX_DATA }, | |
6174 | { "vpandn", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6175 | /* e0 */ |
7531c613 JB |
6176 | { "vpavgb", { XM, Vex, EXx }, PREFIX_DATA }, |
6177 | { "vpsraw", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6178 | { "vpsrad", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6179 | { "vpavgw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6180 | { "vpmulhuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6181 | { "vpmulhw", { XM, Vex, EXx }, PREFIX_DATA }, | |
b5c37946 SJ |
6182 | { PREFIX_TABLE (PREFIX_0FE6) }, |
6183 | { "vmovntdq", { Mx, XM }, PREFIX_DATA }, | |
c0f3af97 | 6184 | /* e8 */ |
7531c613 JB |
6185 | { "vpsubsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6186 | { "vpsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6187 | { "vpminsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6188 | { "vpor", { XM, Vex, EXx }, PREFIX_DATA }, | |
6189 | { "vpaddsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6190 | { "vpaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6191 | { "vpmaxsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6192 | { "vpxor", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6193 | /* f0 */ |
b5c37946 | 6194 | { PREFIX_TABLE (PREFIX_0FF0) }, |
7531c613 JB |
6195 | { "vpsllw", { XM, Vex, EXxmm }, PREFIX_DATA }, |
6196 | { "vpslld", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6197 | { "vpsllq", { XM, Vex, EXxmm }, PREFIX_DATA }, | |
6198 | { "vpmuludq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6199 | { "vpmaddwd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6200 | { "vpsadbw", { XM, Vex, EXx }, PREFIX_DATA }, | |
b5c37946 | 6201 | { "vmaskmovdqu", { XM, Uxmm }, PREFIX_DATA }, |
c0f3af97 | 6202 | /* f8 */ |
7531c613 JB |
6203 | { "vpsubb", { XM, Vex, EXx }, PREFIX_DATA }, |
6204 | { "vpsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6205 | { "vpsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6206 | { "vpsubq", { XM, Vex, EXx }, PREFIX_DATA }, | |
6207 | { "vpaddb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6208 | { "vpaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6209 | { "vpaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
592d1631 | 6210 | { Bad_Opcode }, |
c0f3af97 L |
6211 | }, |
6212 | /* VEX_0F38 */ | |
6213 | { | |
6214 | /* 00 */ | |
7531c613 JB |
6215 | { "vpshufb", { XM, Vex, EXx }, PREFIX_DATA }, |
6216 | { "vphaddw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6217 | { "vphaddd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6218 | { "vphaddsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6219 | { "vpmaddubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6220 | { "vphsubw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6221 | { "vphsubd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6222 | { "vphsubsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6223 | /* 08 */ |
7531c613 JB |
6224 | { "vpsignb", { XM, Vex, EXx }, PREFIX_DATA }, |
6225 | { "vpsignw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6226 | { "vpsignd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6227 | { "vpmulhrsw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6228 | { VEX_W_TABLE (VEX_W_0F380C) }, | |
6229 | { VEX_W_TABLE (VEX_W_0F380D) }, | |
6230 | { VEX_W_TABLE (VEX_W_0F380E) }, | |
6231 | { VEX_W_TABLE (VEX_W_0F380F) }, | |
c0f3af97 | 6232 | /* 10 */ |
592d1631 L |
6233 | { Bad_Opcode }, |
6234 | { Bad_Opcode }, | |
6235 | { Bad_Opcode }, | |
7531c613 | 6236 | { VEX_W_TABLE (VEX_W_0F3813) }, |
592d1631 L |
6237 | { Bad_Opcode }, |
6238 | { Bad_Opcode }, | |
7531c613 JB |
6239 | { VEX_LEN_TABLE (VEX_LEN_0F3816) }, |
6240 | { "vptest", { XM, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6241 | /* 18 */ |
7531c613 JB |
6242 | { VEX_W_TABLE (VEX_W_0F3818) }, |
6243 | { VEX_LEN_TABLE (VEX_LEN_0F3819) }, | |
b5c37946 | 6244 | { VEX_LEN_TABLE (VEX_LEN_0F381A) }, |
592d1631 | 6245 | { Bad_Opcode }, |
7531c613 JB |
6246 | { "vpabsb", { XM, EXx }, PREFIX_DATA }, |
6247 | { "vpabsw", { XM, EXx }, PREFIX_DATA }, | |
6248 | { "vpabsd", { XM, EXx }, PREFIX_DATA }, | |
592d1631 | 6249 | { Bad_Opcode }, |
c0f3af97 | 6250 | /* 20 */ |
7531c613 JB |
6251 | { "vpmovsxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6252 | { "vpmovsxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6253 | { "vpmovsxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6254 | { "vpmovsxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6255 | { "vpmovsxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6256 | { "vpmovsxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
592d1631 L |
6257 | { Bad_Opcode }, |
6258 | { Bad_Opcode }, | |
c0f3af97 | 6259 | /* 28 */ |
7531c613 JB |
6260 | { "vpmuldq", { XM, Vex, EXx }, PREFIX_DATA }, |
6261 | { "vpcmpeqq", { XM, Vex, EXx }, PREFIX_DATA }, | |
b5c37946 | 6262 | { "vmovntdqa", { XM, Mx }, PREFIX_DATA }, |
7531c613 | 6263 | { "vpackusdw", { XM, Vex, EXx }, PREFIX_DATA }, |
b5c37946 SJ |
6264 | { VEX_W_TABLE (VEX_W_0F382C) }, |
6265 | { VEX_W_TABLE (VEX_W_0F382D) }, | |
6266 | { VEX_W_TABLE (VEX_W_0F382E) }, | |
6267 | { VEX_W_TABLE (VEX_W_0F382F) }, | |
c0f3af97 | 6268 | /* 30 */ |
7531c613 JB |
6269 | { "vpmovzxbw", { XM, EXxmmq }, PREFIX_DATA }, |
6270 | { "vpmovzxbd", { XM, EXxmmqd }, PREFIX_DATA }, | |
6271 | { "vpmovzxbq", { XM, EXxmmdw }, PREFIX_DATA }, | |
6272 | { "vpmovzxwd", { XM, EXxmmq }, PREFIX_DATA }, | |
6273 | { "vpmovzxwq", { XM, EXxmmqd }, PREFIX_DATA }, | |
6274 | { "vpmovzxdq", { XM, EXxmmq }, PREFIX_DATA }, | |
6275 | { VEX_LEN_TABLE (VEX_LEN_0F3836) }, | |
6276 | { "vpcmpgtq", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6277 | /* 38 */ |
7531c613 JB |
6278 | { "vpminsb", { XM, Vex, EXx }, PREFIX_DATA }, |
6279 | { "vpminsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6280 | { "vpminuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6281 | { "vpminud", { XM, Vex, EXx }, PREFIX_DATA }, | |
6282 | { "vpmaxsb", { XM, Vex, EXx }, PREFIX_DATA }, | |
6283 | { "vpmaxsd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6284 | { "vpmaxuw", { XM, Vex, EXx }, PREFIX_DATA }, | |
6285 | { "vpmaxud", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6286 | /* 40 */ |
7531c613 JB |
6287 | { "vpmulld", { XM, Vex, EXx }, PREFIX_DATA }, |
6288 | { VEX_LEN_TABLE (VEX_LEN_0F3841) }, | |
592d1631 L |
6289 | { Bad_Opcode }, |
6290 | { Bad_Opcode }, | |
6291 | { Bad_Opcode }, | |
7531c613 JB |
6292 | { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, |
6293 | { VEX_W_TABLE (VEX_W_0F3846) }, | |
6294 | { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6295 | /* 48 */ |
592d1631 | 6296 | { Bad_Opcode }, |
260cd341 | 6297 | { X86_64_TABLE (X86_64_VEX_0F3849) }, |
592d1631 | 6298 | { Bad_Opcode }, |
260cd341 | 6299 | { X86_64_TABLE (X86_64_VEX_0F384B) }, |
592d1631 L |
6300 | { Bad_Opcode }, |
6301 | { Bad_Opcode }, | |
6302 | { Bad_Opcode }, | |
6303 | { Bad_Opcode }, | |
c0f3af97 | 6304 | /* 50 */ |
58bf9b6a L |
6305 | { VEX_W_TABLE (VEX_W_0F3850) }, |
6306 | { VEX_W_TABLE (VEX_W_0F3851) }, | |
6307 | { VEX_W_TABLE (VEX_W_0F3852) }, | |
6308 | { VEX_W_TABLE (VEX_W_0F3853) }, | |
592d1631 L |
6309 | { Bad_Opcode }, |
6310 | { Bad_Opcode }, | |
6311 | { Bad_Opcode }, | |
6312 | { Bad_Opcode }, | |
c0f3af97 | 6313 | /* 58 */ |
7531c613 JB |
6314 | { VEX_W_TABLE (VEX_W_0F3858) }, |
6315 | { VEX_W_TABLE (VEX_W_0F3859) }, | |
b5c37946 | 6316 | { VEX_LEN_TABLE (VEX_LEN_0F385A) }, |
592d1631 | 6317 | { Bad_Opcode }, |
260cd341 | 6318 | { X86_64_TABLE (X86_64_VEX_0F385C) }, |
592d1631 | 6319 | { Bad_Opcode }, |
260cd341 | 6320 | { X86_64_TABLE (X86_64_VEX_0F385E) }, |
592d1631 | 6321 | { Bad_Opcode }, |
c0f3af97 | 6322 | /* 60 */ |
592d1631 L |
6323 | { Bad_Opcode }, |
6324 | { Bad_Opcode }, | |
6325 | { Bad_Opcode }, | |
6326 | { Bad_Opcode }, | |
6327 | { Bad_Opcode }, | |
6328 | { Bad_Opcode }, | |
6329 | { Bad_Opcode }, | |
6330 | { Bad_Opcode }, | |
c0f3af97 | 6331 | /* 68 */ |
592d1631 L |
6332 | { Bad_Opcode }, |
6333 | { Bad_Opcode }, | |
6334 | { Bad_Opcode }, | |
6335 | { Bad_Opcode }, | |
d100d8c1 | 6336 | { X86_64_TABLE (X86_64_VEX_0F386C) }, |
592d1631 L |
6337 | { Bad_Opcode }, |
6338 | { Bad_Opcode }, | |
6339 | { Bad_Opcode }, | |
c0f3af97 | 6340 | /* 70 */ |
592d1631 L |
6341 | { Bad_Opcode }, |
6342 | { Bad_Opcode }, | |
01d8ce74 | 6343 | { PREFIX_TABLE (PREFIX_VEX_0F3872) }, |
592d1631 L |
6344 | { Bad_Opcode }, |
6345 | { Bad_Opcode }, | |
6346 | { Bad_Opcode }, | |
6347 | { Bad_Opcode }, | |
6348 | { Bad_Opcode }, | |
c0f3af97 | 6349 | /* 78 */ |
7531c613 JB |
6350 | { VEX_W_TABLE (VEX_W_0F3878) }, |
6351 | { VEX_W_TABLE (VEX_W_0F3879) }, | |
592d1631 L |
6352 | { Bad_Opcode }, |
6353 | { Bad_Opcode }, | |
6354 | { Bad_Opcode }, | |
6355 | { Bad_Opcode }, | |
6356 | { Bad_Opcode }, | |
6357 | { Bad_Opcode }, | |
c0f3af97 | 6358 | /* 80 */ |
592d1631 L |
6359 | { Bad_Opcode }, |
6360 | { Bad_Opcode }, | |
6361 | { Bad_Opcode }, | |
6362 | { Bad_Opcode }, | |
6363 | { Bad_Opcode }, | |
6364 | { Bad_Opcode }, | |
6365 | { Bad_Opcode }, | |
6366 | { Bad_Opcode }, | |
c0f3af97 | 6367 | /* 88 */ |
592d1631 L |
6368 | { Bad_Opcode }, |
6369 | { Bad_Opcode }, | |
6370 | { Bad_Opcode }, | |
6371 | { Bad_Opcode }, | |
b5c37946 | 6372 | { "vpmaskmov%DQ", { XM, Vex, Mx }, PREFIX_DATA }, |
592d1631 | 6373 | { Bad_Opcode }, |
b5c37946 | 6374 | { "vpmaskmov%DQ", { Mx, Vex, XM }, PREFIX_DATA }, |
592d1631 | 6375 | { Bad_Opcode }, |
c0f3af97 | 6376 | /* 90 */ |
596a02ff | 6377 | { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA }, |
7531c613 | 6378 | { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, |
596a02ff | 6379 | { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA }, |
7531c613 | 6380 | { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA }, |
592d1631 L |
6381 | { Bad_Opcode }, |
6382 | { Bad_Opcode }, | |
7531c613 JB |
6383 | { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6384 | { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6385 | /* 98 */ |
7531c613 | 6386 | { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6387 | { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6388 | { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6389 | { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6390 | { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6391 | { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6392 | { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6393 | { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
c0f3af97 | 6394 | /* a0 */ |
592d1631 L |
6395 | { Bad_Opcode }, |
6396 | { Bad_Opcode }, | |
6397 | { Bad_Opcode }, | |
6398 | { Bad_Opcode }, | |
6399 | { Bad_Opcode }, | |
6400 | { Bad_Opcode }, | |
7531c613 JB |
6401 | { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6402 | { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6403 | /* a8 */ |
7531c613 | 6404 | { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6405 | { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6406 | { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6407 | { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6408 | { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6409 | { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6410 | { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6411 | { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
c0f3af97 | 6412 | /* b0 */ |
01d8ce74 | 6413 | { VEX_W_TABLE (VEX_W_0F38B0) }, |
6414 | { VEX_W_TABLE (VEX_W_0F38B1) }, | |
592d1631 L |
6415 | { Bad_Opcode }, |
6416 | { Bad_Opcode }, | |
4321af3e HW |
6417 | { VEX_W_TABLE (VEX_W_0F38B4) }, |
6418 | { VEX_W_TABLE (VEX_W_0F38B5) }, | |
7531c613 JB |
6419 | { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
6420 | { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6421 | /* b8 */ |
7531c613 | 6422 | { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6423 | { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6424 | { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6425 | { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6426 | { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6427 | { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
7531c613 | 6428 | { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA }, |
eb34d29b | 6429 | { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA }, |
c0f3af97 | 6430 | /* c0 */ |
592d1631 L |
6431 | { Bad_Opcode }, |
6432 | { Bad_Opcode }, | |
6433 | { Bad_Opcode }, | |
6434 | { Bad_Opcode }, | |
6435 | { Bad_Opcode }, | |
6436 | { Bad_Opcode }, | |
6437 | { Bad_Opcode }, | |
6438 | { Bad_Opcode }, | |
c0f3af97 | 6439 | /* c8 */ |
592d1631 L |
6440 | { Bad_Opcode }, |
6441 | { Bad_Opcode }, | |
6442 | { Bad_Opcode }, | |
b5c37946 SJ |
6443 | { PREFIX_TABLE (PREFIX_VEX_0F38CB) }, |
6444 | { PREFIX_TABLE (PREFIX_VEX_0F38CC) }, | |
6445 | { PREFIX_TABLE (PREFIX_VEX_0F38CD) }, | |
592d1631 | 6446 | { Bad_Opcode }, |
7531c613 | 6447 | { VEX_W_TABLE (VEX_W_0F38CF) }, |
c0f3af97 | 6448 | /* d0 */ |
592d1631 L |
6449 | { Bad_Opcode }, |
6450 | { Bad_Opcode }, | |
b5c37946 SJ |
6451 | { VEX_W_TABLE (VEX_W_0F38D2) }, |
6452 | { VEX_W_TABLE (VEX_W_0F38D3) }, | |
592d1631 L |
6453 | { Bad_Opcode }, |
6454 | { Bad_Opcode }, | |
6455 | { Bad_Opcode }, | |
6456 | { Bad_Opcode }, | |
c0f3af97 | 6457 | /* d8 */ |
592d1631 L |
6458 | { Bad_Opcode }, |
6459 | { Bad_Opcode }, | |
b5c37946 | 6460 | { VEX_W_TABLE (VEX_W_0F38DA) }, |
7531c613 JB |
6461 | { VEX_LEN_TABLE (VEX_LEN_0F38DB) }, |
6462 | { "vaesenc", { XM, Vex, EXx }, PREFIX_DATA }, | |
6463 | { "vaesenclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
6464 | { "vaesdec", { XM, Vex, EXx }, PREFIX_DATA }, | |
6465 | { "vaesdeclast", { XM, Vex, EXx }, PREFIX_DATA }, | |
c0f3af97 | 6466 | /* e0 */ |
a93e3234 HJ |
6467 | { X86_64_TABLE (X86_64_VEX_0F38E0) }, |
6468 | { X86_64_TABLE (X86_64_VEX_0F38E1) }, | |
6469 | { X86_64_TABLE (X86_64_VEX_0F38E2) }, | |
6470 | { X86_64_TABLE (X86_64_VEX_0F38E3) }, | |
6471 | { X86_64_TABLE (X86_64_VEX_0F38E4) }, | |
6472 | { X86_64_TABLE (X86_64_VEX_0F38E5) }, | |
6473 | { X86_64_TABLE (X86_64_VEX_0F38E6) }, | |
6474 | { X86_64_TABLE (X86_64_VEX_0F38E7) }, | |
c0f3af97 | 6475 | /* e8 */ |
a93e3234 HJ |
6476 | { X86_64_TABLE (X86_64_VEX_0F38E8) }, |
6477 | { X86_64_TABLE (X86_64_VEX_0F38E9) }, | |
6478 | { X86_64_TABLE (X86_64_VEX_0F38EA) }, | |
6479 | { X86_64_TABLE (X86_64_VEX_0F38EB) }, | |
6480 | { X86_64_TABLE (X86_64_VEX_0F38EC) }, | |
6481 | { X86_64_TABLE (X86_64_VEX_0F38ED) }, | |
6482 | { X86_64_TABLE (X86_64_VEX_0F38EE) }, | |
6483 | { X86_64_TABLE (X86_64_VEX_0F38EF) }, | |
c0f3af97 | 6484 | /* f0 */ |
592d1631 L |
6485 | { Bad_Opcode }, |
6486 | { Bad_Opcode }, | |
035e7389 | 6487 | { VEX_LEN_TABLE (VEX_LEN_0F38F2) }, |
14d10c6c | 6488 | { VEX_LEN_TABLE (VEX_LEN_0F38F3) }, |
592d1631 | 6489 | { Bad_Opcode }, |
14d10c6c JB |
6490 | { VEX_LEN_TABLE (VEX_LEN_0F38F5) }, |
6491 | { VEX_LEN_TABLE (VEX_LEN_0F38F6) }, | |
6492 | { VEX_LEN_TABLE (VEX_LEN_0F38F7) }, | |
c0f3af97 | 6493 | /* f8 */ |
592d1631 L |
6494 | { Bad_Opcode }, |
6495 | { Bad_Opcode }, | |
6496 | { Bad_Opcode }, | |
6497 | { Bad_Opcode }, | |
6498 | { Bad_Opcode }, | |
6499 | { Bad_Opcode }, | |
6500 | { Bad_Opcode }, | |
6501 | { Bad_Opcode }, | |
c0f3af97 L |
6502 | }, |
6503 | /* VEX_0F3A */ | |
6504 | { | |
6505 | /* 00 */ | |
7531c613 JB |
6506 | { VEX_LEN_TABLE (VEX_LEN_0F3A00) }, |
6507 | { VEX_LEN_TABLE (VEX_LEN_0F3A01) }, | |
6508 | { VEX_W_TABLE (VEX_W_0F3A02) }, | |
592d1631 | 6509 | { Bad_Opcode }, |
7531c613 JB |
6510 | { VEX_W_TABLE (VEX_W_0F3A04) }, |
6511 | { VEX_W_TABLE (VEX_W_0F3A05) }, | |
6512 | { VEX_LEN_TABLE (VEX_LEN_0F3A06) }, | |
592d1631 | 6513 | { Bad_Opcode }, |
c0f3af97 | 6514 | /* 08 */ |
7531c613 JB |
6515 | { "vroundps", { XM, EXx, Ib }, PREFIX_DATA }, |
6516 | { "vroundpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
c1d66d5f JB |
6517 | { "vroundss", { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA }, |
6518 | { "vroundsd", { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA }, | |
7531c613 JB |
6519 | { "vblendps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
6520 | { "vblendpd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6521 | { "vpblendw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6522 | { "vpalignr", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
c0f3af97 | 6523 | /* 10 */ |
592d1631 L |
6524 | { Bad_Opcode }, |
6525 | { Bad_Opcode }, | |
6526 | { Bad_Opcode }, | |
6527 | { Bad_Opcode }, | |
7531c613 JB |
6528 | { VEX_LEN_TABLE (VEX_LEN_0F3A14) }, |
6529 | { VEX_LEN_TABLE (VEX_LEN_0F3A15) }, | |
6530 | { VEX_LEN_TABLE (VEX_LEN_0F3A16) }, | |
6531 | { VEX_LEN_TABLE (VEX_LEN_0F3A17) }, | |
c0f3af97 | 6532 | /* 18 */ |
7531c613 JB |
6533 | { VEX_LEN_TABLE (VEX_LEN_0F3A18) }, |
6534 | { VEX_LEN_TABLE (VEX_LEN_0F3A19) }, | |
592d1631 L |
6535 | { Bad_Opcode }, |
6536 | { Bad_Opcode }, | |
6537 | { Bad_Opcode }, | |
7531c613 | 6538 | { VEX_W_TABLE (VEX_W_0F3A1D) }, |
592d1631 L |
6539 | { Bad_Opcode }, |
6540 | { Bad_Opcode }, | |
c0f3af97 | 6541 | /* 20 */ |
7531c613 JB |
6542 | { VEX_LEN_TABLE (VEX_LEN_0F3A20) }, |
6543 | { VEX_LEN_TABLE (VEX_LEN_0F3A21) }, | |
6544 | { VEX_LEN_TABLE (VEX_LEN_0F3A22) }, | |
592d1631 L |
6545 | { Bad_Opcode }, |
6546 | { Bad_Opcode }, | |
6547 | { Bad_Opcode }, | |
6548 | { Bad_Opcode }, | |
6549 | { Bad_Opcode }, | |
c0f3af97 | 6550 | /* 28 */ |
592d1631 L |
6551 | { Bad_Opcode }, |
6552 | { Bad_Opcode }, | |
6553 | { Bad_Opcode }, | |
6554 | { Bad_Opcode }, | |
6555 | { Bad_Opcode }, | |
6556 | { Bad_Opcode }, | |
6557 | { Bad_Opcode }, | |
6558 | { Bad_Opcode }, | |
c0f3af97 | 6559 | /* 30 */ |
7531c613 JB |
6560 | { VEX_LEN_TABLE (VEX_LEN_0F3A30) }, |
6561 | { VEX_LEN_TABLE (VEX_LEN_0F3A31) }, | |
6562 | { VEX_LEN_TABLE (VEX_LEN_0F3A32) }, | |
6563 | { VEX_LEN_TABLE (VEX_LEN_0F3A33) }, | |
592d1631 L |
6564 | { Bad_Opcode }, |
6565 | { Bad_Opcode }, | |
6566 | { Bad_Opcode }, | |
6567 | { Bad_Opcode }, | |
c0f3af97 | 6568 | /* 38 */ |
7531c613 JB |
6569 | { VEX_LEN_TABLE (VEX_LEN_0F3A38) }, |
6570 | { VEX_LEN_TABLE (VEX_LEN_0F3A39) }, | |
592d1631 L |
6571 | { Bad_Opcode }, |
6572 | { Bad_Opcode }, | |
6573 | { Bad_Opcode }, | |
6574 | { Bad_Opcode }, | |
6575 | { Bad_Opcode }, | |
6576 | { Bad_Opcode }, | |
c0f3af97 | 6577 | /* 40 */ |
7531c613 JB |
6578 | { "vdpps", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
6579 | { VEX_LEN_TABLE (VEX_LEN_0F3A41) }, | |
6580 | { "vmpsadbw", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
592d1631 | 6581 | { Bad_Opcode }, |
7531c613 | 6582 | { "vpclmulqdq", { XM, Vex, EXx, PCLMUL }, PREFIX_DATA }, |
592d1631 | 6583 | { Bad_Opcode }, |
7531c613 | 6584 | { VEX_LEN_TABLE (VEX_LEN_0F3A46) }, |
592d1631 | 6585 | { Bad_Opcode }, |
c0f3af97 | 6586 | /* 48 */ |
7531c613 JB |
6587 | { "vpermil2ps", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, |
6588 | { "vpermil2pd", { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA }, | |
6589 | { VEX_W_TABLE (VEX_W_0F3A4A) }, | |
6590 | { VEX_W_TABLE (VEX_W_0F3A4B) }, | |
6591 | { VEX_W_TABLE (VEX_W_0F3A4C) }, | |
592d1631 L |
6592 | { Bad_Opcode }, |
6593 | { Bad_Opcode }, | |
6594 | { Bad_Opcode }, | |
c0f3af97 | 6595 | /* 50 */ |
592d1631 L |
6596 | { Bad_Opcode }, |
6597 | { Bad_Opcode }, | |
6598 | { Bad_Opcode }, | |
6599 | { Bad_Opcode }, | |
6600 | { Bad_Opcode }, | |
6601 | { Bad_Opcode }, | |
6602 | { Bad_Opcode }, | |
6603 | { Bad_Opcode }, | |
c0f3af97 | 6604 | /* 58 */ |
592d1631 L |
6605 | { Bad_Opcode }, |
6606 | { Bad_Opcode }, | |
6607 | { Bad_Opcode }, | |
6608 | { Bad_Opcode }, | |
7531c613 JB |
6609 | { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6610 | { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6611 | { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
6612 | { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c0f3af97 | 6613 | /* 60 */ |
7531c613 JB |
6614 | { VEX_LEN_TABLE (VEX_LEN_0F3A60) }, |
6615 | { VEX_LEN_TABLE (VEX_LEN_0F3A61) }, | |
6616 | { VEX_LEN_TABLE (VEX_LEN_0F3A62) }, | |
6617 | { VEX_LEN_TABLE (VEX_LEN_0F3A63) }, | |
592d1631 L |
6618 | { Bad_Opcode }, |
6619 | { Bad_Opcode }, | |
6620 | { Bad_Opcode }, | |
6621 | { Bad_Opcode }, | |
c0f3af97 | 6622 | /* 68 */ |
7531c613 JB |
6623 | { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6624 | { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c1d66d5f JB |
6625 | { "vfmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, |
6626 | { "vfmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, | |
7531c613 JB |
6627 | { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6628 | { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c1d66d5f JB |
6629 | { "vfmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, |
6630 | { "vfmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6631 | /* 70 */ |
592d1631 L |
6632 | { Bad_Opcode }, |
6633 | { Bad_Opcode }, | |
6634 | { Bad_Opcode }, | |
6635 | { Bad_Opcode }, | |
6636 | { Bad_Opcode }, | |
6637 | { Bad_Opcode }, | |
6638 | { Bad_Opcode }, | |
6639 | { Bad_Opcode }, | |
c0f3af97 | 6640 | /* 78 */ |
7531c613 JB |
6641 | { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6642 | { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c1d66d5f JB |
6643 | { "vfnmaddss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, |
6644 | { "vfnmaddsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, | |
7531c613 JB |
6645 | { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, |
6646 | { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
c1d66d5f JB |
6647 | { "vfnmsubss", { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA }, |
6648 | { "vfnmsubsd", { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA }, | |
c0f3af97 | 6649 | /* 80 */ |
592d1631 L |
6650 | { Bad_Opcode }, |
6651 | { Bad_Opcode }, | |
6652 | { Bad_Opcode }, | |
6653 | { Bad_Opcode }, | |
6654 | { Bad_Opcode }, | |
6655 | { Bad_Opcode }, | |
6656 | { Bad_Opcode }, | |
6657 | { Bad_Opcode }, | |
c0f3af97 | 6658 | /* 88 */ |
592d1631 L |
6659 | { Bad_Opcode }, |
6660 | { Bad_Opcode }, | |
6661 | { Bad_Opcode }, | |
6662 | { Bad_Opcode }, | |
6663 | { Bad_Opcode }, | |
6664 | { Bad_Opcode }, | |
6665 | { Bad_Opcode }, | |
6666 | { Bad_Opcode }, | |
c0f3af97 | 6667 | /* 90 */ |
592d1631 L |
6668 | { Bad_Opcode }, |
6669 | { Bad_Opcode }, | |
6670 | { Bad_Opcode }, | |
6671 | { Bad_Opcode }, | |
6672 | { Bad_Opcode }, | |
6673 | { Bad_Opcode }, | |
6674 | { Bad_Opcode }, | |
6675 | { Bad_Opcode }, | |
c0f3af97 | 6676 | /* 98 */ |
592d1631 L |
6677 | { Bad_Opcode }, |
6678 | { Bad_Opcode }, | |
6679 | { Bad_Opcode }, | |
6680 | { Bad_Opcode }, | |
6681 | { Bad_Opcode }, | |
6682 | { Bad_Opcode }, | |
6683 | { Bad_Opcode }, | |
6684 | { Bad_Opcode }, | |
c0f3af97 | 6685 | /* a0 */ |
592d1631 L |
6686 | { Bad_Opcode }, |
6687 | { Bad_Opcode }, | |
6688 | { Bad_Opcode }, | |
6689 | { Bad_Opcode }, | |
6690 | { Bad_Opcode }, | |
6691 | { Bad_Opcode }, | |
6692 | { Bad_Opcode }, | |
6693 | { Bad_Opcode }, | |
c0f3af97 | 6694 | /* a8 */ |
592d1631 L |
6695 | { Bad_Opcode }, |
6696 | { Bad_Opcode }, | |
6697 | { Bad_Opcode }, | |
6698 | { Bad_Opcode }, | |
6699 | { Bad_Opcode }, | |
6700 | { Bad_Opcode }, | |
6701 | { Bad_Opcode }, | |
6702 | { Bad_Opcode }, | |
c0f3af97 | 6703 | /* b0 */ |
592d1631 L |
6704 | { Bad_Opcode }, |
6705 | { Bad_Opcode }, | |
6706 | { Bad_Opcode }, | |
6707 | { Bad_Opcode }, | |
6708 | { Bad_Opcode }, | |
6709 | { Bad_Opcode }, | |
6710 | { Bad_Opcode }, | |
6711 | { Bad_Opcode }, | |
c0f3af97 | 6712 | /* b8 */ |
592d1631 L |
6713 | { Bad_Opcode }, |
6714 | { Bad_Opcode }, | |
6715 | { Bad_Opcode }, | |
6716 | { Bad_Opcode }, | |
6717 | { Bad_Opcode }, | |
6718 | { Bad_Opcode }, | |
6719 | { Bad_Opcode }, | |
6720 | { Bad_Opcode }, | |
c0f3af97 | 6721 | /* c0 */ |
592d1631 L |
6722 | { Bad_Opcode }, |
6723 | { Bad_Opcode }, | |
6724 | { Bad_Opcode }, | |
6725 | { Bad_Opcode }, | |
6726 | { Bad_Opcode }, | |
6727 | { Bad_Opcode }, | |
6728 | { Bad_Opcode }, | |
6729 | { Bad_Opcode }, | |
c0f3af97 | 6730 | /* c8 */ |
592d1631 L |
6731 | { Bad_Opcode }, |
6732 | { Bad_Opcode }, | |
6733 | { Bad_Opcode }, | |
6734 | { Bad_Opcode }, | |
6735 | { Bad_Opcode }, | |
6736 | { Bad_Opcode }, | |
7531c613 JB |
6737 | { VEX_W_TABLE (VEX_W_0F3ACE) }, |
6738 | { VEX_W_TABLE (VEX_W_0F3ACF) }, | |
c0f3af97 | 6739 | /* d0 */ |
592d1631 L |
6740 | { Bad_Opcode }, |
6741 | { Bad_Opcode }, | |
6742 | { Bad_Opcode }, | |
6743 | { Bad_Opcode }, | |
6744 | { Bad_Opcode }, | |
6745 | { Bad_Opcode }, | |
6746 | { Bad_Opcode }, | |
6747 | { Bad_Opcode }, | |
c0f3af97 | 6748 | /* d8 */ |
592d1631 L |
6749 | { Bad_Opcode }, |
6750 | { Bad_Opcode }, | |
6751 | { Bad_Opcode }, | |
6752 | { Bad_Opcode }, | |
6753 | { Bad_Opcode }, | |
6754 | { Bad_Opcode }, | |
b5c37946 | 6755 | { VEX_W_TABLE (VEX_W_0F3ADE) }, |
7531c613 | 6756 | { VEX_LEN_TABLE (VEX_LEN_0F3ADF) }, |
c0f3af97 | 6757 | /* e0 */ |
592d1631 L |
6758 | { Bad_Opcode }, |
6759 | { Bad_Opcode }, | |
6760 | { Bad_Opcode }, | |
6761 | { Bad_Opcode }, | |
6762 | { Bad_Opcode }, | |
6763 | { Bad_Opcode }, | |
6764 | { Bad_Opcode }, | |
6765 | { Bad_Opcode }, | |
c0f3af97 | 6766 | /* e8 */ |
592d1631 L |
6767 | { Bad_Opcode }, |
6768 | { Bad_Opcode }, | |
6769 | { Bad_Opcode }, | |
6770 | { Bad_Opcode }, | |
6771 | { Bad_Opcode }, | |
6772 | { Bad_Opcode }, | |
6773 | { Bad_Opcode }, | |
6774 | { Bad_Opcode }, | |
c0f3af97 | 6775 | /* f0 */ |
14d10c6c | 6776 | { VEX_LEN_TABLE (VEX_LEN_0F3AF0) }, |
592d1631 L |
6777 | { Bad_Opcode }, |
6778 | { Bad_Opcode }, | |
6779 | { Bad_Opcode }, | |
6780 | { Bad_Opcode }, | |
6781 | { Bad_Opcode }, | |
6782 | { Bad_Opcode }, | |
6783 | { Bad_Opcode }, | |
c0f3af97 | 6784 | /* f8 */ |
592d1631 L |
6785 | { Bad_Opcode }, |
6786 | { Bad_Opcode }, | |
6787 | { Bad_Opcode }, | |
6788 | { Bad_Opcode }, | |
6789 | { Bad_Opcode }, | |
6790 | { Bad_Opcode }, | |
6791 | { Bad_Opcode }, | |
6792 | { Bad_Opcode }, | |
c0f3af97 L |
6793 | }, |
6794 | }; | |
6795 | ||
43234a1e | 6796 | #include "i386-dis-evex.h" |
ad692897 | 6797 | |
c0f3af97 | 6798 | static const struct dis386 vex_len_table[][2] = { |
b5c37946 | 6799 | /* VEX_LEN_0F12_P_0 */ |
c0f3af97 | 6800 | { |
b5c37946 | 6801 | { MOD_TABLE (MOD_0F12_PREFIX_0) }, |
c0f3af97 L |
6802 | }, |
6803 | ||
b5c37946 | 6804 | /* VEX_LEN_0F12_P_2 */ |
c0f3af97 | 6805 | { |
b5c37946 | 6806 | { "%XEVmovlpYX", { XM, Vex, Mq }, 0 }, |
c0f3af97 L |
6807 | }, |
6808 | ||
b5c37946 | 6809 | /* VEX_LEN_0F13 */ |
c0f3af97 | 6810 | { |
b5c37946 | 6811 | { "%XEVmovlpYX", { Mq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6812 | }, |
6813 | ||
b5c37946 | 6814 | /* VEX_LEN_0F16_P_0 */ |
c0f3af97 | 6815 | { |
b5c37946 | 6816 | { MOD_TABLE (MOD_0F16_PREFIX_0) }, |
c0f3af97 L |
6817 | }, |
6818 | ||
b5c37946 | 6819 | /* VEX_LEN_0F16_P_2 */ |
c0f3af97 | 6820 | { |
b5c37946 | 6821 | { "%XEVmovhpYX", { XM, Vex, Mq }, 0 }, |
c0f3af97 L |
6822 | }, |
6823 | ||
b5c37946 | 6824 | /* VEX_LEN_0F17 */ |
c0f3af97 | 6825 | { |
b5c37946 | 6826 | { "%XEVmovhpYX", { Mq, XM }, PREFIX_OPCODE }, |
c0f3af97 L |
6827 | }, |
6828 | ||
13954a31 | 6829 | /* VEX_LEN_0F41 */ |
43234a1e L |
6830 | { |
6831 | { Bad_Opcode }, | |
b5c37946 | 6832 | { VEX_W_TABLE (VEX_W_0F41_L_1) }, |
43234a1e | 6833 | }, |
13954a31 JB |
6834 | |
6835 | /* VEX_LEN_0F42 */ | |
1ba585e8 IT |
6836 | { |
6837 | { Bad_Opcode }, | |
b5c37946 | 6838 | { VEX_W_TABLE (VEX_W_0F42_L_1) }, |
1ba585e8 | 6839 | }, |
13954a31 JB |
6840 | |
6841 | /* VEX_LEN_0F44 */ | |
43234a1e | 6842 | { |
b5c37946 | 6843 | { VEX_W_TABLE (VEX_W_0F44_L_0) }, |
43234a1e | 6844 | }, |
13954a31 JB |
6845 | |
6846 | /* VEX_LEN_0F45 */ | |
1ba585e8 IT |
6847 | { |
6848 | { Bad_Opcode }, | |
b5c37946 | 6849 | { VEX_W_TABLE (VEX_W_0F45_L_1) }, |
1ba585e8 | 6850 | }, |
13954a31 JB |
6851 | |
6852 | /* VEX_LEN_0F46 */ | |
1ba585e8 IT |
6853 | { |
6854 | { Bad_Opcode }, | |
b5c37946 | 6855 | { VEX_W_TABLE (VEX_W_0F46_L_1) }, |
1ba585e8 | 6856 | }, |
13954a31 JB |
6857 | |
6858 | /* VEX_LEN_0F47 */ | |
1ba585e8 IT |
6859 | { |
6860 | { Bad_Opcode }, | |
b5c37946 | 6861 | { VEX_W_TABLE (VEX_W_0F47_L_1) }, |
1ba585e8 | 6862 | }, |
13954a31 JB |
6863 | |
6864 | /* VEX_LEN_0F4A */ | |
1ba585e8 IT |
6865 | { |
6866 | { Bad_Opcode }, | |
b5c37946 | 6867 | { VEX_W_TABLE (VEX_W_0F4A_L_1) }, |
1ba585e8 | 6868 | }, |
13954a31 JB |
6869 | |
6870 | /* VEX_LEN_0F4B */ | |
43234a1e L |
6871 | { |
6872 | { Bad_Opcode }, | |
b5c37946 | 6873 | { VEX_W_TABLE (VEX_W_0F4B_L_1) }, |
43234a1e L |
6874 | }, |
6875 | ||
7531c613 | 6876 | /* VEX_LEN_0F6E */ |
c0f3af97 | 6877 | { |
b5c37946 | 6878 | { "%XEvmovYK", { XMScalar, Edq }, PREFIX_DATA }, |
c0f3af97 L |
6879 | }, |
6880 | ||
035e7389 | 6881 | /* VEX_LEN_0F77 */ |
c0f3af97 | 6882 | { |
ec6f095a L |
6883 | { "vzeroupper", { XX }, 0 }, |
6884 | { "vzeroall", { XX }, 0 }, | |
c0f3af97 L |
6885 | }, |
6886 | ||
ec6f095a | 6887 | /* VEX_LEN_0F7E_P_1 */ |
c0f3af97 | 6888 | { |
b5c37946 | 6889 | { "%XEvmovqY", { XMScalar, EXq }, 0 }, |
c0f3af97 L |
6890 | }, |
6891 | ||
ec6f095a | 6892 | /* VEX_LEN_0F7E_P_2 */ |
c0f3af97 | 6893 | { |
f7cfcddd | 6894 | { "%XEvmovK", { Edq, XMScalar }, 0 }, |
c0f3af97 L |
6895 | }, |
6896 | ||
13954a31 | 6897 | /* VEX_LEN_0F90 */ |
c0f3af97 | 6898 | { |
13954a31 | 6899 | { VEX_W_TABLE (VEX_W_0F90_L_0) }, |
c0f3af97 L |
6900 | }, |
6901 | ||
13954a31 | 6902 | /* VEX_LEN_0F91 */ |
c0f3af97 | 6903 | { |
b5c37946 | 6904 | { VEX_W_TABLE (VEX_W_0F91_L_0) }, |
c0f3af97 L |
6905 | }, |
6906 | ||
13954a31 | 6907 | /* VEX_LEN_0F92 */ |
c0f3af97 | 6908 | { |
b5c37946 | 6909 | { VEX_W_TABLE (VEX_W_0F92_L_0) }, |
c0f3af97 L |
6910 | }, |
6911 | ||
13954a31 | 6912 | /* VEX_LEN_0F93 */ |
c0f3af97 | 6913 | { |
b5c37946 | 6914 | { VEX_W_TABLE (VEX_W_0F93_L_0) }, |
c0f3af97 L |
6915 | }, |
6916 | ||
13954a31 | 6917 | /* VEX_LEN_0F98 */ |
43234a1e | 6918 | { |
b5c37946 | 6919 | { VEX_W_TABLE (VEX_W_0F98_L_0) }, |
43234a1e L |
6920 | }, |
6921 | ||
13954a31 | 6922 | /* VEX_LEN_0F99 */ |
1ba585e8 | 6923 | { |
b5c37946 | 6924 | { VEX_W_TABLE (VEX_W_0F99_L_0) }, |
1ba585e8 IT |
6925 | }, |
6926 | ||
b5c37946 | 6927 | /* VEX_LEN_0FAE_R_2 */ |
c0f3af97 | 6928 | { |
ec6f095a | 6929 | { "vldmxcsr", { Md }, 0 }, |
c0f3af97 L |
6930 | }, |
6931 | ||
b5c37946 | 6932 | /* VEX_LEN_0FAE_R_3 */ |
c0f3af97 | 6933 | { |
ec6f095a | 6934 | { "vstmxcsr", { Md }, 0 }, |
c0f3af97 L |
6935 | }, |
6936 | ||
7531c613 | 6937 | /* VEX_LEN_0FC4 */ |
c0f3af97 | 6938 | { |
b5c37946 | 6939 | { "%XEvpinsrwY", { XM, Vex, Edw, Ib }, PREFIX_DATA }, |
c0f3af97 L |
6940 | }, |
6941 | ||
7531c613 | 6942 | /* VEX_LEN_0FD6 */ |
c0f3af97 | 6943 | { |
b5c37946 | 6944 | { "%XEvmovqY", { EXqS, XMScalar }, PREFIX_DATA }, |
c0f3af97 L |
6945 | }, |
6946 | ||
7531c613 | 6947 | /* VEX_LEN_0F3816 */ |
c0f3af97 | 6948 | { |
6c30d220 | 6949 | { Bad_Opcode }, |
7531c613 | 6950 | { VEX_W_TABLE (VEX_W_0F3816_L_1) }, |
c0f3af97 L |
6951 | }, |
6952 | ||
7531c613 | 6953 | /* VEX_LEN_0F3819 */ |
c0f3af97 | 6954 | { |
6c30d220 | 6955 | { Bad_Opcode }, |
7531c613 | 6956 | { VEX_W_TABLE (VEX_W_0F3819_L_1) }, |
c0f3af97 L |
6957 | }, |
6958 | ||
b5c37946 | 6959 | /* VEX_LEN_0F381A */ |
c0f3af97 | 6960 | { |
6c30d220 | 6961 | { Bad_Opcode }, |
b5c37946 | 6962 | { VEX_W_TABLE (VEX_W_0F381A_L_1) }, |
c0f3af97 L |
6963 | }, |
6964 | ||
7531c613 | 6965 | /* VEX_LEN_0F3836 */ |
c0f3af97 | 6966 | { |
6c30d220 | 6967 | { Bad_Opcode }, |
7531c613 | 6968 | { VEX_W_TABLE (VEX_W_0F3836) }, |
c0f3af97 L |
6969 | }, |
6970 | ||
7531c613 | 6971 | /* VEX_LEN_0F3841 */ |
c0f3af97 | 6972 | { |
7531c613 | 6973 | { "vphminposuw", { XM, EXx }, PREFIX_DATA }, |
c0f3af97 L |
6974 | }, |
6975 | ||
1f506c06 | 6976 | /* VEX_LEN_0F3849_X86_64 */ |
260cd341 | 6977 | { |
1f506c06 | 6978 | { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) }, |
260cd341 LC |
6979 | }, |
6980 | ||
1f506c06 | 6981 | /* VEX_LEN_0F384B_X86_64 */ |
260cd341 | 6982 | { |
1f506c06 | 6983 | { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) }, |
260cd341 LC |
6984 | }, |
6985 | ||
b5c37946 | 6986 | /* VEX_LEN_0F385A */ |
6c30d220 L |
6987 | { |
6988 | { Bad_Opcode }, | |
b5c37946 SJ |
6989 | { VEX_W_TABLE (VEX_W_0F385A_L_0) }, |
6990 | }, | |
6991 | ||
6992 | /* VEX_LEN_0F385C_X86_64 */ | |
6993 | { | |
6994 | { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) }, | |
260cd341 LC |
6995 | }, |
6996 | ||
b5c37946 | 6997 | /* VEX_LEN_0F385E_X86_64 */ |
260cd341 | 6998 | { |
b5c37946 SJ |
6999 | { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) }, |
7000 | }, | |
7001 | ||
7002 | /* VEX_LEN_0F386C_X86_64 */ | |
7003 | { | |
7004 | { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) }, | |
7005 | }, | |
7006 | ||
7007 | /* VEX_LEN_0F38CB_P_3_W_0 */ | |
7008 | { | |
7009 | { Bad_Opcode }, | |
7010 | { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 }, | |
7011 | }, | |
7012 | ||
7013 | /* VEX_LEN_0F38CC_P_3_W_0 */ | |
7014 | { | |
7015 | { Bad_Opcode }, | |
7016 | { "vsha512msg1", { XM, Rxmmq }, 0 }, | |
7017 | }, | |
7018 | ||
7019 | /* VEX_LEN_0F38CD_P_3_W_0 */ | |
7020 | { | |
7021 | { Bad_Opcode }, | |
7022 | { "vsha512msg2", { XM, Rymm }, 0 }, | |
3ac2eb94 HJ |
7023 | }, |
7024 | ||
b5c37946 | 7025 | /* VEX_LEN_0F38DA_W_0_P_0 */ |
c55ba32b | 7026 | { |
b5c37946 | 7027 | { "vsm3msg1", { XM, Vex, EXxmm }, 0 }, |
c55ba32b HJ |
7028 | }, |
7029 | ||
b5c37946 | 7030 | /* VEX_LEN_0F38DA_W_0_P_2 */ |
c55ba32b | 7031 | { |
b5c37946 | 7032 | { "vsm3msg2", { XM, Vex, EXxmm }, 0 }, |
c55ba32b HJ |
7033 | }, |
7034 | ||
7531c613 | 7035 | /* VEX_LEN_0F38DB */ |
a5ff0eb2 | 7036 | { |
7531c613 | 7037 | { "vaesimc", { XM, EXx }, PREFIX_DATA }, |
a5ff0eb2 L |
7038 | }, |
7039 | ||
035e7389 | 7040 | /* VEX_LEN_0F38F2 */ |
f12dc422 | 7041 | { |
035e7389 | 7042 | { "andnS", { Gdq, VexGdq, Edq }, PREFIX_OPCODE }, |
f12dc422 L |
7043 | }, |
7044 | ||
14d10c6c | 7045 | /* VEX_LEN_0F38F3 */ |
6c30d220 | 7046 | { |
14d10c6c | 7047 | { REG_TABLE(REG_VEX_0F38F3_L_0) }, |
6c30d220 L |
7048 | }, |
7049 | ||
14d10c6c | 7050 | /* VEX_LEN_0F38F5 */ |
f12dc422 | 7051 | { |
14d10c6c | 7052 | { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) }, |
f12dc422 L |
7053 | }, |
7054 | ||
14d10c6c | 7055 | /* VEX_LEN_0F38F6 */ |
6c30d220 | 7056 | { |
14d10c6c | 7057 | { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) }, |
6c30d220 L |
7058 | }, |
7059 | ||
14d10c6c | 7060 | /* VEX_LEN_0F38F7 */ |
6c30d220 | 7061 | { |
14d10c6c | 7062 | { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) }, |
6c30d220 L |
7063 | }, |
7064 | ||
7531c613 | 7065 | /* VEX_LEN_0F3A00 */ |
6c30d220 L |
7066 | { |
7067 | { Bad_Opcode }, | |
7531c613 | 7068 | { VEX_W_TABLE (VEX_W_0F3A00_L_1) }, |
6c30d220 L |
7069 | }, |
7070 | ||
7531c613 | 7071 | /* VEX_LEN_0F3A01 */ |
6c30d220 L |
7072 | { |
7073 | { Bad_Opcode }, | |
7531c613 | 7074 | { VEX_W_TABLE (VEX_W_0F3A01_L_1) }, |
6c30d220 L |
7075 | }, |
7076 | ||
7531c613 | 7077 | /* VEX_LEN_0F3A06 */ |
c0f3af97 | 7078 | { |
592d1631 | 7079 | { Bad_Opcode }, |
7531c613 | 7080 | { VEX_W_TABLE (VEX_W_0F3A06_L_1) }, |
c0f3af97 L |
7081 | }, |
7082 | ||
7531c613 | 7083 | /* VEX_LEN_0F3A14 */ |
c0f3af97 | 7084 | { |
f7cfcddd | 7085 | { "%XEvpextrb", { Edb, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7086 | }, |
7087 | ||
7531c613 | 7088 | /* VEX_LEN_0F3A15 */ |
c0f3af97 | 7089 | { |
f7cfcddd | 7090 | { "%XEvpextrw", { Edw, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7091 | }, |
7092 | ||
7531c613 | 7093 | /* VEX_LEN_0F3A16 */ |
c0f3af97 | 7094 | { |
f7cfcddd | 7095 | { "%XEvpextrK", { Edq, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7096 | }, |
7097 | ||
7531c613 | 7098 | /* VEX_LEN_0F3A17 */ |
c0f3af97 | 7099 | { |
f7cfcddd | 7100 | { "%XEvextractps", { Ed, XM, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7101 | }, |
7102 | ||
7531c613 | 7103 | /* VEX_LEN_0F3A18 */ |
c0f3af97 | 7104 | { |
592d1631 | 7105 | { Bad_Opcode }, |
7531c613 | 7106 | { VEX_W_TABLE (VEX_W_0F3A18_L_1) }, |
c0f3af97 L |
7107 | }, |
7108 | ||
7531c613 | 7109 | /* VEX_LEN_0F3A19 */ |
c0f3af97 | 7110 | { |
592d1631 | 7111 | { Bad_Opcode }, |
7531c613 | 7112 | { VEX_W_TABLE (VEX_W_0F3A19_L_1) }, |
c0f3af97 L |
7113 | }, |
7114 | ||
7531c613 | 7115 | /* VEX_LEN_0F3A20 */ |
c0f3af97 | 7116 | { |
b5c37946 | 7117 | { "%XEvpinsrbY", { XM, Vex, Edb, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7118 | }, |
7119 | ||
7531c613 | 7120 | /* VEX_LEN_0F3A21 */ |
c0f3af97 | 7121 | { |
b5c37946 | 7122 | { "%XEvinsertpsY", { XM, Vex, EXd, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7123 | }, |
7124 | ||
7531c613 | 7125 | /* VEX_LEN_0F3A22 */ |
c0f3af97 | 7126 | { |
b5c37946 | 7127 | { "%XEvpinsrYK", { XM, Vex, Edq, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7128 | }, |
7129 | ||
7531c613 | 7130 | /* VEX_LEN_0F3A30 */ |
43234a1e | 7131 | { |
b5c37946 | 7132 | { "kshiftr%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, |
43234a1e L |
7133 | }, |
7134 | ||
7531c613 | 7135 | /* VEX_LEN_0F3A31 */ |
1ba585e8 | 7136 | { |
b5c37946 | 7137 | { "kshiftr%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, |
1ba585e8 IT |
7138 | }, |
7139 | ||
7531c613 | 7140 | /* VEX_LEN_0F3A32 */ |
43234a1e | 7141 | { |
b5c37946 | 7142 | { "kshiftl%BW", { MaskG, MaskR, Ib }, PREFIX_DATA }, |
43234a1e L |
7143 | }, |
7144 | ||
7531c613 | 7145 | /* VEX_LEN_0F3A33 */ |
1ba585e8 | 7146 | { |
b5c37946 | 7147 | { "kshiftl%DQ", { MaskG, MaskR, Ib }, PREFIX_DATA }, |
1ba585e8 IT |
7148 | }, |
7149 | ||
7531c613 | 7150 | /* VEX_LEN_0F3A38 */ |
c0f3af97 | 7151 | { |
6c30d220 | 7152 | { Bad_Opcode }, |
7531c613 | 7153 | { VEX_W_TABLE (VEX_W_0F3A38_L_1) }, |
c0f3af97 L |
7154 | }, |
7155 | ||
7531c613 | 7156 | /* VEX_LEN_0F3A39 */ |
c0f3af97 | 7157 | { |
6c30d220 | 7158 | { Bad_Opcode }, |
7531c613 | 7159 | { VEX_W_TABLE (VEX_W_0F3A39_L_1) }, |
6c30d220 L |
7160 | }, |
7161 | ||
7531c613 | 7162 | /* VEX_LEN_0F3A41 */ |
6c30d220 | 7163 | { |
7531c613 | 7164 | { "vdppd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7165 | }, |
7166 | ||
7531c613 | 7167 | /* VEX_LEN_0F3A46 */ |
c0f3af97 | 7168 | { |
6c30d220 | 7169 | { Bad_Opcode }, |
7531c613 | 7170 | { VEX_W_TABLE (VEX_W_0F3A46_L_1) }, |
c0f3af97 L |
7171 | }, |
7172 | ||
7531c613 | 7173 | /* VEX_LEN_0F3A60 */ |
c0f3af97 | 7174 | { |
7531c613 | 7175 | { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7176 | }, |
7177 | ||
7531c613 | 7178 | /* VEX_LEN_0F3A61 */ |
c0f3af97 | 7179 | { |
7531c613 | 7180 | { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7181 | }, |
7182 | ||
7531c613 | 7183 | /* VEX_LEN_0F3A62 */ |
c0f3af97 | 7184 | { |
7531c613 | 7185 | { "vpcmpistrm", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7186 | }, |
7187 | ||
7531c613 | 7188 | /* VEX_LEN_0F3A63 */ |
c0f3af97 | 7189 | { |
7531c613 | 7190 | { "vpcmpistri", { XM, EXx, Ib }, PREFIX_DATA }, |
c0f3af97 L |
7191 | }, |
7192 | ||
b5c37946 SJ |
7193 | /* VEX_LEN_0F3ADE_W_0 */ |
7194 | { | |
7195 | { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
7196 | }, | |
7197 | ||
7531c613 | 7198 | /* VEX_LEN_0F3ADF */ |
a5ff0eb2 | 7199 | { |
7531c613 | 7200 | { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA }, |
a5ff0eb2 | 7201 | }, |
4c807e72 | 7202 | |
14d10c6c | 7203 | /* VEX_LEN_0F3AF0 */ |
6c30d220 | 7204 | { |
14d10c6c | 7205 | { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) }, |
6c30d220 L |
7206 | }, |
7207 | ||
b5c37946 | 7208 | /* VEX_LEN_XOP_08_85 */ |
467bbef0 | 7209 | { |
b5c37946 | 7210 | { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) }, |
467bbef0 JB |
7211 | }, |
7212 | ||
b5c37946 | 7213 | /* VEX_LEN_XOP_08_86 */ |
467bbef0 | 7214 | { |
b5c37946 | 7215 | { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) }, |
467bbef0 JB |
7216 | }, |
7217 | ||
b5c37946 | 7218 | /* VEX_LEN_XOP_08_87 */ |
467bbef0 | 7219 | { |
b5c37946 | 7220 | { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) }, |
467bbef0 JB |
7221 | }, |
7222 | ||
b5c37946 | 7223 | /* VEX_LEN_XOP_08_8E */ |
467bbef0 | 7224 | { |
b5c37946 | 7225 | { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) }, |
467bbef0 JB |
7226 | }, |
7227 | ||
b5c37946 | 7228 | /* VEX_LEN_XOP_08_8F */ |
467bbef0 | 7229 | { |
b5c37946 | 7230 | { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) }, |
467bbef0 JB |
7231 | }, |
7232 | ||
b5c37946 | 7233 | /* VEX_LEN_XOP_08_95 */ |
467bbef0 | 7234 | { |
b5c37946 | 7235 | { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) }, |
467bbef0 JB |
7236 | }, |
7237 | ||
b5c37946 | 7238 | /* VEX_LEN_XOP_08_96 */ |
467bbef0 | 7239 | { |
b5c37946 | 7240 | { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) }, |
467bbef0 JB |
7241 | }, |
7242 | ||
b5c37946 | 7243 | /* VEX_LEN_XOP_08_97 */ |
467bbef0 | 7244 | { |
b5c37946 | 7245 | { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) }, |
467bbef0 JB |
7246 | }, |
7247 | ||
b5c37946 | 7248 | /* VEX_LEN_XOP_08_9E */ |
467bbef0 | 7249 | { |
b5c37946 | 7250 | { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) }, |
467bbef0 JB |
7251 | }, |
7252 | ||
b5c37946 | 7253 | /* VEX_LEN_XOP_08_9F */ |
467bbef0 | 7254 | { |
b5c37946 | 7255 | { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) }, |
467bbef0 JB |
7256 | }, |
7257 | ||
b5c37946 | 7258 | /* VEX_LEN_XOP_08_A3 */ |
467bbef0 JB |
7259 | { |
7260 | { "vpperm", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7261 | }, | |
7262 | ||
b5c37946 | 7263 | /* VEX_LEN_XOP_08_A6 */ |
467bbef0 | 7264 | { |
b5c37946 | 7265 | { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) }, |
467bbef0 JB |
7266 | }, |
7267 | ||
b5c37946 | 7268 | /* VEX_LEN_XOP_08_B6 */ |
467bbef0 | 7269 | { |
b5c37946 | 7270 | { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) }, |
467bbef0 JB |
7271 | }, |
7272 | ||
b5c37946 | 7273 | /* VEX_LEN_XOP_08_C0 */ |
467bbef0 | 7274 | { |
b5c37946 | 7275 | { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) }, |
467bbef0 JB |
7276 | }, |
7277 | ||
b5c37946 | 7278 | /* VEX_LEN_XOP_08_C1 */ |
467bbef0 | 7279 | { |
b5c37946 | 7280 | { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) }, |
467bbef0 JB |
7281 | }, |
7282 | ||
b5c37946 | 7283 | /* VEX_LEN_XOP_08_C2 */ |
467bbef0 | 7284 | { |
b5c37946 | 7285 | { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) }, |
467bbef0 JB |
7286 | }, |
7287 | ||
b5c37946 | 7288 | /* VEX_LEN_XOP_08_C3 */ |
467bbef0 | 7289 | { |
b5c37946 | 7290 | { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) }, |
467bbef0 JB |
7291 | }, |
7292 | ||
b5c37946 | 7293 | /* VEX_LEN_XOP_08_CC */ |
ff688e1f | 7294 | { |
b5c37946 | 7295 | { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) }, |
ff688e1f L |
7296 | }, |
7297 | ||
b5c37946 | 7298 | /* VEX_LEN_XOP_08_CD */ |
ff688e1f | 7299 | { |
b5c37946 | 7300 | { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) }, |
ff688e1f L |
7301 | }, |
7302 | ||
b5c37946 | 7303 | /* VEX_LEN_XOP_08_CE */ |
ff688e1f | 7304 | { |
b5c37946 | 7305 | { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) }, |
ff688e1f L |
7306 | }, |
7307 | ||
b5c37946 | 7308 | /* VEX_LEN_XOP_08_CF */ |
ff688e1f | 7309 | { |
b5c37946 | 7310 | { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) }, |
ff688e1f L |
7311 | }, |
7312 | ||
b5c37946 | 7313 | /* VEX_LEN_XOP_08_EC */ |
ff688e1f | 7314 | { |
b5c37946 | 7315 | { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) }, |
ff688e1f L |
7316 | }, |
7317 | ||
b5c37946 | 7318 | /* VEX_LEN_XOP_08_ED */ |
ff688e1f | 7319 | { |
b5c37946 | 7320 | { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) }, |
ff688e1f L |
7321 | }, |
7322 | ||
b5c37946 | 7323 | /* VEX_LEN_XOP_08_EE */ |
ff688e1f | 7324 | { |
b5c37946 | 7325 | { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) }, |
ff688e1f L |
7326 | }, |
7327 | ||
b5c37946 | 7328 | /* VEX_LEN_XOP_08_EF */ |
ff688e1f | 7329 | { |
b5c37946 | 7330 | { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) }, |
467bbef0 JB |
7331 | }, |
7332 | ||
b5c37946 | 7333 | /* VEX_LEN_XOP_09_01 */ |
467bbef0 | 7334 | { |
32e31ad7 | 7335 | { REG_TABLE (REG_XOP_09_01_L_0) }, |
467bbef0 JB |
7336 | }, |
7337 | ||
b5c37946 | 7338 | /* VEX_LEN_XOP_09_02 */ |
467bbef0 | 7339 | { |
32e31ad7 | 7340 | { REG_TABLE (REG_XOP_09_02_L_0) }, |
467bbef0 JB |
7341 | }, |
7342 | ||
b5c37946 | 7343 | /* VEX_LEN_XOP_09_12 */ |
467bbef0 | 7344 | { |
b5c37946 | 7345 | { REG_TABLE (REG_XOP_09_12_L_0) }, |
ff688e1f L |
7346 | }, |
7347 | ||
b5c37946 | 7348 | /* VEX_LEN_XOP_09_82_W_0 */ |
5dd85c99 | 7349 | { |
b5b098c2 | 7350 | { "vfrczss", { XM, EXd }, 0 }, |
5dd85c99 | 7351 | }, |
4c807e72 | 7352 | |
b5c37946 | 7353 | /* VEX_LEN_XOP_09_83_W_0 */ |
5dd85c99 | 7354 | { |
b5b098c2 | 7355 | { "vfrczsd", { XM, EXq }, 0 }, |
5dd85c99 | 7356 | }, |
467bbef0 | 7357 | |
b5c37946 | 7358 | /* VEX_LEN_XOP_09_90 */ |
467bbef0 JB |
7359 | { |
7360 | { "vprotb", { XM, EXx, VexW }, 0 }, | |
7361 | }, | |
7362 | ||
b5c37946 | 7363 | /* VEX_LEN_XOP_09_91 */ |
467bbef0 JB |
7364 | { |
7365 | { "vprotw", { XM, EXx, VexW }, 0 }, | |
7366 | }, | |
7367 | ||
b5c37946 | 7368 | /* VEX_LEN_XOP_09_92 */ |
467bbef0 JB |
7369 | { |
7370 | { "vprotd", { XM, EXx, VexW }, 0 }, | |
7371 | }, | |
7372 | ||
b5c37946 | 7373 | /* VEX_LEN_XOP_09_93 */ |
467bbef0 JB |
7374 | { |
7375 | { "vprotq", { XM, EXx, VexW }, 0 }, | |
7376 | }, | |
7377 | ||
b5c37946 | 7378 | /* VEX_LEN_XOP_09_94 */ |
467bbef0 JB |
7379 | { |
7380 | { "vpshlb", { XM, EXx, VexW }, 0 }, | |
7381 | }, | |
7382 | ||
b5c37946 | 7383 | /* VEX_LEN_XOP_09_95 */ |
467bbef0 JB |
7384 | { |
7385 | { "vpshlw", { XM, EXx, VexW }, 0 }, | |
7386 | }, | |
7387 | ||
b5c37946 | 7388 | /* VEX_LEN_XOP_09_96 */ |
467bbef0 JB |
7389 | { |
7390 | { "vpshld", { XM, EXx, VexW }, 0 }, | |
7391 | }, | |
7392 | ||
b5c37946 | 7393 | /* VEX_LEN_XOP_09_97 */ |
467bbef0 JB |
7394 | { |
7395 | { "vpshlq", { XM, EXx, VexW }, 0 }, | |
7396 | }, | |
7397 | ||
b5c37946 | 7398 | /* VEX_LEN_XOP_09_98 */ |
467bbef0 JB |
7399 | { |
7400 | { "vpshab", { XM, EXx, VexW }, 0 }, | |
7401 | }, | |
7402 | ||
b5c37946 | 7403 | /* VEX_LEN_XOP_09_99 */ |
467bbef0 JB |
7404 | { |
7405 | { "vpshaw", { XM, EXx, VexW }, 0 }, | |
7406 | }, | |
7407 | ||
b5c37946 | 7408 | /* VEX_LEN_XOP_09_9A */ |
467bbef0 JB |
7409 | { |
7410 | { "vpshad", { XM, EXx, VexW }, 0 }, | |
7411 | }, | |
7412 | ||
b5c37946 | 7413 | /* VEX_LEN_XOP_09_9B */ |
467bbef0 JB |
7414 | { |
7415 | { "vpshaq", { XM, EXx, VexW }, 0 }, | |
7416 | }, | |
7417 | ||
b5c37946 | 7418 | /* VEX_LEN_XOP_09_C1 */ |
467bbef0 | 7419 | { |
b5c37946 | 7420 | { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) }, |
467bbef0 JB |
7421 | }, |
7422 | ||
b5c37946 | 7423 | /* VEX_LEN_XOP_09_C2 */ |
467bbef0 | 7424 | { |
b5c37946 | 7425 | { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) }, |
467bbef0 JB |
7426 | }, |
7427 | ||
b5c37946 | 7428 | /* VEX_LEN_XOP_09_C3 */ |
467bbef0 | 7429 | { |
b5c37946 | 7430 | { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) }, |
467bbef0 JB |
7431 | }, |
7432 | ||
b5c37946 | 7433 | /* VEX_LEN_XOP_09_C6 */ |
467bbef0 | 7434 | { |
b5c37946 | 7435 | { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) }, |
467bbef0 JB |
7436 | }, |
7437 | ||
b5c37946 | 7438 | /* VEX_LEN_XOP_09_C7 */ |
467bbef0 | 7439 | { |
b5c37946 | 7440 | { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) }, |
467bbef0 JB |
7441 | }, |
7442 | ||
b5c37946 | 7443 | /* VEX_LEN_XOP_09_CB */ |
467bbef0 | 7444 | { |
b5c37946 | 7445 | { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) }, |
467bbef0 JB |
7446 | }, |
7447 | ||
b5c37946 | 7448 | /* VEX_LEN_XOP_09_D1 */ |
467bbef0 | 7449 | { |
b5c37946 | 7450 | { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) }, |
467bbef0 JB |
7451 | }, |
7452 | ||
b5c37946 | 7453 | /* VEX_LEN_XOP_09_D2 */ |
467bbef0 | 7454 | { |
b5c37946 | 7455 | { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) }, |
467bbef0 JB |
7456 | }, |
7457 | ||
b5c37946 | 7458 | /* VEX_LEN_XOP_09_D3 */ |
467bbef0 | 7459 | { |
b5c37946 | 7460 | { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) }, |
467bbef0 JB |
7461 | }, |
7462 | ||
b5c37946 | 7463 | /* VEX_LEN_XOP_09_D6 */ |
467bbef0 | 7464 | { |
b5c37946 | 7465 | { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) }, |
467bbef0 JB |
7466 | }, |
7467 | ||
b5c37946 | 7468 | /* VEX_LEN_XOP_09_D7 */ |
467bbef0 | 7469 | { |
b5c37946 | 7470 | { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) }, |
467bbef0 JB |
7471 | }, |
7472 | ||
b5c37946 | 7473 | /* VEX_LEN_XOP_09_DB */ |
467bbef0 | 7474 | { |
b5c37946 | 7475 | { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) }, |
467bbef0 JB |
7476 | }, |
7477 | ||
b5c37946 | 7478 | /* VEX_LEN_XOP_09_E1 */ |
467bbef0 | 7479 | { |
b5c37946 | 7480 | { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) }, |
467bbef0 JB |
7481 | }, |
7482 | ||
b5c37946 | 7483 | /* VEX_LEN_XOP_09_E2 */ |
467bbef0 | 7484 | { |
b5c37946 | 7485 | { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) }, |
467bbef0 JB |
7486 | }, |
7487 | ||
b5c37946 | 7488 | /* VEX_LEN_XOP_09_E3 */ |
467bbef0 | 7489 | { |
b5c37946 | 7490 | { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) }, |
467bbef0 JB |
7491 | }, |
7492 | ||
b5c37946 | 7493 | /* VEX_LEN_XOP_0A_12 */ |
467bbef0 | 7494 | { |
32e31ad7 | 7495 | { REG_TABLE (REG_XOP_0A_12_L_0) }, |
467bbef0 | 7496 | }, |
331d2d0d L |
7497 | }; |
7498 | ||
ad692897 | 7499 | #include "i386-dis-evex-len.h" |
04e2a182 | 7500 | |
9e30b8e0 | 7501 | static const struct dis386 vex_w_table[][2] = { |
43234a1e | 7502 | { |
13954a31 | 7503 | /* VEX_W_0F41_L_1_M_1 */ |
b5c37946 SJ |
7504 | { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) }, |
7505 | { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) }, | |
1ba585e8 IT |
7506 | }, |
7507 | { | |
13954a31 | 7508 | /* VEX_W_0F42_L_1_M_1 */ |
b5c37946 SJ |
7509 | { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) }, |
7510 | { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) }, | |
43234a1e L |
7511 | }, |
7512 | { | |
13954a31 | 7513 | /* VEX_W_0F44_L_0_M_1 */ |
b5c37946 SJ |
7514 | { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) }, |
7515 | { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) }, | |
1ba585e8 IT |
7516 | }, |
7517 | { | |
13954a31 | 7518 | /* VEX_W_0F45_L_1_M_1 */ |
b5c37946 SJ |
7519 | { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) }, |
7520 | { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) }, | |
43234a1e L |
7521 | }, |
7522 | { | |
13954a31 | 7523 | /* VEX_W_0F46_L_1_M_1 */ |
b5c37946 SJ |
7524 | { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) }, |
7525 | { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) }, | |
9e30b8e0 L |
7526 | }, |
7527 | { | |
13954a31 | 7528 | /* VEX_W_0F47_L_1_M_1 */ |
b5c37946 SJ |
7529 | { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) }, |
7530 | { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) }, | |
9e30b8e0 L |
7531 | }, |
7532 | { | |
13954a31 | 7533 | /* VEX_W_0F4A_L_1_M_1 */ |
b5c37946 SJ |
7534 | { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) }, |
7535 | { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) }, | |
9e30b8e0 L |
7536 | }, |
7537 | { | |
13954a31 | 7538 | /* VEX_W_0F4B_L_1_M_1 */ |
b5c37946 SJ |
7539 | { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) }, |
7540 | { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) }, | |
9e30b8e0 L |
7541 | }, |
7542 | { | |
13954a31 JB |
7543 | /* VEX_W_0F90_L_0 */ |
7544 | { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) }, | |
7545 | { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) }, | |
9e30b8e0 L |
7546 | }, |
7547 | { | |
13954a31 | 7548 | /* VEX_W_0F91_L_0_M_0 */ |
b5c37946 SJ |
7549 | { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) }, |
7550 | { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) }, | |
9e30b8e0 L |
7551 | }, |
7552 | { | |
13954a31 | 7553 | /* VEX_W_0F92_L_0_M_1 */ |
b5c37946 SJ |
7554 | { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) }, |
7555 | { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) }, | |
9e30b8e0 L |
7556 | }, |
7557 | { | |
13954a31 | 7558 | /* VEX_W_0F93_L_0_M_1 */ |
b5c37946 SJ |
7559 | { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) }, |
7560 | { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) }, | |
9e30b8e0 L |
7561 | }, |
7562 | { | |
13954a31 | 7563 | /* VEX_W_0F98_L_0_M_1 */ |
b5c37946 SJ |
7564 | { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) }, |
7565 | { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) }, | |
9e30b8e0 L |
7566 | }, |
7567 | { | |
13954a31 | 7568 | /* VEX_W_0F99_L_0_M_1 */ |
b5c37946 SJ |
7569 | { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) }, |
7570 | { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) }, | |
9e30b8e0 | 7571 | }, |
9e30b8e0 | 7572 | { |
7531c613 | 7573 | /* VEX_W_0F380C */ |
f7cfcddd | 7574 | { "%XEvpermilps", { XM, Vex, EXx }, PREFIX_DATA }, |
9e30b8e0 L |
7575 | }, |
7576 | { | |
7531c613 JB |
7577 | /* VEX_W_0F380D */ |
7578 | { "vpermilpd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7579 | }, |
7580 | { | |
7531c613 JB |
7581 | /* VEX_W_0F380E */ |
7582 | { "vtestps", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 L |
7583 | }, |
7584 | { | |
7531c613 JB |
7585 | /* VEX_W_0F380F */ |
7586 | { "vtestpd", { XM, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7587 | }, |
6431c801 | 7588 | { |
7531c613 JB |
7589 | /* VEX_W_0F3813 */ |
7590 | { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA }, | |
6431c801 | 7591 | }, |
6c30d220 | 7592 | { |
7531c613 JB |
7593 | /* VEX_W_0F3816_L_1 */ |
7594 | { "vpermps", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7595 | }, |
bcf2684f | 7596 | { |
7531c613 | 7597 | /* VEX_W_0F3818 */ |
f7cfcddd | 7598 | { "%XEvbroadcastss", { XM, EXd }, PREFIX_DATA }, |
bcf2684f | 7599 | }, |
9e30b8e0 | 7600 | { |
7531c613 | 7601 | /* VEX_W_0F3819_L_1 */ |
c1d66d5f | 7602 | { "vbroadcastsd", { XM, EXq }, PREFIX_DATA }, |
9e30b8e0 L |
7603 | }, |
7604 | { | |
b5c37946 | 7605 | /* VEX_W_0F381A_L_1 */ |
7531c613 | 7606 | { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA }, |
9e30b8e0 | 7607 | }, |
53aa04a0 | 7608 | { |
b5c37946 | 7609 | /* VEX_W_0F382C */ |
7531c613 | 7610 | { "vmaskmovps", { XM, Vex, Mx }, PREFIX_DATA }, |
53aa04a0 L |
7611 | }, |
7612 | { | |
b5c37946 | 7613 | /* VEX_W_0F382D */ |
7531c613 | 7614 | { "vmaskmovpd", { XM, Vex, Mx }, PREFIX_DATA }, |
53aa04a0 L |
7615 | }, |
7616 | { | |
b5c37946 | 7617 | /* VEX_W_0F382E */ |
7531c613 | 7618 | { "vmaskmovps", { Mx, Vex, XM }, PREFIX_DATA }, |
53aa04a0 L |
7619 | }, |
7620 | { | |
b5c37946 | 7621 | /* VEX_W_0F382F */ |
7531c613 | 7622 | { "vmaskmovpd", { Mx, Vex, XM }, PREFIX_DATA }, |
53aa04a0 | 7623 | }, |
6c30d220 | 7624 | { |
7531c613 JB |
7625 | /* VEX_W_0F3836 */ |
7626 | { "vpermd", { XM, Vex, EXx }, PREFIX_DATA }, | |
9e30b8e0 | 7627 | }, |
6c30d220 | 7628 | { |
7531c613 JB |
7629 | /* VEX_W_0F3846 */ |
7630 | { "vpsravd", { XM, Vex, EXx }, PREFIX_DATA }, | |
6c30d220 | 7631 | }, |
260cd341 | 7632 | { |
1f506c06 JB |
7633 | /* VEX_W_0F3849_X86_64_L_0 */ |
7634 | { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) }, | |
260cd341 LC |
7635 | }, |
7636 | { | |
1f506c06 | 7637 | /* VEX_W_0F384B_X86_64_L_0 */ |
b5c37946 | 7638 | { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) }, |
260cd341 | 7639 | }, |
58bf9b6a L |
7640 | { |
7641 | /* VEX_W_0F3850 */ | |
23ae61ad | 7642 | { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) }, |
58bf9b6a L |
7643 | }, |
7644 | { | |
0a98ae76 | 7645 | /* VEX_W_0F3851 */ |
23ae61ad | 7646 | { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) }, |
58bf9b6a L |
7647 | }, |
7648 | { | |
7649 | /* VEX_W_0F3852 */ | |
995bca23 | 7650 | { "%XVvpdpwssd", { XM, Vex, EXx }, PREFIX_DATA }, |
58bf9b6a L |
7651 | }, |
7652 | { | |
7653 | /* VEX_W_0F3853 */ | |
995bca23 | 7654 | { "%XVvpdpwssds", { XM, Vex, EXx }, PREFIX_DATA }, |
58bf9b6a | 7655 | }, |
6c30d220 | 7656 | { |
7531c613 | 7657 | /* VEX_W_0F3858 */ |
f7cfcddd | 7658 | { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA }, |
6c30d220 L |
7659 | }, |
7660 | { | |
7531c613 | 7661 | /* VEX_W_0F3859 */ |
c1d66d5f | 7662 | { "vpbroadcastq", { XM, EXq }, PREFIX_DATA }, |
6c30d220 L |
7663 | }, |
7664 | { | |
b5c37946 | 7665 | /* VEX_W_0F385A_L_0 */ |
7531c613 | 7666 | { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA }, |
6c30d220 | 7667 | }, |
260cd341 | 7668 | { |
b5c37946 SJ |
7669 | /* VEX_W_0F385C_X86_64_L_0 */ |
7670 | { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) }, | |
260cd341 LC |
7671 | }, |
7672 | { | |
b5c37946 SJ |
7673 | /* VEX_W_0F385E_X86_64_L_0 */ |
7674 | { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) }, | |
260cd341 LC |
7675 | }, |
7676 | { | |
b5c37946 SJ |
7677 | /* VEX_W_0F386C_X86_64_L_0 */ |
7678 | { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) }, | |
d100d8c1 | 7679 | }, |
01d8ce74 | 7680 | { |
7681 | /* VEX_W_0F3872_P_1 */ | |
7682 | { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 }, | |
7683 | }, | |
6c30d220 | 7684 | { |
7531c613 | 7685 | /* VEX_W_0F3878 */ |
f7cfcddd | 7686 | { "%XEvpbroadcastb", { XM, EXb }, PREFIX_DATA }, |
6c30d220 L |
7687 | }, |
7688 | { | |
7531c613 | 7689 | /* VEX_W_0F3879 */ |
f7cfcddd | 7690 | { "%XEvpbroadcastw", { XM, EXw }, PREFIX_DATA }, |
6c30d220 | 7691 | }, |
01d8ce74 | 7692 | { |
7693 | /* VEX_W_0F38B0 */ | |
7694 | { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) }, | |
7695 | }, | |
7696 | { | |
7697 | /* VEX_W_0F38B1 */ | |
7698 | { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) }, | |
7699 | }, | |
4321af3e HW |
7700 | { |
7701 | /* VEX_W_0F38B4 */ | |
7702 | { Bad_Opcode }, | |
7703 | { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA }, | |
7704 | }, | |
7705 | { | |
7706 | /* VEX_W_0F38B5 */ | |
7707 | { Bad_Opcode }, | |
7708 | { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA }, | |
7709 | }, | |
b5c37946 SJ |
7710 | { |
7711 | /* VEX_W_0F38CB_P_3 */ | |
7712 | { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) }, | |
7713 | }, | |
7714 | { | |
7715 | /* VEX_W_0F38CC_P_3 */ | |
7716 | { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) }, | |
7717 | }, | |
7718 | { | |
7719 | /* VEX_W_0F38CD_P_3 */ | |
7720 | { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) }, | |
7721 | }, | |
48521003 | 7722 | { |
7531c613 | 7723 | /* VEX_W_0F38CF */ |
f7cfcddd | 7724 | { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA }, |
48521003 | 7725 | }, |
b5c37946 SJ |
7726 | { |
7727 | /* VEX_W_0F38D2 */ | |
7728 | { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) }, | |
7729 | }, | |
7730 | { | |
7731 | /* VEX_W_0F38D3 */ | |
7732 | { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) }, | |
7733 | }, | |
7734 | { | |
7735 | /* VEX_W_0F38DA */ | |
7736 | { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) }, | |
7737 | }, | |
6c30d220 | 7738 | { |
7531c613 | 7739 | /* VEX_W_0F3A00_L_1 */ |
6c30d220 | 7740 | { Bad_Opcode }, |
f7cfcddd | 7741 | { "%XEvpermq", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7742 | }, |
7743 | { | |
7531c613 | 7744 | /* VEX_W_0F3A01_L_1 */ |
6c30d220 | 7745 | { Bad_Opcode }, |
f7cfcddd | 7746 | { "%XEvpermpd", { XM, EXx, Ib }, PREFIX_DATA }, |
6c30d220 L |
7747 | }, |
7748 | { | |
7531c613 JB |
7749 | /* VEX_W_0F3A02 */ |
7750 | { "vpblendd", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7751 | }, |
9e30b8e0 | 7752 | { |
7531c613 | 7753 | /* VEX_W_0F3A04 */ |
f7cfcddd | 7754 | { "%XEvpermilps", { XM, EXx, Ib }, PREFIX_DATA }, |
9e30b8e0 L |
7755 | }, |
7756 | { | |
7531c613 JB |
7757 | /* VEX_W_0F3A05 */ |
7758 | { "vpermilpd", { XM, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7759 | }, |
7760 | { | |
7531c613 JB |
7761 | /* VEX_W_0F3A06_L_1 */ |
7762 | { "vperm2f128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7763 | }, |
9e30b8e0 | 7764 | { |
7531c613 JB |
7765 | /* VEX_W_0F3A18_L_1 */ |
7766 | { "vinsertf128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
9e30b8e0 L |
7767 | }, |
7768 | { | |
7531c613 JB |
7769 | /* VEX_W_0F3A19_L_1 */ |
7770 | { "vextractf128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
9e30b8e0 | 7771 | }, |
6431c801 | 7772 | { |
7531c613 | 7773 | /* VEX_W_0F3A1D */ |
f7cfcddd | 7774 | { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA }, |
6431c801 | 7775 | }, |
6c30d220 | 7776 | { |
7531c613 JB |
7777 | /* VEX_W_0F3A38_L_1 */ |
7778 | { "vinserti128", { XM, Vex, EXxmm, Ib }, PREFIX_DATA }, | |
6c30d220 L |
7779 | }, |
7780 | { | |
7531c613 JB |
7781 | /* VEX_W_0F3A39_L_1 */ |
7782 | { "vextracti128", { EXxmm, XM, Ib }, PREFIX_DATA }, | |
6c30d220 | 7783 | }, |
6c30d220 | 7784 | { |
7531c613 JB |
7785 | /* VEX_W_0F3A46_L_1 */ |
7786 | { "vperm2i128", { XM, Vex, EXx, Ib }, PREFIX_DATA }, | |
6c30d220 | 7787 | }, |
9e30b8e0 | 7788 | { |
7531c613 JB |
7789 | /* VEX_W_0F3A4A */ |
7790 | { "vblendvps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7791 | }, |
7792 | { | |
7531c613 JB |
7793 | /* VEX_W_0F3A4B */ |
7794 | { "vblendvpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 L |
7795 | }, |
7796 | { | |
7531c613 JB |
7797 | /* VEX_W_0F3A4C */ |
7798 | { "vpblendvb", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA }, | |
9e30b8e0 | 7799 | }, |
48521003 | 7800 | { |
7531c613 | 7801 | /* VEX_W_0F3ACE */ |
48521003 | 7802 | { Bad_Opcode }, |
f7cfcddd | 7803 | { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 IT |
7804 | }, |
7805 | { | |
7531c613 | 7806 | /* VEX_W_0F3ACF */ |
48521003 | 7807 | { Bad_Opcode }, |
f7cfcddd | 7808 | { "%XEvgf2p8affineinvqb", { XM, Vex, EXx, Ib }, PREFIX_DATA }, |
48521003 | 7809 | }, |
b5c37946 SJ |
7810 | { |
7811 | /* VEX_W_0F3ADE */ | |
7812 | { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) }, | |
7813 | }, | |
7814 | /* VEX_W_XOP_08_85_L_0 */ | |
467bbef0 JB |
7815 | { |
7816 | { "vpmacssww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7817 | }, | |
b5c37946 | 7818 | /* VEX_W_XOP_08_86_L_0 */ |
467bbef0 JB |
7819 | { |
7820 | { "vpmacsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7821 | }, | |
b5c37946 | 7822 | /* VEX_W_XOP_08_87_L_0 */ |
467bbef0 JB |
7823 | { |
7824 | { "vpmacssdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7825 | }, | |
b5c37946 | 7826 | /* VEX_W_XOP_08_8E_L_0 */ |
467bbef0 JB |
7827 | { |
7828 | { "vpmacssdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7829 | }, | |
b5c37946 | 7830 | /* VEX_W_XOP_08_8F_L_0 */ |
467bbef0 JB |
7831 | { |
7832 | { "vpmacssdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7833 | }, | |
b5c37946 | 7834 | /* VEX_W_XOP_08_95_L_0 */ |
467bbef0 JB |
7835 | { |
7836 | { "vpmacsww", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7837 | }, | |
b5c37946 | 7838 | /* VEX_W_XOP_08_96_L_0 */ |
467bbef0 JB |
7839 | { |
7840 | { "vpmacswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7841 | }, | |
b5c37946 | 7842 | /* VEX_W_XOP_08_97_L_0 */ |
467bbef0 JB |
7843 | { |
7844 | { "vpmacsdql", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7845 | }, | |
b5c37946 | 7846 | /* VEX_W_XOP_08_9E_L_0 */ |
467bbef0 JB |
7847 | { |
7848 | { "vpmacsdd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7849 | }, | |
b5c37946 | 7850 | /* VEX_W_XOP_08_9F_L_0 */ |
467bbef0 JB |
7851 | { |
7852 | { "vpmacsdqh", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7853 | }, | |
b5c37946 | 7854 | /* VEX_W_XOP_08_A6_L_0 */ |
467bbef0 JB |
7855 | { |
7856 | { "vpmadcsswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7857 | }, | |
b5c37946 | 7858 | /* VEX_W_XOP_08_B6_L_0 */ |
467bbef0 JB |
7859 | { |
7860 | { "vpmadcswd", { XM, Vex, EXx, XMVexI4 }, 0 }, | |
7861 | }, | |
b5c37946 | 7862 | /* VEX_W_XOP_08_C0_L_0 */ |
467bbef0 JB |
7863 | { |
7864 | { "vprotb", { XM, EXx, Ib }, 0 }, | |
7865 | }, | |
b5c37946 | 7866 | /* VEX_W_XOP_08_C1_L_0 */ |
467bbef0 JB |
7867 | { |
7868 | { "vprotw", { XM, EXx, Ib }, 0 }, | |
7869 | }, | |
b5c37946 | 7870 | /* VEX_W_XOP_08_C2_L_0 */ |
467bbef0 JB |
7871 | { |
7872 | { "vprotd", { XM, EXx, Ib }, 0 }, | |
7873 | }, | |
b5c37946 | 7874 | /* VEX_W_XOP_08_C3_L_0 */ |
467bbef0 JB |
7875 | { |
7876 | { "vprotq", { XM, EXx, Ib }, 0 }, | |
7877 | }, | |
b5c37946 | 7878 | /* VEX_W_XOP_08_CC_L_0 */ |
467bbef0 | 7879 | { |
89e65d17 | 7880 | { "vpcomb", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7881 | }, |
b5c37946 | 7882 | /* VEX_W_XOP_08_CD_L_0 */ |
467bbef0 | 7883 | { |
89e65d17 | 7884 | { "vpcomw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7885 | }, |
b5c37946 | 7886 | /* VEX_W_XOP_08_CE_L_0 */ |
467bbef0 | 7887 | { |
89e65d17 | 7888 | { "vpcomd", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7889 | }, |
b5c37946 | 7890 | /* VEX_W_XOP_08_CF_L_0 */ |
467bbef0 | 7891 | { |
89e65d17 | 7892 | { "vpcomq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7893 | }, |
b5c37946 | 7894 | /* VEX_W_XOP_08_EC_L_0 */ |
467bbef0 | 7895 | { |
89e65d17 | 7896 | { "vpcomub", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7897 | }, |
b5c37946 | 7898 | /* VEX_W_XOP_08_ED_L_0 */ |
467bbef0 | 7899 | { |
89e65d17 | 7900 | { "vpcomuw", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7901 | }, |
b5c37946 | 7902 | /* VEX_W_XOP_08_EE_L_0 */ |
467bbef0 | 7903 | { |
89e65d17 | 7904 | { "vpcomud", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7905 | }, |
b5c37946 | 7906 | /* VEX_W_XOP_08_EF_L_0 */ |
467bbef0 | 7907 | { |
89e65d17 | 7908 | { "vpcomuq", { XM, Vex, EXx, VPCOM }, 0 }, |
467bbef0 | 7909 | }, |
b5c37946 | 7910 | /* VEX_W_XOP_09_80 */ |
b5b098c2 JB |
7911 | { |
7912 | { "vfrczps", { XM, EXx }, 0 }, | |
7913 | }, | |
b5c37946 | 7914 | /* VEX_W_XOP_09_81 */ |
b5b098c2 JB |
7915 | { |
7916 | { "vfrczpd", { XM, EXx }, 0 }, | |
7917 | }, | |
b5c37946 | 7918 | /* VEX_W_XOP_09_82 */ |
b5b098c2 | 7919 | { |
b5c37946 | 7920 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) }, |
b5b098c2 | 7921 | }, |
b5c37946 | 7922 | /* VEX_W_XOP_09_83 */ |
b5b098c2 | 7923 | { |
b5c37946 | 7924 | { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) }, |
b5b098c2 | 7925 | }, |
b5c37946 | 7926 | /* VEX_W_XOP_09_C1_L_0 */ |
467bbef0 JB |
7927 | { |
7928 | { "vphaddbw", { XM, EXxmm }, 0 }, | |
7929 | }, | |
b5c37946 | 7930 | /* VEX_W_XOP_09_C2_L_0 */ |
467bbef0 JB |
7931 | { |
7932 | { "vphaddbd", { XM, EXxmm }, 0 }, | |
7933 | }, | |
b5c37946 | 7934 | /* VEX_W_XOP_09_C3_L_0 */ |
467bbef0 JB |
7935 | { |
7936 | { "vphaddbq", { XM, EXxmm }, 0 }, | |
7937 | }, | |
b5c37946 | 7938 | /* VEX_W_XOP_09_C6_L_0 */ |
467bbef0 JB |
7939 | { |
7940 | { "vphaddwd", { XM, EXxmm }, 0 }, | |
7941 | }, | |
b5c37946 | 7942 | /* VEX_W_XOP_09_C7_L_0 */ |
467bbef0 JB |
7943 | { |
7944 | { "vphaddwq", { XM, EXxmm }, 0 }, | |
7945 | }, | |
b5c37946 | 7946 | /* VEX_W_XOP_09_CB_L_0 */ |
467bbef0 JB |
7947 | { |
7948 | { "vphadddq", { XM, EXxmm }, 0 }, | |
7949 | }, | |
b5c37946 | 7950 | /* VEX_W_XOP_09_D1_L_0 */ |
467bbef0 JB |
7951 | { |
7952 | { "vphaddubw", { XM, EXxmm }, 0 }, | |
7953 | }, | |
b5c37946 | 7954 | /* VEX_W_XOP_09_D2_L_0 */ |
467bbef0 JB |
7955 | { |
7956 | { "vphaddubd", { XM, EXxmm }, 0 }, | |
7957 | }, | |
b5c37946 | 7958 | /* VEX_W_XOP_09_D3_L_0 */ |
467bbef0 JB |
7959 | { |
7960 | { "vphaddubq", { XM, EXxmm }, 0 }, | |
7961 | }, | |
b5c37946 | 7962 | /* VEX_W_XOP_09_D6_L_0 */ |
467bbef0 JB |
7963 | { |
7964 | { "vphadduwd", { XM, EXxmm }, 0 }, | |
7965 | }, | |
b5c37946 | 7966 | /* VEX_W_XOP_09_D7_L_0 */ |
467bbef0 JB |
7967 | { |
7968 | { "vphadduwq", { XM, EXxmm }, 0 }, | |
7969 | }, | |
b5c37946 | 7970 | /* VEX_W_XOP_09_DB_L_0 */ |
467bbef0 JB |
7971 | { |
7972 | { "vphaddudq", { XM, EXxmm }, 0 }, | |
7973 | }, | |
b5c37946 | 7974 | /* VEX_W_XOP_09_E1_L_0 */ |
467bbef0 JB |
7975 | { |
7976 | { "vphsubbw", { XM, EXxmm }, 0 }, | |
7977 | }, | |
b5c37946 | 7978 | /* VEX_W_XOP_09_E2_L_0 */ |
467bbef0 JB |
7979 | { |
7980 | { "vphsubwd", { XM, EXxmm }, 0 }, | |
7981 | }, | |
b5c37946 | 7982 | /* VEX_W_XOP_09_E3_L_0 */ |
467bbef0 JB |
7983 | { |
7984 | { "vphsubdq", { XM, EXxmm }, 0 }, | |
7985 | }, | |
ad692897 L |
7986 | |
7987 | #include "i386-dis-evex-w.h" | |
9e30b8e0 L |
7988 | }; |
7989 | ||
7990 | static const struct dis386 mod_table[][2] = { | |
32e31ad7 JB |
7991 | { |
7992 | /* MOD_62_32BIT */ | |
7993 | { "bound{S|}", { Gv, Ma }, 0 }, | |
b5c37946 | 7994 | { EVEX_TABLE () }, |
32e31ad7 | 7995 | }, |
32e31ad7 JB |
7996 | { |
7997 | /* MOD_C4_32BIT */ | |
7998 | { "lesS", { Gv, Mp }, 0 }, | |
b5c37946 | 7999 | { VEX_C4_TABLE () }, |
32e31ad7 JB |
8000 | }, |
8001 | { | |
8002 | /* MOD_C5_32BIT */ | |
8003 | { "ldsS", { Gv, Mp }, 0 }, | |
b5c37946 | 8004 | { VEX_C5_TABLE () }, |
32e31ad7 | 8005 | }, |
9e30b8e0 L |
8006 | { |
8007 | /* MOD_0F01_REG_0 */ | |
8008 | { X86_64_TABLE (X86_64_0F01_REG_0) }, | |
8009 | { RM_TABLE (RM_0F01_REG_0) }, | |
8010 | }, | |
8011 | { | |
8012 | /* MOD_0F01_REG_1 */ | |
8013 | { X86_64_TABLE (X86_64_0F01_REG_1) }, | |
8014 | { RM_TABLE (RM_0F01_REG_1) }, | |
8015 | }, | |
8016 | { | |
8017 | /* MOD_0F01_REG_2 */ | |
8018 | { X86_64_TABLE (X86_64_0F01_REG_2) }, | |
8019 | { RM_TABLE (RM_0F01_REG_2) }, | |
8020 | }, | |
8021 | { | |
8022 | /* MOD_0F01_REG_3 */ | |
8023 | { X86_64_TABLE (X86_64_0F01_REG_3) }, | |
8024 | { RM_TABLE (RM_0F01_REG_3) }, | |
8025 | }, | |
8eab4136 L |
8026 | { |
8027 | /* MOD_0F01_REG_5 */ | |
f8687e93 JB |
8028 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) }, |
8029 | { RM_TABLE (RM_0F01_REG_5_MOD_3) }, | |
8eab4136 | 8030 | }, |
9e30b8e0 L |
8031 | { |
8032 | /* MOD_0F01_REG_7 */ | |
bf890a93 | 8033 | { "invlpg", { Mb }, 0 }, |
f8687e93 | 8034 | { RM_TABLE (RM_0F01_REG_7_MOD_3) }, |
9e30b8e0 L |
8035 | }, |
8036 | { | |
8037 | /* MOD_0F12_PREFIX_0 */ | |
b5c37946 SJ |
8038 | { "%XEVmovlpYX", { XM, Vex, EXq }, 0 }, |
8039 | { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 }, | |
18897deb | 8040 | }, |
9e30b8e0 L |
8041 | { |
8042 | /* MOD_0F16_PREFIX_0 */ | |
b5c37946 SJ |
8043 | { "%XEVmovhpYX", { XM, Vex, EXq }, 0 }, |
8044 | { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 }, | |
9e30b8e0 | 8045 | }, |
9e30b8e0 L |
8046 | { |
8047 | /* MOD_0F18_REG_0 */ | |
bf890a93 | 8048 | { "prefetchnta", { Mb }, 0 }, |
31941983 | 8049 | { "nopQ", { Ev }, 0 }, |
9e30b8e0 L |
8050 | }, |
8051 | { | |
8052 | /* MOD_0F18_REG_1 */ | |
bf890a93 | 8053 | { "prefetcht0", { Mb }, 0 }, |
31941983 | 8054 | { "nopQ", { Ev }, 0 }, |
9e30b8e0 L |
8055 | }, |
8056 | { | |
8057 | /* MOD_0F18_REG_2 */ | |
bf890a93 | 8058 | { "prefetcht1", { Mb }, 0 }, |
31941983 | 8059 | { "nopQ", { Ev }, 0 }, |
9e30b8e0 L |
8060 | }, |
8061 | { | |
8062 | /* MOD_0F18_REG_3 */ | |
bf890a93 | 8063 | { "prefetcht2", { Mb }, 0 }, |
31941983 | 8064 | { "nopQ", { Ev }, 0 }, |
d7189fa5 | 8065 | }, |
ef07be45 CL |
8066 | { |
8067 | /* MOD_0F18_REG_6 */ | |
8068 | { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) }, | |
8069 | { "nopQ", { Ev }, 0 }, | |
8070 | }, | |
8071 | { | |
8072 | /* MOD_0F18_REG_7 */ | |
8073 | { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) }, | |
8074 | { "nopQ", { Ev }, 0 }, | |
8075 | }, | |
7e8b059b L |
8076 | { |
8077 | /* MOD_0F1A_PREFIX_0 */ | |
d276ec69 | 8078 | { "bndldx", { Gbnd, Mv_bnd }, 0 }, |
bf890a93 | 8079 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
8080 | }, |
8081 | { | |
8082 | /* MOD_0F1B_PREFIX_0 */ | |
d276ec69 | 8083 | { "bndstx", { Mv_bnd, Gbnd }, 0 }, |
bf890a93 | 8084 | { "nopQ", { Ev }, 0 }, |
7e8b059b L |
8085 | }, |
8086 | { | |
8087 | /* MOD_0F1B_PREFIX_1 */ | |
d276ec69 | 8088 | { "bndmk", { Gbnd, Mv_bnd }, 0 }, |
31941983 | 8089 | { "nopQ", { Ev }, PREFIX_IGNORED }, |
7e8b059b | 8090 | }, |
c48935d7 IT |
8091 | { |
8092 | /* MOD_0F1C_PREFIX_0 */ | |
f8687e93 | 8093 | { REG_TABLE (REG_0F1C_P_0_MOD_0) }, |
c48935d7 IT |
8094 | { "nopQ", { Ev }, 0 }, |
8095 | }, | |
603555e5 L |
8096 | { |
8097 | /* MOD_0F1E_PREFIX_1 */ | |
31941983 | 8098 | { "nopQ", { Ev }, PREFIX_IGNORED }, |
f8687e93 | 8099 | { REG_TABLE (REG_0F1E_P_1_MOD_3) }, |
603555e5 | 8100 | }, |
c0f3af97 L |
8101 | { |
8102 | /* MOD_0FAE_REG_0 */ | |
bf890a93 | 8103 | { "fxsave", { FXSAVE }, 0 }, |
f8687e93 | 8104 | { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) }, |
c0f3af97 L |
8105 | }, |
8106 | { | |
8107 | /* MOD_0FAE_REG_1 */ | |
bf890a93 | 8108 | { "fxrstor", { FXSAVE }, 0 }, |
f8687e93 | 8109 | { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) }, |
c0f3af97 L |
8110 | }, |
8111 | { | |
8112 | /* MOD_0FAE_REG_2 */ | |
bf890a93 | 8113 | { "ldmxcsr", { Md }, 0 }, |
f8687e93 | 8114 | { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) }, |
c0f3af97 L |
8115 | }, |
8116 | { | |
8117 | /* MOD_0FAE_REG_3 */ | |
bf890a93 | 8118 | { "stmxcsr", { Md }, 0 }, |
f8687e93 | 8119 | { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) }, |
c0f3af97 L |
8120 | }, |
8121 | { | |
8122 | /* MOD_0FAE_REG_4 */ | |
f8687e93 JB |
8123 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) }, |
8124 | { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) }, | |
c0f3af97 L |
8125 | }, |
8126 | { | |
8127 | /* MOD_0FAE_REG_5 */ | |
035e7389 | 8128 | { "xrstor", { FXSAVE }, PREFIX_OPCODE }, |
f8687e93 | 8129 | { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) }, |
c0f3af97 L |
8130 | }, |
8131 | { | |
8132 | /* MOD_0FAE_REG_6 */ | |
f8687e93 JB |
8133 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) }, |
8134 | { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) }, | |
c0f3af97 L |
8135 | }, |
8136 | { | |
8137 | /* MOD_0FAE_REG_7 */ | |
f8687e93 JB |
8138 | { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) }, |
8139 | { RM_TABLE (RM_0FAE_REG_7_MOD_3) }, | |
c0f3af97 | 8140 | }, |
c0f3af97 L |
8141 | { |
8142 | /* MOD_0FC7_REG_6 */ | |
f8687e93 JB |
8143 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) }, |
8144 | { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) } | |
c0f3af97 L |
8145 | }, |
8146 | { | |
8147 | /* MOD_0FC7_REG_7 */ | |
bf890a93 | 8148 | { "vmptrst", { Mq }, 0 }, |
f8687e93 | 8149 | { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) } |
c0f3af97 | 8150 | }, |
c4694f17 TG |
8151 | { |
8152 | /* MOD_0F38DC_PREFIX_1 */ | |
8153 | { "aesenc128kl", { XM, M }, 0 }, | |
8154 | { "loadiwkey", { XM, EXx }, 0 }, | |
8155 | }, | |
09d73035 | 8156 | { |
1f506c06 JB |
8157 | /* MOD_VEX_0F3849_X86_64_L_0_W_0 */ |
8158 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) }, | |
8159 | { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) }, | |
09d73035 | 8160 | }, |
ad692897 L |
8161 | |
8162 | #include "i386-dis-evex-mod.h" | |
b844680a L |
8163 | }; |
8164 | ||
1ceb70f8 | 8165 | static const struct dis386 rm_table[][8] = { |
42164a71 L |
8166 | { |
8167 | /* RM_C6_REG_7 */ | |
bf890a93 | 8168 | { "xabort", { Skip_MODRM, Ib }, 0 }, |
42164a71 L |
8169 | }, |
8170 | { | |
8171 | /* RM_C7_REG_7 */ | |
376cd056 | 8172 | { "xbeginT", { Skip_MODRM, Jdqw }, 0 }, |
42164a71 | 8173 | }, |
b844680a | 8174 | { |
1ceb70f8 | 8175 | /* RM_0F01_REG_0 */ |
a4e78aa5 | 8176 | { "enclv", { Skip_MODRM }, 0 }, |
bf890a93 IT |
8177 | { "vmcall", { Skip_MODRM }, 0 }, |
8178 | { "vmlaunch", { Skip_MODRM }, 0 }, | |
8179 | { "vmresume", { Skip_MODRM }, 0 }, | |
8180 | { "vmxoff", { Skip_MODRM }, 0 }, | |
be3a8dca | 8181 | { "pconfig", { Skip_MODRM }, 0 }, |
941f0833 | 8182 | { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) }, |
b5c37946 | 8183 | { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) }, |
b844680a L |
8184 | }, |
8185 | { | |
1ceb70f8 | 8186 | /* RM_0F01_REG_1 */ |
bf890a93 IT |
8187 | { "monitor", { { OP_Monitor, 0 } }, 0 }, |
8188 | { "mwait", { { OP_Mwait, 0 } }, 0 }, | |
c88ed92f | 8189 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) }, |
bf890a93 | 8190 | { "stac", { Skip_MODRM }, 0 }, |
81d54bb7 CL |
8191 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) }, |
8192 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) }, | |
8193 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) }, | |
8194 | { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) }, | |
b844680a | 8195 | }, |
475a2301 L |
8196 | { |
8197 | /* RM_0F01_REG_2 */ | |
bf890a93 IT |
8198 | { "xgetbv", { Skip_MODRM }, 0 }, |
8199 | { "xsetbv", { Skip_MODRM }, 0 }, | |
8729a6f6 L |
8200 | { Bad_Opcode }, |
8201 | { Bad_Opcode }, | |
bf890a93 IT |
8202 | { "vmfunc", { Skip_MODRM }, 0 }, |
8203 | { "xend", { Skip_MODRM }, 0 }, | |
8204 | { "xtest", { Skip_MODRM }, 0 }, | |
8205 | { "enclu", { Skip_MODRM }, 0 }, | |
475a2301 | 8206 | }, |
b844680a | 8207 | { |
1ceb70f8 | 8208 | /* RM_0F01_REG_3 */ |
bf890a93 | 8209 | { "vmrun", { Skip_MODRM }, 0 }, |
a847e322 | 8210 | { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) }, |
bf890a93 IT |
8211 | { "vmload", { Skip_MODRM }, 0 }, |
8212 | { "vmsave", { Skip_MODRM }, 0 }, | |
8213 | { "stgi", { Skip_MODRM }, 0 }, | |
8214 | { "clgi", { Skip_MODRM }, 0 }, | |
8215 | { "skinit", { Skip_MODRM }, 0 }, | |
8216 | { "invlpga", { Skip_MODRM }, 0 }, | |
4e7d34a6 | 8217 | }, |
8eab4136 | 8218 | { |
f8687e93 JB |
8219 | /* RM_0F01_REG_5_MOD_3 */ |
8220 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) }, | |
bb651e8b | 8221 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) }, |
f8687e93 | 8222 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) }, |
8eab4136 | 8223 | { Bad_Opcode }, |
f64c42a9 LC |
8224 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) }, |
8225 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) }, | |
8226 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) }, | |
8227 | { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) }, | |
8eab4136 | 8228 | }, |
4e7d34a6 | 8229 | { |
f8687e93 | 8230 | /* RM_0F01_REG_7_MOD_3 */ |
bf890a93 IT |
8231 | { "swapgs", { Skip_MODRM }, 0 }, |
8232 | { "rdtscp", { Skip_MODRM }, 0 }, | |
267b8516 | 8233 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) }, |
035e7389 | 8234 | { "mwaitx", { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE }, |
bf890a93 | 8235 | { "clzero", { Skip_MODRM }, 0 }, |
b0e8fa7f | 8236 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) }, |
646cc3e0 GG |
8237 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) }, |
8238 | { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) }, | |
b844680a | 8239 | }, |
603555e5 | 8240 | { |
f8687e93 | 8241 | /* RM_0F1E_P_1_MOD_3_REG_7 */ |
31941983 JB |
8242 | { "nopQ", { Ev }, PREFIX_IGNORED }, |
8243 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
8244 | { "endbr64", { Skip_MODRM }, 0 }, | |
8245 | { "endbr32", { Skip_MODRM }, 0 }, | |
8246 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
8247 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
8248 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
8249 | { "nopQ", { Ev }, PREFIX_IGNORED }, | |
603555e5 | 8250 | }, |
b844680a | 8251 | { |
f8687e93 | 8252 | /* RM_0FAE_REG_6_MOD_3 */ |
bf890a93 | 8253 | { "mfence", { Skip_MODRM }, 0 }, |
b844680a | 8254 | }, |
bbedc832 | 8255 | { |
f8687e93 | 8256 | /* RM_0FAE_REG_7_MOD_3 */ |
b5cefcca | 8257 | { "sfence", { Skip_MODRM }, 0 }, |
32e31ad7 JB |
8258 | }, |
8259 | { | |
b5c37946 | 8260 | /* RM_0F3A0F_P_1_R_0 */ |
32e31ad7 | 8261 | { "hreset", { Skip_MODRM, Ib }, 0 }, |
144c41d9 | 8262 | }, |
260cd341 | 8263 | { |
1f506c06 JB |
8264 | /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */ |
8265 | { "tilerelease", { Skip_MODRM }, 0 }, | |
8266 | }, | |
8267 | { | |
8268 | /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */ | |
8269 | { "tilezero", { TMM, Skip_MODRM }, 0 }, | |
260cd341 | 8270 | }, |
b844680a L |
8271 | }; |
8272 | ||
c608c12e AM |
8273 | #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>") |
8274 | ||
eebc56d6 JB |
8275 | /* The values used here must be non-zero, fit in 'unsigned char', and not be |
8276 | in conflict with actual prefix opcodes. */ | |
8277 | #define REP_PREFIX 0x01 | |
8278 | #define XACQUIRE_PREFIX 0x02 | |
8279 | #define XRELEASE_PREFIX 0x03 | |
8280 | #define BND_PREFIX 0x04 | |
8281 | #define NOTRACK_PREFIX 0x05 | |
f16cd0d5 | 8282 | |
bf4d07d5 JB |
8283 | static enum { |
8284 | ckp_okay, | |
8285 | ckp_bogus, | |
8286 | ckp_fetch_error, | |
8287 | } | |
39fb3698 | 8288 | ckprefix (instr_info *ins) |
252b5132 | 8289 | { |
a4aa034a JB |
8290 | int i, length; |
8291 | uint8_t newrex; | |
384e201e | 8292 | |
f310f33d | 8293 | i = 0; |
f16cd0d5 L |
8294 | length = 0; |
8295 | /* The maximum instruction length is 15bytes. */ | |
8296 | while (length < MAX_CODE_LENGTH - 1) | |
252b5132 | 8297 | { |
bf4d07d5 JB |
8298 | if (!fetch_code (ins->info, ins->codep + 1)) |
8299 | return ckp_fetch_error; | |
52b15da3 | 8300 | newrex = 0; |
a4aa034a | 8301 | switch (*ins->codep) |
252b5132 | 8302 | { |
52b15da3 JH |
8303 | /* REX prefixes family. */ |
8304 | case 0x40: | |
8305 | case 0x41: | |
8306 | case 0x42: | |
8307 | case 0x43: | |
8308 | case 0x44: | |
8309 | case 0x45: | |
8310 | case 0x46: | |
8311 | case 0x47: | |
8312 | case 0x48: | |
8313 | case 0x49: | |
8314 | case 0x4a: | |
8315 | case 0x4b: | |
8316 | case 0x4c: | |
8317 | case 0x4d: | |
8318 | case 0x4e: | |
8319 | case 0x4f: | |
39fb3698 | 8320 | if (ins->address_mode == mode_64bit) |
a4aa034a | 8321 | newrex = *ins->codep; |
f16cd0d5 | 8322 | else |
bf4d07d5 | 8323 | return ckp_okay; |
39fb3698 | 8324 | ins->last_rex_prefix = i; |
52b15da3 | 8325 | break; |
252b5132 | 8326 | case 0xf3: |
39fb3698 VM |
8327 | ins->prefixes |= PREFIX_REPZ; |
8328 | ins->last_repz_prefix = i; | |
252b5132 RH |
8329 | break; |
8330 | case 0xf2: | |
39fb3698 VM |
8331 | ins->prefixes |= PREFIX_REPNZ; |
8332 | ins->last_repnz_prefix = i; | |
252b5132 RH |
8333 | break; |
8334 | case 0xf0: | |
39fb3698 VM |
8335 | ins->prefixes |= PREFIX_LOCK; |
8336 | ins->last_lock_prefix = i; | |
252b5132 RH |
8337 | break; |
8338 | case 0x2e: | |
39fb3698 VM |
8339 | ins->prefixes |= PREFIX_CS; |
8340 | ins->last_seg_prefix = i; | |
8341 | if (ins->address_mode != mode_64bit) | |
8342 | ins->active_seg_prefix = PREFIX_CS; | |
252b5132 RH |
8343 | break; |
8344 | case 0x36: | |
39fb3698 VM |
8345 | ins->prefixes |= PREFIX_SS; |
8346 | ins->last_seg_prefix = i; | |
8347 | if (ins->address_mode != mode_64bit) | |
8348 | ins->active_seg_prefix = PREFIX_SS; | |
252b5132 RH |
8349 | break; |
8350 | case 0x3e: | |
39fb3698 VM |
8351 | ins->prefixes |= PREFIX_DS; |
8352 | ins->last_seg_prefix = i; | |
8353 | if (ins->address_mode != mode_64bit) | |
8354 | ins->active_seg_prefix = PREFIX_DS; | |
252b5132 RH |
8355 | break; |
8356 | case 0x26: | |
39fb3698 VM |
8357 | ins->prefixes |= PREFIX_ES; |
8358 | ins->last_seg_prefix = i; | |
8359 | if (ins->address_mode != mode_64bit) | |
8360 | ins->active_seg_prefix = PREFIX_ES; | |
252b5132 RH |
8361 | break; |
8362 | case 0x64: | |
39fb3698 VM |
8363 | ins->prefixes |= PREFIX_FS; |
8364 | ins->last_seg_prefix = i; | |
8365 | ins->active_seg_prefix = PREFIX_FS; | |
252b5132 RH |
8366 | break; |
8367 | case 0x65: | |
39fb3698 VM |
8368 | ins->prefixes |= PREFIX_GS; |
8369 | ins->last_seg_prefix = i; | |
8370 | ins->active_seg_prefix = PREFIX_GS; | |
252b5132 RH |
8371 | break; |
8372 | case 0x66: | |
39fb3698 VM |
8373 | ins->prefixes |= PREFIX_DATA; |
8374 | ins->last_data_prefix = i; | |
252b5132 RH |
8375 | break; |
8376 | case 0x67: | |
39fb3698 VM |
8377 | ins->prefixes |= PREFIX_ADDR; |
8378 | ins->last_addr_prefix = i; | |
252b5132 | 8379 | break; |
5076851f | 8380 | case FWAIT_OPCODE: |
252b5132 RH |
8381 | /* fwait is really an instruction. If there are prefixes |
8382 | before the fwait, they belong to the fwait, *not* to the | |
8383 | following instruction. */ | |
39fb3698 VM |
8384 | ins->fwait_prefix = i; |
8385 | if (ins->prefixes || ins->rex) | |
252b5132 | 8386 | { |
39fb3698 VM |
8387 | ins->prefixes |= PREFIX_FWAIT; |
8388 | ins->codep++; | |
6c067bbb RM |
8389 | /* This ensures that the previous REX prefixes are noticed |
8390 | as unused prefixes, as in the return case below. */ | |
bf4d07d5 | 8391 | return ins->rex ? ckp_bogus : ckp_okay; |
252b5132 | 8392 | } |
39fb3698 | 8393 | ins->prefixes = PREFIX_FWAIT; |
252b5132 RH |
8394 | break; |
8395 | default: | |
bf4d07d5 | 8396 | return ckp_okay; |
252b5132 | 8397 | } |
52b15da3 | 8398 | /* Rex is ignored when followed by another prefix. */ |
39fb3698 | 8399 | if (ins->rex) |
bf4d07d5 | 8400 | return ckp_bogus; |
a4aa034a JB |
8401 | if (*ins->codep != FWAIT_OPCODE) |
8402 | ins->all_prefixes[i++] = *ins->codep; | |
39fb3698 VM |
8403 | ins->rex = newrex; |
8404 | ins->codep++; | |
f16cd0d5 L |
8405 | length++; |
8406 | } | |
bf4d07d5 | 8407 | return ckp_bogus; |
f16cd0d5 L |
8408 | } |
8409 | ||
7d421014 ILT |
8410 | /* Return the name of the prefix byte PREF, or NULL if PREF is not a |
8411 | prefix byte. */ | |
8412 | ||
8413 | static const char * | |
a4aa034a | 8414 | prefix_name (enum address_mode mode, uint8_t pref, int sizeflag) |
7d421014 | 8415 | { |
0003779b L |
8416 | static const char *rexes [16] = |
8417 | { | |
8418 | "rex", /* 0x40 */ | |
8419 | "rex.B", /* 0x41 */ | |
8420 | "rex.X", /* 0x42 */ | |
8421 | "rex.XB", /* 0x43 */ | |
8422 | "rex.R", /* 0x44 */ | |
8423 | "rex.RB", /* 0x45 */ | |
8424 | "rex.RX", /* 0x46 */ | |
8425 | "rex.RXB", /* 0x47 */ | |
8426 | "rex.W", /* 0x48 */ | |
8427 | "rex.WB", /* 0x49 */ | |
8428 | "rex.WX", /* 0x4a */ | |
8429 | "rex.WXB", /* 0x4b */ | |
8430 | "rex.WR", /* 0x4c */ | |
8431 | "rex.WRB", /* 0x4d */ | |
8432 | "rex.WRX", /* 0x4e */ | |
8433 | "rex.WRXB", /* 0x4f */ | |
8434 | }; | |
8435 | ||
7d421014 ILT |
8436 | switch (pref) |
8437 | { | |
52b15da3 JH |
8438 | /* REX prefixes family. */ |
8439 | case 0x40: | |
52b15da3 | 8440 | case 0x41: |
52b15da3 | 8441 | case 0x42: |
52b15da3 | 8442 | case 0x43: |
52b15da3 | 8443 | case 0x44: |
52b15da3 | 8444 | case 0x45: |
52b15da3 | 8445 | case 0x46: |
52b15da3 | 8446 | case 0x47: |
52b15da3 | 8447 | case 0x48: |
52b15da3 | 8448 | case 0x49: |
52b15da3 | 8449 | case 0x4a: |
52b15da3 | 8450 | case 0x4b: |
52b15da3 | 8451 | case 0x4c: |
52b15da3 | 8452 | case 0x4d: |
52b15da3 | 8453 | case 0x4e: |
52b15da3 | 8454 | case 0x4f: |
0003779b | 8455 | return rexes [pref - 0x40]; |
7d421014 ILT |
8456 | case 0xf3: |
8457 | return "repz"; | |
8458 | case 0xf2: | |
8459 | return "repnz"; | |
8460 | case 0xf0: | |
8461 | return "lock"; | |
8462 | case 0x2e: | |
8463 | return "cs"; | |
8464 | case 0x36: | |
8465 | return "ss"; | |
8466 | case 0x3e: | |
8467 | return "ds"; | |
8468 | case 0x26: | |
8469 | return "es"; | |
8470 | case 0x64: | |
8471 | return "fs"; | |
8472 | case 0x65: | |
8473 | return "gs"; | |
8474 | case 0x66: | |
8475 | return (sizeflag & DFLAG) ? "data16" : "data32"; | |
8476 | case 0x67: | |
ffe983ed | 8477 | if (mode == mode_64bit) |
db6eb5be | 8478 | return (sizeflag & AFLAG) ? "addr32" : "addr64"; |
c1a64871 | 8479 | else |
2888cb7a | 8480 | return (sizeflag & AFLAG) ? "addr16" : "addr32"; |
7d421014 ILT |
8481 | case FWAIT_OPCODE: |
8482 | return "fwait"; | |
f16cd0d5 L |
8483 | case REP_PREFIX: |
8484 | return "rep"; | |
42164a71 L |
8485 | case XACQUIRE_PREFIX: |
8486 | return "xacquire"; | |
8487 | case XRELEASE_PREFIX: | |
8488 | return "xrelease"; | |
7e8b059b L |
8489 | case BND_PREFIX: |
8490 | return "bnd"; | |
04ef582a L |
8491 | case NOTRACK_PREFIX: |
8492 | return "notrack"; | |
7d421014 ILT |
8493 | default: |
8494 | return NULL; | |
8495 | } | |
8496 | } | |
8497 | ||
f59a29b9 L |
8498 | void |
8499 | print_i386_disassembler_options (FILE *stream) | |
8500 | { | |
8501 | fprintf (stream, _("\n\ | |
8502 | The following i386/x86-64 specific disassembler options are supported for use\n\ | |
8503 | with the -M switch (multiple options should be separated by commas):\n")); | |
8504 | ||
8505 | fprintf (stream, _(" x86-64 Disassemble in 64bit mode\n")); | |
8506 | fprintf (stream, _(" i386 Disassemble in 32bit mode\n")); | |
8507 | fprintf (stream, _(" i8086 Disassemble in 16bit mode\n")); | |
8508 | fprintf (stream, _(" att Display instruction in AT&T syntax\n")); | |
8509 | fprintf (stream, _(" intel Display instruction in Intel syntax\n")); | |
9d141669 L |
8510 | fprintf (stream, _(" att-mnemonic\n" |
8511 | " Display instruction in AT&T mnemonic\n")); | |
8512 | fprintf (stream, _(" intel-mnemonic\n" | |
8513 | " Display instruction in Intel mnemonic\n")); | |
f59a29b9 L |
8514 | fprintf (stream, _(" addr64 Assume 64bit address size\n")); |
8515 | fprintf (stream, _(" addr32 Assume 32bit address size\n")); | |
8516 | fprintf (stream, _(" addr16 Assume 16bit address size\n")); | |
8517 | fprintf (stream, _(" data32 Assume 32bit data size\n")); | |
8518 | fprintf (stream, _(" data16 Assume 16bit data size\n")); | |
8519 | fprintf (stream, _(" suffix Always display instruction suffix in AT&T syntax\n")); | |
5db04b09 L |
8520 | fprintf (stream, _(" amd64 Display instruction in AMD64 ISA\n")); |
8521 | fprintf (stream, _(" intel64 Display instruction in Intel64 ISA\n")); | |
f59a29b9 L |
8522 | } |
8523 | ||
592d1631 | 8524 | /* Bad opcode. */ |
bf890a93 | 8525 | static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 }; |
592d1631 | 8526 | |
0b51ac42 JB |
8527 | /* Fetch error indicator. */ |
8528 | static const struct dis386 err_opcode = { NULL, { XX }, 0 }; | |
8529 | ||
b844680a L |
8530 | /* Get a pointer to struct dis386 with a valid name. */ |
8531 | ||
8532 | static const struct dis386 * | |
39fb3698 | 8533 | get_valid_dis386 (const struct dis386 *dp, instr_info *ins) |
b844680a | 8534 | { |
91d6fa6a | 8535 | int vindex, vex_table_index; |
b844680a L |
8536 | |
8537 | if (dp->name != NULL) | |
8538 | return dp; | |
8539 | ||
8540 | switch (dp->op[0].bytemode) | |
8541 | { | |
1ceb70f8 | 8542 | case USE_REG_TABLE: |
39fb3698 | 8543 | dp = ®_table[dp->op[1].bytemode][ins->modrm.reg]; |
1ceb70f8 L |
8544 | break; |
8545 | ||
8546 | case USE_MOD_TABLE: | |
39fb3698 | 8547 | vindex = ins->modrm.mod == 0x3 ? 1 : 0; |
91d6fa6a | 8548 | dp = &mod_table[dp->op[1].bytemode][vindex]; |
1ceb70f8 L |
8549 | break; |
8550 | ||
8551 | case USE_RM_TABLE: | |
39fb3698 | 8552 | dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm]; |
b844680a L |
8553 | break; |
8554 | ||
4e7d34a6 | 8555 | case USE_PREFIX_TABLE: |
39fb3698 | 8556 | if (ins->need_vex) |
b844680a | 8557 | { |
c0f3af97 | 8558 | /* The prefix in VEX is implicit. */ |
39fb3698 | 8559 | switch (ins->vex.prefix) |
c0f3af97 L |
8560 | { |
8561 | case 0: | |
91d6fa6a | 8562 | vindex = 0; |
c0f3af97 L |
8563 | break; |
8564 | case REPE_PREFIX_OPCODE: | |
91d6fa6a | 8565 | vindex = 1; |
c0f3af97 L |
8566 | break; |
8567 | case DATA_PREFIX_OPCODE: | |
91d6fa6a | 8568 | vindex = 2; |
c0f3af97 L |
8569 | break; |
8570 | case REPNE_PREFIX_OPCODE: | |
91d6fa6a | 8571 | vindex = 3; |
c0f3af97 L |
8572 | break; |
8573 | default: | |
8574 | abort (); | |
8575 | break; | |
8576 | } | |
b844680a | 8577 | } |
7bb15c6f | 8578 | else |
b844680a | 8579 | { |
285ca992 L |
8580 | int last_prefix = -1; |
8581 | int prefix = 0; | |
91d6fa6a | 8582 | vindex = 0; |
285ca992 L |
8583 | /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA. |
8584 | When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the | |
8585 | last one wins. */ | |
39fb3698 | 8586 | if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) |
b844680a | 8587 | { |
39fb3698 | 8588 | if (ins->last_repz_prefix > ins->last_repnz_prefix) |
c0f3af97 | 8589 | { |
285ca992 L |
8590 | vindex = 1; |
8591 | prefix = PREFIX_REPZ; | |
39fb3698 | 8592 | last_prefix = ins->last_repz_prefix; |
c0f3af97 L |
8593 | } |
8594 | else | |
b844680a | 8595 | { |
285ca992 L |
8596 | vindex = 3; |
8597 | prefix = PREFIX_REPNZ; | |
39fb3698 | 8598 | last_prefix = ins->last_repnz_prefix; |
b844680a | 8599 | } |
285ca992 | 8600 | |
507bd325 L |
8601 | /* Check if prefix should be ignored. */ |
8602 | if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement | |
8603 | & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT) | |
31941983 JB |
8604 | & prefix) != 0 |
8605 | && !prefix_table[dp->op[1].bytemode][vindex].name) | |
285ca992 L |
8606 | vindex = 0; |
8607 | } | |
8608 | ||
39fb3698 | 8609 | if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0) |
285ca992 L |
8610 | { |
8611 | vindex = 2; | |
8612 | prefix = PREFIX_DATA; | |
39fb3698 | 8613 | last_prefix = ins->last_data_prefix; |
285ca992 L |
8614 | } |
8615 | ||
8616 | if (vindex != 0) | |
8617 | { | |
39fb3698 VM |
8618 | ins->used_prefixes |= prefix; |
8619 | ins->all_prefixes[last_prefix] = 0; | |
b844680a L |
8620 | } |
8621 | } | |
91d6fa6a | 8622 | dp = &prefix_table[dp->op[1].bytemode][vindex]; |
b844680a L |
8623 | break; |
8624 | ||
4e7d34a6 | 8625 | case USE_X86_64_TABLE: |
39fb3698 | 8626 | vindex = ins->address_mode == mode_64bit ? 1 : 0; |
91d6fa6a | 8627 | dp = &x86_64_table[dp->op[1].bytemode][vindex]; |
b844680a L |
8628 | break; |
8629 | ||
4e7d34a6 | 8630 | case USE_3BYTE_TABLE: |
0b51ac42 JB |
8631 | if (!fetch_code (ins->info, ins->codep + 2)) |
8632 | return &err_opcode; | |
a4aa034a | 8633 | vindex = *ins->codep++; |
91d6fa6a | 8634 | dp = &three_byte_table[dp->op[1].bytemode][vindex]; |
39fb3698 | 8635 | ins->end_codep = ins->codep; |
0b51ac42 JB |
8636 | if (!fetch_modrm (ins)) |
8637 | return &err_opcode; | |
8bb15339 L |
8638 | break; |
8639 | ||
c0f3af97 | 8640 | case USE_VEX_LEN_TABLE: |
39fb3698 | 8641 | if (!ins->need_vex) |
c0f3af97 L |
8642 | abort (); |
8643 | ||
39fb3698 | 8644 | switch (ins->vex.length) |
c0f3af97 L |
8645 | { |
8646 | case 128: | |
91d6fa6a | 8647 | vindex = 0; |
c0f3af97 | 8648 | break; |
85ba7507 JB |
8649 | case 512: |
8650 | /* This allows re-using in particular table entries where only | |
8651 | 128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid. */ | |
39fb3698 | 8652 | if (ins->vex.evex) |
85ba7507 | 8653 | { |
c0f3af97 | 8654 | case 256: |
85ba7507 JB |
8655 | vindex = 1; |
8656 | break; | |
8657 | } | |
8658 | /* Fall through. */ | |
c0f3af97 L |
8659 | default: |
8660 | abort (); | |
8661 | break; | |
8662 | } | |
8663 | ||
91d6fa6a | 8664 | dp = &vex_len_table[dp->op[1].bytemode][vindex]; |
c0f3af97 L |
8665 | break; |
8666 | ||
04e2a182 | 8667 | case USE_EVEX_LEN_TABLE: |
39fb3698 | 8668 | if (!ins->vex.evex) |
04e2a182 L |
8669 | abort (); |
8670 | ||
39fb3698 | 8671 | switch (ins->vex.length) |
04e2a182 L |
8672 | { |
8673 | case 128: | |
8674 | vindex = 0; | |
8675 | break; | |
8676 | case 256: | |
8677 | vindex = 1; | |
8678 | break; | |
8679 | case 512: | |
8680 | vindex = 2; | |
8681 | break; | |
8682 | default: | |
8683 | abort (); | |
8684 | break; | |
8685 | } | |
8686 | ||
8687 | dp = &evex_len_table[dp->op[1].bytemode][vindex]; | |
8688 | break; | |
8689 | ||
f88c9eb0 | 8690 | case USE_XOP_8F_TABLE: |
0b51ac42 JB |
8691 | if (!fetch_code (ins->info, ins->codep + 3)) |
8692 | return &err_opcode; | |
39fb3698 | 8693 | ins->rex = ~(*ins->codep >> 5) & 0x7; |
f88c9eb0 SP |
8694 | |
8695 | /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm". */ | |
39fb3698 | 8696 | switch ((*ins->codep & 0x1f)) |
f88c9eb0 SP |
8697 | { |
8698 | default: | |
f07af43e L |
8699 | dp = &bad_opcode; |
8700 | return dp; | |
5dd85c99 SP |
8701 | case 0x8: |
8702 | vex_table_index = XOP_08; | |
8703 | break; | |
f88c9eb0 SP |
8704 | case 0x9: |
8705 | vex_table_index = XOP_09; | |
8706 | break; | |
8707 | case 0xa: | |
8708 | vex_table_index = XOP_0A; | |
8709 | break; | |
8710 | } | |
39fb3698 VM |
8711 | ins->codep++; |
8712 | ins->vex.w = *ins->codep & 0x80; | |
8713 | if (ins->vex.w && ins->address_mode == mode_64bit) | |
8714 | ins->rex |= REX_W; | |
f88c9eb0 | 8715 | |
39fb3698 VM |
8716 | ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; |
8717 | if (ins->address_mode != mode_64bit) | |
f07af43e | 8718 | { |
abfcb414 | 8719 | /* In 16/32-bit mode REX_B is silently ignored. */ |
39fb3698 | 8720 | ins->rex &= ~REX_B; |
f07af43e | 8721 | } |
f88c9eb0 | 8722 | |
39fb3698 VM |
8723 | ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; |
8724 | switch ((*ins->codep & 0x3)) | |
f88c9eb0 SP |
8725 | { |
8726 | case 0: | |
f88c9eb0 SP |
8727 | break; |
8728 | case 1: | |
39fb3698 | 8729 | ins->vex.prefix = DATA_PREFIX_OPCODE; |
f88c9eb0 SP |
8730 | break; |
8731 | case 2: | |
39fb3698 | 8732 | ins->vex.prefix = REPE_PREFIX_OPCODE; |
f88c9eb0 SP |
8733 | break; |
8734 | case 3: | |
39fb3698 | 8735 | ins->vex.prefix = REPNE_PREFIX_OPCODE; |
f88c9eb0 SP |
8736 | break; |
8737 | } | |
b5c37946 | 8738 | ins->need_vex = 3; |
39fb3698 | 8739 | ins->codep++; |
a4aa034a | 8740 | vindex = *ins->codep++; |
91d6fa6a | 8741 | dp = &xop_table[vex_table_index][vindex]; |
c48244a5 | 8742 | |
39fb3698 | 8743 | ins->end_codep = ins->codep; |
0b51ac42 JB |
8744 | if (!fetch_modrm (ins)) |
8745 | return &err_opcode; | |
b5b098c2 JB |
8746 | |
8747 | /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid | |
8748 | having to decode the bits for every otherwise valid encoding. */ | |
39fb3698 | 8749 | if (ins->vex.prefix) |
b5b098c2 | 8750 | return &bad_opcode; |
f88c9eb0 SP |
8751 | break; |
8752 | ||
c0f3af97 | 8753 | case USE_VEX_C4_TABLE: |
43234a1e | 8754 | /* VEX prefix. */ |
0b51ac42 JB |
8755 | if (!fetch_code (ins->info, ins->codep + 3)) |
8756 | return &err_opcode; | |
39fb3698 VM |
8757 | ins->rex = ~(*ins->codep >> 5) & 0x7; |
8758 | switch ((*ins->codep & 0x1f)) | |
c0f3af97 L |
8759 | { |
8760 | default: | |
f07af43e L |
8761 | dp = &bad_opcode; |
8762 | return dp; | |
c0f3af97 | 8763 | case 0x1: |
f88c9eb0 | 8764 | vex_table_index = VEX_0F; |
c0f3af97 L |
8765 | break; |
8766 | case 0x2: | |
f88c9eb0 | 8767 | vex_table_index = VEX_0F38; |
c0f3af97 L |
8768 | break; |
8769 | case 0x3: | |
f88c9eb0 | 8770 | vex_table_index = VEX_0F3A; |
c0f3af97 L |
8771 | break; |
8772 | } | |
39fb3698 VM |
8773 | ins->codep++; |
8774 | ins->vex.w = *ins->codep & 0x80; | |
8775 | if (ins->address_mode == mode_64bit) | |
f07af43e | 8776 | { |
39fb3698 VM |
8777 | if (ins->vex.w) |
8778 | ins->rex |= REX_W; | |
9889cbb1 L |
8779 | } |
8780 | else | |
8781 | { | |
8782 | /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit | |
8783 | is ignored, other REX bits are 0 and the highest bit in | |
5f847646 | 8784 | VEX.vvvv is also ignored (but we mustn't clear it here). */ |
39fb3698 | 8785 | ins->rex = 0; |
f07af43e | 8786 | } |
39fb3698 VM |
8787 | ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; |
8788 | ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; | |
8789 | switch ((*ins->codep & 0x3)) | |
c0f3af97 L |
8790 | { |
8791 | case 0: | |
c0f3af97 L |
8792 | break; |
8793 | case 1: | |
39fb3698 | 8794 | ins->vex.prefix = DATA_PREFIX_OPCODE; |
c0f3af97 L |
8795 | break; |
8796 | case 2: | |
39fb3698 | 8797 | ins->vex.prefix = REPE_PREFIX_OPCODE; |
c0f3af97 L |
8798 | break; |
8799 | case 3: | |
39fb3698 | 8800 | ins->vex.prefix = REPNE_PREFIX_OPCODE; |
c0f3af97 L |
8801 | break; |
8802 | } | |
b5c37946 | 8803 | ins->need_vex = 3; |
39fb3698 | 8804 | ins->codep++; |
a4aa034a | 8805 | vindex = *ins->codep++; |
91d6fa6a | 8806 | dp = &vex_table[vex_table_index][vindex]; |
39fb3698 | 8807 | ins->end_codep = ins->codep; |
53c4d625 | 8808 | /* There is no MODRM byte for VEX0F 77. */ |
0b51ac42 JB |
8809 | if ((vex_table_index != VEX_0F || vindex != 0x77) |
8810 | && !fetch_modrm (ins)) | |
8811 | return &err_opcode; | |
c0f3af97 L |
8812 | break; |
8813 | ||
8814 | case USE_VEX_C5_TABLE: | |
43234a1e | 8815 | /* VEX prefix. */ |
0b51ac42 JB |
8816 | if (!fetch_code (ins->info, ins->codep + 2)) |
8817 | return &err_opcode; | |
39fb3698 | 8818 | ins->rex = (*ins->codep & 0x80) ? 0 : REX_R; |
c0f3af97 | 8819 | |
9889cbb1 L |
8820 | /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in |
8821 | VEX.vvvv is 1. */ | |
39fb3698 VM |
8822 | ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; |
8823 | ins->vex.length = (*ins->codep & 0x4) ? 256 : 128; | |
8824 | switch ((*ins->codep & 0x3)) | |
c0f3af97 L |
8825 | { |
8826 | case 0: | |
c0f3af97 L |
8827 | break; |
8828 | case 1: | |
39fb3698 | 8829 | ins->vex.prefix = DATA_PREFIX_OPCODE; |
c0f3af97 L |
8830 | break; |
8831 | case 2: | |
39fb3698 | 8832 | ins->vex.prefix = REPE_PREFIX_OPCODE; |
c0f3af97 L |
8833 | break; |
8834 | case 3: | |
39fb3698 | 8835 | ins->vex.prefix = REPNE_PREFIX_OPCODE; |
c0f3af97 L |
8836 | break; |
8837 | } | |
b5c37946 | 8838 | ins->need_vex = 2; |
39fb3698 | 8839 | ins->codep++; |
a4aa034a | 8840 | vindex = *ins->codep++; |
b5c37946 | 8841 | dp = &vex_table[VEX_0F][vindex]; |
39fb3698 | 8842 | ins->end_codep = ins->codep; |
53c4d625 | 8843 | /* There is no MODRM byte for VEX 77. */ |
0b51ac42 JB |
8844 | if (vindex != 0x77 && !fetch_modrm (ins)) |
8845 | return &err_opcode; | |
c0f3af97 L |
8846 | break; |
8847 | ||
9e30b8e0 | 8848 | case USE_VEX_W_TABLE: |
39fb3698 | 8849 | if (!ins->need_vex) |
9e30b8e0 L |
8850 | abort (); |
8851 | ||
ab31da6a | 8852 | dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w]; |
9e30b8e0 L |
8853 | break; |
8854 | ||
43234a1e | 8855 | case USE_EVEX_TABLE: |
ab31da6a | 8856 | ins->two_source_ops = false; |
43234a1e | 8857 | /* EVEX prefix. */ |
ab31da6a | 8858 | ins->vex.evex = true; |
0b51ac42 JB |
8859 | if (!fetch_code (ins->info, ins->codep + 4)) |
8860 | return &err_opcode; | |
43234a1e | 8861 | /* The first byte after 0x62. */ |
39fb3698 VM |
8862 | ins->rex = ~(*ins->codep >> 5) & 0x7; |
8863 | ins->vex.r = *ins->codep & 0x10; | |
8864 | switch ((*ins->codep & 0xf)) | |
43234a1e L |
8865 | { |
8866 | default: | |
8867 | return &bad_opcode; | |
8868 | case 0x1: | |
8869 | vex_table_index = EVEX_0F; | |
8870 | break; | |
8871 | case 0x2: | |
8872 | vex_table_index = EVEX_0F38; | |
8873 | break; | |
8874 | case 0x3: | |
8875 | vex_table_index = EVEX_0F3A; | |
8876 | break; | |
0cc78721 CL |
8877 | case 0x5: |
8878 | vex_table_index = EVEX_MAP5; | |
8879 | break; | |
8880 | case 0x6: | |
8881 | vex_table_index = EVEX_MAP6; | |
8882 | break; | |
43234a1e L |
8883 | } |
8884 | ||
8885 | /* The second byte after 0x62. */ | |
39fb3698 VM |
8886 | ins->codep++; |
8887 | ins->vex.w = *ins->codep & 0x80; | |
8888 | if (ins->vex.w && ins->address_mode == mode_64bit) | |
8889 | ins->rex |= REX_W; | |
43234a1e | 8890 | |
39fb3698 | 8891 | ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf; |
43234a1e L |
8892 | |
8893 | /* The U bit. */ | |
39fb3698 | 8894 | if (!(*ins->codep & 0x4)) |
43234a1e L |
8895 | return &bad_opcode; |
8896 | ||
39fb3698 | 8897 | switch ((*ins->codep & 0x3)) |
43234a1e L |
8898 | { |
8899 | case 0: | |
43234a1e L |
8900 | break; |
8901 | case 1: | |
39fb3698 | 8902 | ins->vex.prefix = DATA_PREFIX_OPCODE; |
43234a1e L |
8903 | break; |
8904 | case 2: | |
39fb3698 | 8905 | ins->vex.prefix = REPE_PREFIX_OPCODE; |
43234a1e L |
8906 | break; |
8907 | case 3: | |
39fb3698 | 8908 | ins->vex.prefix = REPNE_PREFIX_OPCODE; |
43234a1e L |
8909 | break; |
8910 | } | |
8911 | ||
8912 | /* The third byte after 0x62. */ | |
39fb3698 | 8913 | ins->codep++; |
43234a1e L |
8914 | |
8915 | /* Remember the static rounding bits. */ | |
39fb3698 | 8916 | ins->vex.ll = (*ins->codep >> 5) & 3; |
ab31da6a | 8917 | ins->vex.b = *ins->codep & 0x10; |
43234a1e | 8918 | |
39fb3698 VM |
8919 | ins->vex.v = *ins->codep & 0x8; |
8920 | ins->vex.mask_register_specifier = *ins->codep & 0x7; | |
8921 | ins->vex.zeroing = *ins->codep & 0x80; | |
43234a1e | 8922 | |
39fb3698 | 8923 | if (ins->address_mode != mode_64bit) |
5f847646 JB |
8924 | { |
8925 | /* In 16/32-bit mode silently ignore following bits. */ | |
39fb3698 | 8926 | ins->rex &= ~REX_B; |
ab31da6a | 8927 | ins->vex.r = true; |
5f847646 JB |
8928 | } |
8929 | ||
b5c37946 | 8930 | ins->need_vex = 4; |
39fb3698 | 8931 | ins->codep++; |
a4aa034a | 8932 | vindex = *ins->codep++; |
43234a1e | 8933 | dp = &evex_table[vex_table_index][vindex]; |
39fb3698 | 8934 | ins->end_codep = ins->codep; |
0b51ac42 JB |
8935 | if (!fetch_modrm (ins)) |
8936 | return &err_opcode; | |
43234a1e L |
8937 | |
8938 | /* Set vector length. */ | |
39fb3698 VM |
8939 | if (ins->modrm.mod == 3 && ins->vex.b) |
8940 | ins->vex.length = 512; | |
43234a1e L |
8941 | else |
8942 | { | |
39fb3698 | 8943 | switch (ins->vex.ll) |
43234a1e L |
8944 | { |
8945 | case 0x0: | |
39fb3698 | 8946 | ins->vex.length = 128; |
43234a1e L |
8947 | break; |
8948 | case 0x1: | |
39fb3698 | 8949 | ins->vex.length = 256; |
43234a1e L |
8950 | break; |
8951 | case 0x2: | |
39fb3698 | 8952 | ins->vex.length = 512; |
43234a1e L |
8953 | break; |
8954 | default: | |
8955 | return &bad_opcode; | |
8956 | } | |
8957 | } | |
8958 | break; | |
8959 | ||
592d1631 L |
8960 | case 0: |
8961 | dp = &bad_opcode; | |
8962 | break; | |
8963 | ||
b844680a | 8964 | default: |
d34b5006 | 8965 | abort (); |
b844680a L |
8966 | } |
8967 | ||
8968 | if (dp->name != NULL) | |
8969 | return dp; | |
8970 | else | |
39fb3698 | 8971 | return get_valid_dis386 (dp, ins); |
b844680a L |
8972 | } |
8973 | ||
06173b5d | 8974 | static bool |
39fb3698 | 8975 | get_sib (instr_info *ins, int sizeflag) |
dfc8cf43 L |
8976 | { |
8977 | /* If modrm.mod == 3, operand must be register. */ | |
39fb3698 VM |
8978 | if (ins->need_modrm |
8979 | && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) | |
8980 | && ins->modrm.mod != 3 | |
8981 | && ins->modrm.rm == 4) | |
dfc8cf43 | 8982 | { |
06173b5d JB |
8983 | if (!fetch_code (ins->info, ins->codep + 2)) |
8984 | return false; | |
39fb3698 VM |
8985 | ins->sib.index = (ins->codep[1] >> 3) & 7; |
8986 | ins->sib.scale = (ins->codep[1] >> 6) & 3; | |
8987 | ins->sib.base = ins->codep[1] & 7; | |
ce20459e | 8988 | ins->has_sib = true; |
dfc8cf43 | 8989 | } |
ce20459e L |
8990 | else |
8991 | ins->has_sib = false; | |
06173b5d JB |
8992 | |
8993 | return true; | |
dfc8cf43 L |
8994 | } |
8995 | ||
2aa11c29 JB |
8996 | /* Like oappend_with_style (below) but always with text style. */ |
8997 | ||
8998 | static void | |
8999 | oappend (instr_info *ins, const char *s) | |
9000 | { | |
9001 | oappend_with_style (ins, s, dis_style_text); | |
9002 | } | |
9003 | ||
9004 | /* Like oappend (above), but S is a string starting with '%'. In | |
95ff6718 | 9005 | Intel syntax, the '%' is elided. */ |
2c3b9a91 | 9006 | |
e564475a | 9007 | static void |
2c3b9a91 AB |
9008 | oappend_register (instr_info *ins, const char *s) |
9009 | { | |
95ff6718 | 9010 | oappend_with_style (ins, s + ins->intel_syntax, dis_style_register); |
2c3b9a91 AB |
9011 | } |
9012 | ||
9013 | /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT. | |
9014 | STYLE is the default style to use in the fprintf_styled_func calls, | |
9015 | however, FMT might include embedded style markers (see oappend_style), | |
9016 | these embedded markers are not printed, but instead change the style | |
ac3fe48f | 9017 | used in the next fprintf_styled_func call. */ |
2c3b9a91 | 9018 | |
ac3fe48f | 9019 | static void ATTRIBUTE_PRINTF_3 |
e4452aa6 | 9020 | i386_dis_printf (const disassemble_info *info, enum disassembler_style style, |
2c3b9a91 | 9021 | const char *fmt, ...) |
e564475a | 9022 | { |
2c3b9a91 AB |
9023 | va_list ap; |
9024 | enum disassembler_style curr_style = style; | |
ac3fe48f JB |
9025 | const char *start, *curr; |
9026 | char staging_area[40]; | |
2c3b9a91 AB |
9027 | |
9028 | va_start (ap, fmt); | |
ac3fe48f JB |
9029 | /* In particular print_insn()'s processing of op_txt[] can hand rather long |
9030 | strings here. Bypass vsnprintf() in such cases to avoid capacity issues | |
9031 | with the staging area. */ | |
9032 | if (strcmp (fmt, "%s")) | |
9033 | { | |
9034 | int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap); | |
2c3b9a91 | 9035 | |
ac3fe48f | 9036 | va_end (ap); |
2c3b9a91 | 9037 | |
ac3fe48f JB |
9038 | if (res < 0) |
9039 | return; | |
2c3b9a91 | 9040 | |
ac3fe48f JB |
9041 | if ((size_t) res >= sizeof (staging_area)) |
9042 | abort (); | |
9043 | ||
9044 | start = curr = staging_area; | |
9045 | } | |
9046 | else | |
9047 | { | |
9048 | start = curr = va_arg (ap, const char *); | |
9049 | va_end (ap); | |
9050 | } | |
2c3b9a91 AB |
9051 | |
9052 | do | |
9053 | { | |
9054 | if (*curr == '\0' | |
9055 | || (*curr == STYLE_MARKER_CHAR | |
9056 | && ISXDIGIT (*(curr + 1)) | |
9057 | && *(curr + 2) == STYLE_MARKER_CHAR)) | |
9058 | { | |
9059 | /* Output content between our START position and CURR. */ | |
9060 | int len = curr - start; | |
e4452aa6 JB |
9061 | int n = (*info->fprintf_styled_func) (info->stream, curr_style, |
9062 | "%.*s", len, start); | |
2c3b9a91 | 9063 | if (n < 0) |
ac3fe48f | 9064 | break; |
2c3b9a91 AB |
9065 | |
9066 | if (*curr == '\0') | |
9067 | break; | |
9068 | ||
9069 | /* Skip over the initial STYLE_MARKER_CHAR. */ | |
9070 | ++curr; | |
9071 | ||
9072 | /* Update the CURR_STYLE. As there are less than 16 styles, it | |
9073 | is possible, that if the input is corrupted in some way, that | |
9074 | we might set CURR_STYLE to an invalid value. Don't worry | |
9075 | though, we check for this situation. */ | |
9076 | if (*curr >= '0' && *curr <= '9') | |
9077 | curr_style = (enum disassembler_style) (*curr - '0'); | |
9078 | else if (*curr >= 'a' && *curr <= 'f') | |
9079 | curr_style = (enum disassembler_style) (*curr - 'a' + 10); | |
9080 | else | |
9081 | curr_style = dis_style_text; | |
9082 | ||
9083 | /* Check for an invalid style having been selected. This should | |
9084 | never happen, but it doesn't hurt to be a little paranoid. */ | |
9085 | if (curr_style > dis_style_comment_start) | |
9086 | curr_style = dis_style_text; | |
9087 | ||
9088 | /* Skip the hex character, and the closing STYLE_MARKER_CHAR. */ | |
9089 | curr += 2; | |
9090 | ||
9091 | /* Reset the START to after the style marker. */ | |
9092 | start = curr; | |
9093 | } | |
9094 | else | |
9095 | ++curr; | |
9096 | } | |
9097 | while (true); | |
e564475a JB |
9098 | } |
9099 | ||
e396998b | 9100 | static int |
384e201e | 9101 | print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax) |
252b5132 | 9102 | { |
2da11e11 | 9103 | const struct dis386 *dp; |
252b5132 | 9104 | int i; |
5b720e50 | 9105 | int ret; |
ce518a5f | 9106 | char *op_txt[MAX_OPERANDS]; |
252b5132 | 9107 | int needcomma; |
90a00d6c | 9108 | bool intel_swap_2_3; |
df18fdba | 9109 | int sizeflag, orig_sizeflag; |
e396998b | 9110 | const char *p; |
252b5132 | 9111 | struct dis_private priv; |
f16cd0d5 | 9112 | int prefix_length; |
202be274 | 9113 | int op_count; |
384e201e JB |
9114 | instr_info ins = { |
9115 | .info = info, | |
9116 | .intel_syntax = intel_syntax >= 0 | |
9117 | ? intel_syntax | |
9118 | : (info->mach & bfd_mach_i386_intel_syntax) != 0, | |
9119 | .intel_mnemonic = !SYSV386_COMPAT, | |
9120 | .op_index[0 ... MAX_OPERANDS - 1] = -1, | |
9121 | .start_pc = pc, | |
9122 | .start_codep = priv.the_buffer, | |
9123 | .codep = priv.the_buffer, | |
9124 | .obufp = ins.obuf, | |
9125 | .last_lock_prefix = -1, | |
9126 | .last_repz_prefix = -1, | |
9127 | .last_repnz_prefix = -1, | |
9128 | .last_data_prefix = -1, | |
9129 | .last_addr_prefix = -1, | |
9130 | .last_rex_prefix = -1, | |
9131 | .last_seg_prefix = -1, | |
9132 | .fwait_prefix = -1, | |
9133 | }; | |
9096fc28 | 9134 | char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE]; |
252b5132 | 9135 | |
d7921315 | 9136 | priv.orig_sizeflag = AFLAG | DFLAG; |
384e201e JB |
9137 | if ((info->mach & bfd_mach_i386_i386) != 0) |
9138 | ins.address_mode = mode_32bit; | |
9139 | else if (info->mach == bfd_mach_i386_i8086) | |
d7921315 | 9140 | { |
384e201e | 9141 | ins.address_mode = mode_16bit; |
d7921315 L |
9142 | priv.orig_sizeflag = 0; |
9143 | } | |
2da11e11 | 9144 | else |
384e201e | 9145 | ins.address_mode = mode_64bit; |
e396998b | 9146 | |
384e201e | 9147 | for (p = info->disassembler_options; p != NULL;) |
e396998b | 9148 | { |
08dedd66 | 9149 | if (startswith (p, "amd64")) |
384e201e | 9150 | ins.isa64 = amd64; |
08dedd66 | 9151 | else if (startswith (p, "intel64")) |
384e201e | 9152 | ins.isa64 = intel64; |
08dedd66 | 9153 | else if (startswith (p, "x86-64")) |
e396998b | 9154 | { |
384e201e | 9155 | ins.address_mode = mode_64bit; |
2a1bb84c | 9156 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9157 | } |
08dedd66 | 9158 | else if (startswith (p, "i386")) |
e396998b | 9159 | { |
384e201e | 9160 | ins.address_mode = mode_32bit; |
2a1bb84c | 9161 | priv.orig_sizeflag |= AFLAG | DFLAG; |
e396998b | 9162 | } |
08dedd66 | 9163 | else if (startswith (p, "i8086")) |
e396998b | 9164 | { |
384e201e | 9165 | ins.address_mode = mode_16bit; |
2a1bb84c | 9166 | priv.orig_sizeflag &= ~(AFLAG | DFLAG); |
e396998b | 9167 | } |
08dedd66 | 9168 | else if (startswith (p, "intel")) |
e396998b | 9169 | { |
384e201e | 9170 | ins.intel_syntax = 1; |
08dedd66 | 9171 | if (startswith (p + 5, "-mnemonic")) |
384e201e | 9172 | ins.intel_mnemonic = true; |
e396998b | 9173 | } |
08dedd66 | 9174 | else if (startswith (p, "att")) |
e396998b | 9175 | { |
384e201e | 9176 | ins.intel_syntax = 0; |
08dedd66 | 9177 | if (startswith (p + 3, "-mnemonic")) |
384e201e | 9178 | ins.intel_mnemonic = false; |
e396998b | 9179 | } |
08dedd66 | 9180 | else if (startswith (p, "addr")) |
e396998b | 9181 | { |
384e201e | 9182 | if (ins.address_mode == mode_64bit) |
f59a29b9 L |
9183 | { |
9184 | if (p[4] == '3' && p[5] == '2') | |
9185 | priv.orig_sizeflag &= ~AFLAG; | |
9186 | else if (p[4] == '6' && p[5] == '4') | |
9187 | priv.orig_sizeflag |= AFLAG; | |
9188 | } | |
9189 | else | |
9190 | { | |
9191 | if (p[4] == '1' && p[5] == '6') | |
9192 | priv.orig_sizeflag &= ~AFLAG; | |
9193 | else if (p[4] == '3' && p[5] == '2') | |
9194 | priv.orig_sizeflag |= AFLAG; | |
9195 | } | |
e396998b | 9196 | } |
08dedd66 | 9197 | else if (startswith (p, "data")) |
e396998b AM |
9198 | { |
9199 | if (p[4] == '1' && p[5] == '6') | |
9200 | priv.orig_sizeflag &= ~DFLAG; | |
9201 | else if (p[4] == '3' && p[5] == '2') | |
9202 | priv.orig_sizeflag |= DFLAG; | |
9203 | } | |
08dedd66 | 9204 | else if (startswith (p, "suffix")) |
e396998b AM |
9205 | priv.orig_sizeflag |= SUFFIX_ALWAYS; |
9206 | ||
9207 | p = strchr (p, ','); | |
9208 | if (p != NULL) | |
9209 | p++; | |
9210 | } | |
9211 | ||
384e201e | 9212 | if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8) |
c0f92bf9 | 9213 | { |
e4452aa6 | 9214 | i386_dis_printf (info, dis_style_text, _("64-bit address is disabled")); |
c0f92bf9 L |
9215 | return -1; |
9216 | } | |
9217 | ||
384e201e | 9218 | if (ins.intel_syntax) |
e396998b | 9219 | { |
384e201e JB |
9220 | ins.open_char = '['; |
9221 | ins.close_char = ']'; | |
9222 | ins.separator_char = '+'; | |
9223 | ins.scale_char = '*'; | |
e396998b AM |
9224 | } |
9225 | else | |
9226 | { | |
384e201e JB |
9227 | ins.open_char = '('; |
9228 | ins.close_char = ')'; | |
9229 | ins.separator_char = ','; | |
9230 | ins.scale_char = ','; | |
e396998b | 9231 | } |
2da11e11 | 9232 | |
4fe53c98 | 9233 | /* The output looks better if we put 7 bytes on a line, since that |
526ca202 | 9234 | puts most long word instructions on a single line. */ |
384e201e | 9235 | info->bytes_per_line = 7; |
252b5132 | 9236 | |
384e201e | 9237 | info->private_data = &priv; |
1a3b4f90 | 9238 | priv.fetched = 0; |
252b5132 | 9239 | priv.insn_start = pc; |
252b5132 | 9240 | |
ce518a5f L |
9241 | for (i = 0; i < MAX_OPERANDS; ++i) |
9242 | { | |
384e201e JB |
9243 | op_out[i][0] = 0; |
9244 | ins.op_out[i] = op_out[i]; | |
ce518a5f | 9245 | } |
252b5132 | 9246 | |
f16cd0d5 L |
9247 | sizeflag = priv.orig_sizeflag; |
9248 | ||
bf4d07d5 | 9249 | switch (ckprefix (&ins)) |
f16cd0d5 | 9250 | { |
bf4d07d5 JB |
9251 | case ckp_okay: |
9252 | break; | |
9253 | ||
9254 | case ckp_bogus: | |
384e201e | 9255 | /* Too many prefixes or unused REX prefixes. */ |
f16cd0d5 | 9256 | for (i = 0; |
384e201e | 9257 | i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i]; |
f16cd0d5 | 9258 | i++) |
e4452aa6 | 9259 | i386_dis_printf (info, dis_style_mnemonic, "%s%s", |
2c3b9a91 | 9260 | (i == 0 ? "" : " "), |
ffe983ed JB |
9261 | prefix_name (ins.address_mode, ins.all_prefixes[i], |
9262 | sizeflag)); | |
5b720e50 AM |
9263 | ret = i; |
9264 | goto out; | |
bf4d07d5 JB |
9265 | |
9266 | case ckp_fetch_error: | |
5b720e50 | 9267 | goto fetch_error_out; |
f16cd0d5 | 9268 | } |
252b5132 | 9269 | |
1a3b4f90 | 9270 | ins.nr_prefixes = ins.codep - ins.start_codep; |
252b5132 | 9271 | |
06173b5d | 9272 | if (!fetch_code (info, ins.codep + 1)) |
5b720e50 AM |
9273 | { |
9274 | fetch_error_out: | |
9275 | ret = fetch_error (&ins); | |
9276 | goto out; | |
9277 | } | |
06173b5d | 9278 | |
a4aa034a | 9279 | ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8); |
252b5132 | 9280 | |
b4617f79 | 9281 | if ((ins.prefixes & PREFIX_FWAIT) |
a4aa034a | 9282 | && (*ins.codep < 0xd8 || *ins.codep > 0xdf)) |
252b5132 | 9283 | { |
384e201e JB |
9284 | /* Handle ins.prefixes before fwait. */ |
9285 | for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i]; | |
86a80a50 | 9286 | i++) |
e4452aa6 | 9287 | i386_dis_printf (info, dis_style_mnemonic, "%s ", |
ffe983ed JB |
9288 | prefix_name (ins.address_mode, ins.all_prefixes[i], |
9289 | sizeflag)); | |
e4452aa6 | 9290 | i386_dis_printf (info, dis_style_mnemonic, "fwait"); |
5b720e50 AM |
9291 | ret = i + 1; |
9292 | goto out; | |
252b5132 RH |
9293 | } |
9294 | ||
a4aa034a | 9295 | if (*ins.codep == 0x0f) |
252b5132 | 9296 | { |
eec0f4ca | 9297 | unsigned char threebyte; |
5f40e14d | 9298 | |
384e201e | 9299 | ins.codep++; |
06173b5d | 9300 | if (!fetch_code (info, ins.codep + 1)) |
5b720e50 | 9301 | goto fetch_error_out; |
a4aa034a | 9302 | threebyte = *ins.codep; |
eec0f4ca | 9303 | dp = &dis386_twobyte[threebyte]; |
384e201e JB |
9304 | ins.need_modrm = twobyte_has_modrm[threebyte]; |
9305 | ins.codep++; | |
252b5132 RH |
9306 | } |
9307 | else | |
9308 | { | |
a4aa034a JB |
9309 | dp = &dis386[*ins.codep]; |
9310 | ins.need_modrm = onebyte_has_modrm[*ins.codep]; | |
384e201e | 9311 | ins.codep++; |
252b5132 | 9312 | } |
246c51aa | 9313 | |
384e201e | 9314 | /* Save sizeflag for printing the extra ins.prefixes later before updating |
df18fdba L |
9315 | it for mnemonic and operand processing. The prefix names depend |
9316 | only on the address mode. */ | |
9317 | orig_sizeflag = sizeflag; | |
384e201e | 9318 | if (ins.prefixes & PREFIX_ADDR) |
df18fdba | 9319 | sizeflag ^= AFLAG; |
384e201e | 9320 | if ((ins.prefixes & PREFIX_DATA)) |
df18fdba | 9321 | sizeflag ^= DFLAG; |
3ffd33cf | 9322 | |
384e201e | 9323 | ins.end_codep = ins.codep; |
06173b5d | 9324 | if (ins.need_modrm && !fetch_modrm (&ins)) |
5b720e50 | 9325 | goto fetch_error_out; |
55b126d4 | 9326 | |
ce518a5f | 9327 | if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE) |
252b5132 | 9328 | { |
97601363 JB |
9329 | if (!get_sib (&ins, sizeflag) |
9330 | || !dofloat (&ins, sizeflag)) | |
5b720e50 | 9331 | goto fetch_error_out; |
252b5132 RH |
9332 | } |
9333 | else | |
9334 | { | |
384e201e | 9335 | dp = get_valid_dis386 (dp, &ins); |
0b51ac42 | 9336 | if (dp == &err_opcode) |
5b720e50 | 9337 | goto fetch_error_out; |
384e201e | 9338 | if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0) |
6c067bbb | 9339 | { |
06173b5d | 9340 | if (!get_sib (&ins, sizeflag)) |
5b720e50 | 9341 | goto fetch_error_out; |
ce518a5f L |
9342 | for (i = 0; i < MAX_OPERANDS; ++i) |
9343 | { | |
384e201e JB |
9344 | ins.obufp = ins.op_out[i]; |
9345 | ins.op_ad = MAX_OPERANDS - 1 - i; | |
97601363 JB |
9346 | if (dp->op[i].rtn |
9347 | && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag)) | |
5b720e50 | 9348 | goto fetch_error_out; |
43234a1e L |
9349 | /* For EVEX instruction after the last operand masking |
9350 | should be printed. */ | |
384e201e | 9351 | if (i == 0 && ins.vex.evex) |
43234a1e L |
9352 | { |
9353 | /* Don't print {%k0}. */ | |
384e201e | 9354 | if (ins.vex.mask_register_specifier) |
43234a1e | 9355 | { |
2c3b9a91 | 9356 | const char *reg_name |
384e201e JB |
9357 | = att_names_mask[ins.vex.mask_register_specifier]; |
9358 | ||
9359 | oappend (&ins, "{"); | |
9360 | oappend_register (&ins, reg_name); | |
9361 | oappend (&ins, "}"); | |
b5c37946 SJ |
9362 | |
9363 | if (ins.vex.zeroing) | |
9364 | oappend (&ins, "{z}"); | |
9365 | } | |
9366 | else if (ins.vex.zeroing) | |
9367 | { | |
9368 | oappend (&ins, "{bad}"); | |
9369 | continue; | |
43234a1e | 9370 | } |
b5c37946 SJ |
9371 | |
9372 | /* Instructions with a mask register destination allow for | |
9373 | zeroing-masking only (if any masking at all), which is | |
9374 | _not_ expressed by EVEX.z. */ | |
9375 | if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode) | |
9376 | ins.illegal_masking = true; | |
ac500f17 | 9377 | |
596a02ff JB |
9378 | /* S/G insns require a mask and don't allow |
9379 | zeroing-masking. */ | |
9380 | if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode | |
9381 | || dp->op[0].bytemode == vex_vsib_q_w_dq_mode) | |
384e201e JB |
9382 | && (ins.vex.mask_register_specifier == 0 |
9383 | || ins.vex.zeroing)) | |
b5c37946 SJ |
9384 | ins.illegal_masking = true; |
9385 | ||
9386 | if (ins.illegal_masking) | |
384e201e | 9387 | oappend (&ins, "/(bad)"); |
43234a1e | 9388 | } |
ce518a5f | 9389 | } |
0e4cc773 JB |
9390 | |
9391 | /* Check whether rounding control was enabled for an insn not | |
9392 | supporting it. */ | |
384e201e JB |
9393 | if (ins.modrm.mod == 3 && ins.vex.b |
9394 | && !(ins.evex_used & EVEX_b_used)) | |
0e4cc773 JB |
9395 | { |
9396 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9397 | { | |
384e201e JB |
9398 | ins.obufp = ins.op_out[i]; |
9399 | if (*ins.obufp) | |
0e4cc773 | 9400 | continue; |
384e201e JB |
9401 | oappend (&ins, names_rounding[ins.vex.ll]); |
9402 | oappend (&ins, "bad}"); | |
0e4cc773 JB |
9403 | break; |
9404 | } | |
9405 | } | |
6439fc28 | 9406 | } |
252b5132 RH |
9407 | } |
9408 | ||
1d67fe3b | 9409 | /* Clear instruction information. */ |
384e201e JB |
9410 | info->insn_info_valid = 0; |
9411 | info->branch_delay_insns = 0; | |
9412 | info->data_size = 0; | |
9413 | info->insn_type = dis_noninsn; | |
9414 | info->target = 0; | |
9415 | info->target2 = 0; | |
1d67fe3b TT |
9416 | |
9417 | /* Reset jump operation indicator. */ | |
384e201e | 9418 | ins.op_is_jump = false; |
1d67fe3b TT |
9419 | { |
9420 | int jump_detection = 0; | |
9421 | ||
9422 | /* Extract flags. */ | |
9423 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9424 | { | |
9425 | if ((dp->op[i].rtn == OP_J) | |
9426 | || (dp->op[i].rtn == OP_indirE)) | |
9427 | jump_detection |= 1; | |
9428 | else if ((dp->op[i].rtn == BND_Fixup) | |
9429 | || (!dp->op[i].rtn && !dp->op[i].bytemode)) | |
9430 | jump_detection |= 2; | |
9431 | else if ((dp->op[i].bytemode == cond_jump_mode) | |
9432 | || (dp->op[i].bytemode == loop_jcxz_mode)) | |
9433 | jump_detection |= 4; | |
9434 | } | |
9435 | ||
9436 | /* Determine if this is a jump or branch. */ | |
9437 | if ((jump_detection & 0x3) == 0x3) | |
9438 | { | |
384e201e | 9439 | ins.op_is_jump = true; |
1d67fe3b | 9440 | if (jump_detection & 0x4) |
384e201e | 9441 | info->insn_type = dis_condbranch; |
1d67fe3b | 9442 | else |
384e201e | 9443 | info->insn_type = (dp->name && !strncmp (dp->name, "call", 4)) |
1d67fe3b TT |
9444 | ? dis_jsr : dis_branch; |
9445 | } | |
9446 | } | |
9447 | ||
63c6fc6c L |
9448 | /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which |
9449 | are all 0s in inverted form. */ | |
384e201e | 9450 | if (ins.need_vex && ins.vex.register_specifier != 0) |
63c6fc6c | 9451 | { |
e4452aa6 | 9452 | i386_dis_printf (info, dis_style_text, "(bad)"); |
5b720e50 AM |
9453 | ret = ins.end_codep - priv.the_buffer; |
9454 | goto out; | |
63c6fc6c L |
9455 | } |
9456 | ||
7531c613 JB |
9457 | switch (dp->prefix_requirement) |
9458 | { | |
9459 | case PREFIX_DATA: | |
9460 | /* If only the data prefix is marked as mandatory, its absence renders | |
9461 | the encoding invalid. Most other PREFIX_OPCODE rules still apply. */ | |
384e201e | 9462 | if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA)) |
7531c613 | 9463 | { |
e4452aa6 | 9464 | i386_dis_printf (info, dis_style_text, "(bad)"); |
5b720e50 AM |
9465 | ret = ins.end_codep - priv.the_buffer; |
9466 | goto out; | |
7531c613 | 9467 | } |
384e201e | 9468 | ins.used_prefixes |= PREFIX_DATA; |
7531c613 JB |
9469 | /* Fall through. */ |
9470 | case PREFIX_OPCODE: | |
9471 | /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is | |
9472 | unused, opcode is invalid. Since the PREFIX_DATA prefix may be | |
9473 | used by putop and MMX/SSE operand and may be overridden by the | |
9474 | PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix | |
9475 | separately. */ | |
384e201e JB |
9476 | if (((ins.need_vex |
9477 | ? ins.vex.prefix == REPE_PREFIX_OPCODE | |
9478 | || ins.vex.prefix == REPNE_PREFIX_OPCODE | |
9479 | : (ins.prefixes | |
7531c613 | 9480 | & (PREFIX_REPZ | PREFIX_REPNZ)) != 0) |
384e201e | 9481 | && (ins.used_prefixes |
7531c613 | 9482 | & (PREFIX_REPZ | PREFIX_REPNZ)) == 0) |
384e201e JB |
9483 | || (((ins.need_vex |
9484 | ? ins.vex.prefix == DATA_PREFIX_OPCODE | |
9485 | : ((ins.prefixes | |
7531c613 JB |
9486 | & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA)) |
9487 | == PREFIX_DATA)) | |
384e201e JB |
9488 | && (ins.used_prefixes & PREFIX_DATA) == 0)) |
9489 | || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA | |
9490 | && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA))) | |
7531c613 | 9491 | { |
e4452aa6 | 9492 | i386_dis_printf (info, dis_style_text, "(bad)"); |
5b720e50 AM |
9493 | ret = ins.end_codep - priv.the_buffer; |
9494 | goto out; | |
7531c613 JB |
9495 | } |
9496 | break; | |
31941983 JB |
9497 | |
9498 | case PREFIX_IGNORED: | |
9499 | /* Zap data size and rep prefixes from used_prefixes and reinstate their | |
9500 | origins in all_prefixes. */ | |
384e201e JB |
9501 | ins.used_prefixes &= ~PREFIX_OPCODE; |
9502 | if (ins.last_data_prefix >= 0) | |
9503 | ins.all_prefixes[ins.last_data_prefix] = 0x66; | |
9504 | if (ins.last_repz_prefix >= 0) | |
9505 | ins.all_prefixes[ins.last_repz_prefix] = 0xf3; | |
9506 | if (ins.last_repnz_prefix >= 0) | |
9507 | ins.all_prefixes[ins.last_repnz_prefix] = 0xf2; | |
31941983 | 9508 | break; |
7531c613 JB |
9509 | } |
9510 | ||
d869730d | 9511 | /* Check if the REX prefix is used. */ |
384e201e JB |
9512 | if ((ins.rex ^ ins.rex_used) == 0 |
9513 | && !ins.need_vex && ins.last_rex_prefix >= 0) | |
9514 | ins.all_prefixes[ins.last_rex_prefix] = 0; | |
f16cd0d5 | 9515 | |
5e6718e4 | 9516 | /* Check if the SEG prefix is used. */ |
384e201e JB |
9517 | if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES |
9518 | | PREFIX_FS | PREFIX_GS)) != 0 | |
9519 | && (ins.used_prefixes & ins.active_seg_prefix) != 0) | |
9520 | ins.all_prefixes[ins.last_seg_prefix] = 0; | |
f16cd0d5 | 9521 | |
5e6718e4 | 9522 | /* Check if the ADDR prefix is used. */ |
384e201e JB |
9523 | if ((ins.prefixes & PREFIX_ADDR) != 0 |
9524 | && (ins.used_prefixes & PREFIX_ADDR) != 0) | |
9525 | ins.all_prefixes[ins.last_addr_prefix] = 0; | |
f16cd0d5 | 9526 | |
df18fdba | 9527 | /* Check if the DATA prefix is used. */ |
384e201e JB |
9528 | if ((ins.prefixes & PREFIX_DATA) != 0 |
9529 | && (ins.used_prefixes & PREFIX_DATA) != 0 | |
9530 | && !ins.need_vex) | |
9531 | ins.all_prefixes[ins.last_data_prefix] = 0; | |
f16cd0d5 | 9532 | |
384e201e | 9533 | /* Print the extra ins.prefixes. */ |
f16cd0d5 | 9534 | prefix_length = 0; |
384e201e JB |
9535 | for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++) |
9536 | if (ins.all_prefixes[i]) | |
f16cd0d5 | 9537 | { |
ffe983ed JB |
9538 | const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i], |
9539 | orig_sizeflag); | |
9540 | ||
f16cd0d5 L |
9541 | if (name == NULL) |
9542 | abort (); | |
9543 | prefix_length += strlen (name) + 1; | |
e4452aa6 | 9544 | i386_dis_printf (info, dis_style_mnemonic, "%s ", name); |
f16cd0d5 | 9545 | } |
b844680a | 9546 | |
f16cd0d5 | 9547 | /* Check maximum code length. */ |
384e201e | 9548 | if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH) |
f16cd0d5 | 9549 | { |
e4452aa6 | 9550 | i386_dis_printf (info, dis_style_text, "(bad)"); |
5b720e50 AM |
9551 | ret = MAX_CODE_LENGTH; |
9552 | goto out; | |
f16cd0d5 | 9553 | } |
b844680a | 9554 | |
202be274 AB |
9555 | /* Calculate the number of operands this instruction has. */ |
9556 | op_count = 0; | |
9557 | for (i = 0; i < MAX_OPERANDS; ++i) | |
8025a164 | 9558 | if (*ins.op_out[i] != '\0') |
202be274 AB |
9559 | ++op_count; |
9560 | ||
9561 | /* Calculate the number of spaces to print after the mnemonic. */ | |
384e201e | 9562 | ins.obufp = ins.mnemonicendp; |
202be274 AB |
9563 | if (op_count > 0) |
9564 | { | |
384e201e | 9565 | i = strlen (ins.obuf) + prefix_length; |
202be274 AB |
9566 | if (i < 7) |
9567 | i = 7 - i; | |
9568 | else | |
9569 | i = 1; | |
9570 | } | |
9571 | else | |
9572 | i = 0; | |
9573 | ||
9574 | /* Print the instruction mnemonic along with any trailing whitespace. */ | |
e4452aa6 | 9575 | i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, ""); |
252b5132 RH |
9576 | |
9577 | /* The enter and bound instructions are printed with operands in the same | |
9578 | order as the intel book; everything else is printed in reverse order. */ | |
90a00d6c | 9579 | intel_swap_2_3 = false; |
384e201e | 9580 | if (ins.intel_syntax || ins.two_source_ops) |
252b5132 | 9581 | { |
ce518a5f | 9582 | for (i = 0; i < MAX_OPERANDS; ++i) |
384e201e | 9583 | op_txt[i] = ins.op_out[i]; |
246c51aa | 9584 | |
384e201e | 9585 | if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding |
3a8547d2 JB |
9586 | && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL) |
9587 | { | |
384e201e JB |
9588 | op_txt[2] = ins.op_out[3]; |
9589 | op_txt[3] = ins.op_out[2]; | |
90a00d6c | 9590 | intel_swap_2_3 = true; |
3a8547d2 JB |
9591 | } |
9592 | ||
ce518a5f L |
9593 | for (i = 0; i < (MAX_OPERANDS >> 1); ++i) |
9594 | { | |
4bb8b8e9 JB |
9595 | bool riprel; |
9596 | ||
384e201e JB |
9597 | ins.op_ad = ins.op_index[i]; |
9598 | ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i]; | |
9599 | ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad; | |
9600 | riprel = ins.op_riprel[i]; | |
9601 | ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i]; | |
9602 | ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel; | |
ce518a5f | 9603 | } |
252b5132 RH |
9604 | } |
9605 | else | |
9606 | { | |
ce518a5f | 9607 | for (i = 0; i < MAX_OPERANDS; ++i) |
384e201e | 9608 | op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i]; |
050dfa73 MM |
9609 | } |
9610 | ||
ce518a5f L |
9611 | needcomma = 0; |
9612 | for (i = 0; i < MAX_OPERANDS; ++i) | |
9613 | if (*op_txt[i]) | |
9614 | { | |
90a00d6c JB |
9615 | /* In Intel syntax embedded rounding / SAE are not separate operands. |
9616 | Instead they're attached to the prior register operand. Simply | |
9617 | suppress emission of the comma to achieve that effect. */ | |
384e201e | 9618 | switch (i & -(ins.intel_syntax && dp)) |
90a00d6c JB |
9619 | { |
9620 | case 2: | |
9621 | if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3) | |
9622 | needcomma = 0; | |
9623 | break; | |
9624 | case 3: | |
9625 | if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3) | |
9626 | needcomma = 0; | |
9627 | break; | |
9628 | } | |
ce518a5f | 9629 | if (needcomma) |
e4452aa6 | 9630 | i386_dis_printf (info, dis_style_text, ","); |
384e201e | 9631 | if (ins.op_index[i] != -1 && !ins.op_riprel[i]) |
1d67fe3b | 9632 | { |
384e201e | 9633 | bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]]; |
1d67fe3b | 9634 | |
384e201e | 9635 | if (ins.op_is_jump) |
1d67fe3b | 9636 | { |
384e201e JB |
9637 | info->insn_info_valid = 1; |
9638 | info->branch_delay_insns = 0; | |
9639 | info->data_size = 0; | |
9640 | info->target = target; | |
9641 | info->target2 = 0; | |
1d67fe3b | 9642 | } |
384e201e | 9643 | (*info->print_address_func) (target, info); |
1d67fe3b | 9644 | } |
ce518a5f | 9645 | else |
e4452aa6 | 9646 | i386_dis_printf (info, dis_style_text, "%s", op_txt[i]); |
ce518a5f L |
9647 | needcomma = 1; |
9648 | } | |
050dfa73 | 9649 | |
ce518a5f | 9650 | for (i = 0; i < MAX_OPERANDS; i++) |
384e201e | 9651 | if (ins.op_index[i] != -1 && ins.op_riprel[i]) |
52b15da3 | 9652 | { |
e4452aa6 | 9653 | i386_dis_printf (info, dis_style_comment_start, " # "); |
384e201e JB |
9654 | (*info->print_address_func) |
9655 | ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep) | |
9656 | + ins.op_address[ins.op_index[i]]), | |
9657 | info); | |
185b1163 | 9658 | break; |
52b15da3 | 9659 | } |
5b720e50 AM |
9660 | ret = ins.codep - priv.the_buffer; |
9661 | out: | |
9662 | info->private_data = NULL; | |
9663 | return ret; | |
384e201e JB |
9664 | } |
9665 | ||
9666 | /* Here for backwards compatibility. When gdb stops using | |
9667 | print_insn_i386_att and print_insn_i386_intel these functions can | |
9668 | disappear, and print_insn_i386 be merged into print_insn. */ | |
9669 | int | |
9670 | print_insn_i386_att (bfd_vma pc, disassemble_info *info) | |
9671 | { | |
9672 | return print_insn (pc, info, 0); | |
9673 | } | |
9674 | ||
9675 | int | |
9676 | print_insn_i386_intel (bfd_vma pc, disassemble_info *info) | |
9677 | { | |
9678 | return print_insn (pc, info, 1); | |
9679 | } | |
9680 | ||
9681 | int | |
9682 | print_insn_i386 (bfd_vma pc, disassemble_info *info) | |
9683 | { | |
9684 | return print_insn (pc, info, -1); | |
252b5132 RH |
9685 | } |
9686 | ||
6439fc28 | 9687 | static const char *float_mem[] = { |
252b5132 | 9688 | /* d8 */ |
7c52e0e8 L |
9689 | "fadd{s|}", |
9690 | "fmul{s|}", | |
9691 | "fcom{s|}", | |
9692 | "fcomp{s|}", | |
9693 | "fsub{s|}", | |
9694 | "fsubr{s|}", | |
9695 | "fdiv{s|}", | |
9696 | "fdivr{s|}", | |
db6eb5be | 9697 | /* d9 */ |
7c52e0e8 | 9698 | "fld{s|}", |
252b5132 | 9699 | "(bad)", |
7c52e0e8 L |
9700 | "fst{s|}", |
9701 | "fstp{s|}", | |
d1c36125 | 9702 | "fldenv{C|C}", |
252b5132 | 9703 | "fldcw", |
d1c36125 | 9704 | "fNstenv{C|C}", |
252b5132 RH |
9705 | "fNstcw", |
9706 | /* da */ | |
7c52e0e8 L |
9707 | "fiadd{l|}", |
9708 | "fimul{l|}", | |
9709 | "ficom{l|}", | |
9710 | "ficomp{l|}", | |
9711 | "fisub{l|}", | |
9712 | "fisubr{l|}", | |
9713 | "fidiv{l|}", | |
9714 | "fidivr{l|}", | |
252b5132 | 9715 | /* db */ |
7c52e0e8 L |
9716 | "fild{l|}", |
9717 | "fisttp{l|}", | |
9718 | "fist{l|}", | |
9719 | "fistp{l|}", | |
252b5132 | 9720 | "(bad)", |
464dc4af | 9721 | "fld{t|}", |
252b5132 | 9722 | "(bad)", |
464dc4af | 9723 | "fstp{t|}", |
252b5132 | 9724 | /* dc */ |
7c52e0e8 L |
9725 | "fadd{l|}", |
9726 | "fmul{l|}", | |
9727 | "fcom{l|}", | |
9728 | "fcomp{l|}", | |
9729 | "fsub{l|}", | |
9730 | "fsubr{l|}", | |
9731 | "fdiv{l|}", | |
9732 | "fdivr{l|}", | |
252b5132 | 9733 | /* dd */ |
7c52e0e8 L |
9734 | "fld{l|}", |
9735 | "fisttp{ll|}", | |
9736 | "fst{l||}", | |
9737 | "fstp{l|}", | |
d1c36125 | 9738 | "frstor{C|C}", |
252b5132 | 9739 | "(bad)", |
d1c36125 | 9740 | "fNsave{C|C}", |
252b5132 RH |
9741 | "fNstsw", |
9742 | /* de */ | |
ac465521 JB |
9743 | "fiadd{s|}", |
9744 | "fimul{s|}", | |
9745 | "ficom{s|}", | |
9746 | "ficomp{s|}", | |
9747 | "fisub{s|}", | |
9748 | "fisubr{s|}", | |
9749 | "fidiv{s|}", | |
9750 | "fidivr{s|}", | |
252b5132 | 9751 | /* df */ |
ac465521 JB |
9752 | "fild{s|}", |
9753 | "fisttp{s|}", | |
9754 | "fist{s|}", | |
9755 | "fistp{s|}", | |
252b5132 | 9756 | "fbld", |
7c52e0e8 | 9757 | "fild{ll|}", |
252b5132 | 9758 | "fbstp", |
7c52e0e8 | 9759 | "fistp{ll|}", |
1d9f512f AM |
9760 | }; |
9761 | ||
9762 | static const unsigned char float_mem_mode[] = { | |
9763 | /* d8 */ | |
9764 | d_mode, | |
9765 | d_mode, | |
9766 | d_mode, | |
9767 | d_mode, | |
9768 | d_mode, | |
9769 | d_mode, | |
9770 | d_mode, | |
9771 | d_mode, | |
9772 | /* d9 */ | |
9773 | d_mode, | |
9774 | 0, | |
9775 | d_mode, | |
9776 | d_mode, | |
9777 | 0, | |
9778 | w_mode, | |
9779 | 0, | |
9780 | w_mode, | |
9781 | /* da */ | |
9782 | d_mode, | |
9783 | d_mode, | |
9784 | d_mode, | |
9785 | d_mode, | |
9786 | d_mode, | |
9787 | d_mode, | |
9788 | d_mode, | |
9789 | d_mode, | |
9790 | /* db */ | |
9791 | d_mode, | |
9792 | d_mode, | |
9793 | d_mode, | |
9794 | d_mode, | |
9795 | 0, | |
9306ca4a | 9796 | t_mode, |
1d9f512f | 9797 | 0, |
9306ca4a | 9798 | t_mode, |
1d9f512f AM |
9799 | /* dc */ |
9800 | q_mode, | |
9801 | q_mode, | |
9802 | q_mode, | |
9803 | q_mode, | |
9804 | q_mode, | |
9805 | q_mode, | |
9806 | q_mode, | |
9807 | q_mode, | |
9808 | /* dd */ | |
9809 | q_mode, | |
9810 | q_mode, | |
9811 | q_mode, | |
9812 | q_mode, | |
9813 | 0, | |
9814 | 0, | |
9815 | 0, | |
9816 | w_mode, | |
9817 | /* de */ | |
9818 | w_mode, | |
9819 | w_mode, | |
9820 | w_mode, | |
9821 | w_mode, | |
9822 | w_mode, | |
9823 | w_mode, | |
9824 | w_mode, | |
9825 | w_mode, | |
9826 | /* df */ | |
9827 | w_mode, | |
9828 | w_mode, | |
9829 | w_mode, | |
9830 | w_mode, | |
9306ca4a | 9831 | t_mode, |
1d9f512f | 9832 | q_mode, |
9306ca4a | 9833 | t_mode, |
1d9f512f | 9834 | q_mode |
252b5132 RH |
9835 | }; |
9836 | ||
ce518a5f L |
9837 | #define ST { OP_ST, 0 } |
9838 | #define STi { OP_STi, 0 } | |
252b5132 | 9839 | |
48c97fa1 L |
9840 | #define FGRPd9_2 NULL, { { NULL, 1 } }, 0 |
9841 | #define FGRPd9_4 NULL, { { NULL, 2 } }, 0 | |
9842 | #define FGRPd9_5 NULL, { { NULL, 3 } }, 0 | |
9843 | #define FGRPd9_6 NULL, { { NULL, 4 } }, 0 | |
9844 | #define FGRPd9_7 NULL, { { NULL, 5 } }, 0 | |
9845 | #define FGRPda_5 NULL, { { NULL, 6 } }, 0 | |
9846 | #define FGRPdb_4 NULL, { { NULL, 7 } }, 0 | |
9847 | #define FGRPde_3 NULL, { { NULL, 8 } }, 0 | |
9848 | #define FGRPdf_4 NULL, { { NULL, 9 } }, 0 | |
252b5132 | 9849 | |
2da11e11 | 9850 | static const struct dis386 float_reg[][8] = { |
252b5132 RH |
9851 | /* d8 */ |
9852 | { | |
bf890a93 IT |
9853 | { "fadd", { ST, STi }, 0 }, |
9854 | { "fmul", { ST, STi }, 0 }, | |
9855 | { "fcom", { STi }, 0 }, | |
9856 | { "fcomp", { STi }, 0 }, | |
9857 | { "fsub", { ST, STi }, 0 }, | |
9858 | { "fsubr", { ST, STi }, 0 }, | |
9859 | { "fdiv", { ST, STi }, 0 }, | |
9860 | { "fdivr", { ST, STi }, 0 }, | |
252b5132 RH |
9861 | }, |
9862 | /* d9 */ | |
9863 | { | |
bf890a93 IT |
9864 | { "fld", { STi }, 0 }, |
9865 | { "fxch", { STi }, 0 }, | |
252b5132 | 9866 | { FGRPd9_2 }, |
592d1631 | 9867 | { Bad_Opcode }, |
252b5132 RH |
9868 | { FGRPd9_4 }, |
9869 | { FGRPd9_5 }, | |
9870 | { FGRPd9_6 }, | |
9871 | { FGRPd9_7 }, | |
9872 | }, | |
9873 | /* da */ | |
9874 | { | |
bf890a93 IT |
9875 | { "fcmovb", { ST, STi }, 0 }, |
9876 | { "fcmove", { ST, STi }, 0 }, | |
9877 | { "fcmovbe",{ ST, STi }, 0 }, | |
9878 | { "fcmovu", { ST, STi }, 0 }, | |
592d1631 | 9879 | { Bad_Opcode }, |
252b5132 | 9880 | { FGRPda_5 }, |
592d1631 L |
9881 | { Bad_Opcode }, |
9882 | { Bad_Opcode }, | |
252b5132 RH |
9883 | }, |
9884 | /* db */ | |
9885 | { | |
bf890a93 IT |
9886 | { "fcmovnb",{ ST, STi }, 0 }, |
9887 | { "fcmovne",{ ST, STi }, 0 }, | |
9888 | { "fcmovnbe",{ ST, STi }, 0 }, | |
9889 | { "fcmovnu",{ ST, STi }, 0 }, | |
252b5132 | 9890 | { FGRPdb_4 }, |
bf890a93 IT |
9891 | { "fucomi", { ST, STi }, 0 }, |
9892 | { "fcomi", { ST, STi }, 0 }, | |
592d1631 | 9893 | { Bad_Opcode }, |
252b5132 RH |
9894 | }, |
9895 | /* dc */ | |
9896 | { | |
bf890a93 IT |
9897 | { "fadd", { STi, ST }, 0 }, |
9898 | { "fmul", { STi, ST }, 0 }, | |
592d1631 L |
9899 | { Bad_Opcode }, |
9900 | { Bad_Opcode }, | |
d53e6b98 JB |
9901 | { "fsub{!M|r}", { STi, ST }, 0 }, |
9902 | { "fsub{M|}", { STi, ST }, 0 }, | |
9903 | { "fdiv{!M|r}", { STi, ST }, 0 }, | |
9904 | { "fdiv{M|}", { STi, ST }, 0 }, | |
252b5132 RH |
9905 | }, |
9906 | /* dd */ | |
9907 | { | |
bf890a93 | 9908 | { "ffree", { STi }, 0 }, |
592d1631 | 9909 | { Bad_Opcode }, |
bf890a93 IT |
9910 | { "fst", { STi }, 0 }, |
9911 | { "fstp", { STi }, 0 }, | |
9912 | { "fucom", { STi }, 0 }, | |
9913 | { "fucomp", { STi }, 0 }, | |
592d1631 L |
9914 | { Bad_Opcode }, |
9915 | { Bad_Opcode }, | |
252b5132 RH |
9916 | }, |
9917 | /* de */ | |
9918 | { | |
bf890a93 IT |
9919 | { "faddp", { STi, ST }, 0 }, |
9920 | { "fmulp", { STi, ST }, 0 }, | |
592d1631 | 9921 | { Bad_Opcode }, |
252b5132 | 9922 | { FGRPde_3 }, |
d53e6b98 JB |
9923 | { "fsub{!M|r}p", { STi, ST }, 0 }, |
9924 | { "fsub{M|}p", { STi, ST }, 0 }, | |
9925 | { "fdiv{!M|r}p", { STi, ST }, 0 }, | |
9926 | { "fdiv{M|}p", { STi, ST }, 0 }, | |
252b5132 RH |
9927 | }, |
9928 | /* df */ | |
9929 | { | |
bf890a93 | 9930 | { "ffreep", { STi }, 0 }, |
592d1631 L |
9931 | { Bad_Opcode }, |
9932 | { Bad_Opcode }, | |
9933 | { Bad_Opcode }, | |
252b5132 | 9934 | { FGRPdf_4 }, |
bf890a93 IT |
9935 | { "fucomip", { ST, STi }, 0 }, |
9936 | { "fcomip", { ST, STi }, 0 }, | |
592d1631 | 9937 | { Bad_Opcode }, |
252b5132 RH |
9938 | }, |
9939 | }; | |
9940 | ||
2a78304e | 9941 | static const char *const fgrps[][8] = { |
48c97fa1 L |
9942 | /* Bad opcode 0 */ |
9943 | { | |
9944 | "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9945 | }, | |
9946 | ||
9947 | /* d9_2 1 */ | |
252b5132 RH |
9948 | { |
9949 | "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9950 | }, | |
9951 | ||
48c97fa1 | 9952 | /* d9_4 2 */ |
252b5132 RH |
9953 | { |
9954 | "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)", | |
9955 | }, | |
9956 | ||
48c97fa1 | 9957 | /* d9_5 3 */ |
252b5132 RH |
9958 | { |
9959 | "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)", | |
9960 | }, | |
9961 | ||
48c97fa1 | 9962 | /* d9_6 4 */ |
252b5132 RH |
9963 | { |
9964 | "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp", | |
9965 | }, | |
9966 | ||
48c97fa1 | 9967 | /* d9_7 5 */ |
252b5132 RH |
9968 | { |
9969 | "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos", | |
9970 | }, | |
9971 | ||
48c97fa1 | 9972 | /* da_5 6 */ |
252b5132 RH |
9973 | { |
9974 | "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9975 | }, | |
9976 | ||
48c97fa1 | 9977 | /* db_4 7 */ |
252b5132 | 9978 | { |
309d3373 JB |
9979 | "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit", |
9980 | "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)", | |
252b5132 RH |
9981 | }, |
9982 | ||
48c97fa1 | 9983 | /* de_3 8 */ |
252b5132 RH |
9984 | { |
9985 | "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9986 | }, | |
9987 | ||
48c97fa1 | 9988 | /* df_4 9 */ |
252b5132 RH |
9989 | { |
9990 | "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)", | |
9991 | }, | |
9992 | }; | |
9993 | ||
b6169b20 | 9994 | static void |
39fb3698 | 9995 | swap_operand (instr_info *ins) |
b6169b20 | 9996 | { |
39fb3698 VM |
9997 | ins->mnemonicendp[0] = '.'; |
9998 | ins->mnemonicendp[1] = 's'; | |
9999 | ins->mnemonicendp[2] = '\0'; | |
10000 | ins->mnemonicendp += 2; | |
b6169b20 L |
10001 | } |
10002 | ||
97601363 | 10003 | static bool |
39fb3698 | 10004 | dofloat (instr_info *ins, int sizeflag) |
252b5132 | 10005 | { |
2da11e11 | 10006 | const struct dis386 *dp; |
a4aa034a | 10007 | unsigned char floatop = ins->codep[-1]; |
252b5132 | 10008 | |
39fb3698 | 10009 | if (ins->modrm.mod != 3) |
252b5132 | 10010 | { |
39fb3698 | 10011 | int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg; |
1d9f512f | 10012 | |
39fb3698 VM |
10013 | putop (ins, float_mem[fp_indx], sizeflag); |
10014 | ins->obufp = ins->op_out[0]; | |
10015 | ins->op_ad = 2; | |
97601363 | 10016 | return OP_E (ins, float_mem_mode[fp_indx], sizeflag); |
252b5132 | 10017 | } |
6608db57 | 10018 | /* Skip mod/rm byte. */ |
4bba6815 | 10019 | MODRM_CHECK; |
39fb3698 | 10020 | ins->codep++; |
252b5132 | 10021 | |
39fb3698 | 10022 | dp = &float_reg[floatop - 0xd8][ins->modrm.reg]; |
252b5132 RH |
10023 | if (dp->name == NULL) |
10024 | { | |
39fb3698 | 10025 | putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag); |
252b5132 | 10026 | |
6608db57 | 10027 | /* Instruction fnstsw is only one with strange arg. */ |
a4aa034a | 10028 | if (floatop == 0xdf && ins->codep[-1] == 0xe0) |
e564475a | 10029 | strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax); |
252b5132 RH |
10030 | } |
10031 | else | |
10032 | { | |
39fb3698 | 10033 | putop (ins, dp->name, sizeflag); |
252b5132 | 10034 | |
39fb3698 VM |
10035 | ins->obufp = ins->op_out[0]; |
10036 | ins->op_ad = 2; | |
97601363 JB |
10037 | if (dp->op[0].rtn |
10038 | && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag)) | |
10039 | return false; | |
6e50d963 | 10040 | |
39fb3698 VM |
10041 | ins->obufp = ins->op_out[1]; |
10042 | ins->op_ad = 1; | |
97601363 JB |
10043 | if (dp->op[1].rtn |
10044 | && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag)) | |
10045 | return false; | |
252b5132 | 10046 | } |
97601363 | 10047 | return true; |
252b5132 RH |
10048 | } |
10049 | ||
97601363 | 10050 | static bool |
39fb3698 VM |
10051 | OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
10052 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 | 10053 | { |
2c3b9a91 | 10054 | oappend_register (ins, "%st"); |
97601363 | 10055 | return true; |
252b5132 RH |
10056 | } |
10057 | ||
97601363 | 10058 | static bool |
39fb3698 VM |
10059 | OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
10060 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 | 10061 | { |
95ff6718 JB |
10062 | char scratch[8]; |
10063 | int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm); | |
10064 | ||
10065 | if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) | |
10066 | abort (); | |
10067 | oappend_register (ins, scratch); | |
97601363 | 10068 | return true; |
252b5132 RH |
10069 | } |
10070 | ||
6608db57 | 10071 | /* Capital letters in template are macros. */ |
6439fc28 | 10072 | static int |
39fb3698 | 10073 | putop (instr_info *ins, const char *in_template, int sizeflag) |
252b5132 | 10074 | { |
2da11e11 | 10075 | const char *p; |
9306ca4a | 10076 | int alt = 0; |
9d141669 | 10077 | int cond = 1; |
21a3faeb | 10078 | unsigned int l = 0, len = 0; |
98b528ac L |
10079 | char last[4]; |
10080 | ||
d3ce72d0 | 10081 | for (p = in_template; *p; p++) |
252b5132 | 10082 | { |
21a3faeb JB |
10083 | if (len > l) |
10084 | { | |
10085 | if (l >= sizeof (last) || !ISUPPER (*p)) | |
10086 | abort (); | |
10087 | last[l++] = *p; | |
10088 | continue; | |
10089 | } | |
252b5132 RH |
10090 | switch (*p) |
10091 | { | |
10092 | default: | |
39fb3698 | 10093 | *ins->obufp++ = *p; |
252b5132 | 10094 | break; |
98b528ac L |
10095 | case '%': |
10096 | len++; | |
10097 | break; | |
9d141669 L |
10098 | case '!': |
10099 | cond = 0; | |
10100 | break; | |
6439fc28 | 10101 | case '{': |
39fb3698 | 10102 | if (ins->intel_syntax) |
6439fc28 AM |
10103 | { |
10104 | while (*++p != '|') | |
7c52e0e8 L |
10105 | if (*p == '}' || *p == '\0') |
10106 | abort (); | |
d1c36125 | 10107 | alt = 1; |
6439fc28 | 10108 | } |
d1c36125 | 10109 | break; |
6439fc28 AM |
10110 | case '|': |
10111 | while (*++p != '}') | |
10112 | { | |
10113 | if (*p == '\0') | |
10114 | abort (); | |
10115 | } | |
10116 | break; | |
10117 | case '}': | |
d1c36125 | 10118 | alt = 0; |
6439fc28 | 10119 | break; |
252b5132 | 10120 | case 'A': |
39fb3698 | 10121 | if (ins->intel_syntax) |
db6eb5be | 10122 | break; |
39fb3698 | 10123 | if ((ins->need_modrm && ins->modrm.mod != 3) |
0e9f3bf1 | 10124 | || (sizeflag & SUFFIX_ALWAYS)) |
39fb3698 | 10125 | *ins->obufp++ = 'b'; |
252b5132 RH |
10126 | break; |
10127 | case 'B': | |
21a3faeb | 10128 | if (l == 0) |
4b06377f | 10129 | { |
dc1e8a47 | 10130 | case_B: |
39fb3698 | 10131 | if (ins->intel_syntax) |
4b06377f L |
10132 | break; |
10133 | if (sizeflag & SUFFIX_ALWAYS) | |
39fb3698 | 10134 | *ins->obufp++ = 'b'; |
4b06377f | 10135 | } |
21a3faeb | 10136 | else if (l == 1 && last[0] == 'L') |
4b06377f | 10137 | { |
39fb3698 VM |
10138 | if (ins->address_mode == mode_64bit |
10139 | && !(ins->prefixes & PREFIX_ADDR)) | |
4b06377f | 10140 | { |
39fb3698 VM |
10141 | *ins->obufp++ = 'a'; |
10142 | *ins->obufp++ = 'b'; | |
10143 | *ins->obufp++ = 's'; | |
4b06377f L |
10144 | } |
10145 | ||
10146 | goto case_B; | |
10147 | } | |
21a3faeb JB |
10148 | else |
10149 | abort (); | |
252b5132 | 10150 | break; |
9306ca4a | 10151 | case 'C': |
39fb3698 | 10152 | if (ins->intel_syntax && !alt) |
9306ca4a | 10153 | break; |
39fb3698 | 10154 | if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
9306ca4a JB |
10155 | { |
10156 | if (sizeflag & DFLAG) | |
39fb3698 | 10157 | *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; |
9306ca4a | 10158 | else |
39fb3698 VM |
10159 | *ins->obufp++ = ins->intel_syntax ? 'w' : 's'; |
10160 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
9306ca4a JB |
10161 | } |
10162 | break; | |
ed7841b3 | 10163 | case 'D': |
2235ecb8 JB |
10164 | if (l == 1) |
10165 | { | |
10166 | switch (last[0]) | |
10167 | { | |
10168 | case 'X': | |
e6cfa893 | 10169 | if (!ins->vex.evex || ins->vex.w) |
2235ecb8 JB |
10170 | *ins->obufp++ = 'd'; |
10171 | else | |
10172 | oappend (ins, "{bad}"); | |
10173 | break; | |
10174 | default: | |
10175 | abort (); | |
10176 | } | |
10177 | break; | |
10178 | } | |
10179 | if (l) | |
10180 | abort (); | |
39fb3698 | 10181 | if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS)) |
ed7841b3 | 10182 | break; |
161a04f6 | 10183 | USED_REX (REX_W); |
39fb3698 | 10184 | if (ins->modrm.mod == 3) |
ed7841b3 | 10185 | { |
39fb3698 VM |
10186 | if (ins->rex & REX_W) |
10187 | *ins->obufp++ = 'q'; | |
ed7841b3 | 10188 | else |
f16cd0d5 L |
10189 | { |
10190 | if (sizeflag & DFLAG) | |
39fb3698 | 10191 | *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; |
f16cd0d5 | 10192 | else |
39fb3698 VM |
10193 | *ins->obufp++ = 'w'; |
10194 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
f16cd0d5 | 10195 | } |
ed7841b3 JB |
10196 | } |
10197 | else | |
39fb3698 | 10198 | *ins->obufp++ = 'w'; |
ed7841b3 | 10199 | break; |
f7cfcddd JB |
10200 | case 'E': |
10201 | if (l == 1) | |
10202 | { | |
10203 | switch (last[0]) | |
10204 | { | |
10205 | case 'X': | |
10206 | if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2 | |
10207 | || !ins->vex.r | |
10208 | || (ins->modrm.mod == 3 && (ins->rex & REX_X)) | |
10209 | || !ins->vex.v || ins->vex.mask_register_specifier) | |
10210 | break; | |
10211 | /* AVX512 extends a number of V*D insns to also have V*Q variants, | |
10212 | merely distinguished by EVEX.W. Look for a use of the | |
10213 | respective macro. */ | |
10214 | if (ins->vex.w) | |
10215 | { | |
10216 | const char *pct = strchr (p + 1, '%'); | |
10217 | ||
10218 | if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q') | |
10219 | break; | |
10220 | } | |
10221 | *ins->obufp++ = '{'; | |
10222 | *ins->obufp++ = 'e'; | |
10223 | *ins->obufp++ = 'v'; | |
10224 | *ins->obufp++ = 'e'; | |
10225 | *ins->obufp++ = 'x'; | |
10226 | *ins->obufp++ = '}'; | |
10227 | *ins->obufp++ = ' '; | |
10228 | break; | |
10229 | default: | |
10230 | abort (); | |
10231 | } | |
10232 | break; | |
10233 | } | |
10234 | /* For jcxz/jecxz */ | |
39fb3698 | 10235 | if (ins->address_mode == mode_64bit) |
c1a64871 JH |
10236 | { |
10237 | if (sizeflag & AFLAG) | |
39fb3698 | 10238 | *ins->obufp++ = 'r'; |
c1a64871 | 10239 | else |
39fb3698 | 10240 | *ins->obufp++ = 'e'; |
c1a64871 JH |
10241 | } |
10242 | else | |
10243 | if (sizeflag & AFLAG) | |
39fb3698 VM |
10244 | *ins->obufp++ = 'e'; |
10245 | ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); | |
3ffd33cf AM |
10246 | break; |
10247 | case 'F': | |
39fb3698 | 10248 | if (ins->intel_syntax) |
db6eb5be | 10249 | break; |
39fb3698 | 10250 | if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS)) |
3ffd33cf AM |
10251 | { |
10252 | if (sizeflag & AFLAG) | |
39fb3698 | 10253 | *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; |
3ffd33cf | 10254 | else |
39fb3698 VM |
10255 | *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w'; |
10256 | ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); | |
3ffd33cf | 10257 | } |
252b5132 | 10258 | break; |
52fd6d94 | 10259 | case 'G': |
39fb3698 VM |
10260 | if (ins->intel_syntax || (ins->obufp[-1] != 's' |
10261 | && !(sizeflag & SUFFIX_ALWAYS))) | |
52fd6d94 | 10262 | break; |
39fb3698 VM |
10263 | if ((ins->rex & REX_W) || (sizeflag & DFLAG)) |
10264 | *ins->obufp++ = 'l'; | |
52fd6d94 | 10265 | else |
39fb3698 VM |
10266 | *ins->obufp++ = 'w'; |
10267 | if (!(ins->rex & REX_W)) | |
10268 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
52fd6d94 | 10269 | break; |
5dd0794d | 10270 | case 'H': |
0cc78721 | 10271 | if (l == 0) |
5dd0794d | 10272 | { |
39fb3698 | 10273 | if (ins->intel_syntax) |
0cc78721 | 10274 | break; |
39fb3698 VM |
10275 | if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS |
10276 | || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS) | |
632ee6fd | 10277 | { |
39fb3698 VM |
10278 | ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS); |
10279 | *ins->obufp++ = ','; | |
10280 | *ins->obufp++ = 'p'; | |
0cc78721 CL |
10281 | |
10282 | /* Set active_seg_prefix even if not set in 64-bit mode | |
10283 | because here it is a valid branch hint. */ | |
39fb3698 | 10284 | if (ins->prefixes & PREFIX_DS) |
0cc78721 | 10285 | { |
39fb3698 VM |
10286 | ins->active_seg_prefix = PREFIX_DS; |
10287 | *ins->obufp++ = 't'; | |
0cc78721 CL |
10288 | } |
10289 | else | |
10290 | { | |
39fb3698 VM |
10291 | ins->active_seg_prefix = PREFIX_CS; |
10292 | *ins->obufp++ = 'n'; | |
0cc78721 | 10293 | } |
632ee6fd | 10294 | } |
0cc78721 CL |
10295 | } |
10296 | else if (l == 1 && last[0] == 'X') | |
10297 | { | |
ab31da6a | 10298 | if (!ins->vex.w) |
39fb3698 | 10299 | *ins->obufp++ = 'h'; |
5dd0794d | 10300 | else |
2235ecb8 | 10301 | oappend (ins, "{bad}"); |
5dd0794d | 10302 | } |
0cc78721 CL |
10303 | else |
10304 | abort (); | |
5dd0794d | 10305 | break; |
42903f7f L |
10306 | case 'K': |
10307 | USED_REX (REX_W); | |
39fb3698 VM |
10308 | if (ins->rex & REX_W) |
10309 | *ins->obufp++ = 'q'; | |
42903f7f | 10310 | else |
39fb3698 | 10311 | *ins->obufp++ = 'd'; |
42903f7f | 10312 | break; |
252b5132 | 10313 | case 'L': |
78467458 | 10314 | abort (); |
9d141669 | 10315 | case 'M': |
39fb3698 VM |
10316 | if (ins->intel_mnemonic != cond) |
10317 | *ins->obufp++ = 'r'; | |
9d141669 | 10318 | break; |
252b5132 | 10319 | case 'N': |
39fb3698 VM |
10320 | if ((ins->prefixes & PREFIX_FWAIT) == 0) |
10321 | *ins->obufp++ = 'n'; | |
7d421014 | 10322 | else |
39fb3698 | 10323 | ins->used_prefixes |= PREFIX_FWAIT; |
252b5132 | 10324 | break; |
52b15da3 | 10325 | case 'O': |
161a04f6 | 10326 | USED_REX (REX_W); |
39fb3698 VM |
10327 | if (ins->rex & REX_W) |
10328 | *ins->obufp++ = 'o'; | |
10329 | else if (ins->intel_syntax && (sizeflag & DFLAG)) | |
10330 | *ins->obufp++ = 'q'; | |
52b15da3 | 10331 | else |
39fb3698 VM |
10332 | *ins->obufp++ = 'd'; |
10333 | if (!(ins->rex & REX_W)) | |
10334 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
52b15da3 | 10335 | break; |
36938cab | 10336 | case '@': |
39fb3698 VM |
10337 | if (ins->address_mode == mode_64bit |
10338 | && (ins->isa64 == intel64 || (ins->rex & REX_W) | |
10339 | || !(ins->prefixes & PREFIX_DATA))) | |
6439fc28 | 10340 | { |
36938cab | 10341 | if (sizeflag & SUFFIX_ALWAYS) |
39fb3698 | 10342 | *ins->obufp++ = 'q'; |
6439fc28 AM |
10343 | break; |
10344 | } | |
6608db57 | 10345 | /* Fall through. */ |
252b5132 | 10346 | case 'P': |
21a3faeb | 10347 | if (l == 0) |
d9e3625e | 10348 | { |
39fb3698 | 10349 | if ((ins->modrm.mod == 3 || !cond) |
c3f5525f | 10350 | && !(sizeflag & SUFFIX_ALWAYS)) |
36938cab JB |
10351 | break; |
10352 | /* Fall through. */ | |
10353 | case 'T': | |
39fb3698 | 10354 | if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA)) |
36938cab | 10355 | || ((sizeflag & SUFFIX_ALWAYS) |
39fb3698 | 10356 | && ins->address_mode != mode_64bit)) |
4b4c407a | 10357 | { |
39fb3698 VM |
10358 | *ins->obufp++ = (sizeflag & DFLAG) |
10359 | ? ins->intel_syntax ? 'd' : 'l' : 'w'; | |
10360 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
d9e3625e | 10361 | } |
36938cab | 10362 | else if (sizeflag & SUFFIX_ALWAYS) |
39fb3698 | 10363 | *ins->obufp++ = 'q'; |
d9e3625e | 10364 | } |
21a3faeb | 10365 | else if (l == 1 && last[0] == 'L') |
252b5132 | 10366 | { |
39fb3698 VM |
10367 | if ((ins->prefixes & PREFIX_DATA) |
10368 | || (ins->rex & REX_W) | |
4b4c407a | 10369 | || (sizeflag & SUFFIX_ALWAYS)) |
52b15da3 | 10370 | { |
4b4c407a | 10371 | USED_REX (REX_W); |
39fb3698 VM |
10372 | if (ins->rex & REX_W) |
10373 | *ins->obufp++ = 'q'; | |
4b4c407a L |
10374 | else |
10375 | { | |
10376 | if (sizeflag & DFLAG) | |
39fb3698 | 10377 | *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; |
4b4c407a | 10378 | else |
39fb3698 VM |
10379 | *ins->obufp++ = 'w'; |
10380 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
4b4c407a | 10381 | } |
52b15da3 | 10382 | } |
252b5132 | 10383 | } |
21a3faeb JB |
10384 | else |
10385 | abort (); | |
252b5132 RH |
10386 | break; |
10387 | case 'Q': | |
21a3faeb | 10388 | if (l == 0) |
252b5132 | 10389 | { |
39fb3698 | 10390 | if (ins->intel_syntax && !alt) |
98b528ac L |
10391 | break; |
10392 | USED_REX (REX_W); | |
39fb3698 | 10393 | if ((ins->need_modrm && ins->modrm.mod != 3) |
0e9f3bf1 | 10394 | || (sizeflag & SUFFIX_ALWAYS)) |
52b15da3 | 10395 | { |
39fb3698 VM |
10396 | if (ins->rex & REX_W) |
10397 | *ins->obufp++ = 'q'; | |
52b15da3 | 10398 | else |
98b528ac L |
10399 | { |
10400 | if (sizeflag & DFLAG) | |
39fb3698 | 10401 | *ins->obufp++ = ins->intel_syntax ? 'd' : 'l'; |
98b528ac | 10402 | else |
39fb3698 VM |
10403 | *ins->obufp++ = 'w'; |
10404 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
98b528ac | 10405 | } |
52b15da3 | 10406 | } |
98b528ac | 10407 | } |
492a76aa | 10408 | else if (l == 1 && last[0] == 'D') |
39fb3698 | 10409 | *ins->obufp++ = ins->vex.w ? 'q' : 'd'; |
21a3faeb | 10410 | else if (l == 1 && last[0] == 'L') |
98b528ac | 10411 | { |
39fb3698 VM |
10412 | if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS) |
10413 | : ins->address_mode != mode_64bit) | |
98b528ac | 10414 | break; |
39fb3698 | 10415 | if ((ins->rex & REX_W)) |
98b528ac L |
10416 | { |
10417 | USED_REX (REX_W); | |
39fb3698 | 10418 | *ins->obufp++ = 'q'; |
98b528ac | 10419 | } |
39fb3698 | 10420 | else if ((ins->address_mode == mode_64bit && cond) |
589958d6 | 10421 | || (sizeflag & SUFFIX_ALWAYS)) |
39fb3698 | 10422 | *ins->obufp++ = ins->intel_syntax? 'd' : 'l'; |
252b5132 | 10423 | } |
21a3faeb JB |
10424 | else |
10425 | abort (); | |
252b5132 RH |
10426 | break; |
10427 | case 'R': | |
161a04f6 | 10428 | USED_REX (REX_W); |
39fb3698 VM |
10429 | if (ins->rex & REX_W) |
10430 | *ins->obufp++ = 'q'; | |
a35ca55a | 10431 | else if (sizeflag & DFLAG) |
c608c12e | 10432 | { |
39fb3698 VM |
10433 | if (ins->intel_syntax) |
10434 | *ins->obufp++ = 'd'; | |
c608c12e | 10435 | else |
39fb3698 | 10436 | *ins->obufp++ = 'l'; |
c608c12e | 10437 | } |
252b5132 | 10438 | else |
39fb3698 VM |
10439 | *ins->obufp++ = 'w'; |
10440 | if (ins->intel_syntax && !p[1] | |
10441 | && ((ins->rex & REX_W) || (sizeflag & DFLAG))) | |
10442 | *ins->obufp++ = 'e'; | |
10443 | if (!(ins->rex & REX_W)) | |
10444 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
252b5132 RH |
10445 | break; |
10446 | case 'S': | |
21a3faeb | 10447 | if (l == 0) |
252b5132 | 10448 | { |
dc1e8a47 | 10449 | case_S: |
39fb3698 | 10450 | if (ins->intel_syntax) |
4b06377f L |
10451 | break; |
10452 | if (sizeflag & SUFFIX_ALWAYS) | |
52b15da3 | 10453 | { |
39fb3698 VM |
10454 | if (ins->rex & REX_W) |
10455 | *ins->obufp++ = 'q'; | |
52b15da3 | 10456 | else |
4b06377f L |
10457 | { |
10458 | if (sizeflag & DFLAG) | |
39fb3698 | 10459 | *ins->obufp++ = 'l'; |
4b06377f | 10460 | else |
39fb3698 VM |
10461 | *ins->obufp++ = 'w'; |
10462 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
4b06377f L |
10463 | } |
10464 | } | |
2235ecb8 | 10465 | break; |
4b06377f | 10466 | } |
2235ecb8 JB |
10467 | if (l != 1) |
10468 | abort (); | |
10469 | switch (last[0]) | |
4b06377f | 10470 | { |
2235ecb8 | 10471 | case 'L': |
39fb3698 VM |
10472 | if (ins->address_mode == mode_64bit |
10473 | && !(ins->prefixes & PREFIX_ADDR)) | |
4b06377f | 10474 | { |
39fb3698 VM |
10475 | *ins->obufp++ = 'a'; |
10476 | *ins->obufp++ = 'b'; | |
10477 | *ins->obufp++ = 's'; | |
4b06377f L |
10478 | } |
10479 | ||
10480 | goto case_S; | |
2235ecb8 | 10481 | case 'X': |
e6cfa893 | 10482 | if (!ins->vex.evex || !ins->vex.w) |
2235ecb8 JB |
10483 | *ins->obufp++ = 's'; |
10484 | else | |
10485 | oappend (ins, "{bad}"); | |
10486 | break; | |
10487 | default: | |
10488 | abort (); | |
252b5132 | 10489 | } |
252b5132 | 10490 | break; |
f0e8d0ba JB |
10491 | case 'V': |
10492 | if (l == 0) | |
b5c37946 SJ |
10493 | { |
10494 | if (ins->need_vex) | |
10495 | *ins->obufp++ = 'v'; | |
10496 | } | |
995bca23 | 10497 | else if (l == 1) |
f0e8d0ba | 10498 | { |
995bca23 | 10499 | switch (last[0]) |
58bf9b6a | 10500 | { |
995bca23 JB |
10501 | case 'X': |
10502 | if (ins->vex.evex) | |
10503 | break; | |
39fb3698 VM |
10504 | *ins->obufp++ = '{'; |
10505 | *ins->obufp++ = 'v'; | |
10506 | *ins->obufp++ = 'e'; | |
10507 | *ins->obufp++ = 'x'; | |
10508 | *ins->obufp++ = '}'; | |
995bca23 JB |
10509 | *ins->obufp++ = ' '; |
10510 | break; | |
10511 | case 'L': | |
fffb10b1 JB |
10512 | if (ins->rex & REX_W) |
10513 | { | |
10514 | *ins->obufp++ = 'a'; | |
10515 | *ins->obufp++ = 'b'; | |
10516 | *ins->obufp++ = 's'; | |
10517 | } | |
10518 | goto case_S; | |
995bca23 JB |
10519 | default: |
10520 | abort (); | |
f0e8d0ba JB |
10521 | } |
10522 | } | |
10523 | else | |
10524 | abort (); | |
fffb10b1 | 10525 | break; |
f0e8d0ba JB |
10526 | case 'W': |
10527 | if (l == 0) | |
10528 | { | |
10529 | /* operand size flag for cwtl, cbtw */ | |
10530 | USED_REX (REX_W); | |
39fb3698 | 10531 | if (ins->rex & REX_W) |
f0e8d0ba | 10532 | { |
39fb3698 VM |
10533 | if (ins->intel_syntax) |
10534 | *ins->obufp++ = 'd'; | |
f0e8d0ba | 10535 | else |
39fb3698 | 10536 | *ins->obufp++ = 'l'; |
f0e8d0ba JB |
10537 | } |
10538 | else if (sizeflag & DFLAG) | |
39fb3698 | 10539 | *ins->obufp++ = 'w'; |
f0e8d0ba | 10540 | else |
39fb3698 VM |
10541 | *ins->obufp++ = 'b'; |
10542 | if (!(ins->rex & REX_W)) | |
10543 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
f0e8d0ba JB |
10544 | } |
10545 | else if (l == 1) | |
10546 | { | |
39fb3698 | 10547 | if (!ins->need_vex) |
f0e8d0ba JB |
10548 | abort (); |
10549 | if (last[0] == 'X') | |
39fb3698 | 10550 | *ins->obufp++ = ins->vex.w ? 'd': 's'; |
f0e8d0ba | 10551 | else if (last[0] == 'B') |
39fb3698 | 10552 | *ins->obufp++ = ins->vex.w ? 'w': 'b'; |
f0e8d0ba JB |
10553 | else |
10554 | abort (); | |
10555 | } | |
10556 | else | |
10557 | abort (); | |
10558 | break; | |
041bd2e0 | 10559 | case 'X': |
21a3faeb JB |
10560 | if (l != 0) |
10561 | abort (); | |
39fb3698 VM |
10562 | if (ins->need_vex |
10563 | ? ins->vex.prefix == DATA_PREFIX_OPCODE | |
10564 | : ins->prefixes & PREFIX_DATA) | |
c0f3af97 | 10565 | { |
39fb3698 VM |
10566 | *ins->obufp++ = 'd'; |
10567 | ins->used_prefixes |= PREFIX_DATA; | |
c0f3af97 | 10568 | } |
041bd2e0 | 10569 | else |
39fb3698 | 10570 | *ins->obufp++ = 's'; |
041bd2e0 | 10571 | break; |
76f227a5 | 10572 | case 'Y': |
b5c37946 SJ |
10573 | if (l == 0) |
10574 | { | |
10575 | if (ins->vex.mask_register_specifier) | |
10576 | ins->illegal_masking = true; | |
10577 | } | |
10578 | else if (l == 1 && last[0] == 'X') | |
c0f3af97 | 10579 | { |
39fb3698 | 10580 | if (!ins->need_vex) |
b5c37946 | 10581 | break; |
39fb3698 VM |
10582 | if (ins->intel_syntax |
10583 | || ((ins->modrm.mod == 3 || ins->vex.b) | |
10584 | && !(sizeflag & SUFFIX_ALWAYS))) | |
c0f3af97 | 10585 | break; |
39fb3698 | 10586 | switch (ins->vex.length) |
c0f3af97 L |
10587 | { |
10588 | case 128: | |
39fb3698 | 10589 | *ins->obufp++ = 'x'; |
c0f3af97 L |
10590 | break; |
10591 | case 256: | |
39fb3698 | 10592 | *ins->obufp++ = 'y'; |
c0f3af97 | 10593 | break; |
04d824a4 | 10594 | case 512: |
39fb3698 | 10595 | if (!ins->vex.evex) |
c0f3af97 | 10596 | default: |
04d824a4 | 10597 | abort (); |
c0f3af97 | 10598 | } |
76f227a5 | 10599 | } |
21a3faeb JB |
10600 | else |
10601 | abort (); | |
76f227a5 | 10602 | break; |
78467458 JB |
10603 | case 'Z': |
10604 | if (l == 0) | |
10605 | { | |
10606 | /* These insns ignore ModR/M.mod: Force it to 3 for OP_E(). */ | |
39fb3698 VM |
10607 | ins->modrm.mod = 3; |
10608 | if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) | |
10609 | *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l'; | |
78467458 JB |
10610 | } |
10611 | else if (l == 1 && last[0] == 'X') | |
10612 | { | |
39fb3698 | 10613 | if (!ins->vex.evex) |
78467458 | 10614 | abort (); |
39fb3698 VM |
10615 | if (ins->intel_syntax |
10616 | || ((ins->modrm.mod == 3 || ins->vex.b) | |
10617 | && !(sizeflag & SUFFIX_ALWAYS))) | |
78467458 | 10618 | break; |
39fb3698 | 10619 | switch (ins->vex.length) |
78467458 JB |
10620 | { |
10621 | case 128: | |
39fb3698 | 10622 | *ins->obufp++ = 'x'; |
78467458 JB |
10623 | break; |
10624 | case 256: | |
39fb3698 | 10625 | *ins->obufp++ = 'y'; |
78467458 JB |
10626 | break; |
10627 | case 512: | |
39fb3698 | 10628 | *ins->obufp++ = 'z'; |
78467458 JB |
10629 | break; |
10630 | default: | |
10631 | abort (); | |
10632 | } | |
10633 | } | |
10634 | else | |
10635 | abort (); | |
10636 | break; | |
a72d2af2 | 10637 | case '^': |
39fb3698 | 10638 | if (ins->intel_syntax) |
a72d2af2 | 10639 | break; |
39fb3698 | 10640 | if (ins->isa64 == intel64 && (ins->rex & REX_W)) |
5990e377 JB |
10641 | { |
10642 | USED_REX (REX_W); | |
39fb3698 | 10643 | *ins->obufp++ = 'q'; |
5990e377 JB |
10644 | break; |
10645 | } | |
39fb3698 | 10646 | if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS)) |
a72d2af2 L |
10647 | { |
10648 | if (sizeflag & DFLAG) | |
39fb3698 | 10649 | *ins->obufp++ = 'l'; |
a72d2af2 | 10650 | else |
39fb3698 VM |
10651 | *ins->obufp++ = 'w'; |
10652 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
a72d2af2 L |
10653 | } |
10654 | break; | |
252b5132 | 10655 | } |
21a3faeb JB |
10656 | |
10657 | if (len == l) | |
10658 | len = l = 0; | |
252b5132 | 10659 | } |
39fb3698 VM |
10660 | *ins->obufp = 0; |
10661 | ins->mnemonicendp = ins->obufp; | |
6439fc28 | 10662 | return 0; |
252b5132 RH |
10663 | } |
10664 | ||
2c3b9a91 AB |
10665 | /* Add a style marker to *INS->obufp that encodes STYLE. This assumes that |
10666 | the buffer pointed to by INS->obufp has space. A style marker is made | |
10667 | from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex | |
10668 | digit, followed by another STYLE_MARKER_CHAR. This function assumes | |
10669 | that the number of styles is not greater than 16. */ | |
10670 | ||
252b5132 | 10671 | static void |
2c3b9a91 | 10672 | oappend_insert_style (instr_info *ins, enum disassembler_style style) |
252b5132 | 10673 | { |
2c3b9a91 AB |
10674 | unsigned num = (unsigned) style; |
10675 | ||
10676 | /* We currently assume that STYLE can be encoded as a single hex | |
10677 | character. If more styles are added then this might start to fail, | |
10678 | and we'll need to expand this code. */ | |
10679 | if (num > 0xf) | |
10680 | abort (); | |
10681 | ||
10682 | *ins->obufp++ = STYLE_MARKER_CHAR; | |
10683 | *ins->obufp++ = (num < 10 ? ('0' + num) | |
10684 | : ((num < 16) ? ('a' + (num - 10)) : '0')); | |
10685 | *ins->obufp++ = STYLE_MARKER_CHAR; | |
10686 | ||
10687 | /* This final null character is not strictly necessary, after inserting a | |
10688 | style marker we should always be inserting some additional content. | |
10689 | However, having the buffer null terminated doesn't cost much, and make | |
10690 | it easier to debug what's going on. Also, if we do ever forget to add | |
10691 | any additional content after this style marker, then the buffer will | |
10692 | still be well formed. */ | |
10693 | *ins->obufp = '\0'; | |
10694 | } | |
10695 | ||
10696 | static void | |
10697 | oappend_with_style (instr_info *ins, const char *s, | |
10698 | enum disassembler_style style) | |
10699 | { | |
10700 | oappend_insert_style (ins, style); | |
39fb3698 | 10701 | ins->obufp = stpcpy (ins->obufp, s); |
252b5132 RH |
10702 | } |
10703 | ||
2c3b9a91 AB |
10704 | /* Add a single character C to the buffer pointer to by INS->obufp, marking |
10705 | the style for the character as STYLE. */ | |
10706 | ||
10707 | static void | |
10708 | oappend_char_with_style (instr_info *ins, const char c, | |
10709 | enum disassembler_style style) | |
10710 | { | |
10711 | oappend_insert_style (ins, style); | |
10712 | *ins->obufp++ = c; | |
10713 | *ins->obufp = '\0'; | |
10714 | } | |
10715 | ||
10716 | /* Like oappend_char_with_style, but always uses dis_style_text. */ | |
10717 | ||
10718 | static void | |
10719 | oappend_char (instr_info *ins, const char c) | |
10720 | { | |
10721 | oappend_char_with_style (ins, c, dis_style_text); | |
10722 | } | |
10723 | ||
252b5132 | 10724 | static void |
39fb3698 | 10725 | append_seg (instr_info *ins) |
252b5132 | 10726 | { |
285ca992 | 10727 | /* Only print the active segment register. */ |
39fb3698 | 10728 | if (!ins->active_seg_prefix) |
285ca992 L |
10729 | return; |
10730 | ||
39fb3698 VM |
10731 | ins->used_prefixes |= ins->active_seg_prefix; |
10732 | switch (ins->active_seg_prefix) | |
7d421014 | 10733 | { |
285ca992 | 10734 | case PREFIX_CS: |
2d9e0890 | 10735 | oappend_register (ins, att_names_seg[1]); |
285ca992 L |
10736 | break; |
10737 | case PREFIX_DS: | |
2d9e0890 | 10738 | oappend_register (ins, att_names_seg[3]); |
285ca992 L |
10739 | break; |
10740 | case PREFIX_SS: | |
2d9e0890 | 10741 | oappend_register (ins, att_names_seg[2]); |
285ca992 L |
10742 | break; |
10743 | case PREFIX_ES: | |
2d9e0890 | 10744 | oappend_register (ins, att_names_seg[0]); |
285ca992 L |
10745 | break; |
10746 | case PREFIX_FS: | |
2d9e0890 | 10747 | oappend_register (ins, att_names_seg[4]); |
285ca992 L |
10748 | break; |
10749 | case PREFIX_GS: | |
2d9e0890 | 10750 | oappend_register (ins, att_names_seg[5]); |
285ca992 L |
10751 | break; |
10752 | default: | |
10753 | break; | |
7d421014 | 10754 | } |
2c3b9a91 | 10755 | oappend_char (ins, ':'); |
252b5132 RH |
10756 | } |
10757 | ||
52b15da3 | 10758 | static void |
5fb28d26 | 10759 | print_operand_value (instr_info *ins, bfd_vma disp, |
95ff6718 | 10760 | enum disassembler_style style) |
52b15da3 | 10761 | { |
95ff6718 JB |
10762 | char tmp[30]; |
10763 | ||
b4617f79 AM |
10764 | if (ins->address_mode != mode_64bit) |
10765 | disp &= 0xffffffff; | |
10766 | sprintf (tmp, "0x%" PRIx64, (uint64_t) disp); | |
f493c217 | 10767 | oappend_with_style (ins, tmp, style); |
52b15da3 JH |
10768 | } |
10769 | ||
95ff6718 JB |
10770 | /* Like oappend, but called for immediate operands. */ |
10771 | ||
10772 | static void | |
10773 | oappend_immediate (instr_info *ins, bfd_vma imm) | |
10774 | { | |
10775 | if (!ins->intel_syntax) | |
10776 | oappend_char_with_style (ins, '$', dis_style_immediate); | |
5fb28d26 | 10777 | print_operand_value (ins, imm, dis_style_immediate); |
95ff6718 JB |
10778 | } |
10779 | ||
5d669648 L |
10780 | /* Put DISP in BUF as signed hex number. */ |
10781 | ||
10782 | static void | |
a82b3c56 | 10783 | print_displacement (instr_info *ins, bfd_signed_vma val) |
5d669648 | 10784 | { |
5d669648 | 10785 | char tmp[30]; |
5d669648 L |
10786 | |
10787 | if (val < 0) | |
10788 | { | |
95ff6718 | 10789 | oappend_char_with_style (ins, '-', dis_style_address_offset); |
a82b3c56 | 10790 | val = (bfd_vma) 0 - val; |
5d669648 L |
10791 | |
10792 | /* Check for possible overflow. */ | |
10793 | if (val < 0) | |
10794 | { | |
39fb3698 | 10795 | switch (ins->address_mode) |
5d669648 L |
10796 | { |
10797 | case mode_64bit: | |
95ff6718 JB |
10798 | oappend_with_style (ins, "0x8000000000000000", |
10799 | dis_style_address_offset); | |
5d669648 L |
10800 | break; |
10801 | case mode_32bit: | |
95ff6718 JB |
10802 | oappend_with_style (ins, "0x80000000", |
10803 | dis_style_address_offset); | |
5d669648 L |
10804 | break; |
10805 | case mode_16bit: | |
95ff6718 JB |
10806 | oappend_with_style (ins, "0x8000", |
10807 | dis_style_address_offset); | |
5d669648 L |
10808 | break; |
10809 | } | |
10810 | return; | |
10811 | } | |
10812 | } | |
10813 | ||
f493c217 AM |
10814 | sprintf (tmp, "0x%" PRIx64, (int64_t) val); |
10815 | oappend_with_style (ins, tmp, dis_style_address_offset); | |
5d669648 L |
10816 | } |
10817 | ||
3f31e633 | 10818 | static void |
39fb3698 | 10819 | intel_operand_size (instr_info *ins, int bytemode, int sizeflag) |
3f31e633 | 10820 | { |
39fb3698 | 10821 | if (ins->vex.b) |
43234a1e | 10822 | { |
39fb3698 | 10823 | if (!ins->vex.no_broadcast) |
2c02075a CL |
10824 | switch (bytemode) |
10825 | { | |
10826 | case x_mode: | |
10827 | case evex_half_bcst_xmmq_mode: | |
39fb3698 | 10828 | if (ins->vex.w) |
811f61d4 | 10829 | oappend (ins, "QWORD BCST "); |
2c02075a | 10830 | else |
811f61d4 | 10831 | oappend (ins, "DWORD BCST "); |
2c02075a CL |
10832 | break; |
10833 | case xh_mode: | |
10834 | case evex_half_bcst_xmmqh_mode: | |
10835 | case evex_half_bcst_xmmqdh_mode: | |
811f61d4 | 10836 | oappend (ins, "WORD BCST "); |
2c02075a CL |
10837 | break; |
10838 | default: | |
ab31da6a | 10839 | ins->vex.no_broadcast = true; |
2c02075a CL |
10840 | break; |
10841 | } | |
43234a1e L |
10842 | return; |
10843 | } | |
3f31e633 JB |
10844 | switch (bytemode) |
10845 | { | |
10846 | case b_mode: | |
b6169b20 | 10847 | case b_swap_mode: |
1ba585e8 | 10848 | case db_mode: |
39fb3698 | 10849 | oappend (ins, "BYTE PTR "); |
3f31e633 JB |
10850 | break; |
10851 | case w_mode: | |
0cc78721 | 10852 | case w_swap_mode: |
1ba585e8 | 10853 | case dw_mode: |
39fb3698 | 10854 | oappend (ins, "WORD PTR "); |
3f31e633 | 10855 | break; |
07f5af7d | 10856 | case indir_v_mode: |
39fb3698 | 10857 | if (ins->address_mode == mode_64bit && ins->isa64 == intel64) |
07f5af7d | 10858 | { |
39fb3698 | 10859 | oappend (ins, "QWORD PTR "); |
07f5af7d L |
10860 | break; |
10861 | } | |
1a0670f3 | 10862 | /* Fall through. */ |
1a114b12 | 10863 | case stack_v_mode: |
39fb3698 VM |
10864 | if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG) |
10865 | || (ins->rex & REX_W))) | |
3f31e633 | 10866 | { |
39fb3698 | 10867 | oappend (ins, "QWORD PTR "); |
3f31e633 JB |
10868 | break; |
10869 | } | |
1a0670f3 | 10870 | /* Fall through. */ |
3f31e633 | 10871 | case v_mode: |
b6169b20 | 10872 | case v_swap_mode: |
3f31e633 | 10873 | case dq_mode: |
161a04f6 | 10874 | USED_REX (REX_W); |
39fb3698 VM |
10875 | if (ins->rex & REX_W) |
10876 | oappend (ins, "QWORD PTR "); | |
035e7389 | 10877 | else if (bytemode == dq_mode) |
39fb3698 | 10878 | oappend (ins, "DWORD PTR "); |
3f31e633 | 10879 | else |
f16cd0d5 | 10880 | { |
035e7389 | 10881 | if (sizeflag & DFLAG) |
39fb3698 | 10882 | oappend (ins, "DWORD PTR "); |
f16cd0d5 | 10883 | else |
39fb3698 VM |
10884 | oappend (ins, "WORD PTR "); |
10885 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
f16cd0d5 | 10886 | } |
3f31e633 | 10887 | break; |
52fd6d94 | 10888 | case z_mode: |
39fb3698 VM |
10889 | if ((ins->rex & REX_W) || (sizeflag & DFLAG)) |
10890 | *ins->obufp++ = 'D'; | |
10891 | oappend (ins, "WORD PTR "); | |
10892 | if (!(ins->rex & REX_W)) | |
10893 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
52fd6d94 | 10894 | break; |
34b772a6 JB |
10895 | case a_mode: |
10896 | if (sizeflag & DFLAG) | |
39fb3698 | 10897 | oappend (ins, "QWORD PTR "); |
34b772a6 | 10898 | else |
39fb3698 VM |
10899 | oappend (ins, "DWORD PTR "); |
10900 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
34b772a6 | 10901 | break; |
bc31405e | 10902 | case movsxd_mode: |
39fb3698 VM |
10903 | if (!(sizeflag & DFLAG) && ins->isa64 == intel64) |
10904 | oappend (ins, "WORD PTR "); | |
bc31405e | 10905 | else |
39fb3698 VM |
10906 | oappend (ins, "DWORD PTR "); |
10907 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
bc31405e | 10908 | break; |
3f31e633 | 10909 | case d_mode: |
fa99fab2 | 10910 | case d_swap_mode: |
39fb3698 | 10911 | oappend (ins, "DWORD PTR "); |
3f31e633 JB |
10912 | break; |
10913 | case q_mode: | |
b6169b20 | 10914 | case q_swap_mode: |
39fb3698 | 10915 | oappend (ins, "QWORD PTR "); |
3f31e633 JB |
10916 | break; |
10917 | case m_mode: | |
39fb3698 VM |
10918 | if (ins->address_mode == mode_64bit) |
10919 | oappend (ins, "QWORD PTR "); | |
3f31e633 | 10920 | else |
39fb3698 | 10921 | oappend (ins, "DWORD PTR "); |
3f31e633 JB |
10922 | break; |
10923 | case f_mode: | |
10924 | if (sizeflag & DFLAG) | |
39fb3698 | 10925 | oappend (ins, "FWORD PTR "); |
3f31e633 | 10926 | else |
39fb3698 VM |
10927 | oappend (ins, "DWORD PTR "); |
10928 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
3f31e633 JB |
10929 | break; |
10930 | case t_mode: | |
39fb3698 | 10931 | oappend (ins, "TBYTE PTR "); |
3f31e633 JB |
10932 | break; |
10933 | case x_mode: | |
0cc78721 | 10934 | case xh_mode: |
b6169b20 | 10935 | case x_swap_mode: |
43234a1e L |
10936 | case evex_x_gscat_mode: |
10937 | case evex_x_nobcst_mode: | |
4726e9a4 | 10938 | case bw_unit_mode: |
39fb3698 | 10939 | if (ins->need_vex) |
c0f3af97 | 10940 | { |
39fb3698 | 10941 | switch (ins->vex.length) |
c0f3af97 L |
10942 | { |
10943 | case 128: | |
39fb3698 | 10944 | oappend (ins, "XMMWORD PTR "); |
c0f3af97 L |
10945 | break; |
10946 | case 256: | |
39fb3698 | 10947 | oappend (ins, "YMMWORD PTR "); |
c0f3af97 | 10948 | break; |
43234a1e | 10949 | case 512: |
39fb3698 | 10950 | oappend (ins, "ZMMWORD PTR "); |
43234a1e | 10951 | break; |
c0f3af97 L |
10952 | default: |
10953 | abort (); | |
10954 | } | |
10955 | } | |
10956 | else | |
39fb3698 | 10957 | oappend (ins, "XMMWORD PTR "); |
c0f3af97 L |
10958 | break; |
10959 | case xmm_mode: | |
39fb3698 | 10960 | oappend (ins, "XMMWORD PTR "); |
3f31e633 | 10961 | break; |
43234a1e | 10962 | case ymm_mode: |
39fb3698 | 10963 | oappend (ins, "YMMWORD PTR "); |
43234a1e | 10964 | break; |
c0f3af97 | 10965 | case xmmq_mode: |
0cc78721 | 10966 | case evex_half_bcst_xmmqh_mode: |
43234a1e | 10967 | case evex_half_bcst_xmmq_mode: |
39fb3698 | 10968 | switch (ins->vex.length) |
c0f3af97 | 10969 | { |
b5c37946 | 10970 | case 0: |
c0f3af97 | 10971 | case 128: |
39fb3698 | 10972 | oappend (ins, "QWORD PTR "); |
c0f3af97 L |
10973 | break; |
10974 | case 256: | |
39fb3698 | 10975 | oappend (ins, "XMMWORD PTR "); |
c0f3af97 | 10976 | break; |
43234a1e | 10977 | case 512: |
39fb3698 | 10978 | oappend (ins, "YMMWORD PTR "); |
43234a1e | 10979 | break; |
c0f3af97 L |
10980 | default: |
10981 | abort (); | |
10982 | } | |
10983 | break; | |
6c30d220 | 10984 | case xmmdw_mode: |
39fb3698 | 10985 | if (!ins->need_vex) |
6c30d220 L |
10986 | abort (); |
10987 | ||
39fb3698 | 10988 | switch (ins->vex.length) |
6c30d220 L |
10989 | { |
10990 | case 128: | |
39fb3698 | 10991 | oappend (ins, "WORD PTR "); |
6c30d220 L |
10992 | break; |
10993 | case 256: | |
39fb3698 | 10994 | oappend (ins, "DWORD PTR "); |
6c30d220 | 10995 | break; |
43234a1e | 10996 | case 512: |
39fb3698 | 10997 | oappend (ins, "QWORD PTR "); |
43234a1e | 10998 | break; |
6c30d220 L |
10999 | default: |
11000 | abort (); | |
11001 | } | |
11002 | break; | |
11003 | case xmmqd_mode: | |
0cc78721 | 11004 | case evex_half_bcst_xmmqdh_mode: |
39fb3698 | 11005 | if (!ins->need_vex) |
6c30d220 L |
11006 | abort (); |
11007 | ||
39fb3698 | 11008 | switch (ins->vex.length) |
6c30d220 L |
11009 | { |
11010 | case 128: | |
39fb3698 | 11011 | oappend (ins, "DWORD PTR "); |
6c30d220 L |
11012 | break; |
11013 | case 256: | |
39fb3698 | 11014 | oappend (ins, "QWORD PTR "); |
6c30d220 | 11015 | break; |
43234a1e | 11016 | case 512: |
39fb3698 | 11017 | oappend (ins, "XMMWORD PTR "); |
43234a1e | 11018 | break; |
6c30d220 L |
11019 | default: |
11020 | abort (); | |
11021 | } | |
11022 | break; | |
c0f3af97 | 11023 | case ymmq_mode: |
39fb3698 | 11024 | if (!ins->need_vex) |
c0f3af97 L |
11025 | abort (); |
11026 | ||
39fb3698 | 11027 | switch (ins->vex.length) |
c0f3af97 L |
11028 | { |
11029 | case 128: | |
39fb3698 | 11030 | oappend (ins, "QWORD PTR "); |
c0f3af97 L |
11031 | break; |
11032 | case 256: | |
39fb3698 | 11033 | oappend (ins, "YMMWORD PTR "); |
c0f3af97 | 11034 | break; |
43234a1e | 11035 | case 512: |
39fb3698 | 11036 | oappend (ins, "ZMMWORD PTR "); |
43234a1e | 11037 | break; |
c0f3af97 L |
11038 | default: |
11039 | abort (); | |
11040 | } | |
11041 | break; | |
fb9c77c7 | 11042 | case o_mode: |
39fb3698 | 11043 | oappend (ins, "OWORD PTR "); |
fb9c77c7 | 11044 | break; |
43234a1e L |
11045 | case vex_vsib_d_w_dq_mode: |
11046 | case vex_vsib_q_w_dq_mode: | |
39fb3698 | 11047 | if (!ins->need_vex) |
43234a1e | 11048 | abort (); |
39fb3698 VM |
11049 | if (ins->vex.w) |
11050 | oappend (ins, "QWORD PTR "); | |
43234a1e | 11051 | else |
39fb3698 | 11052 | oappend (ins, "DWORD PTR "); |
5fc35d96 | 11053 | break; |
1ba585e8 | 11054 | case mask_bd_mode: |
39fb3698 | 11055 | if (!ins->need_vex || ins->vex.length != 128) |
1ba585e8 | 11056 | abort (); |
39fb3698 VM |
11057 | if (ins->vex.w) |
11058 | oappend (ins, "DWORD PTR "); | |
1ba585e8 | 11059 | else |
39fb3698 | 11060 | oappend (ins, "BYTE PTR "); |
1ba585e8 | 11061 | break; |
43234a1e | 11062 | case mask_mode: |
39fb3698 | 11063 | if (!ins->need_vex) |
43234a1e | 11064 | abort (); |
39fb3698 VM |
11065 | if (ins->vex.w) |
11066 | oappend (ins, "QWORD PTR "); | |
1ba585e8 | 11067 | else |
39fb3698 | 11068 | oappend (ins, "WORD PTR "); |
43234a1e | 11069 | break; |
6c75cc62 | 11070 | case v_bnd_mode: |
d276ec69 | 11071 | case v_bndmk_mode: |
3f31e633 JB |
11072 | default: |
11073 | break; | |
11074 | } | |
11075 | } | |
11076 | ||
252b5132 | 11077 | static void |
39fb3698 VM |
11078 | print_register (instr_info *ins, unsigned int reg, unsigned int rexmask, |
11079 | int bytemode, int sizeflag) | |
252b5132 | 11080 | { |
2d9e0890 | 11081 | const char (*names)[8]; |
252b5132 | 11082 | |
b5c37946 SJ |
11083 | /* Masking is invalid for insns with GPR destination. Set the flag uniformly, |
11084 | as the consumer will inspect it only for the destination operand. */ | |
11085 | if (bytemode != mask_mode && ins->vex.mask_register_specifier) | |
11086 | ins->illegal_masking = true; | |
11087 | ||
5f6b8397 | 11088 | USED_REX (rexmask); |
39fb3698 | 11089 | if (ins->rex & rexmask) |
c0f3af97 | 11090 | reg += 8; |
252b5132 | 11091 | |
c0f3af97 | 11092 | switch (bytemode) |
252b5132 | 11093 | { |
c0f3af97 | 11094 | case b_mode: |
b6169b20 | 11095 | case b_swap_mode: |
e184e611 JB |
11096 | if (reg & 4) |
11097 | USED_REX (0); | |
39fb3698 | 11098 | if (ins->rex) |
e564475a | 11099 | names = att_names8rex; |
c0f3af97 | 11100 | else |
e564475a | 11101 | names = att_names8; |
c0f3af97 L |
11102 | break; |
11103 | case w_mode: | |
e564475a | 11104 | names = att_names16; |
c0f3af97 L |
11105 | break; |
11106 | case d_mode: | |
1ba585e8 IT |
11107 | case dw_mode: |
11108 | case db_mode: | |
e564475a | 11109 | names = att_names32; |
c0f3af97 L |
11110 | break; |
11111 | case q_mode: | |
e564475a | 11112 | names = att_names64; |
c0f3af97 L |
11113 | break; |
11114 | case m_mode: | |
6c75cc62 | 11115 | case v_bnd_mode: |
e564475a | 11116 | names = ins->address_mode == mode_64bit ? att_names64 : att_names32; |
c0f3af97 | 11117 | break; |
7e8b059b | 11118 | case bnd_mode: |
9f79e886 | 11119 | case bnd_swap_mode: |
0d96e4df L |
11120 | if (reg > 0x3) |
11121 | { | |
39fb3698 | 11122 | oappend (ins, "(bad)"); |
0d96e4df L |
11123 | return; |
11124 | } | |
e564475a | 11125 | names = att_names_bnd; |
7e8b059b | 11126 | break; |
07f5af7d | 11127 | case indir_v_mode: |
39fb3698 | 11128 | if (ins->address_mode == mode_64bit && ins->isa64 == intel64) |
07f5af7d | 11129 | { |
e564475a | 11130 | names = att_names64; |
07f5af7d L |
11131 | break; |
11132 | } | |
1a0670f3 | 11133 | /* Fall through. */ |
c0f3af97 | 11134 | case stack_v_mode: |
39fb3698 VM |
11135 | if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG) |
11136 | || (ins->rex & REX_W))) | |
252b5132 | 11137 | { |
e564475a | 11138 | names = att_names64; |
252b5132 | 11139 | break; |
252b5132 | 11140 | } |
c0f3af97 | 11141 | bytemode = v_mode; |
1a0670f3 | 11142 | /* Fall through. */ |
c0f3af97 | 11143 | case v_mode: |
b6169b20 | 11144 | case v_swap_mode: |
c0f3af97 | 11145 | case dq_mode: |
c0f3af97 | 11146 | USED_REX (REX_W); |
39fb3698 | 11147 | if (ins->rex & REX_W) |
e564475a | 11148 | names = att_names64; |
035e7389 | 11149 | else if (bytemode != v_mode && bytemode != v_swap_mode) |
e564475a | 11150 | names = att_names32; |
c0f3af97 | 11151 | else |
f16cd0d5 | 11152 | { |
035e7389 | 11153 | if (sizeflag & DFLAG) |
e564475a | 11154 | names = att_names32; |
f16cd0d5 | 11155 | else |
e564475a | 11156 | names = att_names16; |
39fb3698 | 11157 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
f16cd0d5 | 11158 | } |
c0f3af97 | 11159 | break; |
bc31405e | 11160 | case movsxd_mode: |
39fb3698 | 11161 | if (!(sizeflag & DFLAG) && ins->isa64 == intel64) |
e564475a | 11162 | names = att_names16; |
bc31405e | 11163 | else |
e564475a | 11164 | names = att_names32; |
39fb3698 | 11165 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
bc31405e | 11166 | break; |
de89d0a3 | 11167 | case va_mode: |
39fb3698 | 11168 | names = (ins->address_mode == mode_64bit |
e564475a | 11169 | ? att_names64 : att_names32); |
39fb3698 VM |
11170 | if (!(ins->prefixes & PREFIX_ADDR)) |
11171 | names = (ins->address_mode == mode_16bit | |
e564475a | 11172 | ? att_names16 : names); |
de89d0a3 IT |
11173 | else |
11174 | { | |
11175 | /* Remove "addr16/addr32". */ | |
39fb3698 VM |
11176 | ins->all_prefixes[ins->last_addr_prefix] = 0; |
11177 | names = (ins->address_mode != mode_32bit | |
e564475a | 11178 | ? att_names32 : att_names16); |
39fb3698 | 11179 | ins->used_prefixes |= PREFIX_ADDR; |
de89d0a3 IT |
11180 | } |
11181 | break; | |
1ba585e8 | 11182 | case mask_bd_mode: |
43234a1e | 11183 | case mask_mode: |
9889cbb1 L |
11184 | if (reg > 0x7) |
11185 | { | |
39fb3698 | 11186 | oappend (ins, "(bad)"); |
9889cbb1 L |
11187 | return; |
11188 | } | |
e564475a | 11189 | names = att_names_mask; |
43234a1e | 11190 | break; |
c0f3af97 L |
11191 | case 0: |
11192 | return; | |
11193 | default: | |
39fb3698 | 11194 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
252b5132 RH |
11195 | return; |
11196 | } | |
2c3b9a91 | 11197 | oappend_register (ins, names[reg]); |
c0f3af97 L |
11198 | } |
11199 | ||
a675ea09 JB |
11200 | static bool |
11201 | get8s (instr_info *ins, bfd_vma *res) | |
11202 | { | |
11203 | if (!fetch_code (ins->info, ins->codep + 1)) | |
11204 | return false; | |
a4aa034a | 11205 | *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80; |
a675ea09 JB |
11206 | return true; |
11207 | } | |
11208 | ||
11209 | static bool | |
11210 | get16 (instr_info *ins, bfd_vma *res) | |
11211 | { | |
11212 | if (!fetch_code (ins->info, ins->codep + 2)) | |
11213 | return false; | |
a4aa034a JB |
11214 | *res = *ins->codep++; |
11215 | *res |= (bfd_vma) *ins->codep++ << 8; | |
a675ea09 JB |
11216 | return true; |
11217 | } | |
11218 | ||
11219 | static bool | |
11220 | get16s (instr_info *ins, bfd_vma *res) | |
11221 | { | |
11222 | if (!get16 (ins, res)) | |
11223 | return false; | |
11224 | *res = (*res ^ 0x8000) - 0x8000; | |
11225 | return true; | |
11226 | } | |
11227 | ||
11228 | static bool | |
11229 | get32 (instr_info *ins, bfd_vma *res) | |
11230 | { | |
11231 | if (!fetch_code (ins->info, ins->codep + 4)) | |
11232 | return false; | |
a4aa034a JB |
11233 | *res = *ins->codep++; |
11234 | *res |= (bfd_vma) *ins->codep++ << 8; | |
11235 | *res |= (bfd_vma) *ins->codep++ << 16; | |
11236 | *res |= (bfd_vma) *ins->codep++ << 24; | |
a675ea09 JB |
11237 | return true; |
11238 | } | |
11239 | ||
11240 | static bool | |
11241 | get32s (instr_info *ins, bfd_vma *res) | |
11242 | { | |
11243 | if (!get32 (ins, res)) | |
11244 | return false; | |
11245 | ||
11246 | *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31); | |
11247 | ||
11248 | return true; | |
11249 | } | |
11250 | ||
11251 | static bool | |
11252 | get64 (instr_info *ins, uint64_t *res) | |
11253 | { | |
11254 | unsigned int a; | |
11255 | unsigned int b; | |
11256 | ||
11257 | if (!fetch_code (ins->info, ins->codep + 8)) | |
11258 | return false; | |
a4aa034a JB |
11259 | a = *ins->codep++; |
11260 | a |= (unsigned int) *ins->codep++ << 8; | |
11261 | a |= (unsigned int) *ins->codep++ << 16; | |
11262 | a |= (unsigned int) *ins->codep++ << 24; | |
11263 | b = *ins->codep++; | |
11264 | b |= (unsigned int) *ins->codep++ << 8; | |
11265 | b |= (unsigned int) *ins->codep++ << 16; | |
11266 | b |= (unsigned int) *ins->codep++ << 24; | |
a675ea09 JB |
11267 | *res = a + ((uint64_t) b << 32); |
11268 | return true; | |
11269 | } | |
11270 | ||
2aa11c29 JB |
11271 | static void |
11272 | set_op (instr_info *ins, bfd_vma op, bool riprel) | |
11273 | { | |
11274 | ins->op_index[ins->op_ad] = ins->op_ad; | |
11275 | if (ins->address_mode == mode_64bit) | |
11276 | ins->op_address[ins->op_ad] = op; | |
11277 | else /* Mask to get a 32-bit address. */ | |
11278 | ins->op_address[ins->op_ad] = op & 0xffffffff; | |
11279 | ins->op_riprel[ins->op_ad] = riprel; | |
11280 | } | |
11281 | ||
11282 | static bool | |
11283 | BadOp (instr_info *ins) | |
11284 | { | |
11285 | /* Throw away prefixes and 1st. opcode byte. */ | |
1a3b4f90 JB |
11286 | struct dis_private *priv = ins->info->private_data; |
11287 | ||
b5c37946 | 11288 | ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1; |
2aa11c29 JB |
11289 | ins->obufp = stpcpy (ins->obufp, "(bad)"); |
11290 | return true; | |
11291 | } | |
11292 | ||
b5c37946 SJ |
11293 | static bool |
11294 | OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, | |
11295 | int sizeflag ATTRIBUTE_UNUSED) | |
11296 | { | |
11297 | if (ins->modrm.mod != 3) | |
11298 | return BadOp (ins); | |
11299 | ||
11300 | /* Skip mod/rm byte. */ | |
11301 | MODRM_CHECK; | |
11302 | ins->codep++; | |
11303 | return true; | |
11304 | } | |
11305 | ||
97601363 | 11306 | static bool |
39fb3698 | 11307 | OP_E_memory (instr_info *ins, int bytemode, int sizeflag) |
c0f3af97 | 11308 | { |
39fb3698 | 11309 | int add = (ins->rex & REX_B) ? 8 : 0; |
c0f3af97 | 11310 | int riprel = 0; |
43234a1e L |
11311 | int shift; |
11312 | ||
39fb3698 | 11313 | if (ins->vex.evex) |
43234a1e | 11314 | { |
b5c37946 SJ |
11315 | |
11316 | /* Zeroing-masking is invalid for memory destinations. Set the flag | |
11317 | uniformly, as the consumer will inspect it only for the destination | |
11318 | operand. */ | |
11319 | if (ins->vex.zeroing) | |
11320 | ins->illegal_masking = true; | |
11321 | ||
43234a1e L |
11322 | switch (bytemode) |
11323 | { | |
1ba585e8 | 11324 | case dw_mode: |
c1d66d5f | 11325 | case w_mode: |
0cc78721 | 11326 | case w_swap_mode: |
1ba585e8 IT |
11327 | shift = 1; |
11328 | break; | |
1ba585e8 | 11329 | case db_mode: |
c1d66d5f | 11330 | case b_mode: |
1ba585e8 IT |
11331 | shift = 0; |
11332 | break; | |
b50c9f31 | 11333 | case dq_mode: |
39fb3698 | 11334 | if (ins->address_mode != mode_64bit) |
b50c9f31 | 11335 | { |
059edf8b JB |
11336 | case d_mode: |
11337 | case d_swap_mode: | |
b50c9f31 JB |
11338 | shift = 2; |
11339 | break; | |
11340 | } | |
11341 | /* fall through */ | |
43234a1e | 11342 | case vex_vsib_d_w_dq_mode: |
eaa9d1ad | 11343 | case vex_vsib_q_w_dq_mode: |
43234a1e | 11344 | case evex_x_gscat_mode: |
39fb3698 | 11345 | shift = ins->vex.w ? 3 : 2; |
43234a1e | 11346 | break; |
0cc78721 CL |
11347 | case xh_mode: |
11348 | case evex_half_bcst_xmmqh_mode: | |
11349 | case evex_half_bcst_xmmqdh_mode: | |
39fb3698 | 11350 | if (ins->vex.b) |
0cc78721 | 11351 | { |
39fb3698 | 11352 | shift = ins->vex.w ? 2 : 1; |
0cc78721 CL |
11353 | break; |
11354 | } | |
11355 | /* Fall through. */ | |
43234a1e L |
11356 | case x_mode: |
11357 | case evex_half_bcst_xmmq_mode: | |
39fb3698 | 11358 | if (ins->vex.b) |
43234a1e | 11359 | { |
39fb3698 | 11360 | shift = ins->vex.w ? 3 : 2; |
43234a1e L |
11361 | break; |
11362 | } | |
1a0670f3 | 11363 | /* Fall through. */ |
43234a1e L |
11364 | case xmmqd_mode: |
11365 | case xmmdw_mode: | |
da944c8a | 11366 | case xmmq_mode: |
43234a1e L |
11367 | case ymmq_mode: |
11368 | case evex_x_nobcst_mode: | |
11369 | case x_swap_mode: | |
39fb3698 | 11370 | switch (ins->vex.length) |
43234a1e L |
11371 | { |
11372 | case 128: | |
11373 | shift = 4; | |
11374 | break; | |
11375 | case 256: | |
11376 | shift = 5; | |
11377 | break; | |
11378 | case 512: | |
11379 | shift = 6; | |
11380 | break; | |
11381 | default: | |
11382 | abort (); | |
11383 | } | |
059edf8b JB |
11384 | /* Make necessary corrections to shift for modes that need it. */ |
11385 | if (bytemode == xmmq_mode | |
0cc78721 | 11386 | || bytemode == evex_half_bcst_xmmqh_mode |
059edf8b | 11387 | || bytemode == evex_half_bcst_xmmq_mode |
39fb3698 | 11388 | || (bytemode == ymmq_mode && ins->vex.length == 128)) |
059edf8b | 11389 | shift -= 1; |
0cc78721 CL |
11390 | else if (bytemode == xmmqd_mode |
11391 | || bytemode == evex_half_bcst_xmmqdh_mode) | |
059edf8b JB |
11392 | shift -= 2; |
11393 | else if (bytemode == xmmdw_mode) | |
11394 | shift -= 3; | |
43234a1e L |
11395 | break; |
11396 | case ymm_mode: | |
11397 | shift = 5; | |
11398 | break; | |
11399 | case xmm_mode: | |
11400 | shift = 4; | |
11401 | break; | |
43234a1e | 11402 | case q_mode: |
43234a1e | 11403 | case q_swap_mode: |
43234a1e L |
11404 | shift = 3; |
11405 | break; | |
4726e9a4 | 11406 | case bw_unit_mode: |
39fb3698 | 11407 | shift = ins->vex.w ? 1 : 0; |
4726e9a4 | 11408 | break; |
43234a1e L |
11409 | default: |
11410 | abort (); | |
11411 | } | |
43234a1e L |
11412 | } |
11413 | else | |
11414 | shift = 0; | |
252b5132 | 11415 | |
c0f3af97 | 11416 | USED_REX (REX_B); |
39fb3698 VM |
11417 | if (ins->intel_syntax) |
11418 | intel_operand_size (ins, bytemode, sizeflag); | |
11419 | append_seg (ins); | |
252b5132 | 11420 | |
39fb3698 | 11421 | if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) |
252b5132 | 11422 | { |
5d669648 | 11423 | /* 32/64 bit address mode */ |
b4617f79 | 11424 | bfd_vma disp = 0; |
5d669648 | 11425 | int havedisp; |
252b5132 | 11426 | int havebase; |
20afcfb7 | 11427 | int needindex; |
1bc60e56 | 11428 | int needaddr32; |
82c18208 | 11429 | int base, rbase; |
91d6fa6a | 11430 | int vindex = 0; |
252b5132 | 11431 | int scale = 0; |
7e8b059b L |
11432 | int addr32flag = !((sizeflag & AFLAG) |
11433 | || bytemode == v_bnd_mode | |
d276ec69 | 11434 | || bytemode == v_bndmk_mode |
9f79e886 JB |
11435 | || bytemode == bnd_mode |
11436 | || bytemode == bnd_swap_mode); | |
78933a4a | 11437 | bool check_gather = false; |
2d9e0890 | 11438 | const char (*indexes)[8] = NULL; |
252b5132 | 11439 | |
252b5132 | 11440 | havebase = 1; |
39fb3698 | 11441 | base = ins->modrm.rm; |
252b5132 RH |
11442 | |
11443 | if (base == 4) | |
11444 | { | |
39fb3698 | 11445 | vindex = ins->sib.index; |
161a04f6 | 11446 | USED_REX (REX_X); |
39fb3698 | 11447 | if (ins->rex & REX_X) |
91d6fa6a | 11448 | vindex += 8; |
6c30d220 L |
11449 | switch (bytemode) |
11450 | { | |
11451 | case vex_vsib_d_w_dq_mode: | |
11452 | case vex_vsib_q_w_dq_mode: | |
39fb3698 | 11453 | if (!ins->need_vex) |
6c30d220 | 11454 | abort (); |
39fb3698 | 11455 | if (ins->vex.evex) |
43234a1e | 11456 | { |
39fb3698 | 11457 | if (!ins->vex.v) |
43234a1e | 11458 | vindex += 16; |
39fb3698 | 11459 | check_gather = ins->obufp == ins->op_out[1]; |
43234a1e | 11460 | } |
6c30d220 | 11461 | |
39fb3698 | 11462 | switch (ins->vex.length) |
6c30d220 L |
11463 | { |
11464 | case 128: | |
e1f9fbb8 | 11465 | indexes = att_names_xmm; |
6c30d220 L |
11466 | break; |
11467 | case 256: | |
39fb3698 | 11468 | if (!ins->vex.w |
b763d508 | 11469 | || bytemode == vex_vsib_q_w_dq_mode) |
e1f9fbb8 | 11470 | indexes = att_names_ymm; |
6c30d220 | 11471 | else |
e1f9fbb8 | 11472 | indexes = att_names_xmm; |
6c30d220 | 11473 | break; |
43234a1e | 11474 | case 512: |
39fb3698 | 11475 | if (!ins->vex.w |
b763d508 | 11476 | || bytemode == vex_vsib_q_w_dq_mode) |
e1f9fbb8 | 11477 | indexes = att_names_zmm; |
43234a1e | 11478 | else |
e1f9fbb8 | 11479 | indexes = att_names_ymm; |
43234a1e | 11480 | break; |
6c30d220 L |
11481 | default: |
11482 | abort (); | |
11483 | } | |
11484 | break; | |
11485 | default: | |
e1f9fbb8 JB |
11486 | if (vindex != 4) |
11487 | indexes = ins->address_mode == mode_64bit && !addr32flag | |
11488 | ? att_names64 : att_names32; | |
6c30d220 L |
11489 | break; |
11490 | } | |
39fb3698 VM |
11491 | scale = ins->sib.scale; |
11492 | base = ins->sib.base; | |
11493 | ins->codep++; | |
252b5132 | 11494 | } |
260cd341 LC |
11495 | else |
11496 | { | |
596a02ff JB |
11497 | /* Check for mandatory SIB. */ |
11498 | if (bytemode == vex_vsib_d_w_dq_mode | |
11499 | || bytemode == vex_vsib_q_w_dq_mode | |
11500 | || bytemode == vex_sibmem_mode) | |
260cd341 | 11501 | { |
39fb3698 | 11502 | oappend (ins, "(bad)"); |
97601363 | 11503 | return true; |
260cd341 LC |
11504 | } |
11505 | } | |
82c18208 | 11506 | rbase = base + add; |
252b5132 | 11507 | |
39fb3698 | 11508 | switch (ins->modrm.mod) |
252b5132 RH |
11509 | { |
11510 | case 0: | |
82c18208 | 11511 | if (base == 5) |
252b5132 RH |
11512 | { |
11513 | havebase = 0; | |
ce20459e | 11514 | if (ins->address_mode == mode_64bit && !ins->has_sib) |
52b15da3 | 11515 | riprel = 1; |
a82b3c56 JB |
11516 | if (!get32s (ins, &disp)) |
11517 | return false; | |
d276ec69 JB |
11518 | if (riprel && bytemode == v_bndmk_mode) |
11519 | { | |
39fb3698 | 11520 | oappend (ins, "(bad)"); |
97601363 | 11521 | return true; |
d276ec69 | 11522 | } |
252b5132 RH |
11523 | } |
11524 | break; | |
11525 | case 1: | |
b4617f79 | 11526 | if (!get8s (ins, &disp)) |
97601363 | 11527 | return false; |
39fb3698 | 11528 | if (ins->vex.evex && shift > 0) |
43234a1e | 11529 | disp <<= shift; |
252b5132 RH |
11530 | break; |
11531 | case 2: | |
a82b3c56 JB |
11532 | if (!get32s (ins, &disp)) |
11533 | return false; | |
252b5132 RH |
11534 | break; |
11535 | } | |
11536 | ||
1bc60e56 L |
11537 | needindex = 0; |
11538 | needaddr32 = 0; | |
ce20459e | 11539 | if (ins->has_sib |
1bc60e56 | 11540 | && !havebase |
e1f9fbb8 | 11541 | && !indexes |
39fb3698 | 11542 | && ins->address_mode != mode_16bit) |
1bc60e56 | 11543 | { |
39fb3698 | 11544 | if (ins->address_mode == mode_64bit) |
1bc60e56 | 11545 | { |
8e58ef80 L |
11546 | if (addr32flag) |
11547 | { | |
11548 | /* Without base nor index registers, zero-extend the | |
11549 | lower 32-bit displacement to 64 bits. */ | |
b4617f79 | 11550 | disp &= 0xffffffff; |
bf4ba07c | 11551 | needindex = 1; |
8e58ef80 | 11552 | } |
1bc60e56 L |
11553 | needaddr32 = 1; |
11554 | } | |
11555 | else | |
11556 | { | |
11557 | /* In 32-bit mode, we need index register to tell [offset] | |
11558 | from [eiz*1 + offset]. */ | |
11559 | needindex = 1; | |
11560 | } | |
11561 | } | |
11562 | ||
20afcfb7 L |
11563 | havedisp = (havebase |
11564 | || needindex | |
ce20459e | 11565 | || (ins->has_sib && (indexes || scale != 0))); |
5d669648 | 11566 | |
39fb3698 VM |
11567 | if (!ins->intel_syntax) |
11568 | if (ins->modrm.mod != 0 || base == 5) | |
db6eb5be | 11569 | { |
5d669648 | 11570 | if (havedisp || riprel) |
95ff6718 | 11571 | print_displacement (ins, disp); |
5d669648 | 11572 | else |
5fb28d26 | 11573 | print_operand_value (ins, disp, dis_style_address_offset); |
52b15da3 JH |
11574 | if (riprel) |
11575 | { | |
4bb8b8e9 | 11576 | set_op (ins, disp, true); |
2c3b9a91 AB |
11577 | oappend_char (ins, '('); |
11578 | oappend_with_style (ins, !addr32flag ? "%rip" : "%eip", | |
11579 | dis_style_register); | |
11580 | oappend_char (ins, ')'); | |
52b15da3 | 11581 | } |
db6eb5be | 11582 | } |
2da11e11 | 11583 | |
e1f9fbb8 | 11584 | if ((havebase || indexes || needindex || needaddr32 || riprel) |
39fb3698 | 11585 | && (ins->address_mode != mode_64bit |
a23b33b3 JB |
11586 | || ((bytemode != v_bnd_mode) |
11587 | && (bytemode != v_bndmk_mode) | |
11588 | && (bytemode != bnd_mode) | |
11589 | && (bytemode != bnd_swap_mode)))) | |
39fb3698 | 11590 | ins->used_prefixes |= PREFIX_ADDR; |
87767711 | 11591 | |
39fb3698 | 11592 | if (havedisp || (ins->intel_syntax && riprel)) |
252b5132 | 11593 | { |
2c3b9a91 | 11594 | oappend_char (ins, ins->open_char); |
39fb3698 | 11595 | if (ins->intel_syntax && riprel) |
185b1163 | 11596 | { |
4bb8b8e9 | 11597 | set_op (ins, disp, true); |
2c3b9a91 AB |
11598 | oappend_with_style (ins, !addr32flag ? "rip" : "eip", |
11599 | dis_style_register); | |
185b1163 | 11600 | } |
252b5132 | 11601 | if (havebase) |
2c3b9a91 AB |
11602 | oappend_register |
11603 | (ins, | |
11604 | (ins->address_mode == mode_64bit && !addr32flag | |
11605 | ? att_names64 : att_names32)[rbase]); | |
ce20459e | 11606 | if (ins->has_sib) |
252b5132 | 11607 | { |
db51cc60 L |
11608 | /* ESP/RSP won't allow index. If base isn't ESP/RSP, |
11609 | print index to tell base + index from base. */ | |
11610 | if (scale != 0 | |
20afcfb7 | 11611 | || needindex |
e1f9fbb8 | 11612 | || indexes |
db51cc60 | 11613 | || (havebase && base != ESP_REG_NUM)) |
252b5132 | 11614 | { |
39fb3698 | 11615 | if (!ins->intel_syntax || havebase) |
2c3b9a91 | 11616 | oappend_char (ins, ins->separator_char); |
e1f9fbb8 | 11617 | if (indexes) |
54ca11a4 | 11618 | { |
39fb3698 | 11619 | if (ins->address_mode == mode_64bit || vindex < 16) |
2c3b9a91 | 11620 | oappend_register (ins, indexes[vindex]); |
54ca11a4 | 11621 | else |
39fb3698 | 11622 | oappend (ins, "(bad)"); |
54ca11a4 | 11623 | } |
db51cc60 | 11624 | else |
2c3b9a91 AB |
11625 | oappend_register (ins, |
11626 | ins->address_mode == mode_64bit | |
11627 | && !addr32flag | |
11628 | ? att_index64 | |
11629 | : att_index32); | |
db51cc60 | 11630 | |
2c3b9a91 | 11631 | oappend_char (ins, ins->scale_char); |
95ff6718 JB |
11632 | oappend_char_with_style (ins, '0' + (1 << scale), |
11633 | dis_style_immediate); | |
db6eb5be | 11634 | } |
252b5132 | 11635 | } |
39fb3698 VM |
11636 | if (ins->intel_syntax |
11637 | && (disp || ins->modrm.mod != 0 || base == 5)) | |
3d456fa1 | 11638 | { |
b4617f79 | 11639 | if (!havedisp || (bfd_signed_vma) disp >= 0) |
2c3b9a91 | 11640 | oappend_char (ins, '+'); |
db51cc60 | 11641 | if (havedisp) |
95ff6718 | 11642 | print_displacement (ins, disp); |
db51cc60 | 11643 | else |
5fb28d26 | 11644 | print_operand_value (ins, disp, dis_style_address_offset); |
3d456fa1 | 11645 | } |
252b5132 | 11646 | |
2c3b9a91 | 11647 | oappend_char (ins, ins->close_char); |
596a02ff JB |
11648 | |
11649 | if (check_gather) | |
11650 | { | |
11651 | /* Both XMM/YMM/ZMM registers must be distinct. */ | |
39fb3698 | 11652 | int modrm_reg = ins->modrm.reg; |
596a02ff | 11653 | |
39fb3698 | 11654 | if (ins->rex & REX_R) |
596a02ff | 11655 | modrm_reg += 8; |
39fb3698 | 11656 | if (!ins->vex.r) |
596a02ff JB |
11657 | modrm_reg += 16; |
11658 | if (vindex == modrm_reg) | |
39fb3698 | 11659 | oappend (ins, "/(bad)"); |
596a02ff | 11660 | } |
252b5132 | 11661 | } |
39fb3698 | 11662 | else if (ins->intel_syntax) |
db6eb5be | 11663 | { |
39fb3698 | 11664 | if (ins->modrm.mod != 0 || base == 5) |
db6eb5be | 11665 | { |
39fb3698 | 11666 | if (!ins->active_seg_prefix) |
252b5132 | 11667 | { |
2c3b9a91 | 11668 | oappend_register (ins, att_names_seg[ds_reg - es_reg]); |
39fb3698 | 11669 | oappend (ins, ":"); |
252b5132 | 11670 | } |
5fb28d26 | 11671 | print_operand_value (ins, disp, dis_style_text); |
db6eb5be AM |
11672 | } |
11673 | } | |
252b5132 | 11674 | } |
a23b33b3 JB |
11675 | else if (bytemode == v_bnd_mode |
11676 | || bytemode == v_bndmk_mode | |
11677 | || bytemode == bnd_mode | |
596a02ff JB |
11678 | || bytemode == bnd_swap_mode |
11679 | || bytemode == vex_vsib_d_w_dq_mode | |
11680 | || bytemode == vex_vsib_q_w_dq_mode) | |
a23b33b3 | 11681 | { |
39fb3698 | 11682 | oappend (ins, "(bad)"); |
97601363 | 11683 | return true; |
a23b33b3 | 11684 | } |
252b5132 | 11685 | else |
f16cd0d5 L |
11686 | { |
11687 | /* 16 bit address mode */ | |
b4617f79 | 11688 | bfd_vma disp = 0; |
a82b3c56 | 11689 | |
39fb3698 VM |
11690 | ins->used_prefixes |= ins->prefixes & PREFIX_ADDR; |
11691 | switch (ins->modrm.mod) | |
252b5132 RH |
11692 | { |
11693 | case 0: | |
39fb3698 | 11694 | if (ins->modrm.rm == 6) |
252b5132 | 11695 | { |
a82b3c56 | 11696 | case 2: |
b4617f79 | 11697 | if (!get16s (ins, &disp)) |
a82b3c56 | 11698 | return false; |
252b5132 RH |
11699 | } |
11700 | break; | |
11701 | case 1: | |
b4617f79 | 11702 | if (!get8s (ins, &disp)) |
97601363 | 11703 | return false; |
39fb3698 | 11704 | if (ins->vex.evex && shift > 0) |
65f3ed04 | 11705 | disp <<= shift; |
252b5132 | 11706 | break; |
252b5132 RH |
11707 | } |
11708 | ||
39fb3698 VM |
11709 | if (!ins->intel_syntax) |
11710 | if (ins->modrm.mod != 0 || ins->modrm.rm == 6) | |
95ff6718 | 11711 | print_displacement (ins, disp); |
252b5132 | 11712 | |
39fb3698 | 11713 | if (ins->modrm.mod != 0 || ins->modrm.rm != 6) |
252b5132 | 11714 | { |
2c3b9a91 | 11715 | oappend_char (ins, ins->open_char); |
2d9e0890 JB |
11716 | oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm] |
11717 | : att_index16[ins->modrm.rm]); | |
39fb3698 VM |
11718 | if (ins->intel_syntax |
11719 | && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6)) | |
3d456fa1 | 11720 | { |
b4617f79 | 11721 | if ((bfd_signed_vma) disp >= 0) |
2c3b9a91 | 11722 | oappend_char (ins, '+'); |
95ff6718 | 11723 | print_displacement (ins, disp); |
3d456fa1 JB |
11724 | } |
11725 | ||
2c3b9a91 | 11726 | oappend_char (ins, ins->close_char); |
252b5132 | 11727 | } |
39fb3698 | 11728 | else if (ins->intel_syntax) |
3d456fa1 | 11729 | { |
39fb3698 | 11730 | if (!ins->active_seg_prefix) |
3d456fa1 | 11731 | { |
2c3b9a91 | 11732 | oappend_register (ins, att_names_seg[ds_reg - es_reg]); |
39fb3698 | 11733 | oappend (ins, ":"); |
3d456fa1 | 11734 | } |
5fb28d26 | 11735 | print_operand_value (ins, disp & 0xffff, dis_style_text); |
3d456fa1 | 11736 | } |
252b5132 | 11737 | } |
39fb3698 | 11738 | if (ins->vex.b) |
43234a1e | 11739 | { |
39fb3698 | 11740 | ins->evex_used |= EVEX_b_used; |
a364447b JB |
11741 | |
11742 | /* Broadcast can only ever be valid for memory sources. */ | |
11743 | if (ins->obufp == ins->op_out[0]) | |
ab31da6a | 11744 | ins->vex.no_broadcast = true; |
a364447b | 11745 | |
811f61d4 JB |
11746 | if (!ins->vex.no_broadcast |
11747 | && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used))) | |
b28d1bda | 11748 | { |
2c02075a | 11749 | if (bytemode == xh_mode) |
b28d1bda | 11750 | { |
40849d84 | 11751 | switch (ins->vex.length) |
2c02075a | 11752 | { |
40849d84 HJ |
11753 | case 128: |
11754 | oappend (ins, "{1to8}"); | |
11755 | break; | |
11756 | case 256: | |
11757 | oappend (ins, "{1to16}"); | |
11758 | break; | |
11759 | case 512: | |
11760 | oappend (ins, "{1to32}"); | |
11761 | break; | |
11762 | default: | |
11763 | abort (); | |
2c02075a | 11764 | } |
b28d1bda | 11765 | } |
a364447b JB |
11766 | else if (bytemode == q_mode |
11767 | || bytemode == ymmq_mode) | |
ab31da6a | 11768 | ins->vex.no_broadcast = true; |
39fb3698 | 11769 | else if (ins->vex.w |
2c02075a CL |
11770 | || bytemode == evex_half_bcst_xmmqdh_mode |
11771 | || bytemode == evex_half_bcst_xmmq_mode) | |
b28d1bda | 11772 | { |
39fb3698 | 11773 | switch (ins->vex.length) |
2c02075a CL |
11774 | { |
11775 | case 128: | |
39fb3698 | 11776 | oappend (ins, "{1to2}"); |
2c02075a CL |
11777 | break; |
11778 | case 256: | |
39fb3698 | 11779 | oappend (ins, "{1to4}"); |
2c02075a CL |
11780 | break; |
11781 | case 512: | |
39fb3698 | 11782 | oappend (ins, "{1to8}"); |
2c02075a CL |
11783 | break; |
11784 | default: | |
11785 | abort (); | |
11786 | } | |
11787 | } | |
11788 | else if (bytemode == x_mode | |
11789 | || bytemode == evex_half_bcst_xmmqh_mode) | |
11790 | { | |
39fb3698 | 11791 | switch (ins->vex.length) |
2c02075a CL |
11792 | { |
11793 | case 128: | |
39fb3698 | 11794 | oappend (ins, "{1to4}"); |
2c02075a CL |
11795 | break; |
11796 | case 256: | |
39fb3698 | 11797 | oappend (ins, "{1to8}"); |
2c02075a CL |
11798 | break; |
11799 | case 512: | |
39fb3698 | 11800 | oappend (ins, "{1to16}"); |
2c02075a CL |
11801 | break; |
11802 | default: | |
11803 | abort (); | |
11804 | } | |
b28d1bda | 11805 | } |
2c02075a | 11806 | else |
ab31da6a | 11807 | ins->vex.no_broadcast = true; |
b28d1bda | 11808 | } |
39fb3698 VM |
11809 | if (ins->vex.no_broadcast) |
11810 | oappend (ins, "{bad}"); | |
43234a1e | 11811 | } |
97601363 JB |
11812 | |
11813 | return true; | |
252b5132 RH |
11814 | } |
11815 | ||
97601363 | 11816 | static bool |
39fb3698 | 11817 | OP_E (instr_info *ins, int bytemode, int sizeflag) |
c0f3af97 L |
11818 | { |
11819 | /* Skip mod/rm byte. */ | |
11820 | MODRM_CHECK; | |
39fb3698 | 11821 | ins->codep++; |
c0f3af97 | 11822 | |
39fb3698 | 11823 | if (ins->modrm.mod == 3) |
5f6b8397 JB |
11824 | { |
11825 | if ((sizeflag & SUFFIX_ALWAYS) | |
11826 | && (bytemode == b_swap_mode | |
11827 | || bytemode == bnd_swap_mode | |
11828 | || bytemode == v_swap_mode)) | |
39fb3698 | 11829 | swap_operand (ins); |
5f6b8397 | 11830 | |
39fb3698 | 11831 | print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag); |
97601363 | 11832 | return true; |
5f6b8397 | 11833 | } |
97601363 | 11834 | |
b5c37946 SJ |
11835 | /* Masking is invalid for insns with GPR-like memory destination. Set the |
11836 | flag uniformly, as the consumer will inspect it only for the destination | |
11837 | operand. */ | |
11838 | if (ins->vex.mask_register_specifier) | |
11839 | ins->illegal_masking = true; | |
11840 | ||
97601363 | 11841 | return OP_E_memory (ins, bytemode, sizeflag); |
c0f3af97 L |
11842 | } |
11843 | ||
b5c37946 SJ |
11844 | static bool |
11845 | OP_indirE (instr_info *ins, int bytemode, int sizeflag) | |
11846 | { | |
11847 | if (ins->modrm.mod == 3 && bytemode == f_mode) | |
11848 | /* bad lcall/ljmp */ | |
11849 | return BadOp (ins); | |
11850 | if (!ins->intel_syntax) | |
11851 | oappend (ins, "*"); | |
11852 | return OP_E (ins, bytemode, sizeflag); | |
11853 | } | |
11854 | ||
97601363 | 11855 | static bool |
39fb3698 | 11856 | OP_G (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 11857 | { |
39fb3698 | 11858 | if (ins->vex.evex && !ins->vex.r && ins->address_mode == mode_64bit) |
97601363 JB |
11859 | oappend (ins, "(bad)"); |
11860 | else | |
11861 | print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag); | |
11862 | return true; | |
252b5132 RH |
11863 | } |
11864 | ||
97601363 | 11865 | static bool |
39fb3698 | 11866 | OP_REG (instr_info *ins, int code, int sizeflag) |
252b5132 | 11867 | { |
2da11e11 | 11868 | const char *s; |
9b60702d | 11869 | int add; |
de882298 RM |
11870 | |
11871 | switch (code) | |
11872 | { | |
11873 | case es_reg: case ss_reg: case cs_reg: | |
11874 | case ds_reg: case fs_reg: case gs_reg: | |
2c3b9a91 | 11875 | oappend_register (ins, att_names_seg[code - es_reg]); |
97601363 | 11876 | return true; |
de882298 RM |
11877 | } |
11878 | ||
161a04f6 | 11879 | USED_REX (REX_B); |
39fb3698 | 11880 | if (ins->rex & REX_B) |
52b15da3 | 11881 | add = 8; |
9b60702d L |
11882 | else |
11883 | add = 0; | |
52b15da3 JH |
11884 | |
11885 | switch (code) | |
11886 | { | |
52b15da3 JH |
11887 | case ax_reg: case cx_reg: case dx_reg: case bx_reg: |
11888 | case sp_reg: case bp_reg: case si_reg: case di_reg: | |
e564475a | 11889 | s = att_names16[code - ax_reg + add]; |
52b15da3 | 11890 | break; |
e184e611 | 11891 | case ah_reg: case ch_reg: case dh_reg: case bh_reg: |
52b15da3 | 11892 | USED_REX (0); |
e184e611 JB |
11893 | /* Fall through. */ |
11894 | case al_reg: case cl_reg: case dl_reg: case bl_reg: | |
39fb3698 | 11895 | if (ins->rex) |
e564475a | 11896 | s = att_names8rex[code - al_reg + add]; |
52b15da3 | 11897 | else |
e564475a | 11898 | s = att_names8[code - al_reg]; |
52b15da3 | 11899 | break; |
6439fc28 AM |
11900 | case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg: |
11901 | case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg: | |
39fb3698 VM |
11902 | if (ins->address_mode == mode_64bit |
11903 | && ((sizeflag & DFLAG) || (ins->rex & REX_W))) | |
6439fc28 | 11904 | { |
e564475a | 11905 | s = att_names64[code - rAX_reg + add]; |
6439fc28 AM |
11906 | break; |
11907 | } | |
11908 | code += eAX_reg - rAX_reg; | |
6608db57 | 11909 | /* Fall through. */ |
52b15da3 JH |
11910 | case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg: |
11911 | case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg: | |
161a04f6 | 11912 | USED_REX (REX_W); |
39fb3698 | 11913 | if (ins->rex & REX_W) |
e564475a | 11914 | s = att_names64[code - eAX_reg + add]; |
52b15da3 | 11915 | else |
f16cd0d5 L |
11916 | { |
11917 | if (sizeflag & DFLAG) | |
e564475a | 11918 | s = att_names32[code - eAX_reg + add]; |
f16cd0d5 | 11919 | else |
e564475a | 11920 | s = att_names16[code - eAX_reg + add]; |
39fb3698 | 11921 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
f16cd0d5 | 11922 | } |
52b15da3 | 11923 | break; |
52b15da3 | 11924 | default: |
e564475a | 11925 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
97601363 | 11926 | return true; |
52b15da3 | 11927 | } |
2c3b9a91 | 11928 | oappend_register (ins, s); |
97601363 | 11929 | return true; |
52b15da3 JH |
11930 | } |
11931 | ||
97601363 | 11932 | static bool |
39fb3698 | 11933 | OP_IMREG (instr_info *ins, int code, int sizeflag) |
52b15da3 JH |
11934 | { |
11935 | const char *s; | |
252b5132 RH |
11936 | |
11937 | switch (code) | |
11938 | { | |
11939 | case indir_dx_reg: | |
e564475a JB |
11940 | if (!ins->intel_syntax) |
11941 | { | |
11942 | oappend (ins, "(%dx)"); | |
97601363 | 11943 | return true; |
e564475a JB |
11944 | } |
11945 | s = att_names16[dx_reg - ax_reg]; | |
252b5132 | 11946 | break; |
e8b5d5f9 | 11947 | case al_reg: case cl_reg: |
e564475a | 11948 | s = att_names8[code - al_reg]; |
252b5132 | 11949 | break; |
e8b5d5f9 | 11950 | case eAX_reg: |
161a04f6 | 11951 | USED_REX (REX_W); |
39fb3698 | 11952 | if (ins->rex & REX_W) |
f16cd0d5 | 11953 | { |
e564475a | 11954 | s = *att_names64; |
e8b5d5f9 | 11955 | break; |
f16cd0d5 | 11956 | } |
e8b5d5f9 | 11957 | /* Fall through. */ |
52fd6d94 | 11958 | case z_mode_ax_reg: |
39fb3698 | 11959 | if ((ins->rex & REX_W) || (sizeflag & DFLAG)) |
e564475a | 11960 | s = *att_names32; |
52fd6d94 | 11961 | else |
e564475a | 11962 | s = *att_names16; |
39fb3698 VM |
11963 | if (!(ins->rex & REX_W)) |
11964 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
52fd6d94 | 11965 | break; |
252b5132 | 11966 | default: |
e564475a | 11967 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
97601363 | 11968 | return true; |
252b5132 | 11969 | } |
2c3b9a91 | 11970 | oappend_register (ins, s); |
97601363 | 11971 | return true; |
252b5132 RH |
11972 | } |
11973 | ||
97601363 | 11974 | static bool |
39fb3698 | 11975 | OP_I (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 11976 | { |
b4617f79 | 11977 | bfd_vma op; |
252b5132 RH |
11978 | |
11979 | switch (bytemode) | |
11980 | { | |
11981 | case b_mode: | |
97601363 JB |
11982 | if (!fetch_code (ins->info, ins->codep + 1)) |
11983 | return false; | |
a4aa034a | 11984 | op = *ins->codep++; |
52b15da3 | 11985 | break; |
252b5132 | 11986 | case v_mode: |
161a04f6 | 11987 | USED_REX (REX_W); |
39fb3698 | 11988 | if (ins->rex & REX_W) |
a82b3c56 JB |
11989 | { |
11990 | if (!get32s (ins, &op)) | |
11991 | return false; | |
11992 | } | |
252b5132 | 11993 | else |
52b15da3 | 11994 | { |
a82b3c56 | 11995 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
f16cd0d5 L |
11996 | if (sizeflag & DFLAG) |
11997 | { | |
a82b3c56 JB |
11998 | case d_mode: |
11999 | if (!get32 (ins, &op)) | |
12000 | return false; | |
f16cd0d5 L |
12001 | } |
12002 | else | |
12003 | { | |
b4617f79 | 12004 | /* Fall through. */ |
a82b3c56 | 12005 | case w_mode: |
b4617f79 | 12006 | if (!get16 (ins, &op)) |
a82b3c56 | 12007 | return false; |
f16cd0d5 | 12008 | } |
52b15da3 | 12009 | } |
252b5132 | 12010 | break; |
9306ca4a | 12011 | case const_1_mode: |
39fb3698 VM |
12012 | if (ins->intel_syntax) |
12013 | oappend (ins, "1"); | |
97601363 | 12014 | return true; |
252b5132 | 12015 | default: |
39fb3698 | 12016 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
97601363 | 12017 | return true; |
252b5132 RH |
12018 | } |
12019 | ||
95ff6718 | 12020 | oappend_immediate (ins, op); |
97601363 | 12021 | return true; |
52b15da3 JH |
12022 | } |
12023 | ||
97601363 | 12024 | static bool |
39fb3698 | 12025 | OP_I64 (instr_info *ins, int bytemode, int sizeflag) |
52b15da3 | 12026 | { |
32c8e726 | 12027 | uint64_t op; |
a82b3c56 | 12028 | |
39fb3698 VM |
12029 | if (bytemode != v_mode || ins->address_mode != mode_64bit |
12030 | || !(ins->rex & REX_W)) | |
97601363 | 12031 | return OP_I (ins, bytemode, sizeflag); |
6439fc28 | 12032 | |
a280ab8e | 12033 | USED_REX (REX_W); |
52b15da3 | 12034 | |
a82b3c56 JB |
12035 | if (!get64 (ins, &op)) |
12036 | return false; | |
12037 | ||
12038 | oappend_immediate (ins, op); | |
97601363 | 12039 | return true; |
252b5132 RH |
12040 | } |
12041 | ||
97601363 | 12042 | static bool |
39fb3698 | 12043 | OP_sI (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 12044 | { |
b4617f79 | 12045 | bfd_vma op; |
252b5132 RH |
12046 | |
12047 | switch (bytemode) | |
12048 | { | |
12049 | case b_mode: | |
e3949f17 | 12050 | case b_T_mode: |
b4617f79 | 12051 | if (!get8s (ins, &op)) |
97601363 | 12052 | return false; |
e3949f17 L |
12053 | if (bytemode == b_T_mode) |
12054 | { | |
39fb3698 VM |
12055 | if (ins->address_mode != mode_64bit |
12056 | || !((sizeflag & DFLAG) || (ins->rex & REX_W))) | |
e3949f17 | 12057 | { |
6c067bbb | 12058 | /* The operand-size prefix is overridden by a REX prefix. */ |
39fb3698 | 12059 | if ((sizeflag & DFLAG) || (ins->rex & REX_W)) |
e3949f17 L |
12060 | op &= 0xffffffff; |
12061 | else | |
12062 | op &= 0xffff; | |
12063 | } | |
12064 | } | |
12065 | else | |
12066 | { | |
39fb3698 | 12067 | if (!(ins->rex & REX_W)) |
e3949f17 L |
12068 | { |
12069 | if (sizeflag & DFLAG) | |
12070 | op &= 0xffffffff; | |
12071 | else | |
12072 | op &= 0xffff; | |
12073 | } | |
12074 | } | |
252b5132 RH |
12075 | break; |
12076 | case v_mode: | |
7bb15c6f | 12077 | /* The operand-size prefix is overridden by a REX prefix. */ |
a82b3c56 JB |
12078 | if (!(sizeflag & DFLAG) && !(ins->rex & REX_W)) |
12079 | { | |
b4617f79 | 12080 | if (!get16 (ins, &op)) |
a82b3c56 | 12081 | return false; |
a82b3c56 JB |
12082 | } |
12083 | else if (!get32s (ins, &op)) | |
12084 | return false; | |
252b5132 RH |
12085 | break; |
12086 | default: | |
39fb3698 | 12087 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
97601363 | 12088 | return true; |
252b5132 | 12089 | } |
52b15da3 | 12090 | |
95ff6718 | 12091 | oappend_immediate (ins, op); |
97601363 | 12092 | return true; |
252b5132 RH |
12093 | } |
12094 | ||
97601363 | 12095 | static bool |
39fb3698 | 12096 | OP_J (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 12097 | { |
52b15da3 | 12098 | bfd_vma disp; |
7081ff04 | 12099 | bfd_vma mask = -1; |
65ca155d | 12100 | bfd_vma segment = 0; |
252b5132 RH |
12101 | |
12102 | switch (bytemode) | |
12103 | { | |
12104 | case b_mode: | |
b4617f79 | 12105 | if (!get8s (ins, &disp)) |
97601363 | 12106 | return false; |
252b5132 RH |
12107 | break; |
12108 | case v_mode: | |
376cd056 | 12109 | case dqw_mode: |
5db04b09 | 12110 | if ((sizeflag & DFLAG) |
39fb3698 VM |
12111 | || (ins->address_mode == mode_64bit |
12112 | && ((ins->isa64 == intel64 && bytemode != dqw_mode) | |
12113 | || (ins->rex & REX_W)))) | |
a82b3c56 | 12114 | { |
b4617f79 | 12115 | if (!get32s (ins, &disp)) |
a82b3c56 | 12116 | return false; |
a82b3c56 | 12117 | } |
252b5132 RH |
12118 | else |
12119 | { | |
b4617f79 | 12120 | if (!get16s (ins, &disp)) |
da9a978a | 12121 | return false; |
65ca155d L |
12122 | /* In 16bit mode, address is wrapped around at 64k within |
12123 | the same segment. Otherwise, a data16 prefix on a jump | |
12124 | instruction means that the pc is masked to 16 bits after | |
12125 | the displacement is added! */ | |
12126 | mask = 0xffff; | |
39fb3698 VM |
12127 | if ((ins->prefixes & PREFIX_DATA) == 0) |
12128 | segment = ((ins->start_pc + (ins->codep - ins->start_codep)) | |
65ca155d | 12129 | & ~((bfd_vma) 0xffff)); |
252b5132 | 12130 | } |
39fb3698 VM |
12131 | if (ins->address_mode != mode_64bit |
12132 | || (ins->isa64 != intel64 && !(ins->rex & REX_W))) | |
12133 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
252b5132 RH |
12134 | break; |
12135 | default: | |
39fb3698 | 12136 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
97601363 | 12137 | return true; |
252b5132 | 12138 | } |
39fb3698 VM |
12139 | disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask) |
12140 | | segment; | |
4bb8b8e9 | 12141 | set_op (ins, disp, false); |
5fb28d26 | 12142 | print_operand_value (ins, disp, dis_style_text); |
97601363 | 12143 | return true; |
252b5132 RH |
12144 | } |
12145 | ||
97601363 | 12146 | static bool |
39fb3698 | 12147 | OP_SEG (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 12148 | { |
ed7841b3 | 12149 | if (bytemode == w_mode) |
97601363 JB |
12150 | { |
12151 | oappend_register (ins, att_names_seg[ins->modrm.reg]); | |
12152 | return true; | |
12153 | } | |
12154 | return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag); | |
252b5132 RH |
12155 | } |
12156 | ||
97601363 | 12157 | static bool |
39fb3698 | 12158 | OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag) |
252b5132 | 12159 | { |
b4617f79 AM |
12160 | bfd_vma seg, offset; |
12161 | int res; | |
95ff6718 | 12162 | char scratch[24]; |
252b5132 | 12163 | |
c608c12e | 12164 | if (sizeflag & DFLAG) |
252b5132 | 12165 | { |
b4617f79 | 12166 | if (!get32 (ins, &offset)) |
a82b3c56 | 12167 | return false;; |
c608c12e | 12168 | } |
a82b3c56 JB |
12169 | else if (!get16 (ins, &offset)) |
12170 | return false; | |
12171 | if (!get16 (ins, &seg)) | |
12172 | return false;; | |
39fb3698 | 12173 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
95ff6718 JB |
12174 | |
12175 | res = snprintf (scratch, ARRAY_SIZE (scratch), | |
12176 | ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x", | |
b4617f79 | 12177 | (unsigned) seg, (unsigned) offset); |
95ff6718 JB |
12178 | if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) |
12179 | abort (); | |
12180 | oappend (ins, scratch); | |
97601363 | 12181 | return true; |
252b5132 RH |
12182 | } |
12183 | ||
97601363 | 12184 | static bool |
39fb3698 | 12185 | OP_OFF (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 12186 | { |
52b15da3 | 12187 | bfd_vma off; |
252b5132 | 12188 | |
39fb3698 VM |
12189 | if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12190 | intel_operand_size (ins, bytemode, sizeflag); | |
12191 | append_seg (ins); | |
252b5132 | 12192 | |
39fb3698 | 12193 | if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit) |
a82b3c56 | 12194 | { |
b4617f79 | 12195 | if (!get32 (ins, &off)) |
a82b3c56 | 12196 | return false; |
a82b3c56 | 12197 | } |
252b5132 | 12198 | else |
a82b3c56 | 12199 | { |
b4617f79 | 12200 | if (!get16 (ins, &off)) |
a82b3c56 | 12201 | return false; |
a82b3c56 | 12202 | } |
252b5132 | 12203 | |
39fb3698 | 12204 | if (ins->intel_syntax) |
252b5132 | 12205 | { |
39fb3698 | 12206 | if (!ins->active_seg_prefix) |
252b5132 | 12207 | { |
2c3b9a91 | 12208 | oappend_register (ins, att_names_seg[ds_reg - es_reg]); |
39fb3698 | 12209 | oappend (ins, ":"); |
252b5132 RH |
12210 | } |
12211 | } | |
5fb28d26 | 12212 | print_operand_value (ins, off, dis_style_address_offset); |
97601363 | 12213 | return true; |
52b15da3 | 12214 | } |
6439fc28 | 12215 | |
97601363 | 12216 | static bool |
39fb3698 | 12217 | OP_OFF64 (instr_info *ins, int bytemode, int sizeflag) |
52b15da3 | 12218 | { |
32c8e726 | 12219 | uint64_t off; |
52b15da3 | 12220 | |
39fb3698 VM |
12221 | if (ins->address_mode != mode_64bit |
12222 | || (ins->prefixes & PREFIX_ADDR)) | |
97601363 | 12223 | return OP_OFF (ins, bytemode, sizeflag); |
6439fc28 | 12224 | |
39fb3698 VM |
12225 | if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS)) |
12226 | intel_operand_size (ins, bytemode, sizeflag); | |
12227 | append_seg (ins); | |
52b15da3 | 12228 | |
a82b3c56 JB |
12229 | if (!get64 (ins, &off)) |
12230 | return false; | |
52b15da3 | 12231 | |
39fb3698 | 12232 | if (ins->intel_syntax) |
52b15da3 | 12233 | { |
39fb3698 | 12234 | if (!ins->active_seg_prefix) |
52b15da3 | 12235 | { |
2c3b9a91 | 12236 | oappend_register (ins, att_names_seg[ds_reg - es_reg]); |
39fb3698 | 12237 | oappend (ins, ":"); |
52b15da3 JH |
12238 | } |
12239 | } | |
5fb28d26 | 12240 | print_operand_value (ins, off, dis_style_address_offset); |
97601363 | 12241 | return true; |
252b5132 RH |
12242 | } |
12243 | ||
12244 | static void | |
39fb3698 | 12245 | ptr_reg (instr_info *ins, int code, int sizeflag) |
252b5132 | 12246 | { |
2da11e11 | 12247 | const char *s; |
d708bcba | 12248 | |
39fb3698 VM |
12249 | *ins->obufp++ = ins->open_char; |
12250 | ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR); | |
12251 | if (ins->address_mode == mode_64bit) | |
c1a64871 JH |
12252 | { |
12253 | if (!(sizeflag & AFLAG)) | |
e564475a | 12254 | s = att_names32[code - eAX_reg]; |
c1a64871 | 12255 | else |
e564475a | 12256 | s = att_names64[code - eAX_reg]; |
c1a64871 | 12257 | } |
52b15da3 | 12258 | else if (sizeflag & AFLAG) |
e564475a | 12259 | s = att_names32[code - eAX_reg]; |
252b5132 | 12260 | else |
e564475a | 12261 | s = att_names16[code - eAX_reg]; |
2c3b9a91 AB |
12262 | oappend_register (ins, s); |
12263 | oappend_char (ins, ins->close_char); | |
252b5132 RH |
12264 | } |
12265 | ||
97601363 | 12266 | static bool |
39fb3698 | 12267 | OP_ESreg (instr_info *ins, int code, int sizeflag) |
252b5132 | 12268 | { |
39fb3698 | 12269 | if (ins->intel_syntax) |
52fd6d94 | 12270 | { |
a4aa034a | 12271 | switch (ins->codep[-1]) |
52fd6d94 JB |
12272 | { |
12273 | case 0x6d: /* insw/insl */ | |
39fb3698 | 12274 | intel_operand_size (ins, z_mode, sizeflag); |
52fd6d94 JB |
12275 | break; |
12276 | case 0xa5: /* movsw/movsl/movsq */ | |
12277 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12278 | case 0xab: /* stosw/stosl */ | |
12279 | case 0xaf: /* scasw/scasl */ | |
39fb3698 | 12280 | intel_operand_size (ins, v_mode, sizeflag); |
52fd6d94 JB |
12281 | break; |
12282 | default: | |
39fb3698 | 12283 | intel_operand_size (ins, b_mode, sizeflag); |
52fd6d94 JB |
12284 | } |
12285 | } | |
2d9e0890 | 12286 | oappend_register (ins, att_names_seg[0]); |
2c3b9a91 | 12287 | oappend_char (ins, ':'); |
39fb3698 | 12288 | ptr_reg (ins, code, sizeflag); |
97601363 | 12289 | return true; |
252b5132 RH |
12290 | } |
12291 | ||
97601363 | 12292 | static bool |
39fb3698 | 12293 | OP_DSreg (instr_info *ins, int code, int sizeflag) |
252b5132 | 12294 | { |
39fb3698 | 12295 | if (ins->intel_syntax) |
52fd6d94 | 12296 | { |
a4aa034a | 12297 | switch (ins->codep[-1]) |
52fd6d94 JB |
12298 | { |
12299 | case 0x6f: /* outsw/outsl */ | |
39fb3698 | 12300 | intel_operand_size (ins, z_mode, sizeflag); |
52fd6d94 JB |
12301 | break; |
12302 | case 0xa5: /* movsw/movsl/movsq */ | |
12303 | case 0xa7: /* cmpsw/cmpsl/cmpsq */ | |
12304 | case 0xad: /* lodsw/lodsl/lodsq */ | |
39fb3698 | 12305 | intel_operand_size (ins, v_mode, sizeflag); |
52fd6d94 JB |
12306 | break; |
12307 | default: | |
39fb3698 | 12308 | intel_operand_size (ins, b_mode, sizeflag); |
52fd6d94 JB |
12309 | } |
12310 | } | |
39fb3698 | 12311 | /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the |
285ca992 | 12312 | default segment register DS is printed. */ |
39fb3698 VM |
12313 | if (!ins->active_seg_prefix) |
12314 | ins->active_seg_prefix = PREFIX_DS; | |
12315 | append_seg (ins); | |
12316 | ptr_reg (ins, code, sizeflag); | |
97601363 | 12317 | return true; |
252b5132 RH |
12318 | } |
12319 | ||
97601363 | 12320 | static bool |
39fb3698 VM |
12321 | OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED, |
12322 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 | 12323 | { |
95ff6718 JB |
12324 | int add, res; |
12325 | char scratch[8]; | |
12326 | ||
39fb3698 | 12327 | if (ins->rex & REX_R) |
c4a530c5 | 12328 | { |
161a04f6 | 12329 | USED_REX (REX_R); |
c4a530c5 JB |
12330 | add = 8; |
12331 | } | |
39fb3698 | 12332 | else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK)) |
c4a530c5 | 12333 | { |
39fb3698 VM |
12334 | ins->all_prefixes[ins->last_lock_prefix] = 0; |
12335 | ins->used_prefixes |= PREFIX_LOCK; | |
c4a530c5 JB |
12336 | add = 8; |
12337 | } | |
9b60702d L |
12338 | else |
12339 | add = 0; | |
95ff6718 JB |
12340 | res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d", |
12341 | ins->modrm.reg + add); | |
12342 | if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) | |
12343 | abort (); | |
12344 | oappend_register (ins, scratch); | |
97601363 | 12345 | return true; |
252b5132 RH |
12346 | } |
12347 | ||
97601363 | 12348 | static bool |
39fb3698 VM |
12349 | OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED, |
12350 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 | 12351 | { |
95ff6718 JB |
12352 | int add, res; |
12353 | char scratch[8]; | |
12354 | ||
161a04f6 | 12355 | USED_REX (REX_R); |
39fb3698 | 12356 | if (ins->rex & REX_R) |
52b15da3 | 12357 | add = 8; |
9b60702d L |
12358 | else |
12359 | add = 0; | |
95ff6718 JB |
12360 | res = snprintf (scratch, ARRAY_SIZE (scratch), |
12361 | ins->intel_syntax ? "dr%d" : "%%db%d", | |
12362 | ins->modrm.reg + add); | |
12363 | if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) | |
12364 | abort (); | |
12365 | oappend (ins, scratch); | |
97601363 | 12366 | return true; |
252b5132 RH |
12367 | } |
12368 | ||
97601363 | 12369 | static bool |
39fb3698 VM |
12370 | OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED, |
12371 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 | 12372 | { |
95ff6718 JB |
12373 | int res; |
12374 | char scratch[8]; | |
12375 | ||
12376 | res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg); | |
12377 | if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch)) | |
12378 | abort (); | |
12379 | oappend_register (ins, scratch); | |
97601363 | 12380 | return true; |
252b5132 RH |
12381 | } |
12382 | ||
97601363 | 12383 | static bool |
39fb3698 VM |
12384 | OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
12385 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 | 12386 | { |
39fb3698 | 12387 | int reg = ins->modrm.reg; |
2d9e0890 | 12388 | const char (*names)[8]; |
b9733481 | 12389 | |
39fb3698 VM |
12390 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
12391 | if (ins->prefixes & PREFIX_DATA) | |
20f0a1fc | 12392 | { |
e564475a | 12393 | names = att_names_xmm; |
161a04f6 | 12394 | USED_REX (REX_R); |
39fb3698 | 12395 | if (ins->rex & REX_R) |
b9733481 | 12396 | reg += 8; |
20f0a1fc | 12397 | } |
041bd2e0 | 12398 | else |
e564475a | 12399 | names = att_names_mm; |
2c3b9a91 | 12400 | oappend_register (ins, names[reg]); |
97601363 | 12401 | return true; |
252b5132 RH |
12402 | } |
12403 | ||
c608c12e | 12404 | static void |
39fb3698 | 12405 | print_vector_reg (instr_info *ins, unsigned int reg, int bytemode) |
c608c12e | 12406 | { |
2d9e0890 | 12407 | const char (*names)[8]; |
b9733481 | 12408 | |
fd1fd061 | 12409 | if (bytemode == xmmq_mode |
0cc78721 | 12410 | || bytemode == evex_half_bcst_xmmqh_mode |
fd1fd061 | 12411 | || bytemode == evex_half_bcst_xmmq_mode) |
43234a1e | 12412 | { |
39fb3698 | 12413 | switch (ins->vex.length) |
43234a1e | 12414 | { |
b5c37946 | 12415 | case 0: |
43234a1e L |
12416 | case 128: |
12417 | case 256: | |
e564475a | 12418 | names = att_names_xmm; |
43234a1e L |
12419 | break; |
12420 | case 512: | |
e564475a | 12421 | names = att_names_ymm; |
811f61d4 | 12422 | ins->evex_used |= EVEX_len_used; |
43234a1e L |
12423 | break; |
12424 | default: | |
12425 | abort (); | |
12426 | } | |
12427 | } | |
fd1fd061 | 12428 | else if (bytemode == ymm_mode) |
e564475a | 12429 | names = att_names_ymm; |
260cd341 LC |
12430 | else if (bytemode == tmm_mode) |
12431 | { | |
260cd341 LC |
12432 | if (reg >= 8) |
12433 | { | |
39fb3698 | 12434 | oappend (ins, "(bad)"); |
260cd341 LC |
12435 | return; |
12436 | } | |
e564475a | 12437 | names = att_names_tmm; |
260cd341 | 12438 | } |
39fb3698 | 12439 | else if (ins->need_vex |
fd1fd061 | 12440 | && bytemode != xmm_mode |
b0556968 JB |
12441 | && bytemode != scalar_mode |
12442 | && bytemode != xmmdw_mode | |
12443 | && bytemode != xmmqd_mode | |
0cc78721 CL |
12444 | && bytemode != evex_half_bcst_xmmqdh_mode |
12445 | && bytemode != w_swap_mode | |
c1d66d5f JB |
12446 | && bytemode != b_mode |
12447 | && bytemode != w_mode | |
12448 | && bytemode != d_mode | |
eb34d29b | 12449 | && bytemode != q_mode) |
fd1fd061 | 12450 | { |
811f61d4 | 12451 | ins->evex_used |= EVEX_len_used; |
39fb3698 | 12452 | switch (ins->vex.length) |
fd1fd061 JB |
12453 | { |
12454 | case 128: | |
e564475a | 12455 | names = att_names_xmm; |
fd1fd061 JB |
12456 | break; |
12457 | case 256: | |
39fb3698 | 12458 | if (ins->vex.w |
fd1fd061 | 12459 | || bytemode != vex_vsib_q_w_dq_mode) |
e564475a | 12460 | names = att_names_ymm; |
fd1fd061 | 12461 | else |
e564475a | 12462 | names = att_names_xmm; |
fd1fd061 JB |
12463 | break; |
12464 | case 512: | |
39fb3698 | 12465 | if (ins->vex.w |
fd1fd061 | 12466 | || bytemode != vex_vsib_q_w_dq_mode) |
e564475a | 12467 | names = att_names_zmm; |
fd1fd061 | 12468 | else |
e564475a | 12469 | names = att_names_ymm; |
fd1fd061 JB |
12470 | break; |
12471 | default: | |
12472 | abort (); | |
12473 | } | |
12474 | } | |
c0f3af97 | 12475 | else |
e564475a | 12476 | names = att_names_xmm; |
2c3b9a91 | 12477 | oappend_register (ins, names[reg]); |
c608c12e AM |
12478 | } |
12479 | ||
97601363 | 12480 | static bool |
39fb3698 | 12481 | OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
b0556968 | 12482 | { |
39fb3698 | 12483 | unsigned int reg = ins->modrm.reg; |
b0556968 JB |
12484 | |
12485 | USED_REX (REX_R); | |
39fb3698 | 12486 | if (ins->rex & REX_R) |
b0556968 | 12487 | reg += 8; |
39fb3698 | 12488 | if (ins->vex.evex) |
b0556968 | 12489 | { |
39fb3698 | 12490 | if (!ins->vex.r) |
b0556968 JB |
12491 | reg += 16; |
12492 | } | |
12493 | ||
12494 | if (bytemode == tmm_mode) | |
39fb3698 | 12495 | ins->modrm.reg = reg; |
2c02075a | 12496 | else if (bytemode == scalar_mode) |
ab31da6a | 12497 | ins->vex.no_broadcast = true; |
b0556968 | 12498 | |
39fb3698 | 12499 | print_vector_reg (ins, reg, bytemode); |
97601363 | 12500 | return true; |
b0556968 JB |
12501 | } |
12502 | ||
97601363 | 12503 | static bool |
39fb3698 | 12504 | OP_EM (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 12505 | { |
b9733481 | 12506 | int reg; |
2d9e0890 | 12507 | const char (*names)[8]; |
b9733481 | 12508 | |
39fb3698 | 12509 | if (ins->modrm.mod != 3) |
252b5132 | 12510 | { |
39fb3698 | 12511 | if (ins->intel_syntax |
b6169b20 | 12512 | && (bytemode == v_mode || bytemode == v_swap_mode)) |
9306ca4a | 12513 | { |
39fb3698 VM |
12514 | bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode; |
12515 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
6c067bbb | 12516 | } |
97601363 | 12517 | return OP_E (ins, bytemode, sizeflag); |
252b5132 RH |
12518 | } |
12519 | ||
b6169b20 | 12520 | if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode) |
39fb3698 | 12521 | swap_operand (ins); |
b6169b20 | 12522 | |
6608db57 | 12523 | /* Skip mod/rm byte. */ |
4bba6815 | 12524 | MODRM_CHECK; |
39fb3698 VM |
12525 | ins->codep++; |
12526 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
12527 | reg = ins->modrm.rm; | |
12528 | if (ins->prefixes & PREFIX_DATA) | |
20f0a1fc | 12529 | { |
e564475a | 12530 | names = att_names_xmm; |
161a04f6 | 12531 | USED_REX (REX_B); |
39fb3698 | 12532 | if (ins->rex & REX_B) |
b9733481 | 12533 | reg += 8; |
20f0a1fc | 12534 | } |
041bd2e0 | 12535 | else |
e564475a | 12536 | names = att_names_mm; |
2c3b9a91 | 12537 | oappend_register (ins, names[reg]); |
97601363 | 12538 | return true; |
252b5132 RH |
12539 | } |
12540 | ||
246c51aa L |
12541 | /* cvt* are the only instructions in sse2 which have |
12542 | both SSE and MMX operands and also have 0x66 prefix | |
12543 | in their opcode. 0x66 was originally used to differentiate | |
12544 | between SSE and MMX instruction(operands). So we have to handle the | |
4d9567e0 | 12545 | cvt* separately using OP_EMC and OP_MXC */ |
97601363 | 12546 | static bool |
39fb3698 | 12547 | OP_EMC (instr_info *ins, int bytemode, int sizeflag) |
4d9567e0 | 12548 | { |
39fb3698 | 12549 | if (ins->modrm.mod != 3) |
4d9567e0 | 12550 | { |
39fb3698 | 12551 | if (ins->intel_syntax && bytemode == v_mode) |
4d9567e0 | 12552 | { |
39fb3698 VM |
12553 | bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode; |
12554 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
6c067bbb | 12555 | } |
97601363 | 12556 | return OP_E (ins, bytemode, sizeflag); |
4d9567e0 | 12557 | } |
246c51aa | 12558 | |
4d9567e0 MM |
12559 | /* Skip mod/rm byte. */ |
12560 | MODRM_CHECK; | |
39fb3698 VM |
12561 | ins->codep++; |
12562 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
2c3b9a91 | 12563 | oappend_register (ins, att_names_mm[ins->modrm.rm]); |
97601363 | 12564 | return true; |
4d9567e0 MM |
12565 | } |
12566 | ||
97601363 | 12567 | static bool |
39fb3698 VM |
12568 | OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
12569 | int sizeflag ATTRIBUTE_UNUSED) | |
4d9567e0 | 12570 | { |
39fb3698 | 12571 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); |
2c3b9a91 | 12572 | oappend_register (ins, att_names_mm[ins->modrm.reg]); |
97601363 | 12573 | return true; |
4d9567e0 MM |
12574 | } |
12575 | ||
97601363 | 12576 | static bool |
39fb3698 | 12577 | OP_EX (instr_info *ins, int bytemode, int sizeflag) |
c608c12e | 12578 | { |
b9733481 | 12579 | int reg; |
d6f574e0 L |
12580 | |
12581 | /* Skip mod/rm byte. */ | |
12582 | MODRM_CHECK; | |
39fb3698 | 12583 | ins->codep++; |
d6f574e0 | 12584 | |
eb34d29b | 12585 | if (bytemode == dq_mode) |
39fb3698 | 12586 | bytemode = ins->vex.w ? q_mode : d_mode; |
eb34d29b | 12587 | |
39fb3698 | 12588 | if (ins->modrm.mod != 3) |
97601363 | 12589 | return OP_E_memory (ins, bytemode, sizeflag); |
d6f574e0 | 12590 | |
39fb3698 | 12591 | reg = ins->modrm.rm; |
161a04f6 | 12592 | USED_REX (REX_B); |
39fb3698 | 12593 | if (ins->rex & REX_B) |
b9733481 | 12594 | reg += 8; |
39fb3698 | 12595 | if (ins->vex.evex) |
43234a1e L |
12596 | { |
12597 | USED_REX (REX_X); | |
39fb3698 | 12598 | if ((ins->rex & REX_X)) |
43234a1e L |
12599 | reg += 16; |
12600 | } | |
c608c12e | 12601 | |
b6169b20 | 12602 | if ((sizeflag & SUFFIX_ALWAYS) |
fa99fab2 | 12603 | && (bytemode == x_swap_mode |
0cc78721 | 12604 | || bytemode == w_swap_mode |
fa99fab2 | 12605 | || bytemode == d_swap_mode |
41f5efc6 | 12606 | || bytemode == q_swap_mode)) |
39fb3698 | 12607 | swap_operand (ins); |
b6169b20 | 12608 | |
b0556968 | 12609 | if (bytemode == tmm_mode) |
39fb3698 | 12610 | ins->modrm.rm = reg; |
b0556968 | 12611 | |
39fb3698 | 12612 | print_vector_reg (ins, reg, bytemode); |
97601363 | 12613 | return true; |
c608c12e AM |
12614 | } |
12615 | ||
97601363 | 12616 | static bool |
b5c37946 | 12617 | OP_R (instr_info *ins, int bytemode, int sizeflag) |
252b5132 | 12618 | { |
b5c37946 SJ |
12619 | if (ins->modrm.mod != 3) |
12620 | return BadOp (ins); | |
2ad525c2 | 12621 | |
b5c37946 SJ |
12622 | switch (bytemode) |
12623 | { | |
12624 | case d_mode: | |
12625 | case dq_mode: | |
12626 | case mask_mode: | |
12627 | return OP_E (ins, bytemode, sizeflag); | |
12628 | case q_mode: | |
12629 | return OP_EM (ins, x_mode, sizeflag); | |
12630 | case xmm_mode: | |
12631 | if (ins->vex.length <= 128) | |
12632 | break; | |
12633 | return BadOp (ins); | |
12634 | } | |
12635 | ||
12636 | return OP_EX (ins, bytemode, sizeflag); | |
992aaec9 AM |
12637 | } |
12638 | ||
97601363 | 12639 | static bool |
39fb3698 | 12640 | OP_M (instr_info *ins, int bytemode, int sizeflag) |
cc0ec051 | 12641 | { |
b5c37946 SJ |
12642 | /* Skip mod/rm byte. */ |
12643 | MODRM_CHECK; | |
12644 | ins->codep++; | |
12645 | ||
39fb3698 | 12646 | if (ins->modrm.mod == 3) |
75413a22 | 12647 | /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */ |
97601363 | 12648 | return BadOp (ins); |
b5c37946 SJ |
12649 | |
12650 | if (bytemode == x_mode) | |
12651 | ins->vex.no_broadcast = true; | |
12652 | ||
12653 | return OP_E_memory (ins, bytemode, sizeflag); | |
cc0ec051 AM |
12654 | } |
12655 | ||
97601363 | 12656 | static bool |
39fb3698 | 12657 | OP_0f07 (instr_info *ins, int bytemode, int sizeflag) |
cc0ec051 | 12658 | { |
39fb3698 | 12659 | if (ins->modrm.mod != 3 || ins->modrm.rm != 0) |
97601363 JB |
12660 | return BadOp (ins); |
12661 | return OP_E (ins, bytemode, sizeflag); | |
cc0ec051 AM |
12662 | } |
12663 | ||
46e883c5 | 12664 | /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in |
246c51aa | 12665 | 32bit mode and "xchg %rax,%rax" in 64bit mode. */ |
46e883c5 | 12666 | |
97601363 | 12667 | static bool |
2f399d99 | 12668 | NOP_Fixup (instr_info *ins, int opnd, int sizeflag) |
cc0ec051 | 12669 | { |
2f399d99 | 12670 | if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0) |
97601363 JB |
12671 | { |
12672 | ins->mnemonicendp = stpcpy (ins->obuf, "nop"); | |
12673 | return true; | |
12674 | } | |
12675 | if (opnd == 0) | |
12676 | return OP_REG (ins, eAX_reg, sizeflag); | |
12677 | return OP_IMREG (ins, eAX_reg, sizeflag); | |
cc0ec051 AM |
12678 | } |
12679 | ||
84037f8c | 12680 | static const char *const Suffix3DNow[] = { |
252b5132 RH |
12681 | /* 00 */ NULL, NULL, NULL, NULL, |
12682 | /* 04 */ NULL, NULL, NULL, NULL, | |
12683 | /* 08 */ NULL, NULL, NULL, NULL, | |
9e525108 | 12684 | /* 0C */ "pi2fw", "pi2fd", NULL, NULL, |
252b5132 RH |
12685 | /* 10 */ NULL, NULL, NULL, NULL, |
12686 | /* 14 */ NULL, NULL, NULL, NULL, | |
12687 | /* 18 */ NULL, NULL, NULL, NULL, | |
9e525108 | 12688 | /* 1C */ "pf2iw", "pf2id", NULL, NULL, |
252b5132 RH |
12689 | /* 20 */ NULL, NULL, NULL, NULL, |
12690 | /* 24 */ NULL, NULL, NULL, NULL, | |
12691 | /* 28 */ NULL, NULL, NULL, NULL, | |
12692 | /* 2C */ NULL, NULL, NULL, NULL, | |
12693 | /* 30 */ NULL, NULL, NULL, NULL, | |
12694 | /* 34 */ NULL, NULL, NULL, NULL, | |
12695 | /* 38 */ NULL, NULL, NULL, NULL, | |
12696 | /* 3C */ NULL, NULL, NULL, NULL, | |
12697 | /* 40 */ NULL, NULL, NULL, NULL, | |
12698 | /* 44 */ NULL, NULL, NULL, NULL, | |
12699 | /* 48 */ NULL, NULL, NULL, NULL, | |
12700 | /* 4C */ NULL, NULL, NULL, NULL, | |
12701 | /* 50 */ NULL, NULL, NULL, NULL, | |
12702 | /* 54 */ NULL, NULL, NULL, NULL, | |
12703 | /* 58 */ NULL, NULL, NULL, NULL, | |
12704 | /* 5C */ NULL, NULL, NULL, NULL, | |
12705 | /* 60 */ NULL, NULL, NULL, NULL, | |
12706 | /* 64 */ NULL, NULL, NULL, NULL, | |
12707 | /* 68 */ NULL, NULL, NULL, NULL, | |
12708 | /* 6C */ NULL, NULL, NULL, NULL, | |
12709 | /* 70 */ NULL, NULL, NULL, NULL, | |
12710 | /* 74 */ NULL, NULL, NULL, NULL, | |
12711 | /* 78 */ NULL, NULL, NULL, NULL, | |
12712 | /* 7C */ NULL, NULL, NULL, NULL, | |
12713 | /* 80 */ NULL, NULL, NULL, NULL, | |
12714 | /* 84 */ NULL, NULL, NULL, NULL, | |
9e525108 AM |
12715 | /* 88 */ NULL, NULL, "pfnacc", NULL, |
12716 | /* 8C */ NULL, NULL, "pfpnacc", NULL, | |
252b5132 RH |
12717 | /* 90 */ "pfcmpge", NULL, NULL, NULL, |
12718 | /* 94 */ "pfmin", NULL, "pfrcp", "pfrsqrt", | |
12719 | /* 98 */ NULL, NULL, "pfsub", NULL, | |
12720 | /* 9C */ NULL, NULL, "pfadd", NULL, | |
12721 | /* A0 */ "pfcmpgt", NULL, NULL, NULL, | |
12722 | /* A4 */ "pfmax", NULL, "pfrcpit1", "pfrsqit1", | |
12723 | /* A8 */ NULL, NULL, "pfsubr", NULL, | |
12724 | /* AC */ NULL, NULL, "pfacc", NULL, | |
12725 | /* B0 */ "pfcmpeq", NULL, NULL, NULL, | |
9beff690 | 12726 | /* B4 */ "pfmul", NULL, "pfrcpit2", "pmulhrw", |
9e525108 | 12727 | /* B8 */ NULL, NULL, NULL, "pswapd", |
252b5132 RH |
12728 | /* BC */ NULL, NULL, NULL, "pavgusb", |
12729 | /* C0 */ NULL, NULL, NULL, NULL, | |
12730 | /* C4 */ NULL, NULL, NULL, NULL, | |
12731 | /* C8 */ NULL, NULL, NULL, NULL, | |
12732 | /* CC */ NULL, NULL, NULL, NULL, | |
12733 | /* D0 */ NULL, NULL, NULL, NULL, | |
12734 | /* D4 */ NULL, NULL, NULL, NULL, | |
12735 | /* D8 */ NULL, NULL, NULL, NULL, | |
12736 | /* DC */ NULL, NULL, NULL, NULL, | |
12737 | /* E0 */ NULL, NULL, NULL, NULL, | |
12738 | /* E4 */ NULL, NULL, NULL, NULL, | |
12739 | /* E8 */ NULL, NULL, NULL, NULL, | |
12740 | /* EC */ NULL, NULL, NULL, NULL, | |
12741 | /* F0 */ NULL, NULL, NULL, NULL, | |
12742 | /* F4 */ NULL, NULL, NULL, NULL, | |
12743 | /* F8 */ NULL, NULL, NULL, NULL, | |
12744 | /* FC */ NULL, NULL, NULL, NULL, | |
12745 | }; | |
12746 | ||
97601363 | 12747 | static bool |
39fb3698 VM |
12748 | OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
12749 | int sizeflag ATTRIBUTE_UNUSED) | |
252b5132 RH |
12750 | { |
12751 | const char *mnemonic; | |
12752 | ||
97601363 JB |
12753 | if (!fetch_code (ins->info, ins->codep + 1)) |
12754 | return false; | |
252b5132 RH |
12755 | /* AMD 3DNow! instructions are specified by an opcode suffix in the |
12756 | place where an 8-bit immediate would normally go. ie. the last | |
12757 | byte of the instruction. */ | |
39fb3698 | 12758 | ins->obufp = ins->mnemonicendp; |
a4aa034a | 12759 | mnemonic = Suffix3DNow[*ins->codep++]; |
252b5132 | 12760 | if (mnemonic) |
2c3b9a91 | 12761 | ins->obufp = stpcpy (ins->obufp, mnemonic); |
252b5132 RH |
12762 | else |
12763 | { | |
39fb3698 | 12764 | /* Since a variable sized ins->modrm/ins->sib chunk is between the start |
252b5132 | 12765 | of the opcode (0x0f0f) and the opcode suffix, we need to do |
39fb3698 | 12766 | all the ins->modrm processing first, and don't know until now that |
252b5132 | 12767 | we have a bad opcode. This necessitates some cleaning up. */ |
39fb3698 VM |
12768 | ins->op_out[0][0] = '\0'; |
12769 | ins->op_out[1][0] = '\0'; | |
12770 | BadOp (ins); | |
252b5132 | 12771 | } |
39fb3698 | 12772 | ins->mnemonicendp = ins->obufp; |
97601363 | 12773 | return true; |
252b5132 | 12774 | } |
c608c12e | 12775 | |
c4de7606 | 12776 | static const struct op simd_cmp_op[] = |
ea397f5b L |
12777 | { |
12778 | { STRING_COMMA_LEN ("eq") }, | |
12779 | { STRING_COMMA_LEN ("lt") }, | |
12780 | { STRING_COMMA_LEN ("le") }, | |
12781 | { STRING_COMMA_LEN ("unord") }, | |
12782 | { STRING_COMMA_LEN ("neq") }, | |
12783 | { STRING_COMMA_LEN ("nlt") }, | |
12784 | { STRING_COMMA_LEN ("nle") }, | |
12785 | { STRING_COMMA_LEN ("ord") } | |
c608c12e AM |
12786 | }; |
12787 | ||
c4de7606 JB |
12788 | static const struct op vex_cmp_op[] = |
12789 | { | |
12790 | { STRING_COMMA_LEN ("eq_uq") }, | |
12791 | { STRING_COMMA_LEN ("nge") }, | |
12792 | { STRING_COMMA_LEN ("ngt") }, | |
12793 | { STRING_COMMA_LEN ("false") }, | |
12794 | { STRING_COMMA_LEN ("neq_oq") }, | |
12795 | { STRING_COMMA_LEN ("ge") }, | |
12796 | { STRING_COMMA_LEN ("gt") }, | |
12797 | { STRING_COMMA_LEN ("true") }, | |
12798 | { STRING_COMMA_LEN ("eq_os") }, | |
12799 | { STRING_COMMA_LEN ("lt_oq") }, | |
12800 | { STRING_COMMA_LEN ("le_oq") }, | |
12801 | { STRING_COMMA_LEN ("unord_s") }, | |
12802 | { STRING_COMMA_LEN ("neq_us") }, | |
12803 | { STRING_COMMA_LEN ("nlt_uq") }, | |
12804 | { STRING_COMMA_LEN ("nle_uq") }, | |
12805 | { STRING_COMMA_LEN ("ord_s") }, | |
12806 | { STRING_COMMA_LEN ("eq_us") }, | |
12807 | { STRING_COMMA_LEN ("nge_uq") }, | |
12808 | { STRING_COMMA_LEN ("ngt_uq") }, | |
12809 | { STRING_COMMA_LEN ("false_os") }, | |
12810 | { STRING_COMMA_LEN ("neq_os") }, | |
12811 | { STRING_COMMA_LEN ("ge_oq") }, | |
12812 | { STRING_COMMA_LEN ("gt_oq") }, | |
12813 | { STRING_COMMA_LEN ("true_us") }, | |
12814 | }; | |
12815 | ||
97601363 | 12816 | static bool |
39fb3698 VM |
12817 | CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
12818 | int sizeflag ATTRIBUTE_UNUSED) | |
c608c12e AM |
12819 | { |
12820 | unsigned int cmp_type; | |
12821 | ||
97601363 JB |
12822 | if (!fetch_code (ins->info, ins->codep + 1)) |
12823 | return false; | |
a4aa034a | 12824 | cmp_type = *ins->codep++; |
c0f3af97 | 12825 | if (cmp_type < ARRAY_SIZE (simd_cmp_op)) |
c608c12e | 12826 | { |
39fb3698 VM |
12827 | char suffix[3]; |
12828 | char *p = ins->mnemonicendp - 2; | |
ad19981d L |
12829 | suffix[0] = p[0]; |
12830 | suffix[1] = p[1]; | |
12831 | suffix[2] = '\0'; | |
ea397f5b | 12832 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); |
39fb3698 | 12833 | ins->mnemonicendp += simd_cmp_op[cmp_type].len; |
c608c12e | 12834 | } |
39fb3698 | 12835 | else if (ins->need_vex |
c4de7606 JB |
12836 | && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op)) |
12837 | { | |
39fb3698 VM |
12838 | char suffix[3]; |
12839 | char *p = ins->mnemonicendp - 2; | |
c4de7606 JB |
12840 | suffix[0] = p[0]; |
12841 | suffix[1] = p[1]; | |
12842 | suffix[2] = '\0'; | |
12843 | cmp_type -= ARRAY_SIZE (simd_cmp_op); | |
12844 | sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix); | |
39fb3698 | 12845 | ins->mnemonicendp += vex_cmp_op[cmp_type].len; |
c4de7606 | 12846 | } |
c608c12e AM |
12847 | else |
12848 | { | |
ad19981d | 12849 | /* We have a reserved extension byte. Output it directly. */ |
95ff6718 | 12850 | oappend_immediate (ins, cmp_type); |
c608c12e | 12851 | } |
97601363 | 12852 | return true; |
c608c12e AM |
12853 | } |
12854 | ||
97601363 | 12855 | static bool |
39fb3698 | 12856 | OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
9916071f | 12857 | { |
7abb8d81 | 12858 | /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx */ |
39fb3698 | 12859 | if (!ins->intel_syntax) |
b844680a | 12860 | { |
e564475a JB |
12861 | strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax); |
12862 | strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax); | |
7abb8d81 | 12863 | if (bytemode == eBX_reg) |
e564475a | 12864 | strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax); |
ab31da6a | 12865 | ins->two_source_ops = true; |
b844680a L |
12866 | } |
12867 | /* Skip mod/rm byte. */ | |
12868 | MODRM_CHECK; | |
39fb3698 | 12869 | ins->codep++; |
97601363 | 12870 | return true; |
b844680a L |
12871 | } |
12872 | ||
97601363 | 12873 | static bool |
39fb3698 | 12874 | OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
b844680a | 12875 | int sizeflag ATTRIBUTE_UNUSED) |
ca164297 | 12876 | { |
081e283f | 12877 | /* monitor %{e,r,}ax,%ecx,%edx" */ |
39fb3698 | 12878 | if (!ins->intel_syntax) |
ca164297 | 12879 | { |
2d9e0890 JB |
12880 | const char (*names)[8] = (ins->address_mode == mode_64bit |
12881 | ? att_names64 : att_names32); | |
1d9f512f | 12882 | |
39fb3698 | 12883 | if (ins->prefixes & PREFIX_ADDR) |
ca164297 | 12884 | { |
b844680a | 12885 | /* Remove "addr16/addr32". */ |
39fb3698 VM |
12886 | ins->all_prefixes[ins->last_addr_prefix] = 0; |
12887 | names = (ins->address_mode != mode_32bit | |
e564475a | 12888 | ? att_names32 : att_names16); |
39fb3698 | 12889 | ins->used_prefixes |= PREFIX_ADDR; |
ca164297 | 12890 | } |
39fb3698 | 12891 | else if (ins->address_mode == mode_16bit) |
e564475a JB |
12892 | names = att_names16; |
12893 | strcpy (ins->op_out[0], names[0] + ins->intel_syntax); | |
12894 | strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax); | |
12895 | strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax); | |
ab31da6a | 12896 | ins->two_source_ops = true; |
ca164297 | 12897 | } |
b844680a L |
12898 | /* Skip mod/rm byte. */ |
12899 | MODRM_CHECK; | |
39fb3698 | 12900 | ins->codep++; |
97601363 | 12901 | return true; |
2da11e11 | 12902 | } |
4cc91dba | 12903 | |
97601363 | 12904 | static bool |
39fb3698 | 12905 | REP_Fixup (instr_info *ins, int bytemode, int sizeflag) |
35c52694 L |
12906 | { |
12907 | /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs, | |
12908 | lods and stos. */ | |
39fb3698 VM |
12909 | if (ins->prefixes & PREFIX_REPZ) |
12910 | ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX; | |
35c52694 L |
12911 | |
12912 | switch (bytemode) | |
12913 | { | |
12914 | case al_reg: | |
12915 | case eAX_reg: | |
12916 | case indir_dx_reg: | |
97601363 | 12917 | return OP_IMREG (ins, bytemode, sizeflag); |
35c52694 | 12918 | case eDI_reg: |
97601363 | 12919 | return OP_ESreg (ins, bytemode, sizeflag); |
35c52694 | 12920 | case eSI_reg: |
97601363 | 12921 | return OP_DSreg (ins, bytemode, sizeflag); |
35c52694 L |
12922 | default: |
12923 | abort (); | |
12924 | break; | |
12925 | } | |
97601363 | 12926 | return true; |
35c52694 | 12927 | } |
f5804c90 | 12928 | |
97601363 | 12929 | static bool |
39fb3698 VM |
12930 | SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
12931 | int sizeflag ATTRIBUTE_UNUSED) | |
d835a58b | 12932 | { |
39fb3698 | 12933 | if (ins->isa64 != amd64) |
97601363 | 12934 | return true; |
d835a58b | 12935 | |
39fb3698 VM |
12936 | ins->obufp = ins->obuf; |
12937 | BadOp (ins); | |
12938 | ins->mnemonicendp = ins->obufp; | |
12939 | ++ins->codep; | |
97601363 | 12940 | return true; |
d835a58b JB |
12941 | } |
12942 | ||
7e8b059b L |
12943 | /* For BND-prefixed instructions 0xF2 prefix should be displayed as |
12944 | "bnd". */ | |
12945 | ||
97601363 | 12946 | static bool |
39fb3698 VM |
12947 | BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
12948 | int sizeflag ATTRIBUTE_UNUSED) | |
7e8b059b | 12949 | { |
39fb3698 VM |
12950 | if (ins->prefixes & PREFIX_REPNZ) |
12951 | ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX; | |
97601363 | 12952 | return true; |
7e8b059b L |
12953 | } |
12954 | ||
04ef582a L |
12955 | /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as |
12956 | "notrack". */ | |
12957 | ||
97601363 | 12958 | static bool |
39fb3698 | 12959 | NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
04ef582a L |
12960 | int sizeflag ATTRIBUTE_UNUSED) |
12961 | { | |
0fa0fc85 BP |
12962 | /* Since active_seg_prefix is not set in 64-bit mode, check whether |
12963 | we've seen a PREFIX_DS. */ | |
39fb3698 VM |
12964 | if ((ins->prefixes & PREFIX_DS) != 0 |
12965 | && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0)) | |
04ef582a | 12966 | { |
4e9ac44a | 12967 | /* NOTRACK prefix is only valid on indirect branch instructions. |
9fef80d6 | 12968 | NB: DATA prefix is unsupported for Intel64. */ |
39fb3698 VM |
12969 | ins->active_seg_prefix = 0; |
12970 | ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX; | |
04ef582a | 12971 | } |
97601363 | 12972 | return true; |
04ef582a L |
12973 | } |
12974 | ||
39fb3698 | 12975 | /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as |
42164a71 L |
12976 | "xacquire"/"xrelease" for memory operand if there is a LOCK prefix. |
12977 | */ | |
12978 | ||
97601363 | 12979 | static bool |
39fb3698 | 12980 | HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag) |
42164a71 | 12981 | { |
39fb3698 VM |
12982 | if (ins->modrm.mod != 3 |
12983 | && (ins->prefixes & PREFIX_LOCK) != 0) | |
42164a71 | 12984 | { |
39fb3698 VM |
12985 | if (ins->prefixes & PREFIX_REPZ) |
12986 | ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; | |
12987 | if (ins->prefixes & PREFIX_REPNZ) | |
12988 | ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; | |
42164a71 L |
12989 | } |
12990 | ||
97601363 | 12991 | return OP_E (ins, bytemode, sizeflag); |
42164a71 L |
12992 | } |
12993 | ||
39fb3698 | 12994 | /* Similar to OP_E. But the 0xf2/0xf3 ins->prefixes should be displayed as |
42164a71 L |
12995 | "xacquire"/"xrelease" for memory operand. No check for LOCK prefix. |
12996 | */ | |
12997 | ||
97601363 | 12998 | static bool |
39fb3698 | 12999 | HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag) |
42164a71 | 13000 | { |
39fb3698 | 13001 | if (ins->modrm.mod != 3) |
42164a71 | 13002 | { |
39fb3698 VM |
13003 | if (ins->prefixes & PREFIX_REPZ) |
13004 | ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; | |
13005 | if (ins->prefixes & PREFIX_REPNZ) | |
13006 | ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; | |
42164a71 L |
13007 | } |
13008 | ||
97601363 | 13009 | return OP_E (ins, bytemode, sizeflag); |
42164a71 L |
13010 | } |
13011 | ||
13012 | /* Similar to OP_E. But the 0xf3 prefixes should be displayed as | |
13013 | "xrelease" for memory operand. No check for LOCK prefix. */ | |
13014 | ||
97601363 | 13015 | static bool |
39fb3698 | 13016 | HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag) |
42164a71 | 13017 | { |
39fb3698 VM |
13018 | if (ins->modrm.mod != 3 |
13019 | && ins->last_repz_prefix > ins->last_repnz_prefix | |
13020 | && (ins->prefixes & PREFIX_REPZ) != 0) | |
13021 | ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; | |
42164a71 | 13022 | |
97601363 | 13023 | return OP_E (ins, bytemode, sizeflag); |
42164a71 L |
13024 | } |
13025 | ||
97601363 | 13026 | static bool |
39fb3698 | 13027 | CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag) |
f5804c90 | 13028 | { |
161a04f6 | 13029 | USED_REX (REX_W); |
39fb3698 | 13030 | if (ins->rex & REX_W) |
f5804c90 L |
13031 | { |
13032 | /* Change cmpxchg8b to cmpxchg16b. */ | |
39fb3698 VM |
13033 | char *p = ins->mnemonicendp - 2; |
13034 | ins->mnemonicendp = stpcpy (p, "16b"); | |
fb9c77c7 | 13035 | bytemode = o_mode; |
f5804c90 | 13036 | } |
39fb3698 | 13037 | else if ((ins->prefixes & PREFIX_LOCK) != 0) |
42164a71 | 13038 | { |
39fb3698 VM |
13039 | if (ins->prefixes & PREFIX_REPZ) |
13040 | ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX; | |
13041 | if (ins->prefixes & PREFIX_REPNZ) | |
13042 | ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX; | |
42164a71 L |
13043 | } |
13044 | ||
97601363 | 13045 | return OP_M (ins, bytemode, sizeflag); |
f5804c90 | 13046 | } |
42903f7f | 13047 | |
97601363 | 13048 | static bool |
39fb3698 | 13049 | XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED) |
42903f7f | 13050 | { |
2d9e0890 | 13051 | const char (*names)[8] = att_names_xmm; |
b9733481 | 13052 | |
39fb3698 | 13053 | if (ins->need_vex) |
c0f3af97 | 13054 | { |
39fb3698 | 13055 | switch (ins->vex.length) |
c0f3af97 L |
13056 | { |
13057 | case 128: | |
c0f3af97 L |
13058 | break; |
13059 | case 256: | |
e564475a | 13060 | names = att_names_ymm; |
c0f3af97 L |
13061 | break; |
13062 | default: | |
13063 | abort (); | |
13064 | } | |
13065 | } | |
2c3b9a91 | 13066 | oappend_register (ins, names[reg]); |
97601363 | 13067 | return true; |
42903f7f | 13068 | } |
381d071f | 13069 | |
97601363 | 13070 | static bool |
39fb3698 | 13071 | FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag) |
eacc9c89 L |
13072 | { |
13073 | /* Add proper suffix to "fxsave" and "fxrstor". */ | |
13074 | USED_REX (REX_W); | |
39fb3698 | 13075 | if (ins->rex & REX_W) |
eacc9c89 | 13076 | { |
39fb3698 | 13077 | char *p = ins->mnemonicendp; |
eacc9c89 L |
13078 | *p++ = '6'; |
13079 | *p++ = '4'; | |
13080 | *p = '\0'; | |
39fb3698 | 13081 | ins->mnemonicendp = p; |
eacc9c89 | 13082 | } |
97601363 | 13083 | return OP_M (ins, bytemode, sizeflag); |
15c7c1d8 JB |
13084 | } |
13085 | ||
c0f3af97 L |
13086 | /* Display the destination register operand for instructions with |
13087 | VEX. */ | |
13088 | ||
97601363 | 13089 | static bool |
39fb3698 | 13090 | OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c0f3af97 | 13091 | { |
596a02ff | 13092 | int reg, modrm_reg, sib_index = -1; |
2d9e0890 | 13093 | const char (*names)[8]; |
b9733481 | 13094 | |
39fb3698 | 13095 | if (!ins->need_vex) |
b5c37946 | 13096 | return true; |
c0f3af97 | 13097 | |
39fb3698 VM |
13098 | reg = ins->vex.register_specifier; |
13099 | ins->vex.register_specifier = 0; | |
13100 | if (ins->address_mode != mode_64bit) | |
54ca11a4 | 13101 | { |
39fb3698 | 13102 | if (ins->vex.evex && !ins->vex.v) |
54ca11a4 | 13103 | { |
39fb3698 | 13104 | oappend (ins, "(bad)"); |
97601363 | 13105 | return true; |
54ca11a4 JB |
13106 | } |
13107 | ||
13108 | reg &= 7; | |
13109 | } | |
39fb3698 | 13110 | else if (ins->vex.evex && !ins->vex.v) |
5f847646 | 13111 | reg += 16; |
43234a1e | 13112 | |
596a02ff | 13113 | switch (bytemode) |
539f890d | 13114 | { |
605228fc | 13115 | case scalar_mode: |
2c3b9a91 | 13116 | oappend_register (ins, att_names_xmm[reg]); |
97601363 | 13117 | return true; |
539f890d | 13118 | |
596a02ff JB |
13119 | case vex_vsib_d_w_dq_mode: |
13120 | case vex_vsib_q_w_dq_mode: | |
13121 | /* This must be the 3rd operand. */ | |
39fb3698 | 13122 | if (ins->obufp != ins->op_out[2]) |
596a02ff | 13123 | abort (); |
39fb3698 | 13124 | if (ins->vex.length == 128 |
596a02ff | 13125 | || (bytemode != vex_vsib_d_w_dq_mode |
39fb3698 | 13126 | && !ins->vex.w)) |
2c3b9a91 | 13127 | oappend_register (ins, att_names_xmm[reg]); |
596a02ff | 13128 | else |
2c3b9a91 | 13129 | oappend_register (ins, att_names_ymm[reg]); |
596a02ff JB |
13130 | |
13131 | /* All 3 XMM/YMM registers must be distinct. */ | |
39fb3698 VM |
13132 | modrm_reg = ins->modrm.reg; |
13133 | if (ins->rex & REX_R) | |
596a02ff JB |
13134 | modrm_reg += 8; |
13135 | ||
ce20459e | 13136 | if (ins->has_sib && ins->modrm.rm == 4) |
596a02ff | 13137 | { |
39fb3698 VM |
13138 | sib_index = ins->sib.index; |
13139 | if (ins->rex & REX_X) | |
596a02ff JB |
13140 | sib_index += 8; |
13141 | } | |
13142 | ||
13143 | if (reg == modrm_reg || reg == sib_index) | |
39fb3698 | 13144 | strcpy (ins->obufp, "/(bad)"); |
596a02ff | 13145 | if (modrm_reg == sib_index || modrm_reg == reg) |
39fb3698 | 13146 | strcat (ins->op_out[0], "/(bad)"); |
596a02ff | 13147 | if (sib_index == modrm_reg || sib_index == reg) |
39fb3698 | 13148 | strcat (ins->op_out[1], "/(bad)"); |
596a02ff | 13149 | |
97601363 | 13150 | return true; |
596a02ff JB |
13151 | |
13152 | case tmm_mode: | |
260cd341 LC |
13153 | /* All 3 TMM registers must be distinct. */ |
13154 | if (reg >= 8) | |
39fb3698 | 13155 | oappend (ins, "(bad)"); |
260cd341 LC |
13156 | else |
13157 | { | |
13158 | /* This must be the 3rd operand. */ | |
39fb3698 | 13159 | if (ins->obufp != ins->op_out[2]) |
260cd341 | 13160 | abort (); |
2c3b9a91 | 13161 | oappend_register (ins, att_names_tmm[reg]); |
39fb3698 VM |
13162 | if (reg == ins->modrm.reg || reg == ins->modrm.rm) |
13163 | strcpy (ins->obufp, "/(bad)"); | |
260cd341 LC |
13164 | } |
13165 | ||
39fb3698 VM |
13166 | if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg |
13167 | || ins->modrm.rm == reg) | |
260cd341 | 13168 | { |
39fb3698 VM |
13169 | if (ins->modrm.reg <= 8 |
13170 | && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg)) | |
13171 | strcat (ins->op_out[0], "/(bad)"); | |
13172 | if (ins->modrm.rm <= 8 | |
13173 | && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg)) | |
13174 | strcat (ins->op_out[1], "/(bad)"); | |
260cd341 LC |
13175 | } |
13176 | ||
97601363 | 13177 | return true; |
260cd341 LC |
13178 | } |
13179 | ||
39fb3698 | 13180 | switch (ins->vex.length) |
c0f3af97 L |
13181 | { |
13182 | case 128: | |
13183 | switch (bytemode) | |
13184 | { | |
605228fc | 13185 | case x_mode: |
e564475a | 13186 | names = att_names_xmm; |
811f61d4 | 13187 | ins->evex_used |= EVEX_len_used; |
cb21baef L |
13188 | break; |
13189 | case dq_mode: | |
39fb3698 | 13190 | if (ins->rex & REX_W) |
e564475a | 13191 | names = att_names64; |
cb21baef | 13192 | else |
e564475a | 13193 | names = att_names32; |
c0f3af97 | 13194 | break; |
1ba585e8 | 13195 | case mask_bd_mode: |
43234a1e | 13196 | case mask_mode: |
9889cbb1 L |
13197 | if (reg > 0x7) |
13198 | { | |
39fb3698 | 13199 | oappend (ins, "(bad)"); |
97601363 | 13200 | return true; |
9889cbb1 | 13201 | } |
e564475a | 13202 | names = att_names_mask; |
43234a1e | 13203 | break; |
c0f3af97 L |
13204 | default: |
13205 | abort (); | |
97601363 | 13206 | return true; |
c0f3af97 | 13207 | } |
c0f3af97 L |
13208 | break; |
13209 | case 256: | |
13210 | switch (bytemode) | |
13211 | { | |
605228fc | 13212 | case x_mode: |
e564475a | 13213 | names = att_names_ymm; |
811f61d4 | 13214 | ins->evex_used |= EVEX_len_used; |
6c30d220 | 13215 | break; |
1ba585e8 | 13216 | case mask_bd_mode: |
43234a1e | 13217 | case mask_mode: |
97601363 | 13218 | if (reg <= 0x7) |
9889cbb1 | 13219 | { |
97601363 JB |
13220 | names = att_names_mask; |
13221 | break; | |
9889cbb1 | 13222 | } |
97601363 | 13223 | /* Fall through. */ |
c0f3af97 | 13224 | default: |
a37a2806 | 13225 | /* See PR binutils/20893 for a reproducer. */ |
39fb3698 | 13226 | oappend (ins, "(bad)"); |
97601363 | 13227 | return true; |
c0f3af97 | 13228 | } |
c0f3af97 | 13229 | break; |
43234a1e | 13230 | case 512: |
e564475a | 13231 | names = att_names_zmm; |
811f61d4 | 13232 | ins->evex_used |= EVEX_len_used; |
43234a1e | 13233 | break; |
c0f3af97 L |
13234 | default: |
13235 | abort (); | |
13236 | break; | |
13237 | } | |
2c3b9a91 | 13238 | oappend_register (ins, names[reg]); |
97601363 | 13239 | return true; |
c0f3af97 L |
13240 | } |
13241 | ||
97601363 | 13242 | static bool |
39fb3698 | 13243 | OP_VexR (instr_info *ins, int bytemode, int sizeflag) |
41f5efc6 | 13244 | { |
39fb3698 | 13245 | if (ins->modrm.mod == 3) |
97601363 JB |
13246 | return OP_VEX (ins, bytemode, sizeflag); |
13247 | return true; | |
41f5efc6 JB |
13248 | } |
13249 | ||
97601363 | 13250 | static bool |
39fb3698 | 13251 | OP_VexW (instr_info *ins, int bytemode, int sizeflag) |
5dd85c99 | 13252 | { |
39fb3698 | 13253 | OP_VEX (ins, bytemode, sizeflag); |
5dd85c99 | 13254 | |
39fb3698 | 13255 | if (ins->vex.w) |
5f847646 | 13256 | { |
e6123d0c | 13257 | /* Swap 2nd and 3rd operands. */ |
32f06c69 JB |
13258 | char *tmp = ins->op_out[2]; |
13259 | ||
13260 | ins->op_out[2] = ins->op_out[1]; | |
13261 | ins->op_out[1] = tmp; | |
5f847646 | 13262 | } |
97601363 | 13263 | return true; |
5dd85c99 SP |
13264 | } |
13265 | ||
97601363 | 13266 | static bool |
39fb3698 | 13267 | OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
c0f3af97 L |
13268 | { |
13269 | int reg; | |
2d9e0890 | 13270 | const char (*names)[8] = att_names_xmm; |
b9733481 | 13271 | |
97601363 JB |
13272 | if (!fetch_code (ins->info, ins->codep + 1)) |
13273 | return false; | |
a4aa034a | 13274 | reg = *ins->codep++; |
c0f3af97 | 13275 | |
6384fd9e | 13276 | if (bytemode != x_mode && bytemode != scalar_mode) |
c0f3af97 L |
13277 | abort (); |
13278 | ||
c0f3af97 | 13279 | reg >>= 4; |
39fb3698 | 13280 | if (ins->address_mode != mode_64bit) |
5f847646 | 13281 | reg &= 7; |
dae39acc | 13282 | |
39fb3698 | 13283 | if (bytemode == x_mode && ins->vex.length == 256) |
e564475a | 13284 | names = att_names_ymm; |
6384fd9e | 13285 | |
2c3b9a91 | 13286 | oappend_register (ins, names[reg]); |
b13b1bc0 | 13287 | |
39fb3698 | 13288 | if (ins->vex.w) |
b13b1bc0 JB |
13289 | { |
13290 | /* Swap 3rd and 4th operands. */ | |
32f06c69 JB |
13291 | char *tmp = ins->op_out[3]; |
13292 | ||
13293 | ins->op_out[3] = ins->op_out[2]; | |
13294 | ins->op_out[2] = tmp; | |
b13b1bc0 | 13295 | } |
97601363 | 13296 | return true; |
c0f3af97 L |
13297 | } |
13298 | ||
97601363 | 13299 | static bool |
39fb3698 | 13300 | OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
93abb146 | 13301 | int sizeflag ATTRIBUTE_UNUSED) |
922d8de8 | 13302 | { |
95ff6718 | 13303 | oappend_immediate (ins, ins->codep[-1] & 0xf); |
97601363 | 13304 | return true; |
922d8de8 DR |
13305 | } |
13306 | ||
97601363 | 13307 | static bool |
39fb3698 | 13308 | VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
43234a1e L |
13309 | int sizeflag ATTRIBUTE_UNUSED) |
13310 | { | |
13311 | unsigned int cmp_type; | |
13312 | ||
39fb3698 | 13313 | if (!ins->vex.evex) |
43234a1e L |
13314 | abort (); |
13315 | ||
97601363 JB |
13316 | if (!fetch_code (ins->info, ins->codep + 1)) |
13317 | return false; | |
a4aa034a | 13318 | cmp_type = *ins->codep++; |
43234a1e L |
13319 | /* There are aliases for immediates 0, 1, 2, 4, 5, 6. |
13320 | If it's the case, print suffix, otherwise - print the immediate. */ | |
13321 | if (cmp_type < ARRAY_SIZE (simd_cmp_op) | |
13322 | && cmp_type != 3 | |
13323 | && cmp_type != 7) | |
13324 | { | |
39fb3698 VM |
13325 | char suffix[3]; |
13326 | char *p = ins->mnemonicendp - 2; | |
43234a1e L |
13327 | |
13328 | /* vpcmp* can have both one- and two-lettered suffix. */ | |
13329 | if (p[0] == 'p') | |
13330 | { | |
13331 | p++; | |
13332 | suffix[0] = p[0]; | |
13333 | suffix[1] = '\0'; | |
13334 | } | |
13335 | else | |
13336 | { | |
13337 | suffix[0] = p[0]; | |
13338 | suffix[1] = p[1]; | |
13339 | suffix[2] = '\0'; | |
13340 | } | |
13341 | ||
13342 | sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix); | |
39fb3698 | 13343 | ins->mnemonicendp += simd_cmp_op[cmp_type].len; |
43234a1e | 13344 | } |
be92cb14 JB |
13345 | else |
13346 | { | |
13347 | /* We have a reserved extension byte. Output it directly. */ | |
95ff6718 | 13348 | oappend_immediate (ins, cmp_type); |
be92cb14 | 13349 | } |
97601363 | 13350 | return true; |
be92cb14 JB |
13351 | } |
13352 | ||
13353 | static const struct op xop_cmp_op[] = | |
13354 | { | |
13355 | { STRING_COMMA_LEN ("lt") }, | |
13356 | { STRING_COMMA_LEN ("le") }, | |
13357 | { STRING_COMMA_LEN ("gt") }, | |
13358 | { STRING_COMMA_LEN ("ge") }, | |
13359 | { STRING_COMMA_LEN ("eq") }, | |
13360 | { STRING_COMMA_LEN ("neq") }, | |
13361 | { STRING_COMMA_LEN ("false") }, | |
13362 | { STRING_COMMA_LEN ("true") } | |
13363 | }; | |
13364 | ||
97601363 | 13365 | static bool |
39fb3698 | 13366 | VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
be92cb14 JB |
13367 | int sizeflag ATTRIBUTE_UNUSED) |
13368 | { | |
13369 | unsigned int cmp_type; | |
13370 | ||
97601363 JB |
13371 | if (!fetch_code (ins->info, ins->codep + 1)) |
13372 | return false; | |
a4aa034a | 13373 | cmp_type = *ins->codep++; |
be92cb14 JB |
13374 | if (cmp_type < ARRAY_SIZE (xop_cmp_op)) |
13375 | { | |
13376 | char suffix[3]; | |
39fb3698 | 13377 | char *p = ins->mnemonicendp - 2; |
be92cb14 JB |
13378 | |
13379 | /* vpcom* can have both one- and two-lettered suffix. */ | |
13380 | if (p[0] == 'm') | |
13381 | { | |
13382 | p++; | |
13383 | suffix[0] = p[0]; | |
13384 | suffix[1] = '\0'; | |
13385 | } | |
13386 | else | |
13387 | { | |
13388 | suffix[0] = p[0]; | |
13389 | suffix[1] = p[1]; | |
13390 | suffix[2] = '\0'; | |
13391 | } | |
13392 | ||
13393 | sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix); | |
39fb3698 | 13394 | ins->mnemonicendp += xop_cmp_op[cmp_type].len; |
be92cb14 | 13395 | } |
43234a1e L |
13396 | else |
13397 | { | |
13398 | /* We have a reserved extension byte. Output it directly. */ | |
95ff6718 | 13399 | oappend_immediate (ins, cmp_type); |
43234a1e | 13400 | } |
97601363 | 13401 | return true; |
43234a1e L |
13402 | } |
13403 | ||
ea397f5b L |
13404 | static const struct op pclmul_op[] = |
13405 | { | |
13406 | { STRING_COMMA_LEN ("lql") }, | |
13407 | { STRING_COMMA_LEN ("hql") }, | |
13408 | { STRING_COMMA_LEN ("lqh") }, | |
13409 | { STRING_COMMA_LEN ("hqh") } | |
c0f3af97 L |
13410 | }; |
13411 | ||
97601363 | 13412 | static bool |
39fb3698 | 13413 | PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED, |
c0f3af97 L |
13414 | int sizeflag ATTRIBUTE_UNUSED) |
13415 | { | |
13416 | unsigned int pclmul_type; | |
13417 | ||
97601363 JB |
13418 | if (!fetch_code (ins->info, ins->codep + 1)) |
13419 | return false; | |
a4aa034a | 13420 | pclmul_type = *ins->codep++; |
c0f3af97 L |
13421 | switch (pclmul_type) |
13422 | { | |
13423 | case 0x10: | |
13424 | pclmul_type = 2; | |
13425 | break; | |
13426 | case 0x11: | |
13427 | pclmul_type = 3; | |
13428 | break; | |
13429 | default: | |
13430 | break; | |
7bb15c6f | 13431 | } |
c0f3af97 L |
13432 | if (pclmul_type < ARRAY_SIZE (pclmul_op)) |
13433 | { | |
39fb3698 VM |
13434 | char suffix[4]; |
13435 | char *p = ins->mnemonicendp - 3; | |
c0f3af97 L |
13436 | suffix[0] = p[0]; |
13437 | suffix[1] = p[1]; | |
13438 | suffix[2] = p[2]; | |
13439 | suffix[3] = '\0'; | |
ea397f5b | 13440 | sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix); |
39fb3698 | 13441 | ins->mnemonicendp += pclmul_op[pclmul_type].len; |
c0f3af97 L |
13442 | } |
13443 | else | |
13444 | { | |
13445 | /* We have a reserved extension byte. Output it directly. */ | |
95ff6718 | 13446 | oappend_immediate (ins, pclmul_type); |
c0f3af97 | 13447 | } |
97601363 | 13448 | return true; |
c0f3af97 L |
13449 | } |
13450 | ||
97601363 | 13451 | static bool |
39fb3698 | 13452 | MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag) |
bc31405e L |
13453 | { |
13454 | /* Add proper suffix to "movsxd". */ | |
39fb3698 | 13455 | char *p = ins->mnemonicendp; |
bc31405e L |
13456 | |
13457 | switch (bytemode) | |
13458 | { | |
13459 | case movsxd_mode: | |
39fb3698 | 13460 | if (!ins->intel_syntax) |
bc31405e | 13461 | { |
4454883f | 13462 | USED_REX (REX_W); |
39fb3698 | 13463 | if (ins->rex & REX_W) |
4454883f JB |
13464 | { |
13465 | *p++ = 'l'; | |
13466 | *p++ = 'q'; | |
13467 | break; | |
13468 | } | |
bc31405e L |
13469 | } |
13470 | ||
4454883f JB |
13471 | *p++ = 'x'; |
13472 | *p++ = 'd'; | |
bc31405e L |
13473 | break; |
13474 | default: | |
39fb3698 | 13475 | oappend (ins, INTERNAL_DISASSEMBLER_ERROR); |
bc31405e L |
13476 | break; |
13477 | } | |
13478 | ||
39fb3698 | 13479 | ins->mnemonicendp = p; |
bc31405e | 13480 | *p = '\0'; |
97601363 | 13481 | return OP_E (ins, bytemode, sizeflag); |
bc31405e L |
13482 | } |
13483 | ||
97601363 | 13484 | static bool |
39fb3698 | 13485 | DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag) |
0cc78721 | 13486 | { |
39fb3698 VM |
13487 | unsigned int reg = ins->vex.register_specifier; |
13488 | unsigned int modrm_reg = ins->modrm.reg; | |
13489 | unsigned int modrm_rm = ins->modrm.rm; | |
0cc78721 CL |
13490 | |
13491 | /* Calc destination register number. */ | |
39fb3698 | 13492 | if (ins->rex & REX_R) |
0cc78721 | 13493 | modrm_reg += 8; |
39fb3698 | 13494 | if (!ins->vex.r) |
0cc78721 CL |
13495 | modrm_reg += 16; |
13496 | ||
13497 | /* Calc src1 register number. */ | |
39fb3698 | 13498 | if (ins->address_mode != mode_64bit) |
0cc78721 | 13499 | reg &= 7; |
39fb3698 | 13500 | else if (ins->vex.evex && !ins->vex.v) |
0cc78721 CL |
13501 | reg += 16; |
13502 | ||
13503 | /* Calc src2 register number. */ | |
39fb3698 | 13504 | if (ins->modrm.mod == 3) |
0cc78721 | 13505 | { |
39fb3698 | 13506 | if (ins->rex & REX_B) |
0cc78721 | 13507 | modrm_rm += 8; |
39fb3698 | 13508 | if (ins->rex & REX_X) |
0cc78721 CL |
13509 | modrm_rm += 16; |
13510 | } | |
13511 | ||
13512 | /* Destination and source registers must be distinct, output bad if | |
13513 | dest == src1 or dest == src2. */ | |
13514 | if (modrm_reg == reg | |
39fb3698 | 13515 | || (ins->modrm.mod == 3 |
0cc78721 CL |
13516 | && modrm_reg == modrm_rm)) |
13517 | { | |
39fb3698 | 13518 | oappend (ins, "(bad)"); |
97601363 | 13519 | return true; |
0cc78721 | 13520 | } |
97601363 | 13521 | return OP_XMM (ins, bytemode, sizeflag); |
0cc78721 CL |
13522 | } |
13523 | ||
97601363 | 13524 | static bool |
39fb3698 | 13525 | OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED) |
43234a1e | 13526 | { |
39fb3698 | 13527 | if (ins->modrm.mod != 3 || !ins->vex.b) |
97601363 | 13528 | return true; |
0e4cc773 JB |
13529 | |
13530 | switch (bytemode) | |
13531 | { | |
13532 | case evex_rounding_64_mode: | |
39fb3698 | 13533 | if (ins->address_mode != mode_64bit || !ins->vex.w) |
97601363 | 13534 | return true; |
0e4cc773 JB |
13535 | /* Fall through. */ |
13536 | case evex_rounding_mode: | |
39fb3698 VM |
13537 | ins->evex_used |= EVEX_b_used; |
13538 | oappend (ins, names_rounding[ins->vex.ll]); | |
0e4cc773 JB |
13539 | break; |
13540 | case evex_sae_mode: | |
39fb3698 VM |
13541 | ins->evex_used |= EVEX_b_used; |
13542 | oappend (ins, "{"); | |
0e4cc773 JB |
13543 | break; |
13544 | default: | |
13545 | abort (); | |
13546 | } | |
39fb3698 | 13547 | oappend (ins, "sae}"); |
97601363 | 13548 | return true; |
43234a1e | 13549 | } |
ef07be45 | 13550 | |
97601363 | 13551 | static bool |
ef07be45 CL |
13552 | PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag) |
13553 | { | |
13554 | if (ins->modrm.mod != 0 || ins->modrm.rm != 5) | |
13555 | { | |
13556 | if (ins->intel_syntax) | |
13557 | { | |
13558 | ins->mnemonicendp = stpcpy (ins->obuf, "nop "); | |
13559 | } | |
13560 | else | |
13561 | { | |
13562 | USED_REX (REX_W); | |
13563 | if (ins->rex & REX_W) | |
13564 | ins->mnemonicendp = stpcpy (ins->obuf, "nopq "); | |
13565 | else | |
13566 | { | |
13567 | if (sizeflag & DFLAG) | |
13568 | ins->mnemonicendp = stpcpy (ins->obuf, "nopl "); | |
13569 | else | |
13570 | ins->mnemonicendp = stpcpy (ins->obuf, "nopw "); | |
13571 | ins->used_prefixes |= (ins->prefixes & PREFIX_DATA); | |
13572 | } | |
13573 | } | |
13574 | bytemode = v_mode; | |
13575 | } | |
13576 | ||
97601363 | 13577 | return OP_M (ins, bytemode, sizeflag); |
ef07be45 | 13578 | } |