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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
d87bef3a | 2 | Copyright (C) 2007-2023 Free Software Foundation, Inc. |
0b1cf022 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
0b1cf022 | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
9 | any later version. |
10 | ||
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
0b1cf022 L |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | 02110-1301, USA. */ | |
20 | ||
21 | #include "opcode/i386.h" | |
40fb9820 | 22 | #include <limits.h> |
40fb9820 L |
23 | #ifndef CHAR_BIT |
24 | #define CHAR_BIT 8 | |
25 | #endif | |
26 | ||
27 | /* Position of cpu flags bitfiled. */ | |
28 | ||
734dfd1c | 29 | enum i386_cpu |
52a6c1fe L |
30 | { |
31 | /* i186 or better required */ | |
32 | Cpu186 = 0, | |
33 | /* i286 or better required */ | |
34 | Cpu286, | |
35 | /* i386 or better required */ | |
36 | Cpu386, | |
37 | /* i486 or better required */ | |
38 | Cpu486, | |
39 | /* i585 or better required */ | |
40 | Cpu586, | |
41 | /* i686 or better required */ | |
42 | Cpu686, | |
d871f3f4 L |
43 | /* CMOV Instruction support required */ |
44 | CpuCMOV, | |
45 | /* FXSR Instruction support required */ | |
46 | CpuFXSR, | |
b49dfb4a | 47 | /* CLFLUSH Instruction support required */ |
52a6c1fe | 48 | CpuClflush, |
22109423 L |
49 | /* NOP Instruction support required */ |
50 | CpuNop, | |
b49dfb4a | 51 | /* SYSCALL Instructions support required */ |
52a6c1fe L |
52 | CpuSYSCALL, |
53 | /* Floating point support required */ | |
54 | Cpu8087, | |
52a6c1fe L |
55 | /* i686 and floating point support required */ |
56 | Cpu687, | |
57 | /* SSE3 and floating point support required */ | |
58 | CpuFISTTP, | |
59 | /* MMX support required */ | |
60 | CpuMMX, | |
61 | /* SSE support required */ | |
62 | CpuSSE, | |
63 | /* SSE2 support required */ | |
64 | CpuSSE2, | |
52a6c1fe L |
65 | /* SSE3 support required */ |
66 | CpuSSE3, | |
67 | /* VIA PadLock required */ | |
68 | CpuPadLock, | |
69 | /* AMD Secure Virtual Machine Ext-s required */ | |
70 | CpuSVME, | |
71 | /* VMX Instructions required */ | |
72 | CpuVMX, | |
73 | /* SMX Instructions required */ | |
74 | CpuSMX, | |
75 | /* SSSE3 support required */ | |
76 | CpuSSSE3, | |
77 | /* SSE4a support required */ | |
78 | CpuSSE4a, | |
272a84b1 L |
79 | /* LZCNT support required */ |
80 | CpuLZCNT, | |
81 | /* POPCNT support required */ | |
82 | CpuPOPCNT, | |
cafa5ef7 JB |
83 | /* MONITOR support required */ |
84 | CpuMONITOR, | |
52a6c1fe L |
85 | /* SSE4.1 support required */ |
86 | CpuSSE4_1, | |
87 | /* SSE4.2 support required */ | |
88 | CpuSSE4_2, | |
6c30d220 L |
89 | /* AVX2 support required */ |
90 | CpuAVX2, | |
43234a1e L |
91 | /* Intel AVX-512 Conflict Detection Instructions support required */ |
92 | CpuAVX512CD, | |
93 | /* Intel AVX-512 Exponential and Reciprocal Instructions support | |
94 | required */ | |
95 | CpuAVX512ER, | |
96 | /* Intel AVX-512 Prefetch Instructions support required */ | |
97 | CpuAVX512PF, | |
90a915bf IT |
98 | /* Intel AVX-512 DQ Instructions support required. */ |
99 | CpuAVX512DQ, | |
1ba585e8 IT |
100 | /* Intel AVX-512 BW Instructions support required. */ |
101 | CpuAVX512BW, | |
7b6d09fb L |
102 | /* Intel IAMCU support required */ |
103 | CpuIAMCU, | |
b49dfb4a | 104 | /* Xsave/xrstor New Instructions support required */ |
52a6c1fe | 105 | CpuXsave, |
b49dfb4a | 106 | /* Xsaveopt New Instructions support required */ |
c7b8aa3a | 107 | CpuXsaveopt, |
52a6c1fe L |
108 | /* AES support required */ |
109 | CpuAES, | |
d54678eb JB |
110 | /* PCLMULQDQ support required */ |
111 | CpuPCLMULQDQ, | |
52a6c1fe L |
112 | /* FMA support required */ |
113 | CpuFMA, | |
114 | /* FMA4 support required */ | |
115 | CpuFMA4, | |
5dd85c99 SP |
116 | /* XOP support required */ |
117 | CpuXOP, | |
f88c9eb0 SP |
118 | /* LWP support required */ |
119 | CpuLWP, | |
f12dc422 L |
120 | /* BMI support required */ |
121 | CpuBMI, | |
2a2a0f38 QN |
122 | /* TBM support required */ |
123 | CpuTBM, | |
b49dfb4a | 124 | /* MOVBE Instruction support required */ |
52a6c1fe | 125 | CpuMovbe, |
60aa667e L |
126 | /* CMPXCHG16B instruction support required. */ |
127 | CpuCX16, | |
c3bb24f5 JB |
128 | /* LAHF/SAHF instruction support required (in 64-bit mode). */ |
129 | CpuLAHF_SAHF, | |
52a6c1fe L |
130 | /* EPT Instructions required */ |
131 | CpuEPT, | |
b49dfb4a | 132 | /* RDTSCP Instruction support required */ |
52a6c1fe | 133 | CpuRdtscp, |
77321f53 | 134 | /* FSGSBASE Instructions required */ |
c7b8aa3a L |
135 | CpuFSGSBase, |
136 | /* RDRND Instructions required */ | |
137 | CpuRdRnd, | |
138 | /* F16C Instructions required */ | |
139 | CpuF16C, | |
6c30d220 L |
140 | /* Intel BMI2 support required */ |
141 | CpuBMI2, | |
42164a71 L |
142 | /* RTM support required */ |
143 | CpuRTM, | |
6c30d220 L |
144 | /* INVPCID Instructions required */ |
145 | CpuINVPCID, | |
8729a6f6 L |
146 | /* VMFUNC Instruction required */ |
147 | CpuVMFUNC, | |
7e8b059b L |
148 | /* Intel MPX Instructions required */ |
149 | CpuMPX, | |
e2e1fcde L |
150 | /* RDRSEED instruction required. */ |
151 | CpuRDSEED, | |
152 | /* Multi-presisionn add-carry instructions are required. */ | |
153 | CpuADX, | |
7b458c12 | 154 | /* Supports prefetchw and prefetch instructions. */ |
e2e1fcde | 155 | CpuPRFCHW, |
5c111e37 L |
156 | /* SMAP instructions required. */ |
157 | CpuSMAP, | |
a0046408 L |
158 | /* SHA instructions required. */ |
159 | CpuSHA, | |
b5c37946 SJ |
160 | /* SHA512 instructions required. */ |
161 | CpuSHA512, | |
162 | /* SM3 instructions required. */ | |
163 | CpuSM3, | |
164 | /* SM4 instructions required. */ | |
165 | CpuSM4, | |
963f3586 IT |
166 | /* CLFLUSHOPT instruction required */ |
167 | CpuClflushOpt, | |
168 | /* XSAVES/XRSTORS instruction required */ | |
169 | CpuXSAVES, | |
170 | /* XSAVEC instruction required */ | |
171 | CpuXSAVEC, | |
dcf893b5 IT |
172 | /* PREFETCHWT1 instruction required */ |
173 | CpuPREFETCHWT1, | |
2cf200a4 IT |
174 | /* SE1 instruction required */ |
175 | CpuSE1, | |
c5e7287a IT |
176 | /* CLWB instruction required */ |
177 | CpuCLWB, | |
2cc1b5aa IT |
178 | /* Intel AVX-512 IFMA Instructions support required. */ |
179 | CpuAVX512IFMA, | |
14f195c9 IT |
180 | /* Intel AVX-512 VBMI Instructions support required. */ |
181 | CpuAVX512VBMI, | |
920d2ddc IT |
182 | /* Intel AVX-512 4FMAPS Instructions support required. */ |
183 | CpuAVX512_4FMAPS, | |
47acf0bd IT |
184 | /* Intel AVX-512 4VNNIW Instructions support required. */ |
185 | CpuAVX512_4VNNIW, | |
620214f7 IT |
186 | /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ |
187 | CpuAVX512_VPOPCNTDQ, | |
53467f57 IT |
188 | /* Intel AVX-512 VBMI2 Instructions support required. */ |
189 | CpuAVX512_VBMI2, | |
8cfcb765 IT |
190 | /* Intel AVX-512 VNNI Instructions support required. */ |
191 | CpuAVX512_VNNI, | |
ee6872be IT |
192 | /* Intel AVX-512 BITALG Instructions support required. */ |
193 | CpuAVX512_BITALG, | |
d6aab7a1 XG |
194 | /* Intel AVX-512 BF16 Instructions support required. */ |
195 | CpuAVX512_BF16, | |
9186c494 L |
196 | /* Intel AVX-512 VP2INTERSECT Instructions support required. */ |
197 | CpuAVX512_VP2INTERSECT, | |
81d54bb7 CL |
198 | /* TDX Instructions support required. */ |
199 | CpuTDX, | |
58bf9b6a L |
200 | /* Intel AVX VNNI Instructions support required. */ |
201 | CpuAVX_VNNI, | |
0cc78721 CL |
202 | /* Intel AVX-512 FP16 Instructions support required. */ |
203 | CpuAVX512_FP16, | |
ef07be45 CL |
204 | /* PREFETCHI instruction required */ |
205 | CpuPREFETCHI, | |
4321af3e HW |
206 | /* Intel AVX IFMA Instructions support required. */ |
207 | CpuAVX_IFMA, | |
23ae61ad CL |
208 | /* Intel AVX VNNI-INT8 Instructions support required. */ |
209 | CpuAVX_VNNI_INT8, | |
b5c37946 SJ |
210 | /* Intel AVX VNNI-INT16 Instructions support required. */ |
211 | CpuAVX_VNNI_INT16, | |
a93e3234 HJ |
212 | /* Intel CMPccXADD instructions support required. */ |
213 | CpuCMPCCXADD, | |
941f0833 HL |
214 | /* Intel WRMSRNS Instructions support required */ |
215 | CpuWRMSRNS, | |
2188d6ea HL |
216 | /* Intel MSRLIST Instructions support required. */ |
217 | CpuMSRLIST, | |
01d8ce74 | 218 | /* Intel AVX NE CONVERT Instructions support required. */ |
219 | CpuAVX_NE_CONVERT, | |
b06311ad KL |
220 | /* Intel RAO INT Instructions support required. */ |
221 | CpuRAO_INT, | |
c88ed92f ZJ |
222 | /* fred instruction required */ |
223 | CpuFRED, | |
224 | /* lkgs instruction required */ | |
225 | CpuLKGS, | |
8170af78 HL |
226 | /* Intel USER_MSR Instruction support required. */ |
227 | CpuUSER_MSR, | |
9916071f AP |
228 | /* mwaitx instruction required */ |
229 | CpuMWAITX, | |
43e65147 | 230 | /* Clzero instruction required */ |
029f3522 | 231 | CpuCLZERO, |
8eab4136 L |
232 | /* OSPKE instruction required */ |
233 | CpuOSPKE, | |
8bc52696 AF |
234 | /* RDPID instruction required */ |
235 | CpuRDPID, | |
6b40c462 L |
236 | /* PTWRITE instruction required */ |
237 | CpuPTWRITE, | |
d777820b IT |
238 | /* CET instructions support required */ |
239 | CpuIBT, | |
240 | CpuSHSTK, | |
260cd341 LC |
241 | /* AMX-INT8 instructions required */ |
242 | CpuAMX_INT8, | |
243 | /* AMX-BF16 instructions required */ | |
244 | CpuAMX_BF16, | |
68830fba CL |
245 | /* AMX-FP16 instructions required */ |
246 | CpuAMX_FP16, | |
d100d8c1 HJ |
247 | /* AMX-COMPLEX instructions required. */ |
248 | CpuAMX_COMPLEX, | |
260cd341 LC |
249 | /* AMX-TILE instructions required */ |
250 | CpuAMX_TILE, | |
48521003 IT |
251 | /* GFNI instructions required */ |
252 | CpuGFNI, | |
8dcf1fad IT |
253 | /* VAES instructions required */ |
254 | CpuVAES, | |
ff1982d5 IT |
255 | /* VPCLMULQDQ instructions required */ |
256 | CpuVPCLMULQDQ, | |
3233d7d0 IT |
257 | /* WBNOINVD instructions required */ |
258 | CpuWBNOINVD, | |
be3a8dca IT |
259 | /* PCONFIG instructions required */ |
260 | CpuPCONFIG, | |
b5c37946 SJ |
261 | /* PBNDKB instructions required. */ |
262 | CpuPBNDKB, | |
de89d0a3 IT |
263 | /* WAITPKG instructions required */ |
264 | CpuWAITPKG, | |
f64c42a9 LC |
265 | /* UINTR instructions required */ |
266 | CpuUINTR, | |
c48935d7 IT |
267 | /* CLDEMOTE instruction required */ |
268 | CpuCLDEMOTE, | |
c0a30a9f L |
269 | /* MOVDIRI instruction support required */ |
270 | CpuMOVDIRI, | |
271 | /* MOVDIRR64B instruction required */ | |
272 | CpuMOVDIR64B, | |
5d79adc4 L |
273 | /* ENQCMD instruction required */ |
274 | CpuENQCMD, | |
4b27d27c L |
275 | /* SERIALIZE instruction required */ |
276 | CpuSERIALIZE, | |
142861df JB |
277 | /* RDPRU instruction required */ |
278 | CpuRDPRU, | |
279 | /* MCOMMIT instruction required */ | |
280 | CpuMCOMMIT, | |
a847e322 JB |
281 | /* SEV-ES instruction(s) required */ |
282 | CpuSEV_ES, | |
bb651e8b CL |
283 | /* TSXLDTRK instruction required */ |
284 | CpuTSXLDTRK, | |
c4694f17 TG |
285 | /* KL instruction support required */ |
286 | CpuKL, | |
287 | /* WideKL instruction support required */ | |
288 | CpuWideKL, | |
c1fa250a LC |
289 | /* HRESET instruction required */ |
290 | CpuHRESET, | |
646cc3e0 GG |
291 | /* INVLPGB instructions required */ |
292 | CpuINVLPGB, | |
293 | /* TLBSYNC instructions required */ | |
294 | CpuTLBSYNC, | |
295 | /* SNP instructions required */ | |
296 | CpuSNP, | |
b0e8fa7f TJ |
297 | /* RMPQUERY instruction required */ |
298 | CpuRMPQUERY, | |
13ed231a | 299 | |
734dfd1c JB |
300 | /* NOTE: These items, which can be combined with other ISA flags above, need |
301 | to remain second to last and in sync with CPU_FLAGS_COMMON. */ | |
13ed231a | 302 | |
734dfd1c JB |
303 | /* i287 support required */ |
304 | Cpu287, | |
305 | CpuAttrEnums = Cpu287, | |
306 | /* i387 support required */ | |
307 | Cpu387, | |
308 | /* 3dnow! support required */ | |
309 | Cpu3dnow, | |
310 | /* 3dnow! Extensions support required */ | |
311 | Cpu3dnowA, | |
da5f9eb4 JB |
312 | /* 64bit support required */ |
313 | Cpu64, | |
734dfd1c JB |
314 | /* AVX support required */ |
315 | CpuAVX, | |
316 | /* HLE support required */ | |
317 | CpuHLE, | |
318 | /* Intel AVX-512 Foundation Instructions support required */ | |
319 | CpuAVX512F, | |
320 | /* Intel AVX-512 VL Instructions support required. */ | |
321 | CpuAVX512VL, | |
52a6c1fe L |
322 | /* Not supported in the 64bit mode */ |
323 | CpuNo64, | |
734dfd1c JB |
324 | |
325 | /* NOTE: This item needs to remain last. */ | |
326 | ||
52a6c1fe | 327 | /* The last bitfield in i386_cpu_flags. */ |
e92bae62 | 328 | CpuMax = CpuNo64 |
52a6c1fe | 329 | }; |
40fb9820 L |
330 | |
331 | #define CpuNumOfUints \ | |
332 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
333 | #define CpuNumOfBits \ | |
334 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
335 | ||
734dfd1c JB |
336 | #define CpuIsaBits 8 |
337 | #define CpuAttrNumOfUints \ | |
338 | ((CpuIsaBits + CpuMax - CpuAttrEnums) / sizeof (unsigned int) / CHAR_BIT + 1) | |
339 | #define CpuAttrNumOfBits \ | |
340 | (CpuAttrNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
341 | ||
342 | /* If you get a compiler error for zero width of an unused field, | |
343 | comment the respective one out. */ | |
a93e3234 | 344 | #define CpuUnused (CpuMax + 1) |
734dfd1c JB |
345 | #define CpuAttrUnused (CpuIsaBits + CpuMax + 1 - CpuAttrEnums) |
346 | ||
347 | #define CPU_FLAGS_COMMON \ | |
348 | unsigned int cpu287:1, \ | |
349 | cpu387:1, \ | |
350 | cpu3dnow:1, \ | |
351 | cpu3dnowa:1, \ | |
da5f9eb4 | 352 | cpu64:1, \ |
734dfd1c JB |
353 | cpuavx:1, \ |
354 | cpuhle:1, \ | |
355 | cpuavx512f:1, \ | |
356 | cpuavx512vl:1, \ | |
da5f9eb4 | 357 | /* NOTE: This field needs to remain last. */ \ |
734dfd1c JB |
358 | cpuno64:1 |
359 | ||
360 | typedef union i386_cpu_attr | |
361 | { | |
362 | struct | |
363 | { | |
364 | unsigned int isa:CpuIsaBits; | |
365 | CPU_FLAGS_COMMON; | |
366 | #ifdef CpuAttrUnused | |
367 | unsigned int unused:(CpuAttrNumOfBits - CpuAttrUnused); | |
368 | #endif | |
369 | } bitfield; | |
370 | unsigned int array[CpuAttrNumOfUints]; | |
371 | } i386_cpu_attr; | |
53467f57 | 372 | |
40fb9820 L |
373 | /* We can check if an instruction is available with array instead |
374 | of bitfield. */ | |
375 | typedef union i386_cpu_flags | |
376 | { | |
377 | struct | |
378 | { | |
379 | unsigned int cpui186:1; | |
380 | unsigned int cpui286:1; | |
381 | unsigned int cpui386:1; | |
382 | unsigned int cpui486:1; | |
383 | unsigned int cpui586:1; | |
384 | unsigned int cpui686:1; | |
d871f3f4 L |
385 | unsigned int cpucmov:1; |
386 | unsigned int cpufxsr:1; | |
bd5295b2 | 387 | unsigned int cpuclflush:1; |
22109423 | 388 | unsigned int cpunop:1; |
bd5295b2 | 389 | unsigned int cpusyscall:1; |
309d3373 | 390 | unsigned int cpu8087:1; |
309d3373 JB |
391 | unsigned int cpu687:1; |
392 | unsigned int cpufisttp:1; | |
40fb9820 | 393 | unsigned int cpummx:1; |
40fb9820 L |
394 | unsigned int cpusse:1; |
395 | unsigned int cpusse2:1; | |
40fb9820 L |
396 | unsigned int cpusse3:1; |
397 | unsigned int cpupadlock:1; | |
398 | unsigned int cpusvme:1; | |
399 | unsigned int cpuvmx:1; | |
47dd174c | 400 | unsigned int cpusmx:1; |
40fb9820 L |
401 | unsigned int cpussse3:1; |
402 | unsigned int cpusse4a:1; | |
272a84b1 L |
403 | unsigned int cpulzcnt:1; |
404 | unsigned int cpupopcnt:1; | |
cafa5ef7 | 405 | unsigned int cpumonitor:1; |
40fb9820 L |
406 | unsigned int cpusse4_1:1; |
407 | unsigned int cpusse4_2:1; | |
6c30d220 | 408 | unsigned int cpuavx2:1; |
43234a1e L |
409 | unsigned int cpuavx512cd:1; |
410 | unsigned int cpuavx512er:1; | |
411 | unsigned int cpuavx512pf:1; | |
90a915bf | 412 | unsigned int cpuavx512dq:1; |
1ba585e8 | 413 | unsigned int cpuavx512bw:1; |
7b6d09fb | 414 | unsigned int cpuiamcu:1; |
475a2301 | 415 | unsigned int cpuxsave:1; |
c7b8aa3a | 416 | unsigned int cpuxsaveopt:1; |
c0f3af97 | 417 | unsigned int cpuaes:1; |
d54678eb | 418 | unsigned int cpupclmulqdq:1; |
c0f3af97 | 419 | unsigned int cpufma:1; |
922d8de8 | 420 | unsigned int cpufma4:1; |
5dd85c99 | 421 | unsigned int cpuxop:1; |
f88c9eb0 | 422 | unsigned int cpulwp:1; |
f12dc422 | 423 | unsigned int cpubmi:1; |
2a2a0f38 | 424 | unsigned int cputbm:1; |
f1f8f695 | 425 | unsigned int cpumovbe:1; |
60aa667e | 426 | unsigned int cpucx16:1; |
c3bb24f5 | 427 | unsigned int cpulahf_sahf:1; |
f1f8f695 | 428 | unsigned int cpuept:1; |
1b7f3fb0 | 429 | unsigned int cpurdtscp:1; |
c7b8aa3a L |
430 | unsigned int cpufsgsbase:1; |
431 | unsigned int cpurdrnd:1; | |
432 | unsigned int cpuf16c:1; | |
6c30d220 | 433 | unsigned int cpubmi2:1; |
42164a71 | 434 | unsigned int cpurtm:1; |
6c30d220 | 435 | unsigned int cpuinvpcid:1; |
8729a6f6 | 436 | unsigned int cpuvmfunc:1; |
7e8b059b | 437 | unsigned int cpumpx:1; |
e2e1fcde L |
438 | unsigned int cpurdseed:1; |
439 | unsigned int cpuadx:1; | |
440 | unsigned int cpuprfchw:1; | |
5c111e37 | 441 | unsigned int cpusmap:1; |
a0046408 | 442 | unsigned int cpusha:1; |
b5c37946 SJ |
443 | unsigned int cpusha512:1; |
444 | unsigned int cpusm3:1; | |
445 | unsigned int cpusm4:1; | |
963f3586 IT |
446 | unsigned int cpuclflushopt:1; |
447 | unsigned int cpuxsaves:1; | |
448 | unsigned int cpuxsavec:1; | |
dcf893b5 | 449 | unsigned int cpuprefetchwt1:1; |
2cf200a4 | 450 | unsigned int cpuse1:1; |
c5e7287a | 451 | unsigned int cpuclwb:1; |
2cc1b5aa | 452 | unsigned int cpuavx512ifma:1; |
14f195c9 | 453 | unsigned int cpuavx512vbmi:1; |
920d2ddc | 454 | unsigned int cpuavx512_4fmaps:1; |
47acf0bd | 455 | unsigned int cpuavx512_4vnniw:1; |
620214f7 | 456 | unsigned int cpuavx512_vpopcntdq:1; |
53467f57 | 457 | unsigned int cpuavx512_vbmi2:1; |
8cfcb765 | 458 | unsigned int cpuavx512_vnni:1; |
ee6872be | 459 | unsigned int cpuavx512_bitalg:1; |
d6aab7a1 | 460 | unsigned int cpuavx512_bf16:1; |
9186c494 | 461 | unsigned int cpuavx512_vp2intersect:1; |
81d54bb7 | 462 | unsigned int cputdx:1; |
58bf9b6a | 463 | unsigned int cpuavx_vnni:1; |
0cc78721 | 464 | unsigned int cpuavx512_fp16:1; |
ef07be45 | 465 | unsigned int cpuprefetchi:1; |
4321af3e | 466 | unsigned int cpuavx_ifma:1; |
23ae61ad | 467 | unsigned int cpuavx_vnni_int8:1; |
b5c37946 | 468 | unsigned int cpuavx_vnni_int16:1; |
a93e3234 | 469 | unsigned int cpucmpccxadd:1; |
941f0833 | 470 | unsigned int cpuwrmsrns:1; |
2188d6ea | 471 | unsigned int cpumsrlist:1; |
01d8ce74 | 472 | unsigned int cpuavx_ne_convert:1; |
b06311ad | 473 | unsigned int cpurao_int:1; |
c88ed92f ZJ |
474 | unsigned int cpufred:1; |
475 | unsigned int cpulkgs:1; | |
8170af78 | 476 | unsigned int cpuuser_msr:1; |
9916071f | 477 | unsigned int cpumwaitx:1; |
029f3522 | 478 | unsigned int cpuclzero:1; |
8eab4136 | 479 | unsigned int cpuospke:1; |
8bc52696 | 480 | unsigned int cpurdpid:1; |
6b40c462 | 481 | unsigned int cpuptwrite:1; |
d777820b IT |
482 | unsigned int cpuibt:1; |
483 | unsigned int cpushstk:1; | |
260cd341 LC |
484 | unsigned int cpuamx_int8:1; |
485 | unsigned int cpuamx_bf16:1; | |
68830fba | 486 | unsigned int cpuamx_fp16:1; |
d100d8c1 | 487 | unsigned int cpuamx_complex:1; |
260cd341 | 488 | unsigned int cpuamx_tile:1; |
48521003 | 489 | unsigned int cpugfni:1; |
8dcf1fad | 490 | unsigned int cpuvaes:1; |
ff1982d5 | 491 | unsigned int cpuvpclmulqdq:1; |
3233d7d0 | 492 | unsigned int cpuwbnoinvd:1; |
be3a8dca | 493 | unsigned int cpupconfig:1; |
b5c37946 | 494 | unsigned int cpupbndkb:1; |
de89d0a3 | 495 | unsigned int cpuwaitpkg:1; |
f64c42a9 | 496 | unsigned int cpuuintr:1; |
c48935d7 | 497 | unsigned int cpucldemote:1; |
c0a30a9f L |
498 | unsigned int cpumovdiri:1; |
499 | unsigned int cpumovdir64b:1; | |
5d79adc4 | 500 | unsigned int cpuenqcmd:1; |
4b27d27c | 501 | unsigned int cpuserialize:1; |
142861df JB |
502 | unsigned int cpurdpru:1; |
503 | unsigned int cpumcommit:1; | |
a847e322 | 504 | unsigned int cpusev_es:1; |
bb651e8b | 505 | unsigned int cputsxldtrk:1; |
c4694f17 TG |
506 | unsigned int cpukl:1; |
507 | unsigned int cpuwidekl:1; | |
c1fa250a | 508 | unsigned int cpuhreset:1; |
646cc3e0 GG |
509 | unsigned int cpuinvlpgb:1; |
510 | unsigned int cputlbsync:1; | |
511 | unsigned int cpusnp:1; | |
b0e8fa7f | 512 | unsigned int cpurmpquery:1; |
734dfd1c | 513 | CPU_FLAGS_COMMON; |
40fb9820 L |
514 | #ifdef CpuUnused |
515 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
516 | #endif | |
517 | } bitfield; | |
518 | unsigned int array[CpuNumOfUints]; | |
519 | } i386_cpu_flags; | |
520 | ||
521 | /* Position of opcode_modifier bits. */ | |
522 | ||
52a6c1fe L |
523 | enum |
524 | { | |
525 | /* has direction bit. */ | |
526 | D = 0, | |
507916b8 JB |
527 | /* set if operands can be both bytes and words/dwords/qwords, encoded the |
528 | canonical way; the base_opcode field should hold the encoding for byte | |
529 | operands */ | |
52a6c1fe | 530 | W, |
86fa6981 L |
531 | /* load form instruction. Must be placed before store form. */ |
532 | Load, | |
52a6c1fe L |
533 | /* insn has a modrm byte. */ |
534 | Modrm, | |
0cfa3eb3 JB |
535 | /* special case for jump insns; value has to be 1 */ |
536 | #define JUMP 1 | |
52a6c1fe | 537 | /* call and jump */ |
0cfa3eb3 | 538 | #define JUMP_DWORD 2 |
52a6c1fe | 539 | /* loop and jecxz */ |
0cfa3eb3 | 540 | #define JUMP_BYTE 3 |
52a6c1fe | 541 | /* special case for intersegment leaps/calls */ |
0cfa3eb3 | 542 | #define JUMP_INTERSEGMENT 4 |
6f2f06be | 543 | /* absolute address for jump */ |
0cfa3eb3 JB |
544 | #define JUMP_ABSOLUTE 5 |
545 | Jump, | |
52a6c1fe L |
546 | /* FP insn memory format bit, sized by 0x4 */ |
547 | FloatMF, | |
52a6c1fe | 548 | /* needs size prefix if in 32-bit mode */ |
673fe0f0 | 549 | #define SIZE16 1 |
52a6c1fe | 550 | /* needs size prefix if in 16-bit mode */ |
673fe0f0 | 551 | #define SIZE32 2 |
52a6c1fe | 552 | /* needs size prefix if in 64-bit mode */ |
673fe0f0 JB |
553 | #define SIZE64 3 |
554 | Size, | |
9c19e9ec JB |
555 | /* Check that operand sizes match. */ |
556 | CheckOperandSize, | |
255571cd JB |
557 | /* any memory size */ |
558 | #define ANY_SIZE 1 | |
559 | /* fake an extra reg operand for clr, imul and special register | |
560 | processing for some instructions. */ | |
561 | #define REG_KLUDGE 2 | |
562 | /* deprecated fp insn, gets a warning */ | |
563 | #define UGH 3 | |
564 | /* An implicit xmm0 as the first operand */ | |
565 | #define IMPLICIT_1ST_XMM0 4 | |
566 | /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. | |
567 | It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). | |
568 | */ | |
569 | #define IMPLICIT_QUAD_GROUP 5 | |
570 | /* Two source operands are swapped. */ | |
571 | #define SWAP_SOURCES 6 | |
572 | /* Default mask isn't allowed. */ | |
573 | #define NO_DEFAULT_MASK 7 | |
574 | /* Address prefix changes register operand */ | |
575 | #define ADDR_PREFIX_OP_REG 8 | |
0cc78721 CL |
576 | /* Instrucion requires that destination must be distinct from source |
577 | registers. */ | |
255571cd JB |
578 | #define DISTINCT_DEST 9 |
579 | OperandConstraint, | |
52a6c1fe L |
580 | /* instruction ignores operand size prefix and in Intel mode ignores |
581 | mnemonic size suffix check. */ | |
3cd7f3e3 | 582 | #define IGNORESIZE 1 |
52a6c1fe | 583 | /* default insn size depends on mode */ |
3cd7f3e3 L |
584 | #define DEFAULTSIZE 2 |
585 | MnemonicSize, | |
52a6c1fe L |
586 | /* b suffix on instruction illegal */ |
587 | No_bSuf, | |
588 | /* w suffix on instruction illegal */ | |
589 | No_wSuf, | |
590 | /* l suffix on instruction illegal */ | |
591 | No_lSuf, | |
592 | /* s suffix on instruction illegal */ | |
593 | No_sSuf, | |
594 | /* q suffix on instruction illegal */ | |
595 | No_qSuf, | |
52a6c1fe L |
596 | /* instruction needs FWAIT */ |
597 | FWait, | |
51c8edf6 JB |
598 | /* IsString provides for a quick test for string instructions, and |
599 | its actual value also indicates which of the operands (if any) | |
600 | requires use of the %es segment. */ | |
601 | #define IS_STRING_ES_OP0 2 | |
602 | #define IS_STRING_ES_OP1 3 | |
52a6c1fe | 603 | IsString, |
dfd69174 JB |
604 | /* RegMem is for instructions with a modrm byte where the register |
605 | destination operand should be encoded in the mod and regmem fields. | |
606 | Normally, it will be encoded in the reg field. We add a RegMem | |
607 | flag to indicate that it should be encoded in the regmem field. */ | |
608 | RegMem, | |
7e8b059b L |
609 | /* quick test if branch instruction is MPX supported */ |
610 | BNDPrefixOk, | |
742732c7 JB |
611 | #define PrefixNone 0 |
612 | #define PrefixRep 1 | |
613 | #define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */ | |
614 | #define PrefixNoTrack 3 | |
615 | /* Prefixes implying "LOCK okay" must come after Lock. All others have | |
616 | to come before. */ | |
617 | #define PrefixLock 4 | |
618 | #define PrefixHLELock 5 /* Okay with a LOCK prefix. */ | |
619 | #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */ | |
620 | PrefixOk, | |
52a6c1fe L |
621 | /* opcode is a prefix */ |
622 | IsPrefix, | |
623 | /* instruction has extension in 8 bit imm */ | |
624 | ImmExt, | |
625 | /* instruction don't need Rex64 prefix. */ | |
626 | NoRex64, | |
52a6c1fe | 627 | /* insn has VEX prefix: |
10c17abd | 628 | 1: 128bit VEX prefix (or operand dependent). |
2bf05e57 | 629 | 2: 256bit VEX prefix. |
712366da | 630 | 3: Scalar VEX prefix. |
52a6c1fe | 631 | */ |
712366da L |
632 | #define VEX128 1 |
633 | #define VEX256 2 | |
634 | #define VEXScalar 3 | |
52a6c1fe | 635 | Vex, |
2426c15f L |
636 | /* How to encode VEX.vvvv: |
637 | 0: VEX.vvvv must be 1111b. | |
eea96d3f | 638 | 1: VEX.vvvv encodes one of the register operands. |
2426c15f | 639 | */ |
2426c15f | 640 | VexVVVV, |
1ef99a7b L |
641 | /* How the VEX.W bit is used: |
642 | 0: Set by the REX.W bit. | |
643 | 1: VEX.W0. Should always be 0. | |
644 | 2: VEX.W1. Should always be 1. | |
6865c043 | 645 | 3: VEX.WIG. The VEX.W bit is ignored. |
1ef99a7b L |
646 | */ |
647 | #define VEXW0 1 | |
648 | #define VEXW1 2 | |
6865c043 | 649 | #define VEXWIG 3 |
1ef99a7b | 650 | VexW, |
b933fa4b JB |
651 | /* Opcode prefix (values chosen to be usable directly in |
652 | VEX/XOP/EVEX pp fields): | |
7b47a312 L |
653 | 0: None |
654 | 1: Add 0x66 opcode prefix. | |
b933fa4b JB |
655 | 2: Add 0xf3 opcode prefix. |
656 | 3: Add 0xf2 opcode prefix. | |
7b47a312 L |
657 | */ |
658 | #define PREFIX_NONE 0 | |
659 | #define PREFIX_0X66 1 | |
b933fa4b JB |
660 | #define PREFIX_0XF3 2 |
661 | #define PREFIX_0XF2 3 | |
7b47a312 | 662 | OpcodePrefix, |
63112cd6 | 663 | /* Instruction with a mandatory SIB byte: |
6c30d220 L |
664 | 1: 128bit vector register. |
665 | 2: 256bit vector register. | |
43234a1e | 666 | 3: 512bit vector register. |
6c30d220 | 667 | */ |
63112cd6 L |
668 | #define VECSIB128 1 |
669 | #define VECSIB256 2 | |
670 | #define VECSIB512 3 | |
260cd341 | 671 | #define SIBMEM 4 |
63112cd6 | 672 | SIB, |
260cd341 | 673 | |
52a6c1fe L |
674 | /* SSE to AVX support required */ |
675 | SSE2AVX, | |
43234a1e L |
676 | |
677 | /* insn has EVEX prefix: | |
678 | 1: 512bit EVEX prefix. | |
679 | 2: 128bit EVEX prefix. | |
680 | 3: 256bit EVEX prefix. | |
681 | 4: Length-ignored (LIG) EVEX prefix. | |
e771e7c9 | 682 | 5: Length determined from actual operands. |
d0c2e3ec | 683 | 6: L'L = 3 (reserved, .insn only) |
43234a1e L |
684 | */ |
685 | #define EVEX512 1 | |
686 | #define EVEX128 2 | |
687 | #define EVEX256 3 | |
688 | #define EVEXLIG 4 | |
e771e7c9 | 689 | #define EVEXDYN 5 |
d0c2e3ec | 690 | #define EVEX_L3 6 |
43234a1e L |
691 | EVex, |
692 | ||
b1c79256 | 693 | /* AVX512 masking support */ |
43234a1e L |
694 | Masking, |
695 | ||
4a1b91ea L |
696 | /* AVX512 broadcast support. The number of bytes to broadcast is |
697 | 1 << (Broadcast - 1): | |
698 | 1: Byte broadcast. | |
699 | 2: Word broadcast. | |
700 | 3: Dword broadcast. | |
701 | 4: Qword broadcast. | |
702 | */ | |
703 | #define BYTE_BROADCAST 1 | |
704 | #define WORD_BROADCAST 2 | |
705 | #define DWORD_BROADCAST 3 | |
706 | #define QWORD_BROADCAST 4 | |
43234a1e L |
707 | Broadcast, |
708 | ||
709 | /* Static rounding control is supported. */ | |
710 | StaticRounding, | |
711 | ||
712 | /* Supress All Exceptions is supported. */ | |
713 | SAE, | |
714 | ||
7091c612 JB |
715 | /* Compressed Disp8*N attribute. */ |
716 | #define DISP8_SHIFT_VL 7 | |
43234a1e L |
717 | Disp8MemShift, |
718 | ||
4fc85f37 JB |
719 | /* insn has vector size restrictions, requiring a minimum of: |
720 | 0: 128 bits. | |
721 | 1: 256 bits. | |
722 | 2: 512 bits. | |
723 | */ | |
724 | #define VSZ128 0 /* Not to be used in templates. */ | |
725 | #define VSZ256 1 | |
726 | #define VSZ512 2 | |
727 | Vsz, | |
728 | ||
b6f8c7c4 L |
729 | /* Support encoding optimization. */ |
730 | Optimize, | |
731 | ||
52a6c1fe L |
732 | /* AT&T mnemonic. */ |
733 | ATTMnemonic, | |
734 | /* AT&T syntax. */ | |
735 | ATTSyntax, | |
736 | /* Intel syntax. */ | |
737 | IntelSyntax, | |
4b5aaf5f L |
738 | /* ISA64: Don't change the order without other code adjustments. |
739 | 0: Common to AMD64 and Intel64. | |
740 | 1: AMD64. | |
741 | 2: Intel64. | |
742 | 3: Only in Intel64. | |
743 | */ | |
744 | #define AMD64 1 | |
745 | #define INTEL64 2 | |
746 | #define INTEL64ONLY 3 | |
747 | ISA64, | |
52a6c1fe | 748 | /* The last bitfield in i386_opcode_modifier. */ |
1d942ae9 | 749 | Opcode_Modifier_Num |
52a6c1fe | 750 | }; |
40fb9820 L |
751 | |
752 | typedef struct i386_opcode_modifier | |
753 | { | |
754 | unsigned int d:1; | |
755 | unsigned int w:1; | |
86fa6981 | 756 | unsigned int load:1; |
40fb9820 | 757 | unsigned int modrm:1; |
0cfa3eb3 | 758 | unsigned int jump:3; |
40fb9820 | 759 | unsigned int floatmf:1; |
673fe0f0 | 760 | unsigned int size:2; |
9c19e9ec | 761 | unsigned int checkoperandsize:1; |
255571cd | 762 | unsigned int operandconstraint:4; |
3cd7f3e3 | 763 | unsigned int mnemonicsize:2; |
40fb9820 L |
764 | unsigned int no_bsuf:1; |
765 | unsigned int no_wsuf:1; | |
766 | unsigned int no_lsuf:1; | |
767 | unsigned int no_ssuf:1; | |
768 | unsigned int no_qsuf:1; | |
40fb9820 | 769 | unsigned int fwait:1; |
51c8edf6 | 770 | unsigned int isstring:2; |
dfd69174 | 771 | unsigned int regmem:1; |
7e8b059b | 772 | unsigned int bndprefixok:1; |
742732c7 | 773 | unsigned int prefixok:3; |
40fb9820 L |
774 | unsigned int isprefix:1; |
775 | unsigned int immext:1; | |
776 | unsigned int norex64:1; | |
2bf05e57 | 777 | unsigned int vex:2; |
eea96d3f | 778 | unsigned int vexvvvv:1; |
1ef99a7b | 779 | unsigned int vexw:2; |
441f6aca | 780 | unsigned int opcodeprefix:2; |
260cd341 | 781 | unsigned int sib:3; |
c0f3af97 | 782 | unsigned int sse2avx:1; |
43234a1e | 783 | unsigned int evex:3; |
b1c79256 | 784 | unsigned int masking:1; |
4a1b91ea | 785 | unsigned int broadcast:3; |
43234a1e L |
786 | unsigned int staticrounding:1; |
787 | unsigned int sae:1; | |
788 | unsigned int disp8memshift:3; | |
4fc85f37 | 789 | unsigned int vsz:3; |
b6f8c7c4 | 790 | unsigned int optimize:1; |
1efbbeb4 | 791 | unsigned int attmnemonic:1; |
e1d4d893 | 792 | unsigned int attsyntax:1; |
5c07affc | 793 | unsigned int intelsyntax:1; |
4b5aaf5f | 794 | unsigned int isa64:2; |
40fb9820 L |
795 | } i386_opcode_modifier; |
796 | ||
bab6aec1 JB |
797 | /* Operand classes. */ |
798 | ||
799 | #define CLASS_WIDTH 4 | |
800 | enum operand_class | |
801 | { | |
802 | ClassNone, | |
803 | Reg, /* GPRs and FP regs, distinguished by operand size */ | |
00cee14f | 804 | SReg, /* Segment register */ |
4a5c67ed JB |
805 | RegCR, /* Control register */ |
806 | RegDR, /* Debug register */ | |
807 | RegTR, /* Test register */ | |
3528c362 JB |
808 | RegMMX, /* MMX register */ |
809 | RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ | |
f74a6307 JB |
810 | RegMask, /* Vector Mask register */ |
811 | RegBND, /* Bound register */ | |
bab6aec1 JB |
812 | }; |
813 | ||
75e5731b JB |
814 | /* Special operand instances. */ |
815 | ||
816 | #define INSTANCE_WIDTH 3 | |
817 | enum operand_instance | |
818 | { | |
819 | InstanceNone, | |
820 | Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ | |
474da251 JB |
821 | RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ |
822 | RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ | |
823 | RegB, /* %bl / %bx / %ebx / %rbx */ | |
75e5731b JB |
824 | }; |
825 | ||
40fb9820 L |
826 | /* Position of operand_type bits. */ |
827 | ||
52a6c1fe L |
828 | enum |
829 | { | |
75e5731b JB |
830 | /* Class and Instance */ |
831 | ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, | |
52a6c1fe L |
832 | /* 1 bit immediate */ |
833 | Imm1, | |
834 | /* 8 bit immediate */ | |
835 | Imm8, | |
836 | /* 8 bit immediate sign extended */ | |
837 | Imm8S, | |
838 | /* 16 bit immediate */ | |
839 | Imm16, | |
840 | /* 32 bit immediate */ | |
841 | Imm32, | |
842 | /* 32 bit immediate sign extended */ | |
843 | Imm32S, | |
844 | /* 64 bit immediate */ | |
845 | Imm64, | |
846 | /* 8bit/16bit/32bit displacements are used in different ways, | |
847 | depending on the instruction. For jumps, they specify the | |
848 | size of the PC relative displacement, for instructions with | |
849 | memory operand, they specify the size of the offset relative | |
850 | to the base register, and for instructions with memory offset | |
851 | such as `mov 1234,%al' they specify the size of the offset | |
852 | relative to the segment base. */ | |
853 | /* 8 bit displacement */ | |
854 | Disp8, | |
855 | /* 16 bit displacement */ | |
856 | Disp16, | |
a775efc8 | 857 | /* 32 bit displacement (64-bit: sign-extended) */ |
52a6c1fe | 858 | Disp32, |
52a6c1fe L |
859 | /* 64 bit displacement */ |
860 | Disp64, | |
52a6c1fe L |
861 | /* Register which can be used for base or index in memory operand. */ |
862 | BaseIndex, | |
11a322db | 863 | /* BYTE size. */ |
52a6c1fe | 864 | Byte, |
11a322db | 865 | /* WORD size. 2 byte */ |
52a6c1fe | 866 | Word, |
11a322db | 867 | /* DWORD size. 4 byte */ |
52a6c1fe | 868 | Dword, |
11a322db | 869 | /* FWORD size. 6 byte */ |
52a6c1fe | 870 | Fword, |
11a322db | 871 | /* QWORD size. 8 byte */ |
52a6c1fe | 872 | Qword, |
11a322db | 873 | /* TBYTE size. 10 byte */ |
52a6c1fe | 874 | Tbyte, |
11a322db | 875 | /* XMMWORD size. */ |
52a6c1fe | 876 | Xmmword, |
11a322db | 877 | /* YMMWORD size. */ |
52a6c1fe | 878 | Ymmword, |
11a322db | 879 | /* ZMMWORD size. */ |
43234a1e | 880 | Zmmword, |
260cd341 LC |
881 | /* TMMWORD size. */ |
882 | Tmmword, | |
52a6c1fe L |
883 | /* Unspecified memory size. */ |
884 | Unspecified, | |
40fb9820 | 885 | |
bab6aec1 | 886 | /* The number of bits in i386_operand_type. */ |
f0a85b07 | 887 | OTNum |
52a6c1fe | 888 | }; |
40fb9820 L |
889 | |
890 | #define OTNumOfUints \ | |
f0a85b07 | 891 | ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) |
40fb9820 L |
892 | #define OTNumOfBits \ |
893 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
894 | ||
895 | /* If you get a compiler error for zero width of the unused field, | |
601e8564 | 896 | comment it out. */ |
f0a85b07 | 897 | #define OTUnused OTNum |
40fb9820 L |
898 | |
899 | typedef union i386_operand_type | |
900 | { | |
901 | struct | |
902 | { | |
bab6aec1 | 903 | unsigned int class:CLASS_WIDTH; |
75e5731b | 904 | unsigned int instance:INSTANCE_WIDTH; |
7d5e4556 | 905 | unsigned int imm1:1; |
40fb9820 L |
906 | unsigned int imm8:1; |
907 | unsigned int imm8s:1; | |
908 | unsigned int imm16:1; | |
909 | unsigned int imm32:1; | |
910 | unsigned int imm32s:1; | |
911 | unsigned int imm64:1; | |
40fb9820 L |
912 | unsigned int disp8:1; |
913 | unsigned int disp16:1; | |
914 | unsigned int disp32:1; | |
40fb9820 | 915 | unsigned int disp64:1; |
7d5e4556 | 916 | unsigned int baseindex:1; |
7d5e4556 L |
917 | unsigned int byte:1; |
918 | unsigned int word:1; | |
919 | unsigned int dword:1; | |
920 | unsigned int fword:1; | |
921 | unsigned int qword:1; | |
922 | unsigned int tbyte:1; | |
923 | unsigned int xmmword:1; | |
c0f3af97 | 924 | unsigned int ymmword:1; |
43234a1e | 925 | unsigned int zmmword:1; |
260cd341 | 926 | unsigned int tmmword:1; |
7d5e4556 | 927 | unsigned int unspecified:1; |
40fb9820 L |
928 | #ifdef OTUnused |
929 | unsigned int unused:(OTNumOfBits - OTUnused); | |
930 | #endif | |
931 | } bitfield; | |
932 | unsigned int array[OTNumOfUints]; | |
933 | } i386_operand_type; | |
0b1cf022 | 934 | |
d3ce72d0 | 935 | typedef struct insn_template |
0b1cf022 L |
936 | { |
937 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
5c139202 | 938 | unsigned int mnem_off; |
0b1cf022 | 939 | |
37cea588 JB |
940 | /* Bitfield arrangement is such that individual fields can be easily |
941 | extracted (in native builds at least) - either by at most a masking | |
942 | operation (base_opcode, operands), or by just a (signed) right shift | |
943 | (extension_opcode). Please try to maintain this property. */ | |
944 | ||
0b1cf022 L |
945 | /* base_opcode is the fundamental opcode byte without optional |
946 | prefix(es). */ | |
9df6f676 | 947 | unsigned int base_opcode:16; |
0b1cf022 L |
948 | #define Opcode_D 0x2 /* Direction bit: |
949 | set if Reg --> Regmem; | |
950 | unset if Regmem --> Reg. */ | |
bd782808 JB |
951 | #define Opcode_FloatR 0x8 /* ModR/M bit to swap src/dest for float insns. */ |
952 | #define Opcode_FloatD 0x4 /* Direction bit for float insns. */ | |
2c735193 | 953 | #define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */ |
dbbc8b7e | 954 | #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ |
8bd915b7 JB |
955 | /* The next value is arbitrary, as long as it's non-zero and distinct |
956 | from all other values above. */ | |
957 | #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */ | |
0b1cf022 | 958 | |
37cea588 JB |
959 | /* how many operands */ |
960 | unsigned int operands:3; | |
961 | ||
ddb62495 JB |
962 | /* opcode space */ |
963 | unsigned int opcode_space:4; | |
964 | /* Opcode encoding space (values chosen to be usable directly in | |
965 | VEX/XOP mmmmm and EVEX mm fields): | |
966 | 0: Base opcode space. | |
967 | 1: 0F opcode prefix / space. | |
968 | 2: 0F38 opcode prefix / space. | |
969 | 3: 0F3A opcode prefix / space. | |
970 | 5: EVEXMAP5 opcode prefix / space. | |
971 | 6: EVEXMAP6 opcode prefix / space. | |
8170af78 | 972 | 7: VEXMAP7 opcode prefix / space. |
ddb62495 JB |
973 | 8: XOP 08 opcode space. |
974 | 9: XOP 09 opcode space. | |
975 | A: XOP 0A opcode space. | |
976 | */ | |
977 | #define SPACE_BASE 0 | |
978 | #define SPACE_0F 1 | |
979 | #define SPACE_0F38 2 | |
980 | #define SPACE_0F3A 3 | |
981 | #define SPACE_EVEXMAP5 5 | |
982 | #define SPACE_EVEXMAP6 6 | |
8170af78 | 983 | #define SPACE_VEXMAP7 7 |
ddb62495 JB |
984 | #define SPACE_XOP08 8 |
985 | #define SPACE_XOP09 9 | |
986 | #define SPACE_XOP0A 0xA | |
37cea588 | 987 | |
31184569 JB |
988 | /* (Fake) base opcode value for pseudo prefixes. */ |
989 | #define PSEUDO_PREFIX 0 | |
990 | ||
991 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
992 | This field is also used to store the 8-bit opcode suffix for the | |
993 | AMD 3DNow! instructions. | |
994 | If this template has no extension opcode (the usual case) use None | |
995 | Instructions */ | |
9df6f676 JB |
996 | signed int extension_opcode:9; |
997 | #define None (-1) /* If no extension_opcode is possible. */ | |
31184569 | 998 | |
41eb8e88 L |
999 | /* Pseudo prefixes. */ |
1000 | #define Prefix_Disp8 0 /* {disp8} */ | |
1001 | #define Prefix_Disp16 1 /* {disp16} */ | |
1002 | #define Prefix_Disp32 2 /* {disp32} */ | |
1003 | #define Prefix_Load 3 /* {load} */ | |
1004 | #define Prefix_Store 4 /* {store} */ | |
1005 | #define Prefix_VEX 5 /* {vex} */ | |
1006 | #define Prefix_VEX3 6 /* {vex3} */ | |
1007 | #define Prefix_EVEX 7 /* {evex} */ | |
1008 | #define Prefix_REX 8 /* {rex} */ | |
1009 | #define Prefix_NoOptimize 9 /* {nooptimize} */ | |
1010 | ||
0b1cf022 L |
1011 | /* the bits in opcode_modifier are used to generate the final opcode from |
1012 | the base_opcode. These bits also are used to detect alternate forms of | |
1013 | the same instruction */ | |
40fb9820 | 1014 | i386_opcode_modifier opcode_modifier; |
0b1cf022 | 1015 | |
734dfd1c | 1016 | /* cpu feature attributes */ |
a5e91879 | 1017 | i386_cpu_attr cpu, cpu_any; |
dac10fb0 | 1018 | |
0b1cf022 L |
1019 | /* operand_types[i] describes the type of operand i. This is made |
1020 | by OR'ing together all of the possible type masks. (e.g. | |
1021 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
1022 | either a register or an immediate operand. */ | |
40fb9820 | 1023 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 | 1024 | } |
d3ce72d0 | 1025 | insn_template; |
0b1cf022 | 1026 | |
0b1cf022 L |
1027 | /* these are for register name --> number & type hash lookup */ |
1028 | typedef struct | |
1029 | { | |
edf77258 | 1030 | char reg_name[8]; |
40fb9820 | 1031 | i386_operand_type reg_type; |
a60de03c | 1032 | unsigned char reg_flags; |
0b1cf022 L |
1033 | #define RegRex 0x1 /* Extended register. */ |
1034 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
43234a1e | 1035 | #define RegVRex 0x4 /* Extended vector register. */ |
a60de03c | 1036 | unsigned char reg_num; |
e968fc9b | 1037 | #define RegIP ((unsigned char ) ~0) |
db51cc60 | 1038 | /* EIZ and RIZ are fake index registers. */ |
e968fc9b | 1039 | #define RegIZ (RegIP - 1) |
b7240065 JB |
1040 | /* FLAT is a fake segment register (Intel mode). */ |
1041 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
1042 | signed char dw2_regnum[2]; |
1043 | #define Dw2Inval (-1) | |
0b1cf022 L |
1044 | } |
1045 | reg_entry; |