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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
d87bef3a | 2 | Copyright (C) 2007-2023 Free Software Foundation, Inc. |
0b1cf022 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
0b1cf022 | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
9 | any later version. |
10 | ||
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
0b1cf022 L |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | 02110-1301, USA. */ | |
20 | ||
21 | #include "opcode/i386.h" | |
40fb9820 | 22 | #include <limits.h> |
40fb9820 L |
23 | #ifndef CHAR_BIT |
24 | #define CHAR_BIT 8 | |
25 | #endif | |
26 | ||
27 | /* Position of cpu flags bitfiled. */ | |
28 | ||
52a6c1fe L |
29 | enum |
30 | { | |
31 | /* i186 or better required */ | |
32 | Cpu186 = 0, | |
33 | /* i286 or better required */ | |
34 | Cpu286, | |
35 | /* i386 or better required */ | |
36 | Cpu386, | |
37 | /* i486 or better required */ | |
38 | Cpu486, | |
39 | /* i585 or better required */ | |
40 | Cpu586, | |
41 | /* i686 or better required */ | |
42 | Cpu686, | |
d871f3f4 L |
43 | /* CMOV Instruction support required */ |
44 | CpuCMOV, | |
45 | /* FXSR Instruction support required */ | |
46 | CpuFXSR, | |
b49dfb4a | 47 | /* CLFLUSH Instruction support required */ |
52a6c1fe | 48 | CpuClflush, |
22109423 L |
49 | /* NOP Instruction support required */ |
50 | CpuNop, | |
b49dfb4a | 51 | /* SYSCALL Instructions support required */ |
52a6c1fe L |
52 | CpuSYSCALL, |
53 | /* Floating point support required */ | |
54 | Cpu8087, | |
55 | /* i287 support required */ | |
56 | Cpu287, | |
57 | /* i387 support required */ | |
58 | Cpu387, | |
59 | /* i686 and floating point support required */ | |
60 | Cpu687, | |
61 | /* SSE3 and floating point support required */ | |
62 | CpuFISTTP, | |
63 | /* MMX support required */ | |
64 | CpuMMX, | |
65 | /* SSE support required */ | |
66 | CpuSSE, | |
67 | /* SSE2 support required */ | |
68 | CpuSSE2, | |
69 | /* 3dnow! support required */ | |
70 | Cpu3dnow, | |
71 | /* 3dnow! Extensions support required */ | |
72 | Cpu3dnowA, | |
73 | /* SSE3 support required */ | |
74 | CpuSSE3, | |
75 | /* VIA PadLock required */ | |
76 | CpuPadLock, | |
77 | /* AMD Secure Virtual Machine Ext-s required */ | |
78 | CpuSVME, | |
79 | /* VMX Instructions required */ | |
80 | CpuVMX, | |
81 | /* SMX Instructions required */ | |
82 | CpuSMX, | |
83 | /* SSSE3 support required */ | |
84 | CpuSSSE3, | |
85 | /* SSE4a support required */ | |
86 | CpuSSE4a, | |
272a84b1 L |
87 | /* LZCNT support required */ |
88 | CpuLZCNT, | |
89 | /* POPCNT support required */ | |
90 | CpuPOPCNT, | |
52a6c1fe L |
91 | /* SSE4.1 support required */ |
92 | CpuSSE4_1, | |
93 | /* SSE4.2 support required */ | |
94 | CpuSSE4_2, | |
95 | /* AVX support required */ | |
96 | CpuAVX, | |
6c30d220 L |
97 | /* AVX2 support required */ |
98 | CpuAVX2, | |
43234a1e L |
99 | /* Intel AVX-512 Foundation Instructions support required */ |
100 | CpuAVX512F, | |
101 | /* Intel AVX-512 Conflict Detection Instructions support required */ | |
102 | CpuAVX512CD, | |
103 | /* Intel AVX-512 Exponential and Reciprocal Instructions support | |
104 | required */ | |
105 | CpuAVX512ER, | |
106 | /* Intel AVX-512 Prefetch Instructions support required */ | |
107 | CpuAVX512PF, | |
b28d1bda IT |
108 | /* Intel AVX-512 VL Instructions support required. */ |
109 | CpuAVX512VL, | |
90a915bf IT |
110 | /* Intel AVX-512 DQ Instructions support required. */ |
111 | CpuAVX512DQ, | |
1ba585e8 IT |
112 | /* Intel AVX-512 BW Instructions support required. */ |
113 | CpuAVX512BW, | |
7b6d09fb L |
114 | /* Intel IAMCU support required */ |
115 | CpuIAMCU, | |
b49dfb4a | 116 | /* Xsave/xrstor New Instructions support required */ |
52a6c1fe | 117 | CpuXsave, |
b49dfb4a | 118 | /* Xsaveopt New Instructions support required */ |
c7b8aa3a | 119 | CpuXsaveopt, |
52a6c1fe L |
120 | /* AES support required */ |
121 | CpuAES, | |
122 | /* PCLMUL support required */ | |
123 | CpuPCLMUL, | |
124 | /* FMA support required */ | |
125 | CpuFMA, | |
126 | /* FMA4 support required */ | |
127 | CpuFMA4, | |
5dd85c99 SP |
128 | /* XOP support required */ |
129 | CpuXOP, | |
f88c9eb0 SP |
130 | /* LWP support required */ |
131 | CpuLWP, | |
f12dc422 L |
132 | /* BMI support required */ |
133 | CpuBMI, | |
2a2a0f38 QN |
134 | /* TBM support required */ |
135 | CpuTBM, | |
b49dfb4a | 136 | /* MOVBE Instruction support required */ |
52a6c1fe | 137 | CpuMovbe, |
60aa667e L |
138 | /* CMPXCHG16B instruction support required. */ |
139 | CpuCX16, | |
52a6c1fe L |
140 | /* EPT Instructions required */ |
141 | CpuEPT, | |
b49dfb4a | 142 | /* RDTSCP Instruction support required */ |
52a6c1fe | 143 | CpuRdtscp, |
77321f53 | 144 | /* FSGSBASE Instructions required */ |
c7b8aa3a L |
145 | CpuFSGSBase, |
146 | /* RDRND Instructions required */ | |
147 | CpuRdRnd, | |
148 | /* F16C Instructions required */ | |
149 | CpuF16C, | |
6c30d220 L |
150 | /* Intel BMI2 support required */ |
151 | CpuBMI2, | |
42164a71 L |
152 | /* HLE support required */ |
153 | CpuHLE, | |
154 | /* RTM support required */ | |
155 | CpuRTM, | |
6c30d220 L |
156 | /* INVPCID Instructions required */ |
157 | CpuINVPCID, | |
8729a6f6 L |
158 | /* VMFUNC Instruction required */ |
159 | CpuVMFUNC, | |
7e8b059b L |
160 | /* Intel MPX Instructions required */ |
161 | CpuMPX, | |
52a6c1fe L |
162 | /* 64bit support available, used by -march= in assembler. */ |
163 | CpuLM, | |
e2e1fcde L |
164 | /* RDRSEED instruction required. */ |
165 | CpuRDSEED, | |
166 | /* Multi-presisionn add-carry instructions are required. */ | |
167 | CpuADX, | |
7b458c12 | 168 | /* Supports prefetchw and prefetch instructions. */ |
e2e1fcde | 169 | CpuPRFCHW, |
5c111e37 L |
170 | /* SMAP instructions required. */ |
171 | CpuSMAP, | |
a0046408 L |
172 | /* SHA instructions required. */ |
173 | CpuSHA, | |
963f3586 IT |
174 | /* CLFLUSHOPT instruction required */ |
175 | CpuClflushOpt, | |
176 | /* XSAVES/XRSTORS instruction required */ | |
177 | CpuXSAVES, | |
178 | /* XSAVEC instruction required */ | |
179 | CpuXSAVEC, | |
dcf893b5 IT |
180 | /* PREFETCHWT1 instruction required */ |
181 | CpuPREFETCHWT1, | |
2cf200a4 IT |
182 | /* SE1 instruction required */ |
183 | CpuSE1, | |
c5e7287a IT |
184 | /* CLWB instruction required */ |
185 | CpuCLWB, | |
2cc1b5aa IT |
186 | /* Intel AVX-512 IFMA Instructions support required. */ |
187 | CpuAVX512IFMA, | |
14f195c9 IT |
188 | /* Intel AVX-512 VBMI Instructions support required. */ |
189 | CpuAVX512VBMI, | |
920d2ddc IT |
190 | /* Intel AVX-512 4FMAPS Instructions support required. */ |
191 | CpuAVX512_4FMAPS, | |
47acf0bd IT |
192 | /* Intel AVX-512 4VNNIW Instructions support required. */ |
193 | CpuAVX512_4VNNIW, | |
620214f7 IT |
194 | /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ |
195 | CpuAVX512_VPOPCNTDQ, | |
53467f57 IT |
196 | /* Intel AVX-512 VBMI2 Instructions support required. */ |
197 | CpuAVX512_VBMI2, | |
8cfcb765 IT |
198 | /* Intel AVX-512 VNNI Instructions support required. */ |
199 | CpuAVX512_VNNI, | |
ee6872be IT |
200 | /* Intel AVX-512 BITALG Instructions support required. */ |
201 | CpuAVX512_BITALG, | |
d6aab7a1 XG |
202 | /* Intel AVX-512 BF16 Instructions support required. */ |
203 | CpuAVX512_BF16, | |
9186c494 L |
204 | /* Intel AVX-512 VP2INTERSECT Instructions support required. */ |
205 | CpuAVX512_VP2INTERSECT, | |
81d54bb7 CL |
206 | /* TDX Instructions support required. */ |
207 | CpuTDX, | |
58bf9b6a L |
208 | /* Intel AVX VNNI Instructions support required. */ |
209 | CpuAVX_VNNI, | |
0cc78721 CL |
210 | /* Intel AVX-512 FP16 Instructions support required. */ |
211 | CpuAVX512_FP16, | |
ef07be45 CL |
212 | /* PREFETCHI instruction required */ |
213 | CpuPREFETCHI, | |
4321af3e HW |
214 | /* Intel AVX IFMA Instructions support required. */ |
215 | CpuAVX_IFMA, | |
23ae61ad CL |
216 | /* Intel AVX VNNI-INT8 Instructions support required. */ |
217 | CpuAVX_VNNI_INT8, | |
a93e3234 HJ |
218 | /* Intel CMPccXADD instructions support required. */ |
219 | CpuCMPCCXADD, | |
941f0833 HL |
220 | /* Intel WRMSRNS Instructions support required */ |
221 | CpuWRMSRNS, | |
2188d6ea HL |
222 | /* Intel MSRLIST Instructions support required. */ |
223 | CpuMSRLIST, | |
01d8ce74 | 224 | /* Intel AVX NE CONVERT Instructions support required. */ |
225 | CpuAVX_NE_CONVERT, | |
b06311ad KL |
226 | /* Intel RAO INT Instructions support required. */ |
227 | CpuRAO_INT, | |
9916071f AP |
228 | /* mwaitx instruction required */ |
229 | CpuMWAITX, | |
43e65147 | 230 | /* Clzero instruction required */ |
029f3522 | 231 | CpuCLZERO, |
8eab4136 L |
232 | /* OSPKE instruction required */ |
233 | CpuOSPKE, | |
8bc52696 AF |
234 | /* RDPID instruction required */ |
235 | CpuRDPID, | |
6b40c462 L |
236 | /* PTWRITE instruction required */ |
237 | CpuPTWRITE, | |
d777820b IT |
238 | /* CET instructions support required */ |
239 | CpuIBT, | |
240 | CpuSHSTK, | |
260cd341 LC |
241 | /* AMX-INT8 instructions required */ |
242 | CpuAMX_INT8, | |
243 | /* AMX-BF16 instructions required */ | |
244 | CpuAMX_BF16, | |
68830fba CL |
245 | /* AMX-FP16 instructions required */ |
246 | CpuAMX_FP16, | |
260cd341 LC |
247 | /* AMX-TILE instructions required */ |
248 | CpuAMX_TILE, | |
48521003 IT |
249 | /* GFNI instructions required */ |
250 | CpuGFNI, | |
8dcf1fad IT |
251 | /* VAES instructions required */ |
252 | CpuVAES, | |
ff1982d5 IT |
253 | /* VPCLMULQDQ instructions required */ |
254 | CpuVPCLMULQDQ, | |
3233d7d0 IT |
255 | /* WBNOINVD instructions required */ |
256 | CpuWBNOINVD, | |
be3a8dca IT |
257 | /* PCONFIG instructions required */ |
258 | CpuPCONFIG, | |
de89d0a3 IT |
259 | /* WAITPKG instructions required */ |
260 | CpuWAITPKG, | |
f64c42a9 LC |
261 | /* UINTR instructions required */ |
262 | CpuUINTR, | |
c48935d7 IT |
263 | /* CLDEMOTE instruction required */ |
264 | CpuCLDEMOTE, | |
c0a30a9f L |
265 | /* MOVDIRI instruction support required */ |
266 | CpuMOVDIRI, | |
267 | /* MOVDIRR64B instruction required */ | |
268 | CpuMOVDIR64B, | |
5d79adc4 L |
269 | /* ENQCMD instruction required */ |
270 | CpuENQCMD, | |
4b27d27c L |
271 | /* SERIALIZE instruction required */ |
272 | CpuSERIALIZE, | |
142861df JB |
273 | /* RDPRU instruction required */ |
274 | CpuRDPRU, | |
275 | /* MCOMMIT instruction required */ | |
276 | CpuMCOMMIT, | |
a847e322 JB |
277 | /* SEV-ES instruction(s) required */ |
278 | CpuSEV_ES, | |
bb651e8b CL |
279 | /* TSXLDTRK instruction required */ |
280 | CpuTSXLDTRK, | |
c4694f17 TG |
281 | /* KL instruction support required */ |
282 | CpuKL, | |
283 | /* WideKL instruction support required */ | |
284 | CpuWideKL, | |
c1fa250a LC |
285 | /* HRESET instruction required */ |
286 | CpuHRESET, | |
646cc3e0 GG |
287 | /* INVLPGB instructions required */ |
288 | CpuINVLPGB, | |
289 | /* TLBSYNC instructions required */ | |
290 | CpuTLBSYNC, | |
291 | /* SNP instructions required */ | |
292 | CpuSNP, | |
b0e8fa7f TJ |
293 | /* RMPQUERY instruction required */ |
294 | CpuRMPQUERY, | |
13ed231a JB |
295 | |
296 | /* NOTE: These last three items need to remain last and in this order. */ | |
297 | ||
52a6c1fe L |
298 | /* 64bit support required */ |
299 | Cpu64, | |
300 | /* Not supported in the 64bit mode */ | |
301 | CpuNo64, | |
302 | /* The last bitfield in i386_cpu_flags. */ | |
e92bae62 | 303 | CpuMax = CpuNo64 |
52a6c1fe | 304 | }; |
40fb9820 L |
305 | |
306 | #define CpuNumOfUints \ | |
307 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
308 | #define CpuNumOfBits \ | |
309 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
310 | ||
311 | /* If you get a compiler error for zero width of the unused field, | |
312 | comment it out. */ | |
a93e3234 | 313 | #define CpuUnused (CpuMax + 1) |
53467f57 | 314 | |
40fb9820 L |
315 | /* We can check if an instruction is available with array instead |
316 | of bitfield. */ | |
317 | typedef union i386_cpu_flags | |
318 | { | |
319 | struct | |
320 | { | |
321 | unsigned int cpui186:1; | |
322 | unsigned int cpui286:1; | |
323 | unsigned int cpui386:1; | |
324 | unsigned int cpui486:1; | |
325 | unsigned int cpui586:1; | |
326 | unsigned int cpui686:1; | |
d871f3f4 L |
327 | unsigned int cpucmov:1; |
328 | unsigned int cpufxsr:1; | |
bd5295b2 | 329 | unsigned int cpuclflush:1; |
22109423 | 330 | unsigned int cpunop:1; |
bd5295b2 | 331 | unsigned int cpusyscall:1; |
309d3373 JB |
332 | unsigned int cpu8087:1; |
333 | unsigned int cpu287:1; | |
334 | unsigned int cpu387:1; | |
335 | unsigned int cpu687:1; | |
336 | unsigned int cpufisttp:1; | |
40fb9820 | 337 | unsigned int cpummx:1; |
40fb9820 L |
338 | unsigned int cpusse:1; |
339 | unsigned int cpusse2:1; | |
340 | unsigned int cpua3dnow:1; | |
341 | unsigned int cpua3dnowa:1; | |
342 | unsigned int cpusse3:1; | |
343 | unsigned int cpupadlock:1; | |
344 | unsigned int cpusvme:1; | |
345 | unsigned int cpuvmx:1; | |
47dd174c | 346 | unsigned int cpusmx:1; |
40fb9820 L |
347 | unsigned int cpussse3:1; |
348 | unsigned int cpusse4a:1; | |
272a84b1 L |
349 | unsigned int cpulzcnt:1; |
350 | unsigned int cpupopcnt:1; | |
40fb9820 L |
351 | unsigned int cpusse4_1:1; |
352 | unsigned int cpusse4_2:1; | |
c0f3af97 | 353 | unsigned int cpuavx:1; |
6c30d220 | 354 | unsigned int cpuavx2:1; |
43234a1e L |
355 | unsigned int cpuavx512f:1; |
356 | unsigned int cpuavx512cd:1; | |
357 | unsigned int cpuavx512er:1; | |
358 | unsigned int cpuavx512pf:1; | |
b28d1bda | 359 | unsigned int cpuavx512vl:1; |
90a915bf | 360 | unsigned int cpuavx512dq:1; |
1ba585e8 | 361 | unsigned int cpuavx512bw:1; |
7b6d09fb | 362 | unsigned int cpuiamcu:1; |
475a2301 | 363 | unsigned int cpuxsave:1; |
c7b8aa3a | 364 | unsigned int cpuxsaveopt:1; |
c0f3af97 | 365 | unsigned int cpuaes:1; |
594ab6a3 | 366 | unsigned int cpupclmul:1; |
c0f3af97 | 367 | unsigned int cpufma:1; |
922d8de8 | 368 | unsigned int cpufma4:1; |
5dd85c99 | 369 | unsigned int cpuxop:1; |
f88c9eb0 | 370 | unsigned int cpulwp:1; |
f12dc422 | 371 | unsigned int cpubmi:1; |
2a2a0f38 | 372 | unsigned int cputbm:1; |
f1f8f695 | 373 | unsigned int cpumovbe:1; |
60aa667e | 374 | unsigned int cpucx16:1; |
f1f8f695 | 375 | unsigned int cpuept:1; |
1b7f3fb0 | 376 | unsigned int cpurdtscp:1; |
c7b8aa3a L |
377 | unsigned int cpufsgsbase:1; |
378 | unsigned int cpurdrnd:1; | |
379 | unsigned int cpuf16c:1; | |
6c30d220 | 380 | unsigned int cpubmi2:1; |
42164a71 L |
381 | unsigned int cpuhle:1; |
382 | unsigned int cpurtm:1; | |
6c30d220 | 383 | unsigned int cpuinvpcid:1; |
8729a6f6 | 384 | unsigned int cpuvmfunc:1; |
7e8b059b | 385 | unsigned int cpumpx:1; |
40fb9820 | 386 | unsigned int cpulm:1; |
e2e1fcde L |
387 | unsigned int cpurdseed:1; |
388 | unsigned int cpuadx:1; | |
389 | unsigned int cpuprfchw:1; | |
5c111e37 | 390 | unsigned int cpusmap:1; |
a0046408 | 391 | unsigned int cpusha:1; |
963f3586 IT |
392 | unsigned int cpuclflushopt:1; |
393 | unsigned int cpuxsaves:1; | |
394 | unsigned int cpuxsavec:1; | |
dcf893b5 | 395 | unsigned int cpuprefetchwt1:1; |
2cf200a4 | 396 | unsigned int cpuse1:1; |
c5e7287a | 397 | unsigned int cpuclwb:1; |
2cc1b5aa | 398 | unsigned int cpuavx512ifma:1; |
14f195c9 | 399 | unsigned int cpuavx512vbmi:1; |
920d2ddc | 400 | unsigned int cpuavx512_4fmaps:1; |
47acf0bd | 401 | unsigned int cpuavx512_4vnniw:1; |
620214f7 | 402 | unsigned int cpuavx512_vpopcntdq:1; |
53467f57 | 403 | unsigned int cpuavx512_vbmi2:1; |
8cfcb765 | 404 | unsigned int cpuavx512_vnni:1; |
ee6872be | 405 | unsigned int cpuavx512_bitalg:1; |
d6aab7a1 | 406 | unsigned int cpuavx512_bf16:1; |
9186c494 | 407 | unsigned int cpuavx512_vp2intersect:1; |
81d54bb7 | 408 | unsigned int cputdx:1; |
58bf9b6a | 409 | unsigned int cpuavx_vnni:1; |
0cc78721 | 410 | unsigned int cpuavx512_fp16:1; |
ef07be45 | 411 | unsigned int cpuprefetchi:1; |
4321af3e | 412 | unsigned int cpuavx_ifma:1; |
23ae61ad | 413 | unsigned int cpuavx_vnni_int8:1; |
a93e3234 | 414 | unsigned int cpucmpccxadd:1; |
941f0833 | 415 | unsigned int cpuwrmsrns:1; |
2188d6ea | 416 | unsigned int cpumsrlist:1; |
01d8ce74 | 417 | unsigned int cpuavx_ne_convert:1; |
b06311ad | 418 | unsigned int cpurao_int:1; |
9916071f | 419 | unsigned int cpumwaitx:1; |
029f3522 | 420 | unsigned int cpuclzero:1; |
8eab4136 | 421 | unsigned int cpuospke:1; |
8bc52696 | 422 | unsigned int cpurdpid:1; |
6b40c462 | 423 | unsigned int cpuptwrite:1; |
d777820b IT |
424 | unsigned int cpuibt:1; |
425 | unsigned int cpushstk:1; | |
260cd341 LC |
426 | unsigned int cpuamx_int8:1; |
427 | unsigned int cpuamx_bf16:1; | |
68830fba | 428 | unsigned int cpuamx_fp16:1; |
260cd341 | 429 | unsigned int cpuamx_tile:1; |
48521003 | 430 | unsigned int cpugfni:1; |
8dcf1fad | 431 | unsigned int cpuvaes:1; |
ff1982d5 | 432 | unsigned int cpuvpclmulqdq:1; |
3233d7d0 | 433 | unsigned int cpuwbnoinvd:1; |
be3a8dca | 434 | unsigned int cpupconfig:1; |
de89d0a3 | 435 | unsigned int cpuwaitpkg:1; |
f64c42a9 | 436 | unsigned int cpuuintr:1; |
c48935d7 | 437 | unsigned int cpucldemote:1; |
c0a30a9f L |
438 | unsigned int cpumovdiri:1; |
439 | unsigned int cpumovdir64b:1; | |
5d79adc4 | 440 | unsigned int cpuenqcmd:1; |
4b27d27c | 441 | unsigned int cpuserialize:1; |
142861df JB |
442 | unsigned int cpurdpru:1; |
443 | unsigned int cpumcommit:1; | |
a847e322 | 444 | unsigned int cpusev_es:1; |
bb651e8b | 445 | unsigned int cputsxldtrk:1; |
c4694f17 TG |
446 | unsigned int cpukl:1; |
447 | unsigned int cpuwidekl:1; | |
c1fa250a | 448 | unsigned int cpuhreset:1; |
646cc3e0 GG |
449 | unsigned int cpuinvlpgb:1; |
450 | unsigned int cputlbsync:1; | |
451 | unsigned int cpusnp:1; | |
b0e8fa7f | 452 | unsigned int cpurmpquery:1; |
13ed231a | 453 | /* NOTE: These last three fields need to remain last and in this order. */ |
40fb9820 L |
454 | unsigned int cpu64:1; |
455 | unsigned int cpuno64:1; | |
456 | #ifdef CpuUnused | |
457 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
458 | #endif | |
459 | } bitfield; | |
460 | unsigned int array[CpuNumOfUints]; | |
461 | } i386_cpu_flags; | |
462 | ||
463 | /* Position of opcode_modifier bits. */ | |
464 | ||
52a6c1fe L |
465 | enum |
466 | { | |
467 | /* has direction bit. */ | |
468 | D = 0, | |
507916b8 JB |
469 | /* set if operands can be both bytes and words/dwords/qwords, encoded the |
470 | canonical way; the base_opcode field should hold the encoding for byte | |
471 | operands */ | |
52a6c1fe | 472 | W, |
86fa6981 L |
473 | /* load form instruction. Must be placed before store form. */ |
474 | Load, | |
52a6c1fe L |
475 | /* insn has a modrm byte. */ |
476 | Modrm, | |
0cfa3eb3 JB |
477 | /* special case for jump insns; value has to be 1 */ |
478 | #define JUMP 1 | |
52a6c1fe | 479 | /* call and jump */ |
0cfa3eb3 | 480 | #define JUMP_DWORD 2 |
52a6c1fe | 481 | /* loop and jecxz */ |
0cfa3eb3 | 482 | #define JUMP_BYTE 3 |
52a6c1fe | 483 | /* special case for intersegment leaps/calls */ |
0cfa3eb3 | 484 | #define JUMP_INTERSEGMENT 4 |
6f2f06be | 485 | /* absolute address for jump */ |
0cfa3eb3 JB |
486 | #define JUMP_ABSOLUTE 5 |
487 | Jump, | |
52a6c1fe L |
488 | /* FP insn memory format bit, sized by 0x4 */ |
489 | FloatMF, | |
52a6c1fe | 490 | /* needs size prefix if in 32-bit mode */ |
673fe0f0 | 491 | #define SIZE16 1 |
52a6c1fe | 492 | /* needs size prefix if in 16-bit mode */ |
673fe0f0 | 493 | #define SIZE32 2 |
52a6c1fe | 494 | /* needs size prefix if in 64-bit mode */ |
673fe0f0 JB |
495 | #define SIZE64 3 |
496 | Size, | |
9c19e9ec JB |
497 | /* Check that operand sizes match. */ |
498 | CheckOperandSize, | |
255571cd JB |
499 | /* any memory size */ |
500 | #define ANY_SIZE 1 | |
501 | /* fake an extra reg operand for clr, imul and special register | |
502 | processing for some instructions. */ | |
503 | #define REG_KLUDGE 2 | |
504 | /* deprecated fp insn, gets a warning */ | |
505 | #define UGH 3 | |
506 | /* An implicit xmm0 as the first operand */ | |
507 | #define IMPLICIT_1ST_XMM0 4 | |
508 | /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. | |
509 | It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). | |
510 | */ | |
511 | #define IMPLICIT_QUAD_GROUP 5 | |
512 | /* Two source operands are swapped. */ | |
513 | #define SWAP_SOURCES 6 | |
514 | /* Default mask isn't allowed. */ | |
515 | #define NO_DEFAULT_MASK 7 | |
516 | /* Address prefix changes register operand */ | |
517 | #define ADDR_PREFIX_OP_REG 8 | |
0cc78721 CL |
518 | /* Instrucion requires that destination must be distinct from source |
519 | registers. */ | |
255571cd JB |
520 | #define DISTINCT_DEST 9 |
521 | OperandConstraint, | |
52a6c1fe L |
522 | /* instruction ignores operand size prefix and in Intel mode ignores |
523 | mnemonic size suffix check. */ | |
3cd7f3e3 | 524 | #define IGNORESIZE 1 |
52a6c1fe | 525 | /* default insn size depends on mode */ |
3cd7f3e3 L |
526 | #define DEFAULTSIZE 2 |
527 | MnemonicSize, | |
52a6c1fe L |
528 | /* b suffix on instruction illegal */ |
529 | No_bSuf, | |
530 | /* w suffix on instruction illegal */ | |
531 | No_wSuf, | |
532 | /* l suffix on instruction illegal */ | |
533 | No_lSuf, | |
534 | /* s suffix on instruction illegal */ | |
535 | No_sSuf, | |
536 | /* q suffix on instruction illegal */ | |
537 | No_qSuf, | |
52a6c1fe L |
538 | /* instruction needs FWAIT */ |
539 | FWait, | |
51c8edf6 JB |
540 | /* IsString provides for a quick test for string instructions, and |
541 | its actual value also indicates which of the operands (if any) | |
542 | requires use of the %es segment. */ | |
543 | #define IS_STRING_ES_OP0 2 | |
544 | #define IS_STRING_ES_OP1 3 | |
52a6c1fe | 545 | IsString, |
dfd69174 JB |
546 | /* RegMem is for instructions with a modrm byte where the register |
547 | destination operand should be encoded in the mod and regmem fields. | |
548 | Normally, it will be encoded in the reg field. We add a RegMem | |
549 | flag to indicate that it should be encoded in the regmem field. */ | |
550 | RegMem, | |
7e8b059b L |
551 | /* quick test if branch instruction is MPX supported */ |
552 | BNDPrefixOk, | |
742732c7 JB |
553 | #define PrefixNone 0 |
554 | #define PrefixRep 1 | |
555 | #define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */ | |
556 | #define PrefixNoTrack 3 | |
557 | /* Prefixes implying "LOCK okay" must come after Lock. All others have | |
558 | to come before. */ | |
559 | #define PrefixLock 4 | |
560 | #define PrefixHLELock 5 /* Okay with a LOCK prefix. */ | |
561 | #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */ | |
562 | PrefixOk, | |
52a6c1fe L |
563 | /* opcode is a prefix */ |
564 | IsPrefix, | |
565 | /* instruction has extension in 8 bit imm */ | |
566 | ImmExt, | |
567 | /* instruction don't need Rex64 prefix. */ | |
568 | NoRex64, | |
52a6c1fe | 569 | /* insn has VEX prefix: |
10c17abd | 570 | 1: 128bit VEX prefix (or operand dependent). |
2bf05e57 | 571 | 2: 256bit VEX prefix. |
712366da | 572 | 3: Scalar VEX prefix. |
52a6c1fe | 573 | */ |
712366da L |
574 | #define VEX128 1 |
575 | #define VEX256 2 | |
576 | #define VEXScalar 3 | |
52a6c1fe | 577 | Vex, |
2426c15f L |
578 | /* How to encode VEX.vvvv: |
579 | 0: VEX.vvvv must be 1111b. | |
a2a7d12c | 580 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
2426c15f | 581 | the content of source registers will be preserved. |
29c048b6 | 582 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
2426c15f L |
583 | where the content of first source register will be overwritten |
584 | by the result. | |
6c30d220 L |
585 | VEX.NDD2. The second destination register operand is encoded in |
586 | VEX.vvvv for instructions with 2 destination register operands. | |
587 | For assembler, there are no difference between VEX.NDS, VEX.DDS | |
588 | and VEX.NDD2. | |
589 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for | |
590 | instructions with 1 destination register operand. | |
2426c15f L |
591 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
592 | of the operands can access a memory location. | |
593 | */ | |
594 | #define VEXXDS 1 | |
595 | #define VEXNDD 2 | |
596 | #define VEXLWP 3 | |
597 | VexVVVV, | |
1ef99a7b L |
598 | /* How the VEX.W bit is used: |
599 | 0: Set by the REX.W bit. | |
600 | 1: VEX.W0. Should always be 0. | |
601 | 2: VEX.W1. Should always be 1. | |
6865c043 | 602 | 3: VEX.WIG. The VEX.W bit is ignored. |
1ef99a7b L |
603 | */ |
604 | #define VEXW0 1 | |
605 | #define VEXW1 2 | |
6865c043 | 606 | #define VEXWIG 3 |
1ef99a7b | 607 | VexW, |
b933fa4b JB |
608 | /* Opcode prefix (values chosen to be usable directly in |
609 | VEX/XOP/EVEX pp fields): | |
7b47a312 L |
610 | 0: None |
611 | 1: Add 0x66 opcode prefix. | |
b933fa4b JB |
612 | 2: Add 0xf3 opcode prefix. |
613 | 3: Add 0xf2 opcode prefix. | |
7b47a312 L |
614 | */ |
615 | #define PREFIX_NONE 0 | |
616 | #define PREFIX_0X66 1 | |
b933fa4b JB |
617 | #define PREFIX_0XF3 2 |
618 | #define PREFIX_0XF2 3 | |
7b47a312 | 619 | OpcodePrefix, |
63112cd6 | 620 | /* Instruction with a mandatory SIB byte: |
6c30d220 L |
621 | 1: 128bit vector register. |
622 | 2: 256bit vector register. | |
43234a1e | 623 | 3: 512bit vector register. |
6c30d220 | 624 | */ |
63112cd6 L |
625 | #define VECSIB128 1 |
626 | #define VECSIB256 2 | |
627 | #define VECSIB512 3 | |
260cd341 | 628 | #define SIBMEM 4 |
63112cd6 | 629 | SIB, |
260cd341 | 630 | |
52a6c1fe L |
631 | /* SSE to AVX support required */ |
632 | SSE2AVX, | |
43234a1e L |
633 | |
634 | /* insn has EVEX prefix: | |
635 | 1: 512bit EVEX prefix. | |
636 | 2: 128bit EVEX prefix. | |
637 | 3: 256bit EVEX prefix. | |
638 | 4: Length-ignored (LIG) EVEX prefix. | |
e771e7c9 | 639 | 5: Length determined from actual operands. |
43234a1e L |
640 | */ |
641 | #define EVEX512 1 | |
642 | #define EVEX128 2 | |
643 | #define EVEX256 3 | |
644 | #define EVEXLIG 4 | |
e771e7c9 | 645 | #define EVEXDYN 5 |
43234a1e L |
646 | EVex, |
647 | ||
648 | /* AVX512 masking support: | |
ae2387fe | 649 | 1: Zeroing or merging masking depending on operands. |
43234a1e L |
650 | 2: Merging-masking. |
651 | 3: Both zeroing and merging masking. | |
652 | */ | |
ae2387fe | 653 | #define DYNAMIC_MASKING 1 |
43234a1e L |
654 | #define MERGING_MASKING 2 |
655 | #define BOTH_MASKING 3 | |
656 | Masking, | |
657 | ||
4a1b91ea L |
658 | /* AVX512 broadcast support. The number of bytes to broadcast is |
659 | 1 << (Broadcast - 1): | |
660 | 1: Byte broadcast. | |
661 | 2: Word broadcast. | |
662 | 3: Dword broadcast. | |
663 | 4: Qword broadcast. | |
664 | */ | |
665 | #define BYTE_BROADCAST 1 | |
666 | #define WORD_BROADCAST 2 | |
667 | #define DWORD_BROADCAST 3 | |
668 | #define QWORD_BROADCAST 4 | |
43234a1e L |
669 | Broadcast, |
670 | ||
671 | /* Static rounding control is supported. */ | |
672 | StaticRounding, | |
673 | ||
674 | /* Supress All Exceptions is supported. */ | |
675 | SAE, | |
676 | ||
7091c612 JB |
677 | /* Compressed Disp8*N attribute. */ |
678 | #define DISP8_SHIFT_VL 7 | |
43234a1e L |
679 | Disp8MemShift, |
680 | ||
b6f8c7c4 L |
681 | /* Support encoding optimization. */ |
682 | Optimize, | |
683 | ||
52a6c1fe L |
684 | /* AT&T mnemonic. */ |
685 | ATTMnemonic, | |
686 | /* AT&T syntax. */ | |
687 | ATTSyntax, | |
688 | /* Intel syntax. */ | |
689 | IntelSyntax, | |
4b5aaf5f L |
690 | /* ISA64: Don't change the order without other code adjustments. |
691 | 0: Common to AMD64 and Intel64. | |
692 | 1: AMD64. | |
693 | 2: Intel64. | |
694 | 3: Only in Intel64. | |
695 | */ | |
696 | #define AMD64 1 | |
697 | #define INTEL64 2 | |
698 | #define INTEL64ONLY 3 | |
699 | ISA64, | |
52a6c1fe | 700 | /* The last bitfield in i386_opcode_modifier. */ |
1d942ae9 | 701 | Opcode_Modifier_Num |
52a6c1fe | 702 | }; |
40fb9820 L |
703 | |
704 | typedef struct i386_opcode_modifier | |
705 | { | |
706 | unsigned int d:1; | |
707 | unsigned int w:1; | |
86fa6981 | 708 | unsigned int load:1; |
40fb9820 | 709 | unsigned int modrm:1; |
0cfa3eb3 | 710 | unsigned int jump:3; |
40fb9820 | 711 | unsigned int floatmf:1; |
673fe0f0 | 712 | unsigned int size:2; |
9c19e9ec | 713 | unsigned int checkoperandsize:1; |
255571cd | 714 | unsigned int operandconstraint:4; |
3cd7f3e3 | 715 | unsigned int mnemonicsize:2; |
40fb9820 L |
716 | unsigned int no_bsuf:1; |
717 | unsigned int no_wsuf:1; | |
718 | unsigned int no_lsuf:1; | |
719 | unsigned int no_ssuf:1; | |
720 | unsigned int no_qsuf:1; | |
40fb9820 | 721 | unsigned int fwait:1; |
51c8edf6 | 722 | unsigned int isstring:2; |
dfd69174 | 723 | unsigned int regmem:1; |
7e8b059b | 724 | unsigned int bndprefixok:1; |
742732c7 | 725 | unsigned int prefixok:3; |
40fb9820 L |
726 | unsigned int isprefix:1; |
727 | unsigned int immext:1; | |
728 | unsigned int norex64:1; | |
2bf05e57 | 729 | unsigned int vex:2; |
2426c15f | 730 | unsigned int vexvvvv:2; |
1ef99a7b | 731 | unsigned int vexw:2; |
441f6aca | 732 | unsigned int opcodeprefix:2; |
260cd341 | 733 | unsigned int sib:3; |
c0f3af97 | 734 | unsigned int sse2avx:1; |
43234a1e L |
735 | unsigned int evex:3; |
736 | unsigned int masking:2; | |
4a1b91ea | 737 | unsigned int broadcast:3; |
43234a1e L |
738 | unsigned int staticrounding:1; |
739 | unsigned int sae:1; | |
740 | unsigned int disp8memshift:3; | |
b6f8c7c4 | 741 | unsigned int optimize:1; |
1efbbeb4 | 742 | unsigned int attmnemonic:1; |
e1d4d893 | 743 | unsigned int attsyntax:1; |
5c07affc | 744 | unsigned int intelsyntax:1; |
4b5aaf5f | 745 | unsigned int isa64:2; |
40fb9820 L |
746 | } i386_opcode_modifier; |
747 | ||
bab6aec1 JB |
748 | /* Operand classes. */ |
749 | ||
750 | #define CLASS_WIDTH 4 | |
751 | enum operand_class | |
752 | { | |
753 | ClassNone, | |
754 | Reg, /* GPRs and FP regs, distinguished by operand size */ | |
00cee14f | 755 | SReg, /* Segment register */ |
4a5c67ed JB |
756 | RegCR, /* Control register */ |
757 | RegDR, /* Debug register */ | |
758 | RegTR, /* Test register */ | |
3528c362 JB |
759 | RegMMX, /* MMX register */ |
760 | RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ | |
f74a6307 JB |
761 | RegMask, /* Vector Mask register */ |
762 | RegBND, /* Bound register */ | |
bab6aec1 JB |
763 | }; |
764 | ||
75e5731b JB |
765 | /* Special operand instances. */ |
766 | ||
767 | #define INSTANCE_WIDTH 3 | |
768 | enum operand_instance | |
769 | { | |
770 | InstanceNone, | |
771 | Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ | |
474da251 JB |
772 | RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ |
773 | RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ | |
774 | RegB, /* %bl / %bx / %ebx / %rbx */ | |
75e5731b JB |
775 | }; |
776 | ||
40fb9820 L |
777 | /* Position of operand_type bits. */ |
778 | ||
52a6c1fe L |
779 | enum |
780 | { | |
75e5731b JB |
781 | /* Class and Instance */ |
782 | ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, | |
52a6c1fe L |
783 | /* 1 bit immediate */ |
784 | Imm1, | |
785 | /* 8 bit immediate */ | |
786 | Imm8, | |
787 | /* 8 bit immediate sign extended */ | |
788 | Imm8S, | |
789 | /* 16 bit immediate */ | |
790 | Imm16, | |
791 | /* 32 bit immediate */ | |
792 | Imm32, | |
793 | /* 32 bit immediate sign extended */ | |
794 | Imm32S, | |
795 | /* 64 bit immediate */ | |
796 | Imm64, | |
797 | /* 8bit/16bit/32bit displacements are used in different ways, | |
798 | depending on the instruction. For jumps, they specify the | |
799 | size of the PC relative displacement, for instructions with | |
800 | memory operand, they specify the size of the offset relative | |
801 | to the base register, and for instructions with memory offset | |
802 | such as `mov 1234,%al' they specify the size of the offset | |
803 | relative to the segment base. */ | |
804 | /* 8 bit displacement */ | |
805 | Disp8, | |
806 | /* 16 bit displacement */ | |
807 | Disp16, | |
a775efc8 | 808 | /* 32 bit displacement (64-bit: sign-extended) */ |
52a6c1fe | 809 | Disp32, |
52a6c1fe L |
810 | /* 64 bit displacement */ |
811 | Disp64, | |
52a6c1fe L |
812 | /* Register which can be used for base or index in memory operand. */ |
813 | BaseIndex, | |
11a322db | 814 | /* BYTE size. */ |
52a6c1fe | 815 | Byte, |
11a322db | 816 | /* WORD size. 2 byte */ |
52a6c1fe | 817 | Word, |
11a322db | 818 | /* DWORD size. 4 byte */ |
52a6c1fe | 819 | Dword, |
11a322db | 820 | /* FWORD size. 6 byte */ |
52a6c1fe | 821 | Fword, |
11a322db | 822 | /* QWORD size. 8 byte */ |
52a6c1fe | 823 | Qword, |
11a322db | 824 | /* TBYTE size. 10 byte */ |
52a6c1fe | 825 | Tbyte, |
11a322db | 826 | /* XMMWORD size. */ |
52a6c1fe | 827 | Xmmword, |
11a322db | 828 | /* YMMWORD size. */ |
52a6c1fe | 829 | Ymmword, |
11a322db | 830 | /* ZMMWORD size. */ |
43234a1e | 831 | Zmmword, |
260cd341 LC |
832 | /* TMMWORD size. */ |
833 | Tmmword, | |
52a6c1fe L |
834 | /* Unspecified memory size. */ |
835 | Unspecified, | |
40fb9820 | 836 | |
bab6aec1 | 837 | /* The number of bits in i386_operand_type. */ |
f0a85b07 | 838 | OTNum |
52a6c1fe | 839 | }; |
40fb9820 L |
840 | |
841 | #define OTNumOfUints \ | |
f0a85b07 | 842 | ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) |
40fb9820 L |
843 | #define OTNumOfBits \ |
844 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
845 | ||
846 | /* If you get a compiler error for zero width of the unused field, | |
601e8564 | 847 | comment it out. */ |
f0a85b07 | 848 | #define OTUnused OTNum |
40fb9820 L |
849 | |
850 | typedef union i386_operand_type | |
851 | { | |
852 | struct | |
853 | { | |
bab6aec1 | 854 | unsigned int class:CLASS_WIDTH; |
75e5731b | 855 | unsigned int instance:INSTANCE_WIDTH; |
7d5e4556 | 856 | unsigned int imm1:1; |
40fb9820 L |
857 | unsigned int imm8:1; |
858 | unsigned int imm8s:1; | |
859 | unsigned int imm16:1; | |
860 | unsigned int imm32:1; | |
861 | unsigned int imm32s:1; | |
862 | unsigned int imm64:1; | |
40fb9820 L |
863 | unsigned int disp8:1; |
864 | unsigned int disp16:1; | |
865 | unsigned int disp32:1; | |
40fb9820 | 866 | unsigned int disp64:1; |
7d5e4556 | 867 | unsigned int baseindex:1; |
7d5e4556 L |
868 | unsigned int byte:1; |
869 | unsigned int word:1; | |
870 | unsigned int dword:1; | |
871 | unsigned int fword:1; | |
872 | unsigned int qword:1; | |
873 | unsigned int tbyte:1; | |
874 | unsigned int xmmword:1; | |
c0f3af97 | 875 | unsigned int ymmword:1; |
43234a1e | 876 | unsigned int zmmword:1; |
260cd341 | 877 | unsigned int tmmword:1; |
7d5e4556 | 878 | unsigned int unspecified:1; |
40fb9820 L |
879 | #ifdef OTUnused |
880 | unsigned int unused:(OTNumOfBits - OTUnused); | |
881 | #endif | |
882 | } bitfield; | |
883 | unsigned int array[OTNumOfUints]; | |
884 | } i386_operand_type; | |
0b1cf022 | 885 | |
d3ce72d0 | 886 | typedef struct insn_template |
0b1cf022 L |
887 | { |
888 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
5c139202 | 889 | unsigned int mnem_off; |
0b1cf022 | 890 | |
37cea588 JB |
891 | /* Bitfield arrangement is such that individual fields can be easily |
892 | extracted (in native builds at least) - either by at most a masking | |
893 | operation (base_opcode, operands), or by just a (signed) right shift | |
894 | (extension_opcode). Please try to maintain this property. */ | |
895 | ||
0b1cf022 L |
896 | /* base_opcode is the fundamental opcode byte without optional |
897 | prefix(es). */ | |
9df6f676 | 898 | unsigned int base_opcode:16; |
0b1cf022 L |
899 | #define Opcode_D 0x2 /* Direction bit: |
900 | set if Reg --> Regmem; | |
901 | unset if Regmem --> Reg. */ | |
bd782808 JB |
902 | #define Opcode_FloatR 0x8 /* ModR/M bit to swap src/dest for float insns. */ |
903 | #define Opcode_FloatD 0x4 /* Direction bit for float insns. */ | |
2c735193 | 904 | #define Opcode_ExtD 0x1 /* Direction bit for extended opcode space insns. */ |
dbbc8b7e | 905 | #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ |
8bd915b7 JB |
906 | /* The next value is arbitrary, as long as it's non-zero and distinct |
907 | from all other values above. */ | |
908 | #define Opcode_VexW 0xf /* Operand order controlled by VEX.W. */ | |
0b1cf022 | 909 | |
37cea588 JB |
910 | /* how many operands */ |
911 | unsigned int operands:3; | |
912 | ||
ddb62495 JB |
913 | /* opcode space */ |
914 | unsigned int opcode_space:4; | |
915 | /* Opcode encoding space (values chosen to be usable directly in | |
916 | VEX/XOP mmmmm and EVEX mm fields): | |
917 | 0: Base opcode space. | |
918 | 1: 0F opcode prefix / space. | |
919 | 2: 0F38 opcode prefix / space. | |
920 | 3: 0F3A opcode prefix / space. | |
921 | 5: EVEXMAP5 opcode prefix / space. | |
922 | 6: EVEXMAP6 opcode prefix / space. | |
923 | 8: XOP 08 opcode space. | |
924 | 9: XOP 09 opcode space. | |
925 | A: XOP 0A opcode space. | |
926 | */ | |
927 | #define SPACE_BASE 0 | |
928 | #define SPACE_0F 1 | |
929 | #define SPACE_0F38 2 | |
930 | #define SPACE_0F3A 3 | |
931 | #define SPACE_EVEXMAP5 5 | |
932 | #define SPACE_EVEXMAP6 6 | |
933 | #define SPACE_XOP08 8 | |
934 | #define SPACE_XOP09 9 | |
935 | #define SPACE_XOP0A 0xA | |
37cea588 | 936 | |
31184569 JB |
937 | /* (Fake) base opcode value for pseudo prefixes. */ |
938 | #define PSEUDO_PREFIX 0 | |
939 | ||
940 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
941 | This field is also used to store the 8-bit opcode suffix for the | |
942 | AMD 3DNow! instructions. | |
943 | If this template has no extension opcode (the usual case) use None | |
944 | Instructions */ | |
9df6f676 JB |
945 | signed int extension_opcode:9; |
946 | #define None (-1) /* If no extension_opcode is possible. */ | |
31184569 | 947 | |
41eb8e88 L |
948 | /* Pseudo prefixes. */ |
949 | #define Prefix_Disp8 0 /* {disp8} */ | |
950 | #define Prefix_Disp16 1 /* {disp16} */ | |
951 | #define Prefix_Disp32 2 /* {disp32} */ | |
952 | #define Prefix_Load 3 /* {load} */ | |
953 | #define Prefix_Store 4 /* {store} */ | |
954 | #define Prefix_VEX 5 /* {vex} */ | |
955 | #define Prefix_VEX3 6 /* {vex3} */ | |
956 | #define Prefix_EVEX 7 /* {evex} */ | |
957 | #define Prefix_REX 8 /* {rex} */ | |
958 | #define Prefix_NoOptimize 9 /* {nooptimize} */ | |
959 | ||
0b1cf022 L |
960 | /* the bits in opcode_modifier are used to generate the final opcode from |
961 | the base_opcode. These bits also are used to detect alternate forms of | |
962 | the same instruction */ | |
40fb9820 | 963 | i386_opcode_modifier opcode_modifier; |
0b1cf022 | 964 | |
dac10fb0 JB |
965 | /* cpu feature flags */ |
966 | i386_cpu_flags cpu_flags; | |
967 | ||
0b1cf022 L |
968 | /* operand_types[i] describes the type of operand i. This is made |
969 | by OR'ing together all of the possible type masks. (e.g. | |
970 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
971 | either a register or an immediate operand. */ | |
40fb9820 | 972 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 | 973 | } |
d3ce72d0 | 974 | insn_template; |
0b1cf022 | 975 | |
0b1cf022 L |
976 | /* these are for register name --> number & type hash lookup */ |
977 | typedef struct | |
978 | { | |
edf77258 | 979 | char reg_name[8]; |
40fb9820 | 980 | i386_operand_type reg_type; |
a60de03c | 981 | unsigned char reg_flags; |
0b1cf022 L |
982 | #define RegRex 0x1 /* Extended register. */ |
983 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
43234a1e | 984 | #define RegVRex 0x4 /* Extended vector register. */ |
a60de03c | 985 | unsigned char reg_num; |
e968fc9b | 986 | #define RegIP ((unsigned char ) ~0) |
db51cc60 | 987 | /* EIZ and RIZ are fake index registers. */ |
e968fc9b | 988 | #define RegIZ (RegIP - 1) |
b7240065 JB |
989 | /* FLAT is a fake segment register (Intel mode). */ |
990 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
991 | signed char dw2_regnum[2]; |
992 | #define Dw2Inval (-1) | |
0b1cf022 L |
993 | } |
994 | reg_entry; |