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0b1cf022 | 1 | /* Declarations for Intel 80386 opcode table |
250d07de | 2 | Copyright (C) 2007-2021 Free Software Foundation, Inc. |
0b1cf022 | 3 | |
9b201bb5 | 4 | This file is part of the GNU opcodes library. |
0b1cf022 | 5 | |
9b201bb5 | 6 | This library is free software; you can redistribute it and/or modify |
0b1cf022 | 7 | it under the terms of the GNU General Public License as published by |
9b201bb5 | 8 | the Free Software Foundation; either version 3, or (at your option) |
0b1cf022 L |
9 | any later version. |
10 | ||
9b201bb5 NC |
11 | It is distributed in the hope that it will be useful, but WITHOUT |
12 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY | |
13 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public | |
14 | License for more details. | |
0b1cf022 L |
15 | |
16 | You should have received a copy of the GNU General Public License | |
17 | along with GAS; see the file COPYING. If not, write to the Free | |
18 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA | |
19 | 02110-1301, USA. */ | |
20 | ||
21 | #include "opcode/i386.h" | |
40fb9820 L |
22 | #ifdef HAVE_LIMITS_H |
23 | #include <limits.h> | |
24 | #endif | |
25 | ||
26 | #ifndef CHAR_BIT | |
27 | #define CHAR_BIT 8 | |
28 | #endif | |
29 | ||
30 | /* Position of cpu flags bitfiled. */ | |
31 | ||
52a6c1fe L |
32 | enum |
33 | { | |
34 | /* i186 or better required */ | |
35 | Cpu186 = 0, | |
36 | /* i286 or better required */ | |
37 | Cpu286, | |
38 | /* i386 or better required */ | |
39 | Cpu386, | |
40 | /* i486 or better required */ | |
41 | Cpu486, | |
42 | /* i585 or better required */ | |
43 | Cpu586, | |
44 | /* i686 or better required */ | |
45 | Cpu686, | |
d871f3f4 L |
46 | /* CMOV Instruction support required */ |
47 | CpuCMOV, | |
48 | /* FXSR Instruction support required */ | |
49 | CpuFXSR, | |
b49dfb4a | 50 | /* CLFLUSH Instruction support required */ |
52a6c1fe | 51 | CpuClflush, |
22109423 L |
52 | /* NOP Instruction support required */ |
53 | CpuNop, | |
b49dfb4a | 54 | /* SYSCALL Instructions support required */ |
52a6c1fe L |
55 | CpuSYSCALL, |
56 | /* Floating point support required */ | |
57 | Cpu8087, | |
58 | /* i287 support required */ | |
59 | Cpu287, | |
60 | /* i387 support required */ | |
61 | Cpu387, | |
62 | /* i686 and floating point support required */ | |
63 | Cpu687, | |
64 | /* SSE3 and floating point support required */ | |
65 | CpuFISTTP, | |
66 | /* MMX support required */ | |
67 | CpuMMX, | |
68 | /* SSE support required */ | |
69 | CpuSSE, | |
70 | /* SSE2 support required */ | |
71 | CpuSSE2, | |
72 | /* 3dnow! support required */ | |
73 | Cpu3dnow, | |
74 | /* 3dnow! Extensions support required */ | |
75 | Cpu3dnowA, | |
76 | /* SSE3 support required */ | |
77 | CpuSSE3, | |
78 | /* VIA PadLock required */ | |
79 | CpuPadLock, | |
80 | /* AMD Secure Virtual Machine Ext-s required */ | |
81 | CpuSVME, | |
82 | /* VMX Instructions required */ | |
83 | CpuVMX, | |
84 | /* SMX Instructions required */ | |
85 | CpuSMX, | |
86 | /* SSSE3 support required */ | |
87 | CpuSSSE3, | |
88 | /* SSE4a support required */ | |
89 | CpuSSE4a, | |
272a84b1 L |
90 | /* LZCNT support required */ |
91 | CpuLZCNT, | |
92 | /* POPCNT support required */ | |
93 | CpuPOPCNT, | |
52a6c1fe L |
94 | /* SSE4.1 support required */ |
95 | CpuSSE4_1, | |
96 | /* SSE4.2 support required */ | |
97 | CpuSSE4_2, | |
98 | /* AVX support required */ | |
99 | CpuAVX, | |
6c30d220 L |
100 | /* AVX2 support required */ |
101 | CpuAVX2, | |
43234a1e L |
102 | /* Intel AVX-512 Foundation Instructions support required */ |
103 | CpuAVX512F, | |
104 | /* Intel AVX-512 Conflict Detection Instructions support required */ | |
105 | CpuAVX512CD, | |
106 | /* Intel AVX-512 Exponential and Reciprocal Instructions support | |
107 | required */ | |
108 | CpuAVX512ER, | |
109 | /* Intel AVX-512 Prefetch Instructions support required */ | |
110 | CpuAVX512PF, | |
b28d1bda IT |
111 | /* Intel AVX-512 VL Instructions support required. */ |
112 | CpuAVX512VL, | |
90a915bf IT |
113 | /* Intel AVX-512 DQ Instructions support required. */ |
114 | CpuAVX512DQ, | |
1ba585e8 IT |
115 | /* Intel AVX-512 BW Instructions support required. */ |
116 | CpuAVX512BW, | |
52a6c1fe L |
117 | /* Intel L1OM support required */ |
118 | CpuL1OM, | |
7a9068fe L |
119 | /* Intel K1OM support required */ |
120 | CpuK1OM, | |
7b6d09fb L |
121 | /* Intel IAMCU support required */ |
122 | CpuIAMCU, | |
b49dfb4a | 123 | /* Xsave/xrstor New Instructions support required */ |
52a6c1fe | 124 | CpuXsave, |
b49dfb4a | 125 | /* Xsaveopt New Instructions support required */ |
c7b8aa3a | 126 | CpuXsaveopt, |
52a6c1fe L |
127 | /* AES support required */ |
128 | CpuAES, | |
129 | /* PCLMUL support required */ | |
130 | CpuPCLMUL, | |
131 | /* FMA support required */ | |
132 | CpuFMA, | |
133 | /* FMA4 support required */ | |
134 | CpuFMA4, | |
5dd85c99 SP |
135 | /* XOP support required */ |
136 | CpuXOP, | |
f88c9eb0 SP |
137 | /* LWP support required */ |
138 | CpuLWP, | |
f12dc422 L |
139 | /* BMI support required */ |
140 | CpuBMI, | |
2a2a0f38 QN |
141 | /* TBM support required */ |
142 | CpuTBM, | |
b49dfb4a | 143 | /* MOVBE Instruction support required */ |
52a6c1fe | 144 | CpuMovbe, |
60aa667e L |
145 | /* CMPXCHG16B instruction support required. */ |
146 | CpuCX16, | |
52a6c1fe L |
147 | /* EPT Instructions required */ |
148 | CpuEPT, | |
b49dfb4a | 149 | /* RDTSCP Instruction support required */ |
52a6c1fe | 150 | CpuRdtscp, |
77321f53 | 151 | /* FSGSBASE Instructions required */ |
c7b8aa3a L |
152 | CpuFSGSBase, |
153 | /* RDRND Instructions required */ | |
154 | CpuRdRnd, | |
155 | /* F16C Instructions required */ | |
156 | CpuF16C, | |
6c30d220 L |
157 | /* Intel BMI2 support required */ |
158 | CpuBMI2, | |
42164a71 L |
159 | /* HLE support required */ |
160 | CpuHLE, | |
161 | /* RTM support required */ | |
162 | CpuRTM, | |
6c30d220 L |
163 | /* INVPCID Instructions required */ |
164 | CpuINVPCID, | |
8729a6f6 L |
165 | /* VMFUNC Instruction required */ |
166 | CpuVMFUNC, | |
7e8b059b L |
167 | /* Intel MPX Instructions required */ |
168 | CpuMPX, | |
52a6c1fe L |
169 | /* 64bit support available, used by -march= in assembler. */ |
170 | CpuLM, | |
e2e1fcde L |
171 | /* RDRSEED instruction required. */ |
172 | CpuRDSEED, | |
173 | /* Multi-presisionn add-carry instructions are required. */ | |
174 | CpuADX, | |
7b458c12 | 175 | /* Supports prefetchw and prefetch instructions. */ |
e2e1fcde | 176 | CpuPRFCHW, |
5c111e37 L |
177 | /* SMAP instructions required. */ |
178 | CpuSMAP, | |
a0046408 L |
179 | /* SHA instructions required. */ |
180 | CpuSHA, | |
963f3586 IT |
181 | /* CLFLUSHOPT instruction required */ |
182 | CpuClflushOpt, | |
183 | /* XSAVES/XRSTORS instruction required */ | |
184 | CpuXSAVES, | |
185 | /* XSAVEC instruction required */ | |
186 | CpuXSAVEC, | |
dcf893b5 IT |
187 | /* PREFETCHWT1 instruction required */ |
188 | CpuPREFETCHWT1, | |
2cf200a4 IT |
189 | /* SE1 instruction required */ |
190 | CpuSE1, | |
c5e7287a IT |
191 | /* CLWB instruction required */ |
192 | CpuCLWB, | |
2cc1b5aa IT |
193 | /* Intel AVX-512 IFMA Instructions support required. */ |
194 | CpuAVX512IFMA, | |
14f195c9 IT |
195 | /* Intel AVX-512 VBMI Instructions support required. */ |
196 | CpuAVX512VBMI, | |
920d2ddc IT |
197 | /* Intel AVX-512 4FMAPS Instructions support required. */ |
198 | CpuAVX512_4FMAPS, | |
47acf0bd IT |
199 | /* Intel AVX-512 4VNNIW Instructions support required. */ |
200 | CpuAVX512_4VNNIW, | |
620214f7 IT |
201 | /* Intel AVX-512 VPOPCNTDQ Instructions support required. */ |
202 | CpuAVX512_VPOPCNTDQ, | |
53467f57 IT |
203 | /* Intel AVX-512 VBMI2 Instructions support required. */ |
204 | CpuAVX512_VBMI2, | |
8cfcb765 IT |
205 | /* Intel AVX-512 VNNI Instructions support required. */ |
206 | CpuAVX512_VNNI, | |
ee6872be IT |
207 | /* Intel AVX-512 BITALG Instructions support required. */ |
208 | CpuAVX512_BITALG, | |
d6aab7a1 XG |
209 | /* Intel AVX-512 BF16 Instructions support required. */ |
210 | CpuAVX512_BF16, | |
9186c494 L |
211 | /* Intel AVX-512 VP2INTERSECT Instructions support required. */ |
212 | CpuAVX512_VP2INTERSECT, | |
81d54bb7 CL |
213 | /* TDX Instructions support required. */ |
214 | CpuTDX, | |
58bf9b6a L |
215 | /* Intel AVX VNNI Instructions support required. */ |
216 | CpuAVX_VNNI, | |
9916071f AP |
217 | /* mwaitx instruction required */ |
218 | CpuMWAITX, | |
43e65147 | 219 | /* Clzero instruction required */ |
029f3522 | 220 | CpuCLZERO, |
8eab4136 L |
221 | /* OSPKE instruction required */ |
222 | CpuOSPKE, | |
8bc52696 AF |
223 | /* RDPID instruction required */ |
224 | CpuRDPID, | |
6b40c462 L |
225 | /* PTWRITE instruction required */ |
226 | CpuPTWRITE, | |
d777820b IT |
227 | /* CET instructions support required */ |
228 | CpuIBT, | |
229 | CpuSHSTK, | |
260cd341 LC |
230 | /* AMX-INT8 instructions required */ |
231 | CpuAMX_INT8, | |
232 | /* AMX-BF16 instructions required */ | |
233 | CpuAMX_BF16, | |
234 | /* AMX-TILE instructions required */ | |
235 | CpuAMX_TILE, | |
48521003 IT |
236 | /* GFNI instructions required */ |
237 | CpuGFNI, | |
8dcf1fad IT |
238 | /* VAES instructions required */ |
239 | CpuVAES, | |
ff1982d5 IT |
240 | /* VPCLMULQDQ instructions required */ |
241 | CpuVPCLMULQDQ, | |
3233d7d0 IT |
242 | /* WBNOINVD instructions required */ |
243 | CpuWBNOINVD, | |
be3a8dca IT |
244 | /* PCONFIG instructions required */ |
245 | CpuPCONFIG, | |
de89d0a3 IT |
246 | /* WAITPKG instructions required */ |
247 | CpuWAITPKG, | |
f64c42a9 LC |
248 | /* UINTR instructions required */ |
249 | CpuUINTR, | |
c48935d7 IT |
250 | /* CLDEMOTE instruction required */ |
251 | CpuCLDEMOTE, | |
c0a30a9f L |
252 | /* MOVDIRI instruction support required */ |
253 | CpuMOVDIRI, | |
254 | /* MOVDIRR64B instruction required */ | |
255 | CpuMOVDIR64B, | |
5d79adc4 L |
256 | /* ENQCMD instruction required */ |
257 | CpuENQCMD, | |
4b27d27c L |
258 | /* SERIALIZE instruction required */ |
259 | CpuSERIALIZE, | |
142861df JB |
260 | /* RDPRU instruction required */ |
261 | CpuRDPRU, | |
262 | /* MCOMMIT instruction required */ | |
263 | CpuMCOMMIT, | |
a847e322 JB |
264 | /* SEV-ES instruction(s) required */ |
265 | CpuSEV_ES, | |
bb651e8b CL |
266 | /* TSXLDTRK instruction required */ |
267 | CpuTSXLDTRK, | |
c4694f17 TG |
268 | /* KL instruction support required */ |
269 | CpuKL, | |
270 | /* WideKL instruction support required */ | |
271 | CpuWideKL, | |
c1fa250a LC |
272 | /* HRESET instruction required */ |
273 | CpuHRESET, | |
646cc3e0 GG |
274 | /* INVLPGB instructions required */ |
275 | CpuINVLPGB, | |
276 | /* TLBSYNC instructions required */ | |
277 | CpuTLBSYNC, | |
278 | /* SNP instructions required */ | |
279 | CpuSNP, | |
52a6c1fe L |
280 | /* 64bit support required */ |
281 | Cpu64, | |
282 | /* Not supported in the 64bit mode */ | |
283 | CpuNo64, | |
284 | /* The last bitfield in i386_cpu_flags. */ | |
e92bae62 | 285 | CpuMax = CpuNo64 |
52a6c1fe | 286 | }; |
40fb9820 L |
287 | |
288 | #define CpuNumOfUints \ | |
289 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) | |
290 | #define CpuNumOfBits \ | |
291 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
292 | ||
293 | /* If you get a compiler error for zero width of the unused field, | |
294 | comment it out. */ | |
8cfcb765 | 295 | #define CpuUnused (CpuMax + 1) |
53467f57 | 296 | |
40fb9820 L |
297 | /* We can check if an instruction is available with array instead |
298 | of bitfield. */ | |
299 | typedef union i386_cpu_flags | |
300 | { | |
301 | struct | |
302 | { | |
303 | unsigned int cpui186:1; | |
304 | unsigned int cpui286:1; | |
305 | unsigned int cpui386:1; | |
306 | unsigned int cpui486:1; | |
307 | unsigned int cpui586:1; | |
308 | unsigned int cpui686:1; | |
d871f3f4 L |
309 | unsigned int cpucmov:1; |
310 | unsigned int cpufxsr:1; | |
bd5295b2 | 311 | unsigned int cpuclflush:1; |
22109423 | 312 | unsigned int cpunop:1; |
bd5295b2 | 313 | unsigned int cpusyscall:1; |
309d3373 JB |
314 | unsigned int cpu8087:1; |
315 | unsigned int cpu287:1; | |
316 | unsigned int cpu387:1; | |
317 | unsigned int cpu687:1; | |
318 | unsigned int cpufisttp:1; | |
40fb9820 | 319 | unsigned int cpummx:1; |
40fb9820 L |
320 | unsigned int cpusse:1; |
321 | unsigned int cpusse2:1; | |
322 | unsigned int cpua3dnow:1; | |
323 | unsigned int cpua3dnowa:1; | |
324 | unsigned int cpusse3:1; | |
325 | unsigned int cpupadlock:1; | |
326 | unsigned int cpusvme:1; | |
327 | unsigned int cpuvmx:1; | |
47dd174c | 328 | unsigned int cpusmx:1; |
40fb9820 L |
329 | unsigned int cpussse3:1; |
330 | unsigned int cpusse4a:1; | |
272a84b1 L |
331 | unsigned int cpulzcnt:1; |
332 | unsigned int cpupopcnt:1; | |
40fb9820 L |
333 | unsigned int cpusse4_1:1; |
334 | unsigned int cpusse4_2:1; | |
c0f3af97 | 335 | unsigned int cpuavx:1; |
6c30d220 | 336 | unsigned int cpuavx2:1; |
43234a1e L |
337 | unsigned int cpuavx512f:1; |
338 | unsigned int cpuavx512cd:1; | |
339 | unsigned int cpuavx512er:1; | |
340 | unsigned int cpuavx512pf:1; | |
b28d1bda | 341 | unsigned int cpuavx512vl:1; |
90a915bf | 342 | unsigned int cpuavx512dq:1; |
1ba585e8 | 343 | unsigned int cpuavx512bw:1; |
8a9036a4 | 344 | unsigned int cpul1om:1; |
7a9068fe | 345 | unsigned int cpuk1om:1; |
7b6d09fb | 346 | unsigned int cpuiamcu:1; |
475a2301 | 347 | unsigned int cpuxsave:1; |
c7b8aa3a | 348 | unsigned int cpuxsaveopt:1; |
c0f3af97 | 349 | unsigned int cpuaes:1; |
594ab6a3 | 350 | unsigned int cpupclmul:1; |
c0f3af97 | 351 | unsigned int cpufma:1; |
922d8de8 | 352 | unsigned int cpufma4:1; |
5dd85c99 | 353 | unsigned int cpuxop:1; |
f88c9eb0 | 354 | unsigned int cpulwp:1; |
f12dc422 | 355 | unsigned int cpubmi:1; |
2a2a0f38 | 356 | unsigned int cputbm:1; |
f1f8f695 | 357 | unsigned int cpumovbe:1; |
60aa667e | 358 | unsigned int cpucx16:1; |
f1f8f695 | 359 | unsigned int cpuept:1; |
1b7f3fb0 | 360 | unsigned int cpurdtscp:1; |
c7b8aa3a L |
361 | unsigned int cpufsgsbase:1; |
362 | unsigned int cpurdrnd:1; | |
363 | unsigned int cpuf16c:1; | |
6c30d220 | 364 | unsigned int cpubmi2:1; |
42164a71 L |
365 | unsigned int cpuhle:1; |
366 | unsigned int cpurtm:1; | |
6c30d220 | 367 | unsigned int cpuinvpcid:1; |
8729a6f6 | 368 | unsigned int cpuvmfunc:1; |
7e8b059b | 369 | unsigned int cpumpx:1; |
40fb9820 | 370 | unsigned int cpulm:1; |
e2e1fcde L |
371 | unsigned int cpurdseed:1; |
372 | unsigned int cpuadx:1; | |
373 | unsigned int cpuprfchw:1; | |
5c111e37 | 374 | unsigned int cpusmap:1; |
a0046408 | 375 | unsigned int cpusha:1; |
963f3586 IT |
376 | unsigned int cpuclflushopt:1; |
377 | unsigned int cpuxsaves:1; | |
378 | unsigned int cpuxsavec:1; | |
dcf893b5 | 379 | unsigned int cpuprefetchwt1:1; |
2cf200a4 | 380 | unsigned int cpuse1:1; |
c5e7287a | 381 | unsigned int cpuclwb:1; |
2cc1b5aa | 382 | unsigned int cpuavx512ifma:1; |
14f195c9 | 383 | unsigned int cpuavx512vbmi:1; |
920d2ddc | 384 | unsigned int cpuavx512_4fmaps:1; |
47acf0bd | 385 | unsigned int cpuavx512_4vnniw:1; |
620214f7 | 386 | unsigned int cpuavx512_vpopcntdq:1; |
53467f57 | 387 | unsigned int cpuavx512_vbmi2:1; |
8cfcb765 | 388 | unsigned int cpuavx512_vnni:1; |
ee6872be | 389 | unsigned int cpuavx512_bitalg:1; |
d6aab7a1 | 390 | unsigned int cpuavx512_bf16:1; |
9186c494 | 391 | unsigned int cpuavx512_vp2intersect:1; |
81d54bb7 | 392 | unsigned int cputdx:1; |
58bf9b6a | 393 | unsigned int cpuavx_vnni:1; |
9916071f | 394 | unsigned int cpumwaitx:1; |
029f3522 | 395 | unsigned int cpuclzero:1; |
8eab4136 | 396 | unsigned int cpuospke:1; |
8bc52696 | 397 | unsigned int cpurdpid:1; |
6b40c462 | 398 | unsigned int cpuptwrite:1; |
d777820b IT |
399 | unsigned int cpuibt:1; |
400 | unsigned int cpushstk:1; | |
260cd341 LC |
401 | unsigned int cpuamx_int8:1; |
402 | unsigned int cpuamx_bf16:1; | |
403 | unsigned int cpuamx_tile:1; | |
48521003 | 404 | unsigned int cpugfni:1; |
8dcf1fad | 405 | unsigned int cpuvaes:1; |
ff1982d5 | 406 | unsigned int cpuvpclmulqdq:1; |
3233d7d0 | 407 | unsigned int cpuwbnoinvd:1; |
be3a8dca | 408 | unsigned int cpupconfig:1; |
de89d0a3 | 409 | unsigned int cpuwaitpkg:1; |
f64c42a9 | 410 | unsigned int cpuuintr:1; |
c48935d7 | 411 | unsigned int cpucldemote:1; |
c0a30a9f L |
412 | unsigned int cpumovdiri:1; |
413 | unsigned int cpumovdir64b:1; | |
5d79adc4 | 414 | unsigned int cpuenqcmd:1; |
4b27d27c | 415 | unsigned int cpuserialize:1; |
142861df JB |
416 | unsigned int cpurdpru:1; |
417 | unsigned int cpumcommit:1; | |
a847e322 | 418 | unsigned int cpusev_es:1; |
bb651e8b | 419 | unsigned int cputsxldtrk:1; |
c4694f17 TG |
420 | unsigned int cpukl:1; |
421 | unsigned int cpuwidekl:1; | |
c1fa250a | 422 | unsigned int cpuhreset:1; |
646cc3e0 GG |
423 | unsigned int cpuinvlpgb:1; |
424 | unsigned int cputlbsync:1; | |
425 | unsigned int cpusnp:1; | |
40fb9820 L |
426 | unsigned int cpu64:1; |
427 | unsigned int cpuno64:1; | |
428 | #ifdef CpuUnused | |
429 | unsigned int unused:(CpuNumOfBits - CpuUnused); | |
430 | #endif | |
431 | } bitfield; | |
432 | unsigned int array[CpuNumOfUints]; | |
433 | } i386_cpu_flags; | |
434 | ||
435 | /* Position of opcode_modifier bits. */ | |
436 | ||
52a6c1fe L |
437 | enum |
438 | { | |
439 | /* has direction bit. */ | |
440 | D = 0, | |
507916b8 JB |
441 | /* set if operands can be both bytes and words/dwords/qwords, encoded the |
442 | canonical way; the base_opcode field should hold the encoding for byte | |
443 | operands */ | |
52a6c1fe | 444 | W, |
86fa6981 L |
445 | /* load form instruction. Must be placed before store form. */ |
446 | Load, | |
52a6c1fe L |
447 | /* insn has a modrm byte. */ |
448 | Modrm, | |
0cfa3eb3 JB |
449 | /* special case for jump insns; value has to be 1 */ |
450 | #define JUMP 1 | |
52a6c1fe | 451 | /* call and jump */ |
0cfa3eb3 | 452 | #define JUMP_DWORD 2 |
52a6c1fe | 453 | /* loop and jecxz */ |
0cfa3eb3 | 454 | #define JUMP_BYTE 3 |
52a6c1fe | 455 | /* special case for intersegment leaps/calls */ |
0cfa3eb3 | 456 | #define JUMP_INTERSEGMENT 4 |
6f2f06be | 457 | /* absolute address for jump */ |
0cfa3eb3 JB |
458 | #define JUMP_ABSOLUTE 5 |
459 | Jump, | |
52a6c1fe L |
460 | /* FP insn memory format bit, sized by 0x4 */ |
461 | FloatMF, | |
462 | /* src/dest swap for floats. */ | |
463 | FloatR, | |
52a6c1fe | 464 | /* needs size prefix if in 32-bit mode */ |
673fe0f0 | 465 | #define SIZE16 1 |
52a6c1fe | 466 | /* needs size prefix if in 16-bit mode */ |
673fe0f0 | 467 | #define SIZE32 2 |
52a6c1fe | 468 | /* needs size prefix if in 64-bit mode */ |
673fe0f0 JB |
469 | #define SIZE64 3 |
470 | Size, | |
56ffb741 L |
471 | /* check register size. */ |
472 | CheckRegSize, | |
52a6c1fe L |
473 | /* instruction ignores operand size prefix and in Intel mode ignores |
474 | mnemonic size suffix check. */ | |
3cd7f3e3 | 475 | #define IGNORESIZE 1 |
52a6c1fe | 476 | /* default insn size depends on mode */ |
3cd7f3e3 L |
477 | #define DEFAULTSIZE 2 |
478 | MnemonicSize, | |
601e8564 JB |
479 | /* any memory size */ |
480 | Anysize, | |
52a6c1fe L |
481 | /* b suffix on instruction illegal */ |
482 | No_bSuf, | |
483 | /* w suffix on instruction illegal */ | |
484 | No_wSuf, | |
485 | /* l suffix on instruction illegal */ | |
486 | No_lSuf, | |
487 | /* s suffix on instruction illegal */ | |
488 | No_sSuf, | |
489 | /* q suffix on instruction illegal */ | |
490 | No_qSuf, | |
491 | /* long double suffix on instruction illegal */ | |
492 | No_ldSuf, | |
493 | /* instruction needs FWAIT */ | |
494 | FWait, | |
51c8edf6 JB |
495 | /* IsString provides for a quick test for string instructions, and |
496 | its actual value also indicates which of the operands (if any) | |
497 | requires use of the %es segment. */ | |
498 | #define IS_STRING_ES_OP0 2 | |
499 | #define IS_STRING_ES_OP1 3 | |
52a6c1fe | 500 | IsString, |
dfd69174 JB |
501 | /* RegMem is for instructions with a modrm byte where the register |
502 | destination operand should be encoded in the mod and regmem fields. | |
503 | Normally, it will be encoded in the reg field. We add a RegMem | |
504 | flag to indicate that it should be encoded in the regmem field. */ | |
505 | RegMem, | |
7e8b059b L |
506 | /* quick test if branch instruction is MPX supported */ |
507 | BNDPrefixOk, | |
52a6c1fe L |
508 | /* fake an extra reg operand for clr, imul and special register |
509 | processing for some instructions. */ | |
510 | RegKludge, | |
52a6c1fe L |
511 | /* An implicit xmm0 as the first operand */ |
512 | Implicit1stXmm0, | |
742732c7 JB |
513 | #define PrefixNone 0 |
514 | #define PrefixRep 1 | |
515 | #define PrefixHLERelease 2 /* Okay with an XRELEASE (0xf3) prefix. */ | |
516 | #define PrefixNoTrack 3 | |
517 | /* Prefixes implying "LOCK okay" must come after Lock. All others have | |
518 | to come before. */ | |
519 | #define PrefixLock 4 | |
520 | #define PrefixHLELock 5 /* Okay with a LOCK prefix. */ | |
521 | #define PrefixHLEAny 6 /* Okay with or without a LOCK prefix. */ | |
522 | PrefixOk, | |
52a6c1fe L |
523 | /* Convert to DWORD */ |
524 | ToDword, | |
525 | /* Convert to QWORD */ | |
526 | ToQword, | |
75c0a438 L |
527 | /* Address prefix changes register operand */ |
528 | AddrPrefixOpReg, | |
52a6c1fe L |
529 | /* opcode is a prefix */ |
530 | IsPrefix, | |
531 | /* instruction has extension in 8 bit imm */ | |
532 | ImmExt, | |
533 | /* instruction don't need Rex64 prefix. */ | |
534 | NoRex64, | |
52a6c1fe L |
535 | /* deprecated fp insn, gets a warning */ |
536 | Ugh, | |
57392598 CL |
537 | /* Intel AVX Instructions support via {vex} prefix */ |
538 | PseudoVexPrefix, | |
52a6c1fe | 539 | /* insn has VEX prefix: |
10c17abd | 540 | 1: 128bit VEX prefix (or operand dependent). |
2bf05e57 | 541 | 2: 256bit VEX prefix. |
712366da | 542 | 3: Scalar VEX prefix. |
52a6c1fe | 543 | */ |
712366da L |
544 | #define VEX128 1 |
545 | #define VEX256 2 | |
546 | #define VEXScalar 3 | |
52a6c1fe | 547 | Vex, |
2426c15f L |
548 | /* How to encode VEX.vvvv: |
549 | 0: VEX.vvvv must be 1111b. | |
a2a7d12c | 550 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
2426c15f | 551 | the content of source registers will be preserved. |
29c048b6 | 552 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
2426c15f L |
553 | where the content of first source register will be overwritten |
554 | by the result. | |
6c30d220 L |
555 | VEX.NDD2. The second destination register operand is encoded in |
556 | VEX.vvvv for instructions with 2 destination register operands. | |
557 | For assembler, there are no difference between VEX.NDS, VEX.DDS | |
558 | and VEX.NDD2. | |
559 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for | |
560 | instructions with 1 destination register operand. | |
2426c15f L |
561 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
562 | of the operands can access a memory location. | |
563 | */ | |
564 | #define VEXXDS 1 | |
565 | #define VEXNDD 2 | |
566 | #define VEXLWP 3 | |
567 | VexVVVV, | |
1ef99a7b L |
568 | /* How the VEX.W bit is used: |
569 | 0: Set by the REX.W bit. | |
570 | 1: VEX.W0. Should always be 0. | |
571 | 2: VEX.W1. Should always be 1. | |
6865c043 | 572 | 3: VEX.WIG. The VEX.W bit is ignored. |
1ef99a7b L |
573 | */ |
574 | #define VEXW0 1 | |
575 | #define VEXW1 2 | |
6865c043 | 576 | #define VEXWIG 3 |
1ef99a7b | 577 | VexW, |
441f6aca JB |
578 | /* Opcode encoding space (values chosen to be usable directly in |
579 | VEX/XOP mmmmm and EVEX mm fields): | |
580 | 0: Base opcode space. | |
581 | 1: 0F opcode prefix / space. | |
582 | 2: 0F38 opcode prefix / space. | |
583 | 3: 0F3A opcode prefix / space. | |
584 | 8: XOP 08 opcode space. | |
585 | 9: XOP 09 opcode space. | |
586 | A: XOP 0A opcode space. | |
587 | */ | |
588 | #define SPACE_BASE 0 | |
589 | #define SPACE_0F 1 | |
590 | #define SPACE_0F38 2 | |
591 | #define SPACE_0F3A 3 | |
592 | #define SPACE_XOP08 8 | |
593 | #define SPACE_XOP09 9 | |
594 | #define SPACE_XOP0A 0xA | |
595 | OpcodeSpace, | |
b933fa4b JB |
596 | /* Opcode prefix (values chosen to be usable directly in |
597 | VEX/XOP/EVEX pp fields): | |
7b47a312 L |
598 | 0: None |
599 | 1: Add 0x66 opcode prefix. | |
b933fa4b JB |
600 | 2: Add 0xf3 opcode prefix. |
601 | 3: Add 0xf2 opcode prefix. | |
7b47a312 L |
602 | */ |
603 | #define PREFIX_NONE 0 | |
604 | #define PREFIX_0X66 1 | |
b933fa4b JB |
605 | #define PREFIX_0XF3 2 |
606 | #define PREFIX_0XF2 3 | |
7b47a312 | 607 | OpcodePrefix, |
8cd7925b | 608 | /* number of VEX source operands: |
8c43a48b L |
609 | 0: <= 2 source operands. |
610 | 1: 2 XOP source operands. | |
8cd7925b L |
611 | 2: 3 source operands. |
612 | */ | |
8c43a48b | 613 | #define XOP2SOURCES 1 |
8cd7925b L |
614 | #define VEX3SOURCES 2 |
615 | VexSources, | |
63112cd6 | 616 | /* Instruction with a mandatory SIB byte: |
6c30d220 L |
617 | 1: 128bit vector register. |
618 | 2: 256bit vector register. | |
43234a1e | 619 | 3: 512bit vector register. |
6c30d220 | 620 | */ |
63112cd6 L |
621 | #define VECSIB128 1 |
622 | #define VECSIB256 2 | |
623 | #define VECSIB512 3 | |
260cd341 | 624 | #define SIBMEM 4 |
63112cd6 | 625 | SIB, |
260cd341 | 626 | |
52a6c1fe L |
627 | /* SSE to AVX support required */ |
628 | SSE2AVX, | |
629 | /* No AVX equivalent */ | |
630 | NoAVX, | |
43234a1e L |
631 | |
632 | /* insn has EVEX prefix: | |
633 | 1: 512bit EVEX prefix. | |
634 | 2: 128bit EVEX prefix. | |
635 | 3: 256bit EVEX prefix. | |
636 | 4: Length-ignored (LIG) EVEX prefix. | |
e771e7c9 | 637 | 5: Length determined from actual operands. |
43234a1e L |
638 | */ |
639 | #define EVEX512 1 | |
640 | #define EVEX128 2 | |
641 | #define EVEX256 3 | |
642 | #define EVEXLIG 4 | |
e771e7c9 | 643 | #define EVEXDYN 5 |
43234a1e L |
644 | EVex, |
645 | ||
646 | /* AVX512 masking support: | |
ae2387fe | 647 | 1: Zeroing or merging masking depending on operands. |
43234a1e L |
648 | 2: Merging-masking. |
649 | 3: Both zeroing and merging masking. | |
650 | */ | |
ae2387fe | 651 | #define DYNAMIC_MASKING 1 |
43234a1e L |
652 | #define MERGING_MASKING 2 |
653 | #define BOTH_MASKING 3 | |
654 | Masking, | |
655 | ||
4a1b91ea L |
656 | /* AVX512 broadcast support. The number of bytes to broadcast is |
657 | 1 << (Broadcast - 1): | |
658 | 1: Byte broadcast. | |
659 | 2: Word broadcast. | |
660 | 3: Dword broadcast. | |
661 | 4: Qword broadcast. | |
662 | */ | |
663 | #define BYTE_BROADCAST 1 | |
664 | #define WORD_BROADCAST 2 | |
665 | #define DWORD_BROADCAST 3 | |
666 | #define QWORD_BROADCAST 4 | |
43234a1e L |
667 | Broadcast, |
668 | ||
669 | /* Static rounding control is supported. */ | |
670 | StaticRounding, | |
671 | ||
672 | /* Supress All Exceptions is supported. */ | |
673 | SAE, | |
674 | ||
7091c612 JB |
675 | /* Compressed Disp8*N attribute. */ |
676 | #define DISP8_SHIFT_VL 7 | |
43234a1e L |
677 | Disp8MemShift, |
678 | ||
679 | /* Default mask isn't allowed. */ | |
680 | NoDefMask, | |
681 | ||
920d2ddc IT |
682 | /* The second operand must be a vector register, {x,y,z}mmN, where N is a multiple of 4. |
683 | It implicitly denotes the register group of {x,y,z}mmN - {x,y,z}mm(N + 3). | |
684 | */ | |
685 | ImplicitQuadGroup, | |
686 | ||
c2ecccb3 L |
687 | /* Two source operands are swapped. */ |
688 | SwapSources, | |
689 | ||
b6f8c7c4 L |
690 | /* Support encoding optimization. */ |
691 | Optimize, | |
692 | ||
52a6c1fe L |
693 | /* AT&T mnemonic. */ |
694 | ATTMnemonic, | |
695 | /* AT&T syntax. */ | |
696 | ATTSyntax, | |
697 | /* Intel syntax. */ | |
698 | IntelSyntax, | |
4b5aaf5f L |
699 | /* ISA64: Don't change the order without other code adjustments. |
700 | 0: Common to AMD64 and Intel64. | |
701 | 1: AMD64. | |
702 | 2: Intel64. | |
703 | 3: Only in Intel64. | |
704 | */ | |
705 | #define AMD64 1 | |
706 | #define INTEL64 2 | |
707 | #define INTEL64ONLY 3 | |
708 | ISA64, | |
52a6c1fe | 709 | /* The last bitfield in i386_opcode_modifier. */ |
1d942ae9 | 710 | Opcode_Modifier_Num |
52a6c1fe | 711 | }; |
40fb9820 L |
712 | |
713 | typedef struct i386_opcode_modifier | |
714 | { | |
715 | unsigned int d:1; | |
716 | unsigned int w:1; | |
86fa6981 | 717 | unsigned int load:1; |
40fb9820 | 718 | unsigned int modrm:1; |
0cfa3eb3 | 719 | unsigned int jump:3; |
40fb9820 L |
720 | unsigned int floatmf:1; |
721 | unsigned int floatr:1; | |
673fe0f0 | 722 | unsigned int size:2; |
56ffb741 | 723 | unsigned int checkregsize:1; |
3cd7f3e3 | 724 | unsigned int mnemonicsize:2; |
601e8564 | 725 | unsigned int anysize:1; |
40fb9820 L |
726 | unsigned int no_bsuf:1; |
727 | unsigned int no_wsuf:1; | |
728 | unsigned int no_lsuf:1; | |
729 | unsigned int no_ssuf:1; | |
730 | unsigned int no_qsuf:1; | |
7ce189b3 | 731 | unsigned int no_ldsuf:1; |
40fb9820 | 732 | unsigned int fwait:1; |
51c8edf6 | 733 | unsigned int isstring:2; |
dfd69174 | 734 | unsigned int regmem:1; |
7e8b059b | 735 | unsigned int bndprefixok:1; |
40fb9820 | 736 | unsigned int regkludge:1; |
c0f3af97 | 737 | unsigned int implicit1stxmm0:1; |
742732c7 | 738 | unsigned int prefixok:3; |
ca61edf2 L |
739 | unsigned int todword:1; |
740 | unsigned int toqword:1; | |
75c0a438 | 741 | unsigned int addrprefixopreg:1; |
40fb9820 L |
742 | unsigned int isprefix:1; |
743 | unsigned int immext:1; | |
744 | unsigned int norex64:1; | |
40fb9820 | 745 | unsigned int ugh:1; |
57392598 | 746 | unsigned int pseudovexprefix:1; |
2bf05e57 | 747 | unsigned int vex:2; |
2426c15f | 748 | unsigned int vexvvvv:2; |
1ef99a7b | 749 | unsigned int vexw:2; |
441f6aca JB |
750 | unsigned int opcodespace:4; |
751 | unsigned int opcodeprefix:2; | |
8cd7925b | 752 | unsigned int vexsources:2; |
260cd341 | 753 | unsigned int sib:3; |
c0f3af97 | 754 | unsigned int sse2avx:1; |
81f8a913 | 755 | unsigned int noavx:1; |
43234a1e L |
756 | unsigned int evex:3; |
757 | unsigned int masking:2; | |
4a1b91ea | 758 | unsigned int broadcast:3; |
43234a1e L |
759 | unsigned int staticrounding:1; |
760 | unsigned int sae:1; | |
761 | unsigned int disp8memshift:3; | |
762 | unsigned int nodefmask:1; | |
920d2ddc | 763 | unsigned int implicitquadgroup:1; |
c2ecccb3 | 764 | unsigned int swapsources:1; |
b6f8c7c4 | 765 | unsigned int optimize:1; |
1efbbeb4 | 766 | unsigned int attmnemonic:1; |
e1d4d893 | 767 | unsigned int attsyntax:1; |
5c07affc | 768 | unsigned int intelsyntax:1; |
4b5aaf5f | 769 | unsigned int isa64:2; |
40fb9820 L |
770 | } i386_opcode_modifier; |
771 | ||
bab6aec1 JB |
772 | /* Operand classes. */ |
773 | ||
774 | #define CLASS_WIDTH 4 | |
775 | enum operand_class | |
776 | { | |
777 | ClassNone, | |
778 | Reg, /* GPRs and FP regs, distinguished by operand size */ | |
00cee14f | 779 | SReg, /* Segment register */ |
4a5c67ed JB |
780 | RegCR, /* Control register */ |
781 | RegDR, /* Debug register */ | |
782 | RegTR, /* Test register */ | |
3528c362 JB |
783 | RegMMX, /* MMX register */ |
784 | RegSIMD, /* XMM/YMM/ZMM registers, distinguished by operand size */ | |
f74a6307 JB |
785 | RegMask, /* Vector Mask register */ |
786 | RegBND, /* Bound register */ | |
bab6aec1 JB |
787 | }; |
788 | ||
75e5731b JB |
789 | /* Special operand instances. */ |
790 | ||
791 | #define INSTANCE_WIDTH 3 | |
792 | enum operand_instance | |
793 | { | |
794 | InstanceNone, | |
795 | Accum, /* Accumulator %al/%ax/%eax/%rax/%st(0)/%xmm0 */ | |
474da251 JB |
796 | RegC, /* %cl / %cx / %ecx / %rcx, e.g. register to hold shift count */ |
797 | RegD, /* %dl / %dx / %edx / %rdx, e.g. register to hold I/O port addr */ | |
798 | RegB, /* %bl / %bx / %ebx / %rbx */ | |
75e5731b JB |
799 | }; |
800 | ||
40fb9820 L |
801 | /* Position of operand_type bits. */ |
802 | ||
52a6c1fe L |
803 | enum |
804 | { | |
75e5731b JB |
805 | /* Class and Instance */ |
806 | ClassInstance = CLASS_WIDTH + INSTANCE_WIDTH - 1, | |
52a6c1fe L |
807 | /* 1 bit immediate */ |
808 | Imm1, | |
809 | /* 8 bit immediate */ | |
810 | Imm8, | |
811 | /* 8 bit immediate sign extended */ | |
812 | Imm8S, | |
813 | /* 16 bit immediate */ | |
814 | Imm16, | |
815 | /* 32 bit immediate */ | |
816 | Imm32, | |
817 | /* 32 bit immediate sign extended */ | |
818 | Imm32S, | |
819 | /* 64 bit immediate */ | |
820 | Imm64, | |
821 | /* 8bit/16bit/32bit displacements are used in different ways, | |
822 | depending on the instruction. For jumps, they specify the | |
823 | size of the PC relative displacement, for instructions with | |
824 | memory operand, they specify the size of the offset relative | |
825 | to the base register, and for instructions with memory offset | |
826 | such as `mov 1234,%al' they specify the size of the offset | |
827 | relative to the segment base. */ | |
828 | /* 8 bit displacement */ | |
829 | Disp8, | |
830 | /* 16 bit displacement */ | |
831 | Disp16, | |
832 | /* 32 bit displacement */ | |
833 | Disp32, | |
834 | /* 32 bit signed displacement */ | |
835 | Disp32S, | |
836 | /* 64 bit displacement */ | |
837 | Disp64, | |
52a6c1fe L |
838 | /* Register which can be used for base or index in memory operand. */ |
839 | BaseIndex, | |
11a322db | 840 | /* BYTE size. */ |
52a6c1fe | 841 | Byte, |
11a322db | 842 | /* WORD size. 2 byte */ |
52a6c1fe | 843 | Word, |
11a322db | 844 | /* DWORD size. 4 byte */ |
52a6c1fe | 845 | Dword, |
11a322db | 846 | /* FWORD size. 6 byte */ |
52a6c1fe | 847 | Fword, |
11a322db | 848 | /* QWORD size. 8 byte */ |
52a6c1fe | 849 | Qword, |
11a322db | 850 | /* TBYTE size. 10 byte */ |
52a6c1fe | 851 | Tbyte, |
11a322db | 852 | /* XMMWORD size. */ |
52a6c1fe | 853 | Xmmword, |
11a322db | 854 | /* YMMWORD size. */ |
52a6c1fe | 855 | Ymmword, |
11a322db | 856 | /* ZMMWORD size. */ |
43234a1e | 857 | Zmmword, |
260cd341 LC |
858 | /* TMMWORD size. */ |
859 | Tmmword, | |
52a6c1fe L |
860 | /* Unspecified memory size. */ |
861 | Unspecified, | |
40fb9820 | 862 | |
bab6aec1 | 863 | /* The number of bits in i386_operand_type. */ |
f0a85b07 | 864 | OTNum |
52a6c1fe | 865 | }; |
40fb9820 L |
866 | |
867 | #define OTNumOfUints \ | |
f0a85b07 | 868 | ((OTNum - 1) / sizeof (unsigned int) / CHAR_BIT + 1) |
40fb9820 L |
869 | #define OTNumOfBits \ |
870 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) | |
871 | ||
872 | /* If you get a compiler error for zero width of the unused field, | |
601e8564 | 873 | comment it out. */ |
f0a85b07 | 874 | #define OTUnused OTNum |
40fb9820 L |
875 | |
876 | typedef union i386_operand_type | |
877 | { | |
878 | struct | |
879 | { | |
bab6aec1 | 880 | unsigned int class:CLASS_WIDTH; |
75e5731b | 881 | unsigned int instance:INSTANCE_WIDTH; |
7d5e4556 | 882 | unsigned int imm1:1; |
40fb9820 L |
883 | unsigned int imm8:1; |
884 | unsigned int imm8s:1; | |
885 | unsigned int imm16:1; | |
886 | unsigned int imm32:1; | |
887 | unsigned int imm32s:1; | |
888 | unsigned int imm64:1; | |
40fb9820 L |
889 | unsigned int disp8:1; |
890 | unsigned int disp16:1; | |
891 | unsigned int disp32:1; | |
892 | unsigned int disp32s:1; | |
893 | unsigned int disp64:1; | |
7d5e4556 | 894 | unsigned int baseindex:1; |
7d5e4556 L |
895 | unsigned int byte:1; |
896 | unsigned int word:1; | |
897 | unsigned int dword:1; | |
898 | unsigned int fword:1; | |
899 | unsigned int qword:1; | |
900 | unsigned int tbyte:1; | |
901 | unsigned int xmmword:1; | |
c0f3af97 | 902 | unsigned int ymmword:1; |
43234a1e | 903 | unsigned int zmmword:1; |
260cd341 | 904 | unsigned int tmmword:1; |
7d5e4556 | 905 | unsigned int unspecified:1; |
40fb9820 L |
906 | #ifdef OTUnused |
907 | unsigned int unused:(OTNumOfBits - OTUnused); | |
908 | #endif | |
909 | } bitfield; | |
910 | unsigned int array[OTNumOfUints]; | |
911 | } i386_operand_type; | |
0b1cf022 | 912 | |
d3ce72d0 | 913 | typedef struct insn_template |
0b1cf022 L |
914 | { |
915 | /* instruction name sans width suffix ("mov" for movl insns) */ | |
916 | char *name; | |
917 | ||
0b1cf022 L |
918 | /* base_opcode is the fundamental opcode byte without optional |
919 | prefix(es). */ | |
9df6f676 | 920 | unsigned int base_opcode:16; |
0b1cf022 L |
921 | #define Opcode_D 0x2 /* Direction bit: |
922 | set if Reg --> Regmem; | |
923 | unset if Regmem --> Reg. */ | |
924 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ | |
925 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ | |
dbbc8b7e JB |
926 | #define Opcode_SIMD_FloatD 0x1 /* Direction bit for SIMD fp insns. */ |
927 | #define Opcode_SIMD_IntD 0x10 /* Direction bit for SIMD int insns. */ | |
0b1cf022 | 928 | |
31184569 JB |
929 | /* (Fake) base opcode value for pseudo prefixes. */ |
930 | #define PSEUDO_PREFIX 0 | |
931 | ||
932 | /* extension_opcode is the 3 bit extension for group <n> insns. | |
933 | This field is also used to store the 8-bit opcode suffix for the | |
934 | AMD 3DNow! instructions. | |
935 | If this template has no extension opcode (the usual case) use None | |
936 | Instructions */ | |
9df6f676 JB |
937 | signed int extension_opcode:9; |
938 | #define None (-1) /* If no extension_opcode is possible. */ | |
31184569 | 939 | |
41eb8e88 L |
940 | /* Pseudo prefixes. */ |
941 | #define Prefix_Disp8 0 /* {disp8} */ | |
942 | #define Prefix_Disp16 1 /* {disp16} */ | |
943 | #define Prefix_Disp32 2 /* {disp32} */ | |
944 | #define Prefix_Load 3 /* {load} */ | |
945 | #define Prefix_Store 4 /* {store} */ | |
946 | #define Prefix_VEX 5 /* {vex} */ | |
947 | #define Prefix_VEX3 6 /* {vex3} */ | |
948 | #define Prefix_EVEX 7 /* {evex} */ | |
949 | #define Prefix_REX 8 /* {rex} */ | |
950 | #define Prefix_NoOptimize 9 /* {nooptimize} */ | |
951 | ||
a2cebd03 | 952 | /* how many operands */ |
9df6f676 | 953 | unsigned int operands:3; |
a2cebd03 | 954 | |
0b1cf022 L |
955 | /* the bits in opcode_modifier are used to generate the final opcode from |
956 | the base_opcode. These bits also are used to detect alternate forms of | |
957 | the same instruction */ | |
40fb9820 | 958 | i386_opcode_modifier opcode_modifier; |
0b1cf022 | 959 | |
dac10fb0 JB |
960 | /* cpu feature flags */ |
961 | i386_cpu_flags cpu_flags; | |
962 | ||
0b1cf022 L |
963 | /* operand_types[i] describes the type of operand i. This is made |
964 | by OR'ing together all of the possible type masks. (e.g. | |
965 | 'operand_types[i] = Reg|Imm' specifies that operand i can be | |
966 | either a register or an immediate operand. */ | |
40fb9820 | 967 | i386_operand_type operand_types[MAX_OPERANDS]; |
0b1cf022 | 968 | } |
d3ce72d0 | 969 | insn_template; |
0b1cf022 | 970 | |
d3ce72d0 | 971 | extern const insn_template i386_optab[]; |
0b1cf022 L |
972 | |
973 | /* these are for register name --> number & type hash lookup */ | |
974 | typedef struct | |
975 | { | |
8a6fb3f9 | 976 | const char *reg_name; |
40fb9820 | 977 | i386_operand_type reg_type; |
a60de03c | 978 | unsigned char reg_flags; |
0b1cf022 L |
979 | #define RegRex 0x1 /* Extended register. */ |
980 | #define RegRex64 0x2 /* Extended 8 bit register. */ | |
43234a1e | 981 | #define RegVRex 0x4 /* Extended vector register. */ |
a60de03c | 982 | unsigned char reg_num; |
e968fc9b | 983 | #define RegIP ((unsigned char ) ~0) |
db51cc60 | 984 | /* EIZ and RIZ are fake index registers. */ |
e968fc9b | 985 | #define RegIZ (RegIP - 1) |
b7240065 JB |
986 | /* FLAT is a fake segment register (Intel mode). */ |
987 | #define RegFlat ((unsigned char) ~0) | |
a60de03c JB |
988 | signed char dw2_regnum[2]; |
989 | #define Dw2Inval (-1) | |
0b1cf022 L |
990 | } |
991 | reg_entry; | |
992 | ||
993 | /* Entries in i386_regtab. */ | |
6288d05f JB |
994 | #define REGNAM_AL 0 |
995 | #define REGNAM_AX 24 | |
996 | #define REGNAM_EAX 40 | |
0b1cf022 L |
997 | |
998 | extern const reg_entry i386_regtab[]; | |
c3fe08fa | 999 | extern const unsigned int i386_regtab_size; |
0b1cf022 L |
1000 | |
1001 | typedef struct | |
1002 | { | |
1003 | char *seg_name; | |
1004 | unsigned int seg_prefix; | |
1005 | } | |
1006 | seg_entry; | |
1007 | ||
1008 | extern const seg_entry cs; | |
1009 | extern const seg_entry ds; | |
1010 | extern const seg_entry ss; | |
1011 | extern const seg_entry es; | |
1012 | extern const seg_entry fs; | |
1013 | extern const seg_entry gs; |