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* Makefile.tpl: Rename [+target+] to [+make_target+].
[thirdparty/binutils-gdb.git] / opcodes / iq2000-desc.c
CommitLineData
47b1a55a
SC		 1/* CPU data for iq2000.
2
3THIS FILE IS MACHINE GENERATED WITH CGEN.
4
5Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002 Free Software Foundation, Inc.
6
7This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8
9This program is free software; you can redistribute it and/or modify
10it under the terms of the GNU General Public License as published by
11the Free Software Foundation; either version 2, or (at your option)
12any later version.
13
14This program is distributed in the hope that it will be useful,
15but WITHOUT ANY WARRANTY; without even the implied warranty of
16MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17GNU General Public License for more details.
18
19You should have received a copy of the GNU General Public License along
20with this program; if not, write to the Free Software Foundation, Inc.,
2159 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22
23*/
24
25#include "sysdep.h"
26#include <ctype.h>
27#include <stdio.h>
28#include <stdarg.h>
29#include "ansidecl.h"
30#include "bfd.h"
31#include "symcat.h"
32#include "iq2000-desc.h"
33#include "iq2000-opc.h"
34#include "opintl.h"
35#include "libiberty.h"
36
37/* Attributes. */
38
39static const CGEN_ATTR_ENTRY bool_attr[] =
40{
41 { "#f", 0 },
42 { "#t", 1 },
43 { 0, 0 }
44};
45
46static const CGEN_ATTR_ENTRY MACH_attr[] =
47{
48 { "base", MACH_BASE },
49 { "iq2000", MACH_IQ2000 },
50 { "iq10", MACH_IQ10 },
51 { "max", MACH_MAX },
52 { 0, 0 }
53};
54
55static const CGEN_ATTR_ENTRY ISA_attr[] =
56{
57 { "iq2000", ISA_IQ2000 },
58 { "max", ISA_MAX },
59 { 0, 0 }
60};
61
62const CGEN_ATTR_TABLE iq2000_cgen_ifield_attr_table[] =
63{
64 { "MACH", & MACH_attr[0], & MACH_attr[0] },
65 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
66 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
67 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
68 { "RESERVED", &bool_attr[0], &bool_attr[0] },
69 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
70 { "SIGNED", &bool_attr[0], &bool_attr[0] },
71 { 0, 0, 0 }
72};
73
74const CGEN_ATTR_TABLE iq2000_cgen_hardware_attr_table[] =
75{
76 { "MACH", & MACH_attr[0], & MACH_attr[0] },
77 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
78 { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
79 { "PC", &bool_attr[0], &bool_attr[0] },
80 { "PROFILE", &bool_attr[0], &bool_attr[0] },
81 { 0, 0, 0 }
82};
83
84const CGEN_ATTR_TABLE iq2000_cgen_operand_attr_table[] =
85{
86 { "MACH", & MACH_attr[0], & MACH_attr[0] },
87 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
88 { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
89 { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
90 { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
91 { "SIGNED", &bool_attr[0], &bool_attr[0] },
92 { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
93 { "RELAX", &bool_attr[0], &bool_attr[0] },
94 { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
95 { 0, 0, 0 }
96};
97
98const CGEN_ATTR_TABLE iq2000_cgen_insn_attr_table[] =
99{
100 { "MACH", & MACH_attr[0], & MACH_attr[0] },
101 { "ALIAS", &bool_attr[0], &bool_attr[0] },
102 { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
103 { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
104 { "COND-CTI", &bool_attr[0], &bool_attr[0] },
105 { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
106 { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
107 { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
108 { "RELAX", &bool_attr[0], &bool_attr[0] },
109 { "NO-DIS", &bool_attr[0], &bool_attr[0] },
110 { "PBB", &bool_attr[0], &bool_attr[0] },
111 { "YIELD-INSN", &bool_attr[0], &bool_attr[0] },
112 { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
113 { "EVEN-REG-NUM", &bool_attr[0], &bool_attr[0] },
114 { "UNSUPPORTED", &bool_attr[0], &bool_attr[0] },
115 { "USES-RD", &bool_attr[0], &bool_attr[0] },
116 { "USES-RS", &bool_attr[0], &bool_attr[0] },
117 { "USES-RT", &bool_attr[0], &bool_attr[0] },
118 { "USES-R31", &bool_attr[0], &bool_attr[0] },
119 { 0, 0, 0 }
120};
121
122/* Instruction set variants. */
123
124static const CGEN_ISA iq2000_cgen_isa_table[] = {
125 { "iq2000", 32, 32, 32, 32 },
126 { 0, 0, 0, 0, 0 }
127};
128
129/* Machine variants. */
130
131static const CGEN_MACH iq2000_cgen_mach_table[] = {
132 { "iq2000", "iq2000", MACH_IQ2000, 0 },
133 { "iq10", "iq10", MACH_IQ10, 0 },
134 { 0, 0, 0, 0 }
135};
136
137static CGEN_KEYWORD_ENTRY iq2000_cgen_opval_gr_names_entries[] =
138{
139 { "r0", 0, {0, {0}}, 0, 0 },
140 { "%0", 0, {0, {0}}, 0, 0 },
141 { "r1", 1, {0, {0}}, 0, 0 },
142 { "%1", 1, {0, {0}}, 0, 0 },
143 { "r2", 2, {0, {0}}, 0, 0 },
144 { "%2", 2, {0, {0}}, 0, 0 },
145 { "r3", 3, {0, {0}}, 0, 0 },
146 { "%3", 3, {0, {0}}, 0, 0 },
147 { "r4", 4, {0, {0}}, 0, 0 },
148 { "%4", 4, {0, {0}}, 0, 0 },
149 { "r5", 5, {0, {0}}, 0, 0 },
150 { "%5", 5, {0, {0}}, 0, 0 },
151 { "r6", 6, {0, {0}}, 0, 0 },
152 { "%6", 6, {0, {0}}, 0, 0 },
153 { "r7", 7, {0, {0}}, 0, 0 },
154 { "%7", 7, {0, {0}}, 0, 0 },
155 { "r8", 8, {0, {0}}, 0, 0 },
156 { "%8", 8, {0, {0}}, 0, 0 },
157 { "r9", 9, {0, {0}}, 0, 0 },
158 { "%9", 9, {0, {0}}, 0, 0 },
159 { "r10", 10, {0, {0}}, 0, 0 },
160 { "%10", 10, {0, {0}}, 0, 0 },
161 { "r11", 11, {0, {0}}, 0, 0 },
162 { "%11", 11, {0, {0}}, 0, 0 },
163 { "r12", 12, {0, {0}}, 0, 0 },
164 { "%12", 12, {0, {0}}, 0, 0 },
165 { "r13", 13, {0, {0}}, 0, 0 },
166 { "%13", 13, {0, {0}}, 0, 0 },
167 { "r14", 14, {0, {0}}, 0, 0 },
168 { "%14", 14, {0, {0}}, 0, 0 },
169 { "r15", 15, {0, {0}}, 0, 0 },
170 { "%15", 15, {0, {0}}, 0, 0 },
171 { "r16", 16, {0, {0}}, 0, 0 },
172 { "%16", 16, {0, {0}}, 0, 0 },
173 { "r17", 17, {0, {0}}, 0, 0 },
174 { "%17", 17, {0, {0}}, 0, 0 },
175 { "r18", 18, {0, {0}}, 0, 0 },
176 { "%18", 18, {0, {0}}, 0, 0 },
177 { "r19", 19, {0, {0}}, 0, 0 },
178 { "%19", 19, {0, {0}}, 0, 0 },
179 { "r20", 20, {0, {0}}, 0, 0 },
180 { "%20", 20, {0, {0}}, 0, 0 },
181 { "r21", 21, {0, {0}}, 0, 0 },
182 { "%21", 21, {0, {0}}, 0, 0 },
183 { "r22", 22, {0, {0}}, 0, 0 },
184 { "%22", 22, {0, {0}}, 0, 0 },
185 { "r23", 23, {0, {0}}, 0, 0 },
186 { "%23", 23, {0, {0}}, 0, 0 },
187 { "r24", 24, {0, {0}}, 0, 0 },
188 { "%24", 24, {0, {0}}, 0, 0 },
189 { "r25", 25, {0, {0}}, 0, 0 },
190 { "%25", 25, {0, {0}}, 0, 0 },
191 { "r26", 26, {0, {0}}, 0, 0 },
192 { "%26", 26, {0, {0}}, 0, 0 },
193 { "r27", 27, {0, {0}}, 0, 0 },
194 { "%27", 27, {0, {0}}, 0, 0 },
195 { "r28", 28, {0, {0}}, 0, 0 },
196 { "%28", 28, {0, {0}}, 0, 0 },
197 { "r29", 29, {0, {0}}, 0, 0 },
198 { "%29", 29, {0, {0}}, 0, 0 },
199 { "r30", 30, {0, {0}}, 0, 0 },
200 { "%30", 30, {0, {0}}, 0, 0 },
201 { "r31", 31, {0, {0}}, 0, 0 },
202 { "%31", 31, {0, {0}}, 0, 0 }
203};
204
205CGEN_KEYWORD iq2000_cgen_opval_gr_names =
206{
207 & iq2000_cgen_opval_gr_names_entries[0],
208 64,
209 0, 0, 0, 0, ""
210};
211
212
213/* The hardware table. */
214
215#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
216#define A(a) (1 << CGEN_HW_##a)
217#else
218#define A(a) (1 << CGEN_HW_/**/a)
219#endif
220
221const CGEN_HW_ENTRY iq2000_cgen_hw_table[] =
222{
223 { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
224 { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
225 { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
226 { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
227 { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
228 { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
229 { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & iq2000_cgen_opval_gr_names, { 0, { (1<<MACH_BASE) } } },
230 { 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
231};
232
233#undef A
234
235
236/* The instruction field table. */
237
238#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
239#define A(a) (1 << CGEN_IFLD_##a)
240#else
241#define A(a) (1 << CGEN_IFLD_/**/a)
242#endif
243
244const CGEN_IFLD iq2000_cgen_ifld_table[] =
245{
246 { IQ2000_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
247 { IQ2000_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
248 { IQ2000_F_OPCODE, "f-opcode", 0, 32, 31, 6, { 0, { (1<<MACH_BASE) } } },
249 { IQ2000_F_RS, "f-rs", 0, 32, 25, 5, { 0, { (1<<MACH_BASE) } } },
250 { IQ2000_F_RT, "f-rt", 0, 32, 20, 5, { 0, { (1<<MACH_BASE) } } },
251 { IQ2000_F_RD, "f-rd", 0, 32, 15, 5, { 0, { (1<<MACH_BASE) } } },
252 { IQ2000_F_SHAMT, "f-shamt", 0, 32, 10, 5, { 0, { (1<<MACH_BASE) } } },
253 { IQ2000_F_CP_OP, "f-cp-op", 0, 32, 10, 3, { 0, { (1<<MACH_BASE) } } },
254 { IQ2000_F_CP_OP_10, "f-cp-op-10", 0, 32, 10, 5, { 0, { (1<<MACH_BASE) } } },
255 { IQ2000_F_CP_GRP, "f-cp-grp", 0, 32, 7, 2, { 0, { (1<<MACH_BASE) } } },
256 { IQ2000_F_FUNC, "f-func", 0, 32, 5, 6, { 0, { (1<<MACH_BASE) } } },
257 { IQ2000_F_IMM, "f-imm", 0, 32, 15, 16, { 0, { (1<<MACH_BASE) } } },
258 { IQ2000_F_JTARG, "f-jtarg", 0, 32, 15, 16, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
259 { IQ2000_F_JTARGQ10, "f-jtargq10", 0, 32, 20, 21, { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
260 { IQ2000_F_OFFSET, "f-offset", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
261 { IQ2000_F_COUNT, "f-count", 0, 32, 15, 7, { 0, { (1<<MACH_BASE) } } },
262 { IQ2000_F_BYTECOUNT, "f-bytecount", 0, 32, 7, 8, { 0, { (1<<MACH_BASE) } } },
263 { IQ2000_F_INDEX, "f-index", 0, 32, 8, 9, { 0, { (1<<MACH_BASE) } } },
264 { IQ2000_F_MASK, "f-mask", 0, 32, 9, 4, { 0, { (1<<MACH_BASE) } } },
265 { IQ2000_F_MASKQ10, "f-maskq10", 0, 32, 10, 5, { 0, { (1<<MACH_BASE) } } },
266 { IQ2000_F_MASKL, "f-maskl", 0, 32, 4, 5, { 0, { (1<<MACH_BASE) } } },
267 { IQ2000_F_EXCODE, "f-excode", 0, 32, 25, 20, { 0, { (1<<MACH_BASE) } } },
268 { IQ2000_F_RSRVD, "f-rsrvd", 0, 32, 25, 10, { 0, { (1<<MACH_BASE) } } },
269 { IQ2000_F_10_11, "f-10-11", 0, 32, 10, 11, { 0, { (1<<MACH_BASE) } } },
270 { IQ2000_F_24_19, "f-24-19", 0, 32, 24, 19, { 0, { (1<<MACH_BASE) } } },
271 { IQ2000_F_5, "f-5", 0, 32, 5, 1, { 0, { (1<<MACH_BASE) } } },
272 { IQ2000_F_10, "f-10", 0, 32, 10, 1, { 0, { (1<<MACH_BASE) } } },
273 { IQ2000_F_25, "f-25", 0, 32, 25, 1, { 0, { (1<<MACH_BASE) } } },
274 { IQ2000_F_CAM_Z, "f-cam-z", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
275 { IQ2000_F_CAM_Y, "f-cam-y", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } },
276 { IQ2000_F_CM_3FUNC, "f-cm-3func", 0, 32, 5, 3, { 0, { (1<<MACH_BASE) } } },
277 { IQ2000_F_CM_4FUNC, "f-cm-4func", 0, 32, 5, 4, { 0, { (1<<MACH_BASE) } } },
278 { IQ2000_F_CM_3Z, "f-cm-3z", 0, 32, 1, 2, { 0, { (1<<MACH_BASE) } } },
279 { IQ2000_F_CM_4Z, "f-cm-4z", 0, 32, 2, 3, { 0, { (1<<MACH_BASE) } } },
280 { 0, 0, 0, 0, 0, 0, {0, {0}} }
281};
282
283#undef A
284
285
286
287/* multi ifield declarations */
288
289const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [];
290const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [];
291const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [];
292
293
294/* multi ifield definitions */
295
296const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RS_MULTI_IFIELD [] =
297{
298 { 0, { (void *) &(iq2000_cgen_ifld_table[5])} },
299 { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
300 {0,{0}}
301};
302const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RD_RT_MULTI_IFIELD [] =
303{
304 { 0, { (void *) &(iq2000_cgen_ifld_table[5])} },
305 { 0, { (void *) &(iq2000_cgen_ifld_table[4])} },
306 {0,{0}}
307};
308const CGEN_MAYBE_MULTI_IFLD IQ2000_F_RT_RS_MULTI_IFIELD [] =
309{
310 { 0, { (void *) &(iq2000_cgen_ifld_table[4])} },
311 { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
312 {0,{0}}
313};
314
315/* The operand table. */
316
317#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
318#define A(a) (1 << CGEN_OPERAND_##a)
319#else
320#define A(a) (1 << CGEN_OPERAND_/**/a)
321#endif
322#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
323#define OPERAND(op) IQ2000_OPERAND_##op
324#else
325#define OPERAND(op) IQ2000_OPERAND_/**/op
326#endif
327
328const CGEN_OPERAND iq2000_cgen_operand_table[] =
329{
330/* pc: program counter */
331 { "pc", IQ2000_OPERAND_PC, HW_H_PC, 0, 0,
332 { 0, { (void *) &(iq2000_cgen_ifld_table[0])} },
333 { 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
334/* rs: register Rs */
335 { "rs", IQ2000_OPERAND_RS, HW_H_GR, 25, 5,
336 { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
337 { 0, { (1<<MACH_BASE) } } },
338/* rt: register Rt */
339 { "rt", IQ2000_OPERAND_RT, HW_H_GR, 20, 5,
340 { 0, { (void *) &(iq2000_cgen_ifld_table[4])} },
341 { 0, { (1<<MACH_BASE) } } },
342/* rd: register Rd */
343 { "rd", IQ2000_OPERAND_RD, HW_H_GR, 15, 5,
344 { 0, { (void *) &(iq2000_cgen_ifld_table[5])} },
345 { 0, { (1<<MACH_BASE) } } },
346/* rd-rs: register Rd from Rs */
347 { "rd-rs", IQ2000_OPERAND_RD_RS, HW_H_GR, 15, 10,
348 { 2, { (void *) &(IQ2000_F_RD_RS_MULTI_IFIELD[0])} },
349 { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
350/* rd-rt: register Rd from Rt */
351 { "rd-rt", IQ2000_OPERAND_RD_RT, HW_H_GR, 15, 10,
352 { 2, { (void *) &(IQ2000_F_RD_RT_MULTI_IFIELD[0])} },
353 { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
354/* rt-rs: register Rt from Rs */
355 { "rt-rs", IQ2000_OPERAND_RT_RS, HW_H_GR, 20, 10,
356 { 2, { (void *) &(IQ2000_F_RT_RS_MULTI_IFIELD[0])} },
357 { 0|A(VIRTUAL), { (1<<MACH_BASE) } } },
358/* shamt: shift amount */
359 { "shamt", IQ2000_OPERAND_SHAMT, HW_H_UINT, 10, 5,
360 { 0, { (void *) &(iq2000_cgen_ifld_table[6])} },
361 { 0, { (1<<MACH_BASE) } } },
362/* imm: immediate */
363 { "imm", IQ2000_OPERAND_IMM, HW_H_UINT, 15, 16,
364 { 0, { (void *) &(iq2000_cgen_ifld_table[11])} },
365 { 0, { (1<<MACH_BASE) } } },
366/* offset: pc-relative offset */
367 { "offset", IQ2000_OPERAND_OFFSET, HW_H_IADDR, 15, 16,
368 { 0, { (void *) &(iq2000_cgen_ifld_table[14])} },
369 { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
370/* baseoff: base register offset */
371 { "baseoff", IQ2000_OPERAND_BASEOFF, HW_H_IADDR, 15, 16,
372 { 0, { (void *) &(iq2000_cgen_ifld_table[11])} },
373 { 0, { (1<<MACH_BASE) } } },
374/* jmptarg: jump target */
375 { "jmptarg", IQ2000_OPERAND_JMPTARG, HW_H_IADDR, 15, 16,
376 { 0, { (void *) &(iq2000_cgen_ifld_table[12])} },
377 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
378/* mask: mask */
379 { "mask", IQ2000_OPERAND_MASK, HW_H_UINT, 9, 4,
380 { 0, { (void *) &(iq2000_cgen_ifld_table[18])} },
381 { 0, { (1<<MACH_BASE) } } },
382/* maskq10: iq10 mask */
383 { "maskq10", IQ2000_OPERAND_MASKQ10, HW_H_UINT, 10, 5,
384 { 0, { (void *) &(iq2000_cgen_ifld_table[19])} },
385 { 0, { (1<<MACH_BASE) } } },
386/* maskl: mask left */
387 { "maskl", IQ2000_OPERAND_MASKL, HW_H_UINT, 4, 5,
388 { 0, { (void *) &(iq2000_cgen_ifld_table[20])} },
389 { 0, { (1<<MACH_BASE) } } },
390/* count: count */
391 { "count", IQ2000_OPERAND_COUNT, HW_H_UINT, 15, 7,
392 { 0, { (void *) &(iq2000_cgen_ifld_table[15])} },
393 { 0, { (1<<MACH_BASE) } } },
394/* index: index */
395 { "index", IQ2000_OPERAND_INDEX, HW_H_UINT, 8, 9,
396 { 0, { (void *) &(iq2000_cgen_ifld_table[17])} },
397 { 0, { (1<<MACH_BASE) } } },
398/* execode: execcode */
399 { "execode", IQ2000_OPERAND_EXECODE, HW_H_UINT, 25, 20,
400 { 0, { (void *) &(iq2000_cgen_ifld_table[21])} },
401 { 0, { (1<<MACH_BASE) } } },
402/* bytecount: byte count */
403 { "bytecount", IQ2000_OPERAND_BYTECOUNT, HW_H_UINT, 7, 8,
404 { 0, { (void *) &(iq2000_cgen_ifld_table[16])} },
405 { 0, { (1<<MACH_BASE) } } },
406/* cam-y: cam global opn y */
407 { "cam-y", IQ2000_OPERAND_CAM_Y, HW_H_UINT, 2, 3,
408 { 0, { (void *) &(iq2000_cgen_ifld_table[29])} },
409 { 0, { (1<<MACH_BASE) } } },
410/* cam-z: cam global mask z */
411 { "cam-z", IQ2000_OPERAND_CAM_Z, HW_H_UINT, 5, 3,
412 { 0, { (void *) &(iq2000_cgen_ifld_table[28])} },
413 { 0, { (1<<MACH_BASE) } } },
414/* cm-3func: CM 3 bit fn field */
415 { "cm-3func", IQ2000_OPERAND_CM_3FUNC, HW_H_UINT, 5, 3,
416 { 0, { (void *) &(iq2000_cgen_ifld_table[30])} },
417 { 0, { (1<<MACH_BASE) } } },
418/* cm-4func: CM 4 bit fn field */
419 { "cm-4func", IQ2000_OPERAND_CM_4FUNC, HW_H_UINT, 5, 4,
420 { 0, { (void *) &(iq2000_cgen_ifld_table[31])} },
421 { 0, { (1<<MACH_BASE) } } },
422/* cm-3z: CM 3 bit Z field */
423 { "cm-3z", IQ2000_OPERAND_CM_3Z, HW_H_UINT, 1, 2,
424 { 0, { (void *) &(iq2000_cgen_ifld_table[32])} },
425 { 0, { (1<<MACH_BASE) } } },
426/* cm-4z: CM 4 bit Z field */
427 { "cm-4z", IQ2000_OPERAND_CM_4Z, HW_H_UINT, 2, 3,
428 { 0, { (void *) &(iq2000_cgen_ifld_table[33])} },
429 { 0, { (1<<MACH_BASE) } } },
430/* base: base register */
431 { "base", IQ2000_OPERAND_BASE, HW_H_GR, 25, 5,
432 { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
433 { 0, { (1<<MACH_BASE) } } },
434/* maskr: mask right */
435 { "maskr", IQ2000_OPERAND_MASKR, HW_H_UINT, 25, 5,
436 { 0, { (void *) &(iq2000_cgen_ifld_table[3])} },
437 { 0, { (1<<MACH_BASE) } } },
438/* bitnum: bit number */
439 { "bitnum", IQ2000_OPERAND_BITNUM, HW_H_UINT, 20, 5,
440 { 0, { (void *) &(iq2000_cgen_ifld_table[4])} },
441 { 0, { (1<<MACH_BASE) } } },
442/* hi16: high 16 bit immediate */
443 { "hi16", IQ2000_OPERAND_HI16, HW_H_UINT, 15, 16,
444 { 0, { (void *) &(iq2000_cgen_ifld_table[11])} },
445 { 0, { (1<<MACH_BASE) } } },
446/* lo16: 16 bit signed immediate, for low */
447 { "lo16", IQ2000_OPERAND_LO16, HW_H_UINT, 15, 16,
448 { 0, { (void *) &(iq2000_cgen_ifld_table[11])} },
449 { 0, { (1<<MACH_BASE) } } },
450/* mlo16: negated 16 bit signed immediate */
451 { "mlo16", IQ2000_OPERAND_MLO16, HW_H_UINT, 15, 16,
452 { 0, { (void *) &(iq2000_cgen_ifld_table[11])} },
453 { 0, { (1<<MACH_BASE) } } },
454/* jmptargq10: iq10 21-bit jump offset */
455 { "jmptargq10", IQ2000_OPERAND_JMPTARGQ10, HW_H_IADDR, 20, 21,
456 { 0, { (void *) &(iq2000_cgen_ifld_table[13])} },
457 { 0|A(ABS_ADDR), { (1<<MACH_BASE) } } },
458 { 0, 0, 0, 0, 0, {0, {0}}, {0, {0}} }
459};
460
461#undef A
462
463
464/* The instruction table. */
465
466#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
467#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
468#define A(a) (1 << CGEN_INSN_##a)
469#else
470#define A(a) (1 << CGEN_INSN_/**/a)
471#endif
472
473static const CGEN_IBASE iq2000_cgen_insn_table[MAX_INSNS] =
474{
475 /* Special null first entry.
476 A `num' value of zero is thus invalid.
477 Also, the special `invalid' insn resides here. */
478 { 0, 0, 0, 0, {0, {0}} },
479/* add ${rd-rs},$rt */
480 {
481 -1, "add2", "add", 32,
482 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
483 },
484/* add $rd,$rs,$rt */
485 {
486 IQ2000_INSN_ADD, "add", "add", 32,
487 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
488 },
489/* addi ${rt-rs},$lo16 */
490 {
491 -1, "addi2", "addi", 32,
492 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
493 },
494/* addi $rt,$rs,$lo16 */
495 {
496 IQ2000_INSN_ADDI, "addi", "addi", 32,
497 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
498 },
499/* addiu ${rt-rs},$lo16 */
500 {
501 -1, "addiu2", "addiu", 32,
502 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
503 },
504/* addiu $rt,$rs,$lo16 */
505 {
506 IQ2000_INSN_ADDIU, "addiu", "addiu", 32,
507 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
508 },
509/* addu ${rd-rs},$rt */
510 {
511 -1, "addu2", "addu", 32,
512 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
513 },
514/* addu $rd,$rs,$rt */
515 {
516 IQ2000_INSN_ADDU, "addu", "addu", 32,
517 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
518 },
519/* ado16 ${rd-rs},$rt */
520 {
521 -1, "ado162", "ado16", 32,
522 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
523 },
524/* ado16 $rd,$rs,$rt */
525 {
526 IQ2000_INSN_ADO16, "ado16", "ado16", 32,
527 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
528 },
529/* and ${rd-rs},$rt */
530 {
531 -1, "and2", "and", 32,
532 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
533 },
534/* and $rd,$rs,$rt */
535 {
536 IQ2000_INSN_AND, "and", "and", 32,
537 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
538 },
539/* andi ${rt-rs},$lo16 */
540 {
541 -1, "andi2", "andi", 32,
542 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
543 },
544/* andi $rt,$rs,$lo16 */
545 {
546 IQ2000_INSN_ANDI, "andi", "andi", 32,
547 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
548 },
549/* andoi ${rt-rs},$lo16 */
550 {
551 -1, "andoi2", "andoi", 32,
552 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
553 },
554/* andoi $rt,$rs,$lo16 */
555 {
556 IQ2000_INSN_ANDOI, "andoi", "andoi", 32,
557 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
558 },
559/* nor ${rd-rs},$rt */
560 {
561 -1, "nor2", "nor", 32,
562 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
563 },
564/* nor $rd,$rs,$rt */
565 {
566 IQ2000_INSN_NOR, "nor", "nor", 32,
567 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
568 },
569/* or ${rd-rs},$rt */
570 {
571 -1, "or2", "or", 32,
572 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
573 },
574/* or $rd,$rs,$rt */
575 {
576 IQ2000_INSN_OR, "or", "or", 32,
577 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
578 },
579/* ori ${rt-rs},$lo16 */
580 {
581 -1, "ori2", "ori", 32,
582 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
583 },
584/* ori $rt,$rs,$lo16 */
585 {
586 IQ2000_INSN_ORI, "ori", "ori", 32,
587 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
588 },
589/* ram $rd,$rt,$shamt,$maskl,$maskr */
590 {
591 IQ2000_INSN_RAM, "ram", "ram", 32,
592 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
593 },
594/* sll $rd,$rt,$shamt */
595 {
596 IQ2000_INSN_SLL, "sll", "sll", 32,
597 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
598 },
599/* sllv ${rd-rt},$rs */
600 {
601 -1, "sllv2", "sllv", 32,
602 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
603 },
604/* sllv $rd,$rt,$rs */
605 {
606 IQ2000_INSN_SLLV, "sllv", "sllv", 32,
607 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
608 },
609/* slmv ${rd-rt},$rs,$shamt */
610 {
611 -1, "slmv2", "slmv", 32,
612 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
613 },
614/* slmv $rd,$rt,$rs,$shamt */
615 {
616 IQ2000_INSN_SLMV, "slmv", "slmv", 32,
617 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
618 },
619/* slt ${rd-rs},$rt */
620 {
621 -1, "slt2", "slt", 32,
622 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
623 },
624/* slt $rd,$rs,$rt */
625 {
626 IQ2000_INSN_SLT, "slt", "slt", 32,
627 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
628 },
629/* slti ${rt-rs},$imm */
630 {
631 -1, "slti2", "slti", 32,
632 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
633 },
634/* slti $rt,$rs,$imm */
635 {
636 IQ2000_INSN_SLTI, "slti", "slti", 32,
637 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
638 },
639/* sltiu ${rt-rs},$imm */
640 {
641 -1, "sltiu2", "sltiu", 32,
642 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
643 },
644/* sltiu $rt,$rs,$imm */
645 {
646 IQ2000_INSN_SLTIU, "sltiu", "sltiu", 32,
647 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
648 },
649/* sltu ${rd-rs},$rt */
650 {
651 -1, "sltu2", "sltu", 32,
652 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
653 },
654/* sltu $rd,$rs,$rt */
655 {
656 IQ2000_INSN_SLTU, "sltu", "sltu", 32,
657 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
658 },
659/* sra ${rd-rt},$shamt */
660 {
661 -1, "sra2", "sra", 32,
662 { 0|A(USES_RT)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
663 },
664/* sra $rd,$rt,$shamt */
665 {
666 IQ2000_INSN_SRA, "sra", "sra", 32,
667 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
668 },
669/* srav ${rd-rt},$rs */
670 {
671 -1, "srav2", "srav", 32,
672 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
673 },
674/* srav $rd,$rt,$rs */
675 {
676 IQ2000_INSN_SRAV, "srav", "srav", 32,
677 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
678 },
679/* srl $rd,$rt,$shamt */
680 {
681 IQ2000_INSN_SRL, "srl", "srl", 32,
682 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_BASE) } }
683 },
684/* srlv ${rd-rt},$rs */
685 {
686 -1, "srlv2", "srlv", 32,
687 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
688 },
689/* srlv $rd,$rt,$rs */
690 {
691 IQ2000_INSN_SRLV, "srlv", "srlv", 32,
692 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
693 },
694/* srmv ${rd-rt},$rs,$shamt */
695 {
696 -1, "srmv2", "srmv", 32,
697 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
698 },
699/* srmv $rd,$rt,$rs,$shamt */
700 {
701 IQ2000_INSN_SRMV, "srmv", "srmv", 32,
702 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
703 },
704/* sub ${rd-rs},$rt */
705 {
706 -1, "sub2", "sub", 32,
707 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
708 },
709/* sub $rd,$rs,$rt */
710 {
711 IQ2000_INSN_SUB, "sub", "sub", 32,
712 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
713 },
714/* subu ${rd-rs},$rt */
715 {
716 -1, "subu2", "subu", 32,
717 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
718 },
719/* subu $rd,$rs,$rt */
720 {
721 IQ2000_INSN_SUBU, "subu", "subu", 32,
722 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
723 },
724/* xor ${rd-rs},$rt */
725 {
726 -1, "xor2", "xor", 32,
727 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
728 },
729/* xor $rd,$rs,$rt */
730 {
731 IQ2000_INSN_XOR, "xor", "xor", 32,
732 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_BASE) } }
733 },
734/* xori ${rt-rs},$lo16 */
735 {
736 -1, "xori2", "xori", 32,
737 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_BASE) } }
738 },
739/* xori $rt,$rs,$lo16 */
740 {
741 IQ2000_INSN_XORI, "xori", "xori", 32,
742 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
743 },
744/* bbi $rs($bitnum),$offset */
745 {
746 IQ2000_INSN_BBI, "bbi", "bbi", 32,
747 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
748 },
749/* bbin $rs($bitnum),$offset */
750 {
751 IQ2000_INSN_BBIN, "bbin", "bbin", 32,
752 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
753 },
754/* bbv $rs,$rt,$offset */
755 {
756 IQ2000_INSN_BBV, "bbv", "bbv", 32,
757 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
758 },
759/* bbvn $rs,$rt,$offset */
760 {
761 IQ2000_INSN_BBVN, "bbvn", "bbvn", 32,
762 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
763 },
764/* beq $rs,$rt,$offset */
765 {
766 IQ2000_INSN_BEQ, "beq", "beq", 32,
767 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
768 },
769/* beql $rs,$rt,$offset */
770 {
771 IQ2000_INSN_BEQL, "beql", "beql", 32,
772 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
773 },
774/* bgez $rs,$offset */
775 {
776 IQ2000_INSN_BGEZ, "bgez", "bgez", 32,
777 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
778 },
779/* bgezal $rs,$offset */
780 {
781 IQ2000_INSN_BGEZAL, "bgezal", "bgezal", 32,
782 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
783 },
784/* bgezall $rs,$offset */
785 {
786 IQ2000_INSN_BGEZALL, "bgezall", "bgezall", 32,
787 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
788 },
789/* bgezl $rs,$offset */
790 {
791 IQ2000_INSN_BGEZL, "bgezl", "bgezl", 32,
792 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
793 },
794/* bltz $rs,$offset */
795 {
796 IQ2000_INSN_BLTZ, "bltz", "bltz", 32,
797 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
798 },
799/* bltzl $rs,$offset */
800 {
801 IQ2000_INSN_BLTZL, "bltzl", "bltzl", 32,
802 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
803 },
804/* bltzal $rs,$offset */
805 {
806 IQ2000_INSN_BLTZAL, "bltzal", "bltzal", 32,
807 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
808 },
809/* bltzall $rs,$offset */
810 {
811 IQ2000_INSN_BLTZALL, "bltzall", "bltzall", 32,
812 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
813 },
814/* bmb0 $rs,$rt,$offset */
815 {
816 IQ2000_INSN_BMB0, "bmb0", "bmb0", 32,
817 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
818 },
819/* bmb1 $rs,$rt,$offset */
820 {
821 IQ2000_INSN_BMB1, "bmb1", "bmb1", 32,
822 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
823 },
824/* bmb2 $rs,$rt,$offset */
825 {
826 IQ2000_INSN_BMB2, "bmb2", "bmb2", 32,
827 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
828 },
829/* bmb3 $rs,$rt,$offset */
830 {
831 IQ2000_INSN_BMB3, "bmb3", "bmb3", 32,
832 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
833 },
834/* bne $rs,$rt,$offset */
835 {
836 IQ2000_INSN_BNE, "bne", "bne", 32,
837 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
838 },
839/* bnel $rs,$rt,$offset */
840 {
841 IQ2000_INSN_BNEL, "bnel", "bnel", 32,
842 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
843 },
844/* jalr $rd,$rs */
845 {
846 IQ2000_INSN_JALR, "jalr", "jalr", 32,
847 { 0|A(USES_RS)|A(USES_RD)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
848 },
849/* jr $rs */
850 {
851 IQ2000_INSN_JR, "jr", "jr", 32,
852 { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_BASE) } }
853 },
854/* lb $rt,$lo16($base) */
855 {
856 IQ2000_INSN_LB, "lb", "lb", 32,
857 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
858 },
859/* lbu $rt,$lo16($base) */
860 {
861 IQ2000_INSN_LBU, "lbu", "lbu", 32,
862 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
863 },
864/* lh $rt,$lo16($base) */
865 {
866 IQ2000_INSN_LH, "lh", "lh", 32,
867 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
868 },
869/* lhu $rt,$lo16($base) */
870 {
871 IQ2000_INSN_LHU, "lhu", "lhu", 32,
872 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
873 },
874/* lui $rt,$hi16 */
875 {
876 IQ2000_INSN_LUI, "lui", "lui", 32,
877 { 0|A(USES_RT), { (1<<MACH_BASE) } }
878 },
879/* lw $rt,$lo16($base) */
880 {
881 IQ2000_INSN_LW, "lw", "lw", 32,
882 { 0|A(USES_RT)|A(USES_RS)|A(LOAD_DELAY), { (1<<MACH_BASE) } }
883 },
884/* sb $rt,$lo16($base) */
885 {
886 IQ2000_INSN_SB, "sb", "sb", 32,
887 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
888 },
889/* sh $rt,$lo16($base) */
890 {
891 IQ2000_INSN_SH, "sh", "sh", 32,
892 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
893 },
894/* sw $rt,$lo16($base) */
895 {
896 IQ2000_INSN_SW, "sw", "sw", 32,
897 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_BASE) } }
898 },
899/* break */
900 {
901 IQ2000_INSN_BREAK, "break", "break", 32,
902 { 0, { (1<<MACH_BASE) } }
903 },
904/* syscall */
905 {
906 IQ2000_INSN_SYSCALL, "syscall", "syscall", 32,
907 { 0|A(YIELD_INSN), { (1<<MACH_BASE) } }
908 },
909/* andoui $rt,$rs,$hi16 */
910 {
911 IQ2000_INSN_ANDOUI, "andoui", "andoui", 32,
912 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ2000) } }
913 },
914/* andoui ${rt-rs},$hi16 */
915 {
916 -1, "andoui2", "andoui", 32,
917 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ2000) } }
918 },
919/* orui ${rt-rs},$hi16 */
920 {
921 -1, "orui2", "orui", 32,
922 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ2000) } }
923 },
924/* orui $rt,$rs,$hi16 */
925 {
926 IQ2000_INSN_ORUI, "orui", "orui", 32,
927 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ2000) } }
928 },
929/* bgtz $rs,$offset */
930 {
931 IQ2000_INSN_BGTZ, "bgtz", "bgtz", 32,
932 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
933 },
934/* bgtzl $rs,$offset */
935 {
936 IQ2000_INSN_BGTZL, "bgtzl", "bgtzl", 32,
937 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
938 },
939/* blez $rs,$offset */
940 {
941 IQ2000_INSN_BLEZ, "blez", "blez", 32,
942 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
943 },
944/* blezl $rs,$offset */
945 {
946 IQ2000_INSN_BLEZL, "blezl", "blezl", 32,
947 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
948 },
949/* mrgb $rd,$rs,$rt,$mask */
950 {
951 IQ2000_INSN_MRGB, "mrgb", "mrgb", 32,
952 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ2000) } }
953 },
954/* mrgb ${rd-rs},$rt,$mask */
955 {
956 -1, "mrgb2", "mrgb", 32,
957 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ2000) } }
958 },
959/* bctxt $rs,$offset */
960 {
961 IQ2000_INSN_BCTXT, "bctxt", "bctxt", 32,
962 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
963 },
964/* bc0f $offset */
965 {
966 IQ2000_INSN_BC0F, "bc0f", "bc0f", 32,
967 { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
968 },
969/* bc0fl $offset */
970 {
971 IQ2000_INSN_BC0FL, "bc0fl", "bc0fl", 32,
972 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
973 },
974/* bc3f $offset */
975 {
976 IQ2000_INSN_BC3F, "bc3f", "bc3f", 32,
977 { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
978 },
979/* bc3fl $offset */
980 {
981 IQ2000_INSN_BC3FL, "bc3fl", "bc3fl", 32,
982 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
983 },
984/* bc0t $offset */
985 {
986 IQ2000_INSN_BC0T, "bc0t", "bc0t", 32,
987 { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
988 },
989/* bc0tl $offset */
990 {
991 IQ2000_INSN_BC0TL, "bc0tl", "bc0tl", 32,
992 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
993 },
994/* bc3t $offset */
995 {
996 IQ2000_INSN_BC3T, "bc3t", "bc3t", 32,
997 { 0|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
998 },
999/* bc3tl $offset */
1000 {
1001 IQ2000_INSN_BC3TL, "bc3tl", "bc3tl", 32,
1002 { 0|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
1003 },
1004/* cfc0 $rt,$rd */
1005 {
1006 IQ2000_INSN_CFC0, "cfc0", "cfc0", 32,
1007 { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1008 },
1009/* cfc1 $rt,$rd */
1010 {
1011 IQ2000_INSN_CFC1, "cfc1", "cfc1", 32,
1012 { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1013 },
1014/* cfc2 $rt,$rd */
1015 {
1016 IQ2000_INSN_CFC2, "cfc2", "cfc2", 32,
1017 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1018 },
1019/* cfc3 $rt,$rd */
1020 {
1021 IQ2000_INSN_CFC3, "cfc3", "cfc3", 32,
1022 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1023 },
1024/* chkhdr $rd,$rt */
1025 {
1026 IQ2000_INSN_CHKHDR, "chkhdr", "chkhdr", 32,
1027 { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1028 },
1029/* ctc0 $rt,$rd */
1030 {
1031 IQ2000_INSN_CTC0, "ctc0", "ctc0", 32,
1032 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1033 },
1034/* ctc1 $rt,$rd */
1035 {
1036 IQ2000_INSN_CTC1, "ctc1", "ctc1", 32,
1037 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1038 },
1039/* ctc2 $rt,$rd */
1040 {
1041 IQ2000_INSN_CTC2, "ctc2", "ctc2", 32,
1042 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1043 },
1044/* ctc3 $rt,$rd */
1045 {
1046 IQ2000_INSN_CTC3, "ctc3", "ctc3", 32,
1047 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1048 },
1049/* jcr $rs */
1050 {
1051 IQ2000_INSN_JCR, "jcr", "jcr", 32,
1052 { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
1053 },
1054/* luc32 $rt,$rd */
1055 {
1056 IQ2000_INSN_LUC32, "luc32", "luc32", 32,
1057 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1058 },
1059/* luc32l $rt,$rd */
1060 {
1061 IQ2000_INSN_LUC32L, "luc32l", "luc32l", 32,
1062 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1063 },
1064/* luc64 $rt,$rd */
1065 {
1066 IQ2000_INSN_LUC64, "luc64", "luc64", 32,
1067 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1068 },
1069/* luc64l $rt,$rd */
1070 {
1071 IQ2000_INSN_LUC64L, "luc64l", "luc64l", 32,
1072 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1073 },
1074/* luk $rt,$rd */
1075 {
1076 IQ2000_INSN_LUK, "luk", "luk", 32,
1077 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1078 },
1079/* lulck $rt */
1080 {
1081 IQ2000_INSN_LULCK, "lulck", "lulck", 32,
1082 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1083 },
1084/* lum32 $rt,$rd */
1085 {
1086 IQ2000_INSN_LUM32, "lum32", "lum32", 32,
1087 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1088 },
1089/* lum32l $rt,$rd */
1090 {
1091 IQ2000_INSN_LUM32L, "lum32l", "lum32l", 32,
1092 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1093 },
1094/* lum64 $rt,$rd */
1095 {
1096 IQ2000_INSN_LUM64, "lum64", "lum64", 32,
1097 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1098 },
1099/* lum64l $rt,$rd */
1100 {
1101 IQ2000_INSN_LUM64L, "lum64l", "lum64l", 32,
1102 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1103 },
1104/* lur $rt,$rd */
1105 {
1106 IQ2000_INSN_LUR, "lur", "lur", 32,
1107 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1108 },
1109/* lurl $rt,$rd */
1110 {
1111 IQ2000_INSN_LURL, "lurl", "lurl", 32,
1112 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1113 },
1114/* luulck $rt */
1115 {
1116 IQ2000_INSN_LUULCK, "luulck", "luulck", 32,
1117 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1118 },
1119/* mfc0 $rt,$rd */
1120 {
1121 IQ2000_INSN_MFC0, "mfc0", "mfc0", 32,
1122 { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1123 },
1124/* mfc1 $rt,$rd */
1125 {
1126 IQ2000_INSN_MFC1, "mfc1", "mfc1", 32,
1127 { 0|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1128 },
1129/* mfc2 $rt,$rd */
1130 {
1131 IQ2000_INSN_MFC2, "mfc2", "mfc2", 32,
1132 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1133 },
1134/* mfc3 $rt,$rd */
1135 {
1136 IQ2000_INSN_MFC3, "mfc3", "mfc3", 32,
1137 { 0|A(YIELD_INSN)|A(USES_RT)|A(LOAD_DELAY), { (1<<MACH_IQ2000) } }
1138 },
1139/* mtc0 $rt,$rd */
1140 {
1141 IQ2000_INSN_MTC0, "mtc0", "mtc0", 32,
1142 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1143 },
1144/* mtc1 $rt,$rd */
1145 {
1146 IQ2000_INSN_MTC1, "mtc1", "mtc1", 32,
1147 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1148 },
1149/* mtc2 $rt,$rd */
1150 {
1151 IQ2000_INSN_MTC2, "mtc2", "mtc2", 32,
1152 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1153 },
1154/* mtc3 $rt,$rd */
1155 {
1156 IQ2000_INSN_MTC3, "mtc3", "mtc3", 32,
1157 { 0|A(USES_RT), { (1<<MACH_IQ2000) } }
1158 },
1159/* pkrl $rd,$rt */
1160 {
1161 IQ2000_INSN_PKRL, "pkrl", "pkrl", 32,
1162 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1163 },
1164/* pkrlr1 $rt,$index,$count */
1165 {
1166 IQ2000_INSN_PKRLR1, "pkrlr1", "pkrlr1", 32,
1167 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1168 },
1169/* pkrlr30 $rt,$index,$count */
1170 {
1171 IQ2000_INSN_PKRLR30, "pkrlr30", "pkrlr30", 32,
1172 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1173 },
1174/* rb $rd,$rt */
1175 {
1176 IQ2000_INSN_RB, "rb", "rb", 32,
1177 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1178 },
1179/* rbr1 $rt,$index,$count */
1180 {
1181 IQ2000_INSN_RBR1, "rbr1", "rbr1", 32,
1182 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1183 },
1184/* rbr30 $rt,$index,$count */
1185 {
1186 IQ2000_INSN_RBR30, "rbr30", "rbr30", 32,
1187 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1188 },
1189/* rfe */
1190 {
1191 IQ2000_INSN_RFE, "rfe", "rfe", 32,
1192 { 0, { (1<<MACH_IQ2000) } }
1193 },
1194/* rx $rd,$rt */
1195 {
1196 IQ2000_INSN_RX, "rx", "rx", 32,
1197 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1198 },
1199/* rxr1 $rt,$index,$count */
1200 {
1201 IQ2000_INSN_RXR1, "rxr1", "rxr1", 32,
1202 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1203 },
1204/* rxr30 $rt,$index,$count */
1205 {
1206 IQ2000_INSN_RXR30, "rxr30", "rxr30", 32,
1207 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1208 },
1209/* sleep */
1210 {
1211 IQ2000_INSN_SLEEP, "sleep", "sleep", 32,
1212 { 0|A(YIELD_INSN), { (1<<MACH_IQ2000) } }
1213 },
1214/* srrd $rt */
1215 {
1216 IQ2000_INSN_SRRD, "srrd", "srrd", 32,
1217 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1218 },
1219/* srrdl $rt */
1220 {
1221 IQ2000_INSN_SRRDL, "srrdl", "srrdl", 32,
1222 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1223 },
1224/* srulck $rt */
1225 {
1226 IQ2000_INSN_SRULCK, "srulck", "srulck", 32,
1227 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1228 },
1229/* srwr $rt,$rd */
1230 {
1231 IQ2000_INSN_SRWR, "srwr", "srwr", 32,
1232 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1233 },
1234/* srwru $rt,$rd */
1235 {
1236 IQ2000_INSN_SRWRU, "srwru", "srwru", 32,
1237 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1238 },
1239/* trapqfl */
1240 {
1241 IQ2000_INSN_TRAPQFL, "trapqfl", "trapqfl", 32,
1242 { 0|A(YIELD_INSN), { (1<<MACH_IQ2000) } }
1243 },
1244/* trapqne */
1245 {
1246 IQ2000_INSN_TRAPQNE, "trapqne", "trapqne", 32,
1247 { 0|A(YIELD_INSN), { (1<<MACH_IQ2000) } }
1248 },
1249/* traprel $rt */
1250 {
1251 IQ2000_INSN_TRAPREL, "traprel", "traprel", 32,
1252 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1253 },
1254/* wb $rd,$rt */
1255 {
1256 IQ2000_INSN_WB, "wb", "wb", 32,
1257 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1258 },
1259/* wbu $rd,$rt */
1260 {
1261 IQ2000_INSN_WBU, "wbu", "wbu", 32,
1262 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1263 },
1264/* wbr1 $rt,$index,$count */
1265 {
1266 IQ2000_INSN_WBR1, "wbr1", "wbr1", 32,
1267 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1268 },
1269/* wbr1u $rt,$index,$count */
1270 {
1271 IQ2000_INSN_WBR1U, "wbr1u", "wbr1u", 32,
1272 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1273 },
1274/* wbr30 $rt,$index,$count */
1275 {
1276 IQ2000_INSN_WBR30, "wbr30", "wbr30", 32,
1277 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1278 },
1279/* wbr30u $rt,$index,$count */
1280 {
1281 IQ2000_INSN_WBR30U, "wbr30u", "wbr30u", 32,
1282 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1283 },
1284/* wx $rd,$rt */
1285 {
1286 IQ2000_INSN_WX, "wx", "wx", 32,
1287 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1288 },
1289/* wxu $rd,$rt */
1290 {
1291 IQ2000_INSN_WXU, "wxu", "wxu", 32,
1292 { 0|A(YIELD_INSN)|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ2000) } }
1293 },
1294/* wxr1 $rt,$index,$count */
1295 {
1296 IQ2000_INSN_WXR1, "wxr1", "wxr1", 32,
1297 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1298 },
1299/* wxr1u $rt,$index,$count */
1300 {
1301 IQ2000_INSN_WXR1U, "wxr1u", "wxr1u", 32,
1302 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1303 },
1304/* wxr30 $rt,$index,$count */
1305 {
1306 IQ2000_INSN_WXR30, "wxr30", "wxr30", 32,
1307 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1308 },
1309/* wxr30u $rt,$index,$count */
1310 {
1311 IQ2000_INSN_WXR30U, "wxr30u", "wxr30u", 32,
1312 { 0|A(YIELD_INSN)|A(USES_RT), { (1<<MACH_IQ2000) } }
1313 },
1314/* ldw $rt,$lo16($base) */
1315 {
1316 IQ2000_INSN_LDW, "ldw", "ldw", 32,
1317 { 0|A(USES_RT)|A(LOAD_DELAY)|A(EVEN_REG_NUM), { (1<<MACH_IQ2000) } }
1318 },
1319/* sdw $rt,$lo16($base) */
1320 {
1321 IQ2000_INSN_SDW, "sdw", "sdw", 32,
1322 { 0|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ2000) } }
1323 },
1324/* j $jmptarg */
1325 {
1326 IQ2000_INSN_J, "j", "j", 32,
1327 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
1328 },
1329/* jal $jmptarg */
1330 {
1331 IQ2000_INSN_JAL, "jal", "jal", 32,
1332 { 0|A(USES_R31)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
1333 },
1334/* bmb $rs,$rt,$offset */
1335 {
1336 IQ2000_INSN_BMB, "bmb", "bmb", 32,
1337 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ2000) } }
1338 },
1339/* andoui $rt,$rs,$hi16 */
1340 {
1341 IQ2000_INSN_ANDOUI_Q10, "andoui-q10", "andoui", 32,
1342 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1343 },
1344/* andoui ${rt-rs},$hi16 */
1345 {
1346 -1, "andoui2-q10", "andoui", 32,
1347 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
1348 },
1349/* orui $rt,$rs,$hi16 */
1350 {
1351 IQ2000_INSN_ORUI_Q10, "orui-q10", "orui", 32,
1352 { 0|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1353 },
1354/* orui ${rt-rs},$hi16 */
1355 {
1356 -1, "orui2-q10", "orui", 32,
1357 { 0|A(USES_RT)|A(USES_RS)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
1358 },
1359/* mrgb $rd,$rs,$rt,$maskq10 */
1360 {
1361 IQ2000_INSN_MRGBQ10, "mrgbq10", "mrgb", 32,
1362 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1363 },
1364/* mrgb ${rd-rs},$rt,$maskq10 */
1365 {
1366 -1, "mrgbq102", "mrgb", 32,
1367 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD)|A(NO_DIS)|A(ALIAS), { (1<<MACH_IQ10) } }
1368 },
1369/* j $jmptarg */
1370 {
1371 IQ2000_INSN_JQ10, "jq10", "j", 32,
1372 { 0|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1373 },
1374/* jal $rt,$jmptarg */
1375 {
1376 IQ2000_INSN_JALQ10, "jalq10", "jal", 32,
1377 { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1378 },
1379/* jal $jmptarg */
1380 {
1381 IQ2000_INSN_JALQ10_2, "jalq10-2", "jal", 32,
1382 { 0|A(USES_RT)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1383 },
1384/* bbil $rs($bitnum),$offset */
1385 {
1386 IQ2000_INSN_BBIL, "bbil", "bbil", 32,
1387 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1388 },
1389/* bbinl $rs($bitnum),$offset */
1390 {
1391 IQ2000_INSN_BBINL, "bbinl", "bbinl", 32,
1392 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1393 },
1394/* bbvl $rs,$rt,$offset */
1395 {
1396 IQ2000_INSN_BBVL, "bbvl", "bbvl", 32,
1397 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1398 },
1399/* bbvnl $rs,$rt,$offset */
1400 {
1401 IQ2000_INSN_BBVNL, "bbvnl", "bbvnl", 32,
1402 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1403 },
1404/* bgtzal $rs,$offset */
1405 {
1406 IQ2000_INSN_BGTZAL, "bgtzal", "bgtzal", 32,
1407 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1408 },
1409/* bgtzall $rs,$offset */
1410 {
1411 IQ2000_INSN_BGTZALL, "bgtzall", "bgtzall", 32,
1412 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1413 },
1414/* blezal $rs,$offset */
1415 {
1416 IQ2000_INSN_BLEZAL, "blezal", "blezal", 32,
1417 { 0|A(USES_R31)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1418 },
1419/* blezall $rs,$offset */
1420 {
1421 IQ2000_INSN_BLEZALL, "blezall", "blezall", 32,
1422 { 0|A(USES_R31)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1423 },
1424/* bgtz $rs,$offset */
1425 {
1426 IQ2000_INSN_BGTZ_Q10, "bgtz-q10", "bgtz", 32,
1427 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1428 },
1429/* bgtzl $rs,$offset */
1430 {
1431 IQ2000_INSN_BGTZL_Q10, "bgtzl-q10", "bgtzl", 32,
1432 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1433 },
1434/* blez $rs,$offset */
1435 {
1436 IQ2000_INSN_BLEZ_Q10, "blez-q10", "blez", 32,
1437 { 0|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1438 },
1439/* blezl $rs,$offset */
1440 {
1441 IQ2000_INSN_BLEZL_Q10, "blezl-q10", "blezl", 32,
1442 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1443 },
1444/* bmb $rs,$rt,$offset */
1445 {
1446 IQ2000_INSN_BMB_Q10, "bmb-q10", "bmb", 32,
1447 { 0|A(USES_RT)|A(USES_RS)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1448 },
1449/* bmbl $rs,$rt,$offset */
1450 {
1451 IQ2000_INSN_BMBL, "bmbl", "bmbl", 32,
1452 { 0|A(USES_RT)|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1453 },
1454/* bri $rs,$offset */
1455 {
1456 IQ2000_INSN_BRI, "bri", "bri", 32,
1457 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1458 },
1459/* brv $rs,$offset */
1460 {
1461 IQ2000_INSN_BRV, "brv", "brv", 32,
1462 { 0|A(USES_RS)|A(SKIP_CTI)|A(COND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1463 },
1464/* bctx $rs,$offset */
1465 {
1466 IQ2000_INSN_BCTX, "bctx", "bctx", 32,
1467 { 0|A(USES_RS)|A(UNCOND_CTI)|A(DELAY_SLOT), { (1<<MACH_IQ10) } }
1468 },
1469/* yield */
1470 {
1471 IQ2000_INSN_YIELD, "yield", "yield", 32,
1472 { 0, { (1<<MACH_IQ10) } }
1473 },
1474/* crc32 $rd,$rs,$rt */
1475 {
1476 IQ2000_INSN_CRC32, "crc32", "crc32", 32,
1477 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1478 },
1479/* crc32b $rd,$rs,$rt */
1480 {
1481 IQ2000_INSN_CRC32B, "crc32b", "crc32b", 32,
1482 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1483 },
1484/* cnt1s $rd,$rs */
1485 {
1486 IQ2000_INSN_CNT1S, "cnt1s", "cnt1s", 32,
1487 { 0|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1488 },
1489/* avail $rd */
1490 {
1491 IQ2000_INSN_AVAIL, "avail", "avail", 32,
1492 { 0|A(USES_RD), { (1<<MACH_IQ10) } }
1493 },
1494/* free $rd,$rs */
1495 {
1496 IQ2000_INSN_FREE, "free", "free", 32,
1497 { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
1498 },
1499/* tstod $rd,$rs */
1500 {
1501 IQ2000_INSN_TSTOD, "tstod", "tstod", 32,
1502 { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
1503 },
1504/* cmphdr $rd */
1505 {
1506 IQ2000_INSN_CMPHDR, "cmphdr", "cmphdr", 32,
1507 { 0|A(USES_RD), { (1<<MACH_IQ10) } }
1508 },
1509/* mcid $rd,$rt */
1510 {
1511 IQ2000_INSN_MCID, "mcid", "mcid", 32,
1512 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ10) } }
1513 },
1514/* dba $rd */
1515 {
1516 IQ2000_INSN_DBA, "dba", "dba", 32,
1517 { 0|A(USES_RD), { (1<<MACH_IQ10) } }
1518 },
1519/* dbd $rd,$rs,$rt */
1520 {
1521 IQ2000_INSN_DBD, "dbd", "dbd", 32,
1522 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1523 },
1524/* dpwt $rd,$rs */
1525 {
1526 IQ2000_INSN_DPWT, "dpwt", "dpwt", 32,
1527 { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
1528 },
1529/* chkhdr $rd,$rs */
1530 {
1531 IQ2000_INSN_CHKHDRQ10, "chkhdrq10", "chkhdr", 32,
1532 { 0|A(USES_RD)|A(USES_RS), { (1<<MACH_IQ10) } }
1533 },
1534/* rba $rd,$rs,$rt */
1535 {
1536 IQ2000_INSN_RBA, "rba", "rba", 32,
1537 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1538 },
1539/* rbal $rd,$rs,$rt */
1540 {
1541 IQ2000_INSN_RBAL, "rbal", "rbal", 32,
1542 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1543 },
1544/* rbar $rd,$rs,$rt */
1545 {
1546 IQ2000_INSN_RBAR, "rbar", "rbar", 32,
1547 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1548 },
1549/* wba $rd,$rs,$rt */
1550 {
1551 IQ2000_INSN_WBA, "wba", "wba", 32,
1552 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1553 },
1554/* wbau $rd,$rs,$rt */
1555 {
1556 IQ2000_INSN_WBAU, "wbau", "wbau", 32,
1557 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1558 },
1559/* wbac $rd,$rs,$rt */
1560 {
1561 IQ2000_INSN_WBAC, "wbac", "wbac", 32,
1562 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1563 },
1564/* rbi $rd,$rs,$rt,$bytecount */
1565 {
1566 IQ2000_INSN_RBI, "rbi", "rbi", 32,
1567 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1568 },
1569/* rbil $rd,$rs,$rt,$bytecount */
1570 {
1571 IQ2000_INSN_RBIL, "rbil", "rbil", 32,
1572 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1573 },
1574/* rbir $rd,$rs,$rt,$bytecount */
1575 {
1576 IQ2000_INSN_RBIR, "rbir", "rbir", 32,
1577 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1578 },
1579/* wbi $rd,$rs,$rt,$bytecount */
1580 {
1581 IQ2000_INSN_WBI, "wbi", "wbi", 32,
1582 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1583 },
1584/* wbic $rd,$rs,$rt,$bytecount */
1585 {
1586 IQ2000_INSN_WBIC, "wbic", "wbic", 32,
1587 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1588 },
1589/* wbiu $rd,$rs,$rt,$bytecount */
1590 {
1591 IQ2000_INSN_WBIU, "wbiu", "wbiu", 32,
1592 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1593 },
1594/* pkrli $rd,$rs,$rt,$bytecount */
1595 {
1596 IQ2000_INSN_PKRLI, "pkrli", "pkrli", 32,
1597 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1598 },
1599/* pkrlih $rd,$rs,$rt,$bytecount */
1600 {
1601 IQ2000_INSN_PKRLIH, "pkrlih", "pkrlih", 32,
1602 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1603 },
1604/* pkrliu $rd,$rs,$rt,$bytecount */
1605 {
1606 IQ2000_INSN_PKRLIU, "pkrliu", "pkrliu", 32,
1607 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1608 },
1609/* pkrlic $rd,$rs,$rt,$bytecount */
1610 {
1611 IQ2000_INSN_PKRLIC, "pkrlic", "pkrlic", 32,
1612 { 0|A(USES_RT)|A(USES_RS)|A(USES_RD), { (1<<MACH_IQ10) } }
1613 },
1614/* pkrla $rd,$rs,$rt */
1615 {
1616 IQ2000_INSN_PKRLA, "pkrla", "pkrla", 32,
1617 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1618 },
1619/* pkrlau $rd,$rs,$rt */
1620 {
1621 IQ2000_INSN_PKRLAU, "pkrlau", "pkrlau", 32,
1622 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1623 },
1624/* pkrlah $rd,$rs,$rt */
1625 {
1626 IQ2000_INSN_PKRLAH, "pkrlah", "pkrlah", 32,
1627 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1628 },
1629/* pkrlac $rd,$rs,$rt */
1630 {
1631 IQ2000_INSN_PKRLAC, "pkrlac", "pkrlac", 32,
1632 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1633 },
1634/* lock $rd,$rt */
1635 {
1636 IQ2000_INSN_LOCK, "lock", "lock", 32,
1637 { 0|A(USES_RT)|A(USES_RD), { (1<<MACH_IQ10) } }
1638 },
1639/* unlk $rd,$rt */
1640 {
1641 IQ2000_INSN_UNLK, "unlk", "unlk", 32,
1642 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1643 },
1644/* swrd $rd,$rt */
1645 {
1646 IQ2000_INSN_SWRD, "swrd", "swrd", 32,
1647 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1648 },
1649/* swrdl $rd,$rt */
1650 {
1651 IQ2000_INSN_SWRDL, "swrdl", "swrdl", 32,
1652 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1653 },
1654/* swwr $rd,$rs,$rt */
1655 {
1656 IQ2000_INSN_SWWR, "swwr", "swwr", 32,
1657 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1658 },
1659/* swwru $rd,$rs,$rt */
1660 {
1661 IQ2000_INSN_SWWRU, "swwru", "swwru", 32,
1662 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1663 },
1664/* dwrd $rd,$rt */
1665 {
1666 IQ2000_INSN_DWRD, "dwrd", "dwrd", 32,
1667 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1668 },
1669/* dwrdl $rd,$rt */
1670 {
1671 IQ2000_INSN_DWRDL, "dwrdl", "dwrdl", 32,
1672 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1673 },
1674/* cam36 $rd,$rt,${cam-z},${cam-y} */
1675 {
1676 IQ2000_INSN_CAM36, "cam36", "cam36", 32,
1677 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1678 },
1679/* cam72 $rd,$rt,${cam-y},${cam-z} */
1680 {
1681 IQ2000_INSN_CAM72, "cam72", "cam72", 32,
1682 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1683 },
1684/* cam144 $rd,$rt,${cam-y},${cam-z} */
1685 {
1686 IQ2000_INSN_CAM144, "cam144", "cam144", 32,
1687 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1688 },
1689/* cam288 $rd,$rt,${cam-y},${cam-z} */
1690 {
1691 IQ2000_INSN_CAM288, "cam288", "cam288", 32,
1692 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1693 },
1694/* cm32and $rd,$rs,$rt */
1695 {
1696 IQ2000_INSN_CM32AND, "cm32and", "cm32and", 32,
1697 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1698 },
1699/* cm32andn $rd,$rs,$rt */
1700 {
1701 IQ2000_INSN_CM32ANDN, "cm32andn", "cm32andn", 32,
1702 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1703 },
1704/* cm32or $rd,$rs,$rt */
1705 {
1706 IQ2000_INSN_CM32OR, "cm32or", "cm32or", 32,
1707 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1708 },
1709/* cm32ra $rd,$rs,$rt */
1710 {
1711 IQ2000_INSN_CM32RA, "cm32ra", "cm32ra", 32,
1712 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1713 },
1714/* cm32rd $rd,$rt */
1715 {
1716 IQ2000_INSN_CM32RD, "cm32rd", "cm32rd", 32,
1717 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1718 },
1719/* cm32ri $rd,$rt */
1720 {
1721 IQ2000_INSN_CM32RI, "cm32ri", "cm32ri", 32,
1722 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1723 },
1724/* cm32rs $rd,$rs,$rt */
1725 {
1726 IQ2000_INSN_CM32RS, "cm32rs", "cm32rs", 32,
1727 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1728 },
1729/* cm32sa $rd,$rs,$rt */
1730 {
1731 IQ2000_INSN_CM32SA, "cm32sa", "cm32sa", 32,
1732 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1733 },
1734/* cm32sd $rd,$rt */
1735 {
1736 IQ2000_INSN_CM32SD, "cm32sd", "cm32sd", 32,
1737 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1738 },
1739/* cm32si $rd,$rt */
1740 {
1741 IQ2000_INSN_CM32SI, "cm32si", "cm32si", 32,
1742 { 0|A(USES_RD)|A(USES_RT), { (1<<MACH_IQ10) } }
1743 },
1744/* cm32ss $rd,$rs,$rt */
1745 {
1746 IQ2000_INSN_CM32SS, "cm32ss", "cm32ss", 32,
1747 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1748 },
1749/* cm32xor $rd,$rs,$rt */
1750 {
1751 IQ2000_INSN_CM32XOR, "cm32xor", "cm32xor", 32,
1752 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1753 },
1754/* cm64clr $rd,$rt */
1755 {
1756 IQ2000_INSN_CM64CLR, "cm64clr", "cm64clr", 32,
1757 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1758 },
1759/* cm64ra $rd,$rs,$rt */
1760 {
1761 IQ2000_INSN_CM64RA, "cm64ra", "cm64ra", 32,
1762 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1763 },
1764/* cm64rd $rd,$rt */
1765 {
1766 IQ2000_INSN_CM64RD, "cm64rd", "cm64rd", 32,
1767 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1768 },
1769/* cm64ri $rd,$rt */
1770 {
1771 IQ2000_INSN_CM64RI, "cm64ri", "cm64ri", 32,
1772 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1773 },
1774/* cm64ria2 $rd,$rs,$rt */
1775 {
1776 IQ2000_INSN_CM64RIA2, "cm64ria2", "cm64ria2", 32,
1777 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1778 },
1779/* cm64rs $rd,$rs,$rt */
1780 {
1781 IQ2000_INSN_CM64RS, "cm64rs", "cm64rs", 32,
1782 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1783 },
1784/* cm64sa $rd,$rs,$rt */
1785 {
1786 IQ2000_INSN_CM64SA, "cm64sa", "cm64sa", 32,
1787 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1788 },
1789/* cm64sd $rd,$rt */
1790 {
1791 IQ2000_INSN_CM64SD, "cm64sd", "cm64sd", 32,
1792 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1793 },
1794/* cm64si $rd,$rt */
1795 {
1796 IQ2000_INSN_CM64SI, "cm64si", "cm64si", 32,
1797 { 0|A(USES_RD)|A(USES_RT)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1798 },
1799/* cm64sia2 $rd,$rs,$rt */
1800 {
1801 IQ2000_INSN_CM64SIA2, "cm64sia2", "cm64sia2", 32,
1802 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1803 },
1804/* cm64ss $rd,$rs,$rt */
1805 {
1806 IQ2000_INSN_CM64SS, "cm64ss", "cm64ss", 32,
1807 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1808 },
1809/* cm128ria2 $rd,$rs,$rt */
1810 {
1811 IQ2000_INSN_CM128RIA2, "cm128ria2", "cm128ria2", 32,
1812 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1813 },
1814/* cm128ria3 $rd,$rs,$rt,${cm-3z} */
1815 {
1816 IQ2000_INSN_CM128RIA3, "cm128ria3", "cm128ria3", 32,
1817 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1818 },
1819/* cm128ria4 $rd,$rs,$rt,${cm-4z} */
1820 {
1821 IQ2000_INSN_CM128RIA4, "cm128ria4", "cm128ria4", 32,
1822 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1823 },
1824/* cm128sia2 $rd,$rs,$rt */
1825 {
1826 IQ2000_INSN_CM128SIA2, "cm128sia2", "cm128sia2", 32,
1827 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1828 },
1829/* cm128sia3 $rd,$rs,$rt,${cm-3z} */
1830 {
1831 IQ2000_INSN_CM128SIA3, "cm128sia3", "cm128sia3", 32,
1832 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS)|A(EVEN_REG_NUM), { (1<<MACH_IQ10) } }
1833 },
1834/* cm128sia4 $rd,$rs,$rt,${cm-4z} */
1835 {
1836 IQ2000_INSN_CM128SIA4, "cm128sia4", "cm128sia4", 32,
1837 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1838 },
1839/* cm128vsa $rd,$rs,$rt */
1840 {
1841 IQ2000_INSN_CM128VSA, "cm128vsa", "cm128vsa", 32,
1842 { 0|A(USES_RD)|A(USES_RT)|A(USES_RS), { (1<<MACH_IQ10) } }
1843 },
1844/* cfc $rd,$rt */
1845 {
1846 IQ2000_INSN_CFC, "cfc", "cfc", 32,
1847 { 0|A(YIELD_INSN)|A(USES_RD)|A(LOAD_DELAY), { (1<<MACH_IQ10) } }
1848 },
1849/* ctc $rs,$rt */
1850 {
1851 IQ2000_INSN_CTC, "ctc", "ctc", 32,
1852 { 0|A(USES_RS), { (1<<MACH_IQ10) } }
1853 },
1854};
1855
1856#undef OP
1857#undef A
1858
1859/* Initialize anything needed to be done once, before any cpu_open call. */
1860static void init_tables PARAMS ((void));
1861
1862static void
1863init_tables ()
1864{
1865}
1866
1867static const CGEN_MACH * lookup_mach_via_bfd_name
1868 PARAMS ((const CGEN_MACH *, const char *));
1869static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
1870static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
1871static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
1872static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
1873static void iq2000_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
1874
1875/* Subroutine of iq2000_cgen_cpu_open to look up a mach via its bfd name. */
1876
1877static const CGEN_MACH *
1878lookup_mach_via_bfd_name (table, name)
1879 const CGEN_MACH *table;
1880 const char *name;
1881{
1882 while (table->name)
1883 {
1884 if (strcmp (name, table->bfd_name) == 0)
1885 return table;
1886 ++table;
1887 }
1888 abort ();
1889}
1890
1891/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */
1892
1893static void
1894build_hw_table (cd)
1895 CGEN_CPU_TABLE *cd;
1896{
1897 int i;
1898 int machs = cd->machs;
1899 const CGEN_HW_ENTRY *init = & iq2000_cgen_hw_table[0];
1900 /* MAX_HW is only an upper bound on the number of selected entries.
1901 However each entry is indexed by it's enum so there can be holes in
1902 the table. */
1903 const CGEN_HW_ENTRY **selected =
1904 (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1905
1906 cd->hw_table.init_entries = init;
1907 cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1908 memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1909 /* ??? For now we just use machs to determine which ones we want. */
1910 for (i = 0; init[i].name != NULL; ++i)
1911 if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1912 & machs)
1913 selected[init[i].type] = &init[i];
1914 cd->hw_table.entries = selected;
1915 cd->hw_table.num_entries = MAX_HW;
1916}
1917
1918/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */
1919
1920static void
1921build_ifield_table (cd)
1922 CGEN_CPU_TABLE *cd;
1923{
1924 cd->ifld_table = & iq2000_cgen_ifld_table[0];
1925}
1926
1927/* Subroutine of iq2000_cgen_cpu_open to build the hardware table. */
1928
1929static void
1930build_operand_table (cd)
1931 CGEN_CPU_TABLE *cd;
1932{
1933 int i;
1934 int machs = cd->machs;
1935 const CGEN_OPERAND *init = & iq2000_cgen_operand_table[0];
1936 /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1937 However each entry is indexed by it's enum so there can be holes in
1938 the table. */
1939 const CGEN_OPERAND **selected =
1940 (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1941
1942 cd->operand_table.init_entries = init;
1943 cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1944 memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1945 /* ??? For now we just use mach to determine which ones we want. */
1946 for (i = 0; init[i].name != NULL; ++i)
1947 if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1948 & machs)
1949 selected[init[i].type] = &init[i];
1950 cd->operand_table.entries = selected;
1951 cd->operand_table.num_entries = MAX_OPERANDS;
1952}
1953
1954/* Subroutine of iq2000_cgen_cpu_open to build the hardware table.
1955 ??? This could leave out insns not supported by the specified mach/isa,
1956 but that would cause errors like "foo only supported by bar" to become
1957 "unknown insn", so for now we include all insns and require the app to
1958 do the checking later.
1959 ??? On the other hand, parsing of such insns may require their hardware or
1960 operand elements to be in the table [which they mightn't be]. */
1961
1962static void
1963build_insn_table (cd)
1964 CGEN_CPU_TABLE *cd;
1965{
1966 int i;
1967 const CGEN_IBASE *ib = & iq2000_cgen_insn_table[0];
1968 CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1969
1970 memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1971 for (i = 0; i < MAX_INSNS; ++i)
1972 insns[i].base = &ib[i];
1973 cd->insn_table.init_entries = insns;
1974 cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1975 cd->insn_table.num_init_entries = MAX_INSNS;
1976}
1977
1978/* Subroutine of iq2000_cgen_cpu_open to rebuild the tables. */
1979
1980static void
1981iq2000_cgen_rebuild_tables (cd)
1982 CGEN_CPU_TABLE *cd;
1983{
1984 int i;
1985 unsigned int isas = cd->isas;
1986 unsigned int machs = cd->machs;
1987
1988 cd->int_insn_p = CGEN_INT_INSN_P;
1989
1990 /* Data derived from the isa spec. */
1991#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1992 cd->default_insn_bitsize = UNSET;
1993 cd->base_insn_bitsize = UNSET;
1994 cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1995 cd->max_insn_bitsize = 0;
1996 for (i = 0; i < MAX_ISAS; ++i)
1997 if (((1 << i) & isas) != 0)
1998 {
1999 const CGEN_ISA *isa = & iq2000_cgen_isa_table[i];
2000
2001 /* Default insn sizes of all selected isas must be
2002 equal or we set the result to 0, meaning "unknown". */
2003 if (cd->default_insn_bitsize == UNSET)
2004 cd->default_insn_bitsize = isa->default_insn_bitsize;
2005 else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
2006 ; /* this is ok */
2007 else
2008 cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
2009
2010 /* Base insn sizes of all selected isas must be equal
2011 or we set the result to 0, meaning "unknown". */
2012 if (cd->base_insn_bitsize == UNSET)
2013 cd->base_insn_bitsize = isa->base_insn_bitsize;
2014 else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
2015 ; /* this is ok */
2016 else
2017 cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
2018
2019 /* Set min,max insn sizes. */
2020 if (isa->min_insn_bitsize < cd->min_insn_bitsize)
2021 cd->min_insn_bitsize = isa->min_insn_bitsize;
2022 if (isa->max_insn_bitsize > cd->max_insn_bitsize)
2023 cd->max_insn_bitsize = isa->max_insn_bitsize;
2024 }
2025
2026 /* Data derived from the mach spec. */
2027 for (i = 0; i < MAX_MACHS; ++i)
2028 if (((1 << i) & machs) != 0)
2029 {
2030 const CGEN_MACH *mach = & iq2000_cgen_mach_table[i];
2031
2032 if (mach->insn_chunk_bitsize != 0)
2033 {
2034 if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
2035 {
2036 fprintf (stderr, "iq2000_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
2037 cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
2038 abort ();
2039 }
2040
2041 cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
2042 }
2043 }
2044
2045 /* Determine which hw elements are used by MACH. */
2046 build_hw_table (cd);
2047
2048 /* Build the ifield table. */
2049 build_ifield_table (cd);
2050
2051 /* Determine which operands are used by MACH/ISA. */
2052 build_operand_table (cd);
2053
2054 /* Build the instruction table. */
2055 build_insn_table (cd);
2056}
2057
2058/* Initialize a cpu table and return a descriptor.
2059 It's much like opening a file, and must be the first function called.
2060 The arguments are a set of (type/value) pairs, terminated with
2061 CGEN_CPU_OPEN_END.
2062
2063 Currently supported values:
2064 CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
2065 CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
2066 CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
2067 CGEN_CPU_OPEN_ENDIAN: specify endian choice
2068 CGEN_CPU_OPEN_END: terminates arguments
2069
2070 ??? Simultaneous multiple isas might not make sense, but it's not (yet)
2071 precluded.
2072
2073 ??? We only support ISO C stdargs here, not K&R.
2074 Laziness, plus experiment to see if anything requires K&R - eventually
2075 K&R will no longer be supported - e.g. GDB is currently trying this. */
2076
2077CGEN_CPU_DESC
2078iq2000_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
2079{
2080 CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2081 static int init_p;
2082 unsigned int isas = 0; /* 0 = "unspecified" */
2083 unsigned int machs = 0; /* 0 = "unspecified" */
2084 enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2085 va_list ap;
2086
2087 if (! init_p)
2088 {
2089 init_tables ();
2090 init_p = 1;
2091 }
2092
2093 memset (cd, 0, sizeof (*cd));
2094
2095 va_start (ap, arg_type);
2096 while (arg_type != CGEN_CPU_OPEN_END)
2097 {
2098 switch (arg_type)
2099 {
2100 case CGEN_CPU_OPEN_ISAS :
2101 isas = va_arg (ap, unsigned int);
2102 break;
2103 case CGEN_CPU_OPEN_MACHS :
2104 machs = va_arg (ap, unsigned int);
2105 break;
2106 case CGEN_CPU_OPEN_BFDMACH :
2107 {
2108 const char *name = va_arg (ap, const char *);
2109 const CGEN_MACH *mach =
2110 lookup_mach_via_bfd_name (iq2000_cgen_mach_table, name);
2111
2112 machs |= 1 << mach->num;
2113 break;
2114 }
2115 case CGEN_CPU_OPEN_ENDIAN :
2116 endian = va_arg (ap, enum cgen_endian);
2117 break;
2118 default :
2119 fprintf (stderr, "iq2000_cgen_cpu_open: unsupported argument `%d'\n",
2120 arg_type);
2121 abort (); /* ??? return NULL? */
2122 }
2123 arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2124 }
2125 va_end (ap);
2126
2127 /* mach unspecified means "all" */
2128 if (machs == 0)
2129 machs = (1 << MAX_MACHS) - 1;
2130 /* base mach is always selected */
2131 machs |= 1;
2132 /* isa unspecified means "all" */
2133 if (isas == 0)
2134 isas = (1 << MAX_ISAS) - 1;
2135 if (endian == CGEN_ENDIAN_UNKNOWN)
2136 {
2137 /* ??? If target has only one, could have a default. */
2138 fprintf (stderr, "iq2000_cgen_cpu_open: no endianness specified\n");
2139 abort ();
2140 }
2141
2142 cd->isas = isas;
2143 cd->machs = machs;
2144 cd->endian = endian;
2145 /* FIXME: for the sparc case we can determine insn-endianness statically.
2146 The worry here is where both data and insn endian can be independently
2147 chosen, in which case this function will need another argument.
2148 Actually, will want to allow for more arguments in the future anyway. */
2149 cd->insn_endian = endian;
2150
2151 /* Table (re)builder. */
2152 cd->rebuild_tables = iq2000_cgen_rebuild_tables;
2153 iq2000_cgen_rebuild_tables (cd);
2154
2155 /* Default to not allowing signed overflow. */
2156 cd->signed_overflow_ok_p = 0;
2157
2158 return (CGEN_CPU_DESC) cd;
2159}
2160
2161/* Cover fn to iq2000_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2162 MACH_NAME is the bfd name of the mach. */
2163
2164CGEN_CPU_DESC
2165iq2000_cgen_cpu_open_1 (mach_name, endian)
2166 const char *mach_name;
2167 enum cgen_endian endian;
2168{
2169 return iq2000_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2170 CGEN_CPU_OPEN_ENDIAN, endian,
2171 CGEN_CPU_OPEN_END);
2172}
2173
2174/* Close a cpu table.
2175 ??? This can live in a machine independent file, but there's currently
2176 no place to put this file (there's no libcgen). libopcodes is the wrong
2177 place as some simulator ports use this but they don't use libopcodes. */
2178
2179void
2180iq2000_cgen_cpu_close (cd)
2181 CGEN_CPU_DESC cd;
2182{
2183 unsigned int i;
2184 CGEN_INSN *insns;
2185
2186 if (cd->macro_insn_table.init_entries)
2187 {
2188 insns = cd->macro_insn_table.init_entries;
2189 for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
2190 {
2191 if (CGEN_INSN_RX ((insns)))
2192 regfree(CGEN_INSN_RX (insns));
2193 }
2194 }
2195
2196 if (cd->insn_table.init_entries)
2197 {
2198 insns = cd->insn_table.init_entries;
2199 for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
2200 {
2201 if (CGEN_INSN_RX (insns))
2202 regfree(CGEN_INSN_RX (insns));
2203 }
2204 }
2205
2206
2207
2208 if (cd->macro_insn_table.init_entries)
2209 free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
2210
2211 if (cd->insn_table.init_entries)
2212 free ((CGEN_INSN *) cd->insn_table.init_entries);
2213
2214 if (cd->hw_table.entries)
2215 free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2216
2217 if (cd->operand_table.entries)
2218 free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
2219
2220 free (cd);
2221}
2222
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