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252b5132 | 1 | /* Print mips instructions for GDB, the GNU debugger, or for objdump. |
060d22b0 | 2 | Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, |
82f6ea4a | 3 | 2000, 2001, 2002 |
73da6b6b | 4 | Free Software Foundation, Inc. |
252b5132 RH |
5 | Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp). |
6 | ||
7 | This file is part of GDB, GAS, and the GNU binutils. | |
8 | ||
9 | This program is free software; you can redistribute it and/or modify | |
10 | it under the terms of the GNU General Public License as published by | |
11 | the Free Software Foundation; either version 2 of the License, or | |
12 | (at your option) any later version. | |
13 | ||
14 | This program is distributed in the hope that it will be useful, | |
15 | but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | GNU General Public License for more details. | |
18 | ||
19 | You should have received a copy of the GNU General Public License | |
20 | along with this program; if not, write to the Free Software | |
21 | Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. */ | |
22 | ||
252b5132 RH |
23 | #include "sysdep.h" |
24 | #include "dis-asm.h" | |
640c0ccd | 25 | #include "libiberty.h" |
252b5132 RH |
26 | #include "opcode/mips.h" |
27 | #include "opintl.h" | |
28 | ||
29 | /* FIXME: These are needed to figure out if the code is mips16 or | |
30 | not. The low bit of the address is often a good indicator. No | |
31 | symbol table is available when this code runs out in an embedded | |
7f6621cd | 32 | system as when it is used for disassembler support in a monitor. */ |
252b5132 RH |
33 | |
34 | #if !defined(EMBEDDED_ENV) | |
35 | #define SYMTAB_AVAILABLE 1 | |
36 | #include "elf-bfd.h" | |
37 | #include "elf/mips.h" | |
38 | #endif | |
39 | ||
aa5f19f2 NC |
40 | /* Mips instructions are at maximum this many bytes long. */ |
41 | #define INSNLEN 4 | |
42 | ||
640c0ccd CD |
43 | static void set_default_mips_dis_options |
44 | PARAMS ((struct disassemble_info *)); | |
45 | static void parse_mips_dis_option | |
46 | PARAMS ((const char *, unsigned int)); | |
47 | static void parse_mips_dis_options | |
48 | PARAMS ((const char *)); | |
aa5f19f2 NC |
49 | static int _print_insn_mips |
50 | PARAMS ((bfd_vma, struct disassemble_info *, enum bfd_endian)); | |
51 | static int print_insn_mips | |
52 | PARAMS ((bfd_vma, unsigned long int, struct disassemble_info *)); | |
53 | static void print_insn_arg | |
54 | PARAMS ((const char *, unsigned long, bfd_vma, struct disassemble_info *)); | |
55 | static int print_insn_mips16 | |
56 | PARAMS ((bfd_vma, struct disassemble_info *)); | |
7fa108a4 AJ |
57 | static int is_newabi |
58 | PARAMS ((Elf_Internal_Ehdr *)); | |
252b5132 | 59 | static void print_mips16_insn_arg |
b34976b6 | 60 | PARAMS ((int, const struct mips_opcode *, int, bfd_boolean, int, bfd_vma, |
252b5132 | 61 | struct disassemble_info *)); |
252b5132 | 62 | \f |
aa5f19f2 | 63 | /* FIXME: These should be shared with gdb somehow. */ |
252b5132 RH |
64 | |
65 | /* The mips16 register names. */ | |
7f6621cd | 66 | static const char * const mips16_reg_names[] = { |
252b5132 RH |
67 | "s0", "s1", "v0", "v1", "a0", "a1", "a2", "a3" |
68 | }; | |
fb48caed | 69 | |
640c0ccd CD |
70 | static const char * const mips_gpr_names_numeric[32] = { |
71 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", | |
72 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
73 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
74 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
aa5f19f2 NC |
75 | }; |
76 | ||
640c0ccd CD |
77 | static const char * const mips_gpr_names_oldabi[32] = { |
78 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
79 | "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", | |
80 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
81 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
aa5f19f2 NC |
82 | }; |
83 | ||
640c0ccd CD |
84 | static const char * const mips_gpr_names_newabi[32] = { |
85 | "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3", | |
86 | "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3", | |
87 | "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", | |
88 | "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra" | |
89 | }; | |
90 | ||
91 | static const char * const mips_fpr_names_numeric[32] = { | |
92 | "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7", | |
93 | "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15", | |
94 | "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23", | |
95 | "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31" | |
96 | }; | |
97 | ||
98 | static const char * const mips_fpr_names_32[32] = { | |
99 | "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f", | |
100 | "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f", | |
101 | "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f", | |
102 | "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f" | |
103 | }; | |
104 | ||
105 | static const char * const mips_fpr_names_n32[32] = { | |
106 | "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3", | |
107 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
108 | "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9", | |
109 | "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13" | |
110 | }; | |
111 | ||
112 | static const char * const mips_fpr_names_64[32] = { | |
113 | "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3", | |
114 | "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3", | |
115 | "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11", | |
116 | "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7" | |
117 | }; | |
118 | ||
119 | static const char * const mips_cp0_names_numeric[32] = { | |
120 | "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7", | |
121 | "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15", | |
122 | "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23", | |
123 | "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31" | |
124 | }; | |
125 | ||
126 | static const char * const mips_cp0_names_mips3264[32] = { | |
127 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
128 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
129 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
130 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
131 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
132 | "c0_xcontext", "$21", "$22", "c0_debug", | |
133 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr", | |
134 | "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave", | |
135 | }; | |
136 | ||
137 | /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */ | |
138 | static const char * const mips_cp0_names_sb1[32] = { | |
139 | "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1", | |
140 | "c0_context", "c0_pagemask", "c0_wired", "$7", | |
141 | "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare", | |
142 | "c0_status", "c0_cause", "c0_epc", "c0_prid", | |
143 | "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi", | |
144 | "c0_xcontext", "$21", "$22", "c0_debug", | |
145 | "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i", | |
146 | "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave", | |
147 | }; | |
148 | ||
149 | struct mips_abi_choice { | |
150 | const char *name; | |
151 | const char * const *gpr_names; | |
152 | const char * const *fpr_names; | |
153 | }; | |
154 | ||
155 | struct mips_abi_choice mips_abi_choices[] = { | |
156 | { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric }, | |
157 | { "32", mips_gpr_names_oldabi, mips_fpr_names_32 }, | |
158 | { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 }, | |
159 | { "64", mips_gpr_names_newabi, mips_fpr_names_64 }, | |
160 | }; | |
161 | ||
162 | struct mips_arch_choice { | |
163 | const char *name; | |
164 | int bfd_mach_valid; | |
165 | unsigned long bfd_mach; | |
166 | int processor; | |
167 | int isa; | |
168 | const char * const *cp0_names; | |
169 | }; | |
170 | ||
171 | struct mips_arch_choice mips_arch_choices[] = { | |
172 | { "numeric", 0, 0, 0, 0, | |
173 | mips_cp0_names_numeric }, | |
174 | { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1, | |
175 | NULL }, | |
176 | { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1, | |
177 | NULL }, | |
178 | { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3, | |
179 | NULL }, | |
180 | { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2, | |
181 | NULL }, | |
182 | { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3, | |
183 | NULL }, | |
184 | { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3, | |
185 | NULL }, | |
186 | { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3, | |
187 | NULL }, | |
188 | { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3, | |
189 | NULL }, | |
190 | { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3, | |
191 | NULL }, | |
192 | { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3, | |
193 | NULL }, | |
194 | { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3, | |
195 | NULL }, | |
196 | { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4, | |
197 | NULL }, | |
198 | { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4, | |
199 | NULL }, | |
200 | { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4, | |
201 | NULL }, | |
202 | { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2, | |
203 | NULL }, | |
204 | { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4, | |
205 | NULL }, | |
206 | { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4, | |
207 | NULL }, | |
208 | { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4, | |
209 | NULL }, | |
210 | { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5, | |
211 | NULL }, | |
212 | /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs. | |
213 | Note that MIPS-3D and MDMX are not applicable to MIPS32. (See | |
214 | _MIPS32 Architecture For Programmers Volume I: Introduction to the | |
215 | MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95), | |
216 | page 1. */ | |
217 | { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32, | |
218 | ISA_MIPS32 | INSN_MIPS16, | |
219 | mips_cp0_names_mips3264 }, | |
220 | /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */ | |
221 | { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64, | |
222 | ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX, | |
223 | mips_cp0_names_mips3264 }, | |
224 | { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1, | |
225 | ISA_MIPS64 | INSN_MIPS3D | INSN_SB1, | |
226 | mips_cp0_names_sb1 }, | |
227 | ||
228 | /* This entry, mips16, is here only for ISA/processor selection; do | |
229 | not print its name. */ | |
230 | { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16, | |
231 | NULL }, | |
232 | }; | |
233 | ||
234 | /* ISA and processor type to disassemble for, and register names to use. | |
235 | set_default_mips_dis_options and parse_mips_dis_options fill in these | |
236 | values. */ | |
237 | static int mips_processor; | |
238 | static int mips_isa; | |
239 | static const char * const *mips_gpr_names; | |
240 | static const char * const *mips_fpr_names; | |
241 | static const char * const *mips_cp0_names; | |
242 | ||
243 | static const struct mips_abi_choice *choose_abi_by_name | |
244 | PARAMS ((const char *, unsigned int)); | |
245 | static const struct mips_arch_choice *choose_arch_by_name | |
246 | PARAMS ((const char *, unsigned int)); | |
247 | static const struct mips_arch_choice *choose_arch_by_number | |
248 | PARAMS ((unsigned long)); | |
249 | \f | |
250 | static const struct mips_abi_choice * | |
251 | choose_abi_by_name (name, namelen) | |
252 | const char *name; | |
253 | unsigned int namelen; | |
254 | { | |
255 | const struct mips_abi_choice *c; | |
256 | unsigned int i; | |
257 | ||
258 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++) | |
259 | { | |
260 | if (strncmp (mips_abi_choices[i].name, name, namelen) == 0 | |
261 | && strlen (mips_abi_choices[i].name) == namelen) | |
262 | c = &mips_abi_choices[i]; | |
263 | } | |
264 | return c; | |
265 | } | |
266 | ||
267 | static const struct mips_arch_choice * | |
268 | choose_arch_by_name (name, namelen) | |
269 | const char *name; | |
270 | unsigned int namelen; | |
271 | { | |
272 | const struct mips_arch_choice *c = NULL; | |
273 | unsigned int i; | |
274 | ||
275 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
276 | { | |
277 | if (strncmp (mips_arch_choices[i].name, name, namelen) == 0 | |
278 | && strlen (mips_arch_choices[i].name) == namelen) | |
279 | c = &mips_arch_choices[i]; | |
280 | } | |
281 | return c; | |
282 | } | |
283 | ||
284 | static const struct mips_arch_choice * | |
285 | choose_arch_by_number (mach) | |
286 | unsigned long mach; | |
287 | { | |
288 | static unsigned long hint_bfd_mach; | |
289 | static const struct mips_arch_choice *hint_arch_choice; | |
290 | const struct mips_arch_choice *c; | |
291 | unsigned int i; | |
292 | ||
293 | /* We optimize this because even if the user specifies no | |
294 | flags, this will be done for every instruction! */ | |
295 | if (hint_bfd_mach == mach | |
296 | && hint_arch_choice != NULL | |
297 | && hint_arch_choice->bfd_mach == hint_bfd_mach) | |
298 | return hint_arch_choice; | |
299 | ||
300 | for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++) | |
301 | { | |
302 | if (mips_arch_choices[i].bfd_mach_valid | |
303 | && mips_arch_choices[i].bfd_mach == mach) | |
304 | { | |
305 | c = &mips_arch_choices[i]; | |
306 | hint_bfd_mach = mach; | |
307 | hint_arch_choice = c; | |
308 | } | |
309 | } | |
310 | return c; | |
311 | } | |
312 | ||
313 | void | |
314 | set_default_mips_dis_options (info) | |
315 | struct disassemble_info *info; | |
316 | { | |
317 | const struct mips_arch_choice *chosen_arch; | |
318 | ||
319 | /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names, | |
320 | and numeric FPR and CP0 register names. */ | |
321 | mips_isa = ISA_MIPS3; | |
322 | mips_processor = CPU_R3000; | |
323 | mips_gpr_names = mips_gpr_names_oldabi; | |
324 | mips_fpr_names = mips_fpr_names_numeric; | |
325 | mips_cp0_names = mips_cp0_names_numeric; | |
326 | ||
327 | /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */ | |
328 | if (info->flavour == bfd_target_elf_flavour && info->symbols != NULL) | |
329 | { | |
330 | Elf_Internal_Ehdr *header; | |
331 | ||
332 | header = elf_elfheader (bfd_asymbol_bfd (*(info->symbols))); | |
333 | if (is_newabi (header)) | |
334 | mips_gpr_names = mips_gpr_names_newabi; | |
335 | } | |
336 | ||
337 | /* Set ISA, architecture, and cp0 register names as best we can. */ | |
338 | #if ! SYMTAB_AVAILABLE | |
339 | /* This is running out on a target machine, not in a host tool. | |
340 | FIXME: Where does mips_target_info come from? */ | |
341 | target_processor = mips_target_info.processor; | |
342 | mips_isa = mips_target_info.isa; | |
343 | #else | |
344 | chosen_arch = choose_arch_by_number (info->mach); | |
345 | if (chosen_arch != NULL) | |
346 | { | |
347 | mips_processor = chosen_arch->processor; | |
348 | mips_isa = chosen_arch->isa; | |
349 | if (chosen_arch->cp0_names != NULL) | |
350 | mips_cp0_names = chosen_arch->cp0_names; | |
351 | } | |
352 | #endif | |
353 | } | |
354 | ||
355 | void | |
356 | parse_mips_dis_option (option, len) | |
357 | const char *option; | |
358 | unsigned int len; | |
359 | { | |
360 | unsigned int i, optionlen, vallen; | |
361 | const char *val; | |
362 | const struct mips_abi_choice *chosen_abi; | |
363 | const struct mips_arch_choice *chosen_arch; | |
364 | ||
365 | /* Look for the = that delimits the end of the option name. */ | |
366 | for (i = 0; i < len; i++) | |
367 | { | |
368 | if (option[i] == '=') | |
369 | break; | |
370 | } | |
371 | if (i == 0) /* Invalid option: no name before '='. */ | |
372 | return; | |
373 | if (i == len) /* Invalid option: no '='. */ | |
374 | return; | |
375 | if (i == (len - 1)) /* Invalid option: no value after '='. */ | |
376 | return; | |
377 | ||
378 | optionlen = i; | |
379 | val = option + (optionlen + 1); | |
380 | vallen = len - (optionlen + 1); | |
381 | ||
382 | if (strncmp("gpr-names", option, optionlen) == 0 | |
383 | && strlen("gpr-names") == optionlen) | |
384 | { | |
385 | chosen_abi = choose_abi_by_name (val, vallen); | |
386 | if (chosen_abi != NULL && chosen_abi->gpr_names != NULL) | |
387 | mips_gpr_names = chosen_abi->gpr_names; | |
388 | return; | |
389 | } | |
390 | ||
391 | if (strncmp("fpr-names", option, optionlen) == 0 | |
392 | && strlen("fpr-names") == optionlen) | |
393 | { | |
394 | chosen_abi = choose_abi_by_name (val, vallen); | |
395 | if (chosen_abi != NULL && chosen_abi->fpr_names != NULL) | |
396 | mips_fpr_names = chosen_abi->fpr_names; | |
397 | return; | |
398 | } | |
399 | ||
400 | if (strncmp("cp0-names", option, optionlen) == 0 | |
401 | && strlen("cp0-names") == optionlen) | |
402 | { | |
403 | chosen_arch = choose_arch_by_name (val, vallen); | |
404 | if (chosen_arch != NULL && chosen_arch->cp0_names != NULL) | |
405 | mips_cp0_names = chosen_arch->cp0_names; | |
406 | return; | |
407 | } | |
408 | ||
409 | if (strncmp("reg-names", option, optionlen) == 0 | |
410 | && strlen("reg-names") == optionlen) | |
411 | { | |
412 | /* We check both ABI and ARCH here unconditionally, so | |
413 | that "numeric" will do the desirable thing: select | |
414 | numeric register names for all registers. Other than | |
415 | that, a given name probably won't match both. */ | |
416 | chosen_abi = choose_abi_by_name (val, vallen); | |
417 | if (chosen_abi != NULL) | |
418 | { | |
419 | if (chosen_abi->gpr_names != NULL) | |
420 | mips_gpr_names = chosen_abi->gpr_names; | |
421 | if (chosen_abi->fpr_names != NULL) | |
422 | mips_fpr_names = chosen_abi->fpr_names; | |
423 | } | |
424 | chosen_arch = choose_arch_by_name (val, vallen); | |
425 | if (chosen_arch != NULL) | |
426 | { | |
427 | if (chosen_arch->cp0_names != NULL) | |
428 | mips_cp0_names = chosen_arch->cp0_names; | |
429 | } | |
430 | return; | |
431 | } | |
432 | ||
433 | /* Invalid option. */ | |
434 | } | |
435 | ||
436 | void | |
437 | parse_mips_dis_options (options) | |
438 | const char *options; | |
439 | { | |
440 | const char *option_end; | |
441 | ||
442 | if (options == NULL) | |
443 | return; | |
444 | ||
445 | while (*options != '\0') | |
446 | { | |
447 | /* Skip empty options. */ | |
448 | if (*options == ',') | |
449 | { | |
450 | options++; | |
451 | continue; | |
452 | } | |
453 | ||
454 | /* We know that *options is neither NUL or a comma. */ | |
455 | option_end = options + 1; | |
456 | while (*option_end != ',' && *option_end != '\0') | |
457 | option_end++; | |
458 | ||
459 | parse_mips_dis_option (options, option_end - options); | |
460 | ||
461 | /* Go on to the next one. If option_end points to a comma, it | |
462 | will be skipped above. */ | |
463 | options = option_end; | |
464 | } | |
465 | } | |
466 | ||
252b5132 | 467 | \f |
7f6621cd | 468 | /* Print insn arguments for 32/64-bit code. */ |
aa5f19f2 | 469 | |
252b5132 RH |
470 | static void |
471 | print_insn_arg (d, l, pc, info) | |
472 | const char *d; | |
473 | register unsigned long int l; | |
474 | bfd_vma pc; | |
475 | struct disassemble_info *info; | |
476 | { | |
640c0ccd | 477 | int op, delta; |
252b5132 RH |
478 | |
479 | switch (*d) | |
480 | { | |
481 | case ',': | |
482 | case '(': | |
483 | case ')': | |
9752cf1b RS |
484 | case '[': |
485 | case ']': | |
252b5132 RH |
486 | (*info->fprintf_func) (info->stream, "%c", *d); |
487 | break; | |
488 | ||
489 | case 's': | |
490 | case 'b': | |
491 | case 'r': | |
492 | case 'v': | |
aa5f19f2 | 493 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 494 | mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]); |
252b5132 RH |
495 | break; |
496 | ||
497 | case 't': | |
498 | case 'w': | |
aa5f19f2 | 499 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 500 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
252b5132 RH |
501 | break; |
502 | ||
503 | case 'i': | |
504 | case 'u': | |
505 | (*info->fprintf_func) (info->stream, "0x%x", | |
7f6621cd | 506 | (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE); |
252b5132 RH |
507 | break; |
508 | ||
7f6621cd | 509 | case 'j': /* Same as i, but sign-extended. */ |
252b5132 RH |
510 | case 'o': |
511 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; | |
512 | if (delta & 0x8000) | |
513 | delta |= ~0xffff; | |
514 | (*info->fprintf_func) (info->stream, "%d", | |
515 | delta); | |
516 | break; | |
517 | ||
518 | case 'h': | |
519 | (*info->fprintf_func) (info->stream, "0x%x", | |
520 | (unsigned int) ((l >> OP_SH_PREFX) | |
521 | & OP_MASK_PREFX)); | |
522 | break; | |
523 | ||
524 | case 'k': | |
525 | (*info->fprintf_func) (info->stream, "0x%x", | |
526 | (unsigned int) ((l >> OP_SH_CACHE) | |
527 | & OP_MASK_CACHE)); | |
528 | break; | |
529 | ||
530 | case 'a': | |
9bb28706 CD |
531 | info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff) |
532 | | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2)); | |
533 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
534 | break; |
535 | ||
536 | case 'p': | |
7f6621cd | 537 | /* Sign extend the displacement. */ |
252b5132 RH |
538 | delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA; |
539 | if (delta & 0x8000) | |
540 | delta |= ~0xffff; | |
9bb28706 CD |
541 | info->target = (delta << 2) + pc + INSNLEN; |
542 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
543 | break; |
544 | ||
545 | case 'd': | |
aa5f19f2 | 546 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 547 | mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]); |
252b5132 RH |
548 | break; |
549 | ||
4372b673 NC |
550 | case 'U': |
551 | { | |
7f6621cd KH |
552 | /* First check for both rd and rt being equal. */ |
553 | unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD; | |
554 | if (reg == ((l >> OP_SH_RT) & OP_MASK_RT)) | |
555 | (*info->fprintf_func) (info->stream, "%s", | |
640c0ccd | 556 | mips_gpr_names[reg]); |
7f6621cd KH |
557 | else |
558 | { | |
559 | /* If one is zero use the other. */ | |
560 | if (reg == 0) | |
561 | (*info->fprintf_func) (info->stream, "%s", | |
640c0ccd | 562 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); |
7f6621cd KH |
563 | else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0) |
564 | (*info->fprintf_func) (info->stream, "%s", | |
640c0ccd | 565 | mips_gpr_names[reg]); |
7f6621cd KH |
566 | else /* Bogus, result depends on processor. */ |
567 | (*info->fprintf_func) (info->stream, "%s or %s", | |
640c0ccd CD |
568 | mips_gpr_names[reg], |
569 | mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]); | |
7f6621cd | 570 | } |
4372b673 NC |
571 | } |
572 | break; | |
573 | ||
252b5132 | 574 | case 'z': |
640c0ccd | 575 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
252b5132 RH |
576 | break; |
577 | ||
578 | case '<': | |
579 | (*info->fprintf_func) (info->stream, "0x%x", | |
580 | (l >> OP_SH_SHAMT) & OP_MASK_SHAMT); | |
581 | break; | |
582 | ||
583 | case 'c': | |
584 | (*info->fprintf_func) (info->stream, "0x%x", | |
585 | (l >> OP_SH_CODE) & OP_MASK_CODE); | |
586 | break; | |
587 | ||
252b5132 RH |
588 | case 'q': |
589 | (*info->fprintf_func) (info->stream, "0x%x", | |
590 | (l >> OP_SH_CODE2) & OP_MASK_CODE2); | |
591 | break; | |
592 | ||
593 | case 'C': | |
594 | (*info->fprintf_func) (info->stream, "0x%x", | |
595 | (l >> OP_SH_COPZ) & OP_MASK_COPZ); | |
596 | break; | |
597 | ||
598 | case 'B': | |
599 | (*info->fprintf_func) (info->stream, "0x%x", | |
4372b673 NC |
600 | (l >> OP_SH_CODE20) & OP_MASK_CODE20); |
601 | break; | |
602 | ||
603 | case 'J': | |
604 | (*info->fprintf_func) (info->stream, "0x%x", | |
605 | (l >> OP_SH_CODE19) & OP_MASK_CODE19); | |
252b5132 RH |
606 | break; |
607 | ||
608 | case 'S': | |
609 | case 'V': | |
640c0ccd CD |
610 | (*info->fprintf_func) (info->stream, "%s", |
611 | mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]); | |
252b5132 RH |
612 | break; |
613 | ||
252b5132 RH |
614 | case 'T': |
615 | case 'W': | |
640c0ccd CD |
616 | (*info->fprintf_func) (info->stream, "%s", |
617 | mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]); | |
252b5132 RH |
618 | break; |
619 | ||
620 | case 'D': | |
640c0ccd CD |
621 | (*info->fprintf_func) (info->stream, "%s", |
622 | mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]); | |
252b5132 RH |
623 | break; |
624 | ||
625 | case 'R': | |
640c0ccd CD |
626 | (*info->fprintf_func) (info->stream, "%s", |
627 | mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]); | |
252b5132 RH |
628 | break; |
629 | ||
630 | case 'E': | |
640c0ccd CD |
631 | /* Coprocessor register for lwcN instructions, et al. |
632 | ||
633 | Note that there is no load/store cp0 instructions, and | |
634 | that FPU (cp1) instructions disassemble this field using | |
635 | 'T' format. Therefore, until we gain understanding of | |
636 | cp2 register names, | |
637 | we can simply print the register numbers. */ | |
21d34b1c TS |
638 | (*info->fprintf_func) (info->stream, "$%d", |
639 | (l >> OP_SH_RT) & OP_MASK_RT); | |
252b5132 RH |
640 | break; |
641 | ||
642 | case 'G': | |
640c0ccd CD |
643 | /* Coprocessor register for mtcN instructions, et al. |
644 | Note that FPU (cp1) instructions disassemble this field using | |
645 | 'S' format. Therefore, we only need to worry about cp0, cp2, | |
646 | and cp3. */ | |
647 | op = (l >> OP_SH_OP) & OP_MASK_OP; | |
648 | if (op == OP_OP_COP0) | |
649 | (*info->fprintf_func) (info->stream, "%s", | |
650 | mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]); | |
651 | else | |
652 | (*info->fprintf_func) (info->stream, "$%d", | |
653 | (l >> OP_SH_RD) & OP_MASK_RD); | |
252b5132 RH |
654 | break; |
655 | ||
656 | case 'N': | |
657 | (*info->fprintf_func) (info->stream, "$fcc%d", | |
658 | (l >> OP_SH_BCC) & OP_MASK_BCC); | |
659 | break; | |
660 | ||
661 | case 'M': | |
662 | (*info->fprintf_func) (info->stream, "$fcc%d", | |
663 | (l >> OP_SH_CCC) & OP_MASK_CCC); | |
664 | break; | |
665 | ||
666 | case 'P': | |
667 | (*info->fprintf_func) (info->stream, "%d", | |
668 | (l >> OP_SH_PERFREG) & OP_MASK_PERFREG); | |
669 | break; | |
670 | ||
9752cf1b RS |
671 | case 'e': |
672 | (*info->fprintf_func) (info->stream, "%d", | |
673 | (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE); | |
674 | break; | |
675 | ||
676 | case '%': | |
677 | (*info->fprintf_func) (info->stream, "%d", | |
678 | (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN); | |
679 | break; | |
680 | ||
156c2f8b | 681 | case 'H': |
e93d7199 | 682 | (*info->fprintf_func) (info->stream, "%d", |
156c2f8b NC |
683 | (l >> OP_SH_SEL) & OP_MASK_SEL); |
684 | break; | |
252b5132 | 685 | |
deec1734 CD |
686 | case 'O': |
687 | (*info->fprintf_func) (info->stream, "%d", | |
688 | (l >> OP_SH_ALN) & OP_MASK_ALN); | |
689 | break; | |
690 | ||
691 | case 'Q': | |
692 | { | |
693 | unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL; | |
694 | if ((vsel & 0x10) == 0) | |
695 | { | |
696 | int fmt; | |
697 | vsel &= 0x0f; | |
698 | for (fmt = 0; fmt < 3; fmt++, vsel >>= 1) | |
699 | if ((vsel & 1) == 0) | |
700 | break; | |
701 | (*info->fprintf_func) (info->stream, "$v%d[%d]", | |
b34976b6 | 702 | (l >> OP_SH_FT) & OP_MASK_FT, |
deec1734 CD |
703 | vsel >> 1); |
704 | } | |
705 | else if ((vsel & 0x08) == 0) | |
706 | { | |
707 | (*info->fprintf_func) (info->stream, "$v%d", | |
708 | (l >> OP_SH_FT) & OP_MASK_FT); | |
709 | } | |
710 | else | |
711 | { | |
712 | (*info->fprintf_func) (info->stream, "0x%x", | |
713 | (l >> OP_SH_FT) & OP_MASK_FT); | |
714 | } | |
715 | } | |
716 | break; | |
717 | ||
718 | case 'X': | |
719 | (*info->fprintf_func) (info->stream, "$v%d", | |
720 | (l >> OP_SH_FD) & OP_MASK_FD); | |
721 | break; | |
722 | ||
723 | case 'Y': | |
724 | (*info->fprintf_func) (info->stream, "$v%d", | |
725 | (l >> OP_SH_FS) & OP_MASK_FS); | |
726 | break; | |
727 | ||
728 | case 'Z': | |
729 | (*info->fprintf_func) (info->stream, "$v%d", | |
730 | (l >> OP_SH_FT) & OP_MASK_FT); | |
731 | break; | |
732 | ||
252b5132 RH |
733 | default: |
734 | /* xgettext:c-format */ | |
735 | (*info->fprintf_func) (info->stream, | |
736 | _("# internal error, undefined modifier(%c)"), | |
737 | *d); | |
738 | break; | |
739 | } | |
740 | } | |
741 | \f | |
21d34b1c | 742 | /* Check if the object uses NewABI conventions. */ |
aa5f19f2 NC |
743 | |
744 | static int | |
7f6621cd | 745 | is_newabi (header) |
21d34b1c | 746 | Elf_Internal_Ehdr *header; |
aa5f19f2 | 747 | { |
4c563ebf CD |
748 | /* There are no old-style ABIs which use 64-bit ELF. */ |
749 | if (header->e_ident[EI_CLASS] == ELFCLASS64) | |
750 | return 1; | |
751 | ||
563773fe TS |
752 | /* If a 32-bit ELF file, n32 is a new-style ABI. */ |
753 | if ((header->e_flags & EF_MIPS_ABI2) != 0) | |
21d34b1c | 754 | return 1; |
252b5132 | 755 | |
21d34b1c | 756 | return 0; |
aa5f19f2 NC |
757 | } |
758 | \f | |
252b5132 RH |
759 | /* Print the mips instruction at address MEMADDR in debugged memory, |
760 | on using INFO. Returns length of the instruction, in bytes, which is | |
aa5f19f2 | 761 | always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if |
252b5132 RH |
762 | this is little-endian code. */ |
763 | ||
764 | static int | |
aa5f19f2 | 765 | print_insn_mips (memaddr, word, info) |
252b5132 RH |
766 | bfd_vma memaddr; |
767 | unsigned long int word; | |
768 | struct disassemble_info *info; | |
769 | { | |
770 | register const struct mips_opcode *op; | |
b34976b6 | 771 | static bfd_boolean init = 0; |
252b5132 RH |
772 | static const struct mips_opcode *mips_hash[OP_MASK_OP + 1]; |
773 | ||
774 | /* Build a hash table to shorten the search time. */ | |
775 | if (! init) | |
776 | { | |
777 | unsigned int i; | |
778 | ||
779 | for (i = 0; i <= OP_MASK_OP; i++) | |
780 | { | |
781 | for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++) | |
782 | { | |
783 | if (op->pinfo == INSN_MACRO) | |
784 | continue; | |
785 | if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP)) | |
786 | { | |
787 | mips_hash[i] = op; | |
788 | break; | |
789 | } | |
790 | } | |
7f6621cd | 791 | } |
252b5132 RH |
792 | |
793 | init = 1; | |
794 | } | |
795 | ||
aa5f19f2 | 796 | info->bytes_per_chunk = INSNLEN; |
252b5132 | 797 | info->display_endian = info->endian; |
9bb28706 CD |
798 | info->insn_info_valid = 1; |
799 | info->branch_delay_insns = 0; | |
def7143b | 800 | info->data_size = 0; |
9bb28706 CD |
801 | info->insn_type = dis_nonbranch; |
802 | info->target = 0; | |
803 | info->target2 = 0; | |
252b5132 RH |
804 | |
805 | op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP]; | |
806 | if (op != NULL) | |
807 | { | |
808 | for (; op < &mips_opcodes[NUMOPCODES]; op++) | |
809 | { | |
810 | if (op->pinfo != INSN_MACRO && (word & op->mask) == op->match) | |
811 | { | |
812 | register const char *d; | |
2bd7f1f3 | 813 | |
3396de36 | 814 | /* We always allow to disassemble the jalx instruction. */ |
640c0ccd | 815 | if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor) |
3396de36 | 816 | && strcmp (op->name, "jalx")) |
252b5132 RH |
817 | continue; |
818 | ||
9bb28706 CD |
819 | /* Figure out instruction type and branch delay information. */ |
820 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
821 | { | |
822 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
823 | info->insn_type = dis_jsr; | |
824 | else | |
825 | info->insn_type = dis_branch; | |
826 | info->branch_delay_insns = 1; | |
827 | } | |
828 | else if ((op->pinfo & (INSN_COND_BRANCH_DELAY | |
829 | | INSN_COND_BRANCH_LIKELY)) != 0) | |
830 | { | |
831 | if ((info->insn_type & INSN_WRITE_GPR_31) != 0) | |
832 | info->insn_type = dis_condjsr; | |
833 | else | |
834 | info->insn_type = dis_condbranch; | |
835 | info->branch_delay_insns = 1; | |
836 | } | |
837 | else if ((op->pinfo & (INSN_STORE_MEMORY | |
838 | | INSN_LOAD_MEMORY_DELAY)) != 0) | |
839 | info->insn_type = dis_dref; | |
840 | ||
252b5132 RH |
841 | (*info->fprintf_func) (info->stream, "%s", op->name); |
842 | ||
843 | d = op->args; | |
844 | if (d != NULL && *d != '\0') | |
845 | { | |
7f6621cd | 846 | (*info->fprintf_func) (info->stream, "\t"); |
252b5132 | 847 | for (; *d != '\0'; d++) |
7f6621cd | 848 | print_insn_arg (d, word, memaddr, info); |
252b5132 RH |
849 | } |
850 | ||
aa5f19f2 | 851 | return INSNLEN; |
252b5132 RH |
852 | } |
853 | } | |
854 | } | |
855 | ||
856 | /* Handle undefined instructions. */ | |
9bb28706 | 857 | info->insn_type = dis_noninsn; |
252b5132 | 858 | (*info->fprintf_func) (info->stream, "0x%x", word); |
aa5f19f2 | 859 | return INSNLEN; |
252b5132 | 860 | } |
aa5f19f2 | 861 | \f |
252b5132 RH |
862 | /* In an environment where we do not know the symbol type of the |
863 | instruction we are forced to assume that the low order bit of the | |
864 | instructions' address may mark it as a mips16 instruction. If we | |
865 | are single stepping, or the pc is within the disassembled function, | |
866 | this works. Otherwise, we need a clue. Sometimes. */ | |
867 | ||
aa5f19f2 NC |
868 | static int |
869 | _print_insn_mips (memaddr, info, endianness) | |
252b5132 RH |
870 | bfd_vma memaddr; |
871 | struct disassemble_info *info; | |
aa5f19f2 | 872 | enum bfd_endian endianness; |
252b5132 | 873 | { |
aa5f19f2 | 874 | bfd_byte buffer[INSNLEN]; |
252b5132 RH |
875 | int status; |
876 | ||
640c0ccd CD |
877 | set_default_mips_dis_options (info); |
878 | parse_mips_dis_options (info->disassembler_options); | |
879 | ||
252b5132 RH |
880 | #if 1 |
881 | /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */ | |
882 | /* Only a few tools will work this way. */ | |
883 | if (memaddr & 0x01) | |
884 | return print_insn_mips16 (memaddr, info); | |
e93d7199 | 885 | #endif |
252b5132 RH |
886 | |
887 | #if SYMTAB_AVAILABLE | |
53f32ea5 | 888 | if (info->mach == bfd_mach_mips16 |
252b5132 RH |
889 | || (info->flavour == bfd_target_elf_flavour |
890 | && info->symbols != NULL | |
891 | && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other | |
892 | == STO_MIPS16))) | |
893 | return print_insn_mips16 (memaddr, info); | |
e93d7199 | 894 | #endif |
252b5132 | 895 | |
aa5f19f2 | 896 | status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info); |
252b5132 | 897 | if (status == 0) |
aa5f19f2 NC |
898 | { |
899 | unsigned long insn; | |
900 | ||
901 | if (endianness == BFD_ENDIAN_BIG) | |
7f6621cd | 902 | insn = (unsigned long) bfd_getb32 (buffer); |
aa5f19f2 NC |
903 | else |
904 | insn = (unsigned long) bfd_getl32 (buffer); | |
905 | ||
906 | return print_insn_mips (memaddr, insn, info); | |
907 | } | |
252b5132 RH |
908 | else |
909 | { | |
910 | (*info->memory_error_func) (status, memaddr, info); | |
911 | return -1; | |
912 | } | |
913 | } | |
914 | ||
915 | int | |
aa5f19f2 | 916 | print_insn_big_mips (memaddr, info) |
252b5132 RH |
917 | bfd_vma memaddr; |
918 | struct disassemble_info *info; | |
919 | { | |
aa5f19f2 NC |
920 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG); |
921 | } | |
252b5132 | 922 | |
aa5f19f2 NC |
923 | int |
924 | print_insn_little_mips (memaddr, info) | |
925 | bfd_vma memaddr; | |
926 | struct disassemble_info *info; | |
927 | { | |
928 | return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE); | |
252b5132 RH |
929 | } |
930 | \f | |
931 | /* Disassemble mips16 instructions. */ | |
932 | ||
933 | static int | |
934 | print_insn_mips16 (memaddr, info) | |
935 | bfd_vma memaddr; | |
936 | struct disassemble_info *info; | |
937 | { | |
938 | int status; | |
939 | bfd_byte buffer[2]; | |
940 | int length; | |
941 | int insn; | |
b34976b6 | 942 | bfd_boolean use_extend; |
252b5132 RH |
943 | int extend = 0; |
944 | const struct mips_opcode *op, *opend; | |
945 | ||
946 | info->bytes_per_chunk = 2; | |
947 | info->display_endian = info->endian; | |
252b5132 RH |
948 | info->insn_info_valid = 1; |
949 | info->branch_delay_insns = 0; | |
950 | info->data_size = 0; | |
951 | info->insn_type = dis_nonbranch; | |
952 | info->target = 0; | |
953 | info->target2 = 0; | |
954 | ||
955 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
956 | if (status != 0) | |
957 | { | |
958 | (*info->memory_error_func) (status, memaddr, info); | |
959 | return -1; | |
960 | } | |
961 | ||
962 | length = 2; | |
963 | ||
964 | if (info->endian == BFD_ENDIAN_BIG) | |
965 | insn = bfd_getb16 (buffer); | |
966 | else | |
967 | insn = bfd_getl16 (buffer); | |
968 | ||
969 | /* Handle the extend opcode specially. */ | |
b34976b6 | 970 | use_extend = FALSE; |
252b5132 RH |
971 | if ((insn & 0xf800) == 0xf000) |
972 | { | |
b34976b6 | 973 | use_extend = TRUE; |
252b5132 RH |
974 | extend = insn & 0x7ff; |
975 | ||
976 | memaddr += 2; | |
977 | ||
978 | status = (*info->read_memory_func) (memaddr, buffer, 2, info); | |
979 | if (status != 0) | |
980 | { | |
981 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
982 | (unsigned int) extend); | |
983 | (*info->memory_error_func) (status, memaddr, info); | |
984 | return -1; | |
985 | } | |
986 | ||
987 | if (info->endian == BFD_ENDIAN_BIG) | |
988 | insn = bfd_getb16 (buffer); | |
989 | else | |
990 | insn = bfd_getl16 (buffer); | |
991 | ||
992 | /* Check for an extend opcode followed by an extend opcode. */ | |
993 | if ((insn & 0xf800) == 0xf000) | |
994 | { | |
995 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
996 | (unsigned int) extend); | |
997 | info->insn_type = dis_noninsn; | |
998 | return length; | |
999 | } | |
1000 | ||
1001 | length += 2; | |
1002 | } | |
1003 | ||
1004 | /* FIXME: Should probably use a hash table on the major opcode here. */ | |
1005 | ||
1006 | opend = mips16_opcodes + bfd_mips16_num_opcodes; | |
1007 | for (op = mips16_opcodes; op < opend; op++) | |
1008 | { | |
1009 | if (op->pinfo != INSN_MACRO && (insn & op->mask) == op->match) | |
1010 | { | |
1011 | const char *s; | |
1012 | ||
1013 | if (strchr (op->args, 'a') != NULL) | |
1014 | { | |
1015 | if (use_extend) | |
1016 | { | |
1017 | (*info->fprintf_func) (info->stream, "extend 0x%x", | |
1018 | (unsigned int) extend); | |
1019 | info->insn_type = dis_noninsn; | |
1020 | return length - 2; | |
1021 | } | |
1022 | ||
b34976b6 | 1023 | use_extend = FALSE; |
252b5132 RH |
1024 | |
1025 | memaddr += 2; | |
1026 | ||
1027 | status = (*info->read_memory_func) (memaddr, buffer, 2, | |
1028 | info); | |
1029 | if (status == 0) | |
1030 | { | |
b34976b6 | 1031 | use_extend = TRUE; |
252b5132 RH |
1032 | if (info->endian == BFD_ENDIAN_BIG) |
1033 | extend = bfd_getb16 (buffer); | |
1034 | else | |
1035 | extend = bfd_getl16 (buffer); | |
1036 | length += 2; | |
1037 | } | |
1038 | } | |
1039 | ||
1040 | (*info->fprintf_func) (info->stream, "%s", op->name); | |
1041 | if (op->args[0] != '\0') | |
1042 | (*info->fprintf_func) (info->stream, "\t"); | |
1043 | ||
1044 | for (s = op->args; *s != '\0'; s++) | |
1045 | { | |
1046 | if (*s == ',' | |
1047 | && s[1] == 'w' | |
1048 | && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX) | |
1049 | == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY))) | |
1050 | { | |
1051 | /* Skip the register and the comma. */ | |
1052 | ++s; | |
1053 | continue; | |
1054 | } | |
1055 | if (*s == ',' | |
1056 | && s[1] == 'v' | |
1057 | && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ) | |
1058 | == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX))) | |
1059 | { | |
1060 | /* Skip the register and the comma. */ | |
1061 | ++s; | |
1062 | continue; | |
1063 | } | |
1064 | print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr, | |
1065 | info); | |
1066 | } | |
1067 | ||
1068 | if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0) | |
1069 | { | |
1070 | info->branch_delay_insns = 1; | |
1071 | if (info->insn_type != dis_jsr) | |
1072 | info->insn_type = dis_branch; | |
1073 | } | |
1074 | ||
1075 | return length; | |
1076 | } | |
1077 | } | |
1078 | ||
1079 | if (use_extend) | |
1080 | (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000); | |
1081 | (*info->fprintf_func) (info->stream, "0x%x", insn); | |
1082 | info->insn_type = dis_noninsn; | |
1083 | ||
1084 | return length; | |
1085 | } | |
1086 | ||
1087 | /* Disassemble an operand for a mips16 instruction. */ | |
1088 | ||
1089 | static void | |
1090 | print_mips16_insn_arg (type, op, l, use_extend, extend, memaddr, info) | |
aa5f19f2 | 1091 | char type; |
252b5132 RH |
1092 | const struct mips_opcode *op; |
1093 | int l; | |
b34976b6 | 1094 | bfd_boolean use_extend; |
252b5132 RH |
1095 | int extend; |
1096 | bfd_vma memaddr; | |
1097 | struct disassemble_info *info; | |
1098 | { | |
1099 | switch (type) | |
1100 | { | |
1101 | case ',': | |
1102 | case '(': | |
1103 | case ')': | |
1104 | (*info->fprintf_func) (info->stream, "%c", type); | |
1105 | break; | |
1106 | ||
1107 | case 'y': | |
1108 | case 'w': | |
aa5f19f2 | 1109 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1110 | mips16_reg_names[((l >> MIPS16OP_SH_RY) |
1111 | & MIPS16OP_MASK_RY)]); | |
1112 | break; | |
1113 | ||
1114 | case 'x': | |
1115 | case 'v': | |
aa5f19f2 | 1116 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1117 | mips16_reg_names[((l >> MIPS16OP_SH_RX) |
1118 | & MIPS16OP_MASK_RX)]); | |
1119 | break; | |
1120 | ||
1121 | case 'z': | |
aa5f19f2 | 1122 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1123 | mips16_reg_names[((l >> MIPS16OP_SH_RZ) |
1124 | & MIPS16OP_MASK_RZ)]); | |
1125 | break; | |
1126 | ||
1127 | case 'Z': | |
aa5f19f2 | 1128 | (*info->fprintf_func) (info->stream, "%s", |
252b5132 RH |
1129 | mips16_reg_names[((l >> MIPS16OP_SH_MOVE32Z) |
1130 | & MIPS16OP_MASK_MOVE32Z)]); | |
1131 | break; | |
1132 | ||
1133 | case '0': | |
640c0ccd | 1134 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]); |
252b5132 RH |
1135 | break; |
1136 | ||
1137 | case 'S': | |
640c0ccd | 1138 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]); |
252b5132 RH |
1139 | break; |
1140 | ||
1141 | case 'P': | |
1142 | (*info->fprintf_func) (info->stream, "$pc"); | |
1143 | break; | |
1144 | ||
1145 | case 'R': | |
640c0ccd | 1146 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]); |
252b5132 RH |
1147 | break; |
1148 | ||
1149 | case 'X': | |
aa5f19f2 | 1150 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd CD |
1151 | mips_gpr_names[((l >> MIPS16OP_SH_REGR32) |
1152 | & MIPS16OP_MASK_REGR32)]); | |
252b5132 RH |
1153 | break; |
1154 | ||
1155 | case 'Y': | |
aa5f19f2 | 1156 | (*info->fprintf_func) (info->stream, "%s", |
640c0ccd | 1157 | mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]); |
252b5132 RH |
1158 | break; |
1159 | ||
1160 | case '<': | |
1161 | case '>': | |
1162 | case '[': | |
1163 | case ']': | |
1164 | case '4': | |
1165 | case '5': | |
1166 | case 'H': | |
1167 | case 'W': | |
1168 | case 'D': | |
1169 | case 'j': | |
1170 | case '6': | |
1171 | case '8': | |
1172 | case 'V': | |
1173 | case 'C': | |
1174 | case 'U': | |
1175 | case 'k': | |
1176 | case 'K': | |
1177 | case 'p': | |
1178 | case 'q': | |
1179 | case 'A': | |
1180 | case 'B': | |
1181 | case 'E': | |
1182 | { | |
1183 | int immed, nbits, shift, signedp, extbits, pcrel, extu, branch; | |
1184 | ||
1185 | shift = 0; | |
1186 | signedp = 0; | |
1187 | extbits = 16; | |
1188 | pcrel = 0; | |
1189 | extu = 0; | |
1190 | branch = 0; | |
1191 | switch (type) | |
1192 | { | |
1193 | case '<': | |
1194 | nbits = 3; | |
1195 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
1196 | extbits = 5; | |
1197 | extu = 1; | |
1198 | break; | |
1199 | case '>': | |
1200 | nbits = 3; | |
1201 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
1202 | extbits = 5; | |
1203 | extu = 1; | |
1204 | break; | |
1205 | case '[': | |
1206 | nbits = 3; | |
1207 | immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ; | |
1208 | extbits = 6; | |
1209 | extu = 1; | |
1210 | break; | |
1211 | case ']': | |
1212 | nbits = 3; | |
1213 | immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX; | |
1214 | extbits = 6; | |
1215 | extu = 1; | |
1216 | break; | |
1217 | case '4': | |
1218 | nbits = 4; | |
1219 | immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4; | |
1220 | signedp = 1; | |
1221 | extbits = 15; | |
1222 | break; | |
1223 | case '5': | |
1224 | nbits = 5; | |
1225 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1226 | info->insn_type = dis_dref; | |
1227 | info->data_size = 1; | |
1228 | break; | |
1229 | case 'H': | |
1230 | nbits = 5; | |
1231 | shift = 1; | |
1232 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1233 | info->insn_type = dis_dref; | |
1234 | info->data_size = 2; | |
1235 | break; | |
1236 | case 'W': | |
1237 | nbits = 5; | |
1238 | shift = 2; | |
1239 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1240 | if ((op->pinfo & MIPS16_INSN_READ_PC) == 0 | |
1241 | && (op->pinfo & MIPS16_INSN_READ_SP) == 0) | |
1242 | { | |
1243 | info->insn_type = dis_dref; | |
1244 | info->data_size = 4; | |
1245 | } | |
1246 | break; | |
1247 | case 'D': | |
1248 | nbits = 5; | |
1249 | shift = 3; | |
1250 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1251 | info->insn_type = dis_dref; | |
1252 | info->data_size = 8; | |
1253 | break; | |
1254 | case 'j': | |
1255 | nbits = 5; | |
1256 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1257 | signedp = 1; | |
1258 | break; | |
1259 | case '6': | |
1260 | nbits = 6; | |
1261 | immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1262 | break; | |
1263 | case '8': | |
1264 | nbits = 8; | |
1265 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1266 | break; | |
1267 | case 'V': | |
1268 | nbits = 8; | |
1269 | shift = 2; | |
1270 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1271 | /* FIXME: This might be lw, or it might be addiu to $sp or | |
1272 | $pc. We assume it's load. */ | |
1273 | info->insn_type = dis_dref; | |
1274 | info->data_size = 4; | |
1275 | break; | |
1276 | case 'C': | |
1277 | nbits = 8; | |
1278 | shift = 3; | |
1279 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1280 | info->insn_type = dis_dref; | |
1281 | info->data_size = 8; | |
1282 | break; | |
1283 | case 'U': | |
1284 | nbits = 8; | |
1285 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1286 | extu = 1; | |
1287 | break; | |
1288 | case 'k': | |
1289 | nbits = 8; | |
1290 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1291 | signedp = 1; | |
1292 | break; | |
1293 | case 'K': | |
1294 | nbits = 8; | |
1295 | shift = 3; | |
1296 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1297 | signedp = 1; | |
1298 | break; | |
1299 | case 'p': | |
1300 | nbits = 8; | |
1301 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1302 | signedp = 1; | |
1303 | pcrel = 1; | |
1304 | branch = 1; | |
1305 | info->insn_type = dis_condbranch; | |
1306 | break; | |
1307 | case 'q': | |
1308 | nbits = 11; | |
1309 | immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11; | |
1310 | signedp = 1; | |
1311 | pcrel = 1; | |
1312 | branch = 1; | |
1313 | info->insn_type = dis_branch; | |
1314 | break; | |
1315 | case 'A': | |
1316 | nbits = 8; | |
1317 | shift = 2; | |
1318 | immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8; | |
1319 | pcrel = 1; | |
1320 | /* FIXME: This can be lw or la. We assume it is lw. */ | |
1321 | info->insn_type = dis_dref; | |
1322 | info->data_size = 4; | |
1323 | break; | |
1324 | case 'B': | |
1325 | nbits = 5; | |
1326 | shift = 3; | |
1327 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1328 | pcrel = 1; | |
1329 | info->insn_type = dis_dref; | |
1330 | info->data_size = 8; | |
1331 | break; | |
1332 | case 'E': | |
1333 | nbits = 5; | |
1334 | shift = 2; | |
1335 | immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5; | |
1336 | pcrel = 1; | |
1337 | break; | |
1338 | default: | |
1339 | abort (); | |
1340 | } | |
1341 | ||
1342 | if (! use_extend) | |
1343 | { | |
1344 | if (signedp && immed >= (1 << (nbits - 1))) | |
1345 | immed -= 1 << nbits; | |
1346 | immed <<= shift; | |
1347 | if ((type == '<' || type == '>' || type == '[' || type == ']') | |
1348 | && immed == 0) | |
1349 | immed = 8; | |
1350 | } | |
1351 | else | |
1352 | { | |
1353 | if (extbits == 16) | |
1354 | immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0); | |
1355 | else if (extbits == 15) | |
1356 | immed |= ((extend & 0xf) << 11) | (extend & 0x7f0); | |
1357 | else | |
1358 | immed = ((extend >> 6) & 0x1f) | (extend & 0x20); | |
1359 | immed &= (1 << extbits) - 1; | |
1360 | if (! extu && immed >= (1 << (extbits - 1))) | |
1361 | immed -= 1 << extbits; | |
1362 | } | |
1363 | ||
1364 | if (! pcrel) | |
1365 | (*info->fprintf_func) (info->stream, "%d", immed); | |
1366 | else | |
1367 | { | |
1368 | bfd_vma baseaddr; | |
252b5132 RH |
1369 | |
1370 | if (branch) | |
1371 | { | |
1372 | immed *= 2; | |
1373 | baseaddr = memaddr + 2; | |
1374 | } | |
1375 | else if (use_extend) | |
1376 | baseaddr = memaddr - 2; | |
1377 | else | |
1378 | { | |
1379 | int status; | |
1380 | bfd_byte buffer[2]; | |
1381 | ||
1382 | baseaddr = memaddr; | |
1383 | ||
1384 | /* If this instruction is in the delay slot of a jr | |
1385 | instruction, the base address is the address of the | |
1386 | jr instruction. If it is in the delay slot of jalr | |
1387 | instruction, the base address is the address of the | |
1388 | jalr instruction. This test is unreliable: we have | |
1389 | no way of knowing whether the previous word is | |
1390 | instruction or data. */ | |
1391 | status = (*info->read_memory_func) (memaddr - 4, buffer, 2, | |
1392 | info); | |
1393 | if (status == 0 | |
1394 | && (((info->endian == BFD_ENDIAN_BIG | |
1395 | ? bfd_getb16 (buffer) | |
1396 | : bfd_getl16 (buffer)) | |
1397 | & 0xf800) == 0x1800)) | |
1398 | baseaddr = memaddr - 4; | |
1399 | else | |
1400 | { | |
1401 | status = (*info->read_memory_func) (memaddr - 2, buffer, | |
1402 | 2, info); | |
1403 | if (status == 0 | |
1404 | && (((info->endian == BFD_ENDIAN_BIG | |
1405 | ? bfd_getb16 (buffer) | |
1406 | : bfd_getl16 (buffer)) | |
1407 | & 0xf81f) == 0xe800)) | |
1408 | baseaddr = memaddr - 2; | |
1409 | } | |
1410 | } | |
9bb28706 CD |
1411 | info->target = (baseaddr & ~((1 << shift) - 1)) + immed; |
1412 | (*info->print_address_func) (info->target, info); | |
252b5132 RH |
1413 | } |
1414 | } | |
1415 | break; | |
1416 | ||
1417 | case 'a': | |
1418 | if (! use_extend) | |
1419 | extend = 0; | |
1420 | l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2); | |
9bb28706 CD |
1421 | info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l; |
1422 | (*info->print_address_func) (info->target, info); | |
252b5132 | 1423 | info->insn_type = dis_jsr; |
252b5132 RH |
1424 | info->branch_delay_insns = 1; |
1425 | break; | |
1426 | ||
1427 | case 'l': | |
1428 | case 'L': | |
1429 | { | |
1430 | int need_comma, amask, smask; | |
1431 | ||
1432 | need_comma = 0; | |
1433 | ||
1434 | l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6; | |
1435 | ||
1436 | amask = (l >> 3) & 7; | |
1437 | ||
1438 | if (amask > 0 && amask < 5) | |
1439 | { | |
640c0ccd | 1440 | (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]); |
252b5132 | 1441 | if (amask > 1) |
aa5f19f2 | 1442 | (*info->fprintf_func) (info->stream, "-%s", |
640c0ccd | 1443 | mips_gpr_names[amask + 3]); |
252b5132 RH |
1444 | need_comma = 1; |
1445 | } | |
1446 | ||
1447 | smask = (l >> 1) & 3; | |
1448 | if (smask == 3) | |
1449 | { | |
1450 | (*info->fprintf_func) (info->stream, "%s??", | |
1451 | need_comma ? "," : ""); | |
1452 | need_comma = 1; | |
1453 | } | |
1454 | else if (smask > 0) | |
1455 | { | |
aa5f19f2 | 1456 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1457 | need_comma ? "," : "", |
640c0ccd | 1458 | mips_gpr_names[16]); |
252b5132 | 1459 | if (smask > 1) |
aa5f19f2 | 1460 | (*info->fprintf_func) (info->stream, "-%s", |
640c0ccd | 1461 | mips_gpr_names[smask + 15]); |
252b5132 RH |
1462 | need_comma = 1; |
1463 | } | |
1464 | ||
1465 | if (l & 1) | |
1466 | { | |
aa5f19f2 | 1467 | (*info->fprintf_func) (info->stream, "%s%s", |
252b5132 | 1468 | need_comma ? "," : "", |
640c0ccd | 1469 | mips_gpr_names[31]); |
252b5132 RH |
1470 | need_comma = 1; |
1471 | } | |
1472 | ||
1473 | if (amask == 5 || amask == 6) | |
1474 | { | |
1475 | (*info->fprintf_func) (info->stream, "%s$f0", | |
1476 | need_comma ? "," : ""); | |
1477 | if (amask == 6) | |
1478 | (*info->fprintf_func) (info->stream, "-$f1"); | |
1479 | } | |
1480 | } | |
1481 | break; | |
1482 | ||
1483 | default: | |
aa5f19f2 NC |
1484 | /* xgettext:c-format */ |
1485 | (*info->fprintf_func) | |
1486 | (info->stream, | |
1487 | _("# internal disassembler error, unrecognised modifier (%c)"), | |
1488 | type); | |
252b5132 RH |
1489 | abort (); |
1490 | } | |
1491 | } | |
640c0ccd CD |
1492 | |
1493 | void | |
1494 | print_mips_disassembler_options (stream) | |
1495 | FILE *stream; | |
1496 | { | |
1497 | int i; | |
1498 | ||
1499 | fprintf (stream, _("\n\ | |
1500 | The following MIPS specific disassembler options are supported for use\n\ | |
1501 | with the -M switch (multiple options should be separated by commas):\n")); | |
1502 | ||
1503 | fprintf (stream, _("\n\ | |
1504 | gpr-names=ABI Print GPR names according to specified ABI.\n\ | |
1505 | Default: based on binary being disassembled.\n")); | |
1506 | ||
1507 | fprintf (stream, _("\n\ | |
1508 | fpr-names=ABI Print FPR names according to specified ABI.\n\ | |
1509 | Default: numeric.\n")); | |
1510 | ||
1511 | fprintf (stream, _("\n\ | |
1512 | cp0-names=ARCH Print CP0 register names according to\n\ | |
1513 | specified architecture.\n\ | |
1514 | Default: based on binary being disassembled.\n")); | |
1515 | ||
1516 | fprintf (stream, _("\n\ | |
1517 | reg-names=ABI Print GPR and FPR names according to\n\ | |
1518 | specified ABI.\n")); | |
1519 | ||
1520 | fprintf (stream, _("\n\ | |
1521 | reg-names=ARCH Print CP0 register names according to\n\ | |
1522 | specified architecture.\n")); | |
1523 | ||
1524 | fprintf (stream, _("\n\ | |
1525 | For the options above, the following values are supported for \"ABI\":\n\ | |
1526 | ")); | |
1527 | for (i = 0; mips_abi_choices[i].name != NULL; i++) | |
1528 | fprintf (stream, " %s", mips_abi_choices[i].name); | |
1529 | fprintf (stream, _("\n")); | |
1530 | ||
1531 | fprintf (stream, _("\n\ | |
1532 | For the options above, The following values are supported for \"ARCH\":\n\ | |
1533 | ")); | |
1534 | for (i = 0; mips_arch_choices[i].name != NULL; i++) | |
1535 | if (*mips_arch_choices[i].name != '\0') | |
1536 | fprintf (stream, " %s", mips_arch_choices[i].name); | |
1537 | fprintf (stream, _("\n")); | |
1538 | ||
1539 | fprintf (stream, _("\n")); | |
1540 | } |